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authorOlof Johansson <olof@lixom.net>2012-05-12 22:57:34 -0400
committerOlof Johansson <olof@lixom.net>2012-05-12 22:57:34 -0400
commit7af07ad902cce88ebbd2ce0e681d0c541e8f95fa (patch)
tree40a5aedb583c35d16505d96ea8996c413a747fe6 /drivers/pinctrl
parent7afeca1a30360c7b5cee94fc7ff8f350d582282a (diff)
parent08d98fe0e81cd9424ef2451ed13afe91a9a26f9f (diff)
Merge tag 'ux500-gpio-pins-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/pinctrl
ux500 GPIO and pinctrl changes for kernel 3.5 * tag 'ux500-gpio-pins-for-3.5' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ux500: switch MSP to using pinctrl for pins ARM: ux500: alter MSP registration to return a device pointer ARM: ux500: switch to using pinctrl for uart0 ARM: ux500: delete custom pin control system ARM: ux500: switch over to Nomadik pinctrl driver pinctrl: add sleep state definition pinctrl/nomadik: implement pin configuration pinctrl/nomadik: implement pin multiplexing pinctrl/nomadik: reuse GPIO debug function for pins pinctrl/nomadik: break out single GPIO debug function pinctrl/nomadik: basic Nomadik pinctrl interface pinctrl/nomadik: !CONFIG_OF build error gpio: move the Nomadik GPIO driver to pinctrl Context conflicts resolved in drivers/pinctrl/Kconfig and drivers/pinctrl/Makefile. Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig10
-rw-r--r--drivers/pinctrl/Makefile2
-rw-r--r--drivers/pinctrl/pinctrl-nomadik-db8500.c857
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c1780
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.h77
5 files changed, 2726 insertions, 0 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index a54a93112cba..cc01c758bbfc 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -64,6 +64,16 @@ config PINCTRL_IMX28
64 select PINCONF 64 select PINCONF
65 select PINCTRL_MXS 65 select PINCTRL_MXS
66 66
67config PINCTRL_NOMADIK
68 bool "Nomadik pin controller driver"
69 depends on ARCH_U8500
70 select PINMUX
71 select PINCONF
72
73config PINCTRL_DB8500
74 bool "DB8500 pin controller driver"
75 depends on PINCTRL_NOMADIK && ARCH_U8500
76
67config PINCTRL_PXA168 77config PINCTRL_PXA168
68 bool "PXA168 pin controller driver" 78 bool "PXA168 pin controller driver"
69 depends on ARCH_MMP 79 depends on ARCH_MMP
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index c9b0be56ff49..8e764ade929a 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,8 @@ obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
16obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o 16obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
17obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o 17obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
18obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o 18obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
19obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
20obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
19obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o 21obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
20obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o 22obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
21obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o 23obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c
new file mode 100644
index 000000000000..8b2022276f71
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c
@@ -0,0 +1,857 @@
1#include <linux/kernel.h>
2#include <linux/pinctrl/pinctrl.h>
3#include "pinctrl-nomadik.h"
4
5/* All the pins that can be used for GPIO and some other functions */
6#define _GPIO(offset) (offset)
7
8#define DB8500_PIN_AJ5 _GPIO(0)
9#define DB8500_PIN_AJ3 _GPIO(1)
10#define DB8500_PIN_AH4 _GPIO(2)
11#define DB8500_PIN_AH3 _GPIO(3)
12#define DB8500_PIN_AH6 _GPIO(4)
13#define DB8500_PIN_AG6 _GPIO(5)
14#define DB8500_PIN_AF6 _GPIO(6)
15#define DB8500_PIN_AG5 _GPIO(7)
16#define DB8500_PIN_AD5 _GPIO(8)
17#define DB8500_PIN_AE4 _GPIO(9)
18#define DB8500_PIN_AF5 _GPIO(10)
19#define DB8500_PIN_AG4 _GPIO(11)
20#define DB8500_PIN_AC4 _GPIO(12)
21#define DB8500_PIN_AF3 _GPIO(13)
22#define DB8500_PIN_AE3 _GPIO(14)
23#define DB8500_PIN_AC3 _GPIO(15)
24#define DB8500_PIN_AD3 _GPIO(16)
25#define DB8500_PIN_AD4 _GPIO(17)
26#define DB8500_PIN_AC2 _GPIO(18)
27#define DB8500_PIN_AC1 _GPIO(19)
28#define DB8500_PIN_AB4 _GPIO(20)
29#define DB8500_PIN_AB3 _GPIO(21)
30#define DB8500_PIN_AA3 _GPIO(22)
31#define DB8500_PIN_AA4 _GPIO(23)
32#define DB8500_PIN_AB2 _GPIO(24)
33#define DB8500_PIN_Y4 _GPIO(25)
34#define DB8500_PIN_Y2 _GPIO(26)
35#define DB8500_PIN_AA2 _GPIO(27)
36#define DB8500_PIN_AA1 _GPIO(28)
37#define DB8500_PIN_W2 _GPIO(29)
38#define DB8500_PIN_W3 _GPIO(30)
39#define DB8500_PIN_V3 _GPIO(31)
40#define DB8500_PIN_V2 _GPIO(32)
41#define DB8500_PIN_AF2 _GPIO(33)
42#define DB8500_PIN_AE1 _GPIO(34)
43#define DB8500_PIN_AE2 _GPIO(35)
44#define DB8500_PIN_AG2 _GPIO(36)
45/* Hole */
46#define DB8500_PIN_F3 _GPIO(64)
47#define DB8500_PIN_F1 _GPIO(65)
48#define DB8500_PIN_G3 _GPIO(66)
49#define DB8500_PIN_G2 _GPIO(67)
50#define DB8500_PIN_E1 _GPIO(68)
51#define DB8500_PIN_E2 _GPIO(69)
52#define DB8500_PIN_G5 _GPIO(70)
53#define DB8500_PIN_G4 _GPIO(71)
54#define DB8500_PIN_H4 _GPIO(72)
55#define DB8500_PIN_H3 _GPIO(73)
56#define DB8500_PIN_J3 _GPIO(74)
57#define DB8500_PIN_H2 _GPIO(75)
58#define DB8500_PIN_J2 _GPIO(76)
59#define DB8500_PIN_H1 _GPIO(77)
60#define DB8500_PIN_F4 _GPIO(78)
61#define DB8500_PIN_E3 _GPIO(79)
62#define DB8500_PIN_E4 _GPIO(80)
63#define DB8500_PIN_D2 _GPIO(81)
64#define DB8500_PIN_C1 _GPIO(82)
65#define DB8500_PIN_D3 _GPIO(83)
66#define DB8500_PIN_C2 _GPIO(84)
67#define DB8500_PIN_D5 _GPIO(85)
68#define DB8500_PIN_C6 _GPIO(86)
69#define DB8500_PIN_B3 _GPIO(87)
70#define DB8500_PIN_C4 _GPIO(88)
71#define DB8500_PIN_E6 _GPIO(89)
72#define DB8500_PIN_A3 _GPIO(90)
73#define DB8500_PIN_B6 _GPIO(91)
74#define DB8500_PIN_D6 _GPIO(92)
75#define DB8500_PIN_B7 _GPIO(93)
76#define DB8500_PIN_D7 _GPIO(94)
77#define DB8500_PIN_E8 _GPIO(95)
78#define DB8500_PIN_D8 _GPIO(96)
79#define DB8500_PIN_D9 _GPIO(97)
80/* Hole */
81#define DB8500_PIN_A5 _GPIO(128)
82#define DB8500_PIN_B4 _GPIO(129)
83#define DB8500_PIN_C8 _GPIO(130)
84#define DB8500_PIN_A12 _GPIO(131)
85#define DB8500_PIN_C10 _GPIO(132)
86#define DB8500_PIN_B10 _GPIO(133)
87#define DB8500_PIN_B9 _GPIO(134)
88#define DB8500_PIN_A9 _GPIO(135)
89#define DB8500_PIN_C7 _GPIO(136)
90#define DB8500_PIN_A7 _GPIO(137)
91#define DB8500_PIN_C5 _GPIO(138)
92#define DB8500_PIN_C9 _GPIO(139)
93#define DB8500_PIN_B11 _GPIO(140)
94#define DB8500_PIN_C12 _GPIO(141)
95#define DB8500_PIN_C11 _GPIO(142)
96#define DB8500_PIN_D12 _GPIO(143)
97#define DB8500_PIN_B13 _GPIO(144)
98#define DB8500_PIN_C13 _GPIO(145)
99#define DB8500_PIN_D13 _GPIO(146)
100#define DB8500_PIN_C15 _GPIO(147)
101#define DB8500_PIN_B16 _GPIO(148)
102#define DB8500_PIN_B14 _GPIO(149)
103#define DB8500_PIN_C14 _GPIO(150)
104#define DB8500_PIN_D17 _GPIO(151)
105#define DB8500_PIN_D16 _GPIO(152)
106#define DB8500_PIN_B17 _GPIO(153)
107#define DB8500_PIN_C16 _GPIO(154)
108#define DB8500_PIN_C19 _GPIO(155)
109#define DB8500_PIN_C17 _GPIO(156)
110#define DB8500_PIN_A18 _GPIO(157)
111#define DB8500_PIN_C18 _GPIO(158)
112#define DB8500_PIN_B19 _GPIO(159)
113#define DB8500_PIN_B20 _GPIO(160)
114#define DB8500_PIN_D21 _GPIO(161)
115#define DB8500_PIN_D20 _GPIO(162)
116#define DB8500_PIN_C20 _GPIO(163)
117#define DB8500_PIN_B21 _GPIO(164)
118#define DB8500_PIN_C21 _GPIO(165)
119#define DB8500_PIN_A22 _GPIO(166)
120#define DB8500_PIN_B24 _GPIO(167)
121#define DB8500_PIN_C22 _GPIO(168)
122#define DB8500_PIN_D22 _GPIO(169)
123#define DB8500_PIN_C23 _GPIO(170)
124#define DB8500_PIN_D23 _GPIO(171)
125/* Hole */
126#define DB8500_PIN_AJ27 _GPIO(192)
127#define DB8500_PIN_AH27 _GPIO(193)
128#define DB8500_PIN_AF27 _GPIO(194)
129#define DB8500_PIN_AG28 _GPIO(195)
130#define DB8500_PIN_AG26 _GPIO(196)
131#define DB8500_PIN_AH24 _GPIO(197)
132#define DB8500_PIN_AG25 _GPIO(198)
133#define DB8500_PIN_AH23 _GPIO(199)
134#define DB8500_PIN_AH26 _GPIO(200)
135#define DB8500_PIN_AF24 _GPIO(201)
136#define DB8500_PIN_AF25 _GPIO(202)
137#define DB8500_PIN_AE23 _GPIO(203)
138#define DB8500_PIN_AF23 _GPIO(204)
139#define DB8500_PIN_AG23 _GPIO(205)
140#define DB8500_PIN_AG24 _GPIO(206)
141#define DB8500_PIN_AJ23 _GPIO(207)
142#define DB8500_PIN_AH16 _GPIO(208)
143#define DB8500_PIN_AG15 _GPIO(209)
144#define DB8500_PIN_AJ15 _GPIO(210)
145#define DB8500_PIN_AG14 _GPIO(211)
146#define DB8500_PIN_AF13 _GPIO(212)
147#define DB8500_PIN_AG13 _GPIO(213)
148#define DB8500_PIN_AH15 _GPIO(214)
149#define DB8500_PIN_AH13 _GPIO(215)
150#define DB8500_PIN_AG12 _GPIO(216)
151#define DB8500_PIN_AH12 _GPIO(217)
152#define DB8500_PIN_AH11 _GPIO(218)
153#define DB8500_PIN_AG10 _GPIO(219)
154#define DB8500_PIN_AH10 _GPIO(220)
155#define DB8500_PIN_AJ11 _GPIO(221)
156#define DB8500_PIN_AJ9 _GPIO(222)
157#define DB8500_PIN_AH9 _GPIO(223)
158#define DB8500_PIN_AG9 _GPIO(224)
159#define DB8500_PIN_AG8 _GPIO(225)
160#define DB8500_PIN_AF8 _GPIO(226)
161#define DB8500_PIN_AH7 _GPIO(227)
162#define DB8500_PIN_AJ6 _GPIO(228)
163#define DB8500_PIN_AG7 _GPIO(229)
164#define DB8500_PIN_AF7 _GPIO(230)
165/* Hole */
166#define DB8500_PIN_AF28 _GPIO(256)
167#define DB8500_PIN_AE29 _GPIO(257)
168#define DB8500_PIN_AD29 _GPIO(258)
169#define DB8500_PIN_AC29 _GPIO(259)
170#define DB8500_PIN_AD28 _GPIO(260)
171#define DB8500_PIN_AD26 _GPIO(261)
172#define DB8500_PIN_AE26 _GPIO(262)
173#define DB8500_PIN_AG29 _GPIO(263)
174#define DB8500_PIN_AE27 _GPIO(264)
175#define DB8500_PIN_AD27 _GPIO(265)
176#define DB8500_PIN_AC28 _GPIO(266)
177#define DB8500_PIN_AC27 _GPIO(267)
178
179/*
180 * The names of the pins are denoted by GPIO number and ball name, even
181 * though they can be used for other things than GPIO, this is the first
182 * column in the table of the data sheet and often used on schematics and
183 * such.
184 */
185static const struct pinctrl_pin_desc nmk_db8500_pins[] = {
186 PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"),
187 PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"),
188 PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"),
189 PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"),
190 PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"),
191 PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"),
192 PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"),
193 PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"),
194 PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"),
195 PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"),
196 PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"),
197 PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"),
198 PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"),
199 PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"),
200 PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"),
201 PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"),
202 PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"),
203 PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"),
204 PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"),
205 PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"),
206 PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"),
207 PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"),
208 PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"),
209 PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"),
210 PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"),
211 PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"),
212 PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"),
213 PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"),
214 PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"),
215 PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"),
216 PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"),
217 PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"),
218 PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"),
219 PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"),
220 PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"),
221 PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"),
222 PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"),
223 /* Hole */
224 PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"),
225 PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"),
226 PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"),
227 PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"),
228 PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"),
229 PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"),
230 PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"),
231 PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"),
232 PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"),
233 PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"),
234 PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"),
235 PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"),
236 PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"),
237 PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"),
238 PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"),
239 PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"),
240 PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"),
241 PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"),
242 PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"),
243 PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"),
244 PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"),
245 PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"),
246 PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"),
247 PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"),
248 PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"),
249 PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"),
250 PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"),
251 PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"),
252 PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"),
253 PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"),
254 PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"),
255 PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"),
256 PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"),
257 PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"),
258 /* Hole */
259 PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"),
260 PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"),
261 PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"),
262 PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"),
263 PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"),
264 PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"),
265 PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"),
266 PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"),
267 PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"),
268 PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"),
269 PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"),
270 PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"),
271 PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"),
272 PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"),
273 PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"),
274 PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"),
275 PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"),
276 PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"),
277 PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"),
278 PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"),
279 PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"),
280 PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"),
281 PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"),
282 PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"),
283 PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"),
284 PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"),
285 PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"),
286 PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"),
287 PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"),
288 PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"),
289 PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"),
290 PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"),
291 PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"),
292 PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"),
293 PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"),
294 PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"),
295 PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"),
296 PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"),
297 PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"),
298 PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"),
299 PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"),
300 PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"),
301 PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"),
302 PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"),
303 /* Hole */
304 PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"),
305 PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"),
306 PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"),
307 PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"),
308 PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"),
309 PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"),
310 PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"),
311 PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"),
312 PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"),
313 PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"),
314 PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"),
315 PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"),
316 PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"),
317 PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"),
318 PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"),
319 PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"),
320 PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"),
321 PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"),
322 PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"),
323 PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"),
324 PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"),
325 PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"),
326 PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"),
327 PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"),
328 PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"),
329 PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"),
330 PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"),
331 PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"),
332 PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"),
333 PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"),
334 PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"),
335 PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"),
336 PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"),
337 PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"),
338 PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"),
339 PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"),
340 PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"),
341 PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"),
342 PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"),
343 /* Hole */
344 PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"),
345 PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"),
346 PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"),
347 PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"),
348 PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"),
349 PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"),
350 PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"),
351 PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"),
352 PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"),
353 PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"),
354 PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"),
355 PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"),
356};
357
358#define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \
359 .pin_base = b, .npins = c }
360
361/*
362 * This matches the 32-pin gpio chips registered by the GPIO portion. This
363 * cannot be const since we assign the struct gpio_chip * pointer at runtime.
364 */
365static struct pinctrl_gpio_range nmk_db8500_ranges[] = {
366 DB8500_GPIO_RANGE(0, 0, 32),
367 DB8500_GPIO_RANGE(1, 32, 5),
368 DB8500_GPIO_RANGE(2, 64, 32),
369 DB8500_GPIO_RANGE(3, 96, 2),
370 DB8500_GPIO_RANGE(4, 128, 32),
371 DB8500_GPIO_RANGE(5, 160, 12),
372 DB8500_GPIO_RANGE(6, 192, 32),
373 DB8500_GPIO_RANGE(7, 224, 7),
374 DB8500_GPIO_RANGE(8, 256, 12),
375};
376
377/*
378 * Read the pin group names like this:
379 * u0_a_1 = first groups of pins for uart0 on alt function a
380 * i2c2_b_2 = second group of pins for i2c2 on alt function b
381 *
382 * The groups are arranged as sets per altfunction column, so we can
383 * mux in one group at a time by selecting the same altfunction for them
384 * all. When functions require pins on different altfunctions, you need
385 * to combine several groups.
386 */
387
388/* Altfunction A column */
389static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
390 DB8500_PIN_AH4, DB8500_PIN_AH3 };
391static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
392static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
393/* Image processor I2C line, this is driven by image processor firmware */
394static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
395static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
396/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
397static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
398static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 };
399static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
400/* Basic pins of the MMC/SD card 0 interface */
401static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
402 DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
403 DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
404/* Often only 4 bits are used, then these are not needed (only used for MMC) */
405static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
406 DB8500_PIN_V3, DB8500_PIN_V2};
407static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 };
408/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
409static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
410static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 };
411/* LCD interface */
412static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
413 DB8500_PIN_G3, DB8500_PIN_G2 };
414static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 };
415static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 };
416static const unsigned lcd_d0_d7_a_1_pins[] = {
417 DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
418 DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 };
419/* D8 thru D11 often used as TVOUT lines */
420static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4,
421 DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 };
422static const unsigned lcd_d12_d23_a_1_pins[] = {
423 DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5,
424 DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6,
425 DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 };
426static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8,
427 DB8500_PIN_D8, DB8500_PIN_D9 };
428static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 };
429static const unsigned kp_a_2_pins[] = {
430 DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
431 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
432 DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
433 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
434/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
435static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4,
436 DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10,
437 DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7,
438 DB8500_PIN_C5 };
439static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
440 DB8500_PIN_C12, DB8500_PIN_C11 };
441static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13,
442 DB8500_PIN_C13, DB8500_PIN_D13 };
443static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 };
444/*
445 * Image processor GPIO pins are named "ipgpio" and have their own
446 * numberspace
447 */
448static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 };
449static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 };
450/* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */
451static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23,
452 DB8500_PIN_D23 };
453/*
454 * This MSP cannot switch RX and TX, SCK in a separate group since this
455 * seems to be optional.
456 */
457static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 };
458static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27,
459 DB8500_PIN_AG28, DB8500_PIN_AG26 };
460static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25,
461 DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25,
462 DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24,
463 DB8500_PIN_AJ23 };
464/* MC1 has only 4 data pins, designed for SD or SDIO exclusively */
465static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
466 DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,
467 DB8500_PIN_AH15 };
468static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
469 DB8500_PIN_AH12, DB8500_PIN_AH11 };
470static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10 };
471static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ11, DB8500_PIN_AJ9,
472 DB8500_PIN_AH9, DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 };
473static const unsigned clkout_a_1_pins[] = { DB8500_PIN_AH7, DB8500_PIN_AJ6 };
474static const unsigned clkout_a_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
475static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29,
476 DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26,
477 DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27,
478 DB8500_PIN_AC28, DB8500_PIN_AC27 };
479
480/* Altfunction B column */
481static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 };
482static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 };
483static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 };
484static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 };
485static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 };
486static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 };
487static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
488/* Just RX and TX for UART2 */
489static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 };
490static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 };
491static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 };
492static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 };
493static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4,
494 DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
495static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 };
496static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3,
497 DB8500_PIN_V3, DB8500_PIN_V2 };
498static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 };
499static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1,
500 DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2,
501 DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3,
502 DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1,
503 DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2,
504 DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 };
505static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
506 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
507 DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
508 DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8,
509 DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9,
510 DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5,
511 DB8500_PIN_C9, DB8500_PIN_B14 };
512/* This chip select pin can be "ps0" in alt B so have it separately */
513static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 };
514static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 };
515static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 };
516static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 };
517static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 };
518static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22,
519 DB8500_PIN_C23, DB8500_PIN_D23 };
520static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16,
521 DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17,
522 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20,
523 DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21,
524 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 };
525static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 };
526static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 };
527static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13,
528 DB8500_PIN_AG13, DB8500_PIN_AH15 };
529static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
530 DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10,
531 DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9,
532 DB8500_PIN_AG8 };
533static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 };
534static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 };
535static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 };
536
537/* Altfunction C column */
538static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3,
539 DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 };
540static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 };
541static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 };
542static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 };
543static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 };
544static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 };
545static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 };
546/* Optional 4-bit Memory Stick interface */
547static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1,
548 DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2,
549 DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 };
550static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 };
551static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 };
552static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 };
553static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1,
554 DB8500_PIN_AE2, DB8500_PIN_AG2 };
555static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 };
556static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 };
557static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 };
558static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 };
559static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 };
560static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4,
561 DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 };
562static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 };
563static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 };
564static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 };
565static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 };
566static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 };
567static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
568 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
569 DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8,
570 DB8500_PIN_D9 };
571static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 };
572static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11,
573 DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16,
574 DB8500_PIN_C23, DB8500_PIN_D23 };
575static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 };
576static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 };
577static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17,
578 DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 };
579static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 };
580static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 };
581static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21,
582 DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 };
583static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 };
584static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 };
585static const unsigned clkout_c_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12 };
586static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 };
587static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9,
588 DB8500_PIN_AG9, DB8500_PIN_AG8 };
589static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 };
590static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 };
591
592/* Other C1 column */
593static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3,
594 DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6,
595 DB8500_PIN_D6, DB8500_PIN_B7 };
596static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
597 DB8500_PIN_AH12, DB8500_PIN_AH11 };
598
599#define DB8500_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \
600 .npins = ARRAY_SIZE(a##_pins), .altsetting = b }
601
602static const struct nmk_pingroup nmk_db8500_groups[] = {
603 /* Altfunction A column */
604 DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
605 DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
606 DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
607 DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
608 DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
609 DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
610 DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
611 DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
612 DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
613 DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
614 DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
615 DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
616 DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
617 DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
618 DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
619 DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
620 DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
621 DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
622 DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
623 DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
624 DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
625 DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
626 DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
627 DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
628 DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
629 DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
630 DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
631 DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
632 DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
633 DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
634 DB8500_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
635 DB8500_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
636 DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
637 /* Altfunction B column */
638 DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B),
639 DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
640 DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
641 DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
642 DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
643 DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
644 DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
645 DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B),
646 DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B),
647 DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B),
648 DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B),
649 DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
650 DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B),
651 DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B),
652 DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
653 DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
654 DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
655 DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
656 DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
657 DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
658 DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
659 DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B),
660 DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B),
661 DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B),
662 DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
663 DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
664 DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
665 DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
666 DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
667 DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
668 DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
669 /* Altfunction C column */
670 DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C),
671 DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
672 DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
673 DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
674 DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
675 DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
676 DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C),
677 DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C),
678 DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C),
679 DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
680 DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C),
681 DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
682 DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
683 DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
684 DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
685 DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
686 DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
687 DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
688 DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C),
689 DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
690 DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
691 DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
692 DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
693 DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
694 DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
695 DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
696 DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
697 DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C),
698 DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C),
699 DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C),
700 DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C),
701 DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C),
702 DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C),
703 DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
704 DB8500_PIN_GROUP(clkout_c_1, NMK_GPIO_ALT_C),
705 DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
706 DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
707 DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C),
708 DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C),
709 /* Other alt C1 column, these are still configured as alt C */
710 DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
711 DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C),
712};
713
714/* We use this macro to define the groups applicable to a function */
715#define DB8500_FUNC_GROUPS(a, b...) \
716static const char * const a##_groups[] = { b };
717
718DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
719DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1");
720/*
721 * UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however
722 * only available on two pins in alternative function C
723 */
724DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1",
725 "u2rxtx_c_2", "u2rxtx_c_3");
726DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
727/*
728 * MSP0 can only be on a certain set of pins, but the TX/RX pins can be
729 * switched around by selecting the altfunction A or B. The SCK pin is
730 * only available on the altfunction B.
731 */
732DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1",
733 "msp0txrx_b_1", "msp0sck_b_1");
734DB8500_FUNC_GROUPS(mc0, "mc0_a_1");
735/* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */
736DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1");
737DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1");
738DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1",
739 "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1");
740DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
741DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
742DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1");
743DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1");
744DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1");
745/* The image processor has 8 GPIO pins that can be muxed out */
746DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
747 "ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1",
748 "ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1",
749 "ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2",
750 "ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2");
751/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */
752DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
753DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
754DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1");
755DB8500_FUNC_GROUPS(hsi, "hsir1_a_1", "hsit1_a_1");
756DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
757DB8500_FUNC_GROUPS(usb, "usb_a_1");
758DB8500_FUNC_GROUPS(trig, "trig_b_1");
759DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1");
760DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
761DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
762/*
763 * The modem UART can output its RX and TX pins in some different places,
764 * so select one of each.
765 */
766DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2",
767 "uartmodrx_c_1", "uartmod_tx_c_1");
768DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1");
769DB8500_FUNC_GROUPS(spi3, "spi3_b_1");
770/* Select between CS0 on alt B or PS1 on alt C */
771DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcleale_c_1", "smps1_c_1");
772DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1");
773DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
774DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
775DB8500_FUNC_GROUPS(spi1, "spi1_b_1");
776DB8500_FUNC_GROUPS(mc3, "mc3_b_1");
777DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1");
778DB8500_FUNC_GROUPS(slim0, "slim0_c_1");
779DB8500_FUNC_GROUPS(ms, "ms_c_1");
780DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1");
781DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2");
782DB8500_FUNC_GROUPS(mc5, "mc5_c_1");
783DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2");
784DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2");
785DB8500_FUNC_GROUPS(spi0, "spi0_c_1");
786DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1");
787
788#define FUNCTION(fname) \
789 { \
790 .name = #fname, \
791 .groups = fname##_groups, \
792 .ngroups = ARRAY_SIZE(fname##_groups), \
793 }
794
795static const struct nmk_function nmk_db8500_functions[] = {
796 FUNCTION(u0),
797 FUNCTION(u1),
798 FUNCTION(u2),
799 FUNCTION(ipi2c),
800 FUNCTION(msp0),
801 FUNCTION(mc0),
802 FUNCTION(msp1),
803 FUNCTION(lcdb),
804 FUNCTION(lcd),
805 FUNCTION(kp),
806 FUNCTION(mc2),
807 FUNCTION(ssp1),
808 FUNCTION(ssp0),
809 FUNCTION(i2c0),
810 FUNCTION(ipgpio),
811 FUNCTION(msp2),
812 FUNCTION(mc4),
813 FUNCTION(mc1),
814 FUNCTION(hsi),
815 FUNCTION(clkout),
816 FUNCTION(usb),
817 FUNCTION(trig),
818 FUNCTION(i2c4),
819 FUNCTION(i2c1),
820 FUNCTION(i2c2),
821 FUNCTION(uartmod),
822 FUNCTION(stmmod),
823 FUNCTION(spi3),
824 FUNCTION(sm),
825 FUNCTION(lcda),
826 FUNCTION(ddrtrig),
827 FUNCTION(pwl),
828 FUNCTION(spi1),
829 FUNCTION(mc3),
830 FUNCTION(ipjtag),
831 FUNCTION(slim0),
832 FUNCTION(ms),
833 FUNCTION(iptrigout),
834 FUNCTION(stmape),
835 FUNCTION(mc5),
836 FUNCTION(usbsim),
837 FUNCTION(i2c3),
838 FUNCTION(spi0),
839 FUNCTION(spi2),
840};
841
842static const struct nmk_pinctrl_soc_data nmk_db8500_soc = {
843 .gpio_ranges = nmk_db8500_ranges,
844 .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges),
845 .pins = nmk_db8500_pins,
846 .npins = ARRAY_SIZE(nmk_db8500_pins),
847 .functions = nmk_db8500_functions,
848 .nfunctions = ARRAY_SIZE(nmk_db8500_functions),
849 .groups = nmk_db8500_groups,
850 .ngroups = ARRAY_SIZE(nmk_db8500_groups),
851};
852
853void __devinit
854nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
855{
856 *soc = &nmk_db8500_soc;
857}
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
new file mode 100644
index 000000000000..b8e01c3eaa95
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -0,0 +1,1780 @@
1/*
2 * Generic GPIO driver for logic cells found in the Nomadik SoC
3 *
4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/gpio.h>
22#include <linux/spinlock.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/irqdomain.h>
26#include <linux/slab.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/pinctrl/pinconf.h>
30/* Since we request GPIOs from ourself */
31#include <linux/pinctrl/consumer.h>
32
33#include <asm/mach/irq.h>
34
35#include <plat/pincfg.h>
36#include <plat/gpio-nomadik.h>
37
38#include "pinctrl-nomadik.h"
39
40/*
41 * The GPIO module in the Nomadik family of Systems-on-Chip is an
42 * AMBA device, managing 32 pins and alternate functions. The logic block
43 * is currently used in the Nomadik and ux500.
44 *
45 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
46 */
47
48#define NMK_GPIO_PER_CHIP 32
49
50struct nmk_gpio_chip {
51 struct gpio_chip chip;
52 struct irq_domain *domain;
53 void __iomem *addr;
54 struct clk *clk;
55 unsigned int bank;
56 unsigned int parent_irq;
57 int secondary_parent_irq;
58 u32 (*get_secondary_status)(unsigned int bank);
59 void (*set_ioforce)(bool enable);
60 spinlock_t lock;
61 bool sleepmode;
62 /* Keep track of configured edges */
63 u32 edge_rising;
64 u32 edge_falling;
65 u32 real_wake;
66 u32 rwimsc;
67 u32 fwimsc;
68 u32 rimsc;
69 u32 fimsc;
70 u32 pull_up;
71 u32 lowemi;
72};
73
74struct nmk_pinctrl {
75 struct device *dev;
76 struct pinctrl_dev *pctl;
77 const struct nmk_pinctrl_soc_data *soc;
78};
79
80static struct nmk_gpio_chip *
81nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)];
82
83static DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
84
85#define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips)
86
87static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
88 unsigned offset, int gpio_mode)
89{
90 u32 bit = 1 << offset;
91 u32 afunc, bfunc;
92
93 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
94 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
95 if (gpio_mode & NMK_GPIO_ALT_A)
96 afunc |= bit;
97 if (gpio_mode & NMK_GPIO_ALT_B)
98 bfunc |= bit;
99 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
100 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
101}
102
103static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
104 unsigned offset, enum nmk_gpio_slpm mode)
105{
106 u32 bit = 1 << offset;
107 u32 slpm;
108
109 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
110 if (mode == NMK_GPIO_SLPM_NOCHANGE)
111 slpm |= bit;
112 else
113 slpm &= ~bit;
114 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
115}
116
117static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
118 unsigned offset, enum nmk_gpio_pull pull)
119{
120 u32 bit = 1 << offset;
121 u32 pdis;
122
123 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
124 if (pull == NMK_GPIO_PULL_NONE) {
125 pdis |= bit;
126 nmk_chip->pull_up &= ~bit;
127 } else {
128 pdis &= ~bit;
129 }
130
131 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
132
133 if (pull == NMK_GPIO_PULL_UP) {
134 nmk_chip->pull_up |= bit;
135 writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
136 } else if (pull == NMK_GPIO_PULL_DOWN) {
137 nmk_chip->pull_up &= ~bit;
138 writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
139 }
140}
141
142static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
143 unsigned offset, bool lowemi)
144{
145 u32 bit = BIT(offset);
146 bool enabled = nmk_chip->lowemi & bit;
147
148 if (lowemi == enabled)
149 return;
150
151 if (lowemi)
152 nmk_chip->lowemi |= bit;
153 else
154 nmk_chip->lowemi &= ~bit;
155
156 writel_relaxed(nmk_chip->lowemi,
157 nmk_chip->addr + NMK_GPIO_LOWEMI);
158}
159
160static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
161 unsigned offset)
162{
163 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
164}
165
166static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
167 unsigned offset, int val)
168{
169 if (val)
170 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS);
171 else
172 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC);
173}
174
175static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
176 unsigned offset, int val)
177{
178 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
179 __nmk_gpio_set_output(nmk_chip, offset, val);
180}
181
182static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
183 unsigned offset, int gpio_mode,
184 bool glitch)
185{
186 u32 rwimsc = nmk_chip->rwimsc;
187 u32 fwimsc = nmk_chip->fwimsc;
188
189 if (glitch && nmk_chip->set_ioforce) {
190 u32 bit = BIT(offset);
191
192 /* Prevent spurious wakeups */
193 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
194 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
195
196 nmk_chip->set_ioforce(true);
197 }
198
199 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
200
201 if (glitch && nmk_chip->set_ioforce) {
202 nmk_chip->set_ioforce(false);
203
204 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
205 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
206 }
207}
208
209static void
210nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
211{
212 u32 falling = nmk_chip->fimsc & BIT(offset);
213 u32 rising = nmk_chip->rimsc & BIT(offset);
214 int gpio = nmk_chip->chip.base + offset;
215 int irq = NOMADIK_GPIO_TO_IRQ(gpio);
216 struct irq_data *d = irq_get_irq_data(irq);
217
218 if (!rising && !falling)
219 return;
220
221 if (!d || !irqd_irq_disabled(d))
222 return;
223
224 if (rising) {
225 nmk_chip->rimsc &= ~BIT(offset);
226 writel_relaxed(nmk_chip->rimsc,
227 nmk_chip->addr + NMK_GPIO_RIMSC);
228 }
229
230 if (falling) {
231 nmk_chip->fimsc &= ~BIT(offset);
232 writel_relaxed(nmk_chip->fimsc,
233 nmk_chip->addr + NMK_GPIO_FIMSC);
234 }
235
236 dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio);
237}
238
239static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset,
240 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs)
241{
242 static const char *afnames[] = {
243 [NMK_GPIO_ALT_GPIO] = "GPIO",
244 [NMK_GPIO_ALT_A] = "A",
245 [NMK_GPIO_ALT_B] = "B",
246 [NMK_GPIO_ALT_C] = "C"
247 };
248 static const char *pullnames[] = {
249 [NMK_GPIO_PULL_NONE] = "none",
250 [NMK_GPIO_PULL_UP] = "up",
251 [NMK_GPIO_PULL_DOWN] = "down",
252 [3] /* illegal */ = "??"
253 };
254 static const char *slpmnames[] = {
255 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
256 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
257 };
258
259 int pin = PIN_NUM(cfg);
260 int pull = PIN_PULL(cfg);
261 int af = PIN_ALT(cfg);
262 int slpm = PIN_SLPM(cfg);
263 int output = PIN_DIR(cfg);
264 int val = PIN_VAL(cfg);
265 bool glitch = af == NMK_GPIO_ALT_C;
266
267 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n",
268 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm],
269 output ? "output " : "input",
270 output ? (val ? "high" : "low") : "");
271
272 if (sleep) {
273 int slpm_pull = PIN_SLPM_PULL(cfg);
274 int slpm_output = PIN_SLPM_DIR(cfg);
275 int slpm_val = PIN_SLPM_VAL(cfg);
276
277 af = NMK_GPIO_ALT_GPIO;
278
279 /*
280 * The SLPM_* values are normal values + 1 to allow zero to
281 * mean "same as normal".
282 */
283 if (slpm_pull)
284 pull = slpm_pull - 1;
285 if (slpm_output)
286 output = slpm_output - 1;
287 if (slpm_val)
288 val = slpm_val - 1;
289
290 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
291 pin,
292 slpm_pull ? pullnames[pull] : "same",
293 slpm_output ? (output ? "output" : "input") : "same",
294 slpm_val ? (val ? "high" : "low") : "same");
295 }
296
297 if (output)
298 __nmk_gpio_make_output(nmk_chip, offset, val);
299 else {
300 __nmk_gpio_make_input(nmk_chip, offset);
301 __nmk_gpio_set_pull(nmk_chip, offset, pull);
302 }
303
304 __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg));
305
306 /*
307 * If the pin is switching to altfunc, and there was an interrupt
308 * installed on it which has been lazy disabled, actually mask the
309 * interrupt to prevent spurious interrupts that would occur while the
310 * pin is under control of the peripheral. Only SKE does this.
311 */
312 if (af != NMK_GPIO_ALT_GPIO)
313 nmk_gpio_disable_lazy_irq(nmk_chip, offset);
314
315 /*
316 * If we've backed up the SLPM registers (glitch workaround), modify
317 * the backups since they will be restored.
318 */
319 if (slpmregs) {
320 if (slpm == NMK_GPIO_SLPM_NOCHANGE)
321 slpmregs[nmk_chip->bank] |= BIT(offset);
322 else
323 slpmregs[nmk_chip->bank] &= ~BIT(offset);
324 } else
325 __nmk_gpio_set_slpm(nmk_chip, offset, slpm);
326
327 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch);
328}
329
330/*
331 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
332 * - Save SLPM registers
333 * - Set SLPM=0 for the IOs you want to switch and others to 1
334 * - Configure the GPIO registers for the IOs that are being switched
335 * - Set IOFORCE=1
336 * - Modify the AFLSA/B registers for the IOs that are being switched
337 * - Set IOFORCE=0
338 * - Restore SLPM registers
339 * - Any spurious wake up event during switch sequence to be ignored and
340 * cleared
341 */
342static void nmk_gpio_glitch_slpm_init(unsigned int *slpm)
343{
344 int i;
345
346 for (i = 0; i < NUM_BANKS; i++) {
347 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
348 unsigned int temp = slpm[i];
349
350 if (!chip)
351 break;
352
353 clk_enable(chip->clk);
354
355 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
356 writel(temp, chip->addr + NMK_GPIO_SLPC);
357 }
358}
359
360static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
361{
362 int i;
363
364 for (i = 0; i < NUM_BANKS; i++) {
365 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
366
367 if (!chip)
368 break;
369
370 writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
371
372 clk_disable(chip->clk);
373 }
374}
375
376static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
377{
378 static unsigned int slpm[NUM_BANKS];
379 unsigned long flags;
380 bool glitch = false;
381 int ret = 0;
382 int i;
383
384 for (i = 0; i < num; i++) {
385 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) {
386 glitch = true;
387 break;
388 }
389 }
390
391 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
392
393 if (glitch) {
394 memset(slpm, 0xff, sizeof(slpm));
395
396 for (i = 0; i < num; i++) {
397 int pin = PIN_NUM(cfgs[i]);
398 int offset = pin % NMK_GPIO_PER_CHIP;
399
400 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C)
401 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset);
402 }
403
404 nmk_gpio_glitch_slpm_init(slpm);
405 }
406
407 for (i = 0; i < num; i++) {
408 struct nmk_gpio_chip *nmk_chip;
409 int pin = PIN_NUM(cfgs[i]);
410
411 nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP];
412 if (!nmk_chip) {
413 ret = -EINVAL;
414 break;
415 }
416
417 clk_enable(nmk_chip->clk);
418 spin_lock(&nmk_chip->lock);
419 __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP,
420 cfgs[i], sleep, glitch ? slpm : NULL);
421 spin_unlock(&nmk_chip->lock);
422 clk_disable(nmk_chip->clk);
423 }
424
425 if (glitch)
426 nmk_gpio_glitch_slpm_restore(slpm);
427
428 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
429
430 return ret;
431}
432
433/**
434 * nmk_config_pin - configure a pin's mux attributes
435 * @cfg: pin confguration
436 *
437 * Configures a pin's mode (alternate function or GPIO), its pull up status,
438 * and its sleep mode based on the specified configuration. The @cfg is
439 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These
440 * are constructed using, and can be further enhanced with, the macros in
441 * plat/pincfg.h.
442 *
443 * If a pin's mode is set to GPIO, it is configured as an input to avoid
444 * side-effects. The gpio can be manipulated later using standard GPIO API
445 * calls.
446 */
447int nmk_config_pin(pin_cfg_t cfg, bool sleep)
448{
449 return __nmk_config_pins(&cfg, 1, sleep);
450}
451EXPORT_SYMBOL(nmk_config_pin);
452
453/**
454 * nmk_config_pins - configure several pins at once
455 * @cfgs: array of pin configurations
456 * @num: number of elments in the array
457 *
458 * Configures several pins using nmk_config_pin(). Refer to that function for
459 * further information.
460 */
461int nmk_config_pins(pin_cfg_t *cfgs, int num)
462{
463 return __nmk_config_pins(cfgs, num, false);
464}
465EXPORT_SYMBOL(nmk_config_pins);
466
467int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num)
468{
469 return __nmk_config_pins(cfgs, num, true);
470}
471EXPORT_SYMBOL(nmk_config_pins_sleep);
472
473/**
474 * nmk_gpio_set_slpm() - configure the sleep mode of a pin
475 * @gpio: pin number
476 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE,
477 *
478 * This register is actually in the pinmux layer, not the GPIO block itself.
479 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP
480 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code).
481 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is
482 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers.
483 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit),
484 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers.
485 *
486 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO
487 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is
488 * entered) regardless of the altfunction selected. Also wake-up detection is
489 * ENABLED.
490 *
491 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains
492 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS
493 * (for altfunction GPIO) or respective on-chip peripherals (for other
494 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED.
495 *
496 * Note that enable_irq_wake() will automatically enable wakeup detection.
497 */
498int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
499{
500 struct nmk_gpio_chip *nmk_chip;
501 unsigned long flags;
502
503 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
504 if (!nmk_chip)
505 return -EINVAL;
506
507 clk_enable(nmk_chip->clk);
508 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
509 spin_lock(&nmk_chip->lock);
510
511 __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode);
512
513 spin_unlock(&nmk_chip->lock);
514 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
515 clk_disable(nmk_chip->clk);
516
517 return 0;
518}
519
520/**
521 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio
522 * @gpio: pin number
523 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE
524 *
525 * Enables/disables pull up/down on a specified pin. This only takes effect if
526 * the pin is configured as an input (either explicitly or by the alternate
527 * function).
528 *
529 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is
530 * configured as an input. Otherwise, due to the way the controller registers
531 * work, this function will change the value output on the pin.
532 */
533int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
534{
535 struct nmk_gpio_chip *nmk_chip;
536 unsigned long flags;
537
538 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
539 if (!nmk_chip)
540 return -EINVAL;
541
542 clk_enable(nmk_chip->clk);
543 spin_lock_irqsave(&nmk_chip->lock, flags);
544 __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull);
545 spin_unlock_irqrestore(&nmk_chip->lock, flags);
546 clk_disable(nmk_chip->clk);
547
548 return 0;
549}
550
551/* Mode functions */
552/**
553 * nmk_gpio_set_mode() - set the mux mode of a gpio pin
554 * @gpio: pin number
555 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A,
556 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C
557 *
558 * Sets the mode of the specified pin to one of the alternate functions or
559 * plain GPIO.
560 */
561int nmk_gpio_set_mode(int gpio, int gpio_mode)
562{
563 struct nmk_gpio_chip *nmk_chip;
564 unsigned long flags;
565
566 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
567 if (!nmk_chip)
568 return -EINVAL;
569
570 clk_enable(nmk_chip->clk);
571 spin_lock_irqsave(&nmk_chip->lock, flags);
572 __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode);
573 spin_unlock_irqrestore(&nmk_chip->lock, flags);
574 clk_disable(nmk_chip->clk);
575
576 return 0;
577}
578EXPORT_SYMBOL(nmk_gpio_set_mode);
579
580int nmk_gpio_get_mode(int gpio)
581{
582 struct nmk_gpio_chip *nmk_chip;
583 u32 afunc, bfunc, bit;
584
585 nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP];
586 if (!nmk_chip)
587 return -EINVAL;
588
589 bit = 1 << (gpio % NMK_GPIO_PER_CHIP);
590
591 clk_enable(nmk_chip->clk);
592
593 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
594 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
595
596 clk_disable(nmk_chip->clk);
597
598 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
599}
600EXPORT_SYMBOL(nmk_gpio_get_mode);
601
602
603/* IRQ functions */
604static inline int nmk_gpio_get_bitmask(int gpio)
605{
606 return 1 << (gpio % NMK_GPIO_PER_CHIP);
607}
608
609static void nmk_gpio_irq_ack(struct irq_data *d)
610{
611 struct nmk_gpio_chip *nmk_chip;
612
613 nmk_chip = irq_data_get_irq_chip_data(d);
614 if (!nmk_chip)
615 return;
616
617 clk_enable(nmk_chip->clk);
618 writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
619 clk_disable(nmk_chip->clk);
620}
621
622enum nmk_gpio_irq_type {
623 NORMAL,
624 WAKE,
625};
626
627static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
628 int gpio, enum nmk_gpio_irq_type which,
629 bool enable)
630{
631 u32 bitmask = nmk_gpio_get_bitmask(gpio);
632 u32 *rimscval;
633 u32 *fimscval;
634 u32 rimscreg;
635 u32 fimscreg;
636
637 if (which == NORMAL) {
638 rimscreg = NMK_GPIO_RIMSC;
639 fimscreg = NMK_GPIO_FIMSC;
640 rimscval = &nmk_chip->rimsc;
641 fimscval = &nmk_chip->fimsc;
642 } else {
643 rimscreg = NMK_GPIO_RWIMSC;
644 fimscreg = NMK_GPIO_FWIMSC;
645 rimscval = &nmk_chip->rwimsc;
646 fimscval = &nmk_chip->fwimsc;
647 }
648
649 /* we must individually set/clear the two edges */
650 if (nmk_chip->edge_rising & bitmask) {
651 if (enable)
652 *rimscval |= bitmask;
653 else
654 *rimscval &= ~bitmask;
655 writel(*rimscval, nmk_chip->addr + rimscreg);
656 }
657 if (nmk_chip->edge_falling & bitmask) {
658 if (enable)
659 *fimscval |= bitmask;
660 else
661 *fimscval &= ~bitmask;
662 writel(*fimscval, nmk_chip->addr + fimscreg);
663 }
664}
665
666static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
667 int gpio, bool on)
668{
669 /*
670 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is
671 * disabled, since setting SLPM to 1 increases power consumption, and
672 * wakeup is anyhow controlled by the RIMSC and FIMSC registers.
673 */
674 if (nmk_chip->sleepmode && on) {
675 __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base,
676 NMK_GPIO_SLPM_WAKEUP_ENABLE);
677 }
678
679 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
680}
681
682static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
683{
684 struct nmk_gpio_chip *nmk_chip;
685 unsigned long flags;
686 u32 bitmask;
687
688 nmk_chip = irq_data_get_irq_chip_data(d);
689 bitmask = nmk_gpio_get_bitmask(d->hwirq);
690 if (!nmk_chip)
691 return -EINVAL;
692
693 clk_enable(nmk_chip->clk);
694 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
695 spin_lock(&nmk_chip->lock);
696
697 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
698
699 if (!(nmk_chip->real_wake & bitmask))
700 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
701
702 spin_unlock(&nmk_chip->lock);
703 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
704 clk_disable(nmk_chip->clk);
705
706 return 0;
707}
708
709static void nmk_gpio_irq_mask(struct irq_data *d)
710{
711 nmk_gpio_irq_maskunmask(d, false);
712}
713
714static void nmk_gpio_irq_unmask(struct irq_data *d)
715{
716 nmk_gpio_irq_maskunmask(d, true);
717}
718
719static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
720{
721 struct nmk_gpio_chip *nmk_chip;
722 unsigned long flags;
723 u32 bitmask;
724
725 nmk_chip = irq_data_get_irq_chip_data(d);
726 if (!nmk_chip)
727 return -EINVAL;
728 bitmask = nmk_gpio_get_bitmask(d->hwirq);
729
730 clk_enable(nmk_chip->clk);
731 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
732 spin_lock(&nmk_chip->lock);
733
734 if (irqd_irq_disabled(d))
735 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
736
737 if (on)
738 nmk_chip->real_wake |= bitmask;
739 else
740 nmk_chip->real_wake &= ~bitmask;
741
742 spin_unlock(&nmk_chip->lock);
743 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
744 clk_disable(nmk_chip->clk);
745
746 return 0;
747}
748
749static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
750{
751 bool enabled = !irqd_irq_disabled(d);
752 bool wake = irqd_is_wakeup_set(d);
753 struct nmk_gpio_chip *nmk_chip;
754 unsigned long flags;
755 u32 bitmask;
756
757 nmk_chip = irq_data_get_irq_chip_data(d);
758 bitmask = nmk_gpio_get_bitmask(d->hwirq);
759 if (!nmk_chip)
760 return -EINVAL;
761 if (type & IRQ_TYPE_LEVEL_HIGH)
762 return -EINVAL;
763 if (type & IRQ_TYPE_LEVEL_LOW)
764 return -EINVAL;
765
766 clk_enable(nmk_chip->clk);
767 spin_lock_irqsave(&nmk_chip->lock, flags);
768
769 if (enabled)
770 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
771
772 if (enabled || wake)
773 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
774
775 nmk_chip->edge_rising &= ~bitmask;
776 if (type & IRQ_TYPE_EDGE_RISING)
777 nmk_chip->edge_rising |= bitmask;
778
779 nmk_chip->edge_falling &= ~bitmask;
780 if (type & IRQ_TYPE_EDGE_FALLING)
781 nmk_chip->edge_falling |= bitmask;
782
783 if (enabled)
784 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
785
786 if (enabled || wake)
787 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
788
789 spin_unlock_irqrestore(&nmk_chip->lock, flags);
790 clk_disable(nmk_chip->clk);
791
792 return 0;
793}
794
795static unsigned int nmk_gpio_irq_startup(struct irq_data *d)
796{
797 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
798
799 clk_enable(nmk_chip->clk);
800 nmk_gpio_irq_unmask(d);
801 return 0;
802}
803
804static void nmk_gpio_irq_shutdown(struct irq_data *d)
805{
806 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
807
808 nmk_gpio_irq_mask(d);
809 clk_disable(nmk_chip->clk);
810}
811
812static struct irq_chip nmk_gpio_irq_chip = {
813 .name = "Nomadik-GPIO",
814 .irq_ack = nmk_gpio_irq_ack,
815 .irq_mask = nmk_gpio_irq_mask,
816 .irq_unmask = nmk_gpio_irq_unmask,
817 .irq_set_type = nmk_gpio_irq_set_type,
818 .irq_set_wake = nmk_gpio_irq_set_wake,
819 .irq_startup = nmk_gpio_irq_startup,
820 .irq_shutdown = nmk_gpio_irq_shutdown,
821};
822
823static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
824 u32 status)
825{
826 struct nmk_gpio_chip *nmk_chip;
827 struct irq_chip *host_chip = irq_get_chip(irq);
828 unsigned int first_irq;
829
830 chained_irq_enter(host_chip, desc);
831
832 nmk_chip = irq_get_handler_data(irq);
833 first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
834 while (status) {
835 int bit = __ffs(status);
836
837 generic_handle_irq(first_irq + bit);
838 status &= ~BIT(bit);
839 }
840
841 chained_irq_exit(host_chip, desc);
842}
843
844static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
845{
846 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
847 u32 status;
848
849 clk_enable(nmk_chip->clk);
850 status = readl(nmk_chip->addr + NMK_GPIO_IS);
851 clk_disable(nmk_chip->clk);
852
853 __nmk_gpio_irq_handler(irq, desc, status);
854}
855
856static void nmk_gpio_secondary_irq_handler(unsigned int irq,
857 struct irq_desc *desc)
858{
859 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
860 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
861
862 __nmk_gpio_irq_handler(irq, desc, status);
863}
864
865static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
866{
867 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
868 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
869
870 if (nmk_chip->secondary_parent_irq >= 0) {
871 irq_set_chained_handler(nmk_chip->secondary_parent_irq,
872 nmk_gpio_secondary_irq_handler);
873 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
874 }
875
876 return 0;
877}
878
879/* I/O Functions */
880
881static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset)
882{
883 /*
884 * Map back to global GPIO space and request muxing, the direction
885 * parameter does not matter for this controller.
886 */
887 int gpio = chip->base + offset;
888
889 return pinctrl_request_gpio(gpio);
890}
891
892static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset)
893{
894 int gpio = chip->base + offset;
895
896 pinctrl_free_gpio(gpio);
897}
898
899static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
900{
901 struct nmk_gpio_chip *nmk_chip =
902 container_of(chip, struct nmk_gpio_chip, chip);
903
904 clk_enable(nmk_chip->clk);
905
906 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
907
908 clk_disable(nmk_chip->clk);
909
910 return 0;
911}
912
913static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
914{
915 struct nmk_gpio_chip *nmk_chip =
916 container_of(chip, struct nmk_gpio_chip, chip);
917 u32 bit = 1 << offset;
918 int value;
919
920 clk_enable(nmk_chip->clk);
921
922 value = (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
923
924 clk_disable(nmk_chip->clk);
925
926 return value;
927}
928
929static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
930 int val)
931{
932 struct nmk_gpio_chip *nmk_chip =
933 container_of(chip, struct nmk_gpio_chip, chip);
934
935 clk_enable(nmk_chip->clk);
936
937 __nmk_gpio_set_output(nmk_chip, offset, val);
938
939 clk_disable(nmk_chip->clk);
940}
941
942static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
943 int val)
944{
945 struct nmk_gpio_chip *nmk_chip =
946 container_of(chip, struct nmk_gpio_chip, chip);
947
948 clk_enable(nmk_chip->clk);
949
950 __nmk_gpio_make_output(nmk_chip, offset, val);
951
952 clk_disable(nmk_chip->clk);
953
954 return 0;
955}
956
957static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
958{
959 struct nmk_gpio_chip *nmk_chip =
960 container_of(chip, struct nmk_gpio_chip, chip);
961
962 return irq_find_mapping(nmk_chip->domain, offset);
963}
964
965#ifdef CONFIG_DEBUG_FS
966
967#include <linux/seq_file.h>
968
969static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip,
970 unsigned offset, unsigned gpio)
971{
972 const char *label = gpiochip_is_requested(chip, offset);
973 struct nmk_gpio_chip *nmk_chip =
974 container_of(chip, struct nmk_gpio_chip, chip);
975 int mode;
976 bool is_out;
977 bool pull;
978 u32 bit = 1 << offset;
979 const char *modes[] = {
980 [NMK_GPIO_ALT_GPIO] = "gpio",
981 [NMK_GPIO_ALT_A] = "altA",
982 [NMK_GPIO_ALT_B] = "altB",
983 [NMK_GPIO_ALT_C] = "altC",
984 };
985
986 clk_enable(nmk_chip->clk);
987 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit);
988 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit);
989 mode = nmk_gpio_get_mode(gpio);
990
991 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s",
992 gpio, label ?: "(none)",
993 is_out ? "out" : "in ",
994 chip->get
995 ? (chip->get(chip, offset) ? "hi" : "lo")
996 : "? ",
997 (mode < 0) ? "unknown" : modes[mode],
998 pull ? "pull" : "none");
999
1000 if (label && !is_out) {
1001 int irq = gpio_to_irq(gpio);
1002 struct irq_desc *desc = irq_to_desc(irq);
1003
1004 /* This races with request_irq(), set_irq_type(),
1005 * and set_irq_wake() ... but those are "rare".
1006 */
1007 if (irq >= 0 && desc->action) {
1008 char *trigger;
1009 u32 bitmask = nmk_gpio_get_bitmask(gpio);
1010
1011 if (nmk_chip->edge_rising & bitmask)
1012 trigger = "edge-rising";
1013 else if (nmk_chip->edge_falling & bitmask)
1014 trigger = "edge-falling";
1015 else
1016 trigger = "edge-undefined";
1017
1018 seq_printf(s, " irq-%d %s%s",
1019 irq, trigger,
1020 irqd_is_wakeup_set(&desc->irq_data)
1021 ? " wakeup" : "");
1022 }
1023 }
1024 clk_disable(nmk_chip->clk);
1025}
1026
1027static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1028{
1029 unsigned i;
1030 unsigned gpio = chip->base;
1031
1032 for (i = 0; i < chip->ngpio; i++, gpio++) {
1033 nmk_gpio_dbg_show_one(s, chip, i, gpio);
1034 seq_printf(s, "\n");
1035 }
1036}
1037
1038#else
1039static inline void nmk_gpio_dbg_show_one(struct seq_file *s,
1040 struct gpio_chip *chip,
1041 unsigned offset, unsigned gpio)
1042{
1043}
1044#define nmk_gpio_dbg_show NULL
1045#endif
1046
1047/* This structure is replicated for each GPIO block allocated at probe time */
1048static struct gpio_chip nmk_gpio_template = {
1049 .request = nmk_gpio_request,
1050 .free = nmk_gpio_free,
1051 .direction_input = nmk_gpio_make_input,
1052 .get = nmk_gpio_get_input,
1053 .direction_output = nmk_gpio_make_output,
1054 .set = nmk_gpio_set_output,
1055 .to_irq = nmk_gpio_to_irq,
1056 .dbg_show = nmk_gpio_dbg_show,
1057 .can_sleep = 0,
1058};
1059
1060void nmk_gpio_clocks_enable(void)
1061{
1062 int i;
1063
1064 for (i = 0; i < NUM_BANKS; i++) {
1065 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1066
1067 if (!chip)
1068 continue;
1069
1070 clk_enable(chip->clk);
1071 }
1072}
1073
1074void nmk_gpio_clocks_disable(void)
1075{
1076 int i;
1077
1078 for (i = 0; i < NUM_BANKS; i++) {
1079 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1080
1081 if (!chip)
1082 continue;
1083
1084 clk_disable(chip->clk);
1085 }
1086}
1087
1088/*
1089 * Called from the suspend/resume path to only keep the real wakeup interrupts
1090 * (those that have had set_irq_wake() called on them) as wakeup interrupts,
1091 * and not the rest of the interrupts which we needed to have as wakeups for
1092 * cpuidle.
1093 *
1094 * PM ops are not used since this needs to be done at the end, after all the
1095 * other drivers are done with their suspend callbacks.
1096 */
1097void nmk_gpio_wakeups_suspend(void)
1098{
1099 int i;
1100
1101 for (i = 0; i < NUM_BANKS; i++) {
1102 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1103
1104 if (!chip)
1105 break;
1106
1107 clk_enable(chip->clk);
1108
1109 writel(chip->rwimsc & chip->real_wake,
1110 chip->addr + NMK_GPIO_RWIMSC);
1111 writel(chip->fwimsc & chip->real_wake,
1112 chip->addr + NMK_GPIO_FWIMSC);
1113
1114 clk_disable(chip->clk);
1115 }
1116}
1117
1118void nmk_gpio_wakeups_resume(void)
1119{
1120 int i;
1121
1122 for (i = 0; i < NUM_BANKS; i++) {
1123 struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
1124
1125 if (!chip)
1126 break;
1127
1128 clk_enable(chip->clk);
1129
1130 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC);
1131 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC);
1132
1133 clk_disable(chip->clk);
1134 }
1135}
1136
1137/*
1138 * Read the pull up/pull down status.
1139 * A bit set in 'pull_up' means that pull up
1140 * is selected if pull is enabled in PDIS register.
1141 * Note: only pull up/down set via this driver can
1142 * be detected due to HW limitations.
1143 */
1144void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up)
1145{
1146 if (gpio_bank < NUM_BANKS) {
1147 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank];
1148
1149 if (!chip)
1150 return;
1151
1152 *pull_up = chip->pull_up;
1153 }
1154}
1155
1156int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq,
1157 irq_hw_number_t hwirq)
1158{
1159 struct nmk_gpio_chip *nmk_chip = d->host_data;
1160
1161 if (!nmk_chip)
1162 return -EINVAL;
1163
1164 irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq);
1165 set_irq_flags(irq, IRQF_VALID);
1166 irq_set_chip_data(irq, nmk_chip);
1167 irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING);
1168
1169 return 0;
1170}
1171
1172const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1173 .map = nmk_gpio_irq_map,
1174 .xlate = irq_domain_xlate_twocell,
1175};
1176
1177static int __devinit nmk_gpio_probe(struct platform_device *dev)
1178{
1179 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data;
1180 struct device_node *np = dev->dev.of_node;
1181 struct nmk_gpio_chip *nmk_chip;
1182 struct gpio_chip *chip;
1183 struct resource *res;
1184 struct clk *clk;
1185 int secondary_irq;
1186 void __iomem *base;
1187 int irq;
1188 int ret;
1189
1190 if (!pdata && !np) {
1191 dev_err(&dev->dev, "No platform data or device tree found\n");
1192 return -ENODEV;
1193 }
1194
1195 if (np) {
1196 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
1197 if (!pdata)
1198 return -ENOMEM;
1199
1200 if (of_get_property(np, "supports-sleepmode", NULL))
1201 pdata->supports_sleepmode = true;
1202
1203 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1204 dev_err(&dev->dev, "gpio-bank property not found\n");
1205 ret = -EINVAL;
1206 goto out;
1207 }
1208
1209 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1210 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1211 }
1212
1213 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1214 if (!res) {
1215 ret = -ENOENT;
1216 goto out;
1217 }
1218
1219 irq = platform_get_irq(dev, 0);
1220 if (irq < 0) {
1221 ret = irq;
1222 goto out;
1223 }
1224
1225 secondary_irq = platform_get_irq(dev, 1);
1226 if (secondary_irq >= 0 && !pdata->get_secondary_status) {
1227 ret = -EINVAL;
1228 goto out;
1229 }
1230
1231 if (request_mem_region(res->start, resource_size(res),
1232 dev_name(&dev->dev)) == NULL) {
1233 ret = -EBUSY;
1234 goto out;
1235 }
1236
1237 base = ioremap(res->start, resource_size(res));
1238 if (!base) {
1239 ret = -ENOMEM;
1240 goto out_release;
1241 }
1242
1243 clk = clk_get(&dev->dev, NULL);
1244 if (IS_ERR(clk)) {
1245 ret = PTR_ERR(clk);
1246 goto out_unmap;
1247 }
1248
1249 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
1250 if (!nmk_chip) {
1251 ret = -ENOMEM;
1252 goto out_clk;
1253 }
1254
1255 /*
1256 * The virt address in nmk_chip->addr is in the nomadik register space,
1257 * so we can simply convert the resource address, without remapping
1258 */
1259 nmk_chip->bank = dev->id;
1260 nmk_chip->clk = clk;
1261 nmk_chip->addr = base;
1262 nmk_chip->chip = nmk_gpio_template;
1263 nmk_chip->parent_irq = irq;
1264 nmk_chip->secondary_parent_irq = secondary_irq;
1265 nmk_chip->get_secondary_status = pdata->get_secondary_status;
1266 nmk_chip->set_ioforce = pdata->set_ioforce;
1267 nmk_chip->sleepmode = pdata->supports_sleepmode;
1268 spin_lock_init(&nmk_chip->lock);
1269
1270 chip = &nmk_chip->chip;
1271 chip->base = pdata->first_gpio;
1272 chip->ngpio = pdata->num_gpio;
1273 chip->label = pdata->name ?: dev_name(&dev->dev);
1274 chip->dev = &dev->dev;
1275 chip->owner = THIS_MODULE;
1276
1277 clk_enable(nmk_chip->clk);
1278 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1279 clk_disable(nmk_chip->clk);
1280
1281#ifdef CONFIG_OF_GPIO
1282 chip->of_node = np;
1283#endif
1284
1285 ret = gpiochip_add(&nmk_chip->chip);
1286 if (ret)
1287 goto out_free;
1288
1289 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1290
1291 nmk_gpio_chips[nmk_chip->bank] = nmk_chip;
1292
1293 platform_set_drvdata(dev, nmk_chip);
1294
1295 nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP,
1296 NOMADIK_GPIO_TO_IRQ(pdata->first_gpio),
1297 0, &nmk_gpio_irq_simple_ops, nmk_chip);
1298 if (!nmk_chip->domain) {
1299 pr_err("%s: Failed to create irqdomain\n", np->full_name);
1300 ret = -ENOSYS;
1301 goto out_free;
1302 }
1303
1304 nmk_gpio_init_irq(nmk_chip);
1305
1306 dev_info(&dev->dev, "at address %p\n", nmk_chip->addr);
1307
1308 return 0;
1309
1310out_free:
1311 kfree(nmk_chip);
1312out_clk:
1313 clk_disable(clk);
1314 clk_put(clk);
1315out_unmap:
1316 iounmap(base);
1317out_release:
1318 release_mem_region(res->start, resource_size(res));
1319out:
1320 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
1321 pdata->first_gpio, pdata->first_gpio+31);
1322 if (np)
1323 kfree(pdata);
1324
1325 return ret;
1326}
1327
1328static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
1329{
1330 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1331
1332 return npct->soc->ngroups;
1333}
1334
1335static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
1336 unsigned selector)
1337{
1338 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1339
1340 return npct->soc->groups[selector].name;
1341}
1342
1343static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
1344 const unsigned **pins,
1345 unsigned *num_pins)
1346{
1347 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1348
1349 *pins = npct->soc->groups[selector].pins;
1350 *num_pins = npct->soc->groups[selector].npins;
1351 return 0;
1352}
1353
1354static struct pinctrl_gpio_range *
1355nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset)
1356{
1357 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1358 int i;
1359
1360 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1361 struct pinctrl_gpio_range *range;
1362
1363 range = &npct->soc->gpio_ranges[i];
1364 if (offset >= range->pin_base &&
1365 offset <= (range->pin_base + range->npins - 1))
1366 return range;
1367 }
1368 return NULL;
1369}
1370
1371static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
1372 unsigned offset)
1373{
1374 struct pinctrl_gpio_range *range;
1375 struct gpio_chip *chip;
1376
1377 range = nmk_match_gpio_range(pctldev, offset);
1378 if (!range || !range->gc) {
1379 seq_printf(s, "invalid pin offset");
1380 return;
1381 }
1382 chip = range->gc;
1383 nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset);
1384}
1385
1386static struct pinctrl_ops nmk_pinctrl_ops = {
1387 .get_groups_count = nmk_get_groups_cnt,
1388 .get_group_name = nmk_get_group_name,
1389 .get_group_pins = nmk_get_group_pins,
1390 .pin_dbg_show = nmk_pin_dbg_show,
1391};
1392
1393static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
1394{
1395 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1396
1397 return npct->soc->nfunctions;
1398}
1399
1400static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
1401 unsigned function)
1402{
1403 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1404
1405 return npct->soc->functions[function].name;
1406}
1407
1408static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
1409 unsigned function,
1410 const char * const **groups,
1411 unsigned * const num_groups)
1412{
1413 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1414
1415 *groups = npct->soc->functions[function].groups;
1416 *num_groups = npct->soc->functions[function].ngroups;
1417
1418 return 0;
1419}
1420
1421static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function,
1422 unsigned group)
1423{
1424 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1425 const struct nmk_pingroup *g;
1426 static unsigned int slpm[NUM_BANKS];
1427 unsigned long flags;
1428 bool glitch;
1429 int ret = -EINVAL;
1430 int i;
1431
1432 g = &npct->soc->groups[group];
1433
1434 if (g->altsetting < 0)
1435 return -EINVAL;
1436
1437 dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins);
1438
1439 /* Handle this special glitch on altfunction C */
1440 glitch = (g->altsetting == NMK_GPIO_ALT_C);
1441
1442 if (glitch) {
1443 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
1444
1445 /* Initially don't put any pins to sleep when switching */
1446 memset(slpm, 0xff, sizeof(slpm));
1447
1448 /*
1449 * Then mask the pins that need to be sleeping now when we're
1450 * switching to the ALT C function.
1451 */
1452 for (i = 0; i < g->npins; i++)
1453 slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]);
1454 nmk_gpio_glitch_slpm_init(slpm);
1455 }
1456
1457 for (i = 0; i < g->npins; i++) {
1458 struct pinctrl_gpio_range *range;
1459 struct nmk_gpio_chip *nmk_chip;
1460 struct gpio_chip *chip;
1461 unsigned bit;
1462
1463 range = nmk_match_gpio_range(pctldev, g->pins[i]);
1464 if (!range) {
1465 dev_err(npct->dev,
1466 "invalid pin offset %d in group %s at index %d\n",
1467 g->pins[i], g->name, i);
1468 goto out_glitch;
1469 }
1470 if (!range->gc) {
1471 dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n",
1472 g->pins[i], g->name, i);
1473 goto out_glitch;
1474 }
1475 chip = range->gc;
1476 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1477 dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting);
1478
1479 clk_enable(nmk_chip->clk);
1480 bit = g->pins[i] % NMK_GPIO_PER_CHIP;
1481 /*
1482 * If the pin is switching to altfunc, and there was an
1483 * interrupt installed on it which has been lazy disabled,
1484 * actually mask the interrupt to prevent spurious interrupts
1485 * that would occur while the pin is under control of the
1486 * peripheral. Only SKE does this.
1487 */
1488 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1489
1490 __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch);
1491 clk_disable(nmk_chip->clk);
1492 }
1493
1494 /* When all pins are successfully reconfigured we get here */
1495 ret = 0;
1496
1497out_glitch:
1498 if (glitch) {
1499 nmk_gpio_glitch_slpm_restore(slpm);
1500 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
1501 }
1502
1503 return ret;
1504}
1505
1506static void nmk_pmx_disable(struct pinctrl_dev *pctldev,
1507 unsigned function, unsigned group)
1508{
1509 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1510 const struct nmk_pingroup *g;
1511
1512 g = &npct->soc->groups[group];
1513
1514 if (g->altsetting < 0)
1515 return;
1516
1517 /* Poke out the mux, set the pin to some default state? */
1518 dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins);
1519}
1520
1521int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1522 struct pinctrl_gpio_range *range,
1523 unsigned offset)
1524{
1525 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1526 struct nmk_gpio_chip *nmk_chip;
1527 struct gpio_chip *chip;
1528 unsigned bit;
1529
1530 if (!range) {
1531 dev_err(npct->dev, "invalid range\n");
1532 return -EINVAL;
1533 }
1534 if (!range->gc) {
1535 dev_err(npct->dev, "missing GPIO chip in range\n");
1536 return -EINVAL;
1537 }
1538 chip = range->gc;
1539 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1540
1541 dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset);
1542
1543 clk_enable(nmk_chip->clk);
1544 bit = offset % NMK_GPIO_PER_CHIP;
1545 /* There is no glitch when converting any pin to GPIO */
1546 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1547 clk_disable(nmk_chip->clk);
1548
1549 return 0;
1550}
1551
1552void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1553 struct pinctrl_gpio_range *range,
1554 unsigned offset)
1555{
1556 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1557
1558 dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset);
1559 /* Set the pin to some default state, GPIO is usually default */
1560}
1561
1562static struct pinmux_ops nmk_pinmux_ops = {
1563 .get_functions_count = nmk_pmx_get_funcs_cnt,
1564 .get_function_name = nmk_pmx_get_func_name,
1565 .get_function_groups = nmk_pmx_get_func_groups,
1566 .enable = nmk_pmx_enable,
1567 .disable = nmk_pmx_disable,
1568 .gpio_request_enable = nmk_gpio_request_enable,
1569 .gpio_disable_free = nmk_gpio_disable_free,
1570};
1571
1572int nmk_pin_config_get(struct pinctrl_dev *pctldev,
1573 unsigned pin,
1574 unsigned long *config)
1575{
1576 /* Not implemented */
1577 return -EINVAL;
1578}
1579
1580int nmk_pin_config_set(struct pinctrl_dev *pctldev,
1581 unsigned pin,
1582 unsigned long config)
1583{
1584 static const char *pullnames[] = {
1585 [NMK_GPIO_PULL_NONE] = "none",
1586 [NMK_GPIO_PULL_UP] = "up",
1587 [NMK_GPIO_PULL_DOWN] = "down",
1588 [3] /* illegal */ = "??"
1589 };
1590 static const char *slpmnames[] = {
1591 [NMK_GPIO_SLPM_INPUT] = "input/wakeup",
1592 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup",
1593 };
1594 struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1595 struct nmk_gpio_chip *nmk_chip;
1596 struct pinctrl_gpio_range *range;
1597 struct gpio_chip *chip;
1598 unsigned bit;
1599
1600 /*
1601 * The pin config contains pin number and altfunction fields, here
1602 * we just ignore that part. It's being handled by the framework and
1603 * pinmux callback respectively.
1604 */
1605 pin_cfg_t cfg = (pin_cfg_t) config;
1606 int pull = PIN_PULL(cfg);
1607 int slpm = PIN_SLPM(cfg);
1608 int output = PIN_DIR(cfg);
1609 int val = PIN_VAL(cfg);
1610 bool lowemi = PIN_LOWEMI(cfg);
1611 bool gpiomode = PIN_GPIOMODE(cfg);
1612 bool sleep = PIN_SLEEPMODE(cfg);
1613
1614 range = nmk_match_gpio_range(pctldev, pin);
1615 if (!range) {
1616 dev_err(npct->dev, "invalid pin offset %d\n", pin);
1617 return -EINVAL;
1618 }
1619 if (!range->gc) {
1620 dev_err(npct->dev, "GPIO chip missing in range for pin %d\n",
1621 pin);
1622 return -EINVAL;
1623 }
1624 chip = range->gc;
1625 nmk_chip = container_of(chip, struct nmk_gpio_chip, chip);
1626
1627 if (sleep) {
1628 int slpm_pull = PIN_SLPM_PULL(cfg);
1629 int slpm_output = PIN_SLPM_DIR(cfg);
1630 int slpm_val = PIN_SLPM_VAL(cfg);
1631
1632 /* All pins go into GPIO mode at sleep */
1633 gpiomode = true;
1634
1635 /*
1636 * The SLPM_* values are normal values + 1 to allow zero to
1637 * mean "same as normal".
1638 */
1639 if (slpm_pull)
1640 pull = slpm_pull - 1;
1641 if (slpm_output)
1642 output = slpm_output - 1;
1643 if (slpm_val)
1644 val = slpm_val - 1;
1645
1646 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n",
1647 pin,
1648 slpm_pull ? pullnames[pull] : "same",
1649 slpm_output ? (output ? "output" : "input") : "same",
1650 slpm_val ? (val ? "high" : "low") : "same");
1651 }
1652
1653 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1654 pin, cfg, pullnames[pull], slpmnames[slpm],
1655 output ? "output " : "input",
1656 output ? (val ? "high" : "low") : "",
1657 lowemi ? "on" : "off" );
1658
1659 clk_enable(nmk_chip->clk);
1660 bit = pin % NMK_GPIO_PER_CHIP;
1661 if (gpiomode)
1662 /* No glitch when going to GPIO mode */
1663 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1664 if (output)
1665 __nmk_gpio_make_output(nmk_chip, bit, val);
1666 else {
1667 __nmk_gpio_make_input(nmk_chip, bit);
1668 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1669 }
1670 /* TODO: isn't this only applicable on output pins? */
1671 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1672
1673 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1674 clk_disable(nmk_chip->clk);
1675 return 0;
1676}
1677
1678static struct pinconf_ops nmk_pinconf_ops = {
1679 .pin_config_get = nmk_pin_config_get,
1680 .pin_config_set = nmk_pin_config_set,
1681};
1682
1683static struct pinctrl_desc nmk_pinctrl_desc = {
1684 .name = "pinctrl-nomadik",
1685 .pctlops = &nmk_pinctrl_ops,
1686 .pmxops = &nmk_pinmux_ops,
1687 .confops = &nmk_pinconf_ops,
1688 .owner = THIS_MODULE,
1689};
1690
1691static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
1692{
1693 const struct platform_device_id *platid = platform_get_device_id(pdev);
1694 struct nmk_pinctrl *npct;
1695 int i;
1696
1697 npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1698 if (!npct)
1699 return -ENOMEM;
1700
1701 /* Poke in other ASIC variants here */
1702 if (platid->driver_data == PINCTRL_NMK_DB8500)
1703 nmk_pinctrl_db8500_init(&npct->soc);
1704
1705 /*
1706 * We need all the GPIO drivers to probe FIRST, or we will not be able
1707 * to obtain references to the struct gpio_chip * for them, and we
1708 * need this to proceed.
1709 */
1710 for (i = 0; i < npct->soc->gpio_num_ranges; i++) {
1711 if (!nmk_gpio_chips[i]) {
1712 dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i);
1713 devm_kfree(&pdev->dev, npct);
1714 return -EPROBE_DEFER;
1715 }
1716 npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip;
1717 }
1718
1719 nmk_pinctrl_desc.pins = npct->soc->pins;
1720 nmk_pinctrl_desc.npins = npct->soc->npins;
1721 npct->dev = &pdev->dev;
1722 npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct);
1723 if (!npct->pctl) {
1724 dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1725 return -EINVAL;
1726 }
1727
1728 /* We will handle a range of GPIO pins */
1729 for (i = 0; i < npct->soc->gpio_num_ranges; i++)
1730 pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]);
1731
1732 platform_set_drvdata(pdev, npct);
1733 dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1734
1735 return 0;
1736}
1737
1738static const struct of_device_id nmk_gpio_match[] = {
1739 { .compatible = "st,nomadik-gpio", },
1740 {}
1741};
1742
1743static struct platform_driver nmk_gpio_driver = {
1744 .driver = {
1745 .owner = THIS_MODULE,
1746 .name = "gpio",
1747 .of_match_table = nmk_gpio_match,
1748 },
1749 .probe = nmk_gpio_probe,
1750};
1751
1752static const struct platform_device_id nmk_pinctrl_id[] = {
1753 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1754 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1755};
1756
1757static struct platform_driver nmk_pinctrl_driver = {
1758 .driver = {
1759 .owner = THIS_MODULE,
1760 .name = "pinctrl-nomadik",
1761 },
1762 .probe = nmk_pinctrl_probe,
1763 .id_table = nmk_pinctrl_id,
1764};
1765
1766static int __init nmk_gpio_init(void)
1767{
1768 int ret;
1769
1770 ret = platform_driver_register(&nmk_gpio_driver);
1771 if (ret)
1772 return ret;
1773 return platform_driver_register(&nmk_pinctrl_driver);
1774}
1775
1776core_initcall(nmk_gpio_init);
1777
1778MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
1779MODULE_DESCRIPTION("Nomadik GPIO Driver");
1780MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
new file mode 100644
index 000000000000..bc91aed7185d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -0,0 +1,77 @@
1#ifndef PINCTRL_PINCTRL_NOMADIK_H
2#define PINCTRL_PINCTRL_NOMADIK_H
3
4#include <plat/gpio-nomadik.h>
5
6/* Package definitions */
7#define PINCTRL_NMK_STN8815 0
8#define PINCTRL_NMK_DB8500 1
9
10/**
11 * struct nmk_function - Nomadik pinctrl mux function
12 * @name: The name of the function, exported to pinctrl core.
13 * @groups: An array of pin groups that may select this function.
14 * @ngroups: The number of entries in @groups.
15 */
16struct nmk_function {
17 const char *name;
18 const char * const *groups;
19 unsigned ngroups;
20};
21
22/**
23 * struct nmk_pingroup - describes a Nomadik pin group
24 * @name: the name of this specific pin group
25 * @pins: an array of discrete physical pins used in this group, taken
26 * from the driver-local pin enumeration space
27 * @num_pins: the number of pins in this group array, i.e. the number of
28 * elements in .pins so we can iterate over that array
29 * @altsetting: the altsetting to apply to all pins in this group to
30 * configure them to be used by a function
31 */
32struct nmk_pingroup {
33 const char *name;
34 const unsigned int *pins;
35 const unsigned npins;
36 int altsetting;
37};
38
39/**
40 * struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
41 * @gpio_ranges: An array of GPIO ranges for this SoC
42 * @gpio_num_ranges: The number of GPIO ranges for this SoC
43 * @pins: An array describing all pins the pin controller affects.
44 * All pins which are also GPIOs must be listed first within the
45 * array, and be numbered identically to the GPIO controller's
46 * numbering.
47 * @npins: The number of entries in @pins.
48 * @functions: The functions supported on this SoC.
49 * @nfunction: The number of entries in @functions.
50 * @groups: An array describing all pin groups the pin SoC supports.
51 * @ngroups: The number of entries in @groups.
52 */
53struct nmk_pinctrl_soc_data {
54 struct pinctrl_gpio_range *gpio_ranges;
55 unsigned gpio_num_ranges;
56 const struct pinctrl_pin_desc *pins;
57 unsigned npins;
58 const struct nmk_function *functions;
59 unsigned nfunctions;
60 const struct nmk_pingroup *groups;
61 unsigned ngroups;
62};
63
64#ifdef CONFIG_PINCTRL_DB8500
65
66void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
67
68#else
69
70static inline void
71nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
72{
73}
74
75#endif
76
77#endif /* PINCTRL_PINCTRL_NOMADIK_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 22:08:40 -0500