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authorLinus Torvalds <torvalds@linux-foundation.org>2013-05-04 15:32:41 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-05-04 15:32:41 -0400
commit22b154365fbc096a46d936ec1f462ef8b9bd1f05 (patch)
tree69459adc5424e1efc3c74ae3e96bfa44e00672c6 /drivers/pinctrl
parent6fa52ed33bea997374a88dbacbba5bf8c7ac4fef (diff)
parentcb3daf580a6bd798580d274a164e63a598d165c5 (diff)
Merge tag 'renesas-pinctrl-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC pinctrl changes for Renesas from Olof Johansson: "This is yet another driver change, which is split out just because of its size. As already in 3.9, a lot of changes are going on here, as the shmobile platform gets converted from its own pin control API to the generic drivers/pinctrl subsystem. Based on agreements with Paul Mundt, we are merging the sh-arch-side changes here as well" * tag 'renesas-pinctrl-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (142 commits) ARM: shmobile: r8a7779: Remove INTC function GPIOs ARM: shmobile: r8a7779: Remove LBSC function GPIOs ARM: shmobile: r8a7779: Remove USB function GPIOs ARM: shmobile: r8a7779: Remove HSPI function GPIOs ARM: shmobile: r8a7779: Remove SCIF function GPIOs ARM: shmobile: r8a7779: Remove SDHI and MMCIF function GPIOs ARM: shmobile: r8a7779: Remove DU function GPIOs ARM: shmobile: r8a7779: Remove DU1_DOTCLKOUT1 GPIO ARM: shmobile: r8a7740: Remove SDHI and MMCIF function GPIOs ARM: shmobile: r8a7740: Remove LCD0 and LCD1 function GPIOs ARM: shmobile: sh73a0: Remove IrDA function GPIOs ARM: shmobile: sh73a0: Remove USB function GPIOs ARM: shmobile: sh73a0: Remove BSC function GPIOs ARM: shmobile: sh73a0: Remove KEYSC function GPIOs ARM: shmobile: sh73a0: Remove pull-up function GPIOS ARM: shmobile: sh73a0: Remove FSI function GPIOs ARM: shmobile: sh73a0: Remove I2C function GPIOs ARM: shmobile: sh73a0: Remove SCIFA and SCIFB function GPIOs ARM: shmobile: sh73a0: Remove LCDC and LCDC2 function GPIOs ARM: shmobile: sh7372: Remove SDHI and MMCIF function GPIOs ...
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c261
-rw-r--r--drivers/pinctrl/sh-pfc/core.h54
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c363
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c694
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7779.c1648
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7203.c488
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7264.c460
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7269.c624
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c323
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c2656
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7720.c333
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7722.c480
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7723.c642
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7724.c638
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7734.c55
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7757.c620
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7785.c354
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7786.c296
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-shx3.c148
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c484
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h135
22 files changed, 7476 insertions, 4281 deletions
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index c3340f54d2ad..af16f8f6ab6c 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -10,6 +10,7 @@ config PINCTRL_SH_PFC
10 select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB 10 select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
11 select PINMUX 11 select PINMUX
12 select PINCONF 12 select PINCONF
13 select GENERIC_PINCONF
13 def_bool y 14 def_bool y
14 help 15 help
15 This enables pin control drivers for SH and SH Mobile platforms 16 This enables pin control drivers for SH and SH Mobile platforms
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 970ddff2b0b6..feef89792568 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -10,7 +10,6 @@
10 */ 10 */
11 11
12#define DRV_NAME "sh-pfc" 12#define DRV_NAME "sh-pfc"
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 13
15#include <linux/bitops.h> 14#include <linux/bitops.h>
16#include <linux/err.h> 15#include <linux/err.h>
@@ -30,10 +29,8 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
30 struct resource *res; 29 struct resource *res;
31 int k; 30 int k;
32 31
33 if (pdev->num_resources == 0) { 32 if (pdev->num_resources == 0)
34 pfc->num_windows = 0; 33 return -EINVAL;
35 return 0;
36 }
37 34
38 pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources * 35 pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
39 sizeof(*pfc->window), GFP_NOWAIT); 36 sizeof(*pfc->window), GFP_NOWAIT);
@@ -59,11 +56,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
59 unsigned long address) 56 unsigned long address)
60{ 57{
61 struct sh_pfc_window *window; 58 struct sh_pfc_window *window;
62 int k; 59 unsigned int i;
63 60
64 /* scan through physical windows and convert address */ 61 /* scan through physical windows and convert address */
65 for (k = 0; k < pfc->num_windows; k++) { 62 for (i = 0; i < pfc->num_windows; i++) {
66 window = pfc->window + k; 63 window = pfc->window + i;
67 64
68 if (address < window->phys) 65 if (address < window->phys)
69 continue; 66 continue;
@@ -74,11 +71,32 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
74 return window->virt + (address - window->phys); 71 return window->virt + (address - window->phys);
75 } 72 }
76 73
77 /* no windows defined, register must be 1:1 mapped virt:phys */ 74 BUG();
78 return (void __iomem *)address;
79} 75}
80 76
81static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) 77int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
78{
79 unsigned int offset;
80 unsigned int i;
81
82 if (pfc->info->ranges == NULL)
83 return pin;
84
85 for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
86 const struct pinmux_range *range = &pfc->info->ranges[i];
87
88 if (pin <= range->end)
89 return pin >= range->begin
90 ? offset + pin - range->begin : -1;
91
92 offset += range->end - range->begin + 1;
93 }
94
95 return -EINVAL;
96}
97
98static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,
99 const struct pinmux_range *r)
82{ 100{
83 if (enum_id < r->begin) 101 if (enum_id < r->begin)
84 return 0; 102 return 0;
@@ -89,8 +107,8 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
89 return 1; 107 return 1;
90} 108}
91 109
92static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, 110unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
93 unsigned long reg_width) 111 unsigned long reg_width)
94{ 112{
95 switch (reg_width) { 113 switch (reg_width) {
96 case 8: 114 case 8:
@@ -105,8 +123,8 @@ static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
105 return 0; 123 return 0;
106} 124}
107 125
108static void sh_pfc_write_raw_reg(void __iomem *mapped_reg, 126void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
109 unsigned long reg_width, unsigned long data) 127 unsigned long data)
110{ 128{
111 switch (reg_width) { 129 switch (reg_width) {
112 case 8: 130 case 8:
@@ -123,39 +141,8 @@ static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
123 BUG(); 141 BUG();
124} 142}
125 143
126int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
127{
128 unsigned long pos;
129
130 pos = dr->reg_width - (in_pos + 1);
131
132 pr_debug("read_bit: addr = %lx, pos = %ld, "
133 "r_width = %ld\n", dr->reg, pos, dr->reg_width);
134
135 return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
136}
137
138void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
139 unsigned long value)
140{
141 unsigned long pos;
142
143 pos = dr->reg_width - (in_pos + 1);
144
145 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
146 "r_width = %ld\n",
147 dr->reg, !!value, pos, dr->reg_width);
148
149 if (value)
150 set_bit(pos, &dr->reg_shadow);
151 else
152 clear_bit(pos, &dr->reg_shadow);
153
154 sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
155}
156
157static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, 144static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
158 struct pinmux_cfg_reg *crp, 145 const struct pinmux_cfg_reg *crp,
159 unsigned long in_pos, 146 unsigned long in_pos,
160 void __iomem **mapped_regp, 147 void __iomem **mapped_regp,
161 unsigned long *maskp, 148 unsigned long *maskp,
@@ -176,24 +163,8 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
176 } 163 }
177} 164}
178 165
179static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
180 struct pinmux_cfg_reg *crp,
181 unsigned long field)
182{
183 void __iomem *mapped_reg;
184 unsigned long mask, pos;
185
186 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
187
188 pr_debug("read_reg: addr = %lx, field = %ld, "
189 "r_width = %ld, f_width = %ld\n",
190 crp->reg, field, crp->reg_width, crp->field_width);
191
192 return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
193}
194
195static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 166static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
196 struct pinmux_cfg_reg *crp, 167 const struct pinmux_cfg_reg *crp,
197 unsigned long field, unsigned long value) 168 unsigned long field, unsigned long value)
198{ 169{
199 void __iomem *mapped_reg; 170 void __iomem *mapped_reg;
@@ -201,9 +172,9 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
201 172
202 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); 173 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
203 174
204 pr_debug("write_reg addr = %lx, value = %ld, field = %ld, " 175 dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
205 "r_width = %ld, f_width = %ld\n", 176 "r_width = %ld, f_width = %ld\n",
206 crp->reg, value, field, crp->reg_width, crp->field_width); 177 crp->reg, value, field, crp->reg_width, crp->field_width);
207 178
208 mask = ~(mask << pos); 179 mask = ~(mask << pos);
209 value = value << pos; 180 value = value << pos;
@@ -220,83 +191,11 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
220 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); 191 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
221} 192}
222 193
223static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
224{
225 struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
226 struct pinmux_data_reg *data_reg;
227 int k, n;
228
229 if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
230 return -1;
231
232 k = 0;
233 while (1) {
234 data_reg = pfc->info->data_regs + k;
235
236 if (!data_reg->reg_width)
237 break;
238
239 data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
240
241 for (n = 0; n < data_reg->reg_width; n++) {
242 if (data_reg->enum_ids[n] == gpiop->enum_id) {
243 gpiop->flags &= ~PINMUX_FLAG_DREG;
244 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
245 gpiop->flags &= ~PINMUX_FLAG_DBIT;
246 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
247 return 0;
248 }
249 }
250 k++;
251 }
252
253 BUG();
254
255 return -1;
256}
257
258static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
259{
260 struct pinmux_data_reg *drp;
261 int k;
262
263 for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++)
264 sh_pfc_setup_data_reg(pfc, k);
265
266 k = 0;
267 while (1) {
268 drp = pfc->info->data_regs + k;
269
270 if (!drp->reg_width)
271 break;
272
273 drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
274 drp->reg_width);
275 k++;
276 }
277}
278
279int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
280 struct pinmux_data_reg **drp, int *bitp)
281{
282 struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
283 int k, n;
284
285 if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
286 return -1;
287
288 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
289 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
290 *drp = pfc->info->data_regs + k;
291 *bitp = n;
292 return 0;
293}
294
295static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, 194static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
296 struct pinmux_cfg_reg **crp, int *fieldp, 195 const struct pinmux_cfg_reg **crp, int *fieldp,
297 int *valuep, unsigned long **cntp) 196 int *valuep)
298{ 197{
299 struct pinmux_cfg_reg *config_reg; 198 const struct pinmux_cfg_reg *config_reg;
300 unsigned long r_width, f_width, curr_width, ncomb; 199 unsigned long r_width, f_width, curr_width, ncomb;
301 int k, m, n, pos, bit_pos; 200 int k, m, n, pos, bit_pos;
302 201
@@ -324,7 +223,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
324 *crp = config_reg; 223 *crp = config_reg;
325 *fieldp = m; 224 *fieldp = m;
326 *valuep = n; 225 *valuep = n;
327 *cntp = &config_reg->cnt[m];
328 return 0; 226 return 0;
329 } 227 }
330 } 228 }
@@ -334,47 +232,39 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
334 k++; 232 k++;
335 } 233 }
336 234
337 return -1; 235 return -EINVAL;
338} 236}
339 237
340int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, 238static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
341 pinmux_enum_t *enum_idp) 239 pinmux_enum_t *enum_idp)
342{ 240{
343 pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id; 241 const pinmux_enum_t *data = pfc->info->gpio_data;
344 pinmux_enum_t *data = pfc->info->gpio_data;
345 int k; 242 int k;
346 243
347 if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) {
348 if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) {
349 pr_err("non data/mark enum_id for gpio %d\n", gpio);
350 return -1;
351 }
352 }
353
354 if (pos) { 244 if (pos) {
355 *enum_idp = data[pos + 1]; 245 *enum_idp = data[pos + 1];
356 return pos + 1; 246 return pos + 1;
357 } 247 }
358 248
359 for (k = 0; k < pfc->info->gpio_data_size; k++) { 249 for (k = 0; k < pfc->info->gpio_data_size; k++) {
360 if (data[k] == enum_id) { 250 if (data[k] == mark) {
361 *enum_idp = data[k + 1]; 251 *enum_idp = data[k + 1];
362 return k + 1; 252 return k + 1;
363 } 253 }
364 } 254 }
365 255
366 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio); 256 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
367 return -1; 257 mark);
258 return -EINVAL;
368} 259}
369 260
370int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, 261int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
371 int cfg_mode)
372{ 262{
373 struct pinmux_cfg_reg *cr = NULL; 263 const struct pinmux_cfg_reg *cr = NULL;
374 pinmux_enum_t enum_id; 264 pinmux_enum_t enum_id;
375 struct pinmux_range *range; 265 const struct pinmux_range *range;
376 int in_range, pos, field, value; 266 int in_range, pos, field, value;
377 unsigned long *cntp; 267 int ret;
378 268
379 switch (pinmux_type) { 269 switch (pinmux_type) {
380 270
@@ -399,7 +289,7 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
399 break; 289 break;
400 290
401 default: 291 default:
402 goto out_err; 292 return -EINVAL;
403 } 293 }
404 294
405 pos = 0; 295 pos = 0;
@@ -407,9 +297,9 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
407 field = 0; 297 field = 0;
408 value = 0; 298 value = 0;
409 while (1) { 299 while (1) {
410 pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id); 300 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
411 if (pos <= 0) 301 if (pos < 0)
412 goto out_err; 302 return pos;
413 303
414 if (!enum_id) 304 if (!enum_id)
415 break; 305 break;
@@ -452,44 +342,22 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
452 if (!in_range) 342 if (!in_range)
453 continue; 343 continue;
454 344
455 if (sh_pfc_get_config_reg(pfc, enum_id, &cr, 345 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
456 &field, &value, &cntp) != 0) 346 if (ret < 0)
457 goto out_err; 347 return ret;
458
459 switch (cfg_mode) {
460 case GPIO_CFG_DRYRUN:
461 if (!*cntp ||
462 (sh_pfc_read_config_reg(pfc, cr, field) != value))
463 continue;
464 break;
465
466 case GPIO_CFG_REQ:
467 sh_pfc_write_config_reg(pfc, cr, field, value);
468 *cntp = *cntp + 1;
469 break;
470 348
471 case GPIO_CFG_FREE: 349 sh_pfc_write_config_reg(pfc, cr, field, value);
472 *cntp = *cntp - 1;
473 break;
474 }
475 } 350 }
476 351
477 return 0; 352 return 0;
478 out_err:
479 return -1;
480} 353}
481 354
482static int sh_pfc_probe(struct platform_device *pdev) 355static int sh_pfc_probe(struct platform_device *pdev)
483{ 356{
484 struct sh_pfc_soc_info *info; 357 const struct sh_pfc_soc_info *info;
485 struct sh_pfc *pfc; 358 struct sh_pfc *pfc;
486 int ret; 359 int ret;
487 360
488 /*
489 * Ensure that the type encoding fits
490 */
491 BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
492
493 info = pdev->id_entry->driver_data 361 info = pdev->id_entry->driver_data
494 ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data; 362 ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
495 if (info == NULL) 363 if (info == NULL)
@@ -509,7 +377,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
509 spin_lock_init(&pfc->lock); 377 spin_lock_init(&pfc->lock);
510 378
511 pinctrl_provide_dummies(); 379 pinctrl_provide_dummies();
512 sh_pfc_setup_data_regs(pfc);
513 380
514 /* 381 /*
515 * Initialize pinctrl bindings first 382 * Initialize pinctrl bindings first
@@ -529,13 +396,13 @@ static int sh_pfc_probe(struct platform_device *pdev)
529 * PFC state as it is, given that there are already 396 * PFC state as it is, given that there are already
530 * extant users of it that have succeeded by this point. 397 * extant users of it that have succeeded by this point.
531 */ 398 */
532 pr_notice("failed to init GPIO chip, ignoring...\n"); 399 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
533 } 400 }
534#endif 401#endif
535 402
536 platform_set_drvdata(pdev, pfc); 403 platform_set_drvdata(pdev, pfc);
537 404
538 pr_info("%s support registered\n", info->name); 405 dev_info(pfc->dev, "%s support registered\n", info->name);
539 406
540 return 0; 407 return 0;
541} 408}
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index ba7c33c33599..763d717ca979 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -26,13 +26,17 @@ struct sh_pfc_pinctrl;
26 26
27struct sh_pfc { 27struct sh_pfc {
28 struct device *dev; 28 struct device *dev;
29 struct sh_pfc_soc_info *info; 29 const struct sh_pfc_soc_info *info;
30 spinlock_t lock; 30 spinlock_t lock;
31 31
32 unsigned int num_windows; 32 unsigned int num_windows;
33 struct sh_pfc_window *window; 33 struct sh_pfc_window *window;
34 34
35 unsigned int nr_pins;
36
35 struct sh_pfc_chip *gpio; 37 struct sh_pfc_chip *gpio;
38 struct sh_pfc_chip *func;
39
36 struct sh_pfc_pinctrl *pinctrl; 40 struct sh_pfc_pinctrl *pinctrl;
37}; 41};
38 42
@@ -42,31 +46,29 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
42int sh_pfc_register_pinctrl(struct sh_pfc *pfc); 46int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
43int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc); 47int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);
44 48
45int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos); 49unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
46void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, 50 unsigned long reg_width);
47 unsigned long value); 51void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
48int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, 52 unsigned long data);
49 struct pinmux_data_reg **drp, int *bitp); 53
50int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, 54int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
51 pinmux_enum_t *enum_idp); 55int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
52int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
53 int cfg_mode);
54 56
55extern struct sh_pfc_soc_info r8a7740_pinmux_info; 57extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
56extern struct sh_pfc_soc_info r8a7779_pinmux_info; 58extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
57extern struct sh_pfc_soc_info sh7203_pinmux_info; 59extern const struct sh_pfc_soc_info sh7203_pinmux_info;
58extern struct sh_pfc_soc_info sh7264_pinmux_info; 60extern const struct sh_pfc_soc_info sh7264_pinmux_info;
59extern struct sh_pfc_soc_info sh7269_pinmux_info; 61extern const struct sh_pfc_soc_info sh7269_pinmux_info;
60extern struct sh_pfc_soc_info sh7372_pinmux_info; 62extern const struct sh_pfc_soc_info sh7372_pinmux_info;
61extern struct sh_pfc_soc_info sh73a0_pinmux_info; 63extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
62extern struct sh_pfc_soc_info sh7720_pinmux_info; 64extern const struct sh_pfc_soc_info sh7720_pinmux_info;
63extern struct sh_pfc_soc_info sh7722_pinmux_info; 65extern const struct sh_pfc_soc_info sh7722_pinmux_info;
64extern struct sh_pfc_soc_info sh7723_pinmux_info; 66extern const struct sh_pfc_soc_info sh7723_pinmux_info;
65extern struct sh_pfc_soc_info sh7724_pinmux_info; 67extern const struct sh_pfc_soc_info sh7724_pinmux_info;
66extern struct sh_pfc_soc_info sh7734_pinmux_info; 68extern const struct sh_pfc_soc_info sh7734_pinmux_info;
67extern struct sh_pfc_soc_info sh7757_pinmux_info; 69extern const struct sh_pfc_soc_info sh7757_pinmux_info;
68extern struct sh_pfc_soc_info sh7785_pinmux_info; 70extern const struct sh_pfc_soc_info sh7785_pinmux_info;
69extern struct sh_pfc_soc_info sh7786_pinmux_info; 71extern const struct sh_pfc_soc_info sh7786_pinmux_info;
70extern struct sh_pfc_soc_info shx3_pinmux_info; 72extern const struct sh_pfc_soc_info shx3_pinmux_info;
71 73
72#endif /* __SH_PFC_CORE_H__ */ 74#endif /* __SH_PFC_CORE_H__ */
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index a535075c8b69..d7acb06d888c 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -9,8 +9,6 @@
9 * for more details. 9 * for more details.
10 */ 10 */
11 11
12#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt
13
14#include <linux/device.h> 12#include <linux/device.h>
15#include <linux/gpio.h> 13#include <linux/gpio.h>
16#include <linux/init.h> 14#include <linux/init.h>
@@ -21,9 +19,23 @@
21 19
22#include "core.h" 20#include "core.h"
23 21
22struct sh_pfc_gpio_data_reg {
23 const struct pinmux_data_reg *info;
24 unsigned long shadow;
25};
26
27struct sh_pfc_gpio_pin {
28 u8 dbit;
29 u8 dreg;
30};
31
24struct sh_pfc_chip { 32struct sh_pfc_chip {
25 struct sh_pfc *pfc; 33 struct sh_pfc *pfc;
26 struct gpio_chip gpio_chip; 34 struct gpio_chip gpio_chip;
35
36 struct sh_pfc_window *mem;
37 struct sh_pfc_gpio_data_reg *regs;
38 struct sh_pfc_gpio_pin *pins;
27}; 39};
28 40
29static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) 41static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
@@ -36,143 +48,358 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
36 return gpio_to_pfc_chip(gc)->pfc; 48 return gpio_to_pfc_chip(gc)->pfc;
37} 49}
38 50
39static int sh_gpio_request(struct gpio_chip *gc, unsigned offset) 51static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio,
52 struct sh_pfc_gpio_data_reg **reg,
53 unsigned int *bit)
40{ 54{
41 return pinctrl_request_gpio(offset); 55 int idx = sh_pfc_get_pin_index(chip->pfc, gpio);
56 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
57
58 *reg = &chip->regs[gpio_pin->dreg];
59 *bit = gpio_pin->dbit;
42} 60}
43 61
44static void sh_gpio_free(struct gpio_chip *gc, unsigned offset) 62static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip,
63 const struct pinmux_data_reg *dreg)
45{ 64{
46 pinctrl_free_gpio(offset); 65 void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
66
67 return sh_pfc_read_raw_reg(mem, dreg->reg_width);
47} 68}
48 69
49static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value) 70static void gpio_write_data_reg(struct sh_pfc_chip *chip,
71 const struct pinmux_data_reg *dreg,
72 unsigned long value)
50{ 73{
51 struct pinmux_data_reg *dr = NULL; 74 void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
52 int bit = 0;
53 75
54 if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) 76 sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
55 BUG(); 77}
56 else 78
57 sh_pfc_write_bit(dr, bit, value); 79static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
80{
81 struct sh_pfc *pfc = chip->pfc;
82 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio];
83 const struct sh_pfc_pin *pin = &pfc->info->pins[gpio];
84 const struct pinmux_data_reg *dreg;
85 unsigned int bit;
86 unsigned int i;
87
88 for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) {
89 for (bit = 0; bit < dreg->reg_width; bit++) {
90 if (dreg->enum_ids[bit] == pin->enum_id) {
91 gpio_pin->dreg = i;
92 gpio_pin->dbit = bit;
93 return;
94 }
95 }
96 }
97
98 BUG();
99}
100
101static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
102{
103 struct sh_pfc *pfc = chip->pfc;
104 unsigned long addr = pfc->info->data_regs[0].reg;
105 const struct pinmux_data_reg *dreg;
106 unsigned int i;
107
108 /* Find the window that contain the GPIO registers. */
109 for (i = 0; i < pfc->num_windows; ++i) {
110 struct sh_pfc_window *window = &pfc->window[i];
111
112 if (addr >= window->phys && addr < window->phys + window->size)
113 break;
114 }
115
116 if (i == pfc->num_windows)
117 return -EINVAL;
118
119 /* GPIO data registers must be in the first memory resource. */
120 chip->mem = &pfc->window[i];
121
122 /* Count the number of data registers, allocate memory and initialize
123 * them.
124 */
125 for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
126 ;
127
128 chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs),
129 GFP_KERNEL);
130 if (chip->regs == NULL)
131 return -ENOMEM;
132
133 for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
134 chip->regs[i].info = dreg;
135 chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
136 }
137
138 for (i = 0; i < pfc->info->nr_pins; i++) {
139 if (pfc->info->pins[i].enum_id == 0)
140 continue;
141
142 gpio_setup_data_reg(chip, i);
143 }
144
145 return 0;
58} 146}
59 147
60static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio) 148/* -----------------------------------------------------------------------------
149 * Pin GPIOs
150 */
151
152static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
61{ 153{
62 struct pinmux_data_reg *dr = NULL; 154 struct sh_pfc *pfc = gpio_to_pfc(gc);
63 int bit = 0; 155 int idx = sh_pfc_get_pin_index(pfc, offset);
64 156
65 if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) 157 if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
66 return -EINVAL; 158 return -EINVAL;
67 159
68 return sh_pfc_read_bit(dr, bit); 160 return pinctrl_request_gpio(offset);
69} 161}
70 162
71static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 163static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
164{
165 return pinctrl_free_gpio(offset);
166}
167
168static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
169 int value)
170{
171 struct sh_pfc_gpio_data_reg *reg;
172 unsigned long pos;
173 unsigned int bit;
174
175 gpio_get_data_reg(chip, offset, &reg, &bit);
176
177 pos = reg->info->reg_width - (bit + 1);
178
179 if (value)
180 set_bit(pos, &reg->shadow);
181 else
182 clear_bit(pos, &reg->shadow);
183
184 gpio_write_data_reg(chip, reg->info, reg->shadow);
185}
186
187static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
72{ 188{
73 return pinctrl_gpio_direction_input(offset); 189 return pinctrl_gpio_direction_input(offset);
74} 190}
75 191
76static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 192static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
77 int value) 193 int value)
78{ 194{
79 sh_gpio_set_value(gpio_to_pfc(gc), offset, value); 195 gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
80 196
81 return pinctrl_gpio_direction_output(offset); 197 return pinctrl_gpio_direction_output(offset);
82} 198}
83 199
84static int sh_gpio_get(struct gpio_chip *gc, unsigned offset) 200static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
85{ 201{
86 return sh_gpio_get_value(gpio_to_pfc(gc), offset); 202 struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
203 struct sh_pfc_gpio_data_reg *reg;
204 unsigned long pos;
205 unsigned int bit;
206
207 gpio_get_data_reg(chip, offset, &reg, &bit);
208
209 pos = reg->info->reg_width - (bit + 1);
210
211 return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
87} 212}
88 213
89static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 214static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
90{ 215{
91 sh_gpio_set_value(gpio_to_pfc(gc), offset, value); 216 gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
92} 217}
93 218
94static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 219static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
95{ 220{
96 struct sh_pfc *pfc = gpio_to_pfc(gc); 221 struct sh_pfc *pfc = gpio_to_pfc(gc);
97 pinmux_enum_t enum_id; 222 int i, k;
98 pinmux_enum_t *enum_ids;
99 int i, k, pos;
100
101 pos = 0;
102 enum_id = 0;
103 while (1) {
104 pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id);
105 if (pos <= 0 || !enum_id)
106 break;
107 223
108 for (i = 0; i < pfc->info->gpio_irq_size; i++) { 224 for (i = 0; i < pfc->info->gpio_irq_size; i++) {
109 enum_ids = pfc->info->gpio_irq[i].enum_ids; 225 unsigned short *gpios = pfc->info->gpio_irq[i].gpios;
110 for (k = 0; enum_ids[k]; k++) { 226
111 if (enum_ids[k] == enum_id) 227 for (k = 0; gpios[k]; k++) {
112 return pfc->info->gpio_irq[i].irq; 228 if (gpios[k] == offset)
113 } 229 return pfc->info->gpio_irq[i].irq;
114 } 230 }
115 } 231 }
116 232
117 return -ENOSYS; 233 return -ENOSYS;
118} 234}
119 235
120static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip) 236static int gpio_pin_setup(struct sh_pfc_chip *chip)
121{ 237{
122 struct sh_pfc *pfc = chip->pfc; 238 struct sh_pfc *pfc = chip->pfc;
123 struct gpio_chip *gc = &chip->gpio_chip; 239 struct gpio_chip *gc = &chip->gpio_chip;
240 int ret;
241
242 chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins),
243 GFP_KERNEL);
244 if (chip->pins == NULL)
245 return -ENOMEM;
124 246
125 gc->request = sh_gpio_request; 247 ret = gpio_setup_data_regs(chip);
126 gc->free = sh_gpio_free; 248 if (ret < 0)
127 gc->direction_input = sh_gpio_direction_input; 249 return ret;
128 gc->get = sh_gpio_get;
129 gc->direction_output = sh_gpio_direction_output;
130 gc->set = sh_gpio_set;
131 gc->to_irq = sh_gpio_to_irq;
132 250
133 WARN_ON(pfc->info->first_gpio != 0); /* needs testing */ 251 gc->request = gpio_pin_request;
252 gc->free = gpio_pin_free;
253 gc->direction_input = gpio_pin_direction_input;
254 gc->get = gpio_pin_get;
255 gc->direction_output = gpio_pin_direction_output;
256 gc->set = gpio_pin_set;
257 gc->to_irq = gpio_pin_to_irq;
134 258
135 gc->label = pfc->info->name; 259 gc->label = pfc->info->name;
260 gc->dev = pfc->dev;
136 gc->owner = THIS_MODULE; 261 gc->owner = THIS_MODULE;
137 gc->base = pfc->info->first_gpio; 262 gc->base = 0;
138 gc->ngpio = (pfc->info->last_gpio - pfc->info->first_gpio) + 1; 263 gc->ngpio = pfc->nr_pins;
264
265 return 0;
139} 266}
140 267
141int sh_pfc_register_gpiochip(struct sh_pfc *pfc) 268/* -----------------------------------------------------------------------------
269 * Function GPIOs
270 */
271
272static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
273{
274 static bool __print_once;
275 struct sh_pfc *pfc = gpio_to_pfc(gc);
276 unsigned int mark = pfc->info->func_gpios[offset].enum_id;
277 unsigned long flags;
278 int ret;
279
280 if (!__print_once) {
281 dev_notice(pfc->dev,
282 "Use of GPIO API for function requests is deprecated."
283 " Convert to pinctrl\n");
284 __print_once = true;
285 }
286
287 if (mark == 0)
288 return -EINVAL;
289
290 spin_lock_irqsave(&pfc->lock, flags);
291 ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
292 spin_unlock_irqrestore(&pfc->lock, flags);
293
294 return ret;
295}
296
297static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
298{
299}
300
301static int gpio_function_setup(struct sh_pfc_chip *chip)
302{
303 struct sh_pfc *pfc = chip->pfc;
304 struct gpio_chip *gc = &chip->gpio_chip;
305
306 gc->request = gpio_function_request;
307 gc->free = gpio_function_free;
308
309 gc->label = pfc->info->name;
310 gc->owner = THIS_MODULE;
311 gc->base = pfc->nr_pins;
312 gc->ngpio = pfc->info->nr_func_gpios;
313
314 return 0;
315}
316
317/* -----------------------------------------------------------------------------
318 * Register/unregister
319 */
320
321static struct sh_pfc_chip *
322sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *))
142{ 323{
143 struct sh_pfc_chip *chip; 324 struct sh_pfc_chip *chip;
144 int ret; 325 int ret;
145 326
146 chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL); 327 chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
147 if (unlikely(!chip)) 328 if (unlikely(!chip))
148 return -ENOMEM; 329 return ERR_PTR(-ENOMEM);
149 330
150 chip->pfc = pfc; 331 chip->pfc = pfc;
151 332
152 sh_pfc_gpio_setup(chip); 333 ret = setup(chip);
334 if (ret < 0)
335 return ERR_PTR(ret);
153 336
154 ret = gpiochip_add(&chip->gpio_chip); 337 ret = gpiochip_add(&chip->gpio_chip);
155 if (unlikely(ret < 0)) 338 if (unlikely(ret < 0))
156 return ret; 339 return ERR_PTR(ret);
340
341 dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
342 chip->gpio_chip.label, chip->gpio_chip.base,
343 chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
344
345 return chip;
346}
347
348int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
349{
350 const struct pinmux_range *ranges;
351 struct pinmux_range def_range;
352 struct sh_pfc_chip *chip;
353 unsigned int nr_ranges;
354 unsigned int i;
355 int ret;
356
357 /* Register the real GPIOs chip. */
358 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup);
359 if (IS_ERR(chip))
360 return PTR_ERR(chip);
157 361
158 pfc->gpio = chip; 362 pfc->gpio = chip;
159 363
160 pr_info("%s handling gpio %d -> %d\n", 364 /* Register the GPIO to pin mappings. */
161 pfc->info->name, pfc->info->first_gpio, 365 if (pfc->info->ranges == NULL) {
162 pfc->info->last_gpio); 366 def_range.begin = 0;
367 def_range.end = pfc->info->nr_pins - 1;
368 ranges = &def_range;
369 nr_ranges = 1;
370 } else {
371 ranges = pfc->info->ranges;
372 nr_ranges = pfc->info->nr_ranges;
373 }
374
375 for (i = 0; i < nr_ranges; ++i) {
376 const struct pinmux_range *range = &ranges[i];
377
378 ret = gpiochip_add_pin_range(&chip->gpio_chip,
379 dev_name(pfc->dev),
380 range->begin, range->begin,
381 range->end - range->begin + 1);
382 if (ret < 0)
383 return ret;
384 }
385
386 /* Register the function GPIOs chip. */
387 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup);
388 if (IS_ERR(chip))
389 return PTR_ERR(chip);
390
391 pfc->func = chip;
163 392
164 return 0; 393 return 0;
165} 394}
166 395
167int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) 396int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
168{ 397{
169 struct sh_pfc_chip *chip = pfc->gpio; 398 int err;
170 int ret; 399 int ret;
171 400
172 ret = gpiochip_remove(&chip->gpio_chip); 401 ret = gpiochip_remove(&pfc->gpio->gpio_chip);
173 if (unlikely(ret < 0)) 402 err = gpiochip_remove(&pfc->func->gpio_chip);
174 return ret;
175 403
176 pfc->gpio = NULL; 404 return ret < 0 ? ret : err;
177 return 0;
178} 405}
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 214788c4a606..3621d3e81fc3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -577,7 +577,7 @@ enum {
577 PINMUX_MARK_END, 577 PINMUX_MARK_END,
578}; 578};
579 579
580static pinmux_enum_t pinmux_data[] = { 580static const pinmux_enum_t pinmux_data[] = {
581 /* specify valid pin states for each pin in GPIO mode */ 581 /* specify valid pin states for each pin in GPIO mode */
582 582
583 /* I/O and Pull U/D */ 583 /* I/O and Pull U/D */
@@ -1654,11 +1654,532 @@ static pinmux_enum_t pinmux_data[] = {
1654 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), 1654 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1655}; 1655};
1656 1656
1657static struct pinmux_gpio pinmux_gpios[] = { 1657static struct sh_pfc_pin pinmux_pins[] = {
1658
1659 /* PORT */
1660 GPIO_PORT_ALL(), 1658 GPIO_PORT_ALL(),
1659};
1660
1661/* - LCD0 ------------------------------------------------------------------- */
1662static const unsigned int lcd0_data8_pins[] = {
1663 /* D[0:7] */
1664 58, 57, 56, 55, 54, 53, 52, 51,
1665};
1666static const unsigned int lcd0_data8_mux[] = {
1667 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1668 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1669};
1670static const unsigned int lcd0_data9_pins[] = {
1671 /* D[0:8] */
1672 58, 57, 56, 55, 54, 53, 52, 51,
1673 50,
1674};
1675static const unsigned int lcd0_data9_mux[] = {
1676 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1677 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1678 LCD0_D8_MARK,
1679};
1680static const unsigned int lcd0_data12_pins[] = {
1681 /* D[0:11] */
1682 58, 57, 56, 55, 54, 53, 52, 51,
1683 50, 49, 48, 47,
1684};
1685static const unsigned int lcd0_data12_mux[] = {
1686 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1687 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1688 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1689};
1690static const unsigned int lcd0_data16_pins[] = {
1691 /* D[0:15] */
1692 58, 57, 56, 55, 54, 53, 52, 51,
1693 50, 49, 48, 47, 46, 45, 44, 43,
1694};
1695static const unsigned int lcd0_data16_mux[] = {
1696 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1697 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1698 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1699 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1700};
1701static const unsigned int lcd0_data18_pins[] = {
1702 /* D[0:17] */
1703 58, 57, 56, 55, 54, 53, 52, 51,
1704 50, 49, 48, 47, 46, 45, 44, 43,
1705 42, 41,
1706};
1707static const unsigned int lcd0_data18_mux[] = {
1708 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1709 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1710 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1711 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1712 LCD0_D16_MARK, LCD0_D17_MARK,
1713};
1714static const unsigned int lcd0_data24_0_pins[] = {
1715 /* D[0:23] */
1716 58, 57, 56, 55, 54, 53, 52, 51,
1717 50, 49, 48, 47, 46, 45, 44, 43,
1718 42, 41, 40, 4, 3, 2, 0, 1,
1719};
1720static const unsigned int lcd0_data24_0_mux[] = {
1721 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1722 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1723 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1724 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1725 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
1726 LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
1727 LCD0_D23_PORT1_MARK,
1728};
1729static const unsigned int lcd0_data24_1_pins[] = {
1730 /* D[0:23] */
1731 58, 57, 56, 55, 54, 53, 52, 51,
1732 50, 49, 48, 47, 46, 45, 44, 43,
1733 42, 41, 163, 162, 161, 158, 160, 159,
1734};
1735static const unsigned int lcd0_data24_1_mux[] = {
1736 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1737 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1738 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1739 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
1740 LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
1741 LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
1742};
1743static const unsigned int lcd0_display_pins[] = {
1744 /* DON, VCPWC, VEPWC */
1745 61, 59, 60,
1746};
1747static const unsigned int lcd0_display_mux[] = {
1748 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
1749};
1750static const unsigned int lcd0_lclk_0_pins[] = {
1751 /* LCLK */
1752 102,
1753};
1754static const unsigned int lcd0_lclk_0_mux[] = {
1755 LCD0_LCLK_PORT102_MARK,
1756};
1757static const unsigned int lcd0_lclk_1_pins[] = {
1758 /* LCLK */
1759 165,
1760};
1761static const unsigned int lcd0_lclk_1_mux[] = {
1762 LCD0_LCLK_PORT165_MARK,
1763};
1764static const unsigned int lcd0_sync_pins[] = {
1765 /* VSYN, HSYN, DCK, DISP */
1766 63, 64, 62, 65,
1767};
1768static const unsigned int lcd0_sync_mux[] = {
1769 LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
1770};
1771static const unsigned int lcd0_sys_pins[] = {
1772 /* CS, WR, RD, RS */
1773 64, 62, 164, 65,
1774};
1775static const unsigned int lcd0_sys_mux[] = {
1776 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
1777};
1778/* - LCD1 ------------------------------------------------------------------- */
1779static const unsigned int lcd1_data8_pins[] = {
1780 /* D[0:7] */
1781 4, 3, 2, 1, 0, 91, 92, 23,
1782};
1783static const unsigned int lcd1_data8_mux[] = {
1784 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1785 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1786};
1787static const unsigned int lcd1_data9_pins[] = {
1788 /* D[0:8] */
1789 4, 3, 2, 1, 0, 91, 92, 23,
1790 93,
1791};
1792static const unsigned int lcd1_data9_mux[] = {
1793 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1794 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1795 LCD1_D8_MARK,
1796};
1797static const unsigned int lcd1_data12_pins[] = {
1798 /* D[0:12] */
1799 4, 3, 2, 1, 0, 91, 92, 23,
1800 93, 94, 21, 201,
1801};
1802static const unsigned int lcd1_data12_mux[] = {
1803 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1804 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1805 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1806};
1807static const unsigned int lcd1_data16_pins[] = {
1808 /* D[0:15] */
1809 4, 3, 2, 1, 0, 91, 92, 23,
1810 93, 94, 21, 201, 200, 199, 196, 195,
1811};
1812static const unsigned int lcd1_data16_mux[] = {
1813 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1814 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1815 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1816 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
1817};
1818static const unsigned int lcd1_data18_pins[] = {
1819 /* D[0:17] */
1820 4, 3, 2, 1, 0, 91, 92, 23,
1821 93, 94, 21, 201, 200, 199, 196, 195,
1822 194, 193,
1823};
1824static const unsigned int lcd1_data18_mux[] = {
1825 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1826 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1827 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1828 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
1829 LCD1_D16_MARK, LCD1_D17_MARK,
1830};
1831static const unsigned int lcd1_data24_pins[] = {
1832 /* D[0:23] */
1833 4, 3, 2, 1, 0, 91, 92, 23,
1834 93, 94, 21, 201, 200, 199, 196, 195,
1835 194, 193, 198, 197, 75, 74, 15, 14,
1836};
1837static const unsigned int lcd1_data24_mux[] = {
1838 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1839 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1840 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1841 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
1842 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
1843 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
1844};
1845static const unsigned int lcd1_display_pins[] = {
1846 /* DON, VCPWC, VEPWC */
1847 100, 5, 6,
1848};
1849static const unsigned int lcd1_display_mux[] = {
1850 LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
1851};
1852static const unsigned int lcd1_lclk_pins[] = {
1853 /* LCLK */
1854 40,
1855};
1856static const unsigned int lcd1_lclk_mux[] = {
1857 LCD1_LCLK_MARK,
1858};
1859static const unsigned int lcd1_sync_pins[] = {
1860 /* VSYN, HSYN, DCK, DISP */
1861 98, 97, 99, 12,
1862};
1863static const unsigned int lcd1_sync_mux[] = {
1864 LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
1865};
1866static const unsigned int lcd1_sys_pins[] = {
1867 /* CS, WR, RD, RS */
1868 97, 99, 13, 12,
1869};
1870static const unsigned int lcd1_sys_mux[] = {
1871 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
1872};
1873/* - MMCIF ------------------------------------------------------------------ */
1874static const unsigned int mmc0_data1_0_pins[] = {
1875 /* D[0] */
1876 68,
1877};
1878static const unsigned int mmc0_data1_0_mux[] = {
1879 MMC0_D0_PORT68_MARK,
1880};
1881static const unsigned int mmc0_data4_0_pins[] = {
1882 /* D[0:3] */
1883 68, 69, 70, 71,
1884};
1885static const unsigned int mmc0_data4_0_mux[] = {
1886 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
1887};
1888static const unsigned int mmc0_data8_0_pins[] = {
1889 /* D[0:7] */
1890 68, 69, 70, 71, 72, 73, 74, 75,
1891};
1892static const unsigned int mmc0_data8_0_mux[] = {
1893 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
1894 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
1895};
1896static const unsigned int mmc0_ctrl_0_pins[] = {
1897 /* CMD, CLK */
1898 67, 66,
1899};
1900static const unsigned int mmc0_ctrl_0_mux[] = {
1901 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
1902};
1903
1904static const unsigned int mmc0_data1_1_pins[] = {
1905 /* D[0] */
1906 149,
1907};
1908static const unsigned int mmc0_data1_1_mux[] = {
1909 MMC1_D0_PORT149_MARK,
1910};
1911static const unsigned int mmc0_data4_1_pins[] = {
1912 /* D[0:3] */
1913 149, 148, 147, 146,
1914};
1915static const unsigned int mmc0_data4_1_mux[] = {
1916 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
1917};
1918static const unsigned int mmc0_data8_1_pins[] = {
1919 /* D[0:7] */
1920 149, 148, 147, 146, 145, 144, 143, 142,
1921};
1922static const unsigned int mmc0_data8_1_mux[] = {
1923 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
1924 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
1925};
1926static const unsigned int mmc0_ctrl_1_pins[] = {
1927 /* CMD, CLK */
1928 104, 103,
1929};
1930static const unsigned int mmc0_ctrl_1_mux[] = {
1931 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
1932};
1933/* - SDHI0 ------------------------------------------------------------------ */
1934static const unsigned int sdhi0_data1_pins[] = {
1935 /* D0 */
1936 77,
1937};
1938static const unsigned int sdhi0_data1_mux[] = {
1939 SDHI0_D0_MARK,
1940};
1941static const unsigned int sdhi0_data4_pins[] = {
1942 /* D[0:3] */
1943 77, 78, 79, 80,
1944};
1945static const unsigned int sdhi0_data4_mux[] = {
1946 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
1947};
1948static const unsigned int sdhi0_ctrl_pins[] = {
1949 /* CMD, CLK */
1950 76, 82,
1951};
1952static const unsigned int sdhi0_ctrl_mux[] = {
1953 SDHI0_CMD_MARK, SDHI0_CLK_MARK,
1954};
1955static const unsigned int sdhi0_cd_pins[] = {
1956 /* CD */
1957 81,
1958};
1959static const unsigned int sdhi0_cd_mux[] = {
1960 SDHI0_CD_MARK,
1961};
1962static const unsigned int sdhi0_wp_pins[] = {
1963 /* WP */
1964 83,
1965};
1966static const unsigned int sdhi0_wp_mux[] = {
1967 SDHI0_WP_MARK,
1968};
1969/* - SDHI1 ------------------------------------------------------------------ */
1970static const unsigned int sdhi1_data1_pins[] = {
1971 /* D0 */
1972 68,
1973};
1974static const unsigned int sdhi1_data1_mux[] = {
1975 SDHI1_D0_MARK,
1976};
1977static const unsigned int sdhi1_data4_pins[] = {
1978 /* D[0:3] */
1979 68, 69, 70, 71,
1980};
1981static const unsigned int sdhi1_data4_mux[] = {
1982 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
1983};
1984static const unsigned int sdhi1_ctrl_pins[] = {
1985 /* CMD, CLK */
1986 67, 66,
1987};
1988static const unsigned int sdhi1_ctrl_mux[] = {
1989 SDHI1_CMD_MARK, SDHI1_CLK_MARK,
1990};
1991static const unsigned int sdhi1_cd_pins[] = {
1992 /* CD */
1993 72,
1994};
1995static const unsigned int sdhi1_cd_mux[] = {
1996 SDHI1_CD_MARK,
1997};
1998static const unsigned int sdhi1_wp_pins[] = {
1999 /* WP */
2000 73,
2001};
2002static const unsigned int sdhi1_wp_mux[] = {
2003 SDHI1_WP_MARK,
2004};
2005/* - SDHI2 ------------------------------------------------------------------ */
2006static const unsigned int sdhi2_data1_pins[] = {
2007 /* D0 */
2008 205,
2009};
2010static const unsigned int sdhi2_data1_mux[] = {
2011 SDHI2_D0_MARK,
2012};
2013static const unsigned int sdhi2_data4_pins[] = {
2014 /* D[0:3] */
2015 205, 206, 207, 208,
2016};
2017static const unsigned int sdhi2_data4_mux[] = {
2018 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2019};
2020static const unsigned int sdhi2_ctrl_pins[] = {
2021 /* CMD, CLK */
2022 204, 203,
2023};
2024static const unsigned int sdhi2_ctrl_mux[] = {
2025 SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2026};
2027static const unsigned int sdhi2_cd_0_pins[] = {
2028 /* CD */
2029 202,
2030};
2031static const unsigned int sdhi2_cd_0_mux[] = {
2032 SDHI2_CD_PORT202_MARK,
2033};
2034static const unsigned int sdhi2_wp_0_pins[] = {
2035 /* WP */
2036 177,
2037};
2038static const unsigned int sdhi2_wp_0_mux[] = {
2039 SDHI2_WP_PORT177_MARK,
2040};
2041static const unsigned int sdhi2_cd_1_pins[] = {
2042 /* CD */
2043 24,
2044};
2045static const unsigned int sdhi2_cd_1_mux[] = {
2046 SDHI2_CD_PORT24_MARK,
2047};
2048static const unsigned int sdhi2_wp_1_pins[] = {
2049 /* WP */
2050 25,
2051};
2052static const unsigned int sdhi2_wp_1_mux[] = {
2053 SDHI2_WP_PORT25_MARK,
2054};
1661 2055
2056static const struct sh_pfc_pin_group pinmux_groups[] = {
2057 SH_PFC_PIN_GROUP(lcd0_data8),
2058 SH_PFC_PIN_GROUP(lcd0_data9),
2059 SH_PFC_PIN_GROUP(lcd0_data12),
2060 SH_PFC_PIN_GROUP(lcd0_data16),
2061 SH_PFC_PIN_GROUP(lcd0_data18),
2062 SH_PFC_PIN_GROUP(lcd0_data24_0),
2063 SH_PFC_PIN_GROUP(lcd0_data24_1),
2064 SH_PFC_PIN_GROUP(lcd0_display),
2065 SH_PFC_PIN_GROUP(lcd0_lclk_0),
2066 SH_PFC_PIN_GROUP(lcd0_lclk_1),
2067 SH_PFC_PIN_GROUP(lcd0_sync),
2068 SH_PFC_PIN_GROUP(lcd0_sys),
2069 SH_PFC_PIN_GROUP(lcd1_data8),
2070 SH_PFC_PIN_GROUP(lcd1_data9),
2071 SH_PFC_PIN_GROUP(lcd1_data12),
2072 SH_PFC_PIN_GROUP(lcd1_data16),
2073 SH_PFC_PIN_GROUP(lcd1_data18),
2074 SH_PFC_PIN_GROUP(lcd1_data24),
2075 SH_PFC_PIN_GROUP(lcd1_display),
2076 SH_PFC_PIN_GROUP(lcd1_lclk),
2077 SH_PFC_PIN_GROUP(lcd1_sync),
2078 SH_PFC_PIN_GROUP(lcd1_sys),
2079 SH_PFC_PIN_GROUP(mmc0_data1_0),
2080 SH_PFC_PIN_GROUP(mmc0_data4_0),
2081 SH_PFC_PIN_GROUP(mmc0_data8_0),
2082 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2083 SH_PFC_PIN_GROUP(mmc0_data1_1),
2084 SH_PFC_PIN_GROUP(mmc0_data4_1),
2085 SH_PFC_PIN_GROUP(mmc0_data8_1),
2086 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2087 SH_PFC_PIN_GROUP(sdhi0_data1),
2088 SH_PFC_PIN_GROUP(sdhi0_data4),
2089 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2090 SH_PFC_PIN_GROUP(sdhi0_cd),
2091 SH_PFC_PIN_GROUP(sdhi0_wp),
2092 SH_PFC_PIN_GROUP(sdhi1_data1),
2093 SH_PFC_PIN_GROUP(sdhi1_data4),
2094 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2095 SH_PFC_PIN_GROUP(sdhi1_cd),
2096 SH_PFC_PIN_GROUP(sdhi1_wp),
2097 SH_PFC_PIN_GROUP(sdhi2_data1),
2098 SH_PFC_PIN_GROUP(sdhi2_data4),
2099 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2100 SH_PFC_PIN_GROUP(sdhi2_cd_0),
2101 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2102 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2103 SH_PFC_PIN_GROUP(sdhi2_wp_1),
2104};
2105
2106static const char * const lcd0_groups[] = {
2107 "lcd0_data8",
2108 "lcd0_data9",
2109 "lcd0_data12",
2110 "lcd0_data16",
2111 "lcd0_data18",
2112 "lcd0_data24_0",
2113 "lcd0_data24_1",
2114 "lcd0_display",
2115 "lcd0_lclk_0",
2116 "lcd0_lclk_1",
2117 "lcd0_sync",
2118 "lcd0_sys",
2119};
2120
2121static const char * const lcd1_groups[] = {
2122 "lcd1_data8",
2123 "lcd1_data9",
2124 "lcd1_data12",
2125 "lcd1_data16",
2126 "lcd1_data18",
2127 "lcd1_data24",
2128 "lcd1_display",
2129 "lcd1_lclk",
2130 "lcd1_sync",
2131 "lcd1_sys",
2132};
2133
2134static const char * const mmc0_groups[] = {
2135 "mmc0_data1_0",
2136 "mmc0_data4_0",
2137 "mmc0_data8_0",
2138 "mmc0_ctrl_0",
2139 "mmc0_data1_1",
2140 "mmc0_data4_1",
2141 "mmc0_data8_1",
2142 "mmc0_ctrl_1",
2143};
2144
2145static const char * const sdhi0_groups[] = {
2146 "sdhi0_data1",
2147 "sdhi0_data4",
2148 "sdhi0_ctrl",
2149 "sdhi0_cd",
2150 "sdhi0_wp",
2151};
2152
2153static const char * const sdhi1_groups[] = {
2154 "sdhi1_data1",
2155 "sdhi1_data4",
2156 "sdhi1_ctrl",
2157 "sdhi1_cd",
2158 "sdhi1_wp",
2159};
2160
2161static const char * const sdhi2_groups[] = {
2162 "sdhi2_data1",
2163 "sdhi2_data4",
2164 "sdhi2_ctrl",
2165 "sdhi2_cd_0",
2166 "sdhi2_wp_0",
2167 "sdhi2_cd_1",
2168 "sdhi2_wp_1",
2169};
2170
2171static const struct sh_pfc_function pinmux_functions[] = {
2172 SH_PFC_FUNCTION(lcd0),
2173 SH_PFC_FUNCTION(lcd1),
2174 SH_PFC_FUNCTION(mmc0),
2175 SH_PFC_FUNCTION(sdhi0),
2176 SH_PFC_FUNCTION(sdhi1),
2177 SH_PFC_FUNCTION(sdhi2),
2178};
2179
2180#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
2181
2182static const struct pinmux_func pinmux_func_gpios[] = {
1662 /* IRQ */ 2183 /* IRQ */
1663 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), 2184 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
1664 GPIO_FN(IRQ1), 2185 GPIO_FN(IRQ1),
@@ -1792,43 +2313,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1792 GPIO_FN(SCIFB_RTS_PORT172), 2313 GPIO_FN(SCIFB_RTS_PORT172),
1793 GPIO_FN(SCIFB_CTS_PORT173), 2314 GPIO_FN(SCIFB_CTS_PORT173),
1794 2315
1795 /* LCD0 */
1796 GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
1797 GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
1798 GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
1799 GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
1800 GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
1801 GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
1802 GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
1803 GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
1804 GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
1805 GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
1806 GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
1807
1808 GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
1809 GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
1810 GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
1811 GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
1812
1813 GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
1814 GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
1815 GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
1816 GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
1817
1818 /* LCD1 */
1819 GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
1820 GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
1821 GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
1822 GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
1823 GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
1824 GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
1825 GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
1826 GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
1827 GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
1828 GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
1829 GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
1830 GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
1831
1832 /* RSPI */ 2316 /* RSPI */
1833 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), 2317 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
1834 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), 2318 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
@@ -1889,26 +2373,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1889 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ 2373 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
1890 GPIO_FN(SIM_D_PORT199), 2374 GPIO_FN(SIM_D_PORT199),
1891 2375
1892 /* SDHI0 */
1893 GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
1894 GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
1895 GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
1896
1897 /* SDHI1 */
1898 GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
1899 GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
1900 GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
1901
1902 /* SDHI2 */
1903 GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
1904 GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
1905
1906 GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
1907 GPIO_FN(SDHI2_WP_PORT25),
1908
1909 GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
1910 GPIO_FN(SDHI2_CD_PORT202),
1911
1912 /* MSIOF2 */ 2376 /* MSIOF2 */
1913 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), 2377 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
1914 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), 2378 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
@@ -1953,21 +2417,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1953 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), 2417 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
1954 GPIO_FN(MEMC_A0), 2418 GPIO_FN(MEMC_A0),
1955 2419
1956 /* MMC */
1957 GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
1958 GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
1959 GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
1960 GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
1961 GPIO_FN(MMC0_CLK_PORT66),
1962 GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
1963
1964 GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
1965 GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
1966 GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
1967 GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
1968 GPIO_FN(MMC1_CLK_PORT103),
1969 GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
1970
1971 /* MSIOF0 */ 2420 /* MSIOF0 */
1972 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), 2421 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
1973 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), 2422 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
@@ -2126,7 +2575,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
2126 GPIO_FN(TRACEAUD_FROM_MEMC), 2575 GPIO_FN(TRACEAUD_FROM_MEMC),
2127}; 2576};
2128 2577
2129static struct pinmux_cfg_reg pinmux_config_regs[] = { 2578static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2130 PORTCR(0, 0xe6050000), /* PORT0CR */ 2579 PORTCR(0, 0xe6050000), /* PORT0CR */
2131 PORTCR(1, 0xe6050001), /* PORT1CR */ 2580 PORTCR(1, 0xe6050001), /* PORT1CR */
2132 PORTCR(2, 0xe6050002), /* PORT2CR */ 2581 PORTCR(2, 0xe6050002), /* PORT2CR */
@@ -2440,7 +2889,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2440 { }, 2889 { },
2441}; 2890};
2442 2891
2443static struct pinmux_data_reg pinmux_data_regs[] = { 2892static const struct pinmux_data_reg pinmux_data_regs[] = {
2444 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) { 2893 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
2445 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, 2894 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2446 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, 2895 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
@@ -2544,46 +2993,43 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2544 { }, 2993 { },
2545}; 2994};
2546 2995
2547static struct pinmux_irq pinmux_irqs[] = { 2996static const struct pinmux_irq pinmux_irqs[] = {
2548 PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */ 2997 PINMUX_IRQ(evt2irq(0x0200), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */
2549 PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */ 2998 PINMUX_IRQ(evt2irq(0x0220), GPIO_PORT20), /* IRQ1A */
2550 PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */ 2999 PINMUX_IRQ(evt2irq(0x0240), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */
2551 PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */ 3000 PINMUX_IRQ(evt2irq(0x0260), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */
2552 PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */ 3001 PINMUX_IRQ(evt2irq(0x0280), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */
2553 PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */ 3002 PINMUX_IRQ(evt2irq(0x02A0), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */
2554 PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */ 3003 PINMUX_IRQ(evt2irq(0x02C0), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
2555 PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */ 3004 PINMUX_IRQ(evt2irq(0x02E0), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
2556 PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */ 3005 PINMUX_IRQ(evt2irq(0x0300), GPIO_PORT119), /* IRQ8A */
2557 PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */ 3006 PINMUX_IRQ(evt2irq(0x0320), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
2558 PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */ 3007 PINMUX_IRQ(evt2irq(0x0340), GPIO_PORT19), /* IRQ10A */
2559 PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */ 3008 PINMUX_IRQ(evt2irq(0x0360), GPIO_PORT104), /* IRQ11A */
2560 PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */ 3009 PINMUX_IRQ(evt2irq(0x0380), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */
2561 PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */ 3010 PINMUX_IRQ(evt2irq(0x03A0), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */
2562 PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */ 3011 PINMUX_IRQ(evt2irq(0x03C0), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */
2563 PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */ 3012 PINMUX_IRQ(evt2irq(0x03E0), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */
2564 PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */ 3013 PINMUX_IRQ(evt2irq(0x3200), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */
2565 PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */ 3014 PINMUX_IRQ(evt2irq(0x3220), GPIO_PORT69), /* IRQ17A */
2566 PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */ 3015 PINMUX_IRQ(evt2irq(0x3240), GPIO_PORT70), /* IRQ18A */
2567 PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */ 3016 PINMUX_IRQ(evt2irq(0x3260), GPIO_PORT71), /* IRQ19A */
2568 PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */ 3017 PINMUX_IRQ(evt2irq(0x3280), GPIO_PORT67), /* IRQ20A */
2569 PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */ 3018 PINMUX_IRQ(evt2irq(0x32A0), GPIO_PORT202), /* IRQ21A */
2570 PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */ 3019 PINMUX_IRQ(evt2irq(0x32C0), GPIO_PORT95), /* IRQ22A */
2571 PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */ 3020 PINMUX_IRQ(evt2irq(0x32E0), GPIO_PORT96), /* IRQ23A */
2572 PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */ 3021 PINMUX_IRQ(evt2irq(0x3300), GPIO_PORT180), /* IRQ24A */
2573 PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */ 3022 PINMUX_IRQ(evt2irq(0x3320), GPIO_PORT38), /* IRQ25A */
2574 PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */ 3023 PINMUX_IRQ(evt2irq(0x3340), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */
2575 PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */ 3024 PINMUX_IRQ(evt2irq(0x3360), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */
2576 PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */ 3025 PINMUX_IRQ(evt2irq(0x3380), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */
2577 PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */ 3026 PINMUX_IRQ(evt2irq(0x33A0), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */
2578 PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */ 3027 PINMUX_IRQ(evt2irq(0x33C0), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */
2579 PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */ 3028 PINMUX_IRQ(evt2irq(0x33E0), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */
2580}; 3029};
2581 3030
2582struct sh_pfc_soc_info r8a7740_pinmux_info = { 3031const struct sh_pfc_soc_info r8a7740_pinmux_info = {
2583 .name = "r8a7740_pfc", 3032 .name = "r8a7740_pfc",
2584 .reserved_id = PINMUX_RESERVED,
2585 .data = { PINMUX_DATA_BEGIN,
2586 PINMUX_DATA_END },
2587 .input = { PINMUX_INPUT_BEGIN, 3033 .input = { PINMUX_INPUT_BEGIN,
2588 PINMUX_INPUT_END }, 3034 PINMUX_INPUT_END },
2589 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, 3035 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
@@ -2592,15 +3038,19 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = {
2592 PINMUX_INPUT_PULLDOWN_END }, 3038 PINMUX_INPUT_PULLDOWN_END },
2593 .output = { PINMUX_OUTPUT_BEGIN, 3039 .output = { PINMUX_OUTPUT_BEGIN,
2594 PINMUX_OUTPUT_END }, 3040 PINMUX_OUTPUT_END },
2595 .mark = { PINMUX_MARK_BEGIN,
2596 PINMUX_MARK_END },
2597 .function = { PINMUX_FUNCTION_BEGIN, 3041 .function = { PINMUX_FUNCTION_BEGIN,
2598 PINMUX_FUNCTION_END }, 3042 PINMUX_FUNCTION_END },
2599 3043
2600 .first_gpio = GPIO_PORT0, 3044 .pins = pinmux_pins,
2601 .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC, 3045 .nr_pins = ARRAY_SIZE(pinmux_pins),
3046 .groups = pinmux_groups,
3047 .nr_groups = ARRAY_SIZE(pinmux_groups),
3048 .functions = pinmux_functions,
3049 .nr_functions = ARRAY_SIZE(pinmux_functions),
3050
3051 .func_gpios = pinmux_func_gpios,
3052 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2602 3053
2603 .gpios = pinmux_gpios,
2604 .cfg_regs = pinmux_config_regs, 3054 .cfg_regs = pinmux_config_regs,
2605 .data_regs = pinmux_data_regs, 3055 .data_regs = pinmux_data_regs,
2606 3056
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 13feaa0c0eb7..1d7b0dfbbb21 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -23,11 +23,6 @@
23 23
24#include "sh_pfc.h" 24#include "sh_pfc.h"
25 25
26#define CPU_32_PORT(fn, pfx, sfx) \
27 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
28 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
29 PORT_1(fn, pfx##31, sfx)
30
31#define CPU_32_PORT6(fn, pfx, sfx) \ 26#define CPU_32_PORT6(fn, pfx, sfx) \
32 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ 27 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
33 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ 28 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
@@ -36,12 +31,12 @@
36 PORT_1(fn, pfx##8, sfx) 31 PORT_1(fn, pfx##8, sfx)
37 32
38#define CPU_ALL_PORT(fn, pfx, sfx) \ 33#define CPU_ALL_PORT(fn, pfx, sfx) \
39 CPU_32_PORT(fn, pfx##_0_, sfx), \ 34 PORT_32(fn, pfx##_0_, sfx), \
40 CPU_32_PORT(fn, pfx##_1_, sfx), \ 35 PORT_32(fn, pfx##_1_, sfx), \
41 CPU_32_PORT(fn, pfx##_2_, sfx), \ 36 PORT_32(fn, pfx##_2_, sfx), \
42 CPU_32_PORT(fn, pfx##_3_, sfx), \ 37 PORT_32(fn, pfx##_3_, sfx), \
43 CPU_32_PORT(fn, pfx##_4_, sfx), \ 38 PORT_32(fn, pfx##_4_, sfx), \
44 CPU_32_PORT(fn, pfx##_5_, sfx), \ 39 PORT_32(fn, pfx##_5_, sfx), \
45 CPU_32_PORT6(fn, pfx##_6_, sfx) 40 CPU_32_PORT6(fn, pfx##_6_, sfx)
46 41
47#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) 42#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
@@ -55,21 +50,8 @@
55#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) 50#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
56#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) 51#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
57 52
58 53#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
59#define PORT_10_REV(fn, pfx, sfx) \ 54#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
60 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
61 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
62 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
63 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
64 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
65
66#define CPU_32_PORT_REV(fn, pfx, sfx) \
67 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
68 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
69 PORT_10_REV(fn, pfx, sfx)
70
71#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
72#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
73 55
74#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) 56#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
75#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ 57#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
@@ -371,7 +353,7 @@ enum {
371 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, 353 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
372 FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, 354 FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
373 FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0, 355 FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
374 FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2, 356 FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
375 FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1, 357 FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
376 FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, 358 FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
377 359
@@ -447,7 +429,8 @@ enum {
447 A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK, 429 A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
448 BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK, 430 BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
449 ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK, 431 ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
450 USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, 432 USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
433 SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
451 SCIF_CLK_MARK, TCLK0_C_MARK, 434 SCIF_CLK_MARK, TCLK0_C_MARK,
452 435
453 EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK, 436 EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
@@ -632,7 +615,7 @@ enum {
632 HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK, 615 HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
633 MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK, 616 MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
634 SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK, 617 SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
635 VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK, 618 VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
636 DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK, 619 DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
637 VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK, 620 VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
638 DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK, 621 DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
@@ -649,7 +632,7 @@ enum {
649 PINMUX_MARK_END, 632 PINMUX_MARK_END,
650}; 633};
651 634
652static pinmux_enum_t pinmux_data[] = { 635static const pinmux_enum_t pinmux_data[] = {
653 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 636 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
654 637
655 PINMUX_DATA(AVS1_MARK, FN_AVS1), 638 PINMUX_DATA(AVS1_MARK, FN_AVS1),
@@ -658,6 +641,9 @@ static pinmux_enum_t pinmux_data[] = {
658 PINMUX_DATA(A18_MARK, FN_A18), 641 PINMUX_DATA(A18_MARK, FN_A18),
659 PINMUX_DATA(A19_MARK, FN_A19), 642 PINMUX_DATA(A19_MARK, FN_A19),
660 643
644 PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0),
645 PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
646
661 PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2), 647 PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
662 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0), 648 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
663 PINMUX_IPSR_DATA(IP0_2_0, PWM1), 649 PINMUX_IPSR_DATA(IP0_2_0, PWM1),
@@ -1399,7 +1385,6 @@ static pinmux_enum_t pinmux_data[] = {
1399 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3), 1385 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1400 PINMUX_IPSR_DATA(IP11_26_24, VI1_G0), 1386 PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
1401 PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0), 1387 PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
1402 PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
1403 PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1), 1388 PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
1404 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1), 1389 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1405 PINMUX_IPSR_DATA(IP11_26_24, TX2), 1390 PINMUX_IPSR_DATA(IP11_26_24, TX2),
@@ -1450,140 +1435,1372 @@ static pinmux_enum_t pinmux_data[] = {
1450 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), 1435 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1451}; 1436};
1452 1437
1453static struct pinmux_gpio pinmux_gpios[] = { 1438static struct sh_pfc_pin pinmux_pins[] = {
1454 PINMUX_GPIO_GP_ALL(), 1439 PINMUX_GPIO_GP_ALL(),
1440};
1441
1442/* - DU0 -------------------------------------------------------------------- */
1443static const unsigned int du0_rgb666_pins[] = {
1444 /* R[7:2], G[7:2], B[7:2] */
1445 188, 187, 186, 185, 184, 183,
1446 194, 193, 192, 191, 190, 189,
1447 200, 199, 198, 197, 196, 195,
1448};
1449static const unsigned int du0_rgb666_mux[] = {
1450 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1451 DU0_DR3_MARK, DU0_DR2_MARK,
1452 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1453 DU0_DG3_MARK, DU0_DG2_MARK,
1454 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1455 DU0_DB3_MARK, DU0_DB2_MARK,
1456};
1457static const unsigned int du0_rgb888_pins[] = {
1458 /* R[7:0], G[7:0], B[7:0] */
1459 188, 187, 186, 185, 184, 183, 24, 23,
1460 194, 193, 192, 191, 190, 189, 26, 25,
1461 200, 199, 198, 197, 196, 195, 28, 27,
1462};
1463static const unsigned int du0_rgb888_mux[] = {
1464 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1465 DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1466 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1467 DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1468 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1469 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1470};
1471static const unsigned int du0_clk_0_pins[] = {
1472 /* CLKIN, CLKOUT */
1473 29, 180,
1474};
1475static const unsigned int du0_clk_0_mux[] = {
1476 DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT0_MARK,
1477};
1478static const unsigned int du0_clk_1_pins[] = {
1479 /* CLKIN, CLKOUT */
1480 29, 30,
1481};
1482static const unsigned int du0_clk_1_mux[] = {
1483 DU0_DOTCLKIN_MARK, DU0_DOTCLKOUT1_MARK,
1484};
1485static const unsigned int du0_sync_0_pins[] = {
1486 /* VSYNC, HSYNC, DISP */
1487 182, 181, 31,
1488};
1489static const unsigned int du0_sync_0_mux[] = {
1490 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1491 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1492};
1493static const unsigned int du0_sync_1_pins[] = {
1494 /* VSYNC, HSYNC, DISP */
1495 182, 181, 32,
1496};
1497static const unsigned int du0_sync_1_mux[] = {
1498 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1499 DU0_DISP_MARK
1500};
1501static const unsigned int du0_oddf_pins[] = {
1502 /* ODDF */
1503 31,
1504};
1505static const unsigned int du0_oddf_mux[] = {
1506 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1507};
1508static const unsigned int du0_cde_pins[] = {
1509 /* CDE */
1510 33,
1511};
1512static const unsigned int du0_cde_mux[] = {
1513 DU0_CDE_MARK
1514};
1515/* - DU1 -------------------------------------------------------------------- */
1516static const unsigned int du1_rgb666_pins[] = {
1517 /* R[7:2], G[7:2], B[7:2] */
1518 41, 40, 39, 38, 37, 36,
1519 49, 48, 47, 46, 45, 44,
1520 57, 56, 55, 54, 53, 52,
1521};
1522static const unsigned int du1_rgb666_mux[] = {
1523 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1524 DU1_DR3_MARK, DU1_DR2_MARK,
1525 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1526 DU1_DG3_MARK, DU1_DG2_MARK,
1527 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1528 DU1_DB3_MARK, DU1_DB2_MARK,
1529};
1530static const unsigned int du1_rgb888_pins[] = {
1531 /* R[7:0], G[7:0], B[7:0] */
1532 41, 40, 39, 38, 37, 36, 35, 34,
1533 49, 48, 47, 46, 45, 44, 43, 32,
1534 57, 56, 55, 54, 53, 52, 51, 50,
1535};
1536static const unsigned int du1_rgb888_mux[] = {
1537 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1538 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1539 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1540 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1541 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1542 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1543};
1544static const unsigned int du1_clk_pins[] = {
1545 /* CLKIN, CLKOUT */
1546 58, 59,
1547};
1548static const unsigned int du1_clk_mux[] = {
1549 DU1_DOTCLKIN_MARK, DU1_DOTCLKOUT_MARK,
1550};
1551static const unsigned int du1_sync_0_pins[] = {
1552 /* VSYNC, HSYNC, DISP */
1553 61, 60, 62,
1554};
1555static const unsigned int du1_sync_0_mux[] = {
1556 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1557 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1558};
1559static const unsigned int du1_sync_1_pins[] = {
1560 /* VSYNC, HSYNC, DISP */
1561 61, 60, 63,
1562};
1563static const unsigned int du1_sync_1_mux[] = {
1564 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1565 DU1_DISP_MARK
1566};
1567static const unsigned int du1_oddf_pins[] = {
1568 /* ODDF */
1569 62,
1570};
1571static const unsigned int du1_oddf_mux[] = {
1572 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1573};
1574static const unsigned int du1_cde_pins[] = {
1575 /* CDE */
1576 64,
1577};
1578static const unsigned int du1_cde_mux[] = {
1579 DU1_CDE_MARK
1580};
1581/* - HSPI0 ------------------------------------------------------------------ */
1582static const unsigned int hspi0_pins[] = {
1583 /* CLK, CS, RX, TX */
1584 150, 151, 153, 152,
1585};
1586static const unsigned int hspi0_mux[] = {
1587 HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
1588};
1589/* - HSPI1 ------------------------------------------------------------------ */
1590static const unsigned int hspi1_pins[] = {
1591 /* CLK, CS, RX, TX */
1592 63, 58, 64, 62,
1593};
1594static const unsigned int hspi1_mux[] = {
1595 HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
1596};
1597static const unsigned int hspi1_b_pins[] = {
1598 /* CLK, CS, RX, TX */
1599 90, 91, 93, 92,
1600};
1601static const unsigned int hspi1_b_mux[] = {
1602 HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
1603};
1604static const unsigned int hspi1_c_pins[] = {
1605 /* CLK, CS, RX, TX */
1606 141, 142, 144, 143,
1607};
1608static const unsigned int hspi1_c_mux[] = {
1609 HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
1610};
1611static const unsigned int hspi1_d_pins[] = {
1612 /* CLK, CS, RX, TX */
1613 101, 102, 104, 103,
1614};
1615static const unsigned int hspi1_d_mux[] = {
1616 HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
1617};
1618/* - HSPI2 ------------------------------------------------------------------ */
1619static const unsigned int hspi2_pins[] = {
1620 /* CLK, CS, RX, TX */
1621 9, 10, 11, 14,
1622};
1623static const unsigned int hspi2_mux[] = {
1624 HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
1625};
1626static const unsigned int hspi2_b_pins[] = {
1627 /* CLK, CS, RX, TX */
1628 7, 13, 8, 6,
1629};
1630static const unsigned int hspi2_b_mux[] = {
1631 HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
1632};
1633/* - INTC ------------------------------------------------------------------- */
1634static const unsigned int intc_irq0_pins[] = {
1635 /* IRQ */
1636 78,
1637};
1638static const unsigned int intc_irq0_mux[] = {
1639 IRQ0_MARK,
1640};
1641static const unsigned int intc_irq0_b_pins[] = {
1642 /* IRQ */
1643 141,
1644};
1645static const unsigned int intc_irq0_b_mux[] = {
1646 IRQ0_B_MARK,
1647};
1648static const unsigned int intc_irq1_pins[] = {
1649 /* IRQ */
1650 79,
1651};
1652static const unsigned int intc_irq1_mux[] = {
1653 IRQ1_MARK,
1654};
1655static const unsigned int intc_irq1_b_pins[] = {
1656 /* IRQ */
1657 142,
1658};
1659static const unsigned int intc_irq1_b_mux[] = {
1660 IRQ1_B_MARK,
1661};
1662static const unsigned int intc_irq2_pins[] = {
1663 /* IRQ */
1664 88,
1665};
1666static const unsigned int intc_irq2_mux[] = {
1667 IRQ2_MARK,
1668};
1669static const unsigned int intc_irq2_b_pins[] = {
1670 /* IRQ */
1671 143,
1672};
1673static const unsigned int intc_irq2_b_mux[] = {
1674 IRQ2_B_MARK,
1675};
1676static const unsigned int intc_irq3_pins[] = {
1677 /* IRQ */
1678 89,
1679};
1680static const unsigned int intc_irq3_mux[] = {
1681 IRQ3_MARK,
1682};
1683static const unsigned int intc_irq3_b_pins[] = {
1684 /* IRQ */
1685 144,
1686};
1687static const unsigned int intc_irq3_b_mux[] = {
1688 IRQ3_B_MARK,
1689};
1690/* - LSBC ------------------------------------------------------------------- */
1691static const unsigned int lbsc_cs0_pins[] = {
1692 /* CS */
1693 13,
1694};
1695static const unsigned int lbsc_cs0_mux[] = {
1696 CS0_MARK,
1697};
1698static const unsigned int lbsc_cs1_pins[] = {
1699 /* CS */
1700 14,
1701};
1702static const unsigned int lbsc_cs1_mux[] = {
1703 CS1_A26_MARK,
1704};
1705static const unsigned int lbsc_ex_cs0_pins[] = {
1706 /* CS */
1707 15,
1708};
1709static const unsigned int lbsc_ex_cs0_mux[] = {
1710 EX_CS0_MARK,
1711};
1712static const unsigned int lbsc_ex_cs1_pins[] = {
1713 /* CS */
1714 16,
1715};
1716static const unsigned int lbsc_ex_cs1_mux[] = {
1717 EX_CS1_MARK,
1718};
1719static const unsigned int lbsc_ex_cs2_pins[] = {
1720 /* CS */
1721 17,
1722};
1723static const unsigned int lbsc_ex_cs2_mux[] = {
1724 EX_CS2_MARK,
1725};
1726static const unsigned int lbsc_ex_cs3_pins[] = {
1727 /* CS */
1728 18,
1729};
1730static const unsigned int lbsc_ex_cs3_mux[] = {
1731 EX_CS3_MARK,
1732};
1733static const unsigned int lbsc_ex_cs4_pins[] = {
1734 /* CS */
1735 19,
1736};
1737static const unsigned int lbsc_ex_cs4_mux[] = {
1738 EX_CS4_MARK,
1739};
1740static const unsigned int lbsc_ex_cs5_pins[] = {
1741 /* CS */
1742 20,
1743};
1744static const unsigned int lbsc_ex_cs5_mux[] = {
1745 EX_CS5_MARK,
1746};
1747/* - MMCIF ------------------------------------------------------------------ */
1748static const unsigned int mmc0_data1_pins[] = {
1749 /* D[0] */
1750 19,
1751};
1752static const unsigned int mmc0_data1_mux[] = {
1753 MMC0_D0_MARK,
1754};
1755static const unsigned int mmc0_data4_pins[] = {
1756 /* D[0:3] */
1757 19, 20, 21, 2,
1758};
1759static const unsigned int mmc0_data4_mux[] = {
1760 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1761};
1762static const unsigned int mmc0_data8_pins[] = {
1763 /* D[0:7] */
1764 19, 20, 21, 2, 10, 11, 15, 16,
1765};
1766static const unsigned int mmc0_data8_mux[] = {
1767 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1768 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
1769};
1770static const unsigned int mmc0_ctrl_pins[] = {
1771 /* CMD, CLK */
1772 18, 17,
1773};
1774static const unsigned int mmc0_ctrl_mux[] = {
1775 MMC0_CMD_MARK, MMC0_CLK_MARK,
1776};
1777static const unsigned int mmc1_data1_pins[] = {
1778 /* D[0] */
1779 72,
1780};
1781static const unsigned int mmc1_data1_mux[] = {
1782 MMC1_D0_MARK,
1783};
1784static const unsigned int mmc1_data4_pins[] = {
1785 /* D[0:3] */
1786 72, 73, 74, 75,
1787};
1788static const unsigned int mmc1_data4_mux[] = {
1789 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1790};
1791static const unsigned int mmc1_data8_pins[] = {
1792 /* D[0:7] */
1793 72, 73, 74, 75, 76, 77, 80, 81,
1794};
1795static const unsigned int mmc1_data8_mux[] = {
1796 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1797 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
1798};
1799static const unsigned int mmc1_ctrl_pins[] = {
1800 /* CMD, CLK */
1801 68, 65,
1802};
1803static const unsigned int mmc1_ctrl_mux[] = {
1804 MMC1_CMD_MARK, MMC1_CLK_MARK,
1805};
1806/* - SCIF0 ------------------------------------------------------------------ */
1807static const unsigned int scif0_data_pins[] = {
1808 /* RXD, TXD */
1809 153, 152,
1810};
1811static const unsigned int scif0_data_mux[] = {
1812 RX0_MARK, TX0_MARK,
1813};
1814static const unsigned int scif0_clk_pins[] = {
1815 /* SCK */
1816 156,
1817};
1818static const unsigned int scif0_clk_mux[] = {
1819 SCK0_MARK,
1820};
1821static const unsigned int scif0_ctrl_pins[] = {
1822 /* RTS, CTS */
1823 151, 150,
1824};
1825static const unsigned int scif0_ctrl_mux[] = {
1826 RTS0_TANS_MARK, CTS0_MARK,
1827};
1828static const unsigned int scif0_data_b_pins[] = {
1829 /* RXD, TXD */
1830 20, 19,
1831};
1832static const unsigned int scif0_data_b_mux[] = {
1833 RX0_B_MARK, TX0_B_MARK,
1834};
1835static const unsigned int scif0_clk_b_pins[] = {
1836 /* SCK */
1837 33,
1838};
1839static const unsigned int scif0_clk_b_mux[] = {
1840 SCK0_B_MARK,
1841};
1842static const unsigned int scif0_ctrl_b_pins[] = {
1843 /* RTS, CTS */
1844 18, 11,
1845};
1846static const unsigned int scif0_ctrl_b_mux[] = {
1847 RTS0_B_TANS_B_MARK, CTS0_B_MARK,
1848};
1849static const unsigned int scif0_data_c_pins[] = {
1850 /* RXD, TXD */
1851 146, 147,
1852};
1853static const unsigned int scif0_data_c_mux[] = {
1854 RX0_C_MARK, TX0_C_MARK,
1855};
1856static const unsigned int scif0_clk_c_pins[] = {
1857 /* SCK */
1858 145,
1859};
1860static const unsigned int scif0_clk_c_mux[] = {
1861 SCK0_C_MARK,
1862};
1863static const unsigned int scif0_ctrl_c_pins[] = {
1864 /* RTS, CTS */
1865 149, 148,
1866};
1867static const unsigned int scif0_ctrl_c_mux[] = {
1868 RTS0_C_TANS_C_MARK, CTS0_C_MARK,
1869};
1870static const unsigned int scif0_data_d_pins[] = {
1871 /* RXD, TXD */
1872 43, 42,
1873};
1874static const unsigned int scif0_data_d_mux[] = {
1875 RX0_D_MARK, TX0_D_MARK,
1876};
1877static const unsigned int scif0_clk_d_pins[] = {
1878 /* SCK */
1879 50,
1880};
1881static const unsigned int scif0_clk_d_mux[] = {
1882 SCK0_D_MARK,
1883};
1884static const unsigned int scif0_ctrl_d_pins[] = {
1885 /* RTS, CTS */
1886 51, 35,
1887};
1888static const unsigned int scif0_ctrl_d_mux[] = {
1889 RTS0_D_TANS_D_MARK, CTS0_D_MARK,
1890};
1891/* - SCIF1 ------------------------------------------------------------------ */
1892static const unsigned int scif1_data_pins[] = {
1893 /* RXD, TXD */
1894 149, 148,
1895};
1896static const unsigned int scif1_data_mux[] = {
1897 RX1_MARK, TX1_MARK,
1898};
1899static const unsigned int scif1_clk_pins[] = {
1900 /* SCK */
1901 145,
1902};
1903static const unsigned int scif1_clk_mux[] = {
1904 SCK1_MARK,
1905};
1906static const unsigned int scif1_ctrl_pins[] = {
1907 /* RTS, CTS */
1908 147, 146,
1909};
1910static const unsigned int scif1_ctrl_mux[] = {
1911 RTS1_TANS_MARK, CTS1_MARK,
1912};
1913static const unsigned int scif1_data_b_pins[] = {
1914 /* RXD, TXD */
1915 117, 114,
1916};
1917static const unsigned int scif1_data_b_mux[] = {
1918 RX1_B_MARK, TX1_B_MARK,
1919};
1920static const unsigned int scif1_clk_b_pins[] = {
1921 /* SCK */
1922 113,
1923};
1924static const unsigned int scif1_clk_b_mux[] = {
1925 SCK1_B_MARK,
1926};
1927static const unsigned int scif1_ctrl_b_pins[] = {
1928 /* RTS, CTS */
1929 115, 116,
1930};
1931static const unsigned int scif1_ctrl_b_mux[] = {
1932 RTS1_B_TANS_B_MARK, CTS1_B_MARK,
1933};
1934static const unsigned int scif1_data_c_pins[] = {
1935 /* RXD, TXD */
1936 67, 66,
1937};
1938static const unsigned int scif1_data_c_mux[] = {
1939 RX1_C_MARK, TX1_C_MARK,
1940};
1941static const unsigned int scif1_clk_c_pins[] = {
1942 /* SCK */
1943 86,
1944};
1945static const unsigned int scif1_clk_c_mux[] = {
1946 SCK1_C_MARK,
1947};
1948static const unsigned int scif1_ctrl_c_pins[] = {
1949 /* RTS, CTS */
1950 69, 68,
1951};
1952static const unsigned int scif1_ctrl_c_mux[] = {
1953 RTS1_C_TANS_C_MARK, CTS1_C_MARK,
1954};
1955/* - SCIF2 ------------------------------------------------------------------ */
1956static const unsigned int scif2_data_pins[] = {
1957 /* RXD, TXD */
1958 106, 105,
1959};
1960static const unsigned int scif2_data_mux[] = {
1961 RX2_MARK, TX2_MARK,
1962};
1963static const unsigned int scif2_clk_pins[] = {
1964 /* SCK */
1965 107,
1966};
1967static const unsigned int scif2_clk_mux[] = {
1968 SCK2_MARK,
1969};
1970static const unsigned int scif2_data_b_pins[] = {
1971 /* RXD, TXD */
1972 120, 119,
1973};
1974static const unsigned int scif2_data_b_mux[] = {
1975 RX2_B_MARK, TX2_B_MARK,
1976};
1977static const unsigned int scif2_clk_b_pins[] = {
1978 /* SCK */
1979 118,
1980};
1981static const unsigned int scif2_clk_b_mux[] = {
1982 SCK2_B_MARK,
1983};
1984static const unsigned int scif2_data_c_pins[] = {
1985 /* RXD, TXD */
1986 33, 31,
1987};
1988static const unsigned int scif2_data_c_mux[] = {
1989 RX2_C_MARK, TX2_C_MARK,
1990};
1991static const unsigned int scif2_clk_c_pins[] = {
1992 /* SCK */
1993 32,
1994};
1995static const unsigned int scif2_clk_c_mux[] = {
1996 SCK2_C_MARK,
1997};
1998static const unsigned int scif2_data_d_pins[] = {
1999 /* RXD, TXD */
2000 64, 62,
2001};
2002static const unsigned int scif2_data_d_mux[] = {
2003 RX2_D_MARK, TX2_D_MARK,
2004};
2005static const unsigned int scif2_clk_d_pins[] = {
2006 /* SCK */
2007 63,
2008};
2009static const unsigned int scif2_clk_d_mux[] = {
2010 SCK2_D_MARK,
2011};
2012static const unsigned int scif2_data_e_pins[] = {
2013 /* RXD, TXD */
2014 20, 19,
2015};
2016static const unsigned int scif2_data_e_mux[] = {
2017 RX2_E_MARK, TX2_E_MARK,
2018};
2019/* - SCIF3 ------------------------------------------------------------------ */
2020static const unsigned int scif3_data_pins[] = {
2021 /* RXD, TXD */
2022 137, 136,
2023};
2024static const unsigned int scif3_data_mux[] = {
2025 RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
2026};
2027static const unsigned int scif3_clk_pins[] = {
2028 /* SCK */
2029 135,
2030};
2031static const unsigned int scif3_clk_mux[] = {
2032 SCK3_MARK,
2033};
2034
2035static const unsigned int scif3_data_b_pins[] = {
2036 /* RXD, TXD */
2037 64, 62,
2038};
2039static const unsigned int scif3_data_b_mux[] = {
2040 RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
2041};
2042static const unsigned int scif3_data_c_pins[] = {
2043 /* RXD, TXD */
2044 15, 12,
2045};
2046static const unsigned int scif3_data_c_mux[] = {
2047 RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
2048};
2049static const unsigned int scif3_data_d_pins[] = {
2050 /* RXD, TXD */
2051 30, 29,
2052};
2053static const unsigned int scif3_data_d_mux[] = {
2054 RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
2055};
2056static const unsigned int scif3_data_e_pins[] = {
2057 /* RXD, TXD */
2058 35, 34,
2059};
2060static const unsigned int scif3_data_e_mux[] = {
2061 RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
2062};
2063static const unsigned int scif3_clk_e_pins[] = {
2064 /* SCK */
2065 42,
2066};
2067static const unsigned int scif3_clk_e_mux[] = {
2068 SCK3_E_MARK,
2069};
2070/* - SCIF4 ------------------------------------------------------------------ */
2071static const unsigned int scif4_data_pins[] = {
2072 /* RXD, TXD */
2073 123, 122,
2074};
2075static const unsigned int scif4_data_mux[] = {
2076 RX4_MARK, TX4_MARK,
2077};
2078static const unsigned int scif4_clk_pins[] = {
2079 /* SCK */
2080 121,
2081};
2082static const unsigned int scif4_clk_mux[] = {
2083 SCK4_MARK,
2084};
2085static const unsigned int scif4_data_b_pins[] = {
2086 /* RXD, TXD */
2087 111, 110,
2088};
2089static const unsigned int scif4_data_b_mux[] = {
2090 RX4_B_MARK, TX4_B_MARK,
2091};
2092static const unsigned int scif4_clk_b_pins[] = {
2093 /* SCK */
2094 112,
2095};
2096static const unsigned int scif4_clk_b_mux[] = {
2097 SCK4_B_MARK,
2098};
2099static const unsigned int scif4_data_c_pins[] = {
2100 /* RXD, TXD */
2101 22, 21,
2102};
2103static const unsigned int scif4_data_c_mux[] = {
2104 RX4_C_MARK, TX4_C_MARK,
2105};
2106static const unsigned int scif4_data_d_pins[] = {
2107 /* RXD, TXD */
2108 69, 68,
2109};
2110static const unsigned int scif4_data_d_mux[] = {
2111 RX4_D_MARK, TX4_D_MARK,
2112};
2113/* - SCIF5 ------------------------------------------------------------------ */
2114static const unsigned int scif5_data_pins[] = {
2115 /* RXD, TXD */
2116 51, 50,
2117};
2118static const unsigned int scif5_data_mux[] = {
2119 RX5_MARK, TX5_MARK,
2120};
2121static const unsigned int scif5_clk_pins[] = {
2122 /* SCK */
2123 43,
2124};
2125static const unsigned int scif5_clk_mux[] = {
2126 SCK5_MARK,
2127};
2128static const unsigned int scif5_data_b_pins[] = {
2129 /* RXD, TXD */
2130 18, 11,
2131};
2132static const unsigned int scif5_data_b_mux[] = {
2133 RX5_B_MARK, TX5_B_MARK,
2134};
2135static const unsigned int scif5_clk_b_pins[] = {
2136 /* SCK */
2137 19,
2138};
2139static const unsigned int scif5_clk_b_mux[] = {
2140 SCK5_B_MARK,
2141};
2142static const unsigned int scif5_data_c_pins[] = {
2143 /* RXD, TXD */
2144 24, 23,
2145};
2146static const unsigned int scif5_data_c_mux[] = {
2147 RX5_C_MARK, TX5_C_MARK,
2148};
2149static const unsigned int scif5_clk_c_pins[] = {
2150 /* SCK */
2151 28,
2152};
2153static const unsigned int scif5_clk_c_mux[] = {
2154 SCK5_C_MARK,
2155};
2156static const unsigned int scif5_data_d_pins[] = {
2157 /* RXD, TXD */
2158 8, 6,
2159};
2160static const unsigned int scif5_data_d_mux[] = {
2161 RX5_D_MARK, TX5_D_MARK,
2162};
2163static const unsigned int scif5_clk_d_pins[] = {
2164 /* SCK */
2165 7,
2166};
2167static const unsigned int scif5_clk_d_mux[] = {
2168 SCK5_D_MARK,
2169};
2170/* - SDHI0 ------------------------------------------------------------------ */
2171static const unsigned int sdhi0_data1_pins[] = {
2172 /* D0 */
2173 117,
2174};
2175static const unsigned int sdhi0_data1_mux[] = {
2176 SD0_DAT0_MARK,
2177};
2178static const unsigned int sdhi0_data4_pins[] = {
2179 /* D[0:3] */
2180 117, 118, 119, 120,
2181};
2182static const unsigned int sdhi0_data4_mux[] = {
2183 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2184};
2185static const unsigned int sdhi0_ctrl_pins[] = {
2186 /* CMD, CLK */
2187 114, 113,
2188};
2189static const unsigned int sdhi0_ctrl_mux[] = {
2190 SD0_CMD_MARK, SD0_CLK_MARK,
2191};
2192static const unsigned int sdhi0_cd_pins[] = {
2193 /* CD */
2194 115,
2195};
2196static const unsigned int sdhi0_cd_mux[] = {
2197 SD0_CD_MARK,
2198};
2199static const unsigned int sdhi0_wp_pins[] = {
2200 /* WP */
2201 116,
2202};
2203static const unsigned int sdhi0_wp_mux[] = {
2204 SD0_WP_MARK,
2205};
2206/* - SDHI1 ------------------------------------------------------------------ */
2207static const unsigned int sdhi1_data1_pins[] = {
2208 /* D0 */
2209 19,
2210};
2211static const unsigned int sdhi1_data1_mux[] = {
2212 SD1_DAT0_MARK,
2213};
2214static const unsigned int sdhi1_data4_pins[] = {
2215 /* D[0:3] */
2216 19, 20, 21, 2,
2217};
2218static const unsigned int sdhi1_data4_mux[] = {
2219 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2220};
2221static const unsigned int sdhi1_ctrl_pins[] = {
2222 /* CMD, CLK */
2223 18, 17,
2224};
2225static const unsigned int sdhi1_ctrl_mux[] = {
2226 SD1_CMD_MARK, SD1_CLK_MARK,
2227};
2228static const unsigned int sdhi1_cd_pins[] = {
2229 /* CD */
2230 10,
2231};
2232static const unsigned int sdhi1_cd_mux[] = {
2233 SD1_CD_MARK,
2234};
2235static const unsigned int sdhi1_wp_pins[] = {
2236 /* WP */
2237 11,
2238};
2239static const unsigned int sdhi1_wp_mux[] = {
2240 SD1_WP_MARK,
2241};
2242/* - SDHI2 ------------------------------------------------------------------ */
2243static const unsigned int sdhi2_data1_pins[] = {
2244 /* D0 */
2245 97,
2246};
2247static const unsigned int sdhi2_data1_mux[] = {
2248 SD2_DAT0_MARK,
2249};
2250static const unsigned int sdhi2_data4_pins[] = {
2251 /* D[0:3] */
2252 97, 98, 99, 100,
2253};
2254static const unsigned int sdhi2_data4_mux[] = {
2255 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2256};
2257static const unsigned int sdhi2_ctrl_pins[] = {
2258 /* CMD, CLK */
2259 102, 101,
2260};
2261static const unsigned int sdhi2_ctrl_mux[] = {
2262 SD2_CMD_MARK, SD2_CLK_MARK,
2263};
2264static const unsigned int sdhi2_cd_pins[] = {
2265 /* CD */
2266 103,
2267};
2268static const unsigned int sdhi2_cd_mux[] = {
2269 SD2_CD_MARK,
2270};
2271static const unsigned int sdhi2_wp_pins[] = {
2272 /* WP */
2273 104,
2274};
2275static const unsigned int sdhi2_wp_mux[] = {
2276 SD2_WP_MARK,
2277};
2278/* - SDHI3 ------------------------------------------------------------------ */
2279static const unsigned int sdhi3_data1_pins[] = {
2280 /* D0 */
2281 50,
2282};
2283static const unsigned int sdhi3_data1_mux[] = {
2284 SD3_DAT0_MARK,
2285};
2286static const unsigned int sdhi3_data4_pins[] = {
2287 /* D[0:3] */
2288 50, 51, 52, 53,
2289};
2290static const unsigned int sdhi3_data4_mux[] = {
2291 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2292};
2293static const unsigned int sdhi3_ctrl_pins[] = {
2294 /* CMD, CLK */
2295 35, 34,
2296};
2297static const unsigned int sdhi3_ctrl_mux[] = {
2298 SD3_CMD_MARK, SD3_CLK_MARK,
2299};
2300static const unsigned int sdhi3_cd_pins[] = {
2301 /* CD */
2302 62,
2303};
2304static const unsigned int sdhi3_cd_mux[] = {
2305 SD3_CD_MARK,
2306};
2307static const unsigned int sdhi3_wp_pins[] = {
2308 /* WP */
2309 64,
2310};
2311static const unsigned int sdhi3_wp_mux[] = {
2312 SD3_WP_MARK,
2313};
2314/* - USB0 ------------------------------------------------------------------- */
2315static const unsigned int usb0_pins[] = {
2316 /* OVC */
2317 150, 154,
2318};
2319static const unsigned int usb0_mux[] = {
2320 USB_OVC0_MARK, USB_PENC0_MARK,
2321};
2322/* - USB1 ------------------------------------------------------------------- */
2323static const unsigned int usb1_pins[] = {
2324 /* OVC */
2325 152, 155,
2326};
2327static const unsigned int usb1_mux[] = {
2328 USB_OVC1_MARK, USB_PENC1_MARK,
2329};
2330/* - USB2 ------------------------------------------------------------------- */
2331static const unsigned int usb2_pins[] = {
2332 /* OVC, PENC */
2333 125, 156,
2334};
2335static const unsigned int usb2_mux[] = {
2336 USB_OVC2_MARK, USB_PENC2_MARK,
2337};
2338
2339static const struct sh_pfc_pin_group pinmux_groups[] = {
2340 SH_PFC_PIN_GROUP(du0_rgb666),
2341 SH_PFC_PIN_GROUP(du0_rgb888),
2342 SH_PFC_PIN_GROUP(du0_clk_0),
2343 SH_PFC_PIN_GROUP(du0_clk_1),
2344 SH_PFC_PIN_GROUP(du0_sync_0),
2345 SH_PFC_PIN_GROUP(du0_sync_1),
2346 SH_PFC_PIN_GROUP(du0_oddf),
2347 SH_PFC_PIN_GROUP(du0_cde),
2348 SH_PFC_PIN_GROUP(du1_rgb666),
2349 SH_PFC_PIN_GROUP(du1_rgb888),
2350 SH_PFC_PIN_GROUP(du1_clk),
2351 SH_PFC_PIN_GROUP(du1_sync_0),
2352 SH_PFC_PIN_GROUP(du1_sync_1),
2353 SH_PFC_PIN_GROUP(du1_oddf),
2354 SH_PFC_PIN_GROUP(du1_cde),
2355 SH_PFC_PIN_GROUP(hspi0),
2356 SH_PFC_PIN_GROUP(hspi1),
2357 SH_PFC_PIN_GROUP(hspi1_b),
2358 SH_PFC_PIN_GROUP(hspi1_c),
2359 SH_PFC_PIN_GROUP(hspi1_d),
2360 SH_PFC_PIN_GROUP(hspi2),
2361 SH_PFC_PIN_GROUP(hspi2_b),
2362 SH_PFC_PIN_GROUP(intc_irq0),
2363 SH_PFC_PIN_GROUP(intc_irq0_b),
2364 SH_PFC_PIN_GROUP(intc_irq1),
2365 SH_PFC_PIN_GROUP(intc_irq1_b),
2366 SH_PFC_PIN_GROUP(intc_irq2),
2367 SH_PFC_PIN_GROUP(intc_irq2_b),
2368 SH_PFC_PIN_GROUP(intc_irq3),
2369 SH_PFC_PIN_GROUP(intc_irq3_b),
2370 SH_PFC_PIN_GROUP(lbsc_cs0),
2371 SH_PFC_PIN_GROUP(lbsc_cs1),
2372 SH_PFC_PIN_GROUP(lbsc_ex_cs0),
2373 SH_PFC_PIN_GROUP(lbsc_ex_cs1),
2374 SH_PFC_PIN_GROUP(lbsc_ex_cs2),
2375 SH_PFC_PIN_GROUP(lbsc_ex_cs3),
2376 SH_PFC_PIN_GROUP(lbsc_ex_cs4),
2377 SH_PFC_PIN_GROUP(lbsc_ex_cs5),
2378 SH_PFC_PIN_GROUP(mmc0_data1),
2379 SH_PFC_PIN_GROUP(mmc0_data4),
2380 SH_PFC_PIN_GROUP(mmc0_data8),
2381 SH_PFC_PIN_GROUP(mmc0_ctrl),
2382 SH_PFC_PIN_GROUP(mmc1_data1),
2383 SH_PFC_PIN_GROUP(mmc1_data4),
2384 SH_PFC_PIN_GROUP(mmc1_data8),
2385 SH_PFC_PIN_GROUP(mmc1_ctrl),
2386 SH_PFC_PIN_GROUP(scif0_data),
2387 SH_PFC_PIN_GROUP(scif0_clk),
2388 SH_PFC_PIN_GROUP(scif0_ctrl),
2389 SH_PFC_PIN_GROUP(scif0_data_b),
2390 SH_PFC_PIN_GROUP(scif0_clk_b),
2391 SH_PFC_PIN_GROUP(scif0_ctrl_b),
2392 SH_PFC_PIN_GROUP(scif0_data_c),
2393 SH_PFC_PIN_GROUP(scif0_clk_c),
2394 SH_PFC_PIN_GROUP(scif0_ctrl_c),
2395 SH_PFC_PIN_GROUP(scif0_data_d),
2396 SH_PFC_PIN_GROUP(scif0_clk_d),
2397 SH_PFC_PIN_GROUP(scif0_ctrl_d),
2398 SH_PFC_PIN_GROUP(scif1_data),
2399 SH_PFC_PIN_GROUP(scif1_clk),
2400 SH_PFC_PIN_GROUP(scif1_ctrl),
2401 SH_PFC_PIN_GROUP(scif1_data_b),
2402 SH_PFC_PIN_GROUP(scif1_clk_b),
2403 SH_PFC_PIN_GROUP(scif1_ctrl_b),
2404 SH_PFC_PIN_GROUP(scif1_data_c),
2405 SH_PFC_PIN_GROUP(scif1_clk_c),
2406 SH_PFC_PIN_GROUP(scif1_ctrl_c),
2407 SH_PFC_PIN_GROUP(scif2_data),
2408 SH_PFC_PIN_GROUP(scif2_clk),
2409 SH_PFC_PIN_GROUP(scif2_data_b),
2410 SH_PFC_PIN_GROUP(scif2_clk_b),
2411 SH_PFC_PIN_GROUP(scif2_data_c),
2412 SH_PFC_PIN_GROUP(scif2_clk_c),
2413 SH_PFC_PIN_GROUP(scif2_data_d),
2414 SH_PFC_PIN_GROUP(scif2_clk_d),
2415 SH_PFC_PIN_GROUP(scif2_data_e),
2416 SH_PFC_PIN_GROUP(scif3_data),
2417 SH_PFC_PIN_GROUP(scif3_clk),
2418 SH_PFC_PIN_GROUP(scif3_data_b),
2419 SH_PFC_PIN_GROUP(scif3_data_c),
2420 SH_PFC_PIN_GROUP(scif3_data_d),
2421 SH_PFC_PIN_GROUP(scif3_data_e),
2422 SH_PFC_PIN_GROUP(scif3_clk_e),
2423 SH_PFC_PIN_GROUP(scif4_data),
2424 SH_PFC_PIN_GROUP(scif4_clk),
2425 SH_PFC_PIN_GROUP(scif4_data_b),
2426 SH_PFC_PIN_GROUP(scif4_clk_b),
2427 SH_PFC_PIN_GROUP(scif4_data_c),
2428 SH_PFC_PIN_GROUP(scif4_data_d),
2429 SH_PFC_PIN_GROUP(scif5_data),
2430 SH_PFC_PIN_GROUP(scif5_clk),
2431 SH_PFC_PIN_GROUP(scif5_data_b),
2432 SH_PFC_PIN_GROUP(scif5_clk_b),
2433 SH_PFC_PIN_GROUP(scif5_data_c),
2434 SH_PFC_PIN_GROUP(scif5_clk_c),
2435 SH_PFC_PIN_GROUP(scif5_data_d),
2436 SH_PFC_PIN_GROUP(scif5_clk_d),
2437 SH_PFC_PIN_GROUP(sdhi0_data1),
2438 SH_PFC_PIN_GROUP(sdhi0_data4),
2439 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2440 SH_PFC_PIN_GROUP(sdhi0_cd),
2441 SH_PFC_PIN_GROUP(sdhi0_wp),
2442 SH_PFC_PIN_GROUP(sdhi1_data1),
2443 SH_PFC_PIN_GROUP(sdhi1_data4),
2444 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2445 SH_PFC_PIN_GROUP(sdhi1_cd),
2446 SH_PFC_PIN_GROUP(sdhi1_wp),
2447 SH_PFC_PIN_GROUP(sdhi2_data1),
2448 SH_PFC_PIN_GROUP(sdhi2_data4),
2449 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2450 SH_PFC_PIN_GROUP(sdhi2_cd),
2451 SH_PFC_PIN_GROUP(sdhi2_wp),
2452 SH_PFC_PIN_GROUP(sdhi3_data1),
2453 SH_PFC_PIN_GROUP(sdhi3_data4),
2454 SH_PFC_PIN_GROUP(sdhi3_ctrl),
2455 SH_PFC_PIN_GROUP(sdhi3_cd),
2456 SH_PFC_PIN_GROUP(sdhi3_wp),
2457 SH_PFC_PIN_GROUP(usb0),
2458 SH_PFC_PIN_GROUP(usb1),
2459 SH_PFC_PIN_GROUP(usb2),
2460};
2461
2462static const char * const du0_groups[] = {
2463 "du0_rgb666",
2464 "du0_rgb888",
2465 "du0_clk_0",
2466 "du0_clk_1",
2467 "du0_sync_0",
2468 "du0_sync_1",
2469 "du0_oddf",
2470 "du0_cde",
2471};
2472
2473static const char * const du1_groups[] = {
2474 "du1_rgb666",
2475 "du1_rgb888",
2476 "du1_clk",
2477 "du1_sync_0",
2478 "du1_sync_1",
2479 "du1_oddf",
2480 "du1_cde",
2481};
2482
2483static const char * const hspi0_groups[] = {
2484 "hspi0",
2485};
2486
2487static const char * const hspi1_groups[] = {
2488 "hspi1",
2489 "hspi1_b",
2490 "hspi1_c",
2491 "hspi1_d",
2492};
2493
2494static const char * const hspi2_groups[] = {
2495 "hspi2",
2496 "hspi2_b",
2497};
2498
2499static const char * const intc_groups[] = {
2500 "intc_irq0",
2501 "intc_irq0_b",
2502 "intc_irq1",
2503 "intc_irq1_b",
2504 "intc_irq2",
2505 "intc_irq2_b",
2506 "intc_irq3",
2507 "intc_irq4_b",
2508};
2509
2510static const char * const lbsc_groups[] = {
2511 "lbsc_cs0",
2512 "lbsc_cs1",
2513 "lbsc_ex_cs0",
2514 "lbsc_ex_cs1",
2515 "lbsc_ex_cs2",
2516 "lbsc_ex_cs3",
2517 "lbsc_ex_cs4",
2518 "lbsc_ex_cs5",
2519};
2520
2521static const char * const mmc0_groups[] = {
2522 "mmc0_data1",
2523 "mmc0_data4",
2524 "mmc0_data8",
2525 "mmc0_ctrl",
2526};
2527
2528static const char * const mmc1_groups[] = {
2529 "mmc1_data1",
2530 "mmc1_data4",
2531 "mmc1_data8",
2532 "mmc1_ctrl",
2533};
2534
2535static const char * const scif0_groups[] = {
2536 "scif0_data",
2537 "scif0_clk",
2538 "scif0_ctrl",
2539 "scif0_data_b",
2540 "scif0_clk_b",
2541 "scif0_ctrl_b",
2542 "scif0_data_c",
2543 "scif0_clk_c",
2544 "scif0_ctrl_c",
2545 "scif0_data_d",
2546 "scif0_clk_d",
2547 "scif0_ctrl_d",
2548};
2549
2550static const char * const scif1_groups[] = {
2551 "scif1_data",
2552 "scif1_clk",
2553 "scif1_ctrl",
2554 "scif1_data_b",
2555 "scif1_clk_b",
2556 "scif1_ctrl_b",
2557 "scif1_data_c",
2558 "scif1_clk_c",
2559 "scif1_ctrl_c",
2560};
2561
2562static const char * const scif2_groups[] = {
2563 "scif2_data",
2564 "scif2_clk",
2565 "scif2_data_b",
2566 "scif2_clk_b",
2567 "scif2_data_c",
2568 "scif2_clk_c",
2569 "scif2_data_d",
2570 "scif2_clk_d",
2571 "scif2_data_e",
2572};
2573
2574static const char * const scif3_groups[] = {
2575 "scif3_data",
2576 "scif3_clk",
2577 "scif3_data_b",
2578 "scif3_data_c",
2579 "scif3_data_d",
2580 "scif3_data_e",
2581 "scif3_clk_e",
2582};
2583
2584static const char * const scif4_groups[] = {
2585 "scif4_data",
2586 "scif4_clk",
2587 "scif4_data_b",
2588 "scif4_clk_b",
2589 "scif4_data_c",
2590 "scif4_data_d",
2591};
2592
2593static const char * const scif5_groups[] = {
2594 "scif5_data",
2595 "scif5_clk",
2596 "scif5_data_b",
2597 "scif5_clk_b",
2598 "scif5_data_c",
2599 "scif5_clk_c",
2600 "scif5_data_d",
2601 "scif5_clk_d",
2602};
2603
2604static const char * const sdhi0_groups[] = {
2605 "sdhi0_data1",
2606 "sdhi0_data4",
2607 "sdhi0_ctrl",
2608 "sdhi0_cd",
2609 "sdhi0_wp",
2610};
2611
2612static const char * const sdhi1_groups[] = {
2613 "sdhi1_data1",
2614 "sdhi1_data4",
2615 "sdhi1_ctrl",
2616 "sdhi1_cd",
2617 "sdhi1_wp",
2618};
2619
2620static const char * const sdhi2_groups[] = {
2621 "sdhi2_data1",
2622 "sdhi2_data4",
2623 "sdhi2_ctrl",
2624 "sdhi2_cd",
2625 "sdhi2_wp",
2626};
2627
2628static const char * const sdhi3_groups[] = {
2629 "sdhi3_data1",
2630 "sdhi3_data4",
2631 "sdhi3_ctrl",
2632 "sdhi3_cd",
2633 "sdhi3_wp",
2634};
2635
2636static const char * const usb0_groups[] = {
2637 "usb0",
2638};
2639
2640static const char * const usb1_groups[] = {
2641 "usb1",
2642};
2643
2644static const char * const usb2_groups[] = {
2645 "usb2",
2646};
2647
2648static const struct sh_pfc_function pinmux_functions[] = {
2649 SH_PFC_FUNCTION(du0),
2650 SH_PFC_FUNCTION(du1),
2651 SH_PFC_FUNCTION(hspi0),
2652 SH_PFC_FUNCTION(hspi1),
2653 SH_PFC_FUNCTION(hspi2),
2654 SH_PFC_FUNCTION(intc),
2655 SH_PFC_FUNCTION(lbsc),
2656 SH_PFC_FUNCTION(mmc0),
2657 SH_PFC_FUNCTION(mmc1),
2658 SH_PFC_FUNCTION(sdhi0),
2659 SH_PFC_FUNCTION(sdhi1),
2660 SH_PFC_FUNCTION(sdhi2),
2661 SH_PFC_FUNCTION(sdhi3),
2662 SH_PFC_FUNCTION(scif0),
2663 SH_PFC_FUNCTION(scif1),
2664 SH_PFC_FUNCTION(scif2),
2665 SH_PFC_FUNCTION(scif3),
2666 SH_PFC_FUNCTION(scif4),
2667 SH_PFC_FUNCTION(scif5),
2668 SH_PFC_FUNCTION(usb0),
2669 SH_PFC_FUNCTION(usb1),
2670 SH_PFC_FUNCTION(usb2),
2671};
2672
2673#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
2674
2675static const struct pinmux_func pinmux_func_gpios[] = {
1455 GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18), 2676 GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18),
1456 GPIO_FN(A19), 2677 GPIO_FN(A19),
1457 2678
1458 /* IPSR0 */ 2679 /* IPSR0 */
1459 GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0), 2680 GPIO_FN(PWM1), GPIO_FN(PWMFSW0),
1460 GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2), 2681 GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS),
1461 GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), 2682 GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF),
1462 GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3), 2683 GPIO_FN(HCTS1), GPIO_FN(A0),
1463 GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D), 2684 GPIO_FN(FD3), GPIO_FN(A20),
1464 GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D), 2685 GPIO_FN(A21),
1465 GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D), 2686 GPIO_FN(A22),
1466 GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE), 2687 GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE),
1467 GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD), 2688 GPIO_FN(VI1_R1), GPIO_FN(A24),
1468 GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2), 2689 GPIO_FN(FD4), GPIO_FN(VI1_R2),
1469 GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5), 2690 GPIO_FN(SSI_WS78_B), GPIO_FN(A25),
1470 GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B), 2691 GPIO_FN(FD5), GPIO_FN(VI1_R3),
1471 GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT), 2692 GPIO_FN(SSI_SDATA7_B), GPIO_FN(CLKOUT),
1472 GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0), 2693 GPIO_FN(PWM0_B),
1473 GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2),
1474 GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0), 2694 GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0),
1475 GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C), 2695 GPIO_FN(VI1_R7), GPIO_FN(HRTS1),
1476 2696
1477 /* IPSR1 */ 2697 /* IPSR1 */
1478 GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6), 2698 GPIO_FN(FD6), GPIO_FN(FD7),
1479 GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7), 2699 GPIO_FN(FALE),
1480 GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE), 2700 GPIO_FN(ATACS00),
1481 GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD), 2701 GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4),
1482 GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B), 2702 GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B),
1483 GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B), 2703 GPIO_FN(SSI_SDATA9),
1484 GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0), 2704 GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5),
1485 GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5), 2705 GPIO_FN(HTX1),
1486 GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B), 2706 GPIO_FN(SSI_SCK9),
1487 GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1), 2707 GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6),
1488 GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6), 2708 GPIO_FN(HRX1), GPIO_FN(SSI_WS9),
1489 GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9), 2709 GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(MLB_SIG),
1490 GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG), 2710 GPIO_FN(PWM3), GPIO_FN(MLB_DAT), GPIO_FN(PWM4),
1491 GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4), 2711 GPIO_FN(HTX0), GPIO_FN(SDATA),
1492 GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA), 2712 GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
1493 GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2),
1494 GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26), 2713 GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26),
1495 GPIO_FN(CC5_STATE34), 2714 GPIO_FN(CC5_STATE34),
1496 2715
1497 /* IPSR2 */ 2716 /* IPSR2 */
1498 GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C), 2717 GPIO_FN(HRX0), GPIO_FN(SCKZ),
1499 GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11), 2718 GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11),
1500 GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35), 2719 GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35),
1501 GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5), 2720 GPIO_FN(HSCK0), GPIO_FN(MTS), GPIO_FN(PWM5),
1502 GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO), 2721 GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO),
1503 GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16), 2722 GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16),
1504 GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0), 2723 GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0),
1505 GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C), 2724 GPIO_FN(STM), GPIO_FN(PWM0_D),
1506 GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B), 2725 GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B),
1507 GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS), 2726 GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0),
1508 GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1), 2727 GPIO_FN(MDATA), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1),
1509 GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25), 2728 GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25),
1510 GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0), 2729 GPIO_FN(CC5_STATE33), GPIO_FN(LCDOUT0),
1511 GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0), 2730 GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0),
1512 GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0), 2731 GPIO_FN(LCDOUT1), GPIO_FN(DACK0),
1513 GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C), 2732 GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1),
1514 GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3), 2733 GPIO_FN(LCDOUT2), GPIO_FN(LCDOUT3),
1515 GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5), 2734 GPIO_FN(LCDOUT4), GPIO_FN(LCDOUT5),
1516 GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7), 2735 GPIO_FN(LCDOUT6), GPIO_FN(LCDOUT7),
1517 GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2), 2736 GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2),
1518 GPIO_FN(AUDATA2), 2737 GPIO_FN(AUDATA2),
1519 2738
1520 /* IPSR3 */ 2739 /* IPSR3 */
1521 GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2), 2740 GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2),
1522 GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10), 2741 GPIO_FN(AUDATA3), GPIO_FN(LCDOUT10),
1523 GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4), 2742 GPIO_FN(LCDOUT11),
1524 GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13), 2743 GPIO_FN(LCDOUT12), GPIO_FN(LCDOUT13),
1525 GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7), 2744 GPIO_FN(LCDOUT14),
1526 GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16), 2745 GPIO_FN(LCDOUT15), GPIO_FN(LCDOUT16),
1527 GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4), 2746 GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4),
1528 GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1), 2747 GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1),
1529 GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C), 2748 GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5),
1530 GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3), 2749 GPIO_FN(LCDOUT18),
1531 GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20), 2750 GPIO_FN(LCDOUT19), GPIO_FN(LCDOUT20),
1532 GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6), 2751 GPIO_FN(LCDOUT21),
1533 GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23), 2752 GPIO_FN(LCDOUT22), GPIO_FN(LCDOUT23),
1534 GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D), 2753 GPIO_FN(QSTVA_QVS),
1535 GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK), 2754 GPIO_FN(SCL3_B), GPIO_FN(QCLK),
1536 GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D), 2755 GPIO_FN(QSTVB_QVE),
1537 GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B), 2756 GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
1538 GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS), 2757 GPIO_FN(QSTH_QHS),
1539 GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE), 2758 GPIO_FN(QSTB_QHE),
1540 GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE), 2759 GPIO_FN(QCPV_QDE),
1541 GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON), 2760 GPIO_FN(CAN1_TX), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
1542 2761
1543 /* IPSR4 */ 2762 /* IPSR4 */
1544 GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C), 2763 GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C),
1545 GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C), 2764 GPIO_FN(QPOLB), GPIO_FN(CAN1_RX),
1546 GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B), 2765 GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B),
1547 GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6), 2766 GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6),
1548 GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK), 2767 GPIO_FN(AUDCK),
1549 GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1), 2768 GPIO_FN(PWMFSW0_B), GPIO_FN(VI2_DATA1_VI2_B1),
1550 GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E), 2769 GPIO_FN(PWM0),
1551 GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0), 2770 GPIO_FN(AUDSYNC), GPIO_FN(VI2_G0),
1552 GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2), 2771 GPIO_FN(VI2_G1), GPIO_FN(VI2_G2),
1553 GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4), 2772 GPIO_FN(VI2_G3), GPIO_FN(VI2_G4),
1554 GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0), 2773 GPIO_FN(VI2_G5),
1555 GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2), 2774 GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B),
1556 GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1), 2775 GPIO_FN(AUDATA6),
1557 GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3), 2776 GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B),
1558 GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2), 2777 GPIO_FN(AUDATA7),
1559 GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4), 2778 GPIO_FN(VI2_G6), GPIO_FN(VI2_G7),
1560 GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6), 2779 GPIO_FN(VI2_R0), GPIO_FN(VI2_R1),
1561 GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0), 2780 GPIO_FN(VI2_R2), GPIO_FN(VI2_R3),
1562 GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0), 2781 GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B),
1563 GPIO_FN(TX5), GPIO_FN(SCK0_D),
1564 2782
1565 /* IPSR5 */ 2783 /* IPSR5 */
1566 GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B), 2784 GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B),
1567 GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D), 2785 GPIO_FN(VI2_R4), GPIO_FN(VI2_R5),
1568 GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5), 2786 GPIO_FN(VI2_R6), GPIO_FN(VI2_R7),
1569 GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7), 2787 GPIO_FN(SCL2_D), GPIO_FN(SDA2_D),
1570 GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D), 2788 GPIO_FN(VI2_CLKENB),
1571 GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1), 2789 GPIO_FN(SCL1_D), GPIO_FN(VI2_FIELD),
1572 GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD), 2790 GPIO_FN(SDA1_D), GPIO_FN(VI2_HSYNC),
1573 GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC), 2791 GPIO_FN(VI3_HSYNC), GPIO_FN(VI2_VSYNC),
1574 GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC), 2792 GPIO_FN(VI3_VSYNC),
1575 GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), 2793 GPIO_FN(VI2_CLK),
1576 GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD), 2794 GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
1577 GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB), 2795 GPIO_FN(AUDIO_CLKC), GPIO_FN(SPEEDIN),
1578 GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN), 2796 GPIO_FN(GPS_SIGN_D), GPIO_FN(VI2_DATA6_VI2_B6),
1579 GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6), 2797 GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B),
1580 GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1), 2798 GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
1581 GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D), 2799 GPIO_FN(VI2_DATA7_VI2_B7),
1582 GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B), 2800 GPIO_FN(VI1_FIELD),
1583 GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD), 2801 GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT),
1584 GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
1585 GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA), 2802 GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
1586 GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2), 2803 GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB),
1587 GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0), 2804 GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
1588 2805
1589 /* IPSR6 */ 2806 /* IPSR6 */
@@ -1599,89 +2816,87 @@ static struct pinmux_gpio pinmux_gpios[] = {
1599 GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B), 2816 GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
1600 GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9), 2817 GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
1601 GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK), 2818 GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
1602 GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D), 2819 GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(TCLK0_D),
1603 GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11), 2820 GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
1604 GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA), 2821 GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
1605 GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6), 2822 GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6),
1606 GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B), 2823 GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
1607 2824
1608 /* IPSR7 */ 2825 /* IPSR7 */
1609 GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B), 2826 GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B),
1610 GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK), 2827 GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK),
1611 GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13), 2828 GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13),
1612 GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C), 2829 GPIO_FN(SSI_SCK9_B),
1613 GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B), 2830 GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14),
1614 GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7), 2831 GPIO_FN(SSI_WS9_B), GPIO_FN(SSI_SDATA7),
1615 GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C), 2832 GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(TCLK1_C),
1616 GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP), 2833 GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
1617 GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK), 2834 GPIO_FN(ATACS01), GPIO_FN(ATACS11),
1618 GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11), 2835 GPIO_FN(CC5_TDO), GPIO_FN(ATADIR1),
1619 GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1), 2836 GPIO_FN(CC5_TRST), GPIO_FN(ATAG1),
1620 GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1), 2837 GPIO_FN(CC5_TMS), GPIO_FN(ATARD1),
1621 GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1), 2838 GPIO_FN(CC5_TCK), GPIO_FN(ATAWR1),
1622 GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1), 2839 GPIO_FN(CC5_TDI), GPIO_FN(DREQ2),
1623 GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2), 2840 GPIO_FN(DACK2),
1624 GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
1625 GPIO_FN(CTS1_B),
1626 2841
1627 /* IPSR8 */ 2842 /* IPSR8 */
1628 GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK), 2843 GPIO_FN(AD_CLK),
1629 GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20), 2844 GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20),
1630 GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0), 2845 GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36),
1631 GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI), 2846 GPIO_FN(AD_DI),
1632 GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21), 2847 GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21),
1633 GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0), 2848 GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37),
1634 GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO), 2849 GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO),
1635 GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22), 2850 GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22),
1636 GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0), 2851 GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38),
1637 GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7), 2852 GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
1638 GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31), 2853 GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
1639 GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE), 2854 GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
1640 GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA), 2855 GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
1641 GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB), 2856 GPIO_FN(VI0_CLK), GPIO_FN(VI0_CLKENB),
1642 GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC), 2857 GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
1643 GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B), 2858 GPIO_FN(VI0_FIELD), GPIO_FN(HRX1_B),
1644 GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C), 2859 GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B),
1645 GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B), 2860 GPIO_FN(HSCK1_B),
1646 GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B), 2861 GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
1647 GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C), 2862 GPIO_FN(PWMFSW0_C),
1648 2863
1649 /* IPSR9 */ 2864 /* IPSR9 */
1650 GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO), 2865 GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO),
1651 GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM), 2866 GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM),
1652 GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3), 2867 GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(VI0_DATA3_VI0_B3),
1653 GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2), 2868 GPIO_FN(VI0_DATA4_VI0_B4),
1654 GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6), 2869 GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(VI0_DATA6_VI0_B6),
1655 GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7), 2870 GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7),
1656 GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0), 2871 GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0),
1657 GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2), 2872 GPIO_FN(SSI_SCK78_C), GPIO_FN(ARM_TRACEDATA_2),
1658 GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1), 2873 GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C),
1659 GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1), 2874 GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
1660 GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0), 2875 GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
1661 GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7), 2876 GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV),
1662 GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4), 2877 GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
1663 GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6), 2878 GPIO_FN(ETH_TX_EN), GPIO_FN(ARM_TRACEDATA_6),
1664 GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B), 2879 GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER),
1665 GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0), 2880 GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
1666 GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7), 2881 GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
1667 GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9), 2882 GPIO_FN(ETH_RXD1), GPIO_FN(ARM_TRACEDATA_9),
1668 2883
1669 /* IPSR10 */ 2884 /* IPSR10 */
1670 GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C), 2885 GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C),
1671 GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C), 2886 GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C),
1672 GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B), 2887 GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B),
1673 GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C), 2888 GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C),
1674 GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2), 2889 GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK),
1675 GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC), 2890 GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
1676 GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13), 2891 GPIO_FN(ARM_TRACEDATA_13),
1677 GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B), 2892 GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK),
1678 GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK), 2893 GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
1679 GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0), 2894 GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
1680 GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15), 2895 GPIO_FN(ARM_TRACEDATA_15),
1681 GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC), 2896 GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
1682 GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK), 2897 GPIO_FN(DREQ2_C), GPIO_FN(TRACECLK),
1683 GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7), 2898 GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
1684 GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B), 2899 GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C),
1685 GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN), 2900 GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
1686 GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC), 2901 GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
1687 GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C), 2902 GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
@@ -1690,40 +2905,40 @@ static struct pinmux_gpio pinmux_gpios[] = {
1690 GPIO_FN(SPV_TRST), GPIO_FN(SCL3), 2905 GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
1691 2906
1692 /* IPSR11 */ 2907 /* IPSR11 */
1693 GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST), 2908 GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SIM_RST),
1694 GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1), 2909 GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1),
1695 GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS), 2910 GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS),
1696 GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2), 2911 GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2),
1697 GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B), 2912 GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B),
1698 GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN), 2913 GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(MT0_BEN),
1699 GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4), 2914 GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
1700 GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST), 2915 GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
1701 GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5), 2916 GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
1702 GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK), 2917 GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
1703 GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6), 2918 GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
1704 GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS), 2919 GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
1705 GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP), 2920 GPIO_FN(VI1_DATA7_VI1_B7),
1706 GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D), 2921 GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI),
1707 GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1), 2922 GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0),
1708 GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO), 2923 GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(SPA_TDO),
1709 GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1), 2924 GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
1710 GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2), 2925 GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B),
1711 GPIO_FN(HRTS0_B), 2926 GPIO_FN(HRTS0_B),
1712 2927
1713 /* IPSR12 */ 2928 /* IPSR12 */
1714 GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1), 2929 GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1),
1715 GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3), 2930 GPIO_FN(TS_SPSYNC1), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3),
1716 GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1), 2931 GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1),
1717 GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4), 2932 GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4),
1718 GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B), 2933 GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B),
1719 GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5), 2934 GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5),
1720 GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B), 2935 GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(SIM_D_B),
1721 GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB), 2936 GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB),
1722 GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7), 2937 GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7),
1723 GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B), 2938 GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE),
1724}; 2939};
1725 2940
1726static struct pinmux_cfg_reg pinmux_config_regs[] = { 2941static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1727 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { 2942 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
1728 GP_0_31_FN, FN_IP3_31_29, 2943 GP_0_31_FN, FN_IP3_31_29,
1729 GP_0_30_FN, FN_IP3_26_24, 2944 GP_0_30_FN, FN_IP3_26_24,
@@ -2412,7 +3627,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2412 FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1, 3627 FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
2413 FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0, 3628 FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
2414 /* IP11_26_24 [3] */ 3629 /* IP11_26_24 [3] */
2415 FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1, 3630 FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
2416 FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B, 3631 FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
2417 /* IP11_23_21 [3] */ 3632 /* IP11_23_21 [3] */
2418 FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI, 3633 FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
@@ -2584,7 +3799,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2584 { }, 3799 { },
2585}; 3800};
2586 3801
2587static struct pinmux_data_reg pinmux_data_regs[] = { 3802static const struct pinmux_data_reg pinmux_data_regs[] = {
2588 { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } }, 3803 { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
2589 { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } }, 3804 { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
2590 { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } }, 3805 { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
@@ -2600,22 +3815,25 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2600 { }, 3815 { },
2601}; 3816};
2602 3817
2603struct sh_pfc_soc_info r8a7779_pinmux_info = { 3818const struct sh_pfc_soc_info r8a7779_pinmux_info = {
2604 .name = "r8a7779_pfc", 3819 .name = "r8a7779_pfc",
2605 3820
2606 .unlock_reg = 0xfffc0000, /* PMMR */ 3821 .unlock_reg = 0xfffc0000, /* PMMR */
2607 3822
2608 .reserved_id = PINMUX_RESERVED,
2609 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2610 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 3823 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2611 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 3824 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2612 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2613 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 3825 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2614 3826
2615 .first_gpio = GPIO_GP_0_0, 3827 .pins = pinmux_pins,
2616 .last_gpio = GPIO_FN_SCK4_B, 3828 .nr_pins = ARRAY_SIZE(pinmux_pins),
3829 .groups = pinmux_groups,
3830 .nr_groups = ARRAY_SIZE(pinmux_groups),
3831 .functions = pinmux_functions,
3832 .nr_functions = ARRAY_SIZE(pinmux_functions),
3833
3834 .func_gpios = pinmux_func_gpios,
3835 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2617 3836
2618 .gpios = pinmux_gpios,
2619 .cfg_regs = pinmux_config_regs, 3837 .cfg_regs = pinmux_config_regs,
2620 .data_regs = pinmux_data_regs, 3838 .data_regs = pinmux_data_regs,
2621 3839
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index 01b425dfd162..f63d51dc3f4c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -272,7 +272,7 @@ enum {
272 PINMUX_MARK_END, 272 PINMUX_MARK_END,
273}; 273};
274 274
275static pinmux_enum_t pinmux_data[] = { 275static const pinmux_enum_t pinmux_data[] = {
276 276
277 /* PA */ 277 /* PA */
278 PINMUX_DATA(PA7_DATA, PA7_IN), 278 PINMUX_DATA(PA7_DATA, PA7_IN),
@@ -703,7 +703,7 @@ static pinmux_enum_t pinmux_data[] = {
703 PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11), 703 PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11),
704}; 704};
705 705
706static struct pinmux_gpio pinmux_gpios[] = { 706static struct sh_pfc_pin pinmux_pins[] = {
707 707
708 /* PA */ 708 /* PA */
709 PINMUX_GPIO(GPIO_PA7, PA7_DATA), 709 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
@@ -815,265 +815,269 @@ static struct pinmux_gpio pinmux_gpios[] = {
815 PINMUX_GPIO(GPIO_PF2, PF2_DATA), 815 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
816 PINMUX_GPIO(GPIO_PF1, PF1_DATA), 816 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
817 PINMUX_GPIO(GPIO_PF0, PF0_DATA), 817 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
818};
819
820#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
818 821
822static const struct pinmux_func pinmux_func_gpios[] = {
819 /* INTC */ 823 /* INTC */
820 PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK), 824 GPIO_FN(PINT7_PB),
821 PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK), 825 GPIO_FN(PINT6_PB),
822 PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK), 826 GPIO_FN(PINT5_PB),
823 PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK), 827 GPIO_FN(PINT4_PB),
824 PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK), 828 GPIO_FN(PINT3_PB),
825 PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK), 829 GPIO_FN(PINT2_PB),
826 PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK), 830 GPIO_FN(PINT1_PB),
827 PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK), 831 GPIO_FN(PINT0_PB),
828 PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK), 832 GPIO_FN(PINT7_PD),
829 PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK), 833 GPIO_FN(PINT6_PD),
830 PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK), 834 GPIO_FN(PINT5_PD),
831 PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK), 835 GPIO_FN(PINT4_PD),
832 PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK), 836 GPIO_FN(PINT3_PD),
833 PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK), 837 GPIO_FN(PINT2_PD),
834 PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK), 838 GPIO_FN(PINT1_PD),
835 PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK), 839 GPIO_FN(PINT0_PD),
836 PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK), 840 GPIO_FN(IRQ7_PB),
837 PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK), 841 GPIO_FN(IRQ6_PB),
838 PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK), 842 GPIO_FN(IRQ5_PB),
839 PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK), 843 GPIO_FN(IRQ4_PB),
840 PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK), 844 GPIO_FN(IRQ3_PB),
841 PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK), 845 GPIO_FN(IRQ2_PB),
842 PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK), 846 GPIO_FN(IRQ1_PB),
843 PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK), 847 GPIO_FN(IRQ0_PB),
844 PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK), 848 GPIO_FN(IRQ7_PD),
845 PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK), 849 GPIO_FN(IRQ6_PD),
846 PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK), 850 GPIO_FN(IRQ5_PD),
847 PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK), 851 GPIO_FN(IRQ4_PD),
848 PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK), 852 GPIO_FN(IRQ3_PD),
849 PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK), 853 GPIO_FN(IRQ2_PD),
850 PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK), 854 GPIO_FN(IRQ1_PD),
851 PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK), 855 GPIO_FN(IRQ0_PD),
852 PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK), 856 GPIO_FN(IRQ7_PE),
853 PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK), 857 GPIO_FN(IRQ6_PE),
854 PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK), 858 GPIO_FN(IRQ5_PE),
855 PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK), 859 GPIO_FN(IRQ4_PE),
856 PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), 860 GPIO_FN(IRQ3_PE),
857 PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), 861 GPIO_FN(IRQ2_PE),
858 PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), 862 GPIO_FN(IRQ1_PE),
859 PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), 863 GPIO_FN(IRQ0_PE),
860 864
861 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), 865 GPIO_FN(WDTOVF),
862 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), 866 GPIO_FN(IRQOUT),
863 PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), 867 GPIO_FN(REFOUT),
864 PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK), 868 GPIO_FN(IRQOUT_REFOUT),
865 PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK), 869 GPIO_FN(UBCTRG),
866 870
867 /* CAN */ 871 /* CAN */
868 PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), 872 GPIO_FN(CTX1),
869 PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), 873 GPIO_FN(CRX1),
870 PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), 874 GPIO_FN(CTX0),
871 PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK), 875 GPIO_FN(CTX0_CTX1),
872 PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), 876 GPIO_FN(CRX0),
873 PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), 877 GPIO_FN(CRX0_CRX1),
874 878
875 /* IIC3 */ 879 /* IIC3 */
876 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), 880 GPIO_FN(SDA3),
877 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), 881 GPIO_FN(SCL3),
878 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), 882 GPIO_FN(SDA2),
879 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), 883 GPIO_FN(SCL2),
880 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), 884 GPIO_FN(SDA1),
881 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), 885 GPIO_FN(SCL1),
882 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), 886 GPIO_FN(SDA0),
883 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), 887 GPIO_FN(SCL0),
884 888
885 /* DMAC */ 889 /* DMAC */
886 PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK), 890 GPIO_FN(TEND0_PD),
887 PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK), 891 GPIO_FN(TEND0_PE),
888 PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK), 892 GPIO_FN(DACK0_PD),
889 PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK), 893 GPIO_FN(DACK0_PE),
890 PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK), 894 GPIO_FN(DREQ0_PD),
891 PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK), 895 GPIO_FN(DREQ0_PE),
892 PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK), 896 GPIO_FN(TEND1_PD),
893 PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK), 897 GPIO_FN(TEND1_PE),
894 PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK), 898 GPIO_FN(DACK1_PD),
895 PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK), 899 GPIO_FN(DACK1_PE),
896 PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK), 900 GPIO_FN(DREQ1_PD),
897 PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK), 901 GPIO_FN(DREQ1_PE),
898 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), 902 GPIO_FN(DACK2),
899 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), 903 GPIO_FN(DREQ2),
900 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), 904 GPIO_FN(DACK3),
901 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), 905 GPIO_FN(DREQ3),
902 906
903 /* ADC */ 907 /* ADC */
904 PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK), 908 GPIO_FN(ADTRG_PD),
905 PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK), 909 GPIO_FN(ADTRG_PE),
906 910
907 /* BSC */ 911 /* BSC */
908 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 912 GPIO_FN(D31),
909 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 913 GPIO_FN(D30),
910 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 914 GPIO_FN(D29),
911 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 915 GPIO_FN(D28),
912 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 916 GPIO_FN(D27),
913 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 917 GPIO_FN(D26),
914 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 918 GPIO_FN(D25),
915 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 919 GPIO_FN(D24),
916 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 920 GPIO_FN(D23),
917 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 921 GPIO_FN(D22),
918 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 922 GPIO_FN(D21),
919 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 923 GPIO_FN(D20),
920 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 924 GPIO_FN(D19),
921 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 925 GPIO_FN(D18),
922 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 926 GPIO_FN(D17),
923 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 927 GPIO_FN(D16),
924 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 928 GPIO_FN(A25),
925 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 929 GPIO_FN(A24),
926 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 930 GPIO_FN(A23),
927 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 931 GPIO_FN(A22),
928 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 932 GPIO_FN(A21),
929 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), 933 GPIO_FN(CS4),
930 PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK), 934 GPIO_FN(MRES),
931 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 935 GPIO_FN(BS),
932 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 936 GPIO_FN(IOIS16),
933 PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), 937 GPIO_FN(CS1),
934 PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK), 938 GPIO_FN(CS6_CE1B),
935 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 939 GPIO_FN(CE2B),
936 PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK), 940 GPIO_FN(CS5_CE1A),
937 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 941 GPIO_FN(CE2A),
938 PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK), 942 GPIO_FN(FRAME),
939 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 943 GPIO_FN(WAIT),
940 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), 944 GPIO_FN(RDWR),
941 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), 945 GPIO_FN(CKE),
942 PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK), 946 GPIO_FN(CASU),
943 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), 947 GPIO_FN(BREQ),
944 PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK), 948 GPIO_FN(RASU),
945 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), 949 GPIO_FN(BACK),
946 PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK), 950 GPIO_FN(CASL),
947 PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK), 951 GPIO_FN(RASL),
948 PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK), 952 GPIO_FN(WE3_DQMUU_AH_ICIO_WR),
949 PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK), 953 GPIO_FN(WE2_DQMUL_ICIORD),
950 PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK), 954 GPIO_FN(WE1_DQMLU_WE),
951 PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK), 955 GPIO_FN(WE0_DQMLL),
952 PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), 956 GPIO_FN(CS3),
953 PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), 957 GPIO_FN(CS2),
954 PINMUX_GPIO(GPIO_FN_A1, A1_MARK), 958 GPIO_FN(A1),
955 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 959 GPIO_FN(A0),
956 PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK), 960 GPIO_FN(CS7),
957 961
958 /* TMU */ 962 /* TMU */
959 PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), 963 GPIO_FN(TIOC4D),
960 PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), 964 GPIO_FN(TIOC4C),
961 PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), 965 GPIO_FN(TIOC4B),
962 PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), 966 GPIO_FN(TIOC4A),
963 PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), 967 GPIO_FN(TIOC3D),
964 PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), 968 GPIO_FN(TIOC3C),
965 PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), 969 GPIO_FN(TIOC3B),
966 PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), 970 GPIO_FN(TIOC3A),
967 PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), 971 GPIO_FN(TIOC2B),
968 PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), 972 GPIO_FN(TIOC1B),
969 PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), 973 GPIO_FN(TIOC2A),
970 PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), 974 GPIO_FN(TIOC1A),
971 PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), 975 GPIO_FN(TIOC0D),
972 PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), 976 GPIO_FN(TIOC0C),
973 PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), 977 GPIO_FN(TIOC0B),
974 PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), 978 GPIO_FN(TIOC0A),
975 PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK), 979 GPIO_FN(TCLKD_PD),
976 PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK), 980 GPIO_FN(TCLKC_PD),
977 PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK), 981 GPIO_FN(TCLKB_PD),
978 PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK), 982 GPIO_FN(TCLKA_PD),
979 PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK), 983 GPIO_FN(TCLKD_PF),
980 PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK), 984 GPIO_FN(TCLKC_PF),
981 PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK), 985 GPIO_FN(TCLKB_PF),
982 PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK), 986 GPIO_FN(TCLKA_PF),
983 987
984 /* SSU */ 988 /* SSU */
985 PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK), 989 GPIO_FN(SCS0_PD),
986 PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK), 990 GPIO_FN(SSO0_PD),
987 PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK), 991 GPIO_FN(SSI0_PD),
988 PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK), 992 GPIO_FN(SSCK0_PD),
989 PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK), 993 GPIO_FN(SCS0_PF),
990 PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK), 994 GPIO_FN(SSO0_PF),
991 PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK), 995 GPIO_FN(SSI0_PF),
992 PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK), 996 GPIO_FN(SSCK0_PF),
993 PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK), 997 GPIO_FN(SCS1_PD),
994 PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK), 998 GPIO_FN(SSO1_PD),
995 PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK), 999 GPIO_FN(SSI1_PD),
996 PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK), 1000 GPIO_FN(SSCK1_PD),
997 PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK), 1001 GPIO_FN(SCS1_PF),
998 PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK), 1002 GPIO_FN(SSO1_PF),
999 PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK), 1003 GPIO_FN(SSI1_PF),
1000 PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK), 1004 GPIO_FN(SSCK1_PF),
1001 1005
1002 /* SCIF */ 1006 /* SCIF */
1003 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), 1007 GPIO_FN(TXD0),
1004 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), 1008 GPIO_FN(RXD0),
1005 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), 1009 GPIO_FN(SCK0),
1006 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), 1010 GPIO_FN(TXD1),
1007 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), 1011 GPIO_FN(RXD1),
1008 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), 1012 GPIO_FN(SCK1),
1009 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 1013 GPIO_FN(TXD2),
1010 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 1014 GPIO_FN(RXD2),
1011 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 1015 GPIO_FN(SCK2),
1012 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), 1016 GPIO_FN(RTS3),
1013 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), 1017 GPIO_FN(CTS3),
1014 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 1018 GPIO_FN(TXD3),
1015 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 1019 GPIO_FN(RXD3),
1016 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), 1020 GPIO_FN(SCK3),
1017 1021
1018 /* SSI */ 1022 /* SSI */
1019 PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), 1023 GPIO_FN(AUDIO_CLK),
1020 PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), 1024 GPIO_FN(SSIDATA3),
1021 PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), 1025 GPIO_FN(SSIWS3),
1022 PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), 1026 GPIO_FN(SSISCK3),
1023 PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), 1027 GPIO_FN(SSIDATA2),
1024 PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), 1028 GPIO_FN(SSIWS2),
1025 PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), 1029 GPIO_FN(SSISCK2),
1026 PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), 1030 GPIO_FN(SSIDATA1),
1027 PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), 1031 GPIO_FN(SSIWS1),
1028 PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), 1032 GPIO_FN(SSISCK1),
1029 PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK), 1033 GPIO_FN(SSIDATA0),
1030 PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), 1034 GPIO_FN(SSIWS0),
1031 PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), 1035 GPIO_FN(SSISCK0),
1032 1036
1033 /* FLCTL */ 1037 /* FLCTL */
1034 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 1038 GPIO_FN(FCE),
1035 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 1039 GPIO_FN(FRB),
1036 PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), 1040 GPIO_FN(NAF7),
1037 PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), 1041 GPIO_FN(NAF6),
1038 PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), 1042 GPIO_FN(NAF5),
1039 PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), 1043 GPIO_FN(NAF4),
1040 PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), 1044 GPIO_FN(NAF3),
1041 PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), 1045 GPIO_FN(NAF2),
1042 PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), 1046 GPIO_FN(NAF1),
1043 PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), 1047 GPIO_FN(NAF0),
1044 PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), 1048 GPIO_FN(FSC),
1045 PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), 1049 GPIO_FN(FOE),
1046 PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), 1050 GPIO_FN(FCDE),
1047 PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), 1051 GPIO_FN(FWE),
1048 1052
1049 /* LCDC */ 1053 /* LCDC */
1050 PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), 1054 GPIO_FN(LCD_VEPWC),
1051 PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), 1055 GPIO_FN(LCD_VCPWC),
1052 PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), 1056 GPIO_FN(LCD_CLK),
1053 PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), 1057 GPIO_FN(LCD_FLM),
1054 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), 1058 GPIO_FN(LCD_M_DISP),
1055 PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), 1059 GPIO_FN(LCD_CL2),
1056 PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), 1060 GPIO_FN(LCD_CL1),
1057 PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), 1061 GPIO_FN(LCD_DON),
1058 PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), 1062 GPIO_FN(LCD_DATA15),
1059 PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), 1063 GPIO_FN(LCD_DATA14),
1060 PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), 1064 GPIO_FN(LCD_DATA13),
1061 PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), 1065 GPIO_FN(LCD_DATA12),
1062 PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), 1066 GPIO_FN(LCD_DATA11),
1063 PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), 1067 GPIO_FN(LCD_DATA10),
1064 PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), 1068 GPIO_FN(LCD_DATA9),
1065 PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), 1069 GPIO_FN(LCD_DATA8),
1066 PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), 1070 GPIO_FN(LCD_DATA7),
1067 PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), 1071 GPIO_FN(LCD_DATA6),
1068 PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), 1072 GPIO_FN(LCD_DATA5),
1069 PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), 1073 GPIO_FN(LCD_DATA4),
1070 PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), 1074 GPIO_FN(LCD_DATA3),
1071 PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), 1075 GPIO_FN(LCD_DATA2),
1072 PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), 1076 GPIO_FN(LCD_DATA1),
1073 PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), 1077 GPIO_FN(LCD_DATA0),
1074}; 1078};
1075 1079
1076static struct pinmux_cfg_reg pinmux_config_regs[] = { 1080static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1077 { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) { 1081 { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) {
1078 0, 0, 1082 0, 0,
1079 0, 0, 1083 0, 0,
@@ -1525,7 +1529,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1525 {} 1529 {}
1526}; 1530};
1527 1531
1528static struct pinmux_data_reg pinmux_data_regs[] = { 1532static const struct pinmux_data_reg pinmux_data_regs[] = {
1529 { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) { 1533 { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) {
1530 0, 0, 0, 0, 1534 0, 0, 0, 0,
1531 0, 0, 0, 0, 1535 0, 0, 0, 0,
@@ -1571,19 +1575,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1571 { }, 1575 { },
1572}; 1576};
1573 1577
1574struct sh_pfc_soc_info sh7203_pinmux_info = { 1578const struct sh_pfc_soc_info sh7203_pinmux_info = {
1575 .name = "sh7203_pfc", 1579 .name = "sh7203_pfc",
1576 .reserved_id = PINMUX_RESERVED,
1577 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1578 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, 1580 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
1579 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, 1581 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
1580 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1581 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1582 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1582 1583
1583 .first_gpio = GPIO_PA7, 1584 .pins = pinmux_pins,
1584 .last_gpio = GPIO_FN_LCD_DATA0, 1585 .nr_pins = ARRAY_SIZE(pinmux_pins),
1586 .func_gpios = pinmux_func_gpios,
1587 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1585 1588
1586 .gpios = pinmux_gpios,
1587 .cfg_regs = pinmux_config_regs, 1589 .cfg_regs = pinmux_config_regs,
1588 .data_regs = pinmux_data_regs, 1590 .data_regs = pinmux_data_regs,
1589 1591
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index 2ba5639dcf34..284675249ed9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -604,7 +604,7 @@ enum {
604 PINMUX_MARK_END, 604 PINMUX_MARK_END,
605}; 605};
606 606
607static pinmux_enum_t pinmux_data[] = { 607static const pinmux_enum_t pinmux_data[] = {
608 608
609 /* Port A */ 609 /* Port A */
610 PINMUX_DATA(PA3_DATA, PA3_IN), 610 PINMUX_DATA(PA3_DATA, PA3_IN),
@@ -1072,7 +1072,7 @@ static pinmux_enum_t pinmux_data[] = {
1072 PINMUX_DATA(SD_D2_MARK, PK0MD_10), 1072 PINMUX_DATA(SD_D2_MARK, PK0MD_10),
1073}; 1073};
1074 1074
1075static struct pinmux_gpio pinmux_gpios[] = { 1075static struct sh_pfc_pin pinmux_pins[] = {
1076 1076
1077 /* Port A */ 1077 /* Port A */
1078 PINMUX_GPIO(GPIO_PA3, PA3_DATA), 1078 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
@@ -1216,257 +1216,261 @@ static struct pinmux_gpio pinmux_gpios[] = {
1216 PINMUX_GPIO(GPIO_PK2, PK2_DATA), 1216 PINMUX_GPIO(GPIO_PK2, PK2_DATA),
1217 PINMUX_GPIO(GPIO_PK1, PK1_DATA), 1217 PINMUX_GPIO(GPIO_PK1, PK1_DATA),
1218 PINMUX_GPIO(GPIO_PK0, PK0_DATA), 1218 PINMUX_GPIO(GPIO_PK0, PK0_DATA),
1219};
1220
1221#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1219 1222
1223static const struct pinmux_func pinmux_func_gpios[] = {
1220 /* INTC */ 1224 /* INTC */
1221 PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), 1225 GPIO_FN(PINT7_PG),
1222 PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), 1226 GPIO_FN(PINT6_PG),
1223 PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), 1227 GPIO_FN(PINT5_PG),
1224 PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), 1228 GPIO_FN(PINT4_PG),
1225 PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), 1229 GPIO_FN(PINT3_PG),
1226 PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), 1230 GPIO_FN(PINT2_PG),
1227 PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), 1231 GPIO_FN(PINT1_PG),
1228 1232
1229 PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK), 1233 GPIO_FN(IRQ7_PC),
1230 PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK), 1234 GPIO_FN(IRQ6_PC),
1231 PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK), 1235 GPIO_FN(IRQ5_PC),
1232 PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK), 1236 GPIO_FN(IRQ4_PC),
1233 PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), 1237 GPIO_FN(IRQ3_PG),
1234 PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), 1238 GPIO_FN(IRQ2_PG),
1235 PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), 1239 GPIO_FN(IRQ1_PJ),
1236 PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), 1240 GPIO_FN(IRQ0_PJ),
1237 PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), 1241 GPIO_FN(IRQ3_PE),
1238 PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), 1242 GPIO_FN(IRQ2_PE),
1239 PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), 1243 GPIO_FN(IRQ1_PE),
1240 PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), 1244 GPIO_FN(IRQ0_PE),
1241 1245
1242 /* WDT */ 1246 /* WDT */
1243 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), 1247 GPIO_FN(WDTOVF),
1244 1248
1245 /* CAN */ 1249 /* CAN */
1246 PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), 1250 GPIO_FN(CTX1),
1247 PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), 1251 GPIO_FN(CRX1),
1248 PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), 1252 GPIO_FN(CTX0),
1249 PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), 1253 GPIO_FN(CRX0),
1250 PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), 1254 GPIO_FN(CRX0_CRX1),
1251 1255
1252 /* DMAC */ 1256 /* DMAC */
1253 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), 1257 GPIO_FN(TEND0),
1254 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 1258 GPIO_FN(DACK0),
1255 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 1259 GPIO_FN(DREQ0),
1256 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), 1260 GPIO_FN(TEND1),
1257 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 1261 GPIO_FN(DACK1),
1258 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 1262 GPIO_FN(DREQ1),
1259 1263
1260 /* ADC */ 1264 /* ADC */
1261 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), 1265 GPIO_FN(ADTRG),
1262 1266
1263 /* BSCh */ 1267 /* BSCh */
1264 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1268 GPIO_FN(A25),
1265 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1269 GPIO_FN(A24),
1266 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1270 GPIO_FN(A23),
1267 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1271 GPIO_FN(A22),
1268 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 1272 GPIO_FN(A21),
1269 PINMUX_GPIO(GPIO_FN_A20, A20_MARK), 1273 GPIO_FN(A20),
1270 PINMUX_GPIO(GPIO_FN_A19, A19_MARK), 1274 GPIO_FN(A19),
1271 PINMUX_GPIO(GPIO_FN_A18, A18_MARK), 1275 GPIO_FN(A18),
1272 PINMUX_GPIO(GPIO_FN_A17, A17_MARK), 1276 GPIO_FN(A17),
1273 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1277 GPIO_FN(A16),
1274 PINMUX_GPIO(GPIO_FN_A15, A15_MARK), 1278 GPIO_FN(A15),
1275 PINMUX_GPIO(GPIO_FN_A14, A14_MARK), 1279 GPIO_FN(A14),
1276 PINMUX_GPIO(GPIO_FN_A13, A13_MARK), 1280 GPIO_FN(A13),
1277 PINMUX_GPIO(GPIO_FN_A12, A12_MARK), 1281 GPIO_FN(A12),
1278 PINMUX_GPIO(GPIO_FN_A11, A11_MARK), 1282 GPIO_FN(A11),
1279 PINMUX_GPIO(GPIO_FN_A10, A10_MARK), 1283 GPIO_FN(A10),
1280 PINMUX_GPIO(GPIO_FN_A9, A9_MARK), 1284 GPIO_FN(A9),
1281 PINMUX_GPIO(GPIO_FN_A8, A8_MARK), 1285 GPIO_FN(A8),
1282 PINMUX_GPIO(GPIO_FN_A7, A7_MARK), 1286 GPIO_FN(A7),
1283 PINMUX_GPIO(GPIO_FN_A6, A6_MARK), 1287 GPIO_FN(A6),
1284 PINMUX_GPIO(GPIO_FN_A5, A5_MARK), 1288 GPIO_FN(A5),
1285 PINMUX_GPIO(GPIO_FN_A4, A4_MARK), 1289 GPIO_FN(A4),
1286 PINMUX_GPIO(GPIO_FN_A3, A3_MARK), 1290 GPIO_FN(A3),
1287 PINMUX_GPIO(GPIO_FN_A2, A2_MARK), 1291 GPIO_FN(A2),
1288 PINMUX_GPIO(GPIO_FN_A1, A1_MARK), 1292 GPIO_FN(A1),
1289 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 1293 GPIO_FN(A0),
1290 1294
1291 PINMUX_GPIO(GPIO_FN_D15, D15_MARK), 1295 GPIO_FN(D15),
1292 PINMUX_GPIO(GPIO_FN_D14, D14_MARK), 1296 GPIO_FN(D14),
1293 PINMUX_GPIO(GPIO_FN_D13, D13_MARK), 1297 GPIO_FN(D13),
1294 PINMUX_GPIO(GPIO_FN_D12, D12_MARK), 1298 GPIO_FN(D12),
1295 PINMUX_GPIO(GPIO_FN_D11, D11_MARK), 1299 GPIO_FN(D11),
1296 PINMUX_GPIO(GPIO_FN_D10, D10_MARK), 1300 GPIO_FN(D10),
1297 PINMUX_GPIO(GPIO_FN_D9, D9_MARK), 1301 GPIO_FN(D9),
1298 PINMUX_GPIO(GPIO_FN_D8, D8_MARK), 1302 GPIO_FN(D8),
1299 PINMUX_GPIO(GPIO_FN_D7, D7_MARK), 1303 GPIO_FN(D7),
1300 PINMUX_GPIO(GPIO_FN_D6, D6_MARK), 1304 GPIO_FN(D6),
1301 PINMUX_GPIO(GPIO_FN_D5, D5_MARK), 1305 GPIO_FN(D5),
1302 PINMUX_GPIO(GPIO_FN_D4, D4_MARK), 1306 GPIO_FN(D4),
1303 PINMUX_GPIO(GPIO_FN_D3, D3_MARK), 1307 GPIO_FN(D3),
1304 PINMUX_GPIO(GPIO_FN_D2, D2_MARK), 1308 GPIO_FN(D2),
1305 PINMUX_GPIO(GPIO_FN_D1, D1_MARK), 1309 GPIO_FN(D1),
1306 PINMUX_GPIO(GPIO_FN_D0, D0_MARK), 1310 GPIO_FN(D0),
1307 1311
1308 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1312 GPIO_FN(BS),
1309 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), 1313 GPIO_FN(CS4),
1310 PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), 1314 GPIO_FN(CS3),
1311 PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), 1315 GPIO_FN(CS2),
1312 PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), 1316 GPIO_FN(CS1),
1313 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), 1317 GPIO_FN(CS0),
1314 PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK), 1318 GPIO_FN(CS6CE1B),
1315 PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), 1319 GPIO_FN(CS5CE1A),
1316 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 1320 GPIO_FN(CE2A),
1317 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 1321 GPIO_FN(CE2B),
1318 PINMUX_GPIO(GPIO_FN_RD, RD_MARK), 1322 GPIO_FN(RD),
1319 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), 1323 GPIO_FN(RDWR),
1320 PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK), 1324 GPIO_FN(ICIOWRAH),
1321 PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK), 1325 GPIO_FN(ICIORD),
1322 PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), 1326 GPIO_FN(WE1DQMUWE),
1323 PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), 1327 GPIO_FN(WE0DQML),
1324 PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), 1328 GPIO_FN(RAS),
1325 PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), 1329 GPIO_FN(CAS),
1326 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), 1330 GPIO_FN(CKE),
1327 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 1331 GPIO_FN(WAIT),
1328 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), 1332 GPIO_FN(BREQ),
1329 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), 1333 GPIO_FN(BACK),
1330 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 1334 GPIO_FN(IOIS16),
1331 1335
1332 /* TMU */ 1336 /* TMU */
1333 PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), 1337 GPIO_FN(TIOC4D),
1334 PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), 1338 GPIO_FN(TIOC4C),
1335 PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), 1339 GPIO_FN(TIOC4B),
1336 PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), 1340 GPIO_FN(TIOC4A),
1337 PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), 1341 GPIO_FN(TIOC3D),
1338 PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), 1342 GPIO_FN(TIOC3C),
1339 PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), 1343 GPIO_FN(TIOC3B),
1340 PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), 1344 GPIO_FN(TIOC3A),
1341 PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), 1345 GPIO_FN(TIOC2B),
1342 PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), 1346 GPIO_FN(TIOC1B),
1343 PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), 1347 GPIO_FN(TIOC2A),
1344 PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), 1348 GPIO_FN(TIOC1A),
1345 PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), 1349 GPIO_FN(TIOC0D),
1346 PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), 1350 GPIO_FN(TIOC0C),
1347 PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), 1351 GPIO_FN(TIOC0B),
1348 PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), 1352 GPIO_FN(TIOC0A),
1349 PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), 1353 GPIO_FN(TCLKD),
1350 PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), 1354 GPIO_FN(TCLKC),
1351 PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), 1355 GPIO_FN(TCLKB),
1352 PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), 1356 GPIO_FN(TCLKA),
1353 1357
1354 /* SCIF */ 1358 /* SCIF */
1355 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), 1359 GPIO_FN(TXD0),
1356 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), 1360 GPIO_FN(RXD0),
1357 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), 1361 GPIO_FN(SCK0),
1358 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), 1362 GPIO_FN(TXD1),
1359 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), 1363 GPIO_FN(RXD1),
1360 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), 1364 GPIO_FN(SCK1),
1361 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 1365 GPIO_FN(TXD2),
1362 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 1366 GPIO_FN(RXD2),
1363 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 1367 GPIO_FN(SCK2),
1364 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), 1368 GPIO_FN(RTS3),
1365 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), 1369 GPIO_FN(CTS3),
1366 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 1370 GPIO_FN(TXD3),
1367 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 1371 GPIO_FN(RXD3),
1368 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), 1372 GPIO_FN(SCK3),
1369 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), 1373 GPIO_FN(TXD4),
1370 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), 1374 GPIO_FN(RXD4),
1371 PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), 1375 GPIO_FN(TXD5),
1372 PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), 1376 GPIO_FN(RXD5),
1373 PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), 1377 GPIO_FN(TXD6),
1374 PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), 1378 GPIO_FN(RXD6),
1375 PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), 1379 GPIO_FN(TXD7),
1376 PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), 1380 GPIO_FN(RXD7),
1377 PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), 1381 GPIO_FN(RTS1),
1378 PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), 1382 GPIO_FN(CTS1),
1379 1383
1380 /* RSPI */ 1384 /* RSPI */
1381 PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK), 1385 GPIO_FN(RSPCK0),
1382 PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK), 1386 GPIO_FN(MOSI0),
1383 PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK), 1387 GPIO_FN(MISO0_PF12),
1384 PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), 1388 GPIO_FN(MISO1),
1385 PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK), 1389 GPIO_FN(SSL00),
1386 PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), 1390 GPIO_FN(RSPCK1),
1387 PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), 1391 GPIO_FN(MOSI1),
1388 PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK), 1392 GPIO_FN(MISO1_PG19),
1389 PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), 1393 GPIO_FN(SSL10),
1390 1394
1391 /* IIC3 */ 1395 /* IIC3 */
1392 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), 1396 GPIO_FN(SCL0),
1393 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), 1397 GPIO_FN(SCL1),
1394 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), 1398 GPIO_FN(SCL2),
1395 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), 1399 GPIO_FN(SDA0),
1396 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), 1400 GPIO_FN(SDA1),
1397 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), 1401 GPIO_FN(SDA2),
1398 1402
1399 /* SSI */ 1403 /* SSI */
1400 PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), 1404 GPIO_FN(SSISCK0),
1401 PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), 1405 GPIO_FN(SSIWS0),
1402 PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), 1406 GPIO_FN(SSITXD0),
1403 PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), 1407 GPIO_FN(SSIRXD0),
1404 PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), 1408 GPIO_FN(SSIWS1),
1405 PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), 1409 GPIO_FN(SSIWS2),
1406 PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), 1410 GPIO_FN(SSIWS3),
1407 PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), 1411 GPIO_FN(SSISCK1),
1408 PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), 1412 GPIO_FN(SSISCK2),
1409 PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), 1413 GPIO_FN(SSISCK3),
1410 PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), 1414 GPIO_FN(SSIDATA1),
1411 PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), 1415 GPIO_FN(SSIDATA2),
1412 PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), 1416 GPIO_FN(SSIDATA3),
1413 PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), 1417 GPIO_FN(AUDIO_CLK),
1414 1418
1415 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ 1419 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
1416 PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), 1420 GPIO_FN(SIOFTXD),
1417 PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), 1421 GPIO_FN(SIOFRXD),
1418 PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), 1422 GPIO_FN(SIOFSYNC),
1419 PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), 1423 GPIO_FN(SIOFSCK),
1420 1424
1421 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ 1425 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
1422 PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), 1426 GPIO_FN(SPDIF_IN),
1423 PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), 1427 GPIO_FN(SPDIF_OUT),
1424 1428
1425 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ 1429 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
1426 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 1430 GPIO_FN(FCE),
1427 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 1431 GPIO_FN(FRB),
1428 1432
1429 /* VDC3 */ 1433 /* VDC3 */
1430 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), 1434 GPIO_FN(DV_CLK),
1431 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), 1435 GPIO_FN(DV_VSYNC),
1432 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), 1436 GPIO_FN(DV_HSYNC),
1433 1437
1434 PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), 1438 GPIO_FN(DV_DATA7),
1435 PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), 1439 GPIO_FN(DV_DATA6),
1436 PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), 1440 GPIO_FN(DV_DATA5),
1437 PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), 1441 GPIO_FN(DV_DATA4),
1438 PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), 1442 GPIO_FN(DV_DATA3),
1439 PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), 1443 GPIO_FN(DV_DATA2),
1440 PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), 1444 GPIO_FN(DV_DATA1),
1441 PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), 1445 GPIO_FN(DV_DATA0),
1442 1446
1443 PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), 1447 GPIO_FN(LCD_CLK),
1444 PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), 1448 GPIO_FN(LCD_EXTCLK),
1445 PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), 1449 GPIO_FN(LCD_VSYNC),
1446 PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), 1450 GPIO_FN(LCD_HSYNC),
1447 PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), 1451 GPIO_FN(LCD_DE),
1448 1452
1449 PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), 1453 GPIO_FN(LCD_DATA15),
1450 PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), 1454 GPIO_FN(LCD_DATA14),
1451 PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), 1455 GPIO_FN(LCD_DATA13),
1452 PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), 1456 GPIO_FN(LCD_DATA12),
1453 PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), 1457 GPIO_FN(LCD_DATA11),
1454 PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), 1458 GPIO_FN(LCD_DATA10),
1455 PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), 1459 GPIO_FN(LCD_DATA9),
1456 PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), 1460 GPIO_FN(LCD_DATA8),
1457 PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), 1461 GPIO_FN(LCD_DATA7),
1458 PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), 1462 GPIO_FN(LCD_DATA6),
1459 PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), 1463 GPIO_FN(LCD_DATA5),
1460 PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), 1464 GPIO_FN(LCD_DATA4),
1461 PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), 1465 GPIO_FN(LCD_DATA3),
1462 PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), 1466 GPIO_FN(LCD_DATA2),
1463 PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), 1467 GPIO_FN(LCD_DATA1),
1464 PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), 1468 GPIO_FN(LCD_DATA0),
1465 1469
1466 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), 1470 GPIO_FN(LCD_M_DISP),
1467}; 1471};
1468 1472
1469static struct pinmux_cfg_reg pinmux_config_regs[] = { 1473static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1470 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) { 1474 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
1471 0, 0, 0, 0, 0, 0, 0, 0, 1475 0, 0, 0, 0, 0, 0, 0, 0,
1472 0, 0, 0, 0, 0, 0, 0, 0, 1476 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2032,7 +2036,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2032 {} 2036 {}
2033}; 2037};
2034 2038
2035static struct pinmux_data_reg pinmux_data_regs[] = { 2039static const struct pinmux_data_reg pinmux_data_regs[] = {
2036 { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) { 2040 { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
2037 0, 0, 0, 0, 0, 0, 0, PA3_DATA, 2041 0, 0, 0, 0, 0, 0, 0, PA3_DATA,
2038 0, 0, 0, 0, 0, 0, 0, PA2_DATA } 2042 0, 0, 0, 0, 0, 0, 0, PA2_DATA }
@@ -2110,19 +2114,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2110 { } 2114 { }
2111}; 2115};
2112 2116
2113struct sh_pfc_soc_info sh7264_pinmux_info = { 2117const struct sh_pfc_soc_info sh7264_pinmux_info = {
2114 .name = "sh7264_pfc", 2118 .name = "sh7264_pfc",
2115 .reserved_id = PINMUX_RESERVED,
2116 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2117 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, 2119 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
2118 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, 2120 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
2119 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2120 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2121 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2121 2122
2122 .first_gpio = GPIO_PA3, 2123 .pins = pinmux_pins,
2123 .last_gpio = GPIO_FN_LCD_M_DISP, 2124 .nr_pins = ARRAY_SIZE(pinmux_pins),
2125 .func_gpios = pinmux_func_gpios,
2126 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2124 2127
2125 .gpios = pinmux_gpios,
2126 .cfg_regs = pinmux_config_regs, 2128 .cfg_regs = pinmux_config_regs,
2127 .data_regs = pinmux_data_regs, 2129 .data_regs = pinmux_data_regs,
2128 2130
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index b1b5d6d4ad76..4c401a74acd5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -781,7 +781,7 @@ enum {
781 PINMUX_MARK_END, 781 PINMUX_MARK_END,
782}; 782};
783 783
784static pinmux_enum_t pinmux_data[] = { 784static const pinmux_enum_t pinmux_data[] = {
785 785
786 /* Port A */ 786 /* Port A */
787 PINMUX_DATA(PA1_DATA, PA1_IN), 787 PINMUX_DATA(PA1_DATA, PA1_IN),
@@ -1452,7 +1452,7 @@ static pinmux_enum_t pinmux_data[] = {
1452 PINMUX_DATA(PWM1A_MARK, PJ0MD_100), 1452 PINMUX_DATA(PWM1A_MARK, PJ0MD_100),
1453}; 1453};
1454 1454
1455static struct pinmux_gpio pinmux_gpios[] = { 1455static struct sh_pfc_pin pinmux_pins[] = {
1456 /* Port A */ 1456 /* Port A */
1457 PINMUX_GPIO(GPIO_PA1, PA1_DATA), 1457 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
1458 PINMUX_GPIO(GPIO_PA0, PA0_DATA), 1458 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
@@ -1613,339 +1613,343 @@ static struct pinmux_gpio pinmux_gpios[] = {
1613 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), 1613 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
1614 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), 1614 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
1615 PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), 1615 PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
1616};
1617
1618#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1616 1619
1620static const struct pinmux_func pinmux_func_gpios[] = {
1617 /* INTC */ 1621 /* INTC */
1618 PINMUX_GPIO(GPIO_FN_IRQ7_PG, IRQ7_PG_MARK), 1622 GPIO_FN(IRQ7_PG),
1619 PINMUX_GPIO(GPIO_FN_IRQ6_PG, IRQ6_PG_MARK), 1623 GPIO_FN(IRQ6_PG),
1620 PINMUX_GPIO(GPIO_FN_IRQ5_PG, IRQ5_PG_MARK), 1624 GPIO_FN(IRQ5_PG),
1621 PINMUX_GPIO(GPIO_FN_IRQ4_PG, IRQ4_PG_MARK), 1625 GPIO_FN(IRQ4_PG),
1622 PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), 1626 GPIO_FN(IRQ3_PG),
1623 PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), 1627 GPIO_FN(IRQ2_PG),
1624 PINMUX_GPIO(GPIO_FN_IRQ1_PG, IRQ1_PG_MARK), 1628 GPIO_FN(IRQ1_PG),
1625 PINMUX_GPIO(GPIO_FN_IRQ0_PG, IRQ0_PG_MARK), 1629 GPIO_FN(IRQ0_PG),
1626 PINMUX_GPIO(GPIO_FN_IRQ7_PF, IRQ7_PF_MARK), 1630 GPIO_FN(IRQ7_PF),
1627 PINMUX_GPIO(GPIO_FN_IRQ6_PF, IRQ6_PF_MARK), 1631 GPIO_FN(IRQ6_PF),
1628 PINMUX_GPIO(GPIO_FN_IRQ5_PF, IRQ5_PF_MARK), 1632 GPIO_FN(IRQ5_PF),
1629 PINMUX_GPIO(GPIO_FN_IRQ4_PF, IRQ4_PF_MARK), 1633 GPIO_FN(IRQ4_PF),
1630 PINMUX_GPIO(GPIO_FN_IRQ3_PJ, IRQ3_PJ_MARK), 1634 GPIO_FN(IRQ3_PJ),
1631 PINMUX_GPIO(GPIO_FN_IRQ2_PJ, IRQ2_PJ_MARK), 1635 GPIO_FN(IRQ2_PJ),
1632 PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), 1636 GPIO_FN(IRQ1_PJ),
1633 PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), 1637 GPIO_FN(IRQ0_PJ),
1634 PINMUX_GPIO(GPIO_FN_IRQ1_PC, IRQ1_PC_MARK), 1638 GPIO_FN(IRQ1_PC),
1635 PINMUX_GPIO(GPIO_FN_IRQ0_PC, IRQ0_PC_MARK), 1639 GPIO_FN(IRQ0_PC),
1636 1640
1637 PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), 1641 GPIO_FN(PINT7_PG),
1638 PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), 1642 GPIO_FN(PINT6_PG),
1639 PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), 1643 GPIO_FN(PINT5_PG),
1640 PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), 1644 GPIO_FN(PINT4_PG),
1641 PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), 1645 GPIO_FN(PINT3_PG),
1642 PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), 1646 GPIO_FN(PINT2_PG),
1643 PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), 1647 GPIO_FN(PINT1_PG),
1644 PINMUX_GPIO(GPIO_FN_PINT0_PG, PINT0_PG_MARK), 1648 GPIO_FN(PINT0_PG),
1645 PINMUX_GPIO(GPIO_FN_PINT7_PH, PINT7_PH_MARK), 1649 GPIO_FN(PINT7_PH),
1646 PINMUX_GPIO(GPIO_FN_PINT6_PH, PINT6_PH_MARK), 1650 GPIO_FN(PINT6_PH),
1647 PINMUX_GPIO(GPIO_FN_PINT5_PH, PINT5_PH_MARK), 1651 GPIO_FN(PINT5_PH),
1648 PINMUX_GPIO(GPIO_FN_PINT4_PH, PINT4_PH_MARK), 1652 GPIO_FN(PINT4_PH),
1649 PINMUX_GPIO(GPIO_FN_PINT3_PH, PINT3_PH_MARK), 1653 GPIO_FN(PINT3_PH),
1650 PINMUX_GPIO(GPIO_FN_PINT2_PH, PINT2_PH_MARK), 1654 GPIO_FN(PINT2_PH),
1651 PINMUX_GPIO(GPIO_FN_PINT1_PH, PINT1_PH_MARK), 1655 GPIO_FN(PINT1_PH),
1652 PINMUX_GPIO(GPIO_FN_PINT0_PH, PINT0_PH_MARK), 1656 GPIO_FN(PINT0_PH),
1653 PINMUX_GPIO(GPIO_FN_PINT7_PJ, PINT7_PJ_MARK), 1657 GPIO_FN(PINT7_PJ),
1654 PINMUX_GPIO(GPIO_FN_PINT6_PJ, PINT6_PJ_MARK), 1658 GPIO_FN(PINT6_PJ),
1655 PINMUX_GPIO(GPIO_FN_PINT5_PJ, PINT5_PJ_MARK), 1659 GPIO_FN(PINT5_PJ),
1656 PINMUX_GPIO(GPIO_FN_PINT4_PJ, PINT4_PJ_MARK), 1660 GPIO_FN(PINT4_PJ),
1657 PINMUX_GPIO(GPIO_FN_PINT3_PJ, PINT3_PJ_MARK), 1661 GPIO_FN(PINT3_PJ),
1658 PINMUX_GPIO(GPIO_FN_PINT2_PJ, PINT2_PJ_MARK), 1662 GPIO_FN(PINT2_PJ),
1659 PINMUX_GPIO(GPIO_FN_PINT1_PJ, PINT1_PJ_MARK), 1663 GPIO_FN(PINT1_PJ),
1660 PINMUX_GPIO(GPIO_FN_PINT0_PJ, PINT0_PJ_MARK), 1664 GPIO_FN(PINT0_PJ),
1661 1665
1662 /* WDT */ 1666 /* WDT */
1663 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), 1667 GPIO_FN(WDTOVF),
1664 1668
1665 /* CAN */ 1669 /* CAN */
1666 PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), 1670 GPIO_FN(CTX1),
1667 PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), 1671 GPIO_FN(CRX1),
1668 PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), 1672 GPIO_FN(CTX0),
1669 PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), 1673 GPIO_FN(CRX0),
1670 PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), 1674 GPIO_FN(CRX0_CRX1),
1671 PINMUX_GPIO(GPIO_FN_CRX0_CRX1_CRX2, CRX0_CRX1_CRX2_MARK), 1675 GPIO_FN(CRX0_CRX1_CRX2),
1672 1676
1673 /* DMAC */ 1677 /* DMAC */
1674 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), 1678 GPIO_FN(TEND0),
1675 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 1679 GPIO_FN(DACK0),
1676 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 1680 GPIO_FN(DREQ0),
1677 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), 1681 GPIO_FN(TEND1),
1678 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 1682 GPIO_FN(DACK1),
1679 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 1683 GPIO_FN(DREQ1),
1680 1684
1681 /* ADC */ 1685 /* ADC */
1682 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), 1686 GPIO_FN(ADTRG),
1683 1687
1684 /* BSCh */ 1688 /* BSCh */
1685 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1689 GPIO_FN(A25),
1686 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1690 GPIO_FN(A24),
1687 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1691 GPIO_FN(A23),
1688 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1692 GPIO_FN(A22),
1689 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 1693 GPIO_FN(A21),
1690 PINMUX_GPIO(GPIO_FN_A20, A20_MARK), 1694 GPIO_FN(A20),
1691 PINMUX_GPIO(GPIO_FN_A19, A19_MARK), 1695 GPIO_FN(A19),
1692 PINMUX_GPIO(GPIO_FN_A18, A18_MARK), 1696 GPIO_FN(A18),
1693 PINMUX_GPIO(GPIO_FN_A17, A17_MARK), 1697 GPIO_FN(A17),
1694 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1698 GPIO_FN(A16),
1695 PINMUX_GPIO(GPIO_FN_A15, A15_MARK), 1699 GPIO_FN(A15),
1696 PINMUX_GPIO(GPIO_FN_A14, A14_MARK), 1700 GPIO_FN(A14),
1697 PINMUX_GPIO(GPIO_FN_A13, A13_MARK), 1701 GPIO_FN(A13),
1698 PINMUX_GPIO(GPIO_FN_A12, A12_MARK), 1702 GPIO_FN(A12),
1699 PINMUX_GPIO(GPIO_FN_A11, A11_MARK), 1703 GPIO_FN(A11),
1700 PINMUX_GPIO(GPIO_FN_A10, A10_MARK), 1704 GPIO_FN(A10),
1701 PINMUX_GPIO(GPIO_FN_A9, A9_MARK), 1705 GPIO_FN(A9),
1702 PINMUX_GPIO(GPIO_FN_A8, A8_MARK), 1706 GPIO_FN(A8),
1703 PINMUX_GPIO(GPIO_FN_A7, A7_MARK), 1707 GPIO_FN(A7),
1704 PINMUX_GPIO(GPIO_FN_A6, A6_MARK), 1708 GPIO_FN(A6),
1705 PINMUX_GPIO(GPIO_FN_A5, A5_MARK), 1709 GPIO_FN(A5),
1706 PINMUX_GPIO(GPIO_FN_A4, A4_MARK), 1710 GPIO_FN(A4),
1707 PINMUX_GPIO(GPIO_FN_A3, A3_MARK), 1711 GPIO_FN(A3),
1708 PINMUX_GPIO(GPIO_FN_A2, A2_MARK), 1712 GPIO_FN(A2),
1709 PINMUX_GPIO(GPIO_FN_A1, A1_MARK), 1713 GPIO_FN(A1),
1710 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 1714 GPIO_FN(A0),
1711 1715
1712 PINMUX_GPIO(GPIO_FN_D15, D15_MARK), 1716 GPIO_FN(D15),
1713 PINMUX_GPIO(GPIO_FN_D14, D14_MARK), 1717 GPIO_FN(D14),
1714 PINMUX_GPIO(GPIO_FN_D13, D13_MARK), 1718 GPIO_FN(D13),
1715 PINMUX_GPIO(GPIO_FN_D12, D12_MARK), 1719 GPIO_FN(D12),
1716 PINMUX_GPIO(GPIO_FN_D11, D11_MARK), 1720 GPIO_FN(D11),
1717 PINMUX_GPIO(GPIO_FN_D10, D10_MARK), 1721 GPIO_FN(D10),
1718 PINMUX_GPIO(GPIO_FN_D9, D9_MARK), 1722 GPIO_FN(D9),
1719 PINMUX_GPIO(GPIO_FN_D8, D8_MARK), 1723 GPIO_FN(D8),
1720 PINMUX_GPIO(GPIO_FN_D7, D7_MARK), 1724 GPIO_FN(D7),
1721 PINMUX_GPIO(GPIO_FN_D6, D6_MARK), 1725 GPIO_FN(D6),
1722 PINMUX_GPIO(GPIO_FN_D5, D5_MARK), 1726 GPIO_FN(D5),
1723 PINMUX_GPIO(GPIO_FN_D4, D4_MARK), 1727 GPIO_FN(D4),
1724 PINMUX_GPIO(GPIO_FN_D3, D3_MARK), 1728 GPIO_FN(D3),
1725 PINMUX_GPIO(GPIO_FN_D2, D2_MARK), 1729 GPIO_FN(D2),
1726 PINMUX_GPIO(GPIO_FN_D1, D1_MARK), 1730 GPIO_FN(D1),
1727 PINMUX_GPIO(GPIO_FN_D0, D0_MARK), 1731 GPIO_FN(D0),
1728 1732
1729 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1733 GPIO_FN(BS),
1730 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), 1734 GPIO_FN(CS4),
1731 PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), 1735 GPIO_FN(CS3),
1732 PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), 1736 GPIO_FN(CS2),
1733 PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), 1737 GPIO_FN(CS1),
1734 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), 1738 GPIO_FN(CS0),
1735 PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), 1739 GPIO_FN(CS5CE1A),
1736 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 1740 GPIO_FN(CE2A),
1737 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 1741 GPIO_FN(CE2B),
1738 PINMUX_GPIO(GPIO_FN_RD, RD_MARK), 1742 GPIO_FN(RD),
1739 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), 1743 GPIO_FN(RDWR),
1740 PINMUX_GPIO(GPIO_FN_WE3ICIOWRAHDQMUU, WE3ICIOWRAHDQMUU_MARK), 1744 GPIO_FN(WE3ICIOWRAHDQMUU),
1741 PINMUX_GPIO(GPIO_FN_WE2ICIORDDQMUL, WE2ICIORDDQMUL_MARK), 1745 GPIO_FN(WE2ICIORDDQMUL),
1742 PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), 1746 GPIO_FN(WE1DQMUWE),
1743 PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), 1747 GPIO_FN(WE0DQML),
1744 PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), 1748 GPIO_FN(RAS),
1745 PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), 1749 GPIO_FN(CAS),
1746 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), 1750 GPIO_FN(CKE),
1747 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 1751 GPIO_FN(WAIT),
1748 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), 1752 GPIO_FN(BREQ),
1749 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), 1753 GPIO_FN(BACK),
1750 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 1754 GPIO_FN(IOIS16),
1751 1755
1752 /* TMU */ 1756 /* TMU */
1753 PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), 1757 GPIO_FN(TIOC4D),
1754 PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), 1758 GPIO_FN(TIOC4C),
1755 PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), 1759 GPIO_FN(TIOC4B),
1756 PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), 1760 GPIO_FN(TIOC4A),
1757 PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), 1761 GPIO_FN(TIOC3D),
1758 PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), 1762 GPIO_FN(TIOC3C),
1759 PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), 1763 GPIO_FN(TIOC3B),
1760 PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), 1764 GPIO_FN(TIOC3A),
1761 PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), 1765 GPIO_FN(TIOC2B),
1762 PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), 1766 GPIO_FN(TIOC1B),
1763 PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), 1767 GPIO_FN(TIOC2A),
1764 PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), 1768 GPIO_FN(TIOC1A),
1765 PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), 1769 GPIO_FN(TIOC0D),
1766 PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), 1770 GPIO_FN(TIOC0C),
1767 PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), 1771 GPIO_FN(TIOC0B),
1768 PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), 1772 GPIO_FN(TIOC0A),
1769 PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), 1773 GPIO_FN(TCLKD),
1770 PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), 1774 GPIO_FN(TCLKC),
1771 PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), 1775 GPIO_FN(TCLKB),
1772 PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), 1776 GPIO_FN(TCLKA),
1773 1777
1774 /* SCIF */ 1778 /* SCIF */
1775 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), 1779 GPIO_FN(SCK0),
1776 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), 1780 GPIO_FN(TXD0),
1777 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), 1781 GPIO_FN(RXD0),
1778 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), 1782 GPIO_FN(SCK1),
1779 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), 1783 GPIO_FN(TXD1),
1780 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), 1784 GPIO_FN(RXD1),
1781 PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), 1785 GPIO_FN(RTS1),
1782 PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), 1786 GPIO_FN(CTS1),
1783 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 1787 GPIO_FN(SCK2),
1784 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 1788 GPIO_FN(TXD2),
1785 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 1789 GPIO_FN(RXD2),
1786 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), 1790 GPIO_FN(SCK3),
1787 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 1791 GPIO_FN(TXD3),
1788 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 1792 GPIO_FN(RXD3),
1789 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), 1793 GPIO_FN(SCK4),
1790 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), 1794 GPIO_FN(TXD4),
1791 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), 1795 GPIO_FN(RXD4),
1792 PINMUX_GPIO(GPIO_FN_SCK5, SCK5_MARK), 1796 GPIO_FN(SCK5),
1793 PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), 1797 GPIO_FN(TXD5),
1794 PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), 1798 GPIO_FN(RXD5),
1795 PINMUX_GPIO(GPIO_FN_RTS5, RTS5_MARK), 1799 GPIO_FN(RTS5),
1796 PINMUX_GPIO(GPIO_FN_CTS5, CTS5_MARK), 1800 GPIO_FN(CTS5),
1797 PINMUX_GPIO(GPIO_FN_SCK6, SCK6_MARK), 1801 GPIO_FN(SCK6),
1798 PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), 1802 GPIO_FN(TXD6),
1799 PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), 1803 GPIO_FN(RXD6),
1800 PINMUX_GPIO(GPIO_FN_SCK7, SCK7_MARK), 1804 GPIO_FN(SCK7),
1801 PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), 1805 GPIO_FN(TXD7),
1802 PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), 1806 GPIO_FN(RXD7),
1803 PINMUX_GPIO(GPIO_FN_RTS7, RTS7_MARK), 1807 GPIO_FN(RTS7),
1804 PINMUX_GPIO(GPIO_FN_CTS7, CTS7_MARK), 1808 GPIO_FN(CTS7),
1805 1809
1806 /* RSPI */ 1810 /* RSPI */
1807 PINMUX_GPIO(GPIO_FN_RSPCK0_PJ16, RSPCK0_PJ16_MARK), 1811 GPIO_FN(RSPCK0_PJ16),
1808 PINMUX_GPIO(GPIO_FN_SSL00_PJ17, SSL00_PJ17_MARK), 1812 GPIO_FN(SSL00_PJ17),
1809 PINMUX_GPIO(GPIO_FN_MOSI0_PJ18, MOSI0_PJ18_MARK), 1813 GPIO_FN(MOSI0_PJ18),
1810 PINMUX_GPIO(GPIO_FN_MISO0_PJ19, MISO0_PJ19_MARK), 1814 GPIO_FN(MISO0_PJ19),
1811 PINMUX_GPIO(GPIO_FN_RSPCK0_PB17, RSPCK0_PB17_MARK), 1815 GPIO_FN(RSPCK0_PB17),
1812 PINMUX_GPIO(GPIO_FN_SSL00_PB18, SSL00_PB18_MARK), 1816 GPIO_FN(SSL00_PB18),
1813 PINMUX_GPIO(GPIO_FN_MOSI0_PB19, MOSI0_PB19_MARK), 1817 GPIO_FN(MOSI0_PB19),
1814 PINMUX_GPIO(GPIO_FN_MISO0_PB20, MISO0_PB20_MARK), 1818 GPIO_FN(MISO0_PB20),
1815 PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), 1819 GPIO_FN(RSPCK1),
1816 PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), 1820 GPIO_FN(MOSI1),
1817 PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), 1821 GPIO_FN(MISO1),
1818 PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), 1822 GPIO_FN(SSL10),
1819 1823
1820 /* IIC3 */ 1824 /* IIC3 */
1821 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), 1825 GPIO_FN(SCL0),
1822 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), 1826 GPIO_FN(SCL1),
1823 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), 1827 GPIO_FN(SCL2),
1824 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), 1828 GPIO_FN(SDA0),
1825 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), 1829 GPIO_FN(SDA1),
1826 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), 1830 GPIO_FN(SDA2),
1827 1831
1828 /* SSI */ 1832 /* SSI */
1829 PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), 1833 GPIO_FN(SSISCK0),
1830 PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), 1834 GPIO_FN(SSIWS0),
1831 PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), 1835 GPIO_FN(SSITXD0),
1832 PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), 1836 GPIO_FN(SSIRXD0),
1833 PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), 1837 GPIO_FN(SSIWS1),
1834 PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), 1838 GPIO_FN(SSIWS2),
1835 PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), 1839 GPIO_FN(SSIWS3),
1836 PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), 1840 GPIO_FN(SSISCK1),
1837 PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), 1841 GPIO_FN(SSISCK2),
1838 PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), 1842 GPIO_FN(SSISCK3),
1839 PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), 1843 GPIO_FN(SSIDATA1),
1840 PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), 1844 GPIO_FN(SSIDATA2),
1841 PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), 1845 GPIO_FN(SSIDATA3),
1842 PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), 1846 GPIO_FN(AUDIO_CLK),
1843 PINMUX_GPIO(GPIO_FN_AUDIO_XOUT, AUDIO_XOUT_MARK), 1847 GPIO_FN(AUDIO_XOUT),
1844 1848
1845 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ 1849 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
1846 PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), 1850 GPIO_FN(SIOFTXD),
1847 PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), 1851 GPIO_FN(SIOFRXD),
1848 PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), 1852 GPIO_FN(SIOFSYNC),
1849 PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), 1853 GPIO_FN(SIOFSCK),
1850 1854
1851 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ 1855 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
1852 PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), 1856 GPIO_FN(SPDIF_IN),
1853 PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), 1857 GPIO_FN(SPDIF_OUT),
1854 1858
1855 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ 1859 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
1856 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 1860 GPIO_FN(FCE),
1857 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 1861 GPIO_FN(FRB),
1858 1862
1859 /* VDC3 */ 1863 /* VDC3 */
1860 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), 1864 GPIO_FN(DV_CLK),
1861 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), 1865 GPIO_FN(DV_VSYNC),
1862 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), 1866 GPIO_FN(DV_HSYNC),
1863 1867
1864 PINMUX_GPIO(GPIO_FN_DV_DATA23, DV_DATA23_MARK), 1868 GPIO_FN(DV_DATA23),
1865 PINMUX_GPIO(GPIO_FN_DV_DATA22, DV_DATA22_MARK), 1869 GPIO_FN(DV_DATA22),
1866 PINMUX_GPIO(GPIO_FN_DV_DATA21, DV_DATA21_MARK), 1870 GPIO_FN(DV_DATA21),
1867 PINMUX_GPIO(GPIO_FN_DV_DATA20, DV_DATA20_MARK), 1871 GPIO_FN(DV_DATA20),
1868 PINMUX_GPIO(GPIO_FN_DV_DATA19, DV_DATA19_MARK), 1872 GPIO_FN(DV_DATA19),
1869 PINMUX_GPIO(GPIO_FN_DV_DATA18, DV_DATA18_MARK), 1873 GPIO_FN(DV_DATA18),
1870 PINMUX_GPIO(GPIO_FN_DV_DATA17, DV_DATA17_MARK), 1874 GPIO_FN(DV_DATA17),
1871 PINMUX_GPIO(GPIO_FN_DV_DATA16, DV_DATA16_MARK), 1875 GPIO_FN(DV_DATA16),
1872 PINMUX_GPIO(GPIO_FN_DV_DATA15, DV_DATA15_MARK), 1876 GPIO_FN(DV_DATA15),
1873 PINMUX_GPIO(GPIO_FN_DV_DATA14, DV_DATA14_MARK), 1877 GPIO_FN(DV_DATA14),
1874 PINMUX_GPIO(GPIO_FN_DV_DATA13, DV_DATA13_MARK), 1878 GPIO_FN(DV_DATA13),
1875 PINMUX_GPIO(GPIO_FN_DV_DATA12, DV_DATA12_MARK), 1879 GPIO_FN(DV_DATA12),
1876 PINMUX_GPIO(GPIO_FN_DV_DATA11, DV_DATA11_MARK), 1880 GPIO_FN(DV_DATA11),
1877 PINMUX_GPIO(GPIO_FN_DV_DATA10, DV_DATA10_MARK), 1881 GPIO_FN(DV_DATA10),
1878 PINMUX_GPIO(GPIO_FN_DV_DATA9, DV_DATA9_MARK), 1882 GPIO_FN(DV_DATA9),
1879 PINMUX_GPIO(GPIO_FN_DV_DATA8, DV_DATA8_MARK), 1883 GPIO_FN(DV_DATA8),
1880 PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), 1884 GPIO_FN(DV_DATA7),
1881 PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), 1885 GPIO_FN(DV_DATA6),
1882 PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), 1886 GPIO_FN(DV_DATA5),
1883 PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), 1887 GPIO_FN(DV_DATA4),
1884 PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), 1888 GPIO_FN(DV_DATA3),
1885 PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), 1889 GPIO_FN(DV_DATA2),
1886 PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), 1890 GPIO_FN(DV_DATA1),
1887 PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), 1891 GPIO_FN(DV_DATA0),
1888 1892
1889 PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), 1893 GPIO_FN(LCD_CLK),
1890 PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), 1894 GPIO_FN(LCD_EXTCLK),
1891 PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), 1895 GPIO_FN(LCD_VSYNC),
1892 PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), 1896 GPIO_FN(LCD_HSYNC),
1893 PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), 1897 GPIO_FN(LCD_DE),
1894 1898
1895 PINMUX_GPIO(GPIO_FN_LCD_DATA23_PG23, LCD_DATA23_PG23_MARK), 1899 GPIO_FN(LCD_DATA23_PG23),
1896 PINMUX_GPIO(GPIO_FN_LCD_DATA22_PG22, LCD_DATA22_PG22_MARK), 1900 GPIO_FN(LCD_DATA22_PG22),
1897 PINMUX_GPIO(GPIO_FN_LCD_DATA21_PG21, LCD_DATA21_PG21_MARK), 1901 GPIO_FN(LCD_DATA21_PG21),
1898 PINMUX_GPIO(GPIO_FN_LCD_DATA20_PG20, LCD_DATA20_PG20_MARK), 1902 GPIO_FN(LCD_DATA20_PG20),
1899 PINMUX_GPIO(GPIO_FN_LCD_DATA19_PG19, LCD_DATA19_PG19_MARK), 1903 GPIO_FN(LCD_DATA19_PG19),
1900 PINMUX_GPIO(GPIO_FN_LCD_DATA18_PG18, LCD_DATA18_PG18_MARK), 1904 GPIO_FN(LCD_DATA18_PG18),
1901 PINMUX_GPIO(GPIO_FN_LCD_DATA17_PG17, LCD_DATA17_PG17_MARK), 1905 GPIO_FN(LCD_DATA17_PG17),
1902 PINMUX_GPIO(GPIO_FN_LCD_DATA16_PG16, LCD_DATA16_PG16_MARK), 1906 GPIO_FN(LCD_DATA16_PG16),
1903 PINMUX_GPIO(GPIO_FN_LCD_DATA15_PG15, LCD_DATA15_PG15_MARK), 1907 GPIO_FN(LCD_DATA15_PG15),
1904 PINMUX_GPIO(GPIO_FN_LCD_DATA14_PG14, LCD_DATA14_PG14_MARK), 1908 GPIO_FN(LCD_DATA14_PG14),
1905 PINMUX_GPIO(GPIO_FN_LCD_DATA13_PG13, LCD_DATA13_PG13_MARK), 1909 GPIO_FN(LCD_DATA13_PG13),
1906 PINMUX_GPIO(GPIO_FN_LCD_DATA12_PG12, LCD_DATA12_PG12_MARK), 1910 GPIO_FN(LCD_DATA12_PG12),
1907 PINMUX_GPIO(GPIO_FN_LCD_DATA11_PG11, LCD_DATA11_PG11_MARK), 1911 GPIO_FN(LCD_DATA11_PG11),
1908 PINMUX_GPIO(GPIO_FN_LCD_DATA10_PG10, LCD_DATA10_PG10_MARK), 1912 GPIO_FN(LCD_DATA10_PG10),
1909 PINMUX_GPIO(GPIO_FN_LCD_DATA9_PG9, LCD_DATA9_PG9_MARK), 1913 GPIO_FN(LCD_DATA9_PG9),
1910 PINMUX_GPIO(GPIO_FN_LCD_DATA8_PG8, LCD_DATA8_PG8_MARK), 1914 GPIO_FN(LCD_DATA8_PG8),
1911 PINMUX_GPIO(GPIO_FN_LCD_DATA7_PG7, LCD_DATA7_PG7_MARK), 1915 GPIO_FN(LCD_DATA7_PG7),
1912 PINMUX_GPIO(GPIO_FN_LCD_DATA6_PG6, LCD_DATA6_PG6_MARK), 1916 GPIO_FN(LCD_DATA6_PG6),
1913 PINMUX_GPIO(GPIO_FN_LCD_DATA5_PG5, LCD_DATA5_PG5_MARK), 1917 GPIO_FN(LCD_DATA5_PG5),
1914 PINMUX_GPIO(GPIO_FN_LCD_DATA4_PG4, LCD_DATA4_PG4_MARK), 1918 GPIO_FN(LCD_DATA4_PG4),
1915 PINMUX_GPIO(GPIO_FN_LCD_DATA3_PG3, LCD_DATA3_PG3_MARK), 1919 GPIO_FN(LCD_DATA3_PG3),
1916 PINMUX_GPIO(GPIO_FN_LCD_DATA2_PG2, LCD_DATA2_PG2_MARK), 1920 GPIO_FN(LCD_DATA2_PG2),
1917 PINMUX_GPIO(GPIO_FN_LCD_DATA1_PG1, LCD_DATA1_PG1_MARK), 1921 GPIO_FN(LCD_DATA1_PG1),
1918 PINMUX_GPIO(GPIO_FN_LCD_DATA0_PG0, LCD_DATA0_PG0_MARK), 1922 GPIO_FN(LCD_DATA0_PG0),
1919 1923
1920 PINMUX_GPIO(GPIO_FN_LCD_DATA23_PJ23, LCD_DATA23_PJ23_MARK), 1924 GPIO_FN(LCD_DATA23_PJ23),
1921 PINMUX_GPIO(GPIO_FN_LCD_DATA22_PJ22, LCD_DATA22_PJ22_MARK), 1925 GPIO_FN(LCD_DATA22_PJ22),
1922 PINMUX_GPIO(GPIO_FN_LCD_DATA21_PJ21, LCD_DATA21_PJ21_MARK), 1926 GPIO_FN(LCD_DATA21_PJ21),
1923 PINMUX_GPIO(GPIO_FN_LCD_DATA20_PJ20, LCD_DATA20_PJ20_MARK), 1927 GPIO_FN(LCD_DATA20_PJ20),
1924 PINMUX_GPIO(GPIO_FN_LCD_DATA19_PJ19, LCD_DATA19_PJ19_MARK), 1928 GPIO_FN(LCD_DATA19_PJ19),
1925 PINMUX_GPIO(GPIO_FN_LCD_DATA18_PJ18, LCD_DATA18_PJ18_MARK), 1929 GPIO_FN(LCD_DATA18_PJ18),
1926 PINMUX_GPIO(GPIO_FN_LCD_DATA17_PJ17, LCD_DATA17_PJ17_MARK), 1930 GPIO_FN(LCD_DATA17_PJ17),
1927 PINMUX_GPIO(GPIO_FN_LCD_DATA16_PJ16, LCD_DATA16_PJ16_MARK), 1931 GPIO_FN(LCD_DATA16_PJ16),
1928 PINMUX_GPIO(GPIO_FN_LCD_DATA15_PJ15, LCD_DATA15_PJ15_MARK), 1932 GPIO_FN(LCD_DATA15_PJ15),
1929 PINMUX_GPIO(GPIO_FN_LCD_DATA14_PJ14, LCD_DATA14_PJ14_MARK), 1933 GPIO_FN(LCD_DATA14_PJ14),
1930 PINMUX_GPIO(GPIO_FN_LCD_DATA13_PJ13, LCD_DATA13_PJ13_MARK), 1934 GPIO_FN(LCD_DATA13_PJ13),
1931 PINMUX_GPIO(GPIO_FN_LCD_DATA12_PJ12, LCD_DATA12_PJ12_MARK), 1935 GPIO_FN(LCD_DATA12_PJ12),
1932 PINMUX_GPIO(GPIO_FN_LCD_DATA11_PJ11, LCD_DATA11_PJ11_MARK), 1936 GPIO_FN(LCD_DATA11_PJ11),
1933 PINMUX_GPIO(GPIO_FN_LCD_DATA10_PJ10, LCD_DATA10_PJ10_MARK), 1937 GPIO_FN(LCD_DATA10_PJ10),
1934 PINMUX_GPIO(GPIO_FN_LCD_DATA9_PJ9, LCD_DATA9_PJ9_MARK), 1938 GPIO_FN(LCD_DATA9_PJ9),
1935 PINMUX_GPIO(GPIO_FN_LCD_DATA8_PJ8, LCD_DATA8_PJ8_MARK), 1939 GPIO_FN(LCD_DATA8_PJ8),
1936 PINMUX_GPIO(GPIO_FN_LCD_DATA7_PJ7, LCD_DATA7_PJ7_MARK), 1940 GPIO_FN(LCD_DATA7_PJ7),
1937 PINMUX_GPIO(GPIO_FN_LCD_DATA6_PJ6, LCD_DATA6_PJ6_MARK), 1941 GPIO_FN(LCD_DATA6_PJ6),
1938 PINMUX_GPIO(GPIO_FN_LCD_DATA5_PJ5, LCD_DATA5_PJ5_MARK), 1942 GPIO_FN(LCD_DATA5_PJ5),
1939 PINMUX_GPIO(GPIO_FN_LCD_DATA4_PJ4, LCD_DATA4_PJ4_MARK), 1943 GPIO_FN(LCD_DATA4_PJ4),
1940 PINMUX_GPIO(GPIO_FN_LCD_DATA3_PJ3, LCD_DATA3_PJ3_MARK), 1944 GPIO_FN(LCD_DATA3_PJ3),
1941 PINMUX_GPIO(GPIO_FN_LCD_DATA2_PJ2, LCD_DATA2_PJ2_MARK), 1945 GPIO_FN(LCD_DATA2_PJ2),
1942 PINMUX_GPIO(GPIO_FN_LCD_DATA1_PJ1, LCD_DATA1_PJ1_MARK), 1946 GPIO_FN(LCD_DATA1_PJ1),
1943 PINMUX_GPIO(GPIO_FN_LCD_DATA0_PJ0, LCD_DATA0_PJ0_MARK), 1947 GPIO_FN(LCD_DATA0_PJ0),
1944 1948
1945 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), 1949 GPIO_FN(LCD_M_DISP),
1946}; 1950};
1947 1951
1948static struct pinmux_cfg_reg pinmux_config_regs[] = { 1952static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1949 /* "name" addr register_size Field_Width */ 1953 /* "name" addr register_size Field_Width */
1950 1954
1951 /* where Field_Width is 1 for single mode registers or 4 for upto 16 1955 /* where Field_Width is 1 for single mode registers or 4 for upto 16
@@ -2734,7 +2738,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2734 {} 2738 {}
2735}; 2739};
2736 2740
2737static struct pinmux_data_reg pinmux_data_regs[] = { 2741static const struct pinmux_data_reg pinmux_data_regs[] = {
2738 { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) { 2742 { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
2739 0, 0, 0, 0, 0, 0, 0, PA1_DATA, 2743 0, 0, 0, 0, 0, 0, 0, PA1_DATA,
2740 0, 0, 0, 0, 0, 0, 0, PA0_DATA } 2744 0, 0, 0, 0, 0, 0, 0, PA0_DATA }
@@ -2813,19 +2817,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2813 { } 2817 { }
2814}; 2818};
2815 2819
2816struct sh_pfc_soc_info sh7269_pinmux_info = { 2820const struct sh_pfc_soc_info sh7269_pinmux_info = {
2817 .name = "sh7269_pfc", 2821 .name = "sh7269_pfc",
2818 .reserved_id = PINMUX_RESERVED,
2819 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2820 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, 2822 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
2821 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, 2823 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
2822 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2823 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2824 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2824 2825
2825 .first_gpio = GPIO_PA1, 2826 .pins = pinmux_pins,
2826 .last_gpio = GPIO_FN_LCD_M_DISP, 2827 .nr_pins = ARRAY_SIZE(pinmux_pins),
2828 .func_gpios = pinmux_func_gpios,
2829 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2827 2830
2828 .gpios = pinmux_gpios,
2829 .cfg_regs = pinmux_config_regs, 2831 .cfg_regs = pinmux_config_regs,
2830 .data_regs = pinmux_data_regs, 2832 .data_regs = pinmux_data_regs,
2831 2833
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index d44e7f02069b..df0ae21a5ac8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -368,7 +368,7 @@ enum {
368 PINMUX_MARK_END, 368 PINMUX_MARK_END,
369}; 369};
370 370
371static pinmux_enum_t pinmux_data[] = { 371static const pinmux_enum_t pinmux_data[] = {
372 372
373 /* specify valid pin states for each pin in GPIO mode */ 373 /* specify valid pin states for each pin in GPIO mode */
374 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), 374 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
@@ -929,11 +929,214 @@ static pinmux_enum_t pinmux_data[] = {
929 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), 929 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
930}; 930};
931 931
932static struct pinmux_gpio pinmux_gpios[] = { 932static struct sh_pfc_pin pinmux_pins[] = {
933
934 /* PORT */
935 GPIO_PORT_ALL(), 933 GPIO_PORT_ALL(),
934};
936 935
936/* - MMCIF ------------------------------------------------------------------ */
937static const unsigned int mmc0_data1_0_pins[] = {
938 /* D[0] */
939 84,
940};
941static const unsigned int mmc0_data1_0_mux[] = {
942 MMCD0_0_MARK,
943};
944static const unsigned int mmc0_data4_0_pins[] = {
945 /* D[0:3] */
946 84, 85, 86, 87,
947};
948static const unsigned int mmc0_data4_0_mux[] = {
949 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
950};
951static const unsigned int mmc0_data8_0_pins[] = {
952 /* D[0:7] */
953 84, 85, 86, 87, 88, 89, 90, 91,
954};
955static const unsigned int mmc0_data8_0_mux[] = {
956 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
957 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
958};
959static const unsigned int mmc0_ctrl_0_pins[] = {
960 /* CMD, CLK */
961 92, 99,
962};
963static const unsigned int mmc0_ctrl_0_mux[] = {
964 MMCCMD0_MARK, MMCCLK0_MARK,
965};
966
967static const unsigned int mmc0_data1_1_pins[] = {
968 /* D[0] */
969 54,
970};
971static const unsigned int mmc0_data1_1_mux[] = {
972 MMCD1_0_MARK,
973};
974static const unsigned int mmc0_data4_1_pins[] = {
975 /* D[0:3] */
976 54, 55, 56, 57,
977};
978static const unsigned int mmc0_data4_1_mux[] = {
979 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
980};
981static const unsigned int mmc0_data8_1_pins[] = {
982 /* D[0:7] */
983 54, 55, 56, 57, 58, 59, 60, 61,
984};
985static const unsigned int mmc0_data8_1_mux[] = {
986 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
987 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
988};
989static const unsigned int mmc0_ctrl_1_pins[] = {
990 /* CMD, CLK */
991 67, 66,
992};
993static const unsigned int mmc0_ctrl_1_mux[] = {
994 MMCCMD1_MARK, MMCCLK1_MARK,
995};
996/* - SDHI0 ------------------------------------------------------------------ */
997static const unsigned int sdhi0_data1_pins[] = {
998 /* D0 */
999 173,
1000};
1001static const unsigned int sdhi0_data1_mux[] = {
1002 SDHID0_0_MARK,
1003};
1004static const unsigned int sdhi0_data4_pins[] = {
1005 /* D[0:3] */
1006 173, 174, 175, 176,
1007};
1008static const unsigned int sdhi0_data4_mux[] = {
1009 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1010};
1011static const unsigned int sdhi0_ctrl_pins[] = {
1012 /* CMD, CLK */
1013 177, 171,
1014};
1015static const unsigned int sdhi0_ctrl_mux[] = {
1016 SDHICMD0_MARK, SDHICLK0_MARK,
1017};
1018static const unsigned int sdhi0_cd_pins[] = {
1019 /* CD */
1020 172,
1021};
1022static const unsigned int sdhi0_cd_mux[] = {
1023 SDHICD0_MARK,
1024};
1025static const unsigned int sdhi0_wp_pins[] = {
1026 /* WP */
1027 178,
1028};
1029static const unsigned int sdhi0_wp_mux[] = {
1030 SDHIWP0_MARK,
1031};
1032/* - SDHI1 ------------------------------------------------------------------ */
1033static const unsigned int sdhi1_data1_pins[] = {
1034 /* D0 */
1035 180,
1036};
1037static const unsigned int sdhi1_data1_mux[] = {
1038 SDHID1_0_MARK,
1039};
1040static const unsigned int sdhi1_data4_pins[] = {
1041 /* D[0:3] */
1042 180, 181, 182, 183,
1043};
1044static const unsigned int sdhi1_data4_mux[] = {
1045 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1046};
1047static const unsigned int sdhi1_ctrl_pins[] = {
1048 /* CMD, CLK */
1049 184, 179,
1050};
1051static const unsigned int sdhi1_ctrl_mux[] = {
1052 SDHICMD1_MARK, SDHICLK1_MARK,
1053};
1054
1055static const unsigned int sdhi2_data1_pins[] = {
1056 /* D0 */
1057 186,
1058};
1059static const unsigned int sdhi2_data1_mux[] = {
1060 SDHID2_0_MARK,
1061};
1062static const unsigned int sdhi2_data4_pins[] = {
1063 /* D[0:3] */
1064 186, 187, 188, 189,
1065};
1066static const unsigned int sdhi2_data4_mux[] = {
1067 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1068};
1069static const unsigned int sdhi2_ctrl_pins[] = {
1070 /* CMD, CLK */
1071 190, 185,
1072};
1073static const unsigned int sdhi2_ctrl_mux[] = {
1074 SDHICMD2_MARK, SDHICLK2_MARK,
1075};
1076
1077static const struct sh_pfc_pin_group pinmux_groups[] = {
1078 SH_PFC_PIN_GROUP(mmc0_data1_0),
1079 SH_PFC_PIN_GROUP(mmc0_data4_0),
1080 SH_PFC_PIN_GROUP(mmc0_data8_0),
1081 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
1082 SH_PFC_PIN_GROUP(mmc0_data1_1),
1083 SH_PFC_PIN_GROUP(mmc0_data4_1),
1084 SH_PFC_PIN_GROUP(mmc0_data8_1),
1085 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
1086 SH_PFC_PIN_GROUP(sdhi0_data1),
1087 SH_PFC_PIN_GROUP(sdhi0_data4),
1088 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1089 SH_PFC_PIN_GROUP(sdhi0_cd),
1090 SH_PFC_PIN_GROUP(sdhi0_wp),
1091 SH_PFC_PIN_GROUP(sdhi1_data1),
1092 SH_PFC_PIN_GROUP(sdhi1_data4),
1093 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1094 SH_PFC_PIN_GROUP(sdhi2_data1),
1095 SH_PFC_PIN_GROUP(sdhi2_data4),
1096 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1097};
1098
1099static const char * const mmc0_groups[] = {
1100 "mmc0_data1_0",
1101 "mmc0_data4_0",
1102 "mmc0_data8_0",
1103 "mmc0_ctrl_0",
1104 "mmc0_data1_1",
1105 "mmc0_data4_1",
1106 "mmc0_data8_1",
1107 "mmc0_ctrl_1",
1108};
1109
1110static const char * const sdhi0_groups[] = {
1111 "sdhi0_data1",
1112 "sdhi0_data4",
1113 "sdhi0_ctrl",
1114 "sdhi0_cd",
1115 "sdhi0_wp",
1116};
1117
1118static const char * const sdhi1_groups[] = {
1119 "sdhi1_data1",
1120 "sdhi1_data4",
1121 "sdhi1_ctrl",
1122};
1123
1124static const char * const sdhi2_groups[] = {
1125 "sdhi2_data1",
1126 "sdhi2_data4",
1127 "sdhi2_ctrl",
1128};
1129
1130static const struct sh_pfc_function pinmux_functions[] = {
1131 SH_PFC_FUNCTION(mmc0),
1132 SH_PFC_FUNCTION(sdhi0),
1133 SH_PFC_FUNCTION(sdhi1),
1134 SH_PFC_FUNCTION(sdhi2),
1135};
1136
1137#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1138
1139static const struct pinmux_func pinmux_func_gpios[] = {
937 /* IRQ */ 1140 /* IRQ */
938 GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), 1141 GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1),
939 GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), 1142 GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8),
@@ -1074,18 +1277,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1074 GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), 1277 GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13),
1075 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), 1278 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15),
1076 1279
1077 /* MMCIF(1) */
1078 GPIO_FN(MMCD0_0), GPIO_FN(MMCD0_1), GPIO_FN(MMCD0_2),
1079 GPIO_FN(MMCD0_3), GPIO_FN(MMCD0_4), GPIO_FN(MMCD0_5),
1080 GPIO_FN(MMCD0_6), GPIO_FN(MMCD0_7), GPIO_FN(MMCCMD0),
1081 GPIO_FN(MMCCLK0),
1082
1083 /* MMCIF(2) */
1084 GPIO_FN(MMCD1_0), GPIO_FN(MMCD1_1), GPIO_FN(MMCD1_2),
1085 GPIO_FN(MMCD1_3), GPIO_FN(MMCD1_4), GPIO_FN(MMCD1_5),
1086 GPIO_FN(MMCD1_6), GPIO_FN(MMCD1_7), GPIO_FN(MMCCLK1),
1087 GPIO_FN(MMCCMD1),
1088
1089 /* SPU2 */ 1280 /* SPU2 */
1090 GPIO_FN(VINT_I), 1281 GPIO_FN(VINT_I),
1091 1282
@@ -1182,25 +1373,12 @@ static struct pinmux_gpio pinmux_gpios[] = {
1182 /* HDMI */ 1373 /* HDMI */
1183 GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC), 1374 GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC),
1184 1375
1185 /* SDHI0 */
1186 GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), GPIO_FN(SDHICMD0),
1187 GPIO_FN(SDHIWP0), GPIO_FN(SDHID0_0), GPIO_FN(SDHID0_1),
1188 GPIO_FN(SDHID0_2), GPIO_FN(SDHID0_3),
1189
1190 /* SDHI1 */
1191 GPIO_FN(SDHICLK1), GPIO_FN(SDHICMD1), GPIO_FN(SDHID1_0),
1192 GPIO_FN(SDHID1_1), GPIO_FN(SDHID1_2), GPIO_FN(SDHID1_3),
1193
1194 /* SDHI2 */
1195 GPIO_FN(SDHICLK2), GPIO_FN(SDHICMD2), GPIO_FN(SDHID2_0),
1196 GPIO_FN(SDHID2_1), GPIO_FN(SDHID2_2), GPIO_FN(SDHID2_3),
1197
1198 /* SDENC */ 1376 /* SDENC */
1199 GPIO_FN(SDENC_CPG), 1377 GPIO_FN(SDENC_CPG),
1200 GPIO_FN(SDENC_DV_CLKI), 1378 GPIO_FN(SDENC_DV_CLKI),
1201}; 1379};
1202 1380
1203static struct pinmux_cfg_reg pinmux_config_regs[] = { 1381static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1204 PORTCR(0, 0xE6051000), /* PORT0CR */ 1382 PORTCR(0, 0xE6051000), /* PORT0CR */
1205 PORTCR(1, 0xE6051001), /* PORT1CR */ 1383 PORTCR(1, 0xE6051001), /* PORT1CR */
1206 PORTCR(2, 0xE6051002), /* PORT2CR */ 1384 PORTCR(2, 0xE6051002), /* PORT2CR */
@@ -1472,7 +1650,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1472 { }, 1650 { },
1473}; 1651};
1474 1652
1475static struct pinmux_data_reg pinmux_data_regs[] = { 1653static const struct pinmux_data_reg pinmux_data_regs[] = {
1476 { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) { 1654 { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
1477 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, 1655 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
1478 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, 1656 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
@@ -1597,56 +1775,59 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1597 1775
1598#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) 1776#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
1599#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) 1777#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
1600static struct pinmux_irq pinmux_irqs[] = { 1778static const struct pinmux_irq pinmux_irqs[] = {
1601 PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0), 1779 PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
1602 PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0), 1780 PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
1603 PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0), 1781 PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
1604 PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0), 1782 PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16),
1605 PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0), 1783 PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163),
1606 PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0), 1784 PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18),
1607 PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0), 1785 PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164),
1608 PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0), 1786 PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167),
1609 PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0), 1787 PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168),
1610 PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0), 1788 PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169),
1611 PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0), 1789 PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65),
1612 PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0), 1790 PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67),
1613 PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0), 1791 PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137),
1614 PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0), 1792 PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145),
1615 PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0), 1793 PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146),
1616 PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0), 1794 PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147),
1617 PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0), 1795 PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170),
1618 PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0), 1796 PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85),
1619 PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0), 1797 PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86),
1620 PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0), 1798 PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87),
1621 PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0), 1799 PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92),
1622 PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0), 1800 PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93),
1623 PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0), 1801 PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94),
1624 PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0), 1802 PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95),
1625 PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0), 1803 PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112),
1626 PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0), 1804 PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119),
1627 PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0), 1805 PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172),
1628 PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0), 1806 PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180),
1629 PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0), 1807 PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181),
1630 PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0), 1808 PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182),
1631 PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0), 1809 PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183),
1632 PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0), 1810 PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
1633}; 1811};
1634 1812
1635struct sh_pfc_soc_info sh7372_pinmux_info = { 1813const struct sh_pfc_soc_info sh7372_pinmux_info = {
1636 .name = "sh7372_pfc", 1814 .name = "sh7372_pfc",
1637 .reserved_id = PINMUX_RESERVED,
1638 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1639 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 1815 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1640 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 1816 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1641 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, 1817 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1642 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 1818 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1643 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1644 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1819 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1645 1820
1646 .first_gpio = GPIO_PORT0, 1821 .pins = pinmux_pins,
1647 .last_gpio = GPIO_FN_SDENC_DV_CLKI, 1822 .nr_pins = ARRAY_SIZE(pinmux_pins),
1823 .groups = pinmux_groups,
1824 .nr_groups = ARRAY_SIZE(pinmux_groups),
1825 .functions = pinmux_functions,
1826 .nr_functions = ARRAY_SIZE(pinmux_functions),
1827
1828 .func_gpios = pinmux_func_gpios,
1829 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1648 1830
1649 .gpios = pinmux_gpios,
1650 .cfg_regs = pinmux_config_regs, 1831 .cfg_regs = pinmux_config_regs,
1651 .data_regs = pinmux_data_regs, 1832 .data_regs = pinmux_data_regs,
1652 1833
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 6f15c03077a0..587f7772abf2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -18,18 +18,18 @@
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 20 */
21#include <linux/io.h>
21#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/pinctrl/pinconf-generic.h>
24
22#include <mach/sh73a0.h> 25#include <mach/sh73a0.h>
23#include <mach/irqs.h> 26#include <mach/irqs.h>
24 27
28#include "core.h"
25#include "sh_pfc.h" 29#include "sh_pfc.h"
26 30
27#define CPU_ALL_PORT(fn, pfx, sfx) \ 31#define CPU_ALL_PORT(fn, pfx, sfx) \
28 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ 32 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
29 PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \
30 PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \
31 PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \
32 PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \
33 PORT_10(fn, pfx##10, sfx), \ 33 PORT_10(fn, pfx##10, sfx), \
34 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \ 34 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
35 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \ 35 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
@@ -66,14 +66,6 @@ enum {
66 PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */ 66 PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
67 PINMUX_INPUT_END, 67 PINMUX_INPUT_END,
68 68
69 PINMUX_INPUT_PULLUP_BEGIN,
70 PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
71 PINMUX_INPUT_PULLUP_END,
72
73 PINMUX_INPUT_PULLDOWN_BEGIN,
74 PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
75 PINMUX_INPUT_PULLDOWN_END,
76
77 PINMUX_OUTPUT_BEGIN, 69 PINMUX_OUTPUT_BEGIN,
78 PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */ 70 PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
79 PINMUX_OUTPUT_END, 71 PINMUX_OUTPUT_END,
@@ -468,328 +460,15 @@ enum {
468 EDBGREQ_PD_MARK, 460 EDBGREQ_PD_MARK,
469 EDBGREQ_PU_MARK, 461 EDBGREQ_PU_MARK,
470 462
471 /* Functions with pull-ups */
472 KEYIN0_PU_MARK,
473 KEYIN1_PU_MARK,
474 KEYIN2_PU_MARK,
475 KEYIN3_PU_MARK,
476 KEYIN4_PU_MARK,
477 KEYIN5_PU_MARK,
478 KEYIN6_PU_MARK,
479 KEYIN7_PU_MARK,
480 SDHICD0_PU_MARK,
481 SDHID0_0_PU_MARK,
482 SDHID0_1_PU_MARK,
483 SDHID0_2_PU_MARK,
484 SDHID0_3_PU_MARK,
485 SDHICMD0_PU_MARK,
486 SDHIWP0_PU_MARK,
487 SDHID1_0_PU_MARK,
488 SDHID1_1_PU_MARK,
489 SDHID1_2_PU_MARK,
490 SDHID1_3_PU_MARK,
491 SDHICMD1_PU_MARK,
492 SDHID2_0_PU_MARK,
493 SDHID2_1_PU_MARK,
494 SDHID2_2_PU_MARK,
495 SDHID2_3_PU_MARK,
496 SDHICMD2_PU_MARK,
497 MMCCMD0_PU_MARK,
498 MMCCMD1_PU_MARK,
499 MMCD0_0_PU_MARK,
500 MMCD0_1_PU_MARK,
501 MMCD0_2_PU_MARK,
502 MMCD0_3_PU_MARK,
503 MMCD0_4_PU_MARK,
504 MMCD0_5_PU_MARK,
505 MMCD0_6_PU_MARK,
506 MMCD0_7_PU_MARK,
507 FSIBISLD_PU_MARK,
508 FSIACK_PU_MARK,
509 FSIAILR_PU_MARK,
510 FSIAIBT_PU_MARK,
511 FSIAISLD_PU_MARK,
512
513 PINMUX_MARK_END, 463 PINMUX_MARK_END,
514}; 464};
515 465
516static pinmux_enum_t pinmux_data[] = { 466#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
517 /* specify valid pin states for each pin in GPIO mode */ 467#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
518 468
519 /* Table 25-1 (I/O and Pull U/D) */ 469static const pinmux_enum_t pinmux_data[] = {
520 PORT_DATA_I_PD(0), 470 /* specify valid pin states for each pin in GPIO mode */
521 PORT_DATA_I_PU(1), 471 PINMUX_DATA_GP_ALL(),
522 PORT_DATA_I_PU(2),
523 PORT_DATA_I_PU(3),
524 PORT_DATA_I_PU(4),
525 PORT_DATA_I_PU(5),
526 PORT_DATA_I_PU(6),
527 PORT_DATA_I_PU(7),
528 PORT_DATA_I_PU(8),
529 PORT_DATA_I_PD(9),
530 PORT_DATA_I_PD(10),
531 PORT_DATA_I_PU_PD(11),
532 PORT_DATA_IO_PU_PD(12),
533 PORT_DATA_IO_PU_PD(13),
534 PORT_DATA_IO_PU_PD(14),
535 PORT_DATA_IO_PU_PD(15),
536 PORT_DATA_IO_PD(16),
537 PORT_DATA_IO_PD(17),
538 PORT_DATA_IO_PU(18),
539 PORT_DATA_IO_PU(19),
540 PORT_DATA_O(20),
541 PORT_DATA_O(21),
542 PORT_DATA_O(22),
543 PORT_DATA_O(23),
544 PORT_DATA_O(24),
545 PORT_DATA_I_PD(25),
546 PORT_DATA_I_PD(26),
547 PORT_DATA_IO_PU(27),
548 PORT_DATA_IO_PU(28),
549 PORT_DATA_IO_PD(29),
550 PORT_DATA_IO_PD(30),
551 PORT_DATA_IO_PU(31),
552 PORT_DATA_IO_PD(32),
553 PORT_DATA_I_PU_PD(33),
554 PORT_DATA_IO_PD(34),
555 PORT_DATA_I_PU_PD(35),
556 PORT_DATA_IO_PD(36),
557 PORT_DATA_IO(37),
558 PORT_DATA_O(38),
559 PORT_DATA_I_PU(39),
560 PORT_DATA_I_PU_PD(40),
561 PORT_DATA_O(41),
562 PORT_DATA_IO_PD(42),
563 PORT_DATA_IO_PU_PD(43),
564 PORT_DATA_IO_PU_PD(44),
565 PORT_DATA_IO_PD(45),
566 PORT_DATA_IO_PD(46),
567 PORT_DATA_IO_PD(47),
568 PORT_DATA_I_PD(48),
569 PORT_DATA_IO_PU_PD(49),
570 PORT_DATA_IO_PD(50),
571
572 PORT_DATA_IO_PD(51),
573 PORT_DATA_O(52),
574 PORT_DATA_IO_PU_PD(53),
575 PORT_DATA_IO_PU_PD(54),
576 PORT_DATA_IO_PD(55),
577 PORT_DATA_I_PU_PD(56),
578 PORT_DATA_IO(57),
579 PORT_DATA_IO(58),
580 PORT_DATA_IO(59),
581 PORT_DATA_IO(60),
582 PORT_DATA_IO(61),
583 PORT_DATA_IO_PD(62),
584 PORT_DATA_IO_PD(63),
585 PORT_DATA_IO_PU_PD(64),
586 PORT_DATA_IO_PD(65),
587 PORT_DATA_IO_PU_PD(66),
588 PORT_DATA_IO_PU_PD(67),
589 PORT_DATA_IO_PU_PD(68),
590 PORT_DATA_IO_PU_PD(69),
591 PORT_DATA_IO_PU_PD(70),
592 PORT_DATA_IO_PU_PD(71),
593 PORT_DATA_IO_PU_PD(72),
594 PORT_DATA_I_PU_PD(73),
595 PORT_DATA_IO_PU(74),
596 PORT_DATA_IO_PU(75),
597 PORT_DATA_IO_PU(76),
598 PORT_DATA_IO_PU(77),
599 PORT_DATA_IO_PU(78),
600 PORT_DATA_IO_PU(79),
601 PORT_DATA_IO_PU(80),
602 PORT_DATA_IO_PU(81),
603 PORT_DATA_IO_PU(82),
604 PORT_DATA_IO_PU(83),
605 PORT_DATA_IO_PU(84),
606 PORT_DATA_IO_PU(85),
607 PORT_DATA_IO_PU(86),
608 PORT_DATA_IO_PU(87),
609 PORT_DATA_IO_PU(88),
610 PORT_DATA_IO_PU(89),
611 PORT_DATA_O(90),
612 PORT_DATA_IO_PU(91),
613 PORT_DATA_O(92),
614 PORT_DATA_IO_PU(93),
615 PORT_DATA_O(94),
616 PORT_DATA_I_PU_PD(95),
617 PORT_DATA_IO(96),
618 PORT_DATA_IO(97),
619 PORT_DATA_IO(98),
620 PORT_DATA_I_PU(99),
621 PORT_DATA_O(100),
622 PORT_DATA_O(101),
623 PORT_DATA_I_PU(102),
624 PORT_DATA_IO_PD(103),
625 PORT_DATA_I_PU_PD(104),
626 PORT_DATA_I_PD(105),
627 PORT_DATA_I_PD(106),
628 PORT_DATA_I_PU_PD(107),
629 PORT_DATA_I_PU_PD(108),
630 PORT_DATA_IO_PD(109),
631 PORT_DATA_IO_PD(110),
632 PORT_DATA_IO_PU_PD(111),
633 PORT_DATA_IO_PU_PD(112),
634 PORT_DATA_IO_PU_PD(113),
635 PORT_DATA_IO_PD(114),
636 PORT_DATA_IO_PU(115),
637 PORT_DATA_IO_PU(116),
638 PORT_DATA_IO_PU_PD(117),
639 PORT_DATA_IO_PU_PD(118),
640 PORT_DATA_IO_PD(128),
641
642 PORT_DATA_IO_PD(129),
643 PORT_DATA_IO_PU_PD(130),
644 PORT_DATA_IO_PD(131),
645 PORT_DATA_IO_PD(132),
646 PORT_DATA_IO_PD(133),
647 PORT_DATA_IO_PU_PD(134),
648 PORT_DATA_IO_PU_PD(135),
649 PORT_DATA_IO_PU_PD(136),
650 PORT_DATA_IO_PU_PD(137),
651 PORT_DATA_IO_PD(138),
652 PORT_DATA_IO_PD(139),
653 PORT_DATA_IO_PD(140),
654 PORT_DATA_IO_PD(141),
655 PORT_DATA_IO_PD(142),
656 PORT_DATA_IO_PD(143),
657 PORT_DATA_IO_PU_PD(144),
658 PORT_DATA_IO_PD(145),
659 PORT_DATA_IO_PU_PD(146),
660 PORT_DATA_IO_PU_PD(147),
661 PORT_DATA_IO_PU_PD(148),
662 PORT_DATA_IO_PU_PD(149),
663 PORT_DATA_I_PU_PD(150),
664 PORT_DATA_IO_PU_PD(151),
665 PORT_DATA_IO_PU_PD(152),
666 PORT_DATA_IO_PD(153),
667 PORT_DATA_IO_PD(154),
668 PORT_DATA_I_PU_PD(155),
669 PORT_DATA_IO_PU_PD(156),
670 PORT_DATA_I_PD(157),
671 PORT_DATA_IO_PD(158),
672 PORT_DATA_IO_PU_PD(159),
673 PORT_DATA_IO_PU_PD(160),
674 PORT_DATA_I_PU_PD(161),
675 PORT_DATA_I_PU_PD(162),
676 PORT_DATA_IO_PU_PD(163),
677 PORT_DATA_I_PU_PD(164),
678 PORT_DATA_IO_PD(192),
679 PORT_DATA_IO_PU_PD(193),
680 PORT_DATA_IO_PD(194),
681 PORT_DATA_IO_PU_PD(195),
682 PORT_DATA_IO_PD(196),
683 PORT_DATA_IO_PD(197),
684 PORT_DATA_IO_PD(198),
685 PORT_DATA_IO_PD(199),
686 PORT_DATA_IO_PU_PD(200),
687 PORT_DATA_IO_PU_PD(201),
688 PORT_DATA_IO_PU_PD(202),
689 PORT_DATA_IO_PU_PD(203),
690 PORT_DATA_IO_PU_PD(204),
691 PORT_DATA_IO_PU_PD(205),
692 PORT_DATA_IO_PU_PD(206),
693 PORT_DATA_IO_PD(207),
694 PORT_DATA_IO_PD(208),
695 PORT_DATA_IO_PD(209),
696 PORT_DATA_IO_PD(210),
697 PORT_DATA_IO_PD(211),
698 PORT_DATA_IO_PD(212),
699 PORT_DATA_IO_PD(213),
700 PORT_DATA_IO_PU_PD(214),
701 PORT_DATA_IO_PU_PD(215),
702 PORT_DATA_IO_PD(216),
703 PORT_DATA_IO_PD(217),
704 PORT_DATA_O(218),
705 PORT_DATA_IO_PD(219),
706 PORT_DATA_IO_PD(220),
707 PORT_DATA_IO_PU_PD(221),
708 PORT_DATA_IO_PU_PD(222),
709 PORT_DATA_I_PU_PD(223),
710 PORT_DATA_I_PU_PD(224),
711
712 PORT_DATA_IO_PU_PD(225),
713 PORT_DATA_O(226),
714 PORT_DATA_IO_PU_PD(227),
715 PORT_DATA_I_PU_PD(228),
716 PORT_DATA_I_PD(229),
717 PORT_DATA_IO(230),
718 PORT_DATA_IO_PU_PD(231),
719 PORT_DATA_IO_PU_PD(232),
720 PORT_DATA_I_PU_PD(233),
721 PORT_DATA_IO_PU_PD(234),
722 PORT_DATA_IO_PU_PD(235),
723 PORT_DATA_IO_PU_PD(236),
724 PORT_DATA_IO_PD(237),
725 PORT_DATA_IO_PU_PD(238),
726 PORT_DATA_IO_PU_PD(239),
727 PORT_DATA_IO_PU_PD(240),
728 PORT_DATA_O(241),
729 PORT_DATA_I_PD(242),
730 PORT_DATA_IO_PU_PD(243),
731 PORT_DATA_IO_PU_PD(244),
732 PORT_DATA_IO_PU_PD(245),
733 PORT_DATA_IO_PU_PD(246),
734 PORT_DATA_IO_PU_PD(247),
735 PORT_DATA_IO_PU_PD(248),
736 PORT_DATA_IO_PU_PD(249),
737 PORT_DATA_IO_PU_PD(250),
738 PORT_DATA_IO_PU_PD(251),
739 PORT_DATA_IO_PU_PD(252),
740 PORT_DATA_IO_PU_PD(253),
741 PORT_DATA_IO_PU_PD(254),
742 PORT_DATA_IO_PU_PD(255),
743 PORT_DATA_IO_PU_PD(256),
744 PORT_DATA_IO_PU_PD(257),
745 PORT_DATA_IO_PU_PD(258),
746 PORT_DATA_IO_PU_PD(259),
747 PORT_DATA_IO_PU_PD(260),
748 PORT_DATA_IO_PU_PD(261),
749 PORT_DATA_IO_PU_PD(262),
750 PORT_DATA_IO_PU_PD(263),
751 PORT_DATA_IO_PU_PD(264),
752 PORT_DATA_IO_PU_PD(265),
753 PORT_DATA_IO_PU_PD(266),
754 PORT_DATA_IO_PU_PD(267),
755 PORT_DATA_IO_PU_PD(268),
756 PORT_DATA_IO_PU_PD(269),
757 PORT_DATA_IO_PU_PD(270),
758 PORT_DATA_IO_PU_PD(271),
759 PORT_DATA_IO_PU_PD(272),
760 PORT_DATA_IO_PU_PD(273),
761 PORT_DATA_IO_PU_PD(274),
762 PORT_DATA_IO_PU_PD(275),
763 PORT_DATA_IO_PU_PD(276),
764 PORT_DATA_IO_PU_PD(277),
765 PORT_DATA_IO_PU_PD(278),
766 PORT_DATA_IO_PU_PD(279),
767 PORT_DATA_IO_PU_PD(280),
768 PORT_DATA_O(281),
769 PORT_DATA_O(282),
770 PORT_DATA_I_PU(288),
771 PORT_DATA_IO_PU_PD(289),
772 PORT_DATA_IO_PU_PD(290),
773 PORT_DATA_IO_PU_PD(291),
774 PORT_DATA_IO_PU_PD(292),
775 PORT_DATA_IO_PU_PD(293),
776 PORT_DATA_IO_PU_PD(294),
777 PORT_DATA_IO_PU_PD(295),
778 PORT_DATA_IO_PU_PD(296),
779 PORT_DATA_IO_PU_PD(297),
780 PORT_DATA_IO_PU_PD(298),
781
782 PORT_DATA_IO_PU_PD(299),
783 PORT_DATA_IO_PU_PD(300),
784 PORT_DATA_IO_PU_PD(301),
785 PORT_DATA_IO_PU_PD(302),
786 PORT_DATA_IO_PU_PD(303),
787 PORT_DATA_IO_PU_PD(304),
788 PORT_DATA_IO_PU_PD(305),
789 PORT_DATA_O(306),
790 PORT_DATA_O(307),
791 PORT_DATA_I_PU(308),
792 PORT_DATA_O(309),
793 472
794 /* Table 25-1 (Function 0-7) */ 473 /* Table 25-1 (Function 0-7) */
795 PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), 474 PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
@@ -1358,28 +1037,19 @@ static pinmux_enum_t pinmux_data[] = {
1358 PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), 1037 PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1359 PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), 1038 PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1360 PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), 1039 PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1361 PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU, 1040 PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1362 MSEL4CR_MSEL15_0), 1041 PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1363 PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU, 1042 PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1364 MSEL4CR_MSEL15_0), 1043 PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1365 PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU, 1044 PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
1366 MSEL4CR_MSEL15_0),
1367 PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
1368 MSEL4CR_MSEL15_0),
1369 PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
1370 MSEL4CR_MSEL15_0), \
1371 PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), 1045 PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1372 PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU, 1046 PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
1373 MSEL4CR_MSEL15_0), \
1374 PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), 1047 PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1375 PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU, 1048 PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
1376 MSEL4CR_MSEL15_0), \
1377 PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), 1049 PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1378 PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU, 1050 PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
1379 MSEL4CR_MSEL15_0), \
1380 PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), 1051 PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1381 PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU, 1052 PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
1382 MSEL4CR_MSEL15_0),
1383 PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ 1053 PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1384 PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), 1054 PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1385 PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), 1055 PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
@@ -1485,69 +1155,1791 @@ static pinmux_enum_t pinmux_data[] = {
1485 PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1), 1155 PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1486 PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0), 1156 PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1487 PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), 1157 PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
1158};
1159
1160#define SH73A0_PIN(pin, cfgs) \
1161 { \
1162 .name = __stringify(PORT##pin), \
1163 .enum_id = PORT##pin##_DATA, \
1164 .configs = cfgs, \
1165 }
1166
1167#define __I (SH_PFC_PIN_CFG_INPUT)
1168#define __O (SH_PFC_PIN_CFG_OUTPUT)
1169#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1170#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1171#define __PU (SH_PFC_PIN_CFG_PULL_UP)
1172#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1173
1174#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD)
1175#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU)
1176#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD)
1177#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO)
1178#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD)
1179#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU)
1180#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD)
1181#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O)
1182
1183static struct sh_pfc_pin pinmux_pins[] = {
1184 /* Table 25-1 (I/O and Pull U/D) */
1185 SH73A0_PIN_I_PD(0),
1186 SH73A0_PIN_I_PU(1),
1187 SH73A0_PIN_I_PU(2),
1188 SH73A0_PIN_I_PU(3),
1189 SH73A0_PIN_I_PU(4),
1190 SH73A0_PIN_I_PU(5),
1191 SH73A0_PIN_I_PU(6),
1192 SH73A0_PIN_I_PU(7),
1193 SH73A0_PIN_I_PU(8),
1194 SH73A0_PIN_I_PD(9),
1195 SH73A0_PIN_I_PD(10),
1196 SH73A0_PIN_I_PU_PD(11),
1197 SH73A0_PIN_IO_PU_PD(12),
1198 SH73A0_PIN_IO_PU_PD(13),
1199 SH73A0_PIN_IO_PU_PD(14),
1200 SH73A0_PIN_IO_PU_PD(15),
1201 SH73A0_PIN_IO_PD(16),
1202 SH73A0_PIN_IO_PD(17),
1203 SH73A0_PIN_IO_PU(18),
1204 SH73A0_PIN_IO_PU(19),
1205 SH73A0_PIN_O(20),
1206 SH73A0_PIN_O(21),
1207 SH73A0_PIN_O(22),
1208 SH73A0_PIN_O(23),
1209 SH73A0_PIN_O(24),
1210 SH73A0_PIN_I_PD(25),
1211 SH73A0_PIN_I_PD(26),
1212 SH73A0_PIN_IO_PU(27),
1213 SH73A0_PIN_IO_PU(28),
1214 SH73A0_PIN_IO_PD(29),
1215 SH73A0_PIN_IO_PD(30),
1216 SH73A0_PIN_IO_PU(31),
1217 SH73A0_PIN_IO_PD(32),
1218 SH73A0_PIN_I_PU_PD(33),
1219 SH73A0_PIN_IO_PD(34),
1220 SH73A0_PIN_I_PU_PD(35),
1221 SH73A0_PIN_IO_PD(36),
1222 SH73A0_PIN_IO(37),
1223 SH73A0_PIN_O(38),
1224 SH73A0_PIN_I_PU(39),
1225 SH73A0_PIN_I_PU_PD(40),
1226 SH73A0_PIN_O(41),
1227 SH73A0_PIN_IO_PD(42),
1228 SH73A0_PIN_IO_PU_PD(43),
1229 SH73A0_PIN_IO_PU_PD(44),
1230 SH73A0_PIN_IO_PD(45),
1231 SH73A0_PIN_IO_PD(46),
1232 SH73A0_PIN_IO_PD(47),
1233 SH73A0_PIN_I_PD(48),
1234 SH73A0_PIN_IO_PU_PD(49),
1235 SH73A0_PIN_IO_PD(50),
1236 SH73A0_PIN_IO_PD(51),
1237 SH73A0_PIN_O(52),
1238 SH73A0_PIN_IO_PU_PD(53),
1239 SH73A0_PIN_IO_PU_PD(54),
1240 SH73A0_PIN_IO_PD(55),
1241 SH73A0_PIN_I_PU_PD(56),
1242 SH73A0_PIN_IO(57),
1243 SH73A0_PIN_IO(58),
1244 SH73A0_PIN_IO(59),
1245 SH73A0_PIN_IO(60),
1246 SH73A0_PIN_IO(61),
1247 SH73A0_PIN_IO_PD(62),
1248 SH73A0_PIN_IO_PD(63),
1249 SH73A0_PIN_IO_PU_PD(64),
1250 SH73A0_PIN_IO_PD(65),
1251 SH73A0_PIN_IO_PU_PD(66),
1252 SH73A0_PIN_IO_PU_PD(67),
1253 SH73A0_PIN_IO_PU_PD(68),
1254 SH73A0_PIN_IO_PU_PD(69),
1255 SH73A0_PIN_IO_PU_PD(70),
1256 SH73A0_PIN_IO_PU_PD(71),
1257 SH73A0_PIN_IO_PU_PD(72),
1258 SH73A0_PIN_I_PU_PD(73),
1259 SH73A0_PIN_IO_PU(74),
1260 SH73A0_PIN_IO_PU(75),
1261 SH73A0_PIN_IO_PU(76),
1262 SH73A0_PIN_IO_PU(77),
1263 SH73A0_PIN_IO_PU(78),
1264 SH73A0_PIN_IO_PU(79),
1265 SH73A0_PIN_IO_PU(80),
1266 SH73A0_PIN_IO_PU(81),
1267 SH73A0_PIN_IO_PU(82),
1268 SH73A0_PIN_IO_PU(83),
1269 SH73A0_PIN_IO_PU(84),
1270 SH73A0_PIN_IO_PU(85),
1271 SH73A0_PIN_IO_PU(86),
1272 SH73A0_PIN_IO_PU(87),
1273 SH73A0_PIN_IO_PU(88),
1274 SH73A0_PIN_IO_PU(89),
1275 SH73A0_PIN_O(90),
1276 SH73A0_PIN_IO_PU(91),
1277 SH73A0_PIN_O(92),
1278 SH73A0_PIN_IO_PU(93),
1279 SH73A0_PIN_O(94),
1280 SH73A0_PIN_I_PU_PD(95),
1281 SH73A0_PIN_IO(96),
1282 SH73A0_PIN_IO(97),
1283 SH73A0_PIN_IO(98),
1284 SH73A0_PIN_I_PU(99),
1285 SH73A0_PIN_O(100),
1286 SH73A0_PIN_O(101),
1287 SH73A0_PIN_I_PU(102),
1288 SH73A0_PIN_IO_PD(103),
1289 SH73A0_PIN_I_PU_PD(104),
1290 SH73A0_PIN_I_PD(105),
1291 SH73A0_PIN_I_PD(106),
1292 SH73A0_PIN_I_PU_PD(107),
1293 SH73A0_PIN_I_PU_PD(108),
1294 SH73A0_PIN_IO_PD(109),
1295 SH73A0_PIN_IO_PD(110),
1296 SH73A0_PIN_IO_PU_PD(111),
1297 SH73A0_PIN_IO_PU_PD(112),
1298 SH73A0_PIN_IO_PU_PD(113),
1299 SH73A0_PIN_IO_PD(114),
1300 SH73A0_PIN_IO_PU(115),
1301 SH73A0_PIN_IO_PU(116),
1302 SH73A0_PIN_IO_PU_PD(117),
1303 SH73A0_PIN_IO_PU_PD(118),
1304 SH73A0_PIN_IO_PD(128),
1305 SH73A0_PIN_IO_PD(129),
1306 SH73A0_PIN_IO_PU_PD(130),
1307 SH73A0_PIN_IO_PD(131),
1308 SH73A0_PIN_IO_PD(132),
1309 SH73A0_PIN_IO_PD(133),
1310 SH73A0_PIN_IO_PU_PD(134),
1311 SH73A0_PIN_IO_PU_PD(135),
1312 SH73A0_PIN_IO_PU_PD(136),
1313 SH73A0_PIN_IO_PU_PD(137),
1314 SH73A0_PIN_IO_PD(138),
1315 SH73A0_PIN_IO_PD(139),
1316 SH73A0_PIN_IO_PD(140),
1317 SH73A0_PIN_IO_PD(141),
1318 SH73A0_PIN_IO_PD(142),
1319 SH73A0_PIN_IO_PD(143),
1320 SH73A0_PIN_IO_PU_PD(144),
1321 SH73A0_PIN_IO_PD(145),
1322 SH73A0_PIN_IO_PU_PD(146),
1323 SH73A0_PIN_IO_PU_PD(147),
1324 SH73A0_PIN_IO_PU_PD(148),
1325 SH73A0_PIN_IO_PU_PD(149),
1326 SH73A0_PIN_I_PU_PD(150),
1327 SH73A0_PIN_IO_PU_PD(151),
1328 SH73A0_PIN_IO_PU_PD(152),
1329 SH73A0_PIN_IO_PD(153),
1330 SH73A0_PIN_IO_PD(154),
1331 SH73A0_PIN_I_PU_PD(155),
1332 SH73A0_PIN_IO_PU_PD(156),
1333 SH73A0_PIN_I_PD(157),
1334 SH73A0_PIN_IO_PD(158),
1335 SH73A0_PIN_IO_PU_PD(159),
1336 SH73A0_PIN_IO_PU_PD(160),
1337 SH73A0_PIN_I_PU_PD(161),
1338 SH73A0_PIN_I_PU_PD(162),
1339 SH73A0_PIN_IO_PU_PD(163),
1340 SH73A0_PIN_I_PU_PD(164),
1341 SH73A0_PIN_IO_PD(192),
1342 SH73A0_PIN_IO_PU_PD(193),
1343 SH73A0_PIN_IO_PD(194),
1344 SH73A0_PIN_IO_PU_PD(195),
1345 SH73A0_PIN_IO_PD(196),
1346 SH73A0_PIN_IO_PD(197),
1347 SH73A0_PIN_IO_PD(198),
1348 SH73A0_PIN_IO_PD(199),
1349 SH73A0_PIN_IO_PU_PD(200),
1350 SH73A0_PIN_IO_PU_PD(201),
1351 SH73A0_PIN_IO_PU_PD(202),
1352 SH73A0_PIN_IO_PU_PD(203),
1353 SH73A0_PIN_IO_PU_PD(204),
1354 SH73A0_PIN_IO_PU_PD(205),
1355 SH73A0_PIN_IO_PU_PD(206),
1356 SH73A0_PIN_IO_PD(207),
1357 SH73A0_PIN_IO_PD(208),
1358 SH73A0_PIN_IO_PD(209),
1359 SH73A0_PIN_IO_PD(210),
1360 SH73A0_PIN_IO_PD(211),
1361 SH73A0_PIN_IO_PD(212),
1362 SH73A0_PIN_IO_PD(213),
1363 SH73A0_PIN_IO_PU_PD(214),
1364 SH73A0_PIN_IO_PU_PD(215),
1365 SH73A0_PIN_IO_PD(216),
1366 SH73A0_PIN_IO_PD(217),
1367 SH73A0_PIN_O(218),
1368 SH73A0_PIN_IO_PD(219),
1369 SH73A0_PIN_IO_PD(220),
1370 SH73A0_PIN_IO_PU_PD(221),
1371 SH73A0_PIN_IO_PU_PD(222),
1372 SH73A0_PIN_I_PU_PD(223),
1373 SH73A0_PIN_I_PU_PD(224),
1374 SH73A0_PIN_IO_PU_PD(225),
1375 SH73A0_PIN_O(226),
1376 SH73A0_PIN_IO_PU_PD(227),
1377 SH73A0_PIN_I_PU_PD(228),
1378 SH73A0_PIN_I_PD(229),
1379 SH73A0_PIN_IO(230),
1380 SH73A0_PIN_IO_PU_PD(231),
1381 SH73A0_PIN_IO_PU_PD(232),
1382 SH73A0_PIN_I_PU_PD(233),
1383 SH73A0_PIN_IO_PU_PD(234),
1384 SH73A0_PIN_IO_PU_PD(235),
1385 SH73A0_PIN_IO_PU_PD(236),
1386 SH73A0_PIN_IO_PD(237),
1387 SH73A0_PIN_IO_PU_PD(238),
1388 SH73A0_PIN_IO_PU_PD(239),
1389 SH73A0_PIN_IO_PU_PD(240),
1390 SH73A0_PIN_O(241),
1391 SH73A0_PIN_I_PD(242),
1392 SH73A0_PIN_IO_PU_PD(243),
1393 SH73A0_PIN_IO_PU_PD(244),
1394 SH73A0_PIN_IO_PU_PD(245),
1395 SH73A0_PIN_IO_PU_PD(246),
1396 SH73A0_PIN_IO_PU_PD(247),
1397 SH73A0_PIN_IO_PU_PD(248),
1398 SH73A0_PIN_IO_PU_PD(249),
1399 SH73A0_PIN_IO_PU_PD(250),
1400 SH73A0_PIN_IO_PU_PD(251),
1401 SH73A0_PIN_IO_PU_PD(252),
1402 SH73A0_PIN_IO_PU_PD(253),
1403 SH73A0_PIN_IO_PU_PD(254),
1404 SH73A0_PIN_IO_PU_PD(255),
1405 SH73A0_PIN_IO_PU_PD(256),
1406 SH73A0_PIN_IO_PU_PD(257),
1407 SH73A0_PIN_IO_PU_PD(258),
1408 SH73A0_PIN_IO_PU_PD(259),
1409 SH73A0_PIN_IO_PU_PD(260),
1410 SH73A0_PIN_IO_PU_PD(261),
1411 SH73A0_PIN_IO_PU_PD(262),
1412 SH73A0_PIN_IO_PU_PD(263),
1413 SH73A0_PIN_IO_PU_PD(264),
1414 SH73A0_PIN_IO_PU_PD(265),
1415 SH73A0_PIN_IO_PU_PD(266),
1416 SH73A0_PIN_IO_PU_PD(267),
1417 SH73A0_PIN_IO_PU_PD(268),
1418 SH73A0_PIN_IO_PU_PD(269),
1419 SH73A0_PIN_IO_PU_PD(270),
1420 SH73A0_PIN_IO_PU_PD(271),
1421 SH73A0_PIN_IO_PU_PD(272),
1422 SH73A0_PIN_IO_PU_PD(273),
1423 SH73A0_PIN_IO_PU_PD(274),
1424 SH73A0_PIN_IO_PU_PD(275),
1425 SH73A0_PIN_IO_PU_PD(276),
1426 SH73A0_PIN_IO_PU_PD(277),
1427 SH73A0_PIN_IO_PU_PD(278),
1428 SH73A0_PIN_IO_PU_PD(279),
1429 SH73A0_PIN_IO_PU_PD(280),
1430 SH73A0_PIN_O(281),
1431 SH73A0_PIN_O(282),
1432 SH73A0_PIN_I_PU(288),
1433 SH73A0_PIN_IO_PU_PD(289),
1434 SH73A0_PIN_IO_PU_PD(290),
1435 SH73A0_PIN_IO_PU_PD(291),
1436 SH73A0_PIN_IO_PU_PD(292),
1437 SH73A0_PIN_IO_PU_PD(293),
1438 SH73A0_PIN_IO_PU_PD(294),
1439 SH73A0_PIN_IO_PU_PD(295),
1440 SH73A0_PIN_IO_PU_PD(296),
1441 SH73A0_PIN_IO_PU_PD(297),
1442 SH73A0_PIN_IO_PU_PD(298),
1443 SH73A0_PIN_IO_PU_PD(299),
1444 SH73A0_PIN_IO_PU_PD(300),
1445 SH73A0_PIN_IO_PU_PD(301),
1446 SH73A0_PIN_IO_PU_PD(302),
1447 SH73A0_PIN_IO_PU_PD(303),
1448 SH73A0_PIN_IO_PU_PD(304),
1449 SH73A0_PIN_IO_PU_PD(305),
1450 SH73A0_PIN_O(306),
1451 SH73A0_PIN_O(307),
1452 SH73A0_PIN_I_PU(308),
1453 SH73A0_PIN_O(309),
1454};
1455
1456static const struct pinmux_range pinmux_ranges[] = {
1457 {.begin = 0, .end = 118,},
1458 {.begin = 128, .end = 164,},
1459 {.begin = 192, .end = 282,},
1460 {.begin = 288, .end = 309,},
1461};
1462
1463/* Pin numbers for pins without a corresponding GPIO port number are computed
1464 * from the row and column numbers with a 1000 offset to avoid collisions with
1465 * GPIO port numbers.
1466 */
1467#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
1468
1469/* - BSC -------------------------------------------------------------------- */
1470static const unsigned int bsc_data_0_7_pins[] = {
1471 /* D[0:7] */
1472 74, 75, 76, 77, 78, 79, 80, 81,
1473};
1474static const unsigned int bsc_data_0_7_mux[] = {
1475 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1476 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1477};
1478static const unsigned int bsc_data_8_15_pins[] = {
1479 /* D[8:15] */
1480 82, 83, 84, 85, 86, 87, 88, 89,
1481};
1482static const unsigned int bsc_data_8_15_mux[] = {
1483 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1484 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1485};
1486static const unsigned int bsc_cs4_pins[] = {
1487 /* CS */
1488 90,
1489};
1490static const unsigned int bsc_cs4_mux[] = {
1491 CS4__MARK,
1492};
1493static const unsigned int bsc_cs5_a_pins[] = {
1494 /* CS */
1495 91,
1496};
1497static const unsigned int bsc_cs5_a_mux[] = {
1498 CS5A__MARK,
1499};
1500static const unsigned int bsc_cs5_b_pins[] = {
1501 /* CS */
1502 92,
1503};
1504static const unsigned int bsc_cs5_b_mux[] = {
1505 CS5B__MARK,
1506};
1507static const unsigned int bsc_cs6_a_pins[] = {
1508 /* CS */
1509 94,
1510};
1511static const unsigned int bsc_cs6_a_mux[] = {
1512 CS6A__MARK,
1513};
1514static const unsigned int bsc_cs6_b_pins[] = {
1515 /* CS */
1516 93,
1517};
1518static const unsigned int bsc_cs6_b_mux[] = {
1519 CS6B__MARK,
1520};
1521static const unsigned int bsc_rd_pins[] = {
1522 /* RD */
1523 96,
1524};
1525static const unsigned int bsc_rd_mux[] = {
1526 RD__FSC_MARK,
1527};
1528static const unsigned int bsc_rdwr_0_pins[] = {
1529 /* RDWR */
1530 91,
1531};
1532static const unsigned int bsc_rdwr_0_mux[] = {
1533 PORT91_RDWR_MARK,
1534};
1535static const unsigned int bsc_rdwr_1_pins[] = {
1536 /* RDWR */
1537 97,
1538};
1539static const unsigned int bsc_rdwr_1_mux[] = {
1540 RDWR_FWE_MARK,
1541};
1542static const unsigned int bsc_rdwr_2_pins[] = {
1543 /* RDWR */
1544 149,
1545};
1546static const unsigned int bsc_rdwr_2_mux[] = {
1547 PORT149_RDWR_MARK,
1548};
1549static const unsigned int bsc_we0_pins[] = {
1550 /* WE0 */
1551 97,
1552};
1553static const unsigned int bsc_we0_mux[] = {
1554 WE0__FWE_MARK,
1555};
1556static const unsigned int bsc_we1_pins[] = {
1557 /* WE1 */
1558 98,
1559};
1560static const unsigned int bsc_we1_mux[] = {
1561 WE1__MARK,
1562};
1563/* - FSIA ------------------------------------------------------------------- */
1564static const unsigned int fsia_mclk_in_pins[] = {
1565 /* CK */
1566 49,
1567};
1568static const unsigned int fsia_mclk_in_mux[] = {
1569 FSIACK_MARK,
1570};
1571static const unsigned int fsia_mclk_out_pins[] = {
1572 /* OMC */
1573 49,
1574};
1575static const unsigned int fsia_mclk_out_mux[] = {
1576 FSIAOMC_MARK,
1577};
1578static const unsigned int fsia_sclk_in_pins[] = {
1579 /* ILR, IBT */
1580 50, 51,
1581};
1582static const unsigned int fsia_sclk_in_mux[] = {
1583 FSIAILR_MARK, FSIAIBT_MARK,
1584};
1585static const unsigned int fsia_sclk_out_pins[] = {
1586 /* OLR, OBT */
1587 50, 51,
1588};
1589static const unsigned int fsia_sclk_out_mux[] = {
1590 FSIAOLR_MARK, FSIAOBT_MARK,
1591};
1592static const unsigned int fsia_data_in_pins[] = {
1593 /* ISLD */
1594 55,
1595};
1596static const unsigned int fsia_data_in_mux[] = {
1597 FSIAISLD_MARK,
1598};
1599static const unsigned int fsia_data_out_pins[] = {
1600 /* OSLD */
1601 52,
1602};
1603static const unsigned int fsia_data_out_mux[] = {
1604 FSIAOSLD_MARK,
1605};
1606static const unsigned int fsia_spdif_pins[] = {
1607 /* SPDIF */
1608 53,
1609};
1610static const unsigned int fsia_spdif_mux[] = {
1611 FSIASPDIF_MARK,
1612};
1613/* - FSIB ------------------------------------------------------------------- */
1614static const unsigned int fsib_mclk_in_pins[] = {
1615 /* CK */
1616 54,
1617};
1618static const unsigned int fsib_mclk_in_mux[] = {
1619 FSIBCK_MARK,
1620};
1621static const unsigned int fsib_mclk_out_pins[] = {
1622 /* OMC */
1623 54,
1624};
1625static const unsigned int fsib_mclk_out_mux[] = {
1626 FSIBOMC_MARK,
1627};
1628static const unsigned int fsib_sclk_in_pins[] = {
1629 /* ILR, IBT */
1630 37, 36,
1631};
1632static const unsigned int fsib_sclk_in_mux[] = {
1633 FSIBILR_MARK, FSIBIBT_MARK,
1634};
1635static const unsigned int fsib_sclk_out_pins[] = {
1636 /* OLR, OBT */
1637 37, 36,
1638};
1639static const unsigned int fsib_sclk_out_mux[] = {
1640 FSIBOLR_MARK, FSIBOBT_MARK,
1641};
1642static const unsigned int fsib_data_in_pins[] = {
1643 /* ISLD */
1644 39,
1645};
1646static const unsigned int fsib_data_in_mux[] = {
1647 FSIBISLD_MARK,
1648};
1649static const unsigned int fsib_data_out_pins[] = {
1650 /* OSLD */
1651 38,
1652};
1653static const unsigned int fsib_data_out_mux[] = {
1654 FSIBOSLD_MARK,
1655};
1656static const unsigned int fsib_spdif_pins[] = {
1657 /* SPDIF */
1658 53,
1659};
1660static const unsigned int fsib_spdif_mux[] = {
1661 FSIBSPDIF_MARK,
1662};
1663/* - FSIC ------------------------------------------------------------------- */
1664static const unsigned int fsic_mclk_in_pins[] = {
1665 /* CK */
1666 54,
1667};
1668static const unsigned int fsic_mclk_in_mux[] = {
1669 FSICCK_MARK,
1670};
1671static const unsigned int fsic_mclk_out_pins[] = {
1672 /* OMC */
1673 54,
1674};
1675static const unsigned int fsic_mclk_out_mux[] = {
1676 FSICOMC_MARK,
1677};
1678static const unsigned int fsic_sclk_in_pins[] = {
1679 /* ILR, IBT */
1680 46, 45,
1681};
1682static const unsigned int fsic_sclk_in_mux[] = {
1683 FSICILR_MARK, FSICIBT_MARK,
1684};
1685static const unsigned int fsic_sclk_out_pins[] = {
1686 /* OLR, OBT */
1687 46, 45,
1688};
1689static const unsigned int fsic_sclk_out_mux[] = {
1690 FSICOLR_MARK, FSICOBT_MARK,
1691};
1692static const unsigned int fsic_data_in_pins[] = {
1693 /* ISLD */
1694 48,
1695};
1696static const unsigned int fsic_data_in_mux[] = {
1697 FSICISLD_MARK,
1698};
1699static const unsigned int fsic_data_out_pins[] = {
1700 /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1701 47, 44, 42, 16,
1702};
1703static const unsigned int fsic_data_out_mux[] = {
1704 FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1705};
1706static const unsigned int fsic_spdif_0_pins[] = {
1707 /* SPDIF */
1708 53,
1709};
1710static const unsigned int fsic_spdif_0_mux[] = {
1711 PORT53_FSICSPDIF_MARK,
1712};
1713static const unsigned int fsic_spdif_1_pins[] = {
1714 /* SPDIF */
1715 47,
1716};
1717static const unsigned int fsic_spdif_1_mux[] = {
1718 PORT47_FSICSPDIF_MARK,
1719};
1720/* - FSID ------------------------------------------------------------------- */
1721static const unsigned int fsid_sclk_in_pins[] = {
1722 /* ILR, IBT */
1723 46, 45,
1724};
1725static const unsigned int fsid_sclk_in_mux[] = {
1726 FSIDILR_MARK, FSIDIBT_MARK,
1727};
1728static const unsigned int fsid_sclk_out_pins[] = {
1729 /* OLR, OBT */
1730 46, 45,
1731};
1732static const unsigned int fsid_sclk_out_mux[] = {
1733 FSIDOLR_MARK, FSIDOBT_MARK,
1734};
1735static const unsigned int fsid_data_in_pins[] = {
1736 /* ISLD */
1737 48,
1738};
1739static const unsigned int fsid_data_in_mux[] = {
1740 FSIDISLD_MARK,
1741};
1742/* - I2C2 ------------------------------------------------------------------- */
1743static const unsigned int i2c2_0_pins[] = {
1744 /* SCL, SDA */
1745 237, 236,
1746};
1747static const unsigned int i2c2_0_mux[] = {
1748 PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
1749};
1750static const unsigned int i2c2_1_pins[] = {
1751 /* SCL, SDA */
1752 27, 28,
1753};
1754static const unsigned int i2c2_1_mux[] = {
1755 PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
1756};
1757static const unsigned int i2c2_2_pins[] = {
1758 /* SCL, SDA */
1759 115, 116,
1760};
1761static const unsigned int i2c2_2_mux[] = {
1762 PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
1763};
1764/* - I2C3 ------------------------------------------------------------------- */
1765static const unsigned int i2c3_0_pins[] = {
1766 /* SCL, SDA */
1767 248, 249,
1768};
1769static const unsigned int i2c3_0_mux[] = {
1770 PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
1771};
1772static const unsigned int i2c3_1_pins[] = {
1773 /* SCL, SDA */
1774 27, 28,
1775};
1776static const unsigned int i2c3_1_mux[] = {
1777 PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
1778};
1779static const unsigned int i2c3_2_pins[] = {
1780 /* SCL, SDA */
1781 115, 116,
1782};
1783static const unsigned int i2c3_2_mux[] = {
1784 PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
1785};
1786/* - IrDA ------------------------------------------------------------------- */
1787static const unsigned int irda_0_pins[] = {
1788 /* OUT, IN, FIRSEL */
1789 241, 242, 243,
1790};
1791static const unsigned int irda_0_mux[] = {
1792 PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
1793};
1794static const unsigned int irda_1_pins[] = {
1795 /* OUT, IN, FIRSEL */
1796 49, 53, 54,
1797};
1798static const unsigned int irda_1_mux[] = {
1799 PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
1800};
1801/* - KEYSC ------------------------------------------------------------------ */
1802static const unsigned int keysc_in5_pins[] = {
1803 /* KEYIN[0:4] */
1804 66, 67, 68, 69, 70,
1805};
1806static const unsigned int keysc_in5_mux[] = {
1807 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1808 KEYIN4_MARK,
1809};
1810static const unsigned int keysc_in6_pins[] = {
1811 /* KEYIN[0:5] */
1812 66, 67, 68, 69, 70, 71,
1813};
1814static const unsigned int keysc_in6_mux[] = {
1815 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1816 KEYIN4_MARK, KEYIN5_MARK,
1817};
1818static const unsigned int keysc_in7_pins[] = {
1819 /* KEYIN[0:6] */
1820 66, 67, 68, 69, 70, 71, 72,
1821};
1822static const unsigned int keysc_in7_mux[] = {
1823 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1824 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
1825};
1826static const unsigned int keysc_in8_pins[] = {
1827 /* KEYIN[0:7] */
1828 66, 67, 68, 69, 70, 71, 72, 73,
1829};
1830static const unsigned int keysc_in8_mux[] = {
1831 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1832 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
1833};
1834static const unsigned int keysc_out04_pins[] = {
1835 /* KEYOUT[0:4] */
1836 65, 64, 63, 62, 61,
1837};
1838static const unsigned int keysc_out04_mux[] = {
1839 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
1840};
1841static const unsigned int keysc_out5_pins[] = {
1842 /* KEYOUT5 */
1843 60,
1844};
1845static const unsigned int keysc_out5_mux[] = {
1846 KEYOUT5_MARK,
1847};
1848static const unsigned int keysc_out6_0_pins[] = {
1849 /* KEYOUT6 */
1850 59,
1851};
1852static const unsigned int keysc_out6_0_mux[] = {
1853 PORT59_KEYOUT6_MARK,
1854};
1855static const unsigned int keysc_out6_1_pins[] = {
1856 /* KEYOUT6 */
1857 131,
1858};
1859static const unsigned int keysc_out6_1_mux[] = {
1860 PORT131_KEYOUT6_MARK,
1861};
1862static const unsigned int keysc_out6_2_pins[] = {
1863 /* KEYOUT6 */
1864 143,
1865};
1866static const unsigned int keysc_out6_2_mux[] = {
1867 PORT143_KEYOUT6_MARK,
1868};
1869static const unsigned int keysc_out7_0_pins[] = {
1870 /* KEYOUT7 */
1871 58,
1872};
1873static const unsigned int keysc_out7_0_mux[] = {
1874 PORT58_KEYOUT7_MARK,
1875};
1876static const unsigned int keysc_out7_1_pins[] = {
1877 /* KEYOUT7 */
1878 132,
1879};
1880static const unsigned int keysc_out7_1_mux[] = {
1881 PORT132_KEYOUT7_MARK,
1882};
1883static const unsigned int keysc_out7_2_pins[] = {
1884 /* KEYOUT7 */
1885 144,
1886};
1887static const unsigned int keysc_out7_2_mux[] = {
1888 PORT144_KEYOUT7_MARK,
1889};
1890static const unsigned int keysc_out8_0_pins[] = {
1891 /* KEYOUT8 */
1892 PIN_NUMBER(6, 26),
1893};
1894static const unsigned int keysc_out8_0_mux[] = {
1895 KEYOUT8_MARK,
1896};
1897static const unsigned int keysc_out8_1_pins[] = {
1898 /* KEYOUT8 */
1899 136,
1900};
1901static const unsigned int keysc_out8_1_mux[] = {
1902 PORT136_KEYOUT8_MARK,
1903};
1904static const unsigned int keysc_out8_2_pins[] = {
1905 /* KEYOUT8 */
1906 138,
1907};
1908static const unsigned int keysc_out8_2_mux[] = {
1909 PORT138_KEYOUT8_MARK,
1910};
1911static const unsigned int keysc_out9_0_pins[] = {
1912 /* KEYOUT9 */
1913 137,
1914};
1915static const unsigned int keysc_out9_0_mux[] = {
1916 PORT137_KEYOUT9_MARK,
1917};
1918static const unsigned int keysc_out9_1_pins[] = {
1919 /* KEYOUT9 */
1920 139,
1921};
1922static const unsigned int keysc_out9_1_mux[] = {
1923 PORT139_KEYOUT9_MARK,
1924};
1925static const unsigned int keysc_out9_2_pins[] = {
1926 /* KEYOUT9 */
1927 149,
1928};
1929static const unsigned int keysc_out9_2_mux[] = {
1930 PORT149_KEYOUT9_MARK,
1931};
1932static const unsigned int keysc_out10_0_pins[] = {
1933 /* KEYOUT10 */
1934 132,
1935};
1936static const unsigned int keysc_out10_0_mux[] = {
1937 PORT132_KEYOUT10_MARK,
1938};
1939static const unsigned int keysc_out10_1_pins[] = {
1940 /* KEYOUT10 */
1941 142,
1942};
1943static const unsigned int keysc_out10_1_mux[] = {
1944 PORT142_KEYOUT10_MARK,
1945};
1946static const unsigned int keysc_out11_0_pins[] = {
1947 /* KEYOUT11 */
1948 131,
1949};
1950static const unsigned int keysc_out11_0_mux[] = {
1951 PORT131_KEYOUT11_MARK,
1952};
1953static const unsigned int keysc_out11_1_pins[] = {
1954 /* KEYOUT11 */
1955 143,
1956};
1957static const unsigned int keysc_out11_1_mux[] = {
1958 PORT143_KEYOUT11_MARK,
1959};
1960/* - LCD -------------------------------------------------------------------- */
1961static const unsigned int lcd_data8_pins[] = {
1962 /* D[0:7] */
1963 192, 193, 194, 195, 196, 197, 198, 199,
1964};
1965static const unsigned int lcd_data8_mux[] = {
1966 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1967 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1968};
1969static const unsigned int lcd_data9_pins[] = {
1970 /* D[0:8] */
1971 192, 193, 194, 195, 196, 197, 198, 199,
1972 200,
1973};
1974static const unsigned int lcd_data9_mux[] = {
1975 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1976 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1977 LCDD8_MARK,
1978};
1979static const unsigned int lcd_data12_pins[] = {
1980 /* D[0:11] */
1981 192, 193, 194, 195, 196, 197, 198, 199,
1982 200, 201, 202, 203,
1983};
1984static const unsigned int lcd_data12_mux[] = {
1985 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1986 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1987 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1988};
1989static const unsigned int lcd_data16_pins[] = {
1990 /* D[0:15] */
1991 192, 193, 194, 195, 196, 197, 198, 199,
1992 200, 201, 202, 203, 204, 205, 206, 207,
1993};
1994static const unsigned int lcd_data16_mux[] = {
1995 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1996 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1997 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1998 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1999};
2000static const unsigned int lcd_data18_pins[] = {
2001 /* D[0:17] */
2002 192, 193, 194, 195, 196, 197, 198, 199,
2003 200, 201, 202, 203, 204, 205, 206, 207,
2004 208, 209,
2005};
2006static const unsigned int lcd_data18_mux[] = {
2007 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2008 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2009 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2010 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2011 LCDD16_MARK, LCDD17_MARK,
2012};
2013static const unsigned int lcd_data24_pins[] = {
2014 /* D[0:23] */
2015 192, 193, 194, 195, 196, 197, 198, 199,
2016 200, 201, 202, 203, 204, 205, 206, 207,
2017 208, 209, 210, 211, 212, 213, 214, 215
2018};
2019static const unsigned int lcd_data24_mux[] = {
2020 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2021 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2022 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2023 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2024 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
2025 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2026};
2027static const unsigned int lcd_display_pins[] = {
2028 /* DON */
2029 222,
2030};
2031static const unsigned int lcd_display_mux[] = {
2032 LCDDON_MARK,
2033};
2034static const unsigned int lcd_lclk_pins[] = {
2035 /* LCLK */
2036 221,
2037};
2038static const unsigned int lcd_lclk_mux[] = {
2039 LCDLCLK_MARK,
2040};
2041static const unsigned int lcd_sync_pins[] = {
2042 /* VSYN, HSYN, DCK, DISP */
2043 220, 218, 216, 219,
2044};
2045static const unsigned int lcd_sync_mux[] = {
2046 LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2047};
2048static const unsigned int lcd_sys_pins[] = {
2049 /* CS, WR, RD, RS */
2050 218, 216, 217, 219,
2051};
2052static const unsigned int lcd_sys_mux[] = {
2053 LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2054};
2055/* - LCD2 ------------------------------------------------------------------- */
2056static const unsigned int lcd2_data8_pins[] = {
2057 /* D[0:7] */
2058 128, 129, 142, 143, 144, 145, 138, 139,
2059};
2060static const unsigned int lcd2_data8_mux[] = {
2061 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2062 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2063};
2064static const unsigned int lcd2_data9_pins[] = {
2065 /* D[0:8] */
2066 128, 129, 142, 143, 144, 145, 138, 139,
2067 140,
2068};
2069static const unsigned int lcd2_data9_mux[] = {
2070 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2071 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2072 LCD2D8_MARK,
2073};
2074static const unsigned int lcd2_data12_pins[] = {
2075 /* D[0:12] */
2076 128, 129, 142, 143, 144, 145, 138, 139,
2077 140, 141, 130, 131,
2078};
2079static const unsigned int lcd2_data12_mux[] = {
2080 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2081 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2082 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2083};
2084static const unsigned int lcd2_data16_pins[] = {
2085 /* D[0:15] */
2086 128, 129, 142, 143, 144, 145, 138, 139,
2087 140, 141, 130, 131, 132, 133, 134, 135,
2088};
2089static const unsigned int lcd2_data16_mux[] = {
2090 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2091 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2092 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2093 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2094};
2095static const unsigned int lcd2_data18_pins[] = {
2096 /* D[0:17] */
2097 128, 129, 142, 143, 144, 145, 138, 139,
2098 140, 141, 130, 131, 132, 133, 134, 135,
2099 136, 137,
2100};
2101static const unsigned int lcd2_data18_mux[] = {
2102 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2103 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2104 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2105 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2106 LCD2D16_MARK, LCD2D17_MARK,
2107};
2108static const unsigned int lcd2_data24_pins[] = {
2109 /* D[0:23] */
2110 128, 129, 142, 143, 144, 145, 138, 139,
2111 140, 141, 130, 131, 132, 133, 134, 135,
2112 136, 137, 146, 147, 234, 235, 238, 239
2113};
2114static const unsigned int lcd2_data24_mux[] = {
2115 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2116 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2117 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2118 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2119 LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2120 LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2121};
2122static const unsigned int lcd2_sync_0_pins[] = {
2123 /* VSYN, HSYN, DCK, DISP */
2124 128, 129, 146, 145,
2125};
2126static const unsigned int lcd2_sync_0_mux[] = {
2127 PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2128 LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2129};
2130static const unsigned int lcd2_sync_1_pins[] = {
2131 /* VSYN, HSYN, DCK, DISP */
2132 222, 221, 219, 217,
2133};
2134static const unsigned int lcd2_sync_1_mux[] = {
2135 PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2136 LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2137};
2138static const unsigned int lcd2_sys_0_pins[] = {
2139 /* CS, WR, RD, RS */
2140 129, 146, 147, 145,
2141};
2142static const unsigned int lcd2_sys_0_mux[] = {
2143 PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2144 LCD2RD__MARK, PORT145_LCD2RS_MARK,
2145};
2146static const unsigned int lcd2_sys_1_pins[] = {
2147 /* CS, WR, RD, RS */
2148 221, 219, 147, 217,
2149};
2150static const unsigned int lcd2_sys_1_mux[] = {
2151 PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2152 LCD2RD__MARK, PORT217_LCD2RS_MARK,
2153};
2154/* - MMCIF ------------------------------------------------------------------ */
2155static const unsigned int mmc0_data1_0_pins[] = {
2156 /* D[0] */
2157 271,
2158};
2159static const unsigned int mmc0_data1_0_mux[] = {
2160 MMCD0_0_MARK,
2161};
2162static const unsigned int mmc0_data4_0_pins[] = {
2163 /* D[0:3] */
2164 271, 272, 273, 274,
2165};
2166static const unsigned int mmc0_data4_0_mux[] = {
2167 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2168};
2169static const unsigned int mmc0_data8_0_pins[] = {
2170 /* D[0:7] */
2171 271, 272, 273, 274, 275, 276, 277, 278,
2172};
2173static const unsigned int mmc0_data8_0_mux[] = {
2174 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2175 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2176};
2177static const unsigned int mmc0_ctrl_0_pins[] = {
2178 /* CMD, CLK */
2179 279, 270,
2180};
2181static const unsigned int mmc0_ctrl_0_mux[] = {
2182 MMCCMD0_MARK, MMCCLK0_MARK,
2183};
1488 2184
1489 /* Functions with pull-ups */ 2185static const unsigned int mmc0_data1_1_pins[] = {
1490 PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU), 2186 /* D[0] */
1491 PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU), 2187 305,
1492 PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU), 2188};
1493 PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU), 2189static const unsigned int mmc0_data1_1_mux[] = {
1494 PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU), 2190 MMCD1_0_MARK,
1495 PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU), 2191};
1496 PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), 2192static const unsigned int mmc0_data4_1_pins[] = {
1497 PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), 2193 /* D[0:3] */
1498 2194 305, 304, 303, 302,
1499 PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU), 2195};
1500 PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU), 2196static const unsigned int mmc0_data4_1_mux[] = {
1501 PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU), 2197 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1502 PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU), 2198};
1503 PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU), 2199static const unsigned int mmc0_data8_1_pins[] = {
1504 PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU), 2200 /* D[0:7] */
1505 PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU), 2201 305, 304, 303, 302, 301, 300, 299, 298,
1506 PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU), 2202};
1507 PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU), 2203static const unsigned int mmc0_data8_1_mux[] = {
1508 PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU), 2204 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1509 PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU), 2205 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1510 PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU), 2206};
1511 PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU), 2207static const unsigned int mmc0_ctrl_1_pins[] = {
1512 PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU), 2208 /* CMD, CLK */
1513 PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU), 2209 297, 289,
1514 PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU), 2210};
1515 PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU), 2211static const unsigned int mmc0_ctrl_1_mux[] = {
1516 2212 MMCCMD1_MARK, MMCCLK1_MARK,
1517 PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, 2213};
1518 MSEL4CR_MSEL15_0), 2214/* - SCIFA0 ----------------------------------------------------------------- */
1519 PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, 2215static const unsigned int scifa0_data_pins[] = {
1520 MSEL4CR_MSEL15_1), 2216 /* RXD, TXD */
1521 2217 43, 17,
1522 PINMUX_DATA(MMCD0_0_PU_MARK, 2218};
1523 PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0), 2219static const unsigned int scifa0_data_mux[] = {
1524 PINMUX_DATA(MMCD0_1_PU_MARK, 2220 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1525 PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0), 2221};
1526 PINMUX_DATA(MMCD0_2_PU_MARK, 2222static const unsigned int scifa0_clk_pins[] = {
1527 PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0), 2223 /* SCK */
1528 PINMUX_DATA(MMCD0_3_PU_MARK, 2224 16,
1529 PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0), 2225};
1530 PINMUX_DATA(MMCD0_4_PU_MARK, 2226static const unsigned int scifa0_clk_mux[] = {
1531 PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0), 2227 SCIFA0_SCK_MARK,
1532 PINMUX_DATA(MMCD0_5_PU_MARK, 2228};
1533 PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0), 2229static const unsigned int scifa0_ctrl_pins[] = {
1534 PINMUX_DATA(MMCD0_6_PU_MARK, 2230 /* RTS, CTS */
1535 PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0), 2231 42, 44,
1536 PINMUX_DATA(MMCD0_7_PU_MARK, 2232};
1537 PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0), 2233static const unsigned int scifa0_ctrl_mux[] = {
1538 2234 SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
1539 PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), 2235};
1540 PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), 2236/* - SCIFA1 ----------------------------------------------------------------- */
1541 PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), 2237static const unsigned int scifa1_data_pins[] = {
1542 PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), 2238 /* RXD, TXD */
1543 PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), 2239 228, 225,
1544}; 2240};
1545 2241static const unsigned int scifa1_data_mux[] = {
1546static struct pinmux_gpio pinmux_gpios[] = { 2242 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1547 GPIO_PORT_ALL(), 2243};
2244static const unsigned int scifa1_clk_pins[] = {
2245 /* SCK */
2246 226,
2247};
2248static const unsigned int scifa1_clk_mux[] = {
2249 SCIFA1_SCK_MARK,
2250};
2251static const unsigned int scifa1_ctrl_pins[] = {
2252 /* RTS, CTS */
2253 227, 229,
2254};
2255static const unsigned int scifa1_ctrl_mux[] = {
2256 SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2257};
2258/* - SCIFA2 ----------------------------------------------------------------- */
2259static const unsigned int scifa2_data_0_pins[] = {
2260 /* RXD, TXD */
2261 155, 154,
2262};
2263static const unsigned int scifa2_data_0_mux[] = {
2264 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2265};
2266static const unsigned int scifa2_clk_0_pins[] = {
2267 /* SCK */
2268 158,
2269};
2270static const unsigned int scifa2_clk_0_mux[] = {
2271 SCIFA2_SCK1_MARK,
2272};
2273static const unsigned int scifa2_ctrl_0_pins[] = {
2274 /* RTS, CTS */
2275 156, 157,
2276};
2277static const unsigned int scifa2_ctrl_0_mux[] = {
2278 SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2279};
2280static const unsigned int scifa2_data_1_pins[] = {
2281 /* RXD, TXD */
2282 233, 230,
2283};
2284static const unsigned int scifa2_data_1_mux[] = {
2285 SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2286};
2287static const unsigned int scifa2_clk_1_pins[] = {
2288 /* SCK */
2289 232,
2290};
2291static const unsigned int scifa2_clk_1_mux[] = {
2292 SCIFA2_SCK2_MARK,
2293};
2294static const unsigned int scifa2_ctrl_1_pins[] = {
2295 /* RTS, CTS */
2296 234, 231,
2297};
2298static const unsigned int scifa2_ctrl_1_mux[] = {
2299 SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2300};
2301/* - SCIFA3 ----------------------------------------------------------------- */
2302static const unsigned int scifa3_data_pins[] = {
2303 /* RXD, TXD */
2304 108, 110,
2305};
2306static const unsigned int scifa3_data_mux[] = {
2307 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2308};
2309static const unsigned int scifa3_ctrl_pins[] = {
2310 /* RTS, CTS */
2311 109, 107,
2312};
2313static const unsigned int scifa3_ctrl_mux[] = {
2314 SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2315};
2316/* - SCIFA4 ----------------------------------------------------------------- */
2317static const unsigned int scifa4_data_pins[] = {
2318 /* RXD, TXD */
2319 33, 32,
2320};
2321static const unsigned int scifa4_data_mux[] = {
2322 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2323};
2324static const unsigned int scifa4_ctrl_pins[] = {
2325 /* RTS, CTS */
2326 34, 35,
2327};
2328static const unsigned int scifa4_ctrl_mux[] = {
2329 SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2330};
2331/* - SCIFA5 ----------------------------------------------------------------- */
2332static const unsigned int scifa5_data_0_pins[] = {
2333 /* RXD, TXD */
2334 246, 247,
2335};
2336static const unsigned int scifa5_data_0_mux[] = {
2337 PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2338};
2339static const unsigned int scifa5_clk_0_pins[] = {
2340 /* SCK */
2341 248,
2342};
2343static const unsigned int scifa5_clk_0_mux[] = {
2344 PORT248_SCIFA5_SCK_MARK,
2345};
2346static const unsigned int scifa5_ctrl_0_pins[] = {
2347 /* RTS, CTS */
2348 245, 244,
2349};
2350static const unsigned int scifa5_ctrl_0_mux[] = {
2351 PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2352};
2353static const unsigned int scifa5_data_1_pins[] = {
2354 /* RXD, TXD */
2355 195, 196,
2356};
2357static const unsigned int scifa5_data_1_mux[] = {
2358 PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2359};
2360static const unsigned int scifa5_clk_1_pins[] = {
2361 /* SCK */
2362 197,
2363};
2364static const unsigned int scifa5_clk_1_mux[] = {
2365 PORT197_SCIFA5_SCK_MARK,
2366};
2367static const unsigned int scifa5_ctrl_1_pins[] = {
2368 /* RTS, CTS */
2369 194, 193,
2370};
2371static const unsigned int scifa5_ctrl_1_mux[] = {
2372 PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2373};
2374static const unsigned int scifa5_data_2_pins[] = {
2375 /* RXD, TXD */
2376 162, 160,
2377};
2378static const unsigned int scifa5_data_2_mux[] = {
2379 PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2380};
2381static const unsigned int scifa5_clk_2_pins[] = {
2382 /* SCK */
2383 159,
2384};
2385static const unsigned int scifa5_clk_2_mux[] = {
2386 PORT159_SCIFA5_SCK_MARK,
2387};
2388static const unsigned int scifa5_ctrl_2_pins[] = {
2389 /* RTS, CTS */
2390 163, 161,
2391};
2392static const unsigned int scifa5_ctrl_2_mux[] = {
2393 PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2394};
2395/* - SCIFA6 ----------------------------------------------------------------- */
2396static const unsigned int scifa6_pins[] = {
2397 /* TXD */
2398 240,
2399};
2400static const unsigned int scifa6_mux[] = {
2401 SCIFA6_TXD_MARK,
2402};
2403/* - SCIFA7 ----------------------------------------------------------------- */
2404static const unsigned int scifa7_data_pins[] = {
2405 /* RXD, TXD */
2406 12, 18,
2407};
2408static const unsigned int scifa7_data_mux[] = {
2409 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2410};
2411static const unsigned int scifa7_ctrl_pins[] = {
2412 /* RTS, CTS */
2413 19, 13,
2414};
2415static const unsigned int scifa7_ctrl_mux[] = {
2416 SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2417};
2418/* - SCIFB ------------------------------------------------------------------ */
2419static const unsigned int scifb_data_0_pins[] = {
2420 /* RXD, TXD */
2421 162, 160,
2422};
2423static const unsigned int scifb_data_0_mux[] = {
2424 PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2425};
2426static const unsigned int scifb_clk_0_pins[] = {
2427 /* SCK */
2428 159,
2429};
2430static const unsigned int scifb_clk_0_mux[] = {
2431 PORT159_SCIFB_SCK_MARK,
2432};
2433static const unsigned int scifb_ctrl_0_pins[] = {
2434 /* RTS, CTS */
2435 163, 161,
2436};
2437static const unsigned int scifb_ctrl_0_mux[] = {
2438 PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2439};
2440static const unsigned int scifb_data_1_pins[] = {
2441 /* RXD, TXD */
2442 246, 247,
2443};
2444static const unsigned int scifb_data_1_mux[] = {
2445 PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2446};
2447static const unsigned int scifb_clk_1_pins[] = {
2448 /* SCK */
2449 248,
2450};
2451static const unsigned int scifb_clk_1_mux[] = {
2452 PORT248_SCIFB_SCK_MARK,
2453};
2454static const unsigned int scifb_ctrl_1_pins[] = {
2455 /* RTS, CTS */
2456 245, 244,
2457};
2458static const unsigned int scifb_ctrl_1_mux[] = {
2459 PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2460};
2461/* - SDHI0 ------------------------------------------------------------------ */
2462static const unsigned int sdhi0_data1_pins[] = {
2463 /* D0 */
2464 252,
2465};
2466static const unsigned int sdhi0_data1_mux[] = {
2467 SDHID0_0_MARK,
2468};
2469static const unsigned int sdhi0_data4_pins[] = {
2470 /* D[0:3] */
2471 252, 253, 254, 255,
2472};
2473static const unsigned int sdhi0_data4_mux[] = {
2474 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2475};
2476static const unsigned int sdhi0_ctrl_pins[] = {
2477 /* CMD, CLK */
2478 256, 250,
2479};
2480static const unsigned int sdhi0_ctrl_mux[] = {
2481 SDHICMD0_MARK, SDHICLK0_MARK,
2482};
2483static const unsigned int sdhi0_cd_pins[] = {
2484 /* CD */
2485 251,
2486};
2487static const unsigned int sdhi0_cd_mux[] = {
2488 SDHICD0_MARK,
2489};
2490static const unsigned int sdhi0_wp_pins[] = {
2491 /* WP */
2492 257,
2493};
2494static const unsigned int sdhi0_wp_mux[] = {
2495 SDHIWP0_MARK,
2496};
2497/* - SDHI1 ------------------------------------------------------------------ */
2498static const unsigned int sdhi1_data1_pins[] = {
2499 /* D0 */
2500 259,
2501};
2502static const unsigned int sdhi1_data1_mux[] = {
2503 SDHID1_0_MARK,
2504};
2505static const unsigned int sdhi1_data4_pins[] = {
2506 /* D[0:3] */
2507 259, 260, 261, 262,
2508};
2509static const unsigned int sdhi1_data4_mux[] = {
2510 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2511};
2512static const unsigned int sdhi1_ctrl_pins[] = {
2513 /* CMD, CLK */
2514 263, 258,
2515};
2516static const unsigned int sdhi1_ctrl_mux[] = {
2517 SDHICMD1_MARK, SDHICLK1_MARK,
2518};
2519/* - SDHI2 ------------------------------------------------------------------ */
2520static const unsigned int sdhi2_data1_pins[] = {
2521 /* D0 */
2522 265,
2523};
2524static const unsigned int sdhi2_data1_mux[] = {
2525 SDHID2_0_MARK,
2526};
2527static const unsigned int sdhi2_data4_pins[] = {
2528 /* D[0:3] */
2529 265, 266, 267, 268,
2530};
2531static const unsigned int sdhi2_data4_mux[] = {
2532 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2533};
2534static const unsigned int sdhi2_ctrl_pins[] = {
2535 /* CMD, CLK */
2536 269, 264,
2537};
2538static const unsigned int sdhi2_ctrl_mux[] = {
2539 SDHICMD2_MARK, SDHICLK2_MARK,
2540};
2541/* - USB -------------------------------------------------------------------- */
2542static const unsigned int usb_vbus_pins[] = {
2543 /* VBUS */
2544 0,
2545};
2546static const unsigned int usb_vbus_mux[] = {
2547 VBUS_0_MARK,
2548};
2549
2550static const struct sh_pfc_pin_group pinmux_groups[] = {
2551 SH_PFC_PIN_GROUP(bsc_data_0_7),
2552 SH_PFC_PIN_GROUP(bsc_data_8_15),
2553 SH_PFC_PIN_GROUP(bsc_cs4),
2554 SH_PFC_PIN_GROUP(bsc_cs5_a),
2555 SH_PFC_PIN_GROUP(bsc_cs5_b),
2556 SH_PFC_PIN_GROUP(bsc_cs6_a),
2557 SH_PFC_PIN_GROUP(bsc_cs6_b),
2558 SH_PFC_PIN_GROUP(bsc_rd),
2559 SH_PFC_PIN_GROUP(bsc_rdwr_0),
2560 SH_PFC_PIN_GROUP(bsc_rdwr_1),
2561 SH_PFC_PIN_GROUP(bsc_rdwr_2),
2562 SH_PFC_PIN_GROUP(bsc_we0),
2563 SH_PFC_PIN_GROUP(bsc_we1),
2564 SH_PFC_PIN_GROUP(fsia_mclk_in),
2565 SH_PFC_PIN_GROUP(fsia_mclk_out),
2566 SH_PFC_PIN_GROUP(fsia_sclk_in),
2567 SH_PFC_PIN_GROUP(fsia_sclk_out),
2568 SH_PFC_PIN_GROUP(fsia_data_in),
2569 SH_PFC_PIN_GROUP(fsia_data_out),
2570 SH_PFC_PIN_GROUP(fsia_spdif),
2571 SH_PFC_PIN_GROUP(fsib_mclk_in),
2572 SH_PFC_PIN_GROUP(fsib_mclk_out),
2573 SH_PFC_PIN_GROUP(fsib_sclk_in),
2574 SH_PFC_PIN_GROUP(fsib_sclk_out),
2575 SH_PFC_PIN_GROUP(fsib_data_in),
2576 SH_PFC_PIN_GROUP(fsib_data_out),
2577 SH_PFC_PIN_GROUP(fsib_spdif),
2578 SH_PFC_PIN_GROUP(fsic_mclk_in),
2579 SH_PFC_PIN_GROUP(fsic_mclk_out),
2580 SH_PFC_PIN_GROUP(fsic_sclk_in),
2581 SH_PFC_PIN_GROUP(fsic_sclk_out),
2582 SH_PFC_PIN_GROUP(fsic_data_in),
2583 SH_PFC_PIN_GROUP(fsic_data_out),
2584 SH_PFC_PIN_GROUP(fsic_spdif_0),
2585 SH_PFC_PIN_GROUP(fsic_spdif_1),
2586 SH_PFC_PIN_GROUP(fsid_sclk_in),
2587 SH_PFC_PIN_GROUP(fsid_sclk_out),
2588 SH_PFC_PIN_GROUP(fsid_data_in),
2589 SH_PFC_PIN_GROUP(i2c2_0),
2590 SH_PFC_PIN_GROUP(i2c2_1),
2591 SH_PFC_PIN_GROUP(i2c2_2),
2592 SH_PFC_PIN_GROUP(i2c3_0),
2593 SH_PFC_PIN_GROUP(i2c3_1),
2594 SH_PFC_PIN_GROUP(i2c3_2),
2595 SH_PFC_PIN_GROUP(irda_0),
2596 SH_PFC_PIN_GROUP(irda_1),
2597 SH_PFC_PIN_GROUP(keysc_in5),
2598 SH_PFC_PIN_GROUP(keysc_in6),
2599 SH_PFC_PIN_GROUP(keysc_in7),
2600 SH_PFC_PIN_GROUP(keysc_in8),
2601 SH_PFC_PIN_GROUP(keysc_out04),
2602 SH_PFC_PIN_GROUP(keysc_out5),
2603 SH_PFC_PIN_GROUP(keysc_out6_0),
2604 SH_PFC_PIN_GROUP(keysc_out6_1),
2605 SH_PFC_PIN_GROUP(keysc_out6_2),
2606 SH_PFC_PIN_GROUP(keysc_out7_0),
2607 SH_PFC_PIN_GROUP(keysc_out7_1),
2608 SH_PFC_PIN_GROUP(keysc_out7_2),
2609 SH_PFC_PIN_GROUP(keysc_out8_0),
2610 SH_PFC_PIN_GROUP(keysc_out8_1),
2611 SH_PFC_PIN_GROUP(keysc_out8_2),
2612 SH_PFC_PIN_GROUP(keysc_out9_0),
2613 SH_PFC_PIN_GROUP(keysc_out9_1),
2614 SH_PFC_PIN_GROUP(keysc_out9_2),
2615 SH_PFC_PIN_GROUP(keysc_out10_0),
2616 SH_PFC_PIN_GROUP(keysc_out10_1),
2617 SH_PFC_PIN_GROUP(keysc_out11_0),
2618 SH_PFC_PIN_GROUP(keysc_out11_1),
2619 SH_PFC_PIN_GROUP(lcd_data8),
2620 SH_PFC_PIN_GROUP(lcd_data9),
2621 SH_PFC_PIN_GROUP(lcd_data12),
2622 SH_PFC_PIN_GROUP(lcd_data16),
2623 SH_PFC_PIN_GROUP(lcd_data18),
2624 SH_PFC_PIN_GROUP(lcd_data24),
2625 SH_PFC_PIN_GROUP(lcd_display),
2626 SH_PFC_PIN_GROUP(lcd_lclk),
2627 SH_PFC_PIN_GROUP(lcd_sync),
2628 SH_PFC_PIN_GROUP(lcd_sys),
2629 SH_PFC_PIN_GROUP(lcd2_data8),
2630 SH_PFC_PIN_GROUP(lcd2_data9),
2631 SH_PFC_PIN_GROUP(lcd2_data12),
2632 SH_PFC_PIN_GROUP(lcd2_data16),
2633 SH_PFC_PIN_GROUP(lcd2_data18),
2634 SH_PFC_PIN_GROUP(lcd2_data24),
2635 SH_PFC_PIN_GROUP(lcd2_sync_0),
2636 SH_PFC_PIN_GROUP(lcd2_sync_1),
2637 SH_PFC_PIN_GROUP(lcd2_sys_0),
2638 SH_PFC_PIN_GROUP(lcd2_sys_1),
2639 SH_PFC_PIN_GROUP(mmc0_data1_0),
2640 SH_PFC_PIN_GROUP(mmc0_data4_0),
2641 SH_PFC_PIN_GROUP(mmc0_data8_0),
2642 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2643 SH_PFC_PIN_GROUP(mmc0_data1_1),
2644 SH_PFC_PIN_GROUP(mmc0_data4_1),
2645 SH_PFC_PIN_GROUP(mmc0_data8_1),
2646 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2647 SH_PFC_PIN_GROUP(scifa0_data),
2648 SH_PFC_PIN_GROUP(scifa0_clk),
2649 SH_PFC_PIN_GROUP(scifa0_ctrl),
2650 SH_PFC_PIN_GROUP(scifa1_data),
2651 SH_PFC_PIN_GROUP(scifa1_clk),
2652 SH_PFC_PIN_GROUP(scifa1_ctrl),
2653 SH_PFC_PIN_GROUP(scifa2_data_0),
2654 SH_PFC_PIN_GROUP(scifa2_clk_0),
2655 SH_PFC_PIN_GROUP(scifa2_ctrl_0),
2656 SH_PFC_PIN_GROUP(scifa2_data_1),
2657 SH_PFC_PIN_GROUP(scifa2_clk_1),
2658 SH_PFC_PIN_GROUP(scifa2_ctrl_1),
2659 SH_PFC_PIN_GROUP(scifa3_data),
2660 SH_PFC_PIN_GROUP(scifa3_ctrl),
2661 SH_PFC_PIN_GROUP(scifa4_data),
2662 SH_PFC_PIN_GROUP(scifa4_ctrl),
2663 SH_PFC_PIN_GROUP(scifa5_data_0),
2664 SH_PFC_PIN_GROUP(scifa5_clk_0),
2665 SH_PFC_PIN_GROUP(scifa5_ctrl_0),
2666 SH_PFC_PIN_GROUP(scifa5_data_1),
2667 SH_PFC_PIN_GROUP(scifa5_clk_1),
2668 SH_PFC_PIN_GROUP(scifa5_ctrl_1),
2669 SH_PFC_PIN_GROUP(scifa5_data_2),
2670 SH_PFC_PIN_GROUP(scifa5_clk_2),
2671 SH_PFC_PIN_GROUP(scifa5_ctrl_2),
2672 SH_PFC_PIN_GROUP(scifa6),
2673 SH_PFC_PIN_GROUP(scifa7_data),
2674 SH_PFC_PIN_GROUP(scifa7_ctrl),
2675 SH_PFC_PIN_GROUP(scifb_data_0),
2676 SH_PFC_PIN_GROUP(scifb_clk_0),
2677 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2678 SH_PFC_PIN_GROUP(scifb_data_1),
2679 SH_PFC_PIN_GROUP(scifb_clk_1),
2680 SH_PFC_PIN_GROUP(scifb_ctrl_1),
2681 SH_PFC_PIN_GROUP(sdhi0_data1),
2682 SH_PFC_PIN_GROUP(sdhi0_data4),
2683 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2684 SH_PFC_PIN_GROUP(sdhi0_cd),
2685 SH_PFC_PIN_GROUP(sdhi0_wp),
2686 SH_PFC_PIN_GROUP(sdhi1_data1),
2687 SH_PFC_PIN_GROUP(sdhi1_data4),
2688 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2689 SH_PFC_PIN_GROUP(sdhi2_data1),
2690 SH_PFC_PIN_GROUP(sdhi2_data4),
2691 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2692 SH_PFC_PIN_GROUP(usb_vbus),
2693};
2694
2695static const char * const bsc_groups[] = {
2696 "bsc_data_0_7",
2697 "bsc_data_8_15",
2698 "bsc_cs4",
2699 "bsc_cs5_a",
2700 "bsc_cs5_b",
2701 "bsc_cs6_a",
2702 "bsc_cs6_b",
2703 "bsc_rd",
2704 "bsc_rdwr_0",
2705 "bsc_rdwr_1",
2706 "bsc_rdwr_2",
2707 "bsc_we0",
2708 "bsc_we1",
2709};
2710
2711static const char * const fsia_groups[] = {
2712 "fsia_mclk_in",
2713 "fsia_mclk_out",
2714 "fsia_sclk_in",
2715 "fsia_sclk_out",
2716 "fsia_data_in",
2717 "fsia_data_out",
2718 "fsia_spdif",
2719};
2720
2721static const char * const fsib_groups[] = {
2722 "fsib_mclk_in",
2723 "fsib_mclk_out",
2724 "fsib_sclk_in",
2725 "fsib_sclk_out",
2726 "fsib_data_in",
2727 "fsib_data_out",
2728 "fsib_spdif",
2729};
2730
2731static const char * const fsic_groups[] = {
2732 "fsic_mclk_in",
2733 "fsic_mclk_out",
2734 "fsic_sclk_in",
2735 "fsic_sclk_out",
2736 "fsic_data_in",
2737 "fsic_data_out",
2738 "fsic_spdif",
2739};
2740
2741static const char * const fsid_groups[] = {
2742 "fsid_sclk_in",
2743 "fsid_sclk_out",
2744 "fsid_data_in",
2745};
2746
2747static const char * const i2c2_groups[] = {
2748 "i2c2_0",
2749 "i2c2_1",
2750 "i2c2_2",
2751};
2752
2753static const char * const i2c3_groups[] = {
2754 "i2c3_0",
2755 "i2c3_1",
2756 "i2c3_2",
2757};
2758
2759static const char * const irda_groups[] = {
2760 "irda_0",
2761 "irda_1",
2762};
1548 2763
2764static const char * const keysc_groups[] = {
2765 "keysc_in5",
2766 "keysc_in6",
2767 "keysc_in7",
2768 "keysc_in8",
2769 "keysc_out04",
2770 "keysc_out5",
2771 "keysc_out6_0",
2772 "keysc_out6_1",
2773 "keysc_out6_2",
2774 "keysc_out7_0",
2775 "keysc_out7_1",
2776 "keysc_out7_2",
2777 "keysc_out8_0",
2778 "keysc_out8_1",
2779 "keysc_out8_2",
2780 "keysc_out9_0",
2781 "keysc_out9_1",
2782 "keysc_out9_2",
2783 "keysc_out10_0",
2784 "keysc_out10_1",
2785 "keysc_out11_0",
2786 "keysc_out11_1",
2787};
2788
2789static const char * const lcd_groups[] = {
2790 "lcd_data8",
2791 "lcd_data9",
2792 "lcd_data12",
2793 "lcd_data16",
2794 "lcd_data18",
2795 "lcd_data24",
2796 "lcd_display",
2797 "lcd_lclk",
2798 "lcd_sync",
2799 "lcd_sys",
2800};
2801
2802static const char * const lcd2_groups[] = {
2803 "lcd2_data8",
2804 "lcd2_data9",
2805 "lcd2_data12",
2806 "lcd2_data16",
2807 "lcd2_data18",
2808 "lcd2_data24",
2809 "lcd2_sync_0",
2810 "lcd2_sync_1",
2811 "lcd2_sys_0",
2812 "lcd2_sys_1",
2813};
2814
2815static const char * const mmc0_groups[] = {
2816 "mmc0_data1_0",
2817 "mmc0_data4_0",
2818 "mmc0_data8_0",
2819 "mmc0_ctrl_0",
2820 "mmc0_data1_1",
2821 "mmc0_data4_1",
2822 "mmc0_data8_1",
2823 "mmc0_ctrl_1",
2824};
2825
2826static const char * const scifa0_groups[] = {
2827 "scifa0_data",
2828 "scifa0_clk",
2829 "scifa0_ctrl",
2830};
2831
2832static const char * const scifa1_groups[] = {
2833 "scifa1_data",
2834 "scifa1_clk",
2835 "scifa1_ctrl",
2836};
2837
2838static const char * const scifa2_groups[] = {
2839 "scifa2_data_0",
2840 "scifa2_clk_0",
2841 "scifa2_ctrl_0",
2842 "scifa2_data_1",
2843 "scifa2_clk_1",
2844 "scifa2_ctrl_1",
2845};
2846
2847static const char * const scifa3_groups[] = {
2848 "scifa3_data",
2849 "scifa3_ctrl",
2850};
2851
2852static const char * const scifa4_groups[] = {
2853 "scifa4_data",
2854 "scifa4_ctrl",
2855};
2856
2857static const char * const scifa5_groups[] = {
2858 "scifa5_data_0",
2859 "scifa5_clk_0",
2860 "scifa5_ctrl_0",
2861 "scifa5_data_1",
2862 "scifa5_clk_1",
2863 "scifa5_ctrl_1",
2864 "scifa5_data_2",
2865 "scifa5_clk_2",
2866 "scifa5_ctrl_2",
2867};
2868
2869static const char * const scifa6_groups[] = {
2870 "scifa6",
2871};
2872
2873static const char * const scifa7_groups[] = {
2874 "scifa7_data",
2875 "scifa7_ctrl",
2876};
2877
2878static const char * const scifb_groups[] = {
2879 "scifb_data_0",
2880 "scifb_clk_0",
2881 "scifb_ctrl_0",
2882 "scifb_data_1",
2883 "scifb_clk_1",
2884 "scifb_ctrl_1",
2885};
2886
2887static const char * const sdhi0_groups[] = {
2888 "sdhi0_data1",
2889 "sdhi0_data4",
2890 "sdhi0_ctrl",
2891 "sdhi0_cd",
2892 "sdhi0_wp",
2893};
2894
2895static const char * const sdhi1_groups[] = {
2896 "sdhi1_data1",
2897 "sdhi1_data4",
2898 "sdhi1_ctrl",
2899};
2900
2901static const char * const sdhi2_groups[] = {
2902 "sdhi2_data1",
2903 "sdhi2_data4",
2904 "sdhi2_ctrl",
2905};
2906
2907static const char * const usb_groups[] = {
2908 "usb_vbus",
2909};
2910
2911static const struct sh_pfc_function pinmux_functions[] = {
2912 SH_PFC_FUNCTION(bsc),
2913 SH_PFC_FUNCTION(fsia),
2914 SH_PFC_FUNCTION(fsib),
2915 SH_PFC_FUNCTION(fsic),
2916 SH_PFC_FUNCTION(fsid),
2917 SH_PFC_FUNCTION(i2c2),
2918 SH_PFC_FUNCTION(i2c3),
2919 SH_PFC_FUNCTION(irda),
2920 SH_PFC_FUNCTION(keysc),
2921 SH_PFC_FUNCTION(lcd),
2922 SH_PFC_FUNCTION(lcd2),
2923 SH_PFC_FUNCTION(mmc0),
2924 SH_PFC_FUNCTION(scifa0),
2925 SH_PFC_FUNCTION(scifa1),
2926 SH_PFC_FUNCTION(scifa2),
2927 SH_PFC_FUNCTION(scifa3),
2928 SH_PFC_FUNCTION(scifa4),
2929 SH_PFC_FUNCTION(scifa5),
2930 SH_PFC_FUNCTION(scifa6),
2931 SH_PFC_FUNCTION(scifa7),
2932 SH_PFC_FUNCTION(scifb),
2933 SH_PFC_FUNCTION(sdhi0),
2934 SH_PFC_FUNCTION(sdhi1),
2935 SH_PFC_FUNCTION(sdhi2),
2936 SH_PFC_FUNCTION(usb),
2937};
2938
2939#define PINMUX_FN_BASE GPIO_FN_GPI0
2940
2941static const struct pinmux_func pinmux_func_gpios[] = {
1549 /* Table 25-1 (Functions 0-7) */ 2942 /* Table 25-1 (Functions 0-7) */
1550 GPIO_FN(VBUS_0),
1551 GPIO_FN(GPI0), 2943 GPIO_FN(GPI0),
1552 GPIO_FN(GPI1), 2944 GPIO_FN(GPI1),
1553 GPIO_FN(GPI2), 2945 GPIO_FN(GPI2),
@@ -1556,19 +2948,12 @@ static struct pinmux_gpio pinmux_gpios[] = {
1556 GPIO_FN(GPI5), 2948 GPIO_FN(GPI5),
1557 GPIO_FN(GPI6), 2949 GPIO_FN(GPI6),
1558 GPIO_FN(GPI7), 2950 GPIO_FN(GPI7),
1559 GPIO_FN(SCIFA7_RXD),
1560 GPIO_FN(SCIFA7_CTS_),
1561 GPIO_FN(GPO7), \ 2951 GPIO_FN(GPO7), \
1562 GPIO_FN(MFG0_OUT2), 2952 GPIO_FN(MFG0_OUT2),
1563 GPIO_FN(GPO6), \ 2953 GPIO_FN(GPO6), \
1564 GPIO_FN(MFG1_OUT2), 2954 GPIO_FN(MFG1_OUT2),
1565 GPIO_FN(GPO5), \ 2955 GPIO_FN(GPO5), \
1566 GPIO_FN(SCIFA0_SCK), \
1567 GPIO_FN(FSICOSLDT3), \
1568 GPIO_FN(PORT16_VIO_CKOR), 2956 GPIO_FN(PORT16_VIO_CKOR),
1569 GPIO_FN(SCIFA0_TXD),
1570 GPIO_FN(SCIFA7_TXD),
1571 GPIO_FN(SCIFA7_RTS_), \
1572 GPIO_FN(PORT19_VIO_CKO2), 2957 GPIO_FN(PORT19_VIO_CKO2),
1573 GPIO_FN(GPO0), 2958 GPIO_FN(GPO0),
1574 GPIO_FN(GPO1), 2959 GPIO_FN(GPO1),
@@ -1581,13 +2966,9 @@ static struct pinmux_gpio pinmux_gpios[] = {
1581 GPIO_FN(VINT), 2966 GPIO_FN(VINT),
1582 GPIO_FN(TCKON), 2967 GPIO_FN(TCKON),
1583 GPIO_FN(XDVFS1), \ 2968 GPIO_FN(XDVFS1), \
1584 GPIO_FN(PORT27_I2C_SCL2), \
1585 GPIO_FN(PORT27_I2C_SCL3), \
1586 GPIO_FN(MFG0_OUT1), \ 2969 GPIO_FN(MFG0_OUT1), \
1587 GPIO_FN(PORT27_IROUT), 2970 GPIO_FN(PORT27_IROUT),
1588 GPIO_FN(XDVFS2), \ 2971 GPIO_FN(XDVFS2), \
1589 GPIO_FN(PORT28_I2C_SDA2), \
1590 GPIO_FN(PORT28_I2C_SDA3), \
1591 GPIO_FN(PORT28_TPU1TO1), 2972 GPIO_FN(PORT28_TPU1TO1),
1592 GPIO_FN(SIM_RST), \ 2973 GPIO_FN(SIM_RST), \
1593 GPIO_FN(PORT29_TPU1TO1), 2974 GPIO_FN(PORT29_TPU1TO1),
@@ -1595,140 +2976,53 @@ static struct pinmux_gpio pinmux_gpios[] = {
1595 GPIO_FN(PORT30_VIO_CKOR), 2976 GPIO_FN(PORT30_VIO_CKOR),
1596 GPIO_FN(SIM_D), \ 2977 GPIO_FN(SIM_D), \
1597 GPIO_FN(PORT31_IROUT), 2978 GPIO_FN(PORT31_IROUT),
1598 GPIO_FN(SCIFA4_TXD),
1599 GPIO_FN(SCIFA4_RXD), \
1600 GPIO_FN(XWUP), 2979 GPIO_FN(XWUP),
1601 GPIO_FN(SCIFA4_RTS_),
1602 GPIO_FN(SCIFA4_CTS_),
1603 GPIO_FN(FSIBOBT), \
1604 GPIO_FN(FSIBIBT),
1605 GPIO_FN(FSIBOLR), \
1606 GPIO_FN(FSIBILR),
1607 GPIO_FN(FSIBOSLD),
1608 GPIO_FN(FSIBISLD),
1609 GPIO_FN(VACK), 2980 GPIO_FN(VACK),
1610 GPIO_FN(XTAL1L), 2981 GPIO_FN(XTAL1L),
1611 GPIO_FN(SCIFA0_RTS_), \
1612 GPIO_FN(FSICOSLDT2),
1613 GPIO_FN(SCIFA0_RXD),
1614 GPIO_FN(SCIFA0_CTS_), \
1615 GPIO_FN(FSICOSLDT1),
1616 GPIO_FN(FSICOBT), \
1617 GPIO_FN(FSICIBT), \
1618 GPIO_FN(FSIDOBT), \
1619 GPIO_FN(FSIDIBT),
1620 GPIO_FN(FSICOLR), \
1621 GPIO_FN(FSICILR), \
1622 GPIO_FN(FSIDOLR), \
1623 GPIO_FN(FSIDILR),
1624 GPIO_FN(FSICOSLD), \
1625 GPIO_FN(PORT47_FSICSPDIF),
1626 GPIO_FN(FSICISLD), \
1627 GPIO_FN(FSIDISLD),
1628 GPIO_FN(FSIACK), \
1629 GPIO_FN(PORT49_IRDA_OUT), \
1630 GPIO_FN(PORT49_IROUT), \ 2982 GPIO_FN(PORT49_IROUT), \
1631 GPIO_FN(FSIAOMC),
1632 GPIO_FN(FSIAOLR), \
1633 GPIO_FN(BBIF2_TSYNC2), \ 2983 GPIO_FN(BBIF2_TSYNC2), \
1634 GPIO_FN(TPU2TO2), \ 2984 GPIO_FN(TPU2TO2), \
1635 GPIO_FN(FSIAILR),
1636 2985
1637 GPIO_FN(FSIAOBT), \
1638 GPIO_FN(BBIF2_TSCK2), \ 2986 GPIO_FN(BBIF2_TSCK2), \
1639 GPIO_FN(TPU2TO3), \ 2987 GPIO_FN(TPU2TO3), \
1640 GPIO_FN(FSIAIBT),
1641 GPIO_FN(FSIAOSLD), \
1642 GPIO_FN(BBIF2_TXD2), 2988 GPIO_FN(BBIF2_TXD2),
1643 GPIO_FN(FSIASPDIF), \
1644 GPIO_FN(PORT53_IRDA_IN), \
1645 GPIO_FN(TPU3TO3), \ 2989 GPIO_FN(TPU3TO3), \
1646 GPIO_FN(FSIBSPDIF), \
1647 GPIO_FN(PORT53_FSICSPDIF),
1648 GPIO_FN(FSIBCK), \
1649 GPIO_FN(PORT54_IRDA_FIRSEL), \
1650 GPIO_FN(TPU3TO2), \ 2990 GPIO_FN(TPU3TO2), \
1651 GPIO_FN(FSIBOMC), \
1652 GPIO_FN(FSICCK), \
1653 GPIO_FN(FSICOMC),
1654 GPIO_FN(FSIAISLD), \
1655 GPIO_FN(TPU0TO0), 2991 GPIO_FN(TPU0TO0),
1656 GPIO_FN(A0), \ 2992 GPIO_FN(A0), \
1657 GPIO_FN(BS_), 2993 GPIO_FN(BS_),
1658 GPIO_FN(A12), \ 2994 GPIO_FN(A12), \
1659 GPIO_FN(PORT58_KEYOUT7), \
1660 GPIO_FN(TPU4TO2), 2995 GPIO_FN(TPU4TO2),
1661 GPIO_FN(A13), \ 2996 GPIO_FN(A13), \
1662 GPIO_FN(PORT59_KEYOUT6), \
1663 GPIO_FN(TPU0TO1), 2997 GPIO_FN(TPU0TO1),
1664 GPIO_FN(A14), \ 2998 GPIO_FN(A14), \
1665 GPIO_FN(KEYOUT5),
1666 GPIO_FN(A15), \ 2999 GPIO_FN(A15), \
1667 GPIO_FN(KEYOUT4),
1668 GPIO_FN(A16), \ 3000 GPIO_FN(A16), \
1669 GPIO_FN(KEYOUT3), \
1670 GPIO_FN(MSIOF0_SS1), 3001 GPIO_FN(MSIOF0_SS1),
1671 GPIO_FN(A17), \ 3002 GPIO_FN(A17), \
1672 GPIO_FN(KEYOUT2), \
1673 GPIO_FN(MSIOF0_TSYNC), 3003 GPIO_FN(MSIOF0_TSYNC),
1674 GPIO_FN(A18), \ 3004 GPIO_FN(A18), \
1675 GPIO_FN(KEYOUT1), \
1676 GPIO_FN(MSIOF0_TSCK), 3005 GPIO_FN(MSIOF0_TSCK),
1677 GPIO_FN(A19), \ 3006 GPIO_FN(A19), \
1678 GPIO_FN(KEYOUT0), \
1679 GPIO_FN(MSIOF0_TXD), 3007 GPIO_FN(MSIOF0_TXD),
1680 GPIO_FN(A20), \ 3008 GPIO_FN(A20), \
1681 GPIO_FN(KEYIN0), \
1682 GPIO_FN(MSIOF0_RSCK), 3009 GPIO_FN(MSIOF0_RSCK),
1683 GPIO_FN(A21), \ 3010 GPIO_FN(A21), \
1684 GPIO_FN(KEYIN1), \
1685 GPIO_FN(MSIOF0_RSYNC), 3011 GPIO_FN(MSIOF0_RSYNC),
1686 GPIO_FN(A22), \ 3012 GPIO_FN(A22), \
1687 GPIO_FN(KEYIN2), \
1688 GPIO_FN(MSIOF0_MCK0), 3013 GPIO_FN(MSIOF0_MCK0),
1689 GPIO_FN(A23), \ 3014 GPIO_FN(A23), \
1690 GPIO_FN(KEYIN3), \
1691 GPIO_FN(MSIOF0_MCK1), 3015 GPIO_FN(MSIOF0_MCK1),
1692 GPIO_FN(A24), \ 3016 GPIO_FN(A24), \
1693 GPIO_FN(KEYIN4), \
1694 GPIO_FN(MSIOF0_RXD), 3017 GPIO_FN(MSIOF0_RXD),
1695 GPIO_FN(A25), \ 3018 GPIO_FN(A25), \
1696 GPIO_FN(KEYIN5), \
1697 GPIO_FN(MSIOF0_SS2), 3019 GPIO_FN(MSIOF0_SS2),
1698 GPIO_FN(A26), \ 3020 GPIO_FN(A26), \
1699 GPIO_FN(KEYIN6),
1700 GPIO_FN(KEYIN7),
1701 GPIO_FN(D0_NAF0),
1702 GPIO_FN(D1_NAF1),
1703 GPIO_FN(D2_NAF2),
1704 GPIO_FN(D3_NAF3),
1705 GPIO_FN(D4_NAF4),
1706 GPIO_FN(D5_NAF5),
1707 GPIO_FN(D6_NAF6),
1708 GPIO_FN(D7_NAF7),
1709 GPIO_FN(D8_NAF8),
1710 GPIO_FN(D9_NAF9),
1711 GPIO_FN(D10_NAF10),
1712 GPIO_FN(D11_NAF11),
1713 GPIO_FN(D12_NAF12),
1714 GPIO_FN(D13_NAF13),
1715 GPIO_FN(D14_NAF14),
1716 GPIO_FN(D15_NAF15),
1717 GPIO_FN(CS4_),
1718 GPIO_FN(CS5A_), \
1719 GPIO_FN(PORT91_RDWR),
1720 GPIO_FN(CS5B_), \
1721 GPIO_FN(FCE1_), 3021 GPIO_FN(FCE1_),
1722 GPIO_FN(CS6B_), \
1723 GPIO_FN(DACK0), 3022 GPIO_FN(DACK0),
1724 GPIO_FN(FCE0_), \ 3023 GPIO_FN(FCE0_), \
1725 GPIO_FN(CS6A_),
1726 GPIO_FN(WAIT_), \ 3024 GPIO_FN(WAIT_), \
1727 GPIO_FN(DREQ0), 3025 GPIO_FN(DREQ0),
1728 GPIO_FN(RD__FSC),
1729 GPIO_FN(WE0__FWE), \
1730 GPIO_FN(RDWR_FWE),
1731 GPIO_FN(WE1_),
1732 GPIO_FN(FRB), 3026 GPIO_FN(FRB),
1733 GPIO_FN(CKO), 3027 GPIO_FN(CKO),
1734 GPIO_FN(NBRSTOUT_), 3028 GPIO_FN(NBRSTOUT_),
@@ -1737,14 +3031,10 @@ static struct pinmux_gpio pinmux_gpios[] = {
1737 GPIO_FN(BBIF2_RXD), 3031 GPIO_FN(BBIF2_RXD),
1738 GPIO_FN(BBIF2_SYNC), 3032 GPIO_FN(BBIF2_SYNC),
1739 GPIO_FN(BBIF2_SCK), 3033 GPIO_FN(BBIF2_SCK),
1740 GPIO_FN(SCIFA3_CTS_), \
1741 GPIO_FN(MFG3_IN2), 3034 GPIO_FN(MFG3_IN2),
1742 GPIO_FN(SCIFA3_RXD), \
1743 GPIO_FN(MFG3_IN1), 3035 GPIO_FN(MFG3_IN1),
1744 GPIO_FN(BBIF1_SS2), \ 3036 GPIO_FN(BBIF1_SS2), \
1745 GPIO_FN(SCIFA3_RTS_), \
1746 GPIO_FN(MFG3_OUT1), 3037 GPIO_FN(MFG3_OUT1),
1747 GPIO_FN(SCIFA3_TXD),
1748 GPIO_FN(HSI_RX_DATA), \ 3038 GPIO_FN(HSI_RX_DATA), \
1749 GPIO_FN(BBIF1_RXD), 3039 GPIO_FN(BBIF1_RXD),
1750 GPIO_FN(HSI_TX_WAKE), \ 3040 GPIO_FN(HSI_TX_WAKE), \
@@ -1755,103 +3045,57 @@ static struct pinmux_gpio pinmux_gpios[] = {
1755 GPIO_FN(BBIF1_TXD), 3045 GPIO_FN(BBIF1_TXD),
1756 GPIO_FN(HSI_RX_READY), \ 3046 GPIO_FN(HSI_RX_READY), \
1757 GPIO_FN(BBIF1_RSCK), \ 3047 GPIO_FN(BBIF1_RSCK), \
1758 GPIO_FN(PORT115_I2C_SCL2), \
1759 GPIO_FN(PORT115_I2C_SCL3),
1760 GPIO_FN(HSI_RX_WAKE), \ 3048 GPIO_FN(HSI_RX_WAKE), \
1761 GPIO_FN(BBIF1_RSYNC), \ 3049 GPIO_FN(BBIF1_RSYNC), \
1762 GPIO_FN(PORT116_I2C_SDA2), \
1763 GPIO_FN(PORT116_I2C_SDA3),
1764 GPIO_FN(HSI_RX_FLAG), \ 3050 GPIO_FN(HSI_RX_FLAG), \
1765 GPIO_FN(BBIF1_SS1), \ 3051 GPIO_FN(BBIF1_SS1), \
1766 GPIO_FN(BBIF1_FLOW), 3052 GPIO_FN(BBIF1_FLOW),
1767 GPIO_FN(HSI_TX_FLAG), 3053 GPIO_FN(HSI_TX_FLAG),
1768 GPIO_FN(VIO_VD), \ 3054 GPIO_FN(VIO_VD), \
1769 GPIO_FN(PORT128_LCD2VSYN), \
1770 GPIO_FN(VIO2_VD), \ 3055 GPIO_FN(VIO2_VD), \
1771 GPIO_FN(LCD2D0),
1772 3056
1773 GPIO_FN(VIO_HD), \ 3057 GPIO_FN(VIO_HD), \
1774 GPIO_FN(PORT129_LCD2HSYN), \
1775 GPIO_FN(PORT129_LCD2CS_), \
1776 GPIO_FN(VIO2_HD), \ 3058 GPIO_FN(VIO2_HD), \
1777 GPIO_FN(LCD2D1),
1778 GPIO_FN(VIO_D0), \ 3059 GPIO_FN(VIO_D0), \
1779 GPIO_FN(PORT130_MSIOF2_RXD), \ 3060 GPIO_FN(PORT130_MSIOF2_RXD), \
1780 GPIO_FN(LCD2D10),
1781 GPIO_FN(VIO_D1), \ 3061 GPIO_FN(VIO_D1), \
1782 GPIO_FN(PORT131_KEYOUT6), \
1783 GPIO_FN(PORT131_MSIOF2_SS1), \ 3062 GPIO_FN(PORT131_MSIOF2_SS1), \
1784 GPIO_FN(PORT131_KEYOUT11), \
1785 GPIO_FN(LCD2D11),
1786 GPIO_FN(VIO_D2), \ 3063 GPIO_FN(VIO_D2), \
1787 GPIO_FN(PORT132_KEYOUT7), \
1788 GPIO_FN(PORT132_MSIOF2_SS2), \ 3064 GPIO_FN(PORT132_MSIOF2_SS2), \
1789 GPIO_FN(PORT132_KEYOUT10), \
1790 GPIO_FN(LCD2D12),
1791 GPIO_FN(VIO_D3), \ 3065 GPIO_FN(VIO_D3), \
1792 GPIO_FN(MSIOF2_TSYNC), \ 3066 GPIO_FN(MSIOF2_TSYNC), \
1793 GPIO_FN(LCD2D13),
1794 GPIO_FN(VIO_D4), \ 3067 GPIO_FN(VIO_D4), \
1795 GPIO_FN(MSIOF2_TXD), \ 3068 GPIO_FN(MSIOF2_TXD), \
1796 GPIO_FN(LCD2D14),
1797 GPIO_FN(VIO_D5), \ 3069 GPIO_FN(VIO_D5), \
1798 GPIO_FN(MSIOF2_TSCK), \ 3070 GPIO_FN(MSIOF2_TSCK), \
1799 GPIO_FN(LCD2D15),
1800 GPIO_FN(VIO_D6), \ 3071 GPIO_FN(VIO_D6), \
1801 GPIO_FN(PORT136_KEYOUT8), \
1802 GPIO_FN(LCD2D16),
1803 GPIO_FN(VIO_D7), \ 3072 GPIO_FN(VIO_D7), \
1804 GPIO_FN(PORT137_KEYOUT9), \
1805 GPIO_FN(LCD2D17),
1806 GPIO_FN(VIO_D8), \ 3073 GPIO_FN(VIO_D8), \
1807 GPIO_FN(PORT138_KEYOUT8), \
1808 GPIO_FN(VIO2_D0), \ 3074 GPIO_FN(VIO2_D0), \
1809 GPIO_FN(LCD2D6),
1810 GPIO_FN(VIO_D9), \ 3075 GPIO_FN(VIO_D9), \
1811 GPIO_FN(PORT139_KEYOUT9), \
1812 GPIO_FN(VIO2_D1), \ 3076 GPIO_FN(VIO2_D1), \
1813 GPIO_FN(LCD2D7),
1814 GPIO_FN(VIO_D10), \ 3077 GPIO_FN(VIO_D10), \
1815 GPIO_FN(TPU0TO2), \ 3078 GPIO_FN(TPU0TO2), \
1816 GPIO_FN(VIO2_D2), \ 3079 GPIO_FN(VIO2_D2), \
1817 GPIO_FN(LCD2D8),
1818 GPIO_FN(VIO_D11), \ 3080 GPIO_FN(VIO_D11), \
1819 GPIO_FN(TPU0TO3), \ 3081 GPIO_FN(TPU0TO3), \
1820 GPIO_FN(VIO2_D3), \ 3082 GPIO_FN(VIO2_D3), \
1821 GPIO_FN(LCD2D9),
1822 GPIO_FN(VIO_D12), \ 3083 GPIO_FN(VIO_D12), \
1823 GPIO_FN(PORT142_KEYOUT10), \
1824 GPIO_FN(VIO2_D4), \ 3084 GPIO_FN(VIO2_D4), \
1825 GPIO_FN(LCD2D2),
1826 GPIO_FN(VIO_D13), \ 3085 GPIO_FN(VIO_D13), \
1827 GPIO_FN(PORT143_KEYOUT11), \
1828 GPIO_FN(PORT143_KEYOUT6), \
1829 GPIO_FN(VIO2_D5), \ 3086 GPIO_FN(VIO2_D5), \
1830 GPIO_FN(LCD2D3),
1831 GPIO_FN(VIO_D14), \ 3087 GPIO_FN(VIO_D14), \
1832 GPIO_FN(PORT144_KEYOUT7), \
1833 GPIO_FN(VIO2_D6), \ 3088 GPIO_FN(VIO2_D6), \
1834 GPIO_FN(LCD2D4),
1835 GPIO_FN(VIO_D15), \ 3089 GPIO_FN(VIO_D15), \
1836 GPIO_FN(TPU1TO3), \ 3090 GPIO_FN(TPU1TO3), \
1837 GPIO_FN(PORT145_LCD2DISP), \
1838 GPIO_FN(PORT145_LCD2RS), \
1839 GPIO_FN(VIO2_D7), \ 3091 GPIO_FN(VIO2_D7), \
1840 GPIO_FN(LCD2D5),
1841 GPIO_FN(VIO_CLK), \ 3092 GPIO_FN(VIO_CLK), \
1842 GPIO_FN(LCD2DCK), \
1843 GPIO_FN(PORT146_LCD2WR_), \
1844 GPIO_FN(VIO2_CLK), \ 3093 GPIO_FN(VIO2_CLK), \
1845 GPIO_FN(LCD2D18),
1846 GPIO_FN(VIO_FIELD), \ 3094 GPIO_FN(VIO_FIELD), \
1847 GPIO_FN(LCD2RD_), \
1848 GPIO_FN(VIO2_FIELD), \ 3095 GPIO_FN(VIO2_FIELD), \
1849 GPIO_FN(LCD2D19),
1850 GPIO_FN(VIO_CKO), 3096 GPIO_FN(VIO_CKO),
1851 GPIO_FN(A27), \ 3097 GPIO_FN(A27), \
1852 GPIO_FN(PORT149_RDWR), \
1853 GPIO_FN(MFG0_IN1), \ 3098 GPIO_FN(MFG0_IN1), \
1854 GPIO_FN(PORT149_KEYOUT9),
1855 GPIO_FN(MFG0_IN2), 3099 GPIO_FN(MFG0_IN2),
1856 GPIO_FN(TS_SPSYNC3), \ 3100 GPIO_FN(TS_SPSYNC3), \
1857 GPIO_FN(MSIOF2_RSCK), 3101 GPIO_FN(MSIOF2_RSCK),
@@ -1860,201 +3104,105 @@ static struct pinmux_gpio pinmux_gpios[] = {
1860 GPIO_FN(TPU1TO2), \ 3104 GPIO_FN(TPU1TO2), \
1861 GPIO_FN(TS_SDEN3), \ 3105 GPIO_FN(TS_SDEN3), \
1862 GPIO_FN(PORT153_MSIOF2_SS1), 3106 GPIO_FN(PORT153_MSIOF2_SS1),
1863 GPIO_FN(SCIFA2_TXD1), \
1864 GPIO_FN(MSIOF2_MCK0), 3107 GPIO_FN(MSIOF2_MCK0),
1865 GPIO_FN(SCIFA2_RXD1), \
1866 GPIO_FN(MSIOF2_MCK1), 3108 GPIO_FN(MSIOF2_MCK1),
1867 GPIO_FN(SCIFA2_RTS1_), \
1868 GPIO_FN(PORT156_MSIOF2_SS2), 3109 GPIO_FN(PORT156_MSIOF2_SS2),
1869 GPIO_FN(SCIFA2_CTS1_), \
1870 GPIO_FN(PORT157_MSIOF2_RXD), 3110 GPIO_FN(PORT157_MSIOF2_RXD),
1871 GPIO_FN(DINT_), \ 3111 GPIO_FN(DINT_), \
1872 GPIO_FN(SCIFA2_SCK1), \
1873 GPIO_FN(TS_SCK3), 3112 GPIO_FN(TS_SCK3),
1874 GPIO_FN(PORT159_SCIFB_SCK), \
1875 GPIO_FN(PORT159_SCIFA5_SCK), \
1876 GPIO_FN(NMI), 3113 GPIO_FN(NMI),
1877 GPIO_FN(PORT160_SCIFB_TXD), \
1878 GPIO_FN(PORT160_SCIFA5_TXD),
1879 GPIO_FN(PORT161_SCIFB_CTS_), \
1880 GPIO_FN(PORT161_SCIFA5_CTS_),
1881 GPIO_FN(PORT162_SCIFB_RXD), \
1882 GPIO_FN(PORT162_SCIFA5_RXD),
1883 GPIO_FN(PORT163_SCIFB_RTS_), \
1884 GPIO_FN(PORT163_SCIFA5_RTS_), \
1885 GPIO_FN(TPU3TO0), 3114 GPIO_FN(TPU3TO0),
1886 GPIO_FN(LCDD0),
1887 GPIO_FN(LCDD1), \
1888 GPIO_FN(PORT193_SCIFA5_CTS_), \
1889 GPIO_FN(BBIF2_TSYNC1), 3115 GPIO_FN(BBIF2_TSYNC1),
1890 GPIO_FN(LCDD2), \
1891 GPIO_FN(PORT194_SCIFA5_RTS_), \
1892 GPIO_FN(BBIF2_TSCK1), 3116 GPIO_FN(BBIF2_TSCK1),
1893 GPIO_FN(LCDD3), \
1894 GPIO_FN(PORT195_SCIFA5_RXD), \
1895 GPIO_FN(BBIF2_TXD1), 3117 GPIO_FN(BBIF2_TXD1),
1896 GPIO_FN(LCDD4), \
1897 GPIO_FN(PORT196_SCIFA5_TXD),
1898 GPIO_FN(LCDD5), \
1899 GPIO_FN(PORT197_SCIFA5_SCK), \
1900 GPIO_FN(MFG2_OUT2), \ 3118 GPIO_FN(MFG2_OUT2), \
1901 GPIO_FN(TPU2TO1), 3119 GPIO_FN(TPU2TO1),
1902 GPIO_FN(LCDD6),
1903 GPIO_FN(LCDD7), \
1904 GPIO_FN(TPU4TO1), \ 3120 GPIO_FN(TPU4TO1), \
1905 GPIO_FN(MFG4_OUT2), 3121 GPIO_FN(MFG4_OUT2),
1906 GPIO_FN(LCDD8), \
1907 GPIO_FN(D16), 3122 GPIO_FN(D16),
1908 GPIO_FN(LCDD9), \
1909 GPIO_FN(D17), 3123 GPIO_FN(D17),
1910 GPIO_FN(LCDD10), \
1911 GPIO_FN(D18), 3124 GPIO_FN(D18),
1912 GPIO_FN(LCDD11), \
1913 GPIO_FN(D19), 3125 GPIO_FN(D19),
1914 GPIO_FN(LCDD12), \
1915 GPIO_FN(D20), 3126 GPIO_FN(D20),
1916 GPIO_FN(LCDD13), \
1917 GPIO_FN(D21), 3127 GPIO_FN(D21),
1918 GPIO_FN(LCDD14), \
1919 GPIO_FN(D22), 3128 GPIO_FN(D22),
1920 GPIO_FN(LCDD15), \
1921 GPIO_FN(PORT207_MSIOF0L_SS1), \ 3129 GPIO_FN(PORT207_MSIOF0L_SS1), \
1922 GPIO_FN(D23), 3130 GPIO_FN(D23),
1923 GPIO_FN(LCDD16), \
1924 GPIO_FN(PORT208_MSIOF0L_SS2), \ 3131 GPIO_FN(PORT208_MSIOF0L_SS2), \
1925 GPIO_FN(D24), 3132 GPIO_FN(D24),
1926 GPIO_FN(LCDD17), \
1927 GPIO_FN(D25), 3133 GPIO_FN(D25),
1928 GPIO_FN(LCDD18), \
1929 GPIO_FN(DREQ2), \ 3134 GPIO_FN(DREQ2), \
1930 GPIO_FN(PORT210_MSIOF0L_SS1), \ 3135 GPIO_FN(PORT210_MSIOF0L_SS1), \
1931 GPIO_FN(D26), 3136 GPIO_FN(D26),
1932 GPIO_FN(LCDD19), \
1933 GPIO_FN(PORT211_MSIOF0L_SS2), \ 3137 GPIO_FN(PORT211_MSIOF0L_SS2), \
1934 GPIO_FN(D27), 3138 GPIO_FN(D27),
1935 GPIO_FN(LCDD20), \
1936 GPIO_FN(TS_SPSYNC1), \ 3139 GPIO_FN(TS_SPSYNC1), \
1937 GPIO_FN(MSIOF0L_MCK0), \ 3140 GPIO_FN(MSIOF0L_MCK0), \
1938 GPIO_FN(D28), 3141 GPIO_FN(D28),
1939 GPIO_FN(LCDD21), \
1940 GPIO_FN(TS_SDAT1), \ 3142 GPIO_FN(TS_SDAT1), \
1941 GPIO_FN(MSIOF0L_MCK1), \ 3143 GPIO_FN(MSIOF0L_MCK1), \
1942 GPIO_FN(D29), 3144 GPIO_FN(D29),
1943 GPIO_FN(LCDD22), \
1944 GPIO_FN(TS_SDEN1), \ 3145 GPIO_FN(TS_SDEN1), \
1945 GPIO_FN(MSIOF0L_RSCK), \ 3146 GPIO_FN(MSIOF0L_RSCK), \
1946 GPIO_FN(D30), 3147 GPIO_FN(D30),
1947 GPIO_FN(LCDD23), \
1948 GPIO_FN(TS_SCK1), \ 3148 GPIO_FN(TS_SCK1), \
1949 GPIO_FN(MSIOF0L_RSYNC), \ 3149 GPIO_FN(MSIOF0L_RSYNC), \
1950 GPIO_FN(D31), 3150 GPIO_FN(D31),
1951 GPIO_FN(LCDDCK), \
1952 GPIO_FN(LCDWR_),
1953 GPIO_FN(LCDRD_), \
1954 GPIO_FN(DACK2), \ 3151 GPIO_FN(DACK2), \
1955 GPIO_FN(PORT217_LCD2RS), \
1956 GPIO_FN(MSIOF0L_TSYNC), \ 3152 GPIO_FN(MSIOF0L_TSYNC), \
1957 GPIO_FN(VIO2_FIELD3), \ 3153 GPIO_FN(VIO2_FIELD3), \
1958 GPIO_FN(PORT217_LCD2DISP),
1959 GPIO_FN(LCDHSYN), \
1960 GPIO_FN(LCDCS_), \
1961 GPIO_FN(LCDCS2_), \
1962 GPIO_FN(DACK3), \ 3154 GPIO_FN(DACK3), \
1963 GPIO_FN(PORT218_VIO_CKOR), 3155 GPIO_FN(PORT218_VIO_CKOR),
1964 GPIO_FN(LCDDISP), \
1965 GPIO_FN(LCDRS), \
1966 GPIO_FN(PORT219_LCD2WR_), \
1967 GPIO_FN(DREQ3), \ 3156 GPIO_FN(DREQ3), \
1968 GPIO_FN(MSIOF0L_TSCK), \ 3157 GPIO_FN(MSIOF0L_TSCK), \
1969 GPIO_FN(VIO2_CLK3), \ 3158 GPIO_FN(VIO2_CLK3), \
1970 GPIO_FN(LCD2DCK_2),
1971 GPIO_FN(LCDVSYN), \
1972 GPIO_FN(LCDVSYN2),
1973 GPIO_FN(LCDLCLK), \
1974 GPIO_FN(DREQ1), \ 3159 GPIO_FN(DREQ1), \
1975 GPIO_FN(PORT221_LCD2CS_), \
1976 GPIO_FN(PWEN), \ 3160 GPIO_FN(PWEN), \
1977 GPIO_FN(MSIOF0L_RXD), \ 3161 GPIO_FN(MSIOF0L_RXD), \
1978 GPIO_FN(VIO2_HD3), \ 3162 GPIO_FN(VIO2_HD3), \
1979 GPIO_FN(PORT221_LCD2HSYN),
1980 GPIO_FN(LCDDON), \
1981 GPIO_FN(LCDDON2), \
1982 GPIO_FN(DACK1), \ 3163 GPIO_FN(DACK1), \
1983 GPIO_FN(OVCN), \ 3164 GPIO_FN(OVCN), \
1984 GPIO_FN(MSIOF0L_TXD), \ 3165 GPIO_FN(MSIOF0L_TXD), \
1985 GPIO_FN(VIO2_VD3), \ 3166 GPIO_FN(VIO2_VD3), \
1986 GPIO_FN(PORT222_LCD2VSYN),
1987 3167
1988 GPIO_FN(SCIFA1_TXD), \
1989 GPIO_FN(OVCN2), 3168 GPIO_FN(OVCN2),
1990 GPIO_FN(EXTLP), \ 3169 GPIO_FN(EXTLP), \
1991 GPIO_FN(SCIFA1_SCK), \
1992 GPIO_FN(PORT226_VIO_CKO2), 3170 GPIO_FN(PORT226_VIO_CKO2),
1993 GPIO_FN(SCIFA1_RTS_), \
1994 GPIO_FN(IDIN), 3171 GPIO_FN(IDIN),
1995 GPIO_FN(SCIFA1_RXD),
1996 GPIO_FN(SCIFA1_CTS_), \
1997 GPIO_FN(MFG1_IN1), 3172 GPIO_FN(MFG1_IN1),
1998 GPIO_FN(MSIOF1_TXD), \ 3173 GPIO_FN(MSIOF1_TXD), \
1999 GPIO_FN(SCIFA2_TXD2),
2000 GPIO_FN(MSIOF1_TSYNC), \ 3174 GPIO_FN(MSIOF1_TSYNC), \
2001 GPIO_FN(SCIFA2_CTS2_),
2002 GPIO_FN(MSIOF1_TSCK), \ 3175 GPIO_FN(MSIOF1_TSCK), \
2003 GPIO_FN(SCIFA2_SCK2),
2004 GPIO_FN(MSIOF1_RXD), \ 3176 GPIO_FN(MSIOF1_RXD), \
2005 GPIO_FN(SCIFA2_RXD2),
2006 GPIO_FN(MSIOF1_RSCK), \ 3177 GPIO_FN(MSIOF1_RSCK), \
2007 GPIO_FN(SCIFA2_RTS2_), \
2008 GPIO_FN(VIO2_CLK2), \ 3178 GPIO_FN(VIO2_CLK2), \
2009 GPIO_FN(LCD2D20),
2010 GPIO_FN(MSIOF1_RSYNC), \ 3179 GPIO_FN(MSIOF1_RSYNC), \
2011 GPIO_FN(MFG1_IN2), \ 3180 GPIO_FN(MFG1_IN2), \
2012 GPIO_FN(VIO2_VD2), \ 3181 GPIO_FN(VIO2_VD2), \
2013 GPIO_FN(LCD2D21),
2014 GPIO_FN(MSIOF1_MCK0), \ 3182 GPIO_FN(MSIOF1_MCK0), \
2015 GPIO_FN(PORT236_I2C_SDA2),
2016 GPIO_FN(MSIOF1_MCK1), \ 3183 GPIO_FN(MSIOF1_MCK1), \
2017 GPIO_FN(PORT237_I2C_SCL2),
2018 GPIO_FN(MSIOF1_SS1), \ 3184 GPIO_FN(MSIOF1_SS1), \
2019 GPIO_FN(VIO2_FIELD2), \ 3185 GPIO_FN(VIO2_FIELD2), \
2020 GPIO_FN(LCD2D22),
2021 GPIO_FN(MSIOF1_SS2), \ 3186 GPIO_FN(MSIOF1_SS2), \
2022 GPIO_FN(VIO2_HD2), \ 3187 GPIO_FN(VIO2_HD2), \
2023 GPIO_FN(LCD2D23),
2024 GPIO_FN(SCIFA6_TXD),
2025 GPIO_FN(PORT241_IRDA_OUT), \
2026 GPIO_FN(PORT241_IROUT), \ 3188 GPIO_FN(PORT241_IROUT), \
2027 GPIO_FN(MFG4_OUT1), \ 3189 GPIO_FN(MFG4_OUT1), \
2028 GPIO_FN(TPU4TO0), 3190 GPIO_FN(TPU4TO0),
2029 GPIO_FN(PORT242_IRDA_IN), \
2030 GPIO_FN(MFG4_IN2), 3191 GPIO_FN(MFG4_IN2),
2031 GPIO_FN(PORT243_IRDA_FIRSEL), \
2032 GPIO_FN(PORT243_VIO_CKO2), 3192 GPIO_FN(PORT243_VIO_CKO2),
2033 GPIO_FN(PORT244_SCIFA5_CTS_), \
2034 GPIO_FN(MFG2_IN1), \ 3193 GPIO_FN(MFG2_IN1), \
2035 GPIO_FN(PORT244_SCIFB_CTS_), \
2036 GPIO_FN(MSIOF2R_RXD), 3194 GPIO_FN(MSIOF2R_RXD),
2037 GPIO_FN(PORT245_SCIFA5_RTS_), \
2038 GPIO_FN(MFG2_IN2), \ 3195 GPIO_FN(MFG2_IN2), \
2039 GPIO_FN(PORT245_SCIFB_RTS_), \
2040 GPIO_FN(MSIOF2R_TXD), 3196 GPIO_FN(MSIOF2R_TXD),
2041 GPIO_FN(PORT246_SCIFA5_RXD), \
2042 GPIO_FN(MFG1_OUT1), \ 3197 GPIO_FN(MFG1_OUT1), \
2043 GPIO_FN(PORT246_SCIFB_RXD), \
2044 GPIO_FN(TPU1TO0), 3198 GPIO_FN(TPU1TO0),
2045 GPIO_FN(PORT247_SCIFA5_TXD), \
2046 GPIO_FN(MFG3_OUT2), \ 3199 GPIO_FN(MFG3_OUT2), \
2047 GPIO_FN(PORT247_SCIFB_TXD), \
2048 GPIO_FN(TPU3TO1), 3200 GPIO_FN(TPU3TO1),
2049 GPIO_FN(PORT248_SCIFA5_SCK), \
2050 GPIO_FN(MFG2_OUT1), \ 3201 GPIO_FN(MFG2_OUT1), \
2051 GPIO_FN(PORT248_SCIFB_SCK), \
2052 GPIO_FN(TPU2TO0), \ 3202 GPIO_FN(TPU2TO0), \
2053 GPIO_FN(PORT248_I2C_SCL3), \
2054 GPIO_FN(MSIOF2R_TSCK), 3203 GPIO_FN(MSIOF2R_TSCK),
2055 GPIO_FN(PORT249_IROUT), \ 3204 GPIO_FN(PORT249_IROUT), \
2056 GPIO_FN(MFG4_IN1), \ 3205 GPIO_FN(MFG4_IN1), \
2057 GPIO_FN(PORT249_I2C_SDA3), \
2058 GPIO_FN(MSIOF2R_TSYNC), 3206 GPIO_FN(MSIOF2R_TSYNC),
2059 GPIO_FN(SDHICLK0), 3207 GPIO_FN(SDHICLK0),
2060 GPIO_FN(SDHICD0), 3208 GPIO_FN(SDHICD0),
@@ -2172,56 +3320,24 @@ static struct pinmux_gpio pinmux_gpios[] = {
2172 GPIO_FN(IRQ9_MEM_INT), 3320 GPIO_FN(IRQ9_MEM_INT),
2173 GPIO_FN(IRQ9_MCP_INT), 3321 GPIO_FN(IRQ9_MCP_INT),
2174 GPIO_FN(A11), 3322 GPIO_FN(A11),
2175 GPIO_FN(KEYOUT8),
2176 GPIO_FN(TPU4TO3), 3323 GPIO_FN(TPU4TO3),
2177 GPIO_FN(RESETA_N_PU_ON), 3324 GPIO_FN(RESETA_N_PU_ON),
2178 GPIO_FN(RESETA_N_PU_OFF), 3325 GPIO_FN(RESETA_N_PU_OFF),
2179 GPIO_FN(EDBGREQ_PD), 3326 GPIO_FN(EDBGREQ_PD),
2180 GPIO_FN(EDBGREQ_PU), 3327 GPIO_FN(EDBGREQ_PU),
3328};
2181 3329
2182 /* Functions with pull-ups */ 3330#undef PORTCR
2183 GPIO_FN(KEYIN0_PU), 3331#define PORTCR(nr, reg) \
2184 GPIO_FN(KEYIN1_PU), 3332 { \
2185 GPIO_FN(KEYIN2_PU), 3333 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2186 GPIO_FN(KEYIN3_PU), 3334 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
2187 GPIO_FN(KEYIN4_PU), 3335 PORT##nr##_FN0, PORT##nr##_FN1, \
2188 GPIO_FN(KEYIN5_PU), 3336 PORT##nr##_FN2, PORT##nr##_FN3, \
2189 GPIO_FN(KEYIN6_PU), 3337 PORT##nr##_FN4, PORT##nr##_FN5, \
2190 GPIO_FN(KEYIN7_PU), 3338 PORT##nr##_FN6, PORT##nr##_FN7 } \
2191 GPIO_FN(SDHICD0_PU), 3339 }
2192 GPIO_FN(SDHID0_0_PU), 3340static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2193 GPIO_FN(SDHID0_1_PU),
2194 GPIO_FN(SDHID0_2_PU),
2195 GPIO_FN(SDHID0_3_PU),
2196 GPIO_FN(SDHICMD0_PU),
2197 GPIO_FN(SDHIWP0_PU),
2198 GPIO_FN(SDHID1_0_PU),
2199 GPIO_FN(SDHID1_1_PU),
2200 GPIO_FN(SDHID1_2_PU),
2201 GPIO_FN(SDHID1_3_PU),
2202 GPIO_FN(SDHICMD1_PU),
2203 GPIO_FN(SDHID2_0_PU),
2204 GPIO_FN(SDHID2_1_PU),
2205 GPIO_FN(SDHID2_2_PU),
2206 GPIO_FN(SDHID2_3_PU),
2207 GPIO_FN(SDHICMD2_PU),
2208 GPIO_FN(MMCCMD0_PU),
2209 GPIO_FN(MMCCMD1_PU),
2210 GPIO_FN(MMCD0_0_PU),
2211 GPIO_FN(MMCD0_1_PU),
2212 GPIO_FN(MMCD0_2_PU),
2213 GPIO_FN(MMCD0_3_PU),
2214 GPIO_FN(MMCD0_4_PU),
2215 GPIO_FN(MMCD0_5_PU),
2216 GPIO_FN(MMCD0_6_PU),
2217 GPIO_FN(MMCD0_7_PU),
2218 GPIO_FN(FSIACK_PU),
2219 GPIO_FN(FSIAILR_PU),
2220 GPIO_FN(FSIAIBT_PU),
2221 GPIO_FN(FSIAISLD_PU),
2222};
2223
2224static struct pinmux_cfg_reg pinmux_config_regs[] = {
2225 PORTCR(0, 0xe6050000), /* PORT0CR */ 3341 PORTCR(0, 0xe6050000), /* PORT0CR */
2226 PORTCR(1, 0xe6050001), /* PORT1CR */ 3342 PORTCR(1, 0xe6050001), /* PORT1CR */
2227 PORTCR(2, 0xe6050002), /* PORT2CR */ 3343 PORTCR(2, 0xe6050002), /* PORT2CR */
@@ -2629,7 +3745,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2629 { }, 3745 { },
2630}; 3746};
2631 3747
2632static struct pinmux_data_reg pinmux_data_regs[] = { 3748static const struct pinmux_data_reg pinmux_data_regs[] = {
2633 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { 3749 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
2634 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, 3750 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2635 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, 3751 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
@@ -2737,56 +3853,112 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2737#define EXT_IRQ16L(n) irq_pin(n) 3853#define EXT_IRQ16L(n) irq_pin(n)
2738#define EXT_IRQ16H(n) irq_pin(n) 3854#define EXT_IRQ16H(n) irq_pin(n)
2739 3855
2740static struct pinmux_irq pinmux_irqs[] = { 3856static const struct pinmux_irq pinmux_irqs[] = {
2741 PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0), 3857 PINMUX_IRQ(EXT_IRQ16H(19), 9),
2742 PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0), 3858 PINMUX_IRQ(EXT_IRQ16L(1), 10),
2743 PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0), 3859 PINMUX_IRQ(EXT_IRQ16L(0), 11),
2744 PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0), 3860 PINMUX_IRQ(EXT_IRQ16H(18), 13),
2745 PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0), 3861 PINMUX_IRQ(EXT_IRQ16H(20), 14),
2746 PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0), 3862 PINMUX_IRQ(EXT_IRQ16H(21), 15),
2747 PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0), 3863 PINMUX_IRQ(EXT_IRQ16H(31), 26),
2748 PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0), 3864 PINMUX_IRQ(EXT_IRQ16H(30), 27),
2749 PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0), 3865 PINMUX_IRQ(EXT_IRQ16H(29), 28),
2750 PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0), 3866 PINMUX_IRQ(EXT_IRQ16H(22), 40),
2751 PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0), 3867 PINMUX_IRQ(EXT_IRQ16H(23), 53),
2752 PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0), 3868 PINMUX_IRQ(EXT_IRQ16L(10), 54),
2753 PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0), 3869 PINMUX_IRQ(EXT_IRQ16L(9), 56),
2754 PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0), 3870 PINMUX_IRQ(EXT_IRQ16H(26), 115),
2755 PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0), 3871 PINMUX_IRQ(EXT_IRQ16H(27), 116),
2756 PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0), 3872 PINMUX_IRQ(EXT_IRQ16H(28), 117),
2757 PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0), 3873 PINMUX_IRQ(EXT_IRQ16H(24), 118),
2758 PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0), 3874 PINMUX_IRQ(EXT_IRQ16L(6), 147),
2759 PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0), 3875 PINMUX_IRQ(EXT_IRQ16L(2), 149),
2760 PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0), 3876 PINMUX_IRQ(EXT_IRQ16L(7), 150),
2761 PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0), 3877 PINMUX_IRQ(EXT_IRQ16L(12), 156),
2762 PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0), 3878 PINMUX_IRQ(EXT_IRQ16L(4), 159),
2763 PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0), 3879 PINMUX_IRQ(EXT_IRQ16H(25), 164),
2764 PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0), 3880 PINMUX_IRQ(EXT_IRQ16L(8), 223),
2765 PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0), 3881 PINMUX_IRQ(EXT_IRQ16L(3), 224),
2766 PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0), 3882 PINMUX_IRQ(EXT_IRQ16L(5), 227),
2767 PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0), 3883 PINMUX_IRQ(EXT_IRQ16H(17), 234),
2768 PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0), 3884 PINMUX_IRQ(EXT_IRQ16L(11), 238),
2769 PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0), 3885 PINMUX_IRQ(EXT_IRQ16L(13), 239),
2770 PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0), 3886 PINMUX_IRQ(EXT_IRQ16H(16), 249),
2771 PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0), 3887 PINMUX_IRQ(EXT_IRQ16L(14), 251),
2772 PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0), 3888 PINMUX_IRQ(EXT_IRQ16L(9), 308),
2773}; 3889};
2774 3890
2775struct sh_pfc_soc_info sh73a0_pinmux_info = { 3891#define PORTnCR_PULMD_OFF (0 << 6)
3892#define PORTnCR_PULMD_DOWN (2 << 6)
3893#define PORTnCR_PULMD_UP (3 << 6)
3894#define PORTnCR_PULMD_MASK (3 << 6)
3895
3896static const unsigned int sh73a0_portcr_offsets[] = {
3897 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
3898 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
3899};
3900
3901static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3902{
3903 void __iomem *addr = pfc->window->virt
3904 + sh73a0_portcr_offsets[pin >> 5] + pin;
3905 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3906
3907 switch (value) {
3908 case PORTnCR_PULMD_UP:
3909 return PIN_CONFIG_BIAS_PULL_UP;
3910 case PORTnCR_PULMD_DOWN:
3911 return PIN_CONFIG_BIAS_PULL_DOWN;
3912 case PORTnCR_PULMD_OFF:
3913 default:
3914 return PIN_CONFIG_BIAS_DISABLE;
3915 }
3916}
3917
3918static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3919 unsigned int bias)
3920{
3921 void __iomem *addr = pfc->window->virt
3922 + sh73a0_portcr_offsets[pin >> 5] + pin;
3923 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3924
3925 switch (bias) {
3926 case PIN_CONFIG_BIAS_PULL_UP:
3927 value |= PORTnCR_PULMD_UP;
3928 break;
3929 case PIN_CONFIG_BIAS_PULL_DOWN:
3930 value |= PORTnCR_PULMD_DOWN;
3931 break;
3932 }
3933
3934 iowrite8(value, addr);
3935}
3936
3937static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
3938 .get_bias = sh73a0_pinmux_get_bias,
3939 .set_bias = sh73a0_pinmux_set_bias,
3940};
3941
3942const struct sh_pfc_soc_info sh73a0_pinmux_info = {
2776 .name = "sh73a0_pfc", 3943 .name = "sh73a0_pfc",
2777 .reserved_id = PINMUX_RESERVED, 3944 .ops = &sh73a0_pinmux_ops,
2778 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, 3945
2779 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 3946 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2780 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2781 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
2782 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 3947 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2783 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2784 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 3948 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2785 3949
2786 .first_gpio = GPIO_PORT0, 3950 .pins = pinmux_pins,
2787 .last_gpio = GPIO_FN_FSIAISLD_PU, 3951 .nr_pins = ARRAY_SIZE(pinmux_pins),
3952 .ranges = pinmux_ranges,
3953 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
3954 .groups = pinmux_groups,
3955 .nr_groups = ARRAY_SIZE(pinmux_groups),
3956 .functions = pinmux_functions,
3957 .nr_functions = ARRAY_SIZE(pinmux_functions),
3958
3959 .func_gpios = pinmux_func_gpios,
3960 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2788 3961
2789 .gpios = pinmux_gpios,
2790 .cfg_regs = pinmux_config_regs, 3962 .cfg_regs = pinmux_config_regs,
2791 .data_regs = pinmux_data_regs, 3963 .data_regs = pinmux_data_regs,
2792 3964
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index 10872ed688a6..52e9f6be665f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -262,7 +262,7 @@ enum {
262 PINMUX_MARK_END, 262 PINMUX_MARK_END,
263}; 263};
264 264
265static pinmux_enum_t pinmux_data[] = { 265static const pinmux_enum_t pinmux_data[] = {
266 /* PTA GPIO */ 266 /* PTA GPIO */
267 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), 267 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
268 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), 268 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
@@ -606,7 +606,7 @@ static pinmux_enum_t pinmux_data[] = {
606 PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN), 606 PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN),
607}; 607};
608 608
609static struct pinmux_gpio pinmux_gpios[] = { 609static struct sh_pfc_pin pinmux_pins[] = {
610 /* PTA */ 610 /* PTA */
611 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), 611 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
612 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), 612 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -759,202 +759,205 @@ static struct pinmux_gpio pinmux_gpios[] = {
759 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), 759 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
760 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), 760 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
761 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), 761 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
762};
763
764#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
762 765
766static const struct pinmux_func pinmux_func_gpios[] = {
763 /* BSC */ 767 /* BSC */
764 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 768 GPIO_FN(D31),
765 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 769 GPIO_FN(D30),
766 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 770 GPIO_FN(D29),
767 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 771 GPIO_FN(D28),
768 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 772 GPIO_FN(D27),
769 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 773 GPIO_FN(D26),
770 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 774 GPIO_FN(D25),
771 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 775 GPIO_FN(D24),
772 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 776 GPIO_FN(D23),
773 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 777 GPIO_FN(D22),
774 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 778 GPIO_FN(D21),
775 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 779 GPIO_FN(D20),
776 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 780 GPIO_FN(D19),
777 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 781 GPIO_FN(D18),
778 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 782 GPIO_FN(D17),
779 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 783 GPIO_FN(D16),
780 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 784 GPIO_FN(IOIS16),
781 PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), 785 GPIO_FN(RAS),
782 PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), 786 GPIO_FN(CAS),
783 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), 787 GPIO_FN(CKE),
784 PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), 788 GPIO_FN(CS5B_CE1A),
785 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), 789 GPIO_FN(CS6B_CE1B),
786 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 790 GPIO_FN(A25),
787 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 791 GPIO_FN(A24),
788 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 792 GPIO_FN(A23),
789 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 793 GPIO_FN(A22),
790 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 794 GPIO_FN(A21),
791 PINMUX_GPIO(GPIO_FN_A20, A20_MARK), 795 GPIO_FN(A20),
792 PINMUX_GPIO(GPIO_FN_A19, A19_MARK), 796 GPIO_FN(A19),
793 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 797 GPIO_FN(A0),
794 PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), 798 GPIO_FN(REFOUT),
795 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), 799 GPIO_FN(IRQOUT),
796 800
797 /* LCDC */ 801 /* LCDC */
798 PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), 802 GPIO_FN(LCD_DATA15),
799 PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), 803 GPIO_FN(LCD_DATA14),
800 PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), 804 GPIO_FN(LCD_DATA13),
801 PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), 805 GPIO_FN(LCD_DATA12),
802 PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), 806 GPIO_FN(LCD_DATA11),
803 PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), 807 GPIO_FN(LCD_DATA10),
804 PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), 808 GPIO_FN(LCD_DATA9),
805 PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), 809 GPIO_FN(LCD_DATA8),
806 PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), 810 GPIO_FN(LCD_DATA7),
807 PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), 811 GPIO_FN(LCD_DATA6),
808 PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), 812 GPIO_FN(LCD_DATA5),
809 PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), 813 GPIO_FN(LCD_DATA4),
810 PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), 814 GPIO_FN(LCD_DATA3),
811 PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), 815 GPIO_FN(LCD_DATA2),
812 PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), 816 GPIO_FN(LCD_DATA1),
813 PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), 817 GPIO_FN(LCD_DATA0),
814 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), 818 GPIO_FN(LCD_M_DISP),
815 PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), 819 GPIO_FN(LCD_CL1),
816 PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), 820 GPIO_FN(LCD_CL2),
817 PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), 821 GPIO_FN(LCD_DON),
818 PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), 822 GPIO_FN(LCD_FLM),
819 PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), 823 GPIO_FN(LCD_VEPWC),
820 PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), 824 GPIO_FN(LCD_VCPWC),
821 825
822 /* AFEIF */ 826 /* AFEIF */
823 PINMUX_GPIO(GPIO_FN_AFE_RXIN, AFE_RXIN_MARK), 827 GPIO_FN(AFE_RXIN),
824 PINMUX_GPIO(GPIO_FN_AFE_RDET, AFE_RDET_MARK), 828 GPIO_FN(AFE_RDET),
825 PINMUX_GPIO(GPIO_FN_AFE_FS, AFE_FS_MARK), 829 GPIO_FN(AFE_FS),
826 PINMUX_GPIO(GPIO_FN_AFE_TXOUT, AFE_TXOUT_MARK), 830 GPIO_FN(AFE_TXOUT),
827 PINMUX_GPIO(GPIO_FN_AFE_SCLK, AFE_SCLK_MARK), 831 GPIO_FN(AFE_SCLK),
828 PINMUX_GPIO(GPIO_FN_AFE_RLYCNT, AFE_RLYCNT_MARK), 832 GPIO_FN(AFE_RLYCNT),
829 PINMUX_GPIO(GPIO_FN_AFE_HC1, AFE_HC1_MARK), 833 GPIO_FN(AFE_HC1),
830 834
831 /* IIC */ 835 /* IIC */
832 PINMUX_GPIO(GPIO_FN_IIC_SCL, IIC_SCL_MARK), 836 GPIO_FN(IIC_SCL),
833 PINMUX_GPIO(GPIO_FN_IIC_SDA, IIC_SDA_MARK), 837 GPIO_FN(IIC_SDA),
834 838
835 /* DAC */ 839 /* DAC */
836 PINMUX_GPIO(GPIO_FN_DA1, DA1_MARK), 840 GPIO_FN(DA1),
837 PINMUX_GPIO(GPIO_FN_DA0, DA0_MARK), 841 GPIO_FN(DA0),
838 842
839 /* ADC */ 843 /* ADC */
840 PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), 844 GPIO_FN(AN3),
841 PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), 845 GPIO_FN(AN2),
842 PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), 846 GPIO_FN(AN1),
843 PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), 847 GPIO_FN(AN0),
844 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), 848 GPIO_FN(ADTRG),
845 849
846 /* USB */ 850 /* USB */
847 PINMUX_GPIO(GPIO_FN_USB1D_RCV, USB1D_RCV_MARK), 851 GPIO_FN(USB1D_RCV),
848 PINMUX_GPIO(GPIO_FN_USB1D_TXSE0, USB1D_TXSE0_MARK), 852 GPIO_FN(USB1D_TXSE0),
849 PINMUX_GPIO(GPIO_FN_USB1D_TXDPLS, USB1D_TXDPLS_MARK), 853 GPIO_FN(USB1D_TXDPLS),
850 PINMUX_GPIO(GPIO_FN_USB1D_DMNS, USB1D_DMNS_MARK), 854 GPIO_FN(USB1D_DMNS),
851 PINMUX_GPIO(GPIO_FN_USB1D_DPLS, USB1D_DPLS_MARK), 855 GPIO_FN(USB1D_DPLS),
852 PINMUX_GPIO(GPIO_FN_USB1D_SPEED, USB1D_SPEED_MARK), 856 GPIO_FN(USB1D_SPEED),
853 PINMUX_GPIO(GPIO_FN_USB1D_TXENL, USB1D_TXENL_MARK), 857 GPIO_FN(USB1D_TXENL),
854 858
855 PINMUX_GPIO(GPIO_FN_USB2_PWR_EN, USB2_PWR_EN_MARK), 859 GPIO_FN(USB2_PWR_EN),
856 PINMUX_GPIO(GPIO_FN_USB1_PWR_EN_USBF_UPLUP, 860 GPIO_FN(USB1_PWR_EN_USBF_UPLUP),
857 USB1_PWR_EN_USBF_UPLUP_MARK), 861 GPIO_FN(USB1D_SUSPEND),
858 PINMUX_GPIO(GPIO_FN_USB1D_SUSPEND, USB1D_SUSPEND_MARK),
859 862
860 /* INTC */ 863 /* INTC */
861 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), 864 GPIO_FN(IRQ5),
862 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), 865 GPIO_FN(IRQ4),
863 PINMUX_GPIO(GPIO_FN_IRQ3_IRL3, IRQ3_IRL3_MARK), 866 GPIO_FN(IRQ3_IRL3),
864 PINMUX_GPIO(GPIO_FN_IRQ2_IRL2, IRQ2_IRL2_MARK), 867 GPIO_FN(IRQ2_IRL2),
865 PINMUX_GPIO(GPIO_FN_IRQ1_IRL1, IRQ1_IRL1_MARK), 868 GPIO_FN(IRQ1_IRL1),
866 PINMUX_GPIO(GPIO_FN_IRQ0_IRL0, IRQ0_IRL0_MARK), 869 GPIO_FN(IRQ0_IRL0),
867 870
868 /* PCC */ 871 /* PCC */
869 PINMUX_GPIO(GPIO_FN_PCC_REG, PCC_REG_MARK), 872 GPIO_FN(PCC_REG),
870 PINMUX_GPIO(GPIO_FN_PCC_DRV, PCC_DRV_MARK), 873 GPIO_FN(PCC_DRV),
871 PINMUX_GPIO(GPIO_FN_PCC_BVD2, PCC_BVD2_MARK), 874 GPIO_FN(PCC_BVD2),
872 PINMUX_GPIO(GPIO_FN_PCC_BVD1, PCC_BVD1_MARK), 875 GPIO_FN(PCC_BVD1),
873 PINMUX_GPIO(GPIO_FN_PCC_CD2, PCC_CD2_MARK), 876 GPIO_FN(PCC_CD2),
874 PINMUX_GPIO(GPIO_FN_PCC_CD1, PCC_CD1_MARK), 877 GPIO_FN(PCC_CD1),
875 PINMUX_GPIO(GPIO_FN_PCC_RESET, PCC_RESET_MARK), 878 GPIO_FN(PCC_RESET),
876 PINMUX_GPIO(GPIO_FN_PCC_RDY, PCC_RDY_MARK), 879 GPIO_FN(PCC_RDY),
877 PINMUX_GPIO(GPIO_FN_PCC_VS2, PCC_VS2_MARK), 880 GPIO_FN(PCC_VS2),
878 PINMUX_GPIO(GPIO_FN_PCC_VS1, PCC_VS1_MARK), 881 GPIO_FN(PCC_VS1),
879 882
880 /* HUDI */ 883 /* HUDI */
881 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 884 GPIO_FN(AUDATA3),
882 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 885 GPIO_FN(AUDATA2),
883 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 886 GPIO_FN(AUDATA1),
884 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 887 GPIO_FN(AUDATA0),
885 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), 888 GPIO_FN(AUDCK),
886 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 889 GPIO_FN(AUDSYNC),
887 PINMUX_GPIO(GPIO_FN_ASEBRKAK, ASEBRKAK_MARK), 890 GPIO_FN(ASEBRKAK),
888 PINMUX_GPIO(GPIO_FN_TRST, TRST_MARK), 891 GPIO_FN(TRST),
889 PINMUX_GPIO(GPIO_FN_TMS, TMS_MARK), 892 GPIO_FN(TMS),
890 PINMUX_GPIO(GPIO_FN_TDO, TDO_MARK), 893 GPIO_FN(TDO),
891 PINMUX_GPIO(GPIO_FN_TDI, TDI_MARK), 894 GPIO_FN(TDI),
892 PINMUX_GPIO(GPIO_FN_TCK, TCK_MARK), 895 GPIO_FN(TCK),
893 896
894 /* DMAC */ 897 /* DMAC */
895 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 898 GPIO_FN(DACK1),
896 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 899 GPIO_FN(DREQ1),
897 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 900 GPIO_FN(DACK0),
898 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 901 GPIO_FN(DREQ0),
899 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), 902 GPIO_FN(TEND1),
900 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), 903 GPIO_FN(TEND0),
901 904
902 /* SIOF0 */ 905 /* SIOF0 */
903 PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), 906 GPIO_FN(SIOF0_SYNC),
904 PINMUX_GPIO(GPIO_FN_SIOF0_MCLK, SIOF0_MCLK_MARK), 907 GPIO_FN(SIOF0_MCLK),
905 PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), 908 GPIO_FN(SIOF0_TXD),
906 PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), 909 GPIO_FN(SIOF0_RXD),
907 PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), 910 GPIO_FN(SIOF0_SCK),
908 911
909 /* SIOF1 */ 912 /* SIOF1 */
910 PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), 913 GPIO_FN(SIOF1_SYNC),
911 PINMUX_GPIO(GPIO_FN_SIOF1_MCLK, SIOF1_MCLK_MARK), 914 GPIO_FN(SIOF1_MCLK),
912 PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), 915 GPIO_FN(SIOF1_TXD),
913 PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), 916 GPIO_FN(SIOF1_RXD),
914 PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), 917 GPIO_FN(SIOF1_SCK),
915 918
916 /* SCIF0 */ 919 /* SCIF0 */
917 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), 920 GPIO_FN(SCIF0_TXD),
918 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), 921 GPIO_FN(SCIF0_RXD),
919 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), 922 GPIO_FN(SCIF0_RTS),
920 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), 923 GPIO_FN(SCIF0_CTS),
921 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), 924 GPIO_FN(SCIF0_SCK),
922 925
923 /* SCIF1 */ 926 /* SCIF1 */
924 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), 927 GPIO_FN(SCIF1_TXD),
925 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), 928 GPIO_FN(SCIF1_RXD),
926 PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), 929 GPIO_FN(SCIF1_RTS),
927 PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), 930 GPIO_FN(SCIF1_CTS),
928 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), 931 GPIO_FN(SCIF1_SCK),
929 932
930 /* TPU */ 933 /* TPU */
931 PINMUX_GPIO(GPIO_FN_TPU_TO1, TPU_TO1_MARK), 934 GPIO_FN(TPU_TO1),
932 PINMUX_GPIO(GPIO_FN_TPU_TO0, TPU_TO0_MARK), 935 GPIO_FN(TPU_TO0),
933 PINMUX_GPIO(GPIO_FN_TPU_TI3B, TPU_TI3B_MARK), 936 GPIO_FN(TPU_TI3B),
934 PINMUX_GPIO(GPIO_FN_TPU_TI3A, TPU_TI3A_MARK), 937 GPIO_FN(TPU_TI3A),
935 PINMUX_GPIO(GPIO_FN_TPU_TI2B, TPU_TI2B_MARK), 938 GPIO_FN(TPU_TI2B),
936 PINMUX_GPIO(GPIO_FN_TPU_TI2A, TPU_TI2A_MARK), 939 GPIO_FN(TPU_TI2A),
937 PINMUX_GPIO(GPIO_FN_TPU_TO3, TPU_TO3_MARK), 940 GPIO_FN(TPU_TO3),
938 PINMUX_GPIO(GPIO_FN_TPU_TO2, TPU_TO2_MARK), 941 GPIO_FN(TPU_TO2),
939 942
940 /* SIM */ 943 /* SIM */
941 PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), 944 GPIO_FN(SIM_D),
942 PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), 945 GPIO_FN(SIM_CLK),
943 PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), 946 GPIO_FN(SIM_RST),
944 947
945 /* MMC */ 948 /* MMC */
946 PINMUX_GPIO(GPIO_FN_MMC_DAT, MMC_DAT_MARK), 949 GPIO_FN(MMC_DAT),
947 PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), 950 GPIO_FN(MMC_CMD),
948 PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), 951 GPIO_FN(MMC_CLK),
949 PINMUX_GPIO(GPIO_FN_MMC_VDDON, MMC_VDDON_MARK), 952 GPIO_FN(MMC_VDDON),
950 PINMUX_GPIO(GPIO_FN_MMC_ODMOD, MMC_ODMOD_MARK), 953 GPIO_FN(MMC_ODMOD),
951 954
952 /* SYSC */ 955 /* SYSC */
953 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 956 GPIO_FN(STATUS0),
954 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), 957 GPIO_FN(STATUS1),
955}; 958};
956 959
957static struct pinmux_cfg_reg pinmux_config_regs[] = { 960static const struct pinmux_cfg_reg pinmux_config_regs[] = {
958 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 961 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
959 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, 962 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
960 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, 963 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
@@ -1138,7 +1141,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1138 {} 1141 {}
1139}; 1142};
1140 1143
1141static struct pinmux_data_reg pinmux_data_regs[] = { 1144static const struct pinmux_data_reg pinmux_data_regs[] = {
1142 { PINMUX_DATA_REG("PADR", 0xa4050140, 8) { 1145 { PINMUX_DATA_REG("PADR", 0xa4050140, 8) {
1143 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 1146 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1144 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 1147 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1214,20 +1217,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1214 { }, 1217 { },
1215}; 1218};
1216 1219
1217struct sh_pfc_soc_info sh7720_pinmux_info = { 1220const struct sh_pfc_soc_info sh7720_pinmux_info = {
1218 .name = "sh7720_pfc", 1221 .name = "sh7720_pfc",
1219 .reserved_id = PINMUX_RESERVED,
1220 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1221 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 1222 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1222 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 1223 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1223 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 1224 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1224 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1225 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1225 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1226 1226
1227 .first_gpio = GPIO_PTA7, 1227 .pins = pinmux_pins,
1228 .last_gpio = GPIO_FN_STATUS1, 1228 .nr_pins = ARRAY_SIZE(pinmux_pins),
1229 .func_gpios = pinmux_func_gpios,
1230 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1229 1231
1230 .gpios = pinmux_gpios,
1231 .cfg_regs = pinmux_config_regs, 1232 .cfg_regs = pinmux_config_regs,
1232 .data_regs = pinmux_data_regs, 1233 .data_regs = pinmux_data_regs,
1233 1234
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index 2de0929315e6..32034387477b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -296,7 +296,7 @@ enum {
296 PINMUX_FUNCTION_END, 296 PINMUX_FUNCTION_END,
297}; 297};
298 298
299static pinmux_enum_t pinmux_data[] = { 299static const pinmux_enum_t pinmux_data[] = {
300 /* PTA */ 300 /* PTA */
301 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT), 301 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT),
302 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD), 302 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD),
@@ -787,7 +787,7 @@ static pinmux_enum_t pinmux_data[] = {
787 PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5), 787 PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5),
788}; 788};
789 789
790static struct pinmux_gpio pinmux_gpios[] = { 790static struct sh_pfc_pin pinmux_pins[] = {
791 /* PTA */ 791 /* PTA */
792 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), 792 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
793 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), 793 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -982,289 +982,293 @@ static struct pinmux_gpio pinmux_gpios[] = {
982 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), 982 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
983 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), 983 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
984 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), 984 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
985};
986
987#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
985 988
989static const struct pinmux_func pinmux_func_gpios[] = {
986 /* SCIF0 */ 990 /* SCIF0 */
987 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), 991 GPIO_FN(SCIF0_TXD),
988 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), 992 GPIO_FN(SCIF0_RXD),
989 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), 993 GPIO_FN(SCIF0_RTS),
990 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), 994 GPIO_FN(SCIF0_CTS),
991 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), 995 GPIO_FN(SCIF0_SCK),
992 996
993 /* SCIF1 */ 997 /* SCIF1 */
994 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), 998 GPIO_FN(SCIF1_TXD),
995 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), 999 GPIO_FN(SCIF1_RXD),
996 PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), 1000 GPIO_FN(SCIF1_RTS),
997 PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), 1001 GPIO_FN(SCIF1_CTS),
998 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), 1002 GPIO_FN(SCIF1_SCK),
999 1003
1000 /* SCIF2 */ 1004 /* SCIF2 */
1001 PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), 1005 GPIO_FN(SCIF2_TXD),
1002 PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), 1006 GPIO_FN(SCIF2_RXD),
1003 PINMUX_GPIO(GPIO_FN_SCIF2_RTS, SCIF2_RTS_MARK), 1007 GPIO_FN(SCIF2_RTS),
1004 PINMUX_GPIO(GPIO_FN_SCIF2_CTS, SCIF2_CTS_MARK), 1008 GPIO_FN(SCIF2_CTS),
1005 PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), 1009 GPIO_FN(SCIF2_SCK),
1006 1010
1007 /* SIO */ 1011 /* SIO */
1008 PINMUX_GPIO(GPIO_FN_SIOTXD, SIOTXD_MARK), 1012 GPIO_FN(SIOTXD),
1009 PINMUX_GPIO(GPIO_FN_SIORXD, SIORXD_MARK), 1013 GPIO_FN(SIORXD),
1010 PINMUX_GPIO(GPIO_FN_SIOD, SIOD_MARK), 1014 GPIO_FN(SIOD),
1011 PINMUX_GPIO(GPIO_FN_SIOSTRB0, SIOSTRB0_MARK), 1015 GPIO_FN(SIOSTRB0),
1012 PINMUX_GPIO(GPIO_FN_SIOSTRB1, SIOSTRB1_MARK), 1016 GPIO_FN(SIOSTRB1),
1013 PINMUX_GPIO(GPIO_FN_SIOSCK, SIOSCK_MARK), 1017 GPIO_FN(SIOSCK),
1014 PINMUX_GPIO(GPIO_FN_SIOMCK, SIOMCK_MARK), 1018 GPIO_FN(SIOMCK),
1015 1019
1016 /* CEU */ 1020 /* CEU */
1017 PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), 1021 GPIO_FN(VIO_D15),
1018 PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), 1022 GPIO_FN(VIO_D14),
1019 PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), 1023 GPIO_FN(VIO_D13),
1020 PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), 1024 GPIO_FN(VIO_D12),
1021 PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), 1025 GPIO_FN(VIO_D11),
1022 PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), 1026 GPIO_FN(VIO_D10),
1023 PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), 1027 GPIO_FN(VIO_D9),
1024 PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), 1028 GPIO_FN(VIO_D8),
1025 PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), 1029 GPIO_FN(VIO_D7),
1026 PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), 1030 GPIO_FN(VIO_D6),
1027 PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), 1031 GPIO_FN(VIO_D5),
1028 PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), 1032 GPIO_FN(VIO_D4),
1029 PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), 1033 GPIO_FN(VIO_D3),
1030 PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), 1034 GPIO_FN(VIO_D2),
1031 PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), 1035 GPIO_FN(VIO_D1),
1032 PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), 1036 GPIO_FN(VIO_D0),
1033 PINMUX_GPIO(GPIO_FN_VIO_CLK, VIO_CLK_MARK), 1037 GPIO_FN(VIO_CLK),
1034 PINMUX_GPIO(GPIO_FN_VIO_VD, VIO_VD_MARK), 1038 GPIO_FN(VIO_VD),
1035 PINMUX_GPIO(GPIO_FN_VIO_HD, VIO_HD_MARK), 1039 GPIO_FN(VIO_HD),
1036 PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), 1040 GPIO_FN(VIO_FLD),
1037 PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), 1041 GPIO_FN(VIO_CKO),
1038 PINMUX_GPIO(GPIO_FN_VIO_STEX, VIO_STEX_MARK), 1042 GPIO_FN(VIO_STEX),
1039 PINMUX_GPIO(GPIO_FN_VIO_STEM, VIO_STEM_MARK), 1043 GPIO_FN(VIO_STEM),
1040 PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), 1044 GPIO_FN(VIO_VD2),
1041 PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), 1045 GPIO_FN(VIO_HD2),
1042 PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), 1046 GPIO_FN(VIO_CLK2),
1043 1047
1044 /* LCDC */ 1048 /* LCDC */
1045 PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), 1049 GPIO_FN(LCDD23),
1046 PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), 1050 GPIO_FN(LCDD22),
1047 PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), 1051 GPIO_FN(LCDD21),
1048 PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), 1052 GPIO_FN(LCDD20),
1049 PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), 1053 GPIO_FN(LCDD19),
1050 PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), 1054 GPIO_FN(LCDD18),
1051 PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), 1055 GPIO_FN(LCDD17),
1052 PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), 1056 GPIO_FN(LCDD16),
1053 PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), 1057 GPIO_FN(LCDD15),
1054 PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), 1058 GPIO_FN(LCDD14),
1055 PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), 1059 GPIO_FN(LCDD13),
1056 PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), 1060 GPIO_FN(LCDD12),
1057 PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), 1061 GPIO_FN(LCDD11),
1058 PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), 1062 GPIO_FN(LCDD10),
1059 PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), 1063 GPIO_FN(LCDD9),
1060 PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), 1064 GPIO_FN(LCDD8),
1061 PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), 1065 GPIO_FN(LCDD7),
1062 PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), 1066 GPIO_FN(LCDD6),
1063 PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), 1067 GPIO_FN(LCDD5),
1064 PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), 1068 GPIO_FN(LCDD4),
1065 PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), 1069 GPIO_FN(LCDD3),
1066 PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), 1070 GPIO_FN(LCDD2),
1067 PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), 1071 GPIO_FN(LCDD1),
1068 PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), 1072 GPIO_FN(LCDD0),
1069 PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), 1073 GPIO_FN(LCDLCLK),
1070 /* Main LCD */ 1074 /* Main LCD */
1071 PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), 1075 GPIO_FN(LCDDON),
1072 PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), 1076 GPIO_FN(LCDVCPWC),
1073 PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), 1077 GPIO_FN(LCDVEPWC),
1074 PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), 1078 GPIO_FN(LCDVSYN),
1075 /* Main LCD - RGB Mode */ 1079 /* Main LCD - RGB Mode */
1076 PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), 1080 GPIO_FN(LCDDCK),
1077 PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), 1081 GPIO_FN(LCDHSYN),
1078 PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), 1082 GPIO_FN(LCDDISP),
1079 /* Main LCD - SYS Mode */ 1083 /* Main LCD - SYS Mode */
1080 PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), 1084 GPIO_FN(LCDRS),
1081 PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), 1085 GPIO_FN(LCDCS),
1082 PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), 1086 GPIO_FN(LCDWR),
1083 PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), 1087 GPIO_FN(LCDRD),
1084 /* Sub LCD - SYS Mode */ 1088 /* Sub LCD - SYS Mode */
1085 PINMUX_GPIO(GPIO_FN_LCDDON2, LCDDON2_MARK), 1089 GPIO_FN(LCDDON2),
1086 PINMUX_GPIO(GPIO_FN_LCDVCPWC2, LCDVCPWC2_MARK), 1090 GPIO_FN(LCDVCPWC2),
1087 PINMUX_GPIO(GPIO_FN_LCDVEPWC2, LCDVEPWC2_MARK), 1091 GPIO_FN(LCDVEPWC2),
1088 PINMUX_GPIO(GPIO_FN_LCDVSYN2, LCDVSYN2_MARK), 1092 GPIO_FN(LCDVSYN2),
1089 PINMUX_GPIO(GPIO_FN_LCDCS2, LCDCS2_MARK), 1093 GPIO_FN(LCDCS2),
1090 1094
1091 /* BSC */ 1095 /* BSC */
1092 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 1096 GPIO_FN(IOIS16),
1093 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1097 GPIO_FN(A25),
1094 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1098 GPIO_FN(A24),
1095 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1099 GPIO_FN(A23),
1096 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1100 GPIO_FN(A22),
1097 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1101 GPIO_FN(BS),
1098 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), 1102 GPIO_FN(CS6B_CE1B),
1099 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 1103 GPIO_FN(WAIT),
1100 PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), 1104 GPIO_FN(CS6A_CE2B),
1101 1105
1102 /* SBSC */ 1106 /* SBSC */
1103 PINMUX_GPIO(GPIO_FN_HPD63, HPD63_MARK), 1107 GPIO_FN(HPD63),
1104 PINMUX_GPIO(GPIO_FN_HPD62, HPD62_MARK), 1108 GPIO_FN(HPD62),
1105 PINMUX_GPIO(GPIO_FN_HPD61, HPD61_MARK), 1109 GPIO_FN(HPD61),
1106 PINMUX_GPIO(GPIO_FN_HPD60, HPD60_MARK), 1110 GPIO_FN(HPD60),
1107 PINMUX_GPIO(GPIO_FN_HPD59, HPD59_MARK), 1111 GPIO_FN(HPD59),
1108 PINMUX_GPIO(GPIO_FN_HPD58, HPD58_MARK), 1112 GPIO_FN(HPD58),
1109 PINMUX_GPIO(GPIO_FN_HPD57, HPD57_MARK), 1113 GPIO_FN(HPD57),
1110 PINMUX_GPIO(GPIO_FN_HPD56, HPD56_MARK), 1114 GPIO_FN(HPD56),
1111 PINMUX_GPIO(GPIO_FN_HPD55, HPD55_MARK), 1115 GPIO_FN(HPD55),
1112 PINMUX_GPIO(GPIO_FN_HPD54, HPD54_MARK), 1116 GPIO_FN(HPD54),
1113 PINMUX_GPIO(GPIO_FN_HPD53, HPD53_MARK), 1117 GPIO_FN(HPD53),
1114 PINMUX_GPIO(GPIO_FN_HPD52, HPD52_MARK), 1118 GPIO_FN(HPD52),
1115 PINMUX_GPIO(GPIO_FN_HPD51, HPD51_MARK), 1119 GPIO_FN(HPD51),
1116 PINMUX_GPIO(GPIO_FN_HPD50, HPD50_MARK), 1120 GPIO_FN(HPD50),
1117 PINMUX_GPIO(GPIO_FN_HPD49, HPD49_MARK), 1121 GPIO_FN(HPD49),
1118 PINMUX_GPIO(GPIO_FN_HPD48, HPD48_MARK), 1122 GPIO_FN(HPD48),
1119 PINMUX_GPIO(GPIO_FN_HPDQM7, HPDQM7_MARK), 1123 GPIO_FN(HPDQM7),
1120 PINMUX_GPIO(GPIO_FN_HPDQM6, HPDQM6_MARK), 1124 GPIO_FN(HPDQM6),
1121 PINMUX_GPIO(GPIO_FN_HPDQM5, HPDQM5_MARK), 1125 GPIO_FN(HPDQM5),
1122 PINMUX_GPIO(GPIO_FN_HPDQM4, HPDQM4_MARK), 1126 GPIO_FN(HPDQM4),
1123 1127
1124 /* IRQ */ 1128 /* IRQ */
1125 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), 1129 GPIO_FN(IRQ0),
1126 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), 1130 GPIO_FN(IRQ1),
1127 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), 1131 GPIO_FN(IRQ2),
1128 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), 1132 GPIO_FN(IRQ3),
1129 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), 1133 GPIO_FN(IRQ4),
1130 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), 1134 GPIO_FN(IRQ5),
1131 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), 1135 GPIO_FN(IRQ6),
1132 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), 1136 GPIO_FN(IRQ7),
1133 1137
1134 /* SDHI */ 1138 /* SDHI */
1135 PINMUX_GPIO(GPIO_FN_SDHICD, SDHICD_MARK), 1139 GPIO_FN(SDHICD),
1136 PINMUX_GPIO(GPIO_FN_SDHIWP, SDHIWP_MARK), 1140 GPIO_FN(SDHIWP),
1137 PINMUX_GPIO(GPIO_FN_SDHID3, SDHID3_MARK), 1141 GPIO_FN(SDHID3),
1138 PINMUX_GPIO(GPIO_FN_SDHID2, SDHID2_MARK), 1142 GPIO_FN(SDHID2),
1139 PINMUX_GPIO(GPIO_FN_SDHID1, SDHID1_MARK), 1143 GPIO_FN(SDHID1),
1140 PINMUX_GPIO(GPIO_FN_SDHID0, SDHID0_MARK), 1144 GPIO_FN(SDHID0),
1141 PINMUX_GPIO(GPIO_FN_SDHICMD, SDHICMD_MARK), 1145 GPIO_FN(SDHICMD),
1142 PINMUX_GPIO(GPIO_FN_SDHICLK, SDHICLK_MARK), 1146 GPIO_FN(SDHICLK),
1143 1147
1144 /* SIU - Port A */ 1148 /* SIU - Port A */
1145 PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), 1149 GPIO_FN(SIUAOLR),
1146 PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), 1150 GPIO_FN(SIUAOBT),
1147 PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), 1151 GPIO_FN(SIUAISLD),
1148 PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), 1152 GPIO_FN(SIUAILR),
1149 PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), 1153 GPIO_FN(SIUAIBT),
1150 PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), 1154 GPIO_FN(SIUAOSLD),
1151 PINMUX_GPIO(GPIO_FN_SIUMCKA, SIUMCKA_MARK), 1155 GPIO_FN(SIUMCKA),
1152 PINMUX_GPIO(GPIO_FN_SIUFCKA, SIUFCKA_MARK), 1156 GPIO_FN(SIUFCKA),
1153 1157
1154 /* SIU - Port B */ 1158 /* SIU - Port B */
1155 PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), 1159 GPIO_FN(SIUBOLR),
1156 PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), 1160 GPIO_FN(SIUBOBT),
1157 PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), 1161 GPIO_FN(SIUBISLD),
1158 PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), 1162 GPIO_FN(SIUBILR),
1159 PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), 1163 GPIO_FN(SIUBIBT),
1160 PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), 1164 GPIO_FN(SIUBOSLD),
1161 PINMUX_GPIO(GPIO_FN_SIUMCKB, SIUMCKB_MARK), 1165 GPIO_FN(SIUMCKB),
1162 PINMUX_GPIO(GPIO_FN_SIUFCKB, SIUFCKB_MARK), 1166 GPIO_FN(SIUFCKB),
1163 1167
1164 /* AUD */ 1168 /* AUD */
1165 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 1169 GPIO_FN(AUDSYNC),
1166 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 1170 GPIO_FN(AUDATA3),
1167 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 1171 GPIO_FN(AUDATA2),
1168 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 1172 GPIO_FN(AUDATA1),
1169 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 1173 GPIO_FN(AUDATA0),
1170 1174
1171 /* DMAC */ 1175 /* DMAC */
1172 PINMUX_GPIO(GPIO_FN_DACK, DACK_MARK), 1176 GPIO_FN(DACK),
1173 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 1177 GPIO_FN(DREQ0),
1174 1178
1175 /* VOU */ 1179 /* VOU */
1176 PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), 1180 GPIO_FN(DV_CLKI),
1177 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), 1181 GPIO_FN(DV_CLK),
1178 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), 1182 GPIO_FN(DV_HSYNC),
1179 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), 1183 GPIO_FN(DV_VSYNC),
1180 PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), 1184 GPIO_FN(DV_D15),
1181 PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), 1185 GPIO_FN(DV_D14),
1182 PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), 1186 GPIO_FN(DV_D13),
1183 PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), 1187 GPIO_FN(DV_D12),
1184 PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), 1188 GPIO_FN(DV_D11),
1185 PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), 1189 GPIO_FN(DV_D10),
1186 PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), 1190 GPIO_FN(DV_D9),
1187 PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), 1191 GPIO_FN(DV_D8),
1188 PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), 1192 GPIO_FN(DV_D7),
1189 PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), 1193 GPIO_FN(DV_D6),
1190 PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), 1194 GPIO_FN(DV_D5),
1191 PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), 1195 GPIO_FN(DV_D4),
1192 PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), 1196 GPIO_FN(DV_D3),
1193 PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), 1197 GPIO_FN(DV_D2),
1194 PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), 1198 GPIO_FN(DV_D1),
1195 PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), 1199 GPIO_FN(DV_D0),
1196 1200
1197 /* CPG */ 1201 /* CPG */
1198 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 1202 GPIO_FN(STATUS0),
1199 PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), 1203 GPIO_FN(PDSTATUS),
1200 1204
1201 /* SIOF0 */ 1205 /* SIOF0 */
1202 PINMUX_GPIO(GPIO_FN_SIOF0_MCK, SIOF0_MCK_MARK), 1206 GPIO_FN(SIOF0_MCK),
1203 PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), 1207 GPIO_FN(SIOF0_SCK),
1204 PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), 1208 GPIO_FN(SIOF0_SYNC),
1205 PINMUX_GPIO(GPIO_FN_SIOF0_SS1, SIOF0_SS1_MARK), 1209 GPIO_FN(SIOF0_SS1),
1206 PINMUX_GPIO(GPIO_FN_SIOF0_SS2, SIOF0_SS2_MARK), 1210 GPIO_FN(SIOF0_SS2),
1207 PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), 1211 GPIO_FN(SIOF0_TXD),
1208 PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), 1212 GPIO_FN(SIOF0_RXD),
1209 1213
1210 /* SIOF1 */ 1214 /* SIOF1 */
1211 PINMUX_GPIO(GPIO_FN_SIOF1_MCK, SIOF1_MCK_MARK), 1215 GPIO_FN(SIOF1_MCK),
1212 PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), 1216 GPIO_FN(SIOF1_SCK),
1213 PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), 1217 GPIO_FN(SIOF1_SYNC),
1214 PINMUX_GPIO(GPIO_FN_SIOF1_SS1, SIOF1_SS1_MARK), 1218 GPIO_FN(SIOF1_SS1),
1215 PINMUX_GPIO(GPIO_FN_SIOF1_SS2, SIOF1_SS2_MARK), 1219 GPIO_FN(SIOF1_SS2),
1216 PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), 1220 GPIO_FN(SIOF1_TXD),
1217 PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), 1221 GPIO_FN(SIOF1_RXD),
1218 1222
1219 /* SIM */ 1223 /* SIM */
1220 PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), 1224 GPIO_FN(SIM_D),
1221 PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), 1225 GPIO_FN(SIM_CLK),
1222 PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), 1226 GPIO_FN(SIM_RST),
1223 1227
1224 /* TSIF */ 1228 /* TSIF */
1225 PINMUX_GPIO(GPIO_FN_TS_SDAT, TS_SDAT_MARK), 1229 GPIO_FN(TS_SDAT),
1226 PINMUX_GPIO(GPIO_FN_TS_SCK, TS_SCK_MARK), 1230 GPIO_FN(TS_SCK),
1227 PINMUX_GPIO(GPIO_FN_TS_SDEN, TS_SDEN_MARK), 1231 GPIO_FN(TS_SDEN),
1228 PINMUX_GPIO(GPIO_FN_TS_SPSYNC, TS_SPSYNC_MARK), 1232 GPIO_FN(TS_SPSYNC),
1229 1233
1230 /* IRDA */ 1234 /* IRDA */
1231 PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), 1235 GPIO_FN(IRDA_IN),
1232 PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), 1236 GPIO_FN(IRDA_OUT),
1233 1237
1234 /* TPU */ 1238 /* TPU */
1235 PINMUX_GPIO(GPIO_FN_TPUTO, TPUTO_MARK), 1239 GPIO_FN(TPUTO),
1236 1240
1237 /* FLCTL */ 1241 /* FLCTL */
1238 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 1242 GPIO_FN(FCE),
1239 PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), 1243 GPIO_FN(NAF7),
1240 PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), 1244 GPIO_FN(NAF6),
1241 PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), 1245 GPIO_FN(NAF5),
1242 PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), 1246 GPIO_FN(NAF4),
1243 PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), 1247 GPIO_FN(NAF3),
1244 PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), 1248 GPIO_FN(NAF2),
1245 PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), 1249 GPIO_FN(NAF1),
1246 PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), 1250 GPIO_FN(NAF0),
1247 PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), 1251 GPIO_FN(FCDE),
1248 PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), 1252 GPIO_FN(FOE),
1249 PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), 1253 GPIO_FN(FSC),
1250 PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), 1254 GPIO_FN(FWE),
1251 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 1255 GPIO_FN(FRB),
1252 1256
1253 /* KEYSC */ 1257 /* KEYSC */
1254 PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), 1258 GPIO_FN(KEYIN0),
1255 PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), 1259 GPIO_FN(KEYIN1),
1256 PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), 1260 GPIO_FN(KEYIN2),
1257 PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), 1261 GPIO_FN(KEYIN3),
1258 PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), 1262 GPIO_FN(KEYIN4),
1259 PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), 1263 GPIO_FN(KEYOUT0),
1260 PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), 1264 GPIO_FN(KEYOUT1),
1261 PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), 1265 GPIO_FN(KEYOUT2),
1262 PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), 1266 GPIO_FN(KEYOUT3),
1263 PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), 1267 GPIO_FN(KEYOUT4_IN6),
1264 PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), 1268 GPIO_FN(KEYOUT5_IN5),
1265}; 1269};
1266 1270
1267static struct pinmux_cfg_reg pinmux_config_regs[] = { 1271static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1268 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 1272 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1269 VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN, 1273 VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN,
1270 VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN, 1274 VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN,
@@ -1660,7 +1664,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1660 {} 1664 {}
1661}; 1665};
1662 1666
1663static struct pinmux_data_reg pinmux_data_regs[] = { 1667static const struct pinmux_data_reg pinmux_data_regs[] = {
1664 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { 1668 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
1665 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 1669 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1666 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 1670 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1756,21 +1760,19 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1756 { }, 1760 { },
1757}; 1761};
1758 1762
1759struct sh_pfc_soc_info sh7722_pinmux_info = { 1763const struct sh_pfc_soc_info sh7722_pinmux_info = {
1760 .name = "sh7722_pfc", 1764 .name = "sh7722_pfc",
1761 .reserved_id = PINMUX_RESERVED,
1762 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1763 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 1765 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1764 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, 1766 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1765 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 1767 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1766 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 1768 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1767 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1768 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1769 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1769 1770
1770 .first_gpio = GPIO_PTA7, 1771 .pins = pinmux_pins,
1771 .last_gpio = GPIO_FN_KEYOUT5_IN5, 1772 .nr_pins = ARRAY_SIZE(pinmux_pins),
1773 .func_gpios = pinmux_func_gpios,
1774 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1772 1775
1773 .gpios = pinmux_gpios,
1774 .cfg_regs = pinmux_config_regs, 1776 .cfg_regs = pinmux_config_regs,
1775 .data_regs = pinmux_data_regs, 1777 .data_regs = pinmux_data_regs,
1776 1778
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index 609673d3d70e..07ad1d8d6c8b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -350,7 +350,7 @@ enum {
350 PINMUX_MARK_END, 350 PINMUX_MARK_END,
351}; 351};
352 352
353static pinmux_enum_t pinmux_data[] = { 353static const pinmux_enum_t pinmux_data[] = {
354 /* PTA GPIO */ 354 /* PTA GPIO */
355 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), 355 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
356 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), 356 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
@@ -923,7 +923,7 @@ static pinmux_enum_t pinmux_data[] = {
923 PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN), 923 PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN),
924}; 924};
925 925
926static struct pinmux_gpio pinmux_gpios[] = { 926static struct sh_pfc_pin pinmux_pins[] = {
927 /* PTA */ 927 /* PTA */
928 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), 928 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
929 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), 929 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1139,379 +1139,383 @@ static struct pinmux_gpio pinmux_gpios[] = {
1139 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), 1139 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1140 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), 1140 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1141 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), 1141 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1142};
1143
1144#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1142 1145
1146static const struct pinmux_func pinmux_func_gpios[] = {
1143 /* SCIF0 */ 1147 /* SCIF0 */
1144 PINMUX_GPIO(GPIO_FN_SCIF0_PTT_TXD, SCIF0_PTT_TXD_MARK), 1148 GPIO_FN(SCIF0_PTT_TXD),
1145 PINMUX_GPIO(GPIO_FN_SCIF0_PTT_RXD, SCIF0_PTT_RXD_MARK), 1149 GPIO_FN(SCIF0_PTT_RXD),
1146 PINMUX_GPIO(GPIO_FN_SCIF0_PTT_SCK, SCIF0_PTT_SCK_MARK), 1150 GPIO_FN(SCIF0_PTT_SCK),
1147 PINMUX_GPIO(GPIO_FN_SCIF0_PTU_TXD, SCIF0_PTU_TXD_MARK), 1151 GPIO_FN(SCIF0_PTU_TXD),
1148 PINMUX_GPIO(GPIO_FN_SCIF0_PTU_RXD, SCIF0_PTU_RXD_MARK), 1152 GPIO_FN(SCIF0_PTU_RXD),
1149 PINMUX_GPIO(GPIO_FN_SCIF0_PTU_SCK, SCIF0_PTU_SCK_MARK), 1153 GPIO_FN(SCIF0_PTU_SCK),
1150 1154
1151 /* SCIF1 */ 1155 /* SCIF1 */
1152 PINMUX_GPIO(GPIO_FN_SCIF1_PTS_TXD, SCIF1_PTS_TXD_MARK), 1156 GPIO_FN(SCIF1_PTS_TXD),
1153 PINMUX_GPIO(GPIO_FN_SCIF1_PTS_RXD, SCIF1_PTS_RXD_MARK), 1157 GPIO_FN(SCIF1_PTS_RXD),
1154 PINMUX_GPIO(GPIO_FN_SCIF1_PTS_SCK, SCIF1_PTS_SCK_MARK), 1158 GPIO_FN(SCIF1_PTS_SCK),
1155 PINMUX_GPIO(GPIO_FN_SCIF1_PTV_TXD, SCIF1_PTV_TXD_MARK), 1159 GPIO_FN(SCIF1_PTV_TXD),
1156 PINMUX_GPIO(GPIO_FN_SCIF1_PTV_RXD, SCIF1_PTV_RXD_MARK), 1160 GPIO_FN(SCIF1_PTV_RXD),
1157 PINMUX_GPIO(GPIO_FN_SCIF1_PTV_SCK, SCIF1_PTV_SCK_MARK), 1161 GPIO_FN(SCIF1_PTV_SCK),
1158 1162
1159 /* SCIF2 */ 1163 /* SCIF2 */
1160 PINMUX_GPIO(GPIO_FN_SCIF2_PTT_TXD, SCIF2_PTT_TXD_MARK), 1164 GPIO_FN(SCIF2_PTT_TXD),
1161 PINMUX_GPIO(GPIO_FN_SCIF2_PTT_RXD, SCIF2_PTT_RXD_MARK), 1165 GPIO_FN(SCIF2_PTT_RXD),
1162 PINMUX_GPIO(GPIO_FN_SCIF2_PTT_SCK, SCIF2_PTT_SCK_MARK), 1166 GPIO_FN(SCIF2_PTT_SCK),
1163 PINMUX_GPIO(GPIO_FN_SCIF2_PTU_TXD, SCIF2_PTU_TXD_MARK), 1167 GPIO_FN(SCIF2_PTU_TXD),
1164 PINMUX_GPIO(GPIO_FN_SCIF2_PTU_RXD, SCIF2_PTU_RXD_MARK), 1168 GPIO_FN(SCIF2_PTU_RXD),
1165 PINMUX_GPIO(GPIO_FN_SCIF2_PTU_SCK, SCIF2_PTU_SCK_MARK), 1169 GPIO_FN(SCIF2_PTU_SCK),
1166 1170
1167 /* SCIF3 */ 1171 /* SCIF3 */
1168 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_TXD, SCIF3_PTS_TXD_MARK), 1172 GPIO_FN(SCIF3_PTS_TXD),
1169 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RXD, SCIF3_PTS_RXD_MARK), 1173 GPIO_FN(SCIF3_PTS_RXD),
1170 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_SCK, SCIF3_PTS_SCK_MARK), 1174 GPIO_FN(SCIF3_PTS_SCK),
1171 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RTS, SCIF3_PTS_RTS_MARK), 1175 GPIO_FN(SCIF3_PTS_RTS),
1172 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_CTS, SCIF3_PTS_CTS_MARK), 1176 GPIO_FN(SCIF3_PTS_CTS),
1173 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_TXD, SCIF3_PTV_TXD_MARK), 1177 GPIO_FN(SCIF3_PTV_TXD),
1174 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RXD, SCIF3_PTV_RXD_MARK), 1178 GPIO_FN(SCIF3_PTV_RXD),
1175 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_SCK, SCIF3_PTV_SCK_MARK), 1179 GPIO_FN(SCIF3_PTV_SCK),
1176 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RTS, SCIF3_PTV_RTS_MARK), 1180 GPIO_FN(SCIF3_PTV_RTS),
1177 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_CTS, SCIF3_PTV_CTS_MARK), 1181 GPIO_FN(SCIF3_PTV_CTS),
1178 1182
1179 /* SCIF4 */ 1183 /* SCIF4 */
1180 PINMUX_GPIO(GPIO_FN_SCIF4_PTE_TXD, SCIF4_PTE_TXD_MARK), 1184 GPIO_FN(SCIF4_PTE_TXD),
1181 PINMUX_GPIO(GPIO_FN_SCIF4_PTE_RXD, SCIF4_PTE_RXD_MARK), 1185 GPIO_FN(SCIF4_PTE_RXD),
1182 PINMUX_GPIO(GPIO_FN_SCIF4_PTE_SCK, SCIF4_PTE_SCK_MARK), 1186 GPIO_FN(SCIF4_PTE_SCK),
1183 PINMUX_GPIO(GPIO_FN_SCIF4_PTN_TXD, SCIF4_PTN_TXD_MARK), 1187 GPIO_FN(SCIF4_PTN_TXD),
1184 PINMUX_GPIO(GPIO_FN_SCIF4_PTN_RXD, SCIF4_PTN_RXD_MARK), 1188 GPIO_FN(SCIF4_PTN_RXD),
1185 PINMUX_GPIO(GPIO_FN_SCIF4_PTN_SCK, SCIF4_PTN_SCK_MARK), 1189 GPIO_FN(SCIF4_PTN_SCK),
1186 1190
1187 /* SCIF5 */ 1191 /* SCIF5 */
1188 PINMUX_GPIO(GPIO_FN_SCIF5_PTE_TXD, SCIF5_PTE_TXD_MARK), 1192 GPIO_FN(SCIF5_PTE_TXD),
1189 PINMUX_GPIO(GPIO_FN_SCIF5_PTE_RXD, SCIF5_PTE_RXD_MARK), 1193 GPIO_FN(SCIF5_PTE_RXD),
1190 PINMUX_GPIO(GPIO_FN_SCIF5_PTE_SCK, SCIF5_PTE_SCK_MARK), 1194 GPIO_FN(SCIF5_PTE_SCK),
1191 PINMUX_GPIO(GPIO_FN_SCIF5_PTN_TXD, SCIF5_PTN_TXD_MARK), 1195 GPIO_FN(SCIF5_PTN_TXD),
1192 PINMUX_GPIO(GPIO_FN_SCIF5_PTN_RXD, SCIF5_PTN_RXD_MARK), 1196 GPIO_FN(SCIF5_PTN_RXD),
1193 PINMUX_GPIO(GPIO_FN_SCIF5_PTN_SCK, SCIF5_PTN_SCK_MARK), 1197 GPIO_FN(SCIF5_PTN_SCK),
1194 1198
1195 /* CEU */ 1199 /* CEU */
1196 PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), 1200 GPIO_FN(VIO_D15),
1197 PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), 1201 GPIO_FN(VIO_D14),
1198 PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), 1202 GPIO_FN(VIO_D13),
1199 PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), 1203 GPIO_FN(VIO_D12),
1200 PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), 1204 GPIO_FN(VIO_D11),
1201 PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), 1205 GPIO_FN(VIO_D10),
1202 PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), 1206 GPIO_FN(VIO_D9),
1203 PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), 1207 GPIO_FN(VIO_D8),
1204 PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), 1208 GPIO_FN(VIO_D7),
1205 PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), 1209 GPIO_FN(VIO_D6),
1206 PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), 1210 GPIO_FN(VIO_D5),
1207 PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), 1211 GPIO_FN(VIO_D4),
1208 PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), 1212 GPIO_FN(VIO_D3),
1209 PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), 1213 GPIO_FN(VIO_D2),
1210 PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), 1214 GPIO_FN(VIO_D1),
1211 PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), 1215 GPIO_FN(VIO_D0),
1212 PINMUX_GPIO(GPIO_FN_VIO_CLK1, VIO_CLK1_MARK), 1216 GPIO_FN(VIO_CLK1),
1213 PINMUX_GPIO(GPIO_FN_VIO_VD1, VIO_VD1_MARK), 1217 GPIO_FN(VIO_VD1),
1214 PINMUX_GPIO(GPIO_FN_VIO_HD1, VIO_HD1_MARK), 1218 GPIO_FN(VIO_HD1),
1215 PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), 1219 GPIO_FN(VIO_FLD),
1216 PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), 1220 GPIO_FN(VIO_CKO),
1217 PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), 1221 GPIO_FN(VIO_VD2),
1218 PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), 1222 GPIO_FN(VIO_HD2),
1219 PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), 1223 GPIO_FN(VIO_CLK2),
1220 1224
1221 /* LCDC */ 1225 /* LCDC */
1222 PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), 1226 GPIO_FN(LCDD23),
1223 PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), 1227 GPIO_FN(LCDD22),
1224 PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), 1228 GPIO_FN(LCDD21),
1225 PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), 1229 GPIO_FN(LCDD20),
1226 PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), 1230 GPIO_FN(LCDD19),
1227 PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), 1231 GPIO_FN(LCDD18),
1228 PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), 1232 GPIO_FN(LCDD17),
1229 PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), 1233 GPIO_FN(LCDD16),
1230 PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), 1234 GPIO_FN(LCDD15),
1231 PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), 1235 GPIO_FN(LCDD14),
1232 PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), 1236 GPIO_FN(LCDD13),
1233 PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), 1237 GPIO_FN(LCDD12),
1234 PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), 1238 GPIO_FN(LCDD11),
1235 PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), 1239 GPIO_FN(LCDD10),
1236 PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), 1240 GPIO_FN(LCDD9),
1237 PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), 1241 GPIO_FN(LCDD8),
1238 PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), 1242 GPIO_FN(LCDD7),
1239 PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), 1243 GPIO_FN(LCDD6),
1240 PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), 1244 GPIO_FN(LCDD5),
1241 PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), 1245 GPIO_FN(LCDD4),
1242 PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), 1246 GPIO_FN(LCDD3),
1243 PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), 1247 GPIO_FN(LCDD2),
1244 PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), 1248 GPIO_FN(LCDD1),
1245 PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), 1249 GPIO_FN(LCDD0),
1246 PINMUX_GPIO(GPIO_FN_LCDLCLK_PTR, LCDLCLK_PTR_MARK), 1250 GPIO_FN(LCDLCLK_PTR),
1247 PINMUX_GPIO(GPIO_FN_LCDLCLK_PTW, LCDLCLK_PTW_MARK), 1251 GPIO_FN(LCDLCLK_PTW),
1248 /* Main LCD */ 1252 /* Main LCD */
1249 PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), 1253 GPIO_FN(LCDDON),
1250 PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), 1254 GPIO_FN(LCDVCPWC),
1251 PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), 1255 GPIO_FN(LCDVEPWC),
1252 PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), 1256 GPIO_FN(LCDVSYN),
1253 /* Main LCD - RGB Mode */ 1257 /* Main LCD - RGB Mode */
1254 PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), 1258 GPIO_FN(LCDDCK),
1255 PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), 1259 GPIO_FN(LCDHSYN),
1256 PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), 1260 GPIO_FN(LCDDISP),
1257 /* Main LCD - SYS Mode */ 1261 /* Main LCD - SYS Mode */
1258 PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), 1262 GPIO_FN(LCDRS),
1259 PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), 1263 GPIO_FN(LCDCS),
1260 PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), 1264 GPIO_FN(LCDWR),
1261 PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), 1265 GPIO_FN(LCDRD),
1262 1266
1263 /* IRQ */ 1267 /* IRQ */
1264 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), 1268 GPIO_FN(IRQ0),
1265 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), 1269 GPIO_FN(IRQ1),
1266 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), 1270 GPIO_FN(IRQ2),
1267 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), 1271 GPIO_FN(IRQ3),
1268 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), 1272 GPIO_FN(IRQ4),
1269 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), 1273 GPIO_FN(IRQ5),
1270 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), 1274 GPIO_FN(IRQ6),
1271 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), 1275 GPIO_FN(IRQ7),
1272 1276
1273 /* AUD */ 1277 /* AUD */
1274 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), 1278 GPIO_FN(AUDCK),
1275 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 1279 GPIO_FN(AUDSYNC),
1276 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 1280 GPIO_FN(AUDATA3),
1277 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 1281 GPIO_FN(AUDATA2),
1278 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 1282 GPIO_FN(AUDATA1),
1279 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 1283 GPIO_FN(AUDATA0),
1280 1284
1281 /* SDHI0 (PTD) */ 1285 /* SDHI0 (PTD) */
1282 PINMUX_GPIO(GPIO_FN_SDHI0CD_PTD, SDHI0CD_PTD_MARK), 1286 GPIO_FN(SDHI0CD_PTD),
1283 PINMUX_GPIO(GPIO_FN_SDHI0WP_PTD, SDHI0WP_PTD_MARK), 1287 GPIO_FN(SDHI0WP_PTD),
1284 PINMUX_GPIO(GPIO_FN_SDHI0D3_PTD, SDHI0D3_PTD_MARK), 1288 GPIO_FN(SDHI0D3_PTD),
1285 PINMUX_GPIO(GPIO_FN_SDHI0D2_PTD, SDHI0D2_PTD_MARK), 1289 GPIO_FN(SDHI0D2_PTD),
1286 PINMUX_GPIO(GPIO_FN_SDHI0D1_PTD, SDHI0D1_PTD_MARK), 1290 GPIO_FN(SDHI0D1_PTD),
1287 PINMUX_GPIO(GPIO_FN_SDHI0D0_PTD, SDHI0D0_PTD_MARK), 1291 GPIO_FN(SDHI0D0_PTD),
1288 PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTD, SDHI0CMD_PTD_MARK), 1292 GPIO_FN(SDHI0CMD_PTD),
1289 PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTD, SDHI0CLK_PTD_MARK), 1293 GPIO_FN(SDHI0CLK_PTD),
1290 1294
1291 /* SDHI0 (PTS) */ 1295 /* SDHI0 (PTS) */
1292 PINMUX_GPIO(GPIO_FN_SDHI0CD_PTS, SDHI0CD_PTS_MARK), 1296 GPIO_FN(SDHI0CD_PTS),
1293 PINMUX_GPIO(GPIO_FN_SDHI0WP_PTS, SDHI0WP_PTS_MARK), 1297 GPIO_FN(SDHI0WP_PTS),
1294 PINMUX_GPIO(GPIO_FN_SDHI0D3_PTS, SDHI0D3_PTS_MARK), 1298 GPIO_FN(SDHI0D3_PTS),
1295 PINMUX_GPIO(GPIO_FN_SDHI0D2_PTS, SDHI0D2_PTS_MARK), 1299 GPIO_FN(SDHI0D2_PTS),
1296 PINMUX_GPIO(GPIO_FN_SDHI0D1_PTS, SDHI0D1_PTS_MARK), 1300 GPIO_FN(SDHI0D1_PTS),
1297 PINMUX_GPIO(GPIO_FN_SDHI0D0_PTS, SDHI0D0_PTS_MARK), 1301 GPIO_FN(SDHI0D0_PTS),
1298 PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTS, SDHI0CMD_PTS_MARK), 1302 GPIO_FN(SDHI0CMD_PTS),
1299 PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTS, SDHI0CLK_PTS_MARK), 1303 GPIO_FN(SDHI0CLK_PTS),
1300 1304
1301 /* SDHI1 */ 1305 /* SDHI1 */
1302 PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), 1306 GPIO_FN(SDHI1CD),
1303 PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), 1307 GPIO_FN(SDHI1WP),
1304 PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), 1308 GPIO_FN(SDHI1D3),
1305 PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), 1309 GPIO_FN(SDHI1D2),
1306 PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), 1310 GPIO_FN(SDHI1D1),
1307 PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), 1311 GPIO_FN(SDHI1D0),
1308 PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), 1312 GPIO_FN(SDHI1CMD),
1309 PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), 1313 GPIO_FN(SDHI1CLK),
1310 1314
1311 /* SIUA */ 1315 /* SIUA */
1312 PINMUX_GPIO(GPIO_FN_SIUAFCK, SIUAFCK_MARK), 1316 GPIO_FN(SIUAFCK),
1313 PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), 1317 GPIO_FN(SIUAILR),
1314 PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), 1318 GPIO_FN(SIUAIBT),
1315 PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), 1319 GPIO_FN(SIUAISLD),
1316 PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), 1320 GPIO_FN(SIUAOLR),
1317 PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), 1321 GPIO_FN(SIUAOBT),
1318 PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), 1322 GPIO_FN(SIUAOSLD),
1319 PINMUX_GPIO(GPIO_FN_SIUAMCK, SIUAMCK_MARK), 1323 GPIO_FN(SIUAMCK),
1320 PINMUX_GPIO(GPIO_FN_SIUAISPD, SIUAISPD_MARK), 1324 GPIO_FN(SIUAISPD),
1321 PINMUX_GPIO(GPIO_FN_SIUAOSPD, SIUAOSPD_MARK), 1325 GPIO_FN(SIUAOSPD),
1322 1326
1323 /* SIUB */ 1327 /* SIUB */
1324 PINMUX_GPIO(GPIO_FN_SIUBFCK, SIUBFCK_MARK), 1328 GPIO_FN(SIUBFCK),
1325 PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), 1329 GPIO_FN(SIUBILR),
1326 PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), 1330 GPIO_FN(SIUBIBT),
1327 PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), 1331 GPIO_FN(SIUBISLD),
1328 PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), 1332 GPIO_FN(SIUBOLR),
1329 PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), 1333 GPIO_FN(SIUBOBT),
1330 PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), 1334 GPIO_FN(SIUBOSLD),
1331 PINMUX_GPIO(GPIO_FN_SIUBMCK, SIUBMCK_MARK), 1335 GPIO_FN(SIUBMCK),
1332 1336
1333 /* IRDA */ 1337 /* IRDA */
1334 PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), 1338 GPIO_FN(IRDA_IN),
1335 PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), 1339 GPIO_FN(IRDA_OUT),
1336 1340
1337 /* VOU */ 1341 /* VOU */
1338 PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), 1342 GPIO_FN(DV_CLKI),
1339 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), 1343 GPIO_FN(DV_CLK),
1340 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), 1344 GPIO_FN(DV_HSYNC),
1341 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), 1345 GPIO_FN(DV_VSYNC),
1342 PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), 1346 GPIO_FN(DV_D15),
1343 PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), 1347 GPIO_FN(DV_D14),
1344 PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), 1348 GPIO_FN(DV_D13),
1345 PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), 1349 GPIO_FN(DV_D12),
1346 PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), 1350 GPIO_FN(DV_D11),
1347 PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), 1351 GPIO_FN(DV_D10),
1348 PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), 1352 GPIO_FN(DV_D9),
1349 PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), 1353 GPIO_FN(DV_D8),
1350 PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), 1354 GPIO_FN(DV_D7),
1351 PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), 1355 GPIO_FN(DV_D6),
1352 PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), 1356 GPIO_FN(DV_D5),
1353 PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), 1357 GPIO_FN(DV_D4),
1354 PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), 1358 GPIO_FN(DV_D3),
1355 PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), 1359 GPIO_FN(DV_D2),
1356 PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), 1360 GPIO_FN(DV_D1),
1357 PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), 1361 GPIO_FN(DV_D0),
1358 1362
1359 /* KEYSC */ 1363 /* KEYSC */
1360 PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), 1364 GPIO_FN(KEYIN0),
1361 PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), 1365 GPIO_FN(KEYIN1),
1362 PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), 1366 GPIO_FN(KEYIN2),
1363 PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), 1367 GPIO_FN(KEYIN3),
1364 PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), 1368 GPIO_FN(KEYIN4),
1365 PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), 1369 GPIO_FN(KEYOUT0),
1366 PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), 1370 GPIO_FN(KEYOUT1),
1367 PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), 1371 GPIO_FN(KEYOUT2),
1368 PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), 1372 GPIO_FN(KEYOUT3),
1369 PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), 1373 GPIO_FN(KEYOUT4_IN6),
1370 PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), 1374 GPIO_FN(KEYOUT5_IN5),
1371 1375
1372 /* MSIOF0 (PTF) */ 1376 /* MSIOF0 (PTF) */
1373 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TXD, MSIOF0_PTF_TXD_MARK), 1377 GPIO_FN(MSIOF0_PTF_TXD),
1374 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RXD, MSIOF0_PTF_RXD_MARK), 1378 GPIO_FN(MSIOF0_PTF_RXD),
1375 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_MCK, MSIOF0_PTF_MCK_MARK), 1379 GPIO_FN(MSIOF0_PTF_MCK),
1376 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSYNC, MSIOF0_PTF_TSYNC_MARK), 1380 GPIO_FN(MSIOF0_PTF_TSYNC),
1377 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSCK, MSIOF0_PTF_TSCK_MARK), 1381 GPIO_FN(MSIOF0_PTF_TSCK),
1378 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSYNC, MSIOF0_PTF_RSYNC_MARK), 1382 GPIO_FN(MSIOF0_PTF_RSYNC),
1379 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSCK, MSIOF0_PTF_RSCK_MARK), 1383 GPIO_FN(MSIOF0_PTF_RSCK),
1380 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS1, MSIOF0_PTF_SS1_MARK), 1384 GPIO_FN(MSIOF0_PTF_SS1),
1381 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS2, MSIOF0_PTF_SS2_MARK), 1385 GPIO_FN(MSIOF0_PTF_SS2),
1382 1386
1383 /* MSIOF0 (PTT+PTX) */ 1387 /* MSIOF0 (PTT+PTX) */
1384 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TXD, MSIOF0_PTT_TXD_MARK), 1388 GPIO_FN(MSIOF0_PTT_TXD),
1385 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RXD, MSIOF0_PTT_RXD_MARK), 1389 GPIO_FN(MSIOF0_PTT_RXD),
1386 PINMUX_GPIO(GPIO_FN_MSIOF0_PTX_MCK, MSIOF0_PTX_MCK_MARK), 1390 GPIO_FN(MSIOF0_PTX_MCK),
1387 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSYNC, MSIOF0_PTT_TSYNC_MARK), 1391 GPIO_FN(MSIOF0_PTT_TSYNC),
1388 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSCK, MSIOF0_PTT_TSCK_MARK), 1392 GPIO_FN(MSIOF0_PTT_TSCK),
1389 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSYNC, MSIOF0_PTT_RSYNC_MARK), 1393 GPIO_FN(MSIOF0_PTT_RSYNC),
1390 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSCK, MSIOF0_PTT_RSCK_MARK), 1394 GPIO_FN(MSIOF0_PTT_RSCK),
1391 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS1, MSIOF0_PTT_SS1_MARK), 1395 GPIO_FN(MSIOF0_PTT_SS1),
1392 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS2, MSIOF0_PTT_SS2_MARK), 1396 GPIO_FN(MSIOF0_PTT_SS2),
1393 1397
1394 /* MSIOF1 */ 1398 /* MSIOF1 */
1395 PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), 1399 GPIO_FN(MSIOF1_TXD),
1396 PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), 1400 GPIO_FN(MSIOF1_RXD),
1397 PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), 1401 GPIO_FN(MSIOF1_MCK),
1398 PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), 1402 GPIO_FN(MSIOF1_TSYNC),
1399 PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), 1403 GPIO_FN(MSIOF1_TSCK),
1400 PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), 1404 GPIO_FN(MSIOF1_RSYNC),
1401 PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), 1405 GPIO_FN(MSIOF1_RSCK),
1402 PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), 1406 GPIO_FN(MSIOF1_SS1),
1403 PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), 1407 GPIO_FN(MSIOF1_SS2),
1404 1408
1405 /* TSIF */ 1409 /* TSIF */
1406 PINMUX_GPIO(GPIO_FN_TS0_SDAT, TS0_SDAT_MARK), 1410 GPIO_FN(TS0_SDAT),
1407 PINMUX_GPIO(GPIO_FN_TS0_SCK, TS0_SCK_MARK), 1411 GPIO_FN(TS0_SCK),
1408 PINMUX_GPIO(GPIO_FN_TS0_SDEN, TS0_SDEN_MARK), 1412 GPIO_FN(TS0_SDEN),
1409 PINMUX_GPIO(GPIO_FN_TS0_SPSYNC, TS0_SPSYNC_MARK), 1413 GPIO_FN(TS0_SPSYNC),
1410 1414
1411 /* FLCTL */ 1415 /* FLCTL */
1412 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 1416 GPIO_FN(FCE),
1413 PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), 1417 GPIO_FN(NAF7),
1414 PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), 1418 GPIO_FN(NAF6),
1415 PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), 1419 GPIO_FN(NAF5),
1416 PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), 1420 GPIO_FN(NAF4),
1417 PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), 1421 GPIO_FN(NAF3),
1418 PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), 1422 GPIO_FN(NAF2),
1419 PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), 1423 GPIO_FN(NAF1),
1420 PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), 1424 GPIO_FN(NAF0),
1421 PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), 1425 GPIO_FN(FCDE),
1422 PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), 1426 GPIO_FN(FOE),
1423 PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), 1427 GPIO_FN(FSC),
1424 PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), 1428 GPIO_FN(FWE),
1425 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 1429 GPIO_FN(FRB),
1426 1430
1427 /* DMAC */ 1431 /* DMAC */
1428 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 1432 GPIO_FN(DACK1),
1429 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 1433 GPIO_FN(DREQ1),
1430 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 1434 GPIO_FN(DACK0),
1431 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 1435 GPIO_FN(DREQ0),
1432 1436
1433 /* ADC */ 1437 /* ADC */
1434 PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), 1438 GPIO_FN(AN3),
1435 PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), 1439 GPIO_FN(AN2),
1436 PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), 1440 GPIO_FN(AN1),
1437 PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), 1441 GPIO_FN(AN0),
1438 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), 1442 GPIO_FN(ADTRG),
1439 1443
1440 /* CPG */ 1444 /* CPG */
1441 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 1445 GPIO_FN(STATUS0),
1442 PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), 1446 GPIO_FN(PDSTATUS),
1443 1447
1444 /* TPU */ 1448 /* TPU */
1445 PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), 1449 GPIO_FN(TPUTO0),
1446 PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), 1450 GPIO_FN(TPUTO1),
1447 PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), 1451 GPIO_FN(TPUTO2),
1448 PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), 1452 GPIO_FN(TPUTO3),
1449 1453
1450 /* BSC */ 1454 /* BSC */
1451 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 1455 GPIO_FN(D31),
1452 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 1456 GPIO_FN(D30),
1453 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 1457 GPIO_FN(D29),
1454 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 1458 GPIO_FN(D28),
1455 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 1459 GPIO_FN(D27),
1456 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 1460 GPIO_FN(D26),
1457 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 1461 GPIO_FN(D25),
1458 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 1462 GPIO_FN(D24),
1459 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 1463 GPIO_FN(D23),
1460 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 1464 GPIO_FN(D22),
1461 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 1465 GPIO_FN(D21),
1462 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 1466 GPIO_FN(D20),
1463 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 1467 GPIO_FN(D19),
1464 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 1468 GPIO_FN(D18),
1465 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 1469 GPIO_FN(D17),
1466 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 1470 GPIO_FN(D16),
1467 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 1471 GPIO_FN(IOIS16),
1468 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 1472 GPIO_FN(WAIT),
1469 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1473 GPIO_FN(BS),
1470 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1474 GPIO_FN(A25),
1471 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1475 GPIO_FN(A24),
1472 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1476 GPIO_FN(A23),
1473 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1477 GPIO_FN(A22),
1474 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), 1478 GPIO_FN(CS6B_CE1B),
1475 PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), 1479 GPIO_FN(CS6A_CE2B),
1476 PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), 1480 GPIO_FN(CS5B_CE1A),
1477 PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), 1481 GPIO_FN(CS5A_CE2A),
1478 PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), 1482 GPIO_FN(WE3_ICIOWR),
1479 PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), 1483 GPIO_FN(WE2_ICIORD),
1480 1484
1481 /* ATAPI */ 1485 /* ATAPI */
1482 PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), 1486 GPIO_FN(IDED15),
1483 PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), 1487 GPIO_FN(IDED14),
1484 PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), 1488 GPIO_FN(IDED13),
1485 PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), 1489 GPIO_FN(IDED12),
1486 PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), 1490 GPIO_FN(IDED11),
1487 PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), 1491 GPIO_FN(IDED10),
1488 PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), 1492 GPIO_FN(IDED9),
1489 PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), 1493 GPIO_FN(IDED8),
1490 PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), 1494 GPIO_FN(IDED7),
1491 PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), 1495 GPIO_FN(IDED6),
1492 PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), 1496 GPIO_FN(IDED5),
1493 PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), 1497 GPIO_FN(IDED4),
1494 PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), 1498 GPIO_FN(IDED3),
1495 PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), 1499 GPIO_FN(IDED2),
1496 PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), 1500 GPIO_FN(IDED1),
1497 PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), 1501 GPIO_FN(IDED0),
1498 PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), 1502 GPIO_FN(DIRECTION),
1499 PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), 1503 GPIO_FN(EXBUF_ENB),
1500 PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), 1504 GPIO_FN(IDERST),
1501 PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), 1505 GPIO_FN(IODACK),
1502 PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), 1506 GPIO_FN(IODREQ),
1503 PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), 1507 GPIO_FN(IDEIORDY),
1504 PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), 1508 GPIO_FN(IDEINT),
1505 PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), 1509 GPIO_FN(IDEIOWR),
1506 PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), 1510 GPIO_FN(IDEIORD),
1507 PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), 1511 GPIO_FN(IDECS1),
1508 PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), 1512 GPIO_FN(IDECS0),
1509 PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), 1513 GPIO_FN(IDEA2),
1510 PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), 1514 GPIO_FN(IDEA1),
1511 PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), 1515 GPIO_FN(IDEA0),
1512}; 1516};
1513 1517
1514static struct pinmux_cfg_reg pinmux_config_regs[] = { 1518static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1515 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 1519 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1516 PTA7_FN, PTA7_OUT, 0, PTA7_IN, 1520 PTA7_FN, PTA7_OUT, 0, PTA7_IN,
1517 PTA6_FN, PTA6_OUT, 0, PTA6_IN, 1521 PTA6_FN, PTA6_OUT, 0, PTA6_IN,
@@ -1785,7 +1789,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1785 {} 1789 {}
1786}; 1790};
1787 1791
1788static struct pinmux_data_reg pinmux_data_regs[] = { 1792static const struct pinmux_data_reg pinmux_data_regs[] = {
1789 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { 1793 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
1790 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 1794 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1791 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 1795 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1881,20 +1885,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1881 { }, 1885 { },
1882}; 1886};
1883 1887
1884struct sh_pfc_soc_info sh7723_pinmux_info = { 1888const struct sh_pfc_soc_info sh7723_pinmux_info = {
1885 .name = "sh7723_pfc", 1889 .name = "sh7723_pfc",
1886 .reserved_id = PINMUX_RESERVED,
1887 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1888 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 1890 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1889 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 1891 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1890 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 1892 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1891 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1892 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1893 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1893 1894
1894 .first_gpio = GPIO_PTA7, 1895 .pins = pinmux_pins,
1895 .last_gpio = GPIO_FN_IDEA0, 1896 .nr_pins = ARRAY_SIZE(pinmux_pins),
1897 .func_gpios = pinmux_func_gpios,
1898 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1896 1899
1897 .gpios = pinmux_gpios,
1898 .cfg_regs = pinmux_config_regs, 1900 .cfg_regs = pinmux_config_regs,
1899 .data_regs = pinmux_data_regs, 1901 .data_regs = pinmux_data_regs,
1900 1902
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 233fbf750b39..35e551609805 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -572,7 +572,7 @@ enum {
572 PINMUX_MARK_END, 572 PINMUX_MARK_END,
573}; 573};
574 574
575static pinmux_enum_t pinmux_data[] = { 575static const pinmux_enum_t pinmux_data[] = {
576 /* PTA GPIO */ 576 /* PTA GPIO */
577 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), 577 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
578 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), 578 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
@@ -1192,7 +1192,7 @@ static pinmux_enum_t pinmux_data[] = {
1192 PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN), 1192 PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN),
1193}; 1193};
1194 1194
1195static struct pinmux_gpio pinmux_gpios[] = { 1195static struct sh_pfc_pin pinmux_pins[] = {
1196 /* PTA */ 1196 /* PTA */
1197 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), 1197 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
1198 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), 1198 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1418,372 +1418,376 @@ static struct pinmux_gpio pinmux_gpios[] = {
1418 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), 1418 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1419 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), 1419 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1420 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), 1420 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1421};
1422
1423#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1421 1424
1425static const struct pinmux_func pinmux_func_gpios[] = {
1422 /* BSC */ 1426 /* BSC */
1423 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 1427 GPIO_FN(D31),
1424 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 1428 GPIO_FN(D30),
1425 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 1429 GPIO_FN(D29),
1426 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 1430 GPIO_FN(D28),
1427 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 1431 GPIO_FN(D27),
1428 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 1432 GPIO_FN(D26),
1429 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 1433 GPIO_FN(D25),
1430 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 1434 GPIO_FN(D24),
1431 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 1435 GPIO_FN(D23),
1432 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 1436 GPIO_FN(D22),
1433 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 1437 GPIO_FN(D21),
1434 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 1438 GPIO_FN(D20),
1435 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 1439 GPIO_FN(D19),
1436 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 1440 GPIO_FN(D18),
1437 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 1441 GPIO_FN(D17),
1438 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 1442 GPIO_FN(D16),
1439 PINMUX_GPIO(GPIO_FN_D15, D15_MARK), 1443 GPIO_FN(D15),
1440 PINMUX_GPIO(GPIO_FN_D14, D14_MARK), 1444 GPIO_FN(D14),
1441 PINMUX_GPIO(GPIO_FN_D13, D13_MARK), 1445 GPIO_FN(D13),
1442 PINMUX_GPIO(GPIO_FN_D12, D12_MARK), 1446 GPIO_FN(D12),
1443 PINMUX_GPIO(GPIO_FN_D11, D11_MARK), 1447 GPIO_FN(D11),
1444 PINMUX_GPIO(GPIO_FN_D10, D10_MARK), 1448 GPIO_FN(D10),
1445 PINMUX_GPIO(GPIO_FN_D9, D9_MARK), 1449 GPIO_FN(D9),
1446 PINMUX_GPIO(GPIO_FN_D8, D8_MARK), 1450 GPIO_FN(D8),
1447 PINMUX_GPIO(GPIO_FN_D7, D7_MARK), 1451 GPIO_FN(D7),
1448 PINMUX_GPIO(GPIO_FN_D6, D6_MARK), 1452 GPIO_FN(D6),
1449 PINMUX_GPIO(GPIO_FN_D5, D5_MARK), 1453 GPIO_FN(D5),
1450 PINMUX_GPIO(GPIO_FN_D4, D4_MARK), 1454 GPIO_FN(D4),
1451 PINMUX_GPIO(GPIO_FN_D3, D3_MARK), 1455 GPIO_FN(D3),
1452 PINMUX_GPIO(GPIO_FN_D2, D2_MARK), 1456 GPIO_FN(D2),
1453 PINMUX_GPIO(GPIO_FN_D1, D1_MARK), 1457 GPIO_FN(D1),
1454 PINMUX_GPIO(GPIO_FN_D0, D0_MARK), 1458 GPIO_FN(D0),
1455 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1459 GPIO_FN(A25),
1456 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1460 GPIO_FN(A24),
1457 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1461 GPIO_FN(A23),
1458 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1462 GPIO_FN(A22),
1459 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), 1463 GPIO_FN(CS6B_CE1B),
1460 PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), 1464 GPIO_FN(CS6A_CE2B),
1461 PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), 1465 GPIO_FN(CS5B_CE1A),
1462 PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), 1466 GPIO_FN(CS5A_CE2A),
1463 PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), 1467 GPIO_FN(WE3_ICIOWR),
1464 PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), 1468 GPIO_FN(WE2_ICIORD),
1465 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 1469 GPIO_FN(IOIS16),
1466 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 1470 GPIO_FN(WAIT),
1467 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1471 GPIO_FN(BS),
1468 1472
1469 /* KEYSC */ 1473 /* KEYSC */
1470 PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), 1474 GPIO_FN(KEYOUT5_IN5),
1471 PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), 1475 GPIO_FN(KEYOUT4_IN6),
1472 PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), 1476 GPIO_FN(KEYIN4),
1473 PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), 1477 GPIO_FN(KEYIN3),
1474 PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), 1478 GPIO_FN(KEYIN2),
1475 PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), 1479 GPIO_FN(KEYIN1),
1476 PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), 1480 GPIO_FN(KEYIN0),
1477 PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), 1481 GPIO_FN(KEYOUT3),
1478 PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), 1482 GPIO_FN(KEYOUT2),
1479 PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), 1483 GPIO_FN(KEYOUT1),
1480 PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), 1484 GPIO_FN(KEYOUT0),
1481 1485
1482 /* ATAPI */ 1486 /* ATAPI */
1483 PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), 1487 GPIO_FN(IDED15),
1484 PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), 1488 GPIO_FN(IDED14),
1485 PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), 1489 GPIO_FN(IDED13),
1486 PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), 1490 GPIO_FN(IDED12),
1487 PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), 1491 GPIO_FN(IDED11),
1488 PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), 1492 GPIO_FN(IDED10),
1489 PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), 1493 GPIO_FN(IDED9),
1490 PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), 1494 GPIO_FN(IDED8),
1491 PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), 1495 GPIO_FN(IDED7),
1492 PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), 1496 GPIO_FN(IDED6),
1493 PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), 1497 GPIO_FN(IDED5),
1494 PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), 1498 GPIO_FN(IDED4),
1495 PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), 1499 GPIO_FN(IDED3),
1496 PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), 1500 GPIO_FN(IDED2),
1497 PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), 1501 GPIO_FN(IDED1),
1498 PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), 1502 GPIO_FN(IDED0),
1499 PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), 1503 GPIO_FN(IDEA2),
1500 PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), 1504 GPIO_FN(IDEA1),
1501 PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), 1505 GPIO_FN(IDEA0),
1502 PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), 1506 GPIO_FN(IDEIOWR),
1503 PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), 1507 GPIO_FN(IODREQ),
1504 PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), 1508 GPIO_FN(IDECS0),
1505 PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), 1509 GPIO_FN(IDECS1),
1506 PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), 1510 GPIO_FN(IDEIORD),
1507 PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), 1511 GPIO_FN(DIRECTION),
1508 PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), 1512 GPIO_FN(EXBUF_ENB),
1509 PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), 1513 GPIO_FN(IDERST),
1510 PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), 1514 GPIO_FN(IODACK),
1511 PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), 1515 GPIO_FN(IDEINT),
1512 PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), 1516 GPIO_FN(IDEIORDY),
1513 1517
1514 /* TPU */ 1518 /* TPU */
1515 PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), 1519 GPIO_FN(TPUTO3),
1516 PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), 1520 GPIO_FN(TPUTO2),
1517 PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), 1521 GPIO_FN(TPUTO1),
1518 PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), 1522 GPIO_FN(TPUTO0),
1519 PINMUX_GPIO(GPIO_FN_TPUTI3, TPUTI3_MARK), 1523 GPIO_FN(TPUTI3),
1520 PINMUX_GPIO(GPIO_FN_TPUTI2, TPUTI2_MARK), 1524 GPIO_FN(TPUTI2),
1521 1525
1522 /* LCDC */ 1526 /* LCDC */
1523 PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), 1527 GPIO_FN(LCDD23),
1524 PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), 1528 GPIO_FN(LCDD22),
1525 PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), 1529 GPIO_FN(LCDD21),
1526 PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), 1530 GPIO_FN(LCDD20),
1527 PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), 1531 GPIO_FN(LCDD19),
1528 PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), 1532 GPIO_FN(LCDD18),
1529 PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), 1533 GPIO_FN(LCDD17),
1530 PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), 1534 GPIO_FN(LCDD16),
1531 PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), 1535 GPIO_FN(LCDD15),
1532 PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), 1536 GPIO_FN(LCDD14),
1533 PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), 1537 GPIO_FN(LCDD13),
1534 PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), 1538 GPIO_FN(LCDD12),
1535 PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), 1539 GPIO_FN(LCDD11),
1536 PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), 1540 GPIO_FN(LCDD10),
1537 PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), 1541 GPIO_FN(LCDD9),
1538 PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), 1542 GPIO_FN(LCDD8),
1539 PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), 1543 GPIO_FN(LCDD7),
1540 PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), 1544 GPIO_FN(LCDD6),
1541 PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), 1545 GPIO_FN(LCDD5),
1542 PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), 1546 GPIO_FN(LCDD4),
1543 PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), 1547 GPIO_FN(LCDD3),
1544 PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), 1548 GPIO_FN(LCDD2),
1545 PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), 1549 GPIO_FN(LCDD1),
1546 PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), 1550 GPIO_FN(LCDD0),
1547 PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), 1551 GPIO_FN(LCDVSYN),
1548 PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), 1552 GPIO_FN(LCDDISP),
1549 PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), 1553 GPIO_FN(LCDRS),
1550 PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), 1554 GPIO_FN(LCDHSYN),
1551 PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), 1555 GPIO_FN(LCDCS),
1552 PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), 1556 GPIO_FN(LCDDON),
1553 PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), 1557 GPIO_FN(LCDDCK),
1554 PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), 1558 GPIO_FN(LCDWR),
1555 PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), 1559 GPIO_FN(LCDVEPWC),
1556 PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), 1560 GPIO_FN(LCDVCPWC),
1557 PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), 1561 GPIO_FN(LCDRD),
1558 PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), 1562 GPIO_FN(LCDLCLK),
1559 1563
1560 /* SCIF0 */ 1564 /* SCIF0 */
1561 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), 1565 GPIO_FN(SCIF0_TXD),
1562 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), 1566 GPIO_FN(SCIF0_RXD),
1563 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), 1567 GPIO_FN(SCIF0_SCK),
1564 1568
1565 /* SCIF1 */ 1569 /* SCIF1 */
1566 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), 1570 GPIO_FN(SCIF1_SCK),
1567 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), 1571 GPIO_FN(SCIF1_RXD),
1568 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), 1572 GPIO_FN(SCIF1_TXD),
1569 1573
1570 /* SCIF2 */ 1574 /* SCIF2 */
1571 PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD, SCIF2_L_TXD_MARK), 1575 GPIO_FN(SCIF2_L_TXD),
1572 PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK, SCIF2_L_SCK_MARK), 1576 GPIO_FN(SCIF2_L_SCK),
1573 PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD, SCIF2_L_RXD_MARK), 1577 GPIO_FN(SCIF2_L_RXD),
1574 PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD, SCIF2_V_TXD_MARK), 1578 GPIO_FN(SCIF2_V_TXD),
1575 PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK, SCIF2_V_SCK_MARK), 1579 GPIO_FN(SCIF2_V_SCK),
1576 PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD, SCIF2_V_RXD_MARK), 1580 GPIO_FN(SCIF2_V_RXD),
1577 1581
1578 /* SCIF3 */ 1582 /* SCIF3 */
1579 PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK, SCIF3_V_SCK_MARK), 1583 GPIO_FN(SCIF3_V_SCK),
1580 PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD, SCIF3_V_RXD_MARK), 1584 GPIO_FN(SCIF3_V_RXD),
1581 PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD, SCIF3_V_TXD_MARK), 1585 GPIO_FN(SCIF3_V_TXD),
1582 PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS, SCIF3_V_CTS_MARK), 1586 GPIO_FN(SCIF3_V_CTS),
1583 PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS, SCIF3_V_RTS_MARK), 1587 GPIO_FN(SCIF3_V_RTS),
1584 PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK, SCIF3_I_SCK_MARK), 1588 GPIO_FN(SCIF3_I_SCK),
1585 PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD, SCIF3_I_RXD_MARK), 1589 GPIO_FN(SCIF3_I_RXD),
1586 PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD, SCIF3_I_TXD_MARK), 1590 GPIO_FN(SCIF3_I_TXD),
1587 PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS, SCIF3_I_CTS_MARK), 1591 GPIO_FN(SCIF3_I_CTS),
1588 PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS, SCIF3_I_RTS_MARK), 1592 GPIO_FN(SCIF3_I_RTS),
1589 1593
1590 /* SCIF4 */ 1594 /* SCIF4 */
1591 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), 1595 GPIO_FN(SCIF4_SCK),
1592 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), 1596 GPIO_FN(SCIF4_RXD),
1593 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), 1597 GPIO_FN(SCIF4_TXD),
1594 1598
1595 /* SCIF5 */ 1599 /* SCIF5 */
1596 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), 1600 GPIO_FN(SCIF5_SCK),
1597 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), 1601 GPIO_FN(SCIF5_RXD),
1598 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), 1602 GPIO_FN(SCIF5_TXD),
1599 1603
1600 /* FSI */ 1604 /* FSI */
1601 PINMUX_GPIO(GPIO_FN_FSIMCKB, FSIMCKB_MARK), 1605 GPIO_FN(FSIMCKB),
1602 PINMUX_GPIO(GPIO_FN_FSIMCKA, FSIMCKA_MARK), 1606 GPIO_FN(FSIMCKA),
1603 PINMUX_GPIO(GPIO_FN_FSIOASD, FSIOASD_MARK), 1607 GPIO_FN(FSIOASD),
1604 PINMUX_GPIO(GPIO_FN_FSIIABCK, FSIIABCK_MARK), 1608 GPIO_FN(FSIIABCK),
1605 PINMUX_GPIO(GPIO_FN_FSIIALRCK, FSIIALRCK_MARK), 1609 GPIO_FN(FSIIALRCK),
1606 PINMUX_GPIO(GPIO_FN_FSIOABCK, FSIOABCK_MARK), 1610 GPIO_FN(FSIOABCK),
1607 PINMUX_GPIO(GPIO_FN_FSIOALRCK, FSIOALRCK_MARK), 1611 GPIO_FN(FSIOALRCK),
1608 PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK), 1612 GPIO_FN(CLKAUDIOAO),
1609 PINMUX_GPIO(GPIO_FN_FSIIBSD, FSIIBSD_MARK), 1613 GPIO_FN(FSIIBSD),
1610 PINMUX_GPIO(GPIO_FN_FSIOBSD, FSIOBSD_MARK), 1614 GPIO_FN(FSIOBSD),
1611 PINMUX_GPIO(GPIO_FN_FSIIBBCK, FSIIBBCK_MARK), 1615 GPIO_FN(FSIIBBCK),
1612 PINMUX_GPIO(GPIO_FN_FSIIBLRCK, FSIIBLRCK_MARK), 1616 GPIO_FN(FSIIBLRCK),
1613 PINMUX_GPIO(GPIO_FN_FSIOBBCK, FSIOBBCK_MARK), 1617 GPIO_FN(FSIOBBCK),
1614 PINMUX_GPIO(GPIO_FN_FSIOBLRCK, FSIOBLRCK_MARK), 1618 GPIO_FN(FSIOBLRCK),
1615 PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK), 1619 GPIO_FN(CLKAUDIOBO),
1616 PINMUX_GPIO(GPIO_FN_FSIIASD, FSIIASD_MARK), 1620 GPIO_FN(FSIIASD),
1617 1621
1618 /* AUD */ 1622 /* AUD */
1619 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), 1623 GPIO_FN(AUDCK),
1620 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 1624 GPIO_FN(AUDSYNC),
1621 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 1625 GPIO_FN(AUDATA3),
1622 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 1626 GPIO_FN(AUDATA2),
1623 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 1627 GPIO_FN(AUDATA1),
1624 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 1628 GPIO_FN(AUDATA0),
1625 1629
1626 /* VIO */ 1630 /* VIO */
1627 PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), 1631 GPIO_FN(VIO_CKO),
1628 1632
1629 /* VIO0 */ 1633 /* VIO0 */
1630 PINMUX_GPIO(GPIO_FN_VIO0_D15, VIO0_D15_MARK), 1634 GPIO_FN(VIO0_D15),
1631 PINMUX_GPIO(GPIO_FN_VIO0_D14, VIO0_D14_MARK), 1635 GPIO_FN(VIO0_D14),
1632 PINMUX_GPIO(GPIO_FN_VIO0_D13, VIO0_D13_MARK), 1636 GPIO_FN(VIO0_D13),
1633 PINMUX_GPIO(GPIO_FN_VIO0_D12, VIO0_D12_MARK), 1637 GPIO_FN(VIO0_D12),
1634 PINMUX_GPIO(GPIO_FN_VIO0_D11, VIO0_D11_MARK), 1638 GPIO_FN(VIO0_D11),
1635 PINMUX_GPIO(GPIO_FN_VIO0_D10, VIO0_D10_MARK), 1639 GPIO_FN(VIO0_D10),
1636 PINMUX_GPIO(GPIO_FN_VIO0_D9, VIO0_D9_MARK), 1640 GPIO_FN(VIO0_D9),
1637 PINMUX_GPIO(GPIO_FN_VIO0_D8, VIO0_D8_MARK), 1641 GPIO_FN(VIO0_D8),
1638 PINMUX_GPIO(GPIO_FN_VIO0_D7, VIO0_D7_MARK), 1642 GPIO_FN(VIO0_D7),
1639 PINMUX_GPIO(GPIO_FN_VIO0_D6, VIO0_D6_MARK), 1643 GPIO_FN(VIO0_D6),
1640 PINMUX_GPIO(GPIO_FN_VIO0_D5, VIO0_D5_MARK), 1644 GPIO_FN(VIO0_D5),
1641 PINMUX_GPIO(GPIO_FN_VIO0_D4, VIO0_D4_MARK), 1645 GPIO_FN(VIO0_D4),
1642 PINMUX_GPIO(GPIO_FN_VIO0_D3, VIO0_D3_MARK), 1646 GPIO_FN(VIO0_D3),
1643 PINMUX_GPIO(GPIO_FN_VIO0_D2, VIO0_D2_MARK), 1647 GPIO_FN(VIO0_D2),
1644 PINMUX_GPIO(GPIO_FN_VIO0_D1, VIO0_D1_MARK), 1648 GPIO_FN(VIO0_D1),
1645 PINMUX_GPIO(GPIO_FN_VIO0_D0, VIO0_D0_MARK), 1649 GPIO_FN(VIO0_D0),
1646 PINMUX_GPIO(GPIO_FN_VIO0_VD, VIO0_VD_MARK), 1650 GPIO_FN(VIO0_VD),
1647 PINMUX_GPIO(GPIO_FN_VIO0_CLK, VIO0_CLK_MARK), 1651 GPIO_FN(VIO0_CLK),
1648 PINMUX_GPIO(GPIO_FN_VIO0_FLD, VIO0_FLD_MARK), 1652 GPIO_FN(VIO0_FLD),
1649 PINMUX_GPIO(GPIO_FN_VIO0_HD, VIO0_HD_MARK), 1653 GPIO_FN(VIO0_HD),
1650 1654
1651 /* VIO1 */ 1655 /* VIO1 */
1652 PINMUX_GPIO(GPIO_FN_VIO1_D7, VIO1_D7_MARK), 1656 GPIO_FN(VIO1_D7),
1653 PINMUX_GPIO(GPIO_FN_VIO1_D6, VIO1_D6_MARK), 1657 GPIO_FN(VIO1_D6),
1654 PINMUX_GPIO(GPIO_FN_VIO1_D5, VIO1_D5_MARK), 1658 GPIO_FN(VIO1_D5),
1655 PINMUX_GPIO(GPIO_FN_VIO1_D4, VIO1_D4_MARK), 1659 GPIO_FN(VIO1_D4),
1656 PINMUX_GPIO(GPIO_FN_VIO1_D3, VIO1_D3_MARK), 1660 GPIO_FN(VIO1_D3),
1657 PINMUX_GPIO(GPIO_FN_VIO1_D2, VIO1_D2_MARK), 1661 GPIO_FN(VIO1_D2),
1658 PINMUX_GPIO(GPIO_FN_VIO1_D1, VIO1_D1_MARK), 1662 GPIO_FN(VIO1_D1),
1659 PINMUX_GPIO(GPIO_FN_VIO1_D0, VIO1_D0_MARK), 1663 GPIO_FN(VIO1_D0),
1660 PINMUX_GPIO(GPIO_FN_VIO1_FLD, VIO1_FLD_MARK), 1664 GPIO_FN(VIO1_FLD),
1661 PINMUX_GPIO(GPIO_FN_VIO1_HD, VIO1_HD_MARK), 1665 GPIO_FN(VIO1_HD),
1662 PINMUX_GPIO(GPIO_FN_VIO1_VD, VIO1_VD_MARK), 1666 GPIO_FN(VIO1_VD),
1663 PINMUX_GPIO(GPIO_FN_VIO1_CLK, VIO1_CLK_MARK), 1667 GPIO_FN(VIO1_CLK),
1664 1668
1665 /* Eth */ 1669 /* Eth */
1666 PINMUX_GPIO(GPIO_FN_RMII_RXD0, RMII_RXD0_MARK), 1670 GPIO_FN(RMII_RXD0),
1667 PINMUX_GPIO(GPIO_FN_RMII_RXD1, RMII_RXD1_MARK), 1671 GPIO_FN(RMII_RXD1),
1668 PINMUX_GPIO(GPIO_FN_RMII_TXD0, RMII_TXD0_MARK), 1672 GPIO_FN(RMII_TXD0),
1669 PINMUX_GPIO(GPIO_FN_RMII_TXD1, RMII_TXD1_MARK), 1673 GPIO_FN(RMII_TXD1),
1670 PINMUX_GPIO(GPIO_FN_RMII_REF_CLK, RMII_REF_CLK_MARK), 1674 GPIO_FN(RMII_REF_CLK),
1671 PINMUX_GPIO(GPIO_FN_RMII_TX_EN, RMII_TX_EN_MARK), 1675 GPIO_FN(RMII_TX_EN),
1672 PINMUX_GPIO(GPIO_FN_RMII_RX_ER, RMII_RX_ER_MARK), 1676 GPIO_FN(RMII_RX_ER),
1673 PINMUX_GPIO(GPIO_FN_RMII_CRS_DV, RMII_CRS_DV_MARK), 1677 GPIO_FN(RMII_CRS_DV),
1674 PINMUX_GPIO(GPIO_FN_LNKSTA, LNKSTA_MARK), 1678 GPIO_FN(LNKSTA),
1675 PINMUX_GPIO(GPIO_FN_MDIO, MDIO_MARK), 1679 GPIO_FN(MDIO),
1676 PINMUX_GPIO(GPIO_FN_MDC, MDC_MARK), 1680 GPIO_FN(MDC),
1677 1681
1678 /* System */ 1682 /* System */
1679 PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), 1683 GPIO_FN(PDSTATUS),
1680 PINMUX_GPIO(GPIO_FN_STATUS2, STATUS2_MARK), 1684 GPIO_FN(STATUS2),
1681 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 1685 GPIO_FN(STATUS0),
1682 1686
1683 /* VOU */ 1687 /* VOU */
1684 PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), 1688 GPIO_FN(DV_D15),
1685 PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), 1689 GPIO_FN(DV_D14),
1686 PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), 1690 GPIO_FN(DV_D13),
1687 PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), 1691 GPIO_FN(DV_D12),
1688 PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), 1692 GPIO_FN(DV_D11),
1689 PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), 1693 GPIO_FN(DV_D10),
1690 PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), 1694 GPIO_FN(DV_D9),
1691 PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), 1695 GPIO_FN(DV_D8),
1692 PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), 1696 GPIO_FN(DV_D7),
1693 PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), 1697 GPIO_FN(DV_D6),
1694 PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), 1698 GPIO_FN(DV_D5),
1695 PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), 1699 GPIO_FN(DV_D4),
1696 PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), 1700 GPIO_FN(DV_D3),
1697 PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), 1701 GPIO_FN(DV_D2),
1698 PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), 1702 GPIO_FN(DV_D1),
1699 PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), 1703 GPIO_FN(DV_D0),
1700 PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), 1704 GPIO_FN(DV_CLKI),
1701 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), 1705 GPIO_FN(DV_CLK),
1702 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), 1706 GPIO_FN(DV_VSYNC),
1703 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), 1707 GPIO_FN(DV_HSYNC),
1704 1708
1705 /* MSIOF0 */ 1709 /* MSIOF0 */
1706 PINMUX_GPIO(GPIO_FN_MSIOF0_RXD, MSIOF0_RXD_MARK), 1710 GPIO_FN(MSIOF0_RXD),
1707 PINMUX_GPIO(GPIO_FN_MSIOF0_TXD, MSIOF0_TXD_MARK), 1711 GPIO_FN(MSIOF0_TXD),
1708 PINMUX_GPIO(GPIO_FN_MSIOF0_MCK, MSIOF0_MCK_MARK), 1712 GPIO_FN(MSIOF0_MCK),
1709 PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK, MSIOF0_TSCK_MARK), 1713 GPIO_FN(MSIOF0_TSCK),
1710 PINMUX_GPIO(GPIO_FN_MSIOF0_SS1, MSIOF0_SS1_MARK), 1714 GPIO_FN(MSIOF0_SS1),
1711 PINMUX_GPIO(GPIO_FN_MSIOF0_SS2, MSIOF0_SS2_MARK), 1715 GPIO_FN(MSIOF0_SS2),
1712 PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC, MSIOF0_TSYNC_MARK), 1716 GPIO_FN(MSIOF0_TSYNC),
1713 PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK, MSIOF0_RSCK_MARK), 1717 GPIO_FN(MSIOF0_RSCK),
1714 PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC, MSIOF0_RSYNC_MARK), 1718 GPIO_FN(MSIOF0_RSYNC),
1715 1719
1716 /* MSIOF1 */ 1720 /* MSIOF1 */
1717 PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), 1721 GPIO_FN(MSIOF1_RXD),
1718 PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), 1722 GPIO_FN(MSIOF1_TXD),
1719 PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), 1723 GPIO_FN(MSIOF1_MCK),
1720 PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), 1724 GPIO_FN(MSIOF1_TSCK),
1721 PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), 1725 GPIO_FN(MSIOF1_SS1),
1722 PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), 1726 GPIO_FN(MSIOF1_SS2),
1723 PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), 1727 GPIO_FN(MSIOF1_TSYNC),
1724 PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), 1728 GPIO_FN(MSIOF1_RSCK),
1725 PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), 1729 GPIO_FN(MSIOF1_RSYNC),
1726 1730
1727 /* DMAC */ 1731 /* DMAC */
1728 PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK), 1732 GPIO_FN(DMAC_DACK0),
1729 PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK), 1733 GPIO_FN(DMAC_DREQ0),
1730 PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK), 1734 GPIO_FN(DMAC_DACK1),
1731 PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK), 1735 GPIO_FN(DMAC_DREQ1),
1732 1736
1733 /* SDHI0 */ 1737 /* SDHI0 */
1734 PINMUX_GPIO(GPIO_FN_SDHI0CD, SDHI0CD_MARK), 1738 GPIO_FN(SDHI0CD),
1735 PINMUX_GPIO(GPIO_FN_SDHI0WP, SDHI0WP_MARK), 1739 GPIO_FN(SDHI0WP),
1736 PINMUX_GPIO(GPIO_FN_SDHI0CMD, SDHI0CMD_MARK), 1740 GPIO_FN(SDHI0CMD),
1737 PINMUX_GPIO(GPIO_FN_SDHI0CLK, SDHI0CLK_MARK), 1741 GPIO_FN(SDHI0CLK),
1738 PINMUX_GPIO(GPIO_FN_SDHI0D3, SDHI0D3_MARK), 1742 GPIO_FN(SDHI0D3),
1739 PINMUX_GPIO(GPIO_FN_SDHI0D2, SDHI0D2_MARK), 1743 GPIO_FN(SDHI0D2),
1740 PINMUX_GPIO(GPIO_FN_SDHI0D1, SDHI0D1_MARK), 1744 GPIO_FN(SDHI0D1),
1741 PINMUX_GPIO(GPIO_FN_SDHI0D0, SDHI0D0_MARK), 1745 GPIO_FN(SDHI0D0),
1742 1746
1743 /* SDHI1 */ 1747 /* SDHI1 */
1744 PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), 1748 GPIO_FN(SDHI1CD),
1745 PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), 1749 GPIO_FN(SDHI1WP),
1746 PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), 1750 GPIO_FN(SDHI1CMD),
1747 PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), 1751 GPIO_FN(SDHI1CLK),
1748 PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), 1752 GPIO_FN(SDHI1D3),
1749 PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), 1753 GPIO_FN(SDHI1D2),
1750 PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), 1754 GPIO_FN(SDHI1D1),
1751 PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), 1755 GPIO_FN(SDHI1D0),
1752 1756
1753 /* MMC */ 1757 /* MMC */
1754 PINMUX_GPIO(GPIO_FN_MMC_D7, MMC_D7_MARK), 1758 GPIO_FN(MMC_D7),
1755 PINMUX_GPIO(GPIO_FN_MMC_D6, MMC_D6_MARK), 1759 GPIO_FN(MMC_D6),
1756 PINMUX_GPIO(GPIO_FN_MMC_D5, MMC_D5_MARK), 1760 GPIO_FN(MMC_D5),
1757 PINMUX_GPIO(GPIO_FN_MMC_D4, MMC_D4_MARK), 1761 GPIO_FN(MMC_D4),
1758 PINMUX_GPIO(GPIO_FN_MMC_D3, MMC_D3_MARK), 1762 GPIO_FN(MMC_D3),
1759 PINMUX_GPIO(GPIO_FN_MMC_D2, MMC_D2_MARK), 1763 GPIO_FN(MMC_D2),
1760 PINMUX_GPIO(GPIO_FN_MMC_D1, MMC_D1_MARK), 1764 GPIO_FN(MMC_D1),
1761 PINMUX_GPIO(GPIO_FN_MMC_D0, MMC_D0_MARK), 1765 GPIO_FN(MMC_D0),
1762 PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), 1766 GPIO_FN(MMC_CLK),
1763 PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), 1767 GPIO_FN(MMC_CMD),
1764 1768
1765 /* IrDA */ 1769 /* IrDA */
1766 PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), 1770 GPIO_FN(IRDA_OUT),
1767 PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), 1771 GPIO_FN(IRDA_IN),
1768 1772
1769 /* TSIF */ 1773 /* TSIF */
1770 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT, TSIF_TS0_SDAT_MARK), 1774 GPIO_FN(TSIF_TS0_SDAT),
1771 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK, TSIF_TS0_SCK_MARK), 1775 GPIO_FN(TSIF_TS0_SCK),
1772 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN, TSIF_TS0_SDEN_MARK), 1776 GPIO_FN(TSIF_TS0_SDEN),
1773 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC, TSIF_TS0_SPSYNC_MARK), 1777 GPIO_FN(TSIF_TS0_SPSYNC),
1774 1778
1775 /* IRQ */ 1779 /* IRQ */
1776 PINMUX_GPIO(GPIO_FN_INTC_IRQ7, INTC_IRQ7_MARK), 1780 GPIO_FN(INTC_IRQ7),
1777 PINMUX_GPIO(GPIO_FN_INTC_IRQ6, INTC_IRQ6_MARK), 1781 GPIO_FN(INTC_IRQ6),
1778 PINMUX_GPIO(GPIO_FN_INTC_IRQ5, INTC_IRQ5_MARK), 1782 GPIO_FN(INTC_IRQ5),
1779 PINMUX_GPIO(GPIO_FN_INTC_IRQ4, INTC_IRQ4_MARK), 1783 GPIO_FN(INTC_IRQ4),
1780 PINMUX_GPIO(GPIO_FN_INTC_IRQ3, INTC_IRQ3_MARK), 1784 GPIO_FN(INTC_IRQ3),
1781 PINMUX_GPIO(GPIO_FN_INTC_IRQ2, INTC_IRQ2_MARK), 1785 GPIO_FN(INTC_IRQ2),
1782 PINMUX_GPIO(GPIO_FN_INTC_IRQ1, INTC_IRQ1_MARK), 1786 GPIO_FN(INTC_IRQ1),
1783 PINMUX_GPIO(GPIO_FN_INTC_IRQ0, INTC_IRQ0_MARK), 1787 GPIO_FN(INTC_IRQ0),
1784}; 1788};
1785 1789
1786static struct pinmux_cfg_reg pinmux_config_regs[] = { 1790static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1787 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 1791 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1788 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, 1792 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
1789 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, 1793 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
@@ -2107,7 +2111,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2107 {} 2111 {}
2108}; 2112};
2109 2113
2110static struct pinmux_data_reg pinmux_data_regs[] = { 2114static const struct pinmux_data_reg pinmux_data_regs[] = {
2111 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { 2115 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
2112 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 2116 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
2113 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 2117 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -2203,20 +2207,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2203 { }, 2207 { },
2204}; 2208};
2205 2209
2206struct sh_pfc_soc_info sh7724_pinmux_info = { 2210const struct sh_pfc_soc_info sh7724_pinmux_info = {
2207 .name = "sh7724_pfc", 2211 .name = "sh7724_pfc",
2208 .reserved_id = PINMUX_RESERVED,
2209 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2210 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2212 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2211 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 2213 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2212 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2214 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2213 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2214 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2215 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2215 2216
2216 .first_gpio = GPIO_PTA7, 2217 .pins = pinmux_pins,
2217 .last_gpio = GPIO_FN_INTC_IRQ0, 2218 .nr_pins = ARRAY_SIZE(pinmux_pins),
2219 .func_gpios = pinmux_func_gpios,
2220 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2218 2221
2219 .gpios = pinmux_gpios,
2220 .cfg_regs = pinmux_config_regs, 2222 .cfg_regs = pinmux_config_regs,
2221 .data_regs = pinmux_data_regs, 2223 .data_regs = pinmux_data_regs,
2222 2224
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index 23d76d262c32..2fd5b7d4cb94 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -14,11 +14,6 @@
14 14
15#include "sh_pfc.h" 15#include "sh_pfc.h"
16 16
17#define CPU_32_PORT(fn, pfx, sfx) \
18 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
19 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
20 PORT_1(fn, pfx##31, sfx)
21
22#define CPU_32_PORT5(fn, pfx, sfx) \ 17#define CPU_32_PORT5(fn, pfx, sfx) \
23 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ 18 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
24 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ 19 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
@@ -29,11 +24,11 @@
29 24
30/* GPSR0 - GPSR5 */ 25/* GPSR0 - GPSR5 */
31#define CPU_ALL_PORT(fn, pfx, sfx) \ 26#define CPU_ALL_PORT(fn, pfx, sfx) \
32 CPU_32_PORT(fn, pfx##_0_, sfx), \ 27 PORT_32(fn, pfx##_0_, sfx), \
33 CPU_32_PORT(fn, pfx##_1_, sfx), \ 28 PORT_32(fn, pfx##_1_, sfx), \
34 CPU_32_PORT(fn, pfx##_2_, sfx), \ 29 PORT_32(fn, pfx##_2_, sfx), \
35 CPU_32_PORT(fn, pfx##_3_, sfx), \ 30 PORT_32(fn, pfx##_3_, sfx), \
36 CPU_32_PORT(fn, pfx##_4_, sfx), \ 31 PORT_32(fn, pfx##_4_, sfx), \
37 CPU_32_PORT5(fn, pfx##_5_, sfx) 32 CPU_32_PORT5(fn, pfx##_5_, sfx)
38 33
39#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) 34#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
@@ -47,20 +42,8 @@
47#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) 42#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
48#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) 43#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
49 44
50#define PORT_10_REV(fn, pfx, sfx) \ 45#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
51 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ 46#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
52 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
53 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
54 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
55 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
56
57#define CPU_32_PORT_REV(fn, pfx, sfx) \
58 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
59 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
60 PORT_10_REV(fn, pfx, sfx)
61
62#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
63#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
64 47
65#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) 48#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
66#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ 49#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
@@ -609,7 +592,7 @@ enum {
609 PINMUX_MARK_END, 592 PINMUX_MARK_END,
610}; 593};
611 594
612static pinmux_enum_t pinmux_data[] = { 595static const pinmux_enum_t pinmux_data[] = {
613 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 596 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
614 597
615 PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT), 598 PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),
@@ -1384,9 +1367,13 @@ static pinmux_enum_t pinmux_data[] = {
1384 PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT), 1367 PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
1385}; 1368};
1386 1369
1387static struct pinmux_gpio pinmux_gpios[] = { 1370static struct sh_pfc_pin pinmux_pins[] = {
1388 PINMUX_GPIO_GP_ALL(), 1371 PINMUX_GPIO_GP_ALL(),
1372};
1373
1374#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1389 1375
1376static const struct pinmux_func pinmux_func_gpios[] = {
1390 GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0), 1377 GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
1391 GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1), 1378 GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
1392 GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0), 1379 GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
@@ -1665,7 +1652,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
1665 GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C), 1652 GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
1666}; 1653};
1667 1654
1668static struct pinmux_cfg_reg pinmux_config_regs[] = { 1655static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1669 { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) { 1656 { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) {
1670 GP_0_31_FN, FN_IP2_2_0, 1657 GP_0_31_FN, FN_IP2_2_0,
1671 GP_0_30_FN, FN_IP1_31_29, 1658 GP_0_30_FN, FN_IP1_31_29,
@@ -2434,7 +2421,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2434 { }, 2421 { },
2435}; 2422};
2436 2423
2437static struct pinmux_data_reg pinmux_data_regs[] = { 2424static const struct pinmux_data_reg pinmux_data_regs[] = {
2438 /* GPIO 0 - 5*/ 2425 /* GPIO 0 - 5*/
2439 { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } }, 2426 { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } },
2440 { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } }, 2427 { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } },
@@ -2451,22 +2438,20 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2451 { }, 2438 { },
2452}; 2439};
2453 2440
2454struct sh_pfc_soc_info sh7734_pinmux_info = { 2441const struct sh_pfc_soc_info sh7734_pinmux_info = {
2455 .name = "sh7734_pfc", 2442 .name = "sh7734_pfc",
2456 2443
2457 .unlock_reg = 0xFFFC0000, 2444 .unlock_reg = 0xFFFC0000,
2458 2445
2459 .reserved_id = PINMUX_RESERVED,
2460 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2461 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2446 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2462 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2447 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2463 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2464 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2448 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2465 2449
2466 .first_gpio = GPIO_GP_0_0, 2450 .pins = pinmux_pins,
2467 .last_gpio = GPIO_FN_ST_CLKOUT, 2451 .nr_pins = ARRAY_SIZE(pinmux_pins),
2452 .func_gpios = pinmux_func_gpios,
2453 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2468 2454
2469 .gpios = pinmux_gpios,
2470 .cfg_regs = pinmux_config_regs, 2455 .cfg_regs = pinmux_config_regs,
2471 .data_regs = pinmux_data_regs, 2456 .data_regs = pinmux_data_regs,
2472 2457
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index 5ed74cd0ba99..e074230e6243 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -526,7 +526,7 @@ enum {
526 PINMUX_MARK_END, 526 PINMUX_MARK_END,
527}; 527};
528 528
529static pinmux_enum_t pinmux_data[] = { 529static const pinmux_enum_t pinmux_data[] = {
530 /* PTA GPIO */ 530 /* PTA GPIO */
531 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), 531 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
532 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), 532 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
@@ -1114,7 +1114,7 @@ static pinmux_enum_t pinmux_data[] = {
1114 PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN), 1114 PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
1115}; 1115};
1116 1116
1117static struct pinmux_gpio pinmux_gpios[] = { 1117static struct sh_pfc_pin pinmux_pins[] = {
1118 /* PTA */ 1118 /* PTA */
1119 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), 1119 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
1120 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), 1120 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1370,359 +1370,363 @@ static struct pinmux_gpio pinmux_gpios[] = {
1370 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), 1370 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1371 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), 1371 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1372 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), 1372 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1373};
1374
1375#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1373 1376
1377static const struct pinmux_func pinmux_func_gpios[] = {
1374 /* PTA (mobule: LBSC, RGMII) */ 1378 /* PTA (mobule: LBSC, RGMII) */
1375 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1379 GPIO_FN(BS),
1376 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), 1380 GPIO_FN(RDWR),
1377 PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK), 1381 GPIO_FN(WE1),
1378 PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK), 1382 GPIO_FN(RDY),
1379 PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK), 1383 GPIO_FN(ET0_MDC),
1380 PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK), 1384 GPIO_FN(ET0_MDIO),
1381 PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK), 1385 GPIO_FN(ET1_MDC),
1382 PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK), 1386 GPIO_FN(ET1_MDIO),
1383 1387
1384 /* PTB (mobule: INTC, ONFI, TMU) */ 1388 /* PTB (mobule: INTC, ONFI, TMU) */
1385 PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), 1389 GPIO_FN(IRQ15),
1386 PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), 1390 GPIO_FN(IRQ14),
1387 PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), 1391 GPIO_FN(IRQ13),
1388 PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), 1392 GPIO_FN(IRQ12),
1389 PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), 1393 GPIO_FN(IRQ11),
1390 PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), 1394 GPIO_FN(IRQ10),
1391 PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), 1395 GPIO_FN(IRQ9),
1392 PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), 1396 GPIO_FN(IRQ8),
1393 PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK), 1397 GPIO_FN(ON_NRE),
1394 PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK), 1398 GPIO_FN(ON_NWE),
1395 PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK), 1399 GPIO_FN(ON_NWP),
1396 PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK), 1400 GPIO_FN(ON_NCE0),
1397 PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK), 1401 GPIO_FN(ON_R_B0),
1398 PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK), 1402 GPIO_FN(ON_ALE),
1399 PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK), 1403 GPIO_FN(ON_CLE),
1400 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), 1404 GPIO_FN(TCLK),
1401 1405
1402 /* PTC (mobule: IRQ, PWMU) */ 1406 /* PTC (mobule: IRQ, PWMU) */
1403 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), 1407 GPIO_FN(IRQ7),
1404 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), 1408 GPIO_FN(IRQ6),
1405 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), 1409 GPIO_FN(IRQ5),
1406 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), 1410 GPIO_FN(IRQ4),
1407 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), 1411 GPIO_FN(IRQ3),
1408 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), 1412 GPIO_FN(IRQ2),
1409 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), 1413 GPIO_FN(IRQ1),
1410 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), 1414 GPIO_FN(IRQ0),
1411 PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK), 1415 GPIO_FN(PWMU0),
1412 PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK), 1416 GPIO_FN(PWMU1),
1413 PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK), 1417 GPIO_FN(PWMU2),
1414 PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK), 1418 GPIO_FN(PWMU3),
1415 PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK), 1419 GPIO_FN(PWMU4),
1416 PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK), 1420 GPIO_FN(PWMU5),
1417 1421
1418 /* PTD (mobule: SPI0, DMAC) */ 1422 /* PTD (mobule: SPI0, DMAC) */
1419 PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK), 1423 GPIO_FN(SP0_MOSI),
1420 PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK), 1424 GPIO_FN(SP0_MISO),
1421 PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK), 1425 GPIO_FN(SP0_SCK),
1422 PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK), 1426 GPIO_FN(SP0_SCK_FB),
1423 PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK), 1427 GPIO_FN(SP0_SS0),
1424 PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), 1428 GPIO_FN(SP0_SS1),
1425 PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK), 1429 GPIO_FN(SP0_SS2),
1426 PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK), 1430 GPIO_FN(SP0_SS3),
1427 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 1431 GPIO_FN(DREQ0),
1428 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 1432 GPIO_FN(DACK0),
1429 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), 1433 GPIO_FN(TEND0),
1430 1434
1431 /* PTE (mobule: RMII) */ 1435 /* PTE (mobule: RMII) */
1432 PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK), 1436 GPIO_FN(RMII0_CRS_DV),
1433 PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK), 1437 GPIO_FN(RMII0_TXD1),
1434 PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK), 1438 GPIO_FN(RMII0_TXD0),
1435 PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK), 1439 GPIO_FN(RMII0_TXEN),
1436 PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK), 1440 GPIO_FN(RMII0_REFCLK),
1437 PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK), 1441 GPIO_FN(RMII0_RXD1),
1438 PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK), 1442 GPIO_FN(RMII0_RXD0),
1439 PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK), 1443 GPIO_FN(RMII0_RX_ER),
1440 1444
1441 /* PTF (mobule: RMII, SerMux) */ 1445 /* PTF (mobule: RMII, SerMux) */
1442 PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK), 1446 GPIO_FN(RMII1_CRS_DV),
1443 PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK), 1447 GPIO_FN(RMII1_TXD1),
1444 PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK), 1448 GPIO_FN(RMII1_TXD0),
1445 PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK), 1449 GPIO_FN(RMII1_TXEN),
1446 PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK), 1450 GPIO_FN(RMII1_REFCLK),
1447 PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK), 1451 GPIO_FN(RMII1_RXD1),
1448 PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK), 1452 GPIO_FN(RMII1_RXD0),
1449 PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK), 1453 GPIO_FN(RMII1_RX_ER),
1450 PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), 1454 GPIO_FN(RAC_RI),
1451 1455
1452 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ 1456 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
1453 PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK), 1457 GPIO_FN(BOOTFMS),
1454 PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK), 1458 GPIO_FN(BOOTWP),
1455 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1459 GPIO_FN(A25),
1456 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1460 GPIO_FN(A24),
1457 PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK), 1461 GPIO_FN(SERIRQ),
1458 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), 1462 GPIO_FN(WDTOVF),
1459 PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK), 1463 GPIO_FN(LPCPD),
1460 PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK), 1464 GPIO_FN(LDRQ),
1461 PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), 1465 GPIO_FN(MMCCLK),
1462 PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), 1466 GPIO_FN(MMCCMD),
1463 1467
1464 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ 1468 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
1465 PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK), 1469 GPIO_FN(SP1_MOSI),
1466 PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK), 1470 GPIO_FN(SP1_MISO),
1467 PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK), 1471 GPIO_FN(SP1_SCK),
1468 PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK), 1472 GPIO_FN(SP1_SCK_FB),
1469 PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK), 1473 GPIO_FN(SP1_SS0),
1470 PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK), 1474 GPIO_FN(SP1_SS1),
1471 PINMUX_GPIO(GPIO_FN_WP, WP_MARK), 1475 GPIO_FN(WP),
1472 PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK), 1476 GPIO_FN(FMS0),
1473 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), 1477 GPIO_FN(TEND1),
1474 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 1478 GPIO_FN(DREQ1),
1475 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 1479 GPIO_FN(DACK1),
1476 PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), 1480 GPIO_FN(ADTRG1),
1477 PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), 1481 GPIO_FN(ADTRG0),
1478 1482
1479 /* PTI (mobule: LBSC, SDHI) */ 1483 /* PTI (mobule: LBSC, SDHI) */
1480 PINMUX_GPIO(GPIO_FN_D15, D15_MARK), 1484 GPIO_FN(D15),
1481 PINMUX_GPIO(GPIO_FN_D14, D14_MARK), 1485 GPIO_FN(D14),
1482 PINMUX_GPIO(GPIO_FN_D13, D13_MARK), 1486 GPIO_FN(D13),
1483 PINMUX_GPIO(GPIO_FN_D12, D12_MARK), 1487 GPIO_FN(D12),
1484 PINMUX_GPIO(GPIO_FN_D11, D11_MARK), 1488 GPIO_FN(D11),
1485 PINMUX_GPIO(GPIO_FN_D10, D10_MARK), 1489 GPIO_FN(D10),
1486 PINMUX_GPIO(GPIO_FN_D9, D9_MARK), 1490 GPIO_FN(D9),
1487 PINMUX_GPIO(GPIO_FN_D8, D8_MARK), 1491 GPIO_FN(D8),
1488 PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK), 1492 GPIO_FN(SD_WP),
1489 PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK), 1493 GPIO_FN(SD_CD),
1490 PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK), 1494 GPIO_FN(SD_CLK),
1491 PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK), 1495 GPIO_FN(SD_CMD),
1492 PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK), 1496 GPIO_FN(SD_D3),
1493 PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK), 1497 GPIO_FN(SD_D2),
1494 PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK), 1498 GPIO_FN(SD_D1),
1495 PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK), 1499 GPIO_FN(SD_D0),
1496 1500
1497 /* PTJ (mobule: SCIF234, SERMUX) */ 1501 /* PTJ (mobule: SCIF234, SERMUX) */
1498 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), 1502 GPIO_FN(RTS3),
1499 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), 1503 GPIO_FN(CTS3),
1500 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 1504 GPIO_FN(TXD3),
1501 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 1505 GPIO_FN(RXD3),
1502 PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), 1506 GPIO_FN(RTS4),
1503 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), 1507 GPIO_FN(RXD4),
1504 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), 1508 GPIO_FN(TXD4),
1505 1509
1506 /* PTK (mobule: SERMUX, LBSC, SCIF) */ 1510 /* PTK (mobule: SERMUX, LBSC, SCIF) */
1507 PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK), 1511 GPIO_FN(COM2_TXD),
1508 PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK), 1512 GPIO_FN(COM2_RXD),
1509 PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK), 1513 GPIO_FN(COM2_RTS),
1510 PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK), 1514 GPIO_FN(COM2_CTS),
1511 PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK), 1515 GPIO_FN(COM2_DTR),
1512 PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK), 1516 GPIO_FN(COM2_DSR),
1513 PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK), 1517 GPIO_FN(COM2_DCD),
1514 PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK), 1518 GPIO_FN(CLKOUT),
1515 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 1519 GPIO_FN(SCK2),
1516 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), 1520 GPIO_FN(SCK4),
1517 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), 1521 GPIO_FN(SCK3),
1518 1522
1519 /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ 1523 /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
1520 PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK), 1524 GPIO_FN(RAC_RXD),
1521 PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK), 1525 GPIO_FN(RAC_RTS),
1522 PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK), 1526 GPIO_FN(RAC_CTS),
1523 PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK), 1527 GPIO_FN(RAC_DTR),
1524 PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK), 1528 GPIO_FN(RAC_DSR),
1525 PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK), 1529 GPIO_FN(RAC_DCD),
1526 PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK), 1530 GPIO_FN(RAC_TXD),
1527 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 1531 GPIO_FN(RXD2),
1528 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), 1532 GPIO_FN(CS5),
1529 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), 1533 GPIO_FN(CS6),
1530 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 1534 GPIO_FN(AUDSYNC),
1531 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), 1535 GPIO_FN(AUDCK),
1532 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 1536 GPIO_FN(TXD2),
1533 1537
1534 /* PTM (mobule: LBSC, IIC) */ 1538 /* PTM (mobule: LBSC, IIC) */
1535 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), 1539 GPIO_FN(CS4),
1536 PINMUX_GPIO(GPIO_FN_RD, RD_MARK), 1540 GPIO_FN(RD),
1537 PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK), 1541 GPIO_FN(WE0),
1538 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), 1542 GPIO_FN(CS0),
1539 PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK), 1543 GPIO_FN(SDA6),
1540 PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK), 1544 GPIO_FN(SCL6),
1541 PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK), 1545 GPIO_FN(SDA7),
1542 PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK), 1546 GPIO_FN(SCL7),
1543 1547
1544 /* PTN (mobule: USB, JMC, SGPIO, WDT) */ 1548 /* PTN (mobule: USB, JMC, SGPIO, WDT) */
1545 PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK), 1549 GPIO_FN(VBUS_EN),
1546 PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK), 1550 GPIO_FN(VBUS_OC),
1547 PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK), 1551 GPIO_FN(JMCTCK),
1548 PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK), 1552 GPIO_FN(JMCTMS),
1549 PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK), 1553 GPIO_FN(JMCTDO),
1550 PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK), 1554 GPIO_FN(JMCTDI),
1551 PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK), 1555 GPIO_FN(JMCTRST),
1552 PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), 1556 GPIO_FN(SGPIO1_CLK),
1553 PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), 1557 GPIO_FN(SGPIO1_LOAD),
1554 PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), 1558 GPIO_FN(SGPIO1_DI),
1555 PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), 1559 GPIO_FN(SGPIO1_DO),
1556 PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK), 1560 GPIO_FN(SUB_CLKIN),
1557 1561
1558 /* PTO (mobule: SGPIO, SerMux) */ 1562 /* PTO (mobule: SGPIO, SerMux) */
1559 PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK), 1563 GPIO_FN(SGPIO0_CLK),
1560 PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK), 1564 GPIO_FN(SGPIO0_LOAD),
1561 PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK), 1565 GPIO_FN(SGPIO0_DI),
1562 PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK), 1566 GPIO_FN(SGPIO0_DO),
1563 PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK), 1567 GPIO_FN(SGPIO2_CLK),
1564 PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK), 1568 GPIO_FN(SGPIO2_LOAD),
1565 PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK), 1569 GPIO_FN(SGPIO2_DI),
1566 PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK), 1570 GPIO_FN(SGPIO2_DO),
1567 PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), 1571 GPIO_FN(COM1_TXD),
1568 PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), 1572 GPIO_FN(COM1_RXD),
1569 PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK), 1573 GPIO_FN(COM1_RTS),
1570 PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK), 1574 GPIO_FN(COM1_CTS),
1571 1575
1572 /* PTP (mobule: EVC, ADC) */ 1576 /* PTP (mobule: EVC, ADC) */
1573 1577
1574 /* PTQ (mobule: LPC) */ 1578 /* PTQ (mobule: LPC) */
1575 PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK), 1579 GPIO_FN(LAD3),
1576 PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK), 1580 GPIO_FN(LAD2),
1577 PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK), 1581 GPIO_FN(LAD1),
1578 PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK), 1582 GPIO_FN(LAD0),
1579 PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK), 1583 GPIO_FN(LFRAME),
1580 PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK), 1584 GPIO_FN(LRESET),
1581 PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK), 1585 GPIO_FN(LCLK),
1582 1586
1583 /* PTR (mobule: GRA, IIC) */ 1587 /* PTR (mobule: GRA, IIC) */
1584 PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK), 1588 GPIO_FN(DDC3),
1585 PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK), 1589 GPIO_FN(DDC2),
1586 PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK), 1590 GPIO_FN(SDA8),
1587 PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK), 1591 GPIO_FN(SCL8),
1588 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), 1592 GPIO_FN(SDA2),
1589 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), 1593 GPIO_FN(SCL2),
1590 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), 1594 GPIO_FN(SDA1),
1591 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), 1595 GPIO_FN(SCL1),
1592 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), 1596 GPIO_FN(SDA0),
1593 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), 1597 GPIO_FN(SCL0),
1594 1598
1595 /* PTS (mobule: GRA, IIC) */ 1599 /* PTS (mobule: GRA, IIC) */
1596 PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK), 1600 GPIO_FN(DDC1),
1597 PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK), 1601 GPIO_FN(DDC0),
1598 PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK), 1602 GPIO_FN(SDA9),
1599 PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK), 1603 GPIO_FN(SCL9),
1600 PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK), 1604 GPIO_FN(SDA5),
1601 PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK), 1605 GPIO_FN(SCL5),
1602 PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK), 1606 GPIO_FN(SDA4),
1603 PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK), 1607 GPIO_FN(SCL4),
1604 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), 1608 GPIO_FN(SDA3),
1605 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), 1609 GPIO_FN(SCL3),
1606 1610
1607 /* PTT (mobule: PWMX, AUD) */ 1611 /* PTT (mobule: PWMX, AUD) */
1608 PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK), 1612 GPIO_FN(PWMX7),
1609 PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK), 1613 GPIO_FN(PWMX6),
1610 PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK), 1614 GPIO_FN(PWMX5),
1611 PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK), 1615 GPIO_FN(PWMX4),
1612 PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK), 1616 GPIO_FN(PWMX3),
1613 PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK), 1617 GPIO_FN(PWMX2),
1614 PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK), 1618 GPIO_FN(PWMX1),
1615 PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK), 1619 GPIO_FN(PWMX0),
1616 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 1620 GPIO_FN(AUDATA3),
1617 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 1621 GPIO_FN(AUDATA2),
1618 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 1622 GPIO_FN(AUDATA1),
1619 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 1623 GPIO_FN(AUDATA0),
1620 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), 1624 GPIO_FN(STATUS1),
1621 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 1625 GPIO_FN(STATUS0),
1622 1626
1623 /* PTU (mobule: LPC, APM) */ 1627 /* PTU (mobule: LPC, APM) */
1624 PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK), 1628 GPIO_FN(LGPIO7),
1625 PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK), 1629 GPIO_FN(LGPIO6),
1626 PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK), 1630 GPIO_FN(LGPIO5),
1627 PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK), 1631 GPIO_FN(LGPIO4),
1628 PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK), 1632 GPIO_FN(LGPIO3),
1629 PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK), 1633 GPIO_FN(LGPIO2),
1630 PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK), 1634 GPIO_FN(LGPIO1),
1631 PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK), 1635 GPIO_FN(LGPIO0),
1632 PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK), 1636 GPIO_FN(APMONCTL_O),
1633 PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK), 1637 GPIO_FN(APMPWBTOUT_O),
1634 PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK), 1638 GPIO_FN(APMSCI_O),
1635 PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK), 1639 GPIO_FN(APMVDDON),
1636 PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK), 1640 GPIO_FN(APMSLPBTN),
1637 PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK), 1641 GPIO_FN(APMPWRBTN),
1638 PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK), 1642 GPIO_FN(APMS5N),
1639 PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK), 1643 GPIO_FN(APMS3N),
1640 1644
1641 /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ 1645 /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
1642 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1646 GPIO_FN(A23),
1643 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1647 GPIO_FN(A22),
1644 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 1648 GPIO_FN(A21),
1645 PINMUX_GPIO(GPIO_FN_A20, A20_MARK), 1649 GPIO_FN(A20),
1646 PINMUX_GPIO(GPIO_FN_A19, A19_MARK), 1650 GPIO_FN(A19),
1647 PINMUX_GPIO(GPIO_FN_A18, A18_MARK), 1651 GPIO_FN(A18),
1648 PINMUX_GPIO(GPIO_FN_A17, A17_MARK), 1652 GPIO_FN(A17),
1649 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1653 GPIO_FN(A16),
1650 PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), 1654 GPIO_FN(COM2_RI),
1651 PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK), 1655 GPIO_FN(R_SPI_MOSI),
1652 PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK), 1656 GPIO_FN(R_SPI_MISO),
1653 PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK), 1657 GPIO_FN(R_SPI_RSPCK),
1654 PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK), 1658 GPIO_FN(R_SPI_SSL0),
1655 PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK), 1659 GPIO_FN(R_SPI_SSL1),
1656 PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), 1660 GPIO_FN(EVENT7),
1657 PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), 1661 GPIO_FN(EVENT6),
1658 PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK), 1662 GPIO_FN(VBIOS_DI),
1659 PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK), 1663 GPIO_FN(VBIOS_DO),
1660 PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK), 1664 GPIO_FN(VBIOS_CLK),
1661 PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK), 1665 GPIO_FN(VBIOS_CS),
1662 1666
1663 /* PTW (mobule: LBSC, EVC, SCIF) */ 1667 /* PTW (mobule: LBSC, EVC, SCIF) */
1664 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1668 GPIO_FN(A16),
1665 PINMUX_GPIO(GPIO_FN_A15, A15_MARK), 1669 GPIO_FN(A15),
1666 PINMUX_GPIO(GPIO_FN_A14, A14_MARK), 1670 GPIO_FN(A14),
1667 PINMUX_GPIO(GPIO_FN_A13, A13_MARK), 1671 GPIO_FN(A13),
1668 PINMUX_GPIO(GPIO_FN_A12, A12_MARK), 1672 GPIO_FN(A12),
1669 PINMUX_GPIO(GPIO_FN_A11, A11_MARK), 1673 GPIO_FN(A11),
1670 PINMUX_GPIO(GPIO_FN_A10, A10_MARK), 1674 GPIO_FN(A10),
1671 PINMUX_GPIO(GPIO_FN_A9, A9_MARK), 1675 GPIO_FN(A9),
1672 PINMUX_GPIO(GPIO_FN_A8, A8_MARK), 1676 GPIO_FN(A8),
1673 PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), 1677 GPIO_FN(EVENT5),
1674 PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), 1678 GPIO_FN(EVENT4),
1675 PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), 1679 GPIO_FN(EVENT3),
1676 PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK), 1680 GPIO_FN(EVENT2),
1677 PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK), 1681 GPIO_FN(EVENT1),
1678 PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK), 1682 GPIO_FN(EVENT0),
1679 PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), 1683 GPIO_FN(CTS4),
1680 PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), 1684 GPIO_FN(CTS2),
1681 1685
1682 /* PTX (mobule: LBSC) */ 1686 /* PTX (mobule: LBSC) */
1683 PINMUX_GPIO(GPIO_FN_A7, A7_MARK), 1687 GPIO_FN(A7),
1684 PINMUX_GPIO(GPIO_FN_A6, A6_MARK), 1688 GPIO_FN(A6),
1685 PINMUX_GPIO(GPIO_FN_A5, A5_MARK), 1689 GPIO_FN(A5),
1686 PINMUX_GPIO(GPIO_FN_A4, A4_MARK), 1690 GPIO_FN(A4),
1687 PINMUX_GPIO(GPIO_FN_A3, A3_MARK), 1691 GPIO_FN(A3),
1688 PINMUX_GPIO(GPIO_FN_A2, A2_MARK), 1692 GPIO_FN(A2),
1689 PINMUX_GPIO(GPIO_FN_A1, A1_MARK), 1693 GPIO_FN(A1),
1690 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 1694 GPIO_FN(A0),
1691 PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), 1695 GPIO_FN(RTS2),
1692 PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), 1696 GPIO_FN(SIM_D),
1693 PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), 1697 GPIO_FN(SIM_CLK),
1694 PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), 1698 GPIO_FN(SIM_RST),
1695 1699
1696 /* PTY (mobule: LBSC) */ 1700 /* PTY (mobule: LBSC) */
1697 PINMUX_GPIO(GPIO_FN_D7, D7_MARK), 1701 GPIO_FN(D7),
1698 PINMUX_GPIO(GPIO_FN_D6, D6_MARK), 1702 GPIO_FN(D6),
1699 PINMUX_GPIO(GPIO_FN_D5, D5_MARK), 1703 GPIO_FN(D5),
1700 PINMUX_GPIO(GPIO_FN_D4, D4_MARK), 1704 GPIO_FN(D4),
1701 PINMUX_GPIO(GPIO_FN_D3, D3_MARK), 1705 GPIO_FN(D3),
1702 PINMUX_GPIO(GPIO_FN_D2, D2_MARK), 1706 GPIO_FN(D2),
1703 PINMUX_GPIO(GPIO_FN_D1, D1_MARK), 1707 GPIO_FN(D1),
1704 PINMUX_GPIO(GPIO_FN_D0, D0_MARK), 1708 GPIO_FN(D0),
1705 1709
1706 /* PTZ (mobule: eMMC, ONFI) */ 1710 /* PTZ (mobule: eMMC, ONFI) */
1707 PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK), 1711 GPIO_FN(MMCDAT7),
1708 PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK), 1712 GPIO_FN(MMCDAT6),
1709 PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK), 1713 GPIO_FN(MMCDAT5),
1710 PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK), 1714 GPIO_FN(MMCDAT4),
1711 PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK), 1715 GPIO_FN(MMCDAT3),
1712 PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK), 1716 GPIO_FN(MMCDAT2),
1713 PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK), 1717 GPIO_FN(MMCDAT1),
1714 PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK), 1718 GPIO_FN(MMCDAT0),
1715 PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK), 1719 GPIO_FN(ON_DQ7),
1716 PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK), 1720 GPIO_FN(ON_DQ6),
1717 PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK), 1721 GPIO_FN(ON_DQ5),
1718 PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK), 1722 GPIO_FN(ON_DQ4),
1719 PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK), 1723 GPIO_FN(ON_DQ3),
1720 PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK), 1724 GPIO_FN(ON_DQ2),
1721 PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK), 1725 GPIO_FN(ON_DQ1),
1722 PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK), 1726 GPIO_FN(ON_DQ0),
1723}; 1727};
1724 1728
1725static struct pinmux_cfg_reg pinmux_config_regs[] = { 1729static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1726 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { 1730 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
1727 PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU, 1731 PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
1728 PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU, 1732 PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
@@ -2152,7 +2156,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2152 {} 2156 {}
2153}; 2157};
2154 2158
2155static struct pinmux_data_reg pinmux_data_regs[] = { 2159static const struct pinmux_data_reg pinmux_data_regs[] = {
2156 { PINMUX_DATA_REG("PADR", 0xffec0034, 8) { 2160 { PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
2157 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 2161 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
2158 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 2162 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -2260,20 +2264,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2260 { }, 2264 { },
2261}; 2265};
2262 2266
2263struct sh_pfc_soc_info sh7757_pinmux_info = { 2267const struct sh_pfc_soc_info sh7757_pinmux_info = {
2264 .name = "sh7757_pfc", 2268 .name = "sh7757_pfc",
2265 .reserved_id = PINMUX_RESERVED,
2266 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2267 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2269 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2268 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 2270 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2269 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2271 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2270 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2271 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2272 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2272 2273
2273 .first_gpio = GPIO_PTA0, 2274 .pins = pinmux_pins,
2274 .last_gpio = GPIO_FN_ON_DQ0, 2275 .nr_pins = ARRAY_SIZE(pinmux_pins),
2276 .func_gpios = pinmux_func_gpios,
2277 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2275 2278
2276 .gpios = pinmux_gpios,
2277 .cfg_regs = pinmux_config_regs, 2279 .cfg_regs = pinmux_config_regs,
2278 .data_regs = pinmux_data_regs, 2280 .data_regs = pinmux_data_regs,
2279 2281
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index 3b1825d925bb..c176b794f240 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -355,7 +355,7 @@ enum {
355 PINMUX_MARK_END, 355 PINMUX_MARK_END,
356}; 356};
357 357
358static pinmux_enum_t pinmux_data[] = { 358static const pinmux_enum_t pinmux_data[] = {
359 359
360 /* PA GPIO */ 360 /* PA GPIO */
361 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), 361 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -702,7 +702,7 @@ static pinmux_enum_t pinmux_data[] = {
702 PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1), 702 PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1),
703}; 703};
704 704
705static struct pinmux_gpio pinmux_gpios[] = { 705static struct sh_pfc_pin pinmux_pins[] = {
706 /* PA */ 706 /* PA */
707 PINMUX_GPIO(GPIO_PA7, PA7_DATA), 707 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
708 PINMUX_GPIO(GPIO_PA6, PA6_DATA), 708 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -845,176 +845,180 @@ static struct pinmux_gpio pinmux_gpios[] = {
845 PINMUX_GPIO(GPIO_PR2, PR2_DATA), 845 PINMUX_GPIO(GPIO_PR2, PR2_DATA),
846 PINMUX_GPIO(GPIO_PR1, PR1_DATA), 846 PINMUX_GPIO(GPIO_PR1, PR1_DATA),
847 PINMUX_GPIO(GPIO_PR0, PR0_DATA), 847 PINMUX_GPIO(GPIO_PR0, PR0_DATA),
848};
849
850#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
848 851
852static const struct pinmux_func pinmux_func_gpios[] = {
849 /* FN */ 853 /* FN */
850 PINMUX_GPIO(GPIO_FN_D63_AD31, D63_AD31_MARK), 854 GPIO_FN(D63_AD31),
851 PINMUX_GPIO(GPIO_FN_D62_AD30, D62_AD30_MARK), 855 GPIO_FN(D62_AD30),
852 PINMUX_GPIO(GPIO_FN_D61_AD29, D61_AD29_MARK), 856 GPIO_FN(D61_AD29),
853 PINMUX_GPIO(GPIO_FN_D60_AD28, D60_AD28_MARK), 857 GPIO_FN(D60_AD28),
854 PINMUX_GPIO(GPIO_FN_D59_AD27, D59_AD27_MARK), 858 GPIO_FN(D59_AD27),
855 PINMUX_GPIO(GPIO_FN_D58_AD26, D58_AD26_MARK), 859 GPIO_FN(D58_AD26),
856 PINMUX_GPIO(GPIO_FN_D57_AD25, D57_AD25_MARK), 860 GPIO_FN(D57_AD25),
857 PINMUX_GPIO(GPIO_FN_D56_AD24, D56_AD24_MARK), 861 GPIO_FN(D56_AD24),
858 PINMUX_GPIO(GPIO_FN_D55_AD23, D55_AD23_MARK), 862 GPIO_FN(D55_AD23),
859 PINMUX_GPIO(GPIO_FN_D54_AD22, D54_AD22_MARK), 863 GPIO_FN(D54_AD22),
860 PINMUX_GPIO(GPIO_FN_D53_AD21, D53_AD21_MARK), 864 GPIO_FN(D53_AD21),
861 PINMUX_GPIO(GPIO_FN_D52_AD20, D52_AD20_MARK), 865 GPIO_FN(D52_AD20),
862 PINMUX_GPIO(GPIO_FN_D51_AD19, D51_AD19_MARK), 866 GPIO_FN(D51_AD19),
863 PINMUX_GPIO(GPIO_FN_D50_AD18, D50_AD18_MARK), 867 GPIO_FN(D50_AD18),
864 PINMUX_GPIO(GPIO_FN_D49_AD17_DB5, D49_AD17_DB5_MARK), 868 GPIO_FN(D49_AD17_DB5),
865 PINMUX_GPIO(GPIO_FN_D48_AD16_DB4, D48_AD16_DB4_MARK), 869 GPIO_FN(D48_AD16_DB4),
866 PINMUX_GPIO(GPIO_FN_D47_AD15_DB3, D47_AD15_DB3_MARK), 870 GPIO_FN(D47_AD15_DB3),
867 PINMUX_GPIO(GPIO_FN_D46_AD14_DB2, D46_AD14_DB2_MARK), 871 GPIO_FN(D46_AD14_DB2),
868 PINMUX_GPIO(GPIO_FN_D45_AD13_DB1, D45_AD13_DB1_MARK), 872 GPIO_FN(D45_AD13_DB1),
869 PINMUX_GPIO(GPIO_FN_D44_AD12_DB0, D44_AD12_DB0_MARK), 873 GPIO_FN(D44_AD12_DB0),
870 PINMUX_GPIO(GPIO_FN_D43_AD11_DG5, D43_AD11_DG5_MARK), 874 GPIO_FN(D43_AD11_DG5),
871 PINMUX_GPIO(GPIO_FN_D42_AD10_DG4, D42_AD10_DG4_MARK), 875 GPIO_FN(D42_AD10_DG4),
872 PINMUX_GPIO(GPIO_FN_D41_AD9_DG3, D41_AD9_DG3_MARK), 876 GPIO_FN(D41_AD9_DG3),
873 PINMUX_GPIO(GPIO_FN_D40_AD8_DG2, D40_AD8_DG2_MARK), 877 GPIO_FN(D40_AD8_DG2),
874 PINMUX_GPIO(GPIO_FN_D39_AD7_DG1, D39_AD7_DG1_MARK), 878 GPIO_FN(D39_AD7_DG1),
875 PINMUX_GPIO(GPIO_FN_D38_AD6_DG0, D38_AD6_DG0_MARK), 879 GPIO_FN(D38_AD6_DG0),
876 PINMUX_GPIO(GPIO_FN_D37_AD5_DR5, D37_AD5_DR5_MARK), 880 GPIO_FN(D37_AD5_DR5),
877 PINMUX_GPIO(GPIO_FN_D36_AD4_DR4, D36_AD4_DR4_MARK), 881 GPIO_FN(D36_AD4_DR4),
878 PINMUX_GPIO(GPIO_FN_D35_AD3_DR3, D35_AD3_DR3_MARK), 882 GPIO_FN(D35_AD3_DR3),
879 PINMUX_GPIO(GPIO_FN_D34_AD2_DR2, D34_AD2_DR2_MARK), 883 GPIO_FN(D34_AD2_DR2),
880 PINMUX_GPIO(GPIO_FN_D33_AD1_DR1, D33_AD1_DR1_MARK), 884 GPIO_FN(D33_AD1_DR1),
881 PINMUX_GPIO(GPIO_FN_D32_AD0_DR0, D32_AD0_DR0_MARK), 885 GPIO_FN(D32_AD0_DR0),
882 PINMUX_GPIO(GPIO_FN_REQ1, REQ1_MARK), 886 GPIO_FN(REQ1),
883 PINMUX_GPIO(GPIO_FN_REQ2, REQ2_MARK), 887 GPIO_FN(REQ2),
884 PINMUX_GPIO(GPIO_FN_REQ3, REQ3_MARK), 888 GPIO_FN(REQ3),
885 PINMUX_GPIO(GPIO_FN_GNT1, GNT1_MARK), 889 GPIO_FN(GNT1),
886 PINMUX_GPIO(GPIO_FN_GNT2, GNT2_MARK), 890 GPIO_FN(GNT2),
887 PINMUX_GPIO(GPIO_FN_GNT3, GNT3_MARK), 891 GPIO_FN(GNT3),
888 PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), 892 GPIO_FN(MMCCLK),
889 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 893 GPIO_FN(D31),
890 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 894 GPIO_FN(D30),
891 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 895 GPIO_FN(D29),
892 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 896 GPIO_FN(D28),
893 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 897 GPIO_FN(D27),
894 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 898 GPIO_FN(D26),
895 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 899 GPIO_FN(D25),
896 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 900 GPIO_FN(D24),
897 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 901 GPIO_FN(D23),
898 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 902 GPIO_FN(D22),
899 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 903 GPIO_FN(D21),
900 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 904 GPIO_FN(D20),
901 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 905 GPIO_FN(D19),
902 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 906 GPIO_FN(D18),
903 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 907 GPIO_FN(D17),
904 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 908 GPIO_FN(D16),
905 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), 909 GPIO_FN(SCIF1_SCK),
906 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), 910 GPIO_FN(SCIF1_RXD),
907 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), 911 GPIO_FN(SCIF1_TXD),
908 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), 912 GPIO_FN(SCIF0_CTS),
909 PINMUX_GPIO(GPIO_FN_INTD, INTD_MARK), 913 GPIO_FN(INTD),
910 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 914 GPIO_FN(FCE),
911 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), 915 GPIO_FN(SCIF0_RTS),
912 PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), 916 GPIO_FN(HSPI_CS),
913 PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), 917 GPIO_FN(FSE),
914 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), 918 GPIO_FN(SCIF0_SCK),
915 PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), 919 GPIO_FN(HSPI_CLK),
916 PINMUX_GPIO(GPIO_FN_FRE, FRE_MARK), 920 GPIO_FN(FRE),
917 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), 921 GPIO_FN(SCIF0_RXD),
918 PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), 922 GPIO_FN(HSPI_RX),
919 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 923 GPIO_FN(FRB),
920 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), 924 GPIO_FN(SCIF0_TXD),
921 PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), 925 GPIO_FN(HSPI_TX),
922 PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), 926 GPIO_FN(FWE),
923 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), 927 GPIO_FN(SCIF5_TXD),
924 PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), 928 GPIO_FN(HAC1_SYNC),
925 PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), 929 GPIO_FN(SSI1_WS),
926 PINMUX_GPIO(GPIO_FN_SIOF_TXD_PJ, SIOF_TXD_PJ_MARK), 930 GPIO_FN(SIOF_TXD_PJ),
927 PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), 931 GPIO_FN(HAC0_SDOUT),
928 PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), 932 GPIO_FN(SSI0_SDATA),
929 PINMUX_GPIO(GPIO_FN_SIOF_RXD_PJ, SIOF_RXD_PJ_MARK), 933 GPIO_FN(SIOF_RXD_PJ),
930 PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), 934 GPIO_FN(HAC0_SDIN),
931 PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), 935 GPIO_FN(SSI0_SCK),
932 PINMUX_GPIO(GPIO_FN_SIOF_SYNC_PJ, SIOF_SYNC_PJ_MARK), 936 GPIO_FN(SIOF_SYNC_PJ),
933 PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), 937 GPIO_FN(HAC0_SYNC),
934 PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), 938 GPIO_FN(SSI0_WS),
935 PINMUX_GPIO(GPIO_FN_SIOF_MCLK_PJ, SIOF_MCLK_PJ_MARK), 939 GPIO_FN(SIOF_MCLK_PJ),
936 PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), 940 GPIO_FN(HAC_RES),
937 PINMUX_GPIO(GPIO_FN_SIOF_SCK_PJ, SIOF_SCK_PJ_MARK), 941 GPIO_FN(SIOF_SCK_PJ),
938 PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), 942 GPIO_FN(HAC0_BITCLK),
939 PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), 943 GPIO_FN(SSI0_CLK),
940 PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), 944 GPIO_FN(HAC1_BITCLK),
941 PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), 945 GPIO_FN(SSI1_CLK),
942 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), 946 GPIO_FN(TCLK),
943 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 947 GPIO_FN(IOIS16),
944 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 948 GPIO_FN(STATUS0),
945 PINMUX_GPIO(GPIO_FN_DRAK0_PK3, DRAK0_PK3_MARK), 949 GPIO_FN(DRAK0_PK3),
946 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), 950 GPIO_FN(STATUS1),
947 PINMUX_GPIO(GPIO_FN_DRAK1_PK2, DRAK1_PK2_MARK), 951 GPIO_FN(DRAK1_PK2),
948 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), 952 GPIO_FN(DACK2),
949 PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), 953 GPIO_FN(SCIF2_TXD),
950 PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), 954 GPIO_FN(MMCCMD),
951 PINMUX_GPIO(GPIO_FN_SIOF_TXD_PK, SIOF_TXD_PK_MARK), 955 GPIO_FN(SIOF_TXD_PK),
952 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), 956 GPIO_FN(DACK3),
953 PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), 957 GPIO_FN(SCIF2_SCK),
954 PINMUX_GPIO(GPIO_FN_MMCDAT, MMCDAT_MARK), 958 GPIO_FN(MMCDAT),
955 PINMUX_GPIO(GPIO_FN_SIOF_SCK_PK, SIOF_SCK_PK_MARK), 959 GPIO_FN(SIOF_SCK_PK),
956 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 960 GPIO_FN(DREQ0),
957 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 961 GPIO_FN(DREQ1),
958 PINMUX_GPIO(GPIO_FN_DRAK0_PK1, DRAK0_PK1_MARK), 962 GPIO_FN(DRAK0_PK1),
959 PINMUX_GPIO(GPIO_FN_DRAK1_PK0, DRAK1_PK0_MARK), 963 GPIO_FN(DRAK1_PK0),
960 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), 964 GPIO_FN(DREQ2),
961 PINMUX_GPIO(GPIO_FN_INTB, INTB_MARK), 965 GPIO_FN(INTB),
962 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), 966 GPIO_FN(DREQ3),
963 PINMUX_GPIO(GPIO_FN_INTC, INTC_MARK), 967 GPIO_FN(INTC),
964 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), 968 GPIO_FN(DRAK2),
965 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 969 GPIO_FN(CE2A),
966 PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), 970 GPIO_FN(IRL4),
967 PINMUX_GPIO(GPIO_FN_FD4, FD4_MARK), 971 GPIO_FN(FD4),
968 PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), 972 GPIO_FN(IRL5),
969 PINMUX_GPIO(GPIO_FN_FD5, FD5_MARK), 973 GPIO_FN(FD5),
970 PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), 974 GPIO_FN(IRL6),
971 PINMUX_GPIO(GPIO_FN_FD6, FD6_MARK), 975 GPIO_FN(FD6),
972 PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), 976 GPIO_FN(IRL7),
973 PINMUX_GPIO(GPIO_FN_FD7, FD7_MARK), 977 GPIO_FN(FD7),
974 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), 978 GPIO_FN(DRAK3),
975 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 979 GPIO_FN(CE2B),
976 PINMUX_GPIO(GPIO_FN_BREQ_BSACK, BREQ_BSACK_MARK), 980 GPIO_FN(BREQ_BSACK),
977 PINMUX_GPIO(GPIO_FN_BACK_BSREQ, BACK_BSREQ_MARK), 981 GPIO_FN(BACK_BSREQ),
978 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), 982 GPIO_FN(SCIF5_RXD),
979 PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), 983 GPIO_FN(HAC1_SDIN),
980 PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), 984 GPIO_FN(SSI1_SCK),
981 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), 985 GPIO_FN(SCIF5_SCK),
982 PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), 986 GPIO_FN(HAC1_SDOUT),
983 PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), 987 GPIO_FN(SSI1_SDATA),
984 PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), 988 GPIO_FN(SCIF3_TXD),
985 PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), 989 GPIO_FN(FCLE),
986 PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), 990 GPIO_FN(SCIF3_RXD),
987 PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), 991 GPIO_FN(FALE),
988 PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), 992 GPIO_FN(SCIF3_SCK),
989 PINMUX_GPIO(GPIO_FN_FD0, FD0_MARK), 993 GPIO_FN(FD0),
990 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), 994 GPIO_FN(SCIF4_TXD),
991 PINMUX_GPIO(GPIO_FN_FD1, FD1_MARK), 995 GPIO_FN(FD1),
992 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), 996 GPIO_FN(SCIF4_RXD),
993 PINMUX_GPIO(GPIO_FN_FD2, FD2_MARK), 997 GPIO_FN(FD2),
994 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), 998 GPIO_FN(SCIF4_SCK),
995 PINMUX_GPIO(GPIO_FN_FD3, FD3_MARK), 999 GPIO_FN(FD3),
996 PINMUX_GPIO(GPIO_FN_DEVSEL_DCLKOUT, DEVSEL_DCLKOUT_MARK), 1000 GPIO_FN(DEVSEL_DCLKOUT),
997 PINMUX_GPIO(GPIO_FN_STOP_CDE, STOP_CDE_MARK), 1001 GPIO_FN(STOP_CDE),
998 PINMUX_GPIO(GPIO_FN_LOCK_ODDF, LOCK_ODDF_MARK), 1002 GPIO_FN(LOCK_ODDF),
999 PINMUX_GPIO(GPIO_FN_TRDY_DISPL, TRDY_DISPL_MARK), 1003 GPIO_FN(TRDY_DISPL),
1000 PINMUX_GPIO(GPIO_FN_IRDY_HSYNC, IRDY_HSYNC_MARK), 1004 GPIO_FN(IRDY_HSYNC),
1001 PINMUX_GPIO(GPIO_FN_PCIFRAME_VSYNC, PCIFRAME_VSYNC_MARK), 1005 GPIO_FN(PCIFRAME_VSYNC),
1002 PINMUX_GPIO(GPIO_FN_INTA, INTA_MARK), 1006 GPIO_FN(INTA),
1003 PINMUX_GPIO(GPIO_FN_GNT0_GNTIN, GNT0_GNTIN_MARK), 1007 GPIO_FN(GNT0_GNTIN),
1004 PINMUX_GPIO(GPIO_FN_REQ0_REQOUT, REQ0_REQOUT_MARK), 1008 GPIO_FN(REQ0_REQOUT),
1005 PINMUX_GPIO(GPIO_FN_PERR, PERR_MARK), 1009 GPIO_FN(PERR),
1006 PINMUX_GPIO(GPIO_FN_SERR, SERR_MARK), 1010 GPIO_FN(SERR),
1007 PINMUX_GPIO(GPIO_FN_WE7_CBE3, WE7_CBE3_MARK), 1011 GPIO_FN(WE7_CBE3),
1008 PINMUX_GPIO(GPIO_FN_WE6_CBE2, WE6_CBE2_MARK), 1012 GPIO_FN(WE6_CBE2),
1009 PINMUX_GPIO(GPIO_FN_WE5_CBE1, WE5_CBE1_MARK), 1013 GPIO_FN(WE5_CBE1),
1010 PINMUX_GPIO(GPIO_FN_WE4_CBE0, WE4_CBE0_MARK), 1014 GPIO_FN(WE4_CBE0),
1011 PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), 1015 GPIO_FN(SCIF2_RXD),
1012 PINMUX_GPIO(GPIO_FN_SIOF_RXD, SIOF_RXD_MARK), 1016 GPIO_FN(SIOF_RXD),
1013 PINMUX_GPIO(GPIO_FN_MRESETOUT, MRESETOUT_MARK), 1017 GPIO_FN(MRESETOUT),
1014 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), 1018 GPIO_FN(IRQOUT),
1015}; 1019};
1016 1020
1017static struct pinmux_cfg_reg pinmux_config_regs[] = { 1021static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1018 { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) { 1022 { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) {
1019 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, 1023 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
1020 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, 1024 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -1214,7 +1218,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1214 {} 1218 {}
1215}; 1219};
1216 1220
1217static struct pinmux_data_reg pinmux_data_regs[] = { 1221static const struct pinmux_data_reg pinmux_data_regs[] = {
1218 { PINMUX_DATA_REG("PADR", 0xffe70020, 8) { 1222 { PINMUX_DATA_REG("PADR", 0xffe70020, 8) {
1219 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 1223 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
1220 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } 1224 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
@@ -1282,20 +1286,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1282 { }, 1286 { },
1283}; 1287};
1284 1288
1285struct sh_pfc_soc_info sh7785_pinmux_info = { 1289const struct sh_pfc_soc_info sh7785_pinmux_info = {
1286 .name = "sh7785_pfc", 1290 .name = "sh7785_pfc",
1287 .reserved_id = PINMUX_RESERVED,
1288 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1289 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 1291 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1290 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 1292 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1291 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 1293 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1292 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1293 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1294 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1294 1295
1295 .first_gpio = GPIO_PA7, 1296 .pins = pinmux_pins,
1296 .last_gpio = GPIO_FN_IRQOUT, 1297 .nr_pins = ARRAY_SIZE(pinmux_pins),
1298 .func_gpios = pinmux_func_gpios,
1299 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1297 1300
1298 .gpios = pinmux_gpios,
1299 .cfg_regs = pinmux_config_regs, 1301 .cfg_regs = pinmux_config_regs,
1300 .data_regs = pinmux_data_regs, 1302 .data_regs = pinmux_data_regs,
1301 1303
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index 1e18b58f9e5f..8ae0e32844e9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -191,7 +191,7 @@ enum {
191 PINMUX_MARK_END, 191 PINMUX_MARK_END,
192}; 192};
193 193
194static pinmux_enum_t pinmux_data[] = { 194static const pinmux_enum_t pinmux_data[] = {
195 195
196 /* PA GPIO */ 196 /* PA GPIO */
197 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), 197 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -427,7 +427,7 @@ static pinmux_enum_t pinmux_data[] = {
427 PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN), 427 PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
428}; 428};
429 429
430static struct pinmux_gpio pinmux_gpios[] = { 430static struct sh_pfc_pin pinmux_pins[] = {
431 /* PA */ 431 /* PA */
432 PINMUX_GPIO(GPIO_PA7, PA7_DATA), 432 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
433 PINMUX_GPIO(GPIO_PA6, PA6_DATA), 433 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -505,147 +505,151 @@ static struct pinmux_gpio pinmux_gpios[] = {
505 PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), 505 PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
506 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), 506 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
507 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), 507 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
508};
509
510#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
508 511
512static const struct pinmux_func pinmux_func_gpios[] = {
509 /* FN */ 513 /* FN */
510 PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK), 514 GPIO_FN(CDE),
511 PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK), 515 GPIO_FN(ETH_MAGIC),
512 PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK), 516 GPIO_FN(DISP),
513 PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK), 517 GPIO_FN(ETH_LINK),
514 PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK), 518 GPIO_FN(DR5),
515 PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK), 519 GPIO_FN(ETH_TX_ER),
516 PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK), 520 GPIO_FN(DR4),
517 PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK), 521 GPIO_FN(ETH_TX_EN),
518 PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK), 522 GPIO_FN(DR3),
519 PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK), 523 GPIO_FN(ETH_TXD3),
520 PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK), 524 GPIO_FN(DR2),
521 PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK), 525 GPIO_FN(ETH_TXD2),
522 PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK), 526 GPIO_FN(DR1),
523 PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK), 527 GPIO_FN(ETH_TXD1),
524 PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK), 528 GPIO_FN(DR0),
525 PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK), 529 GPIO_FN(ETH_TXD0),
526 PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK), 530 GPIO_FN(VSYNC),
527 PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), 531 GPIO_FN(HSPI_CLK),
528 PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK), 532 GPIO_FN(ODDF),
529 PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), 533 GPIO_FN(HSPI_CS),
530 PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK), 534 GPIO_FN(DG5),
531 PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK), 535 GPIO_FN(ETH_MDIO),
532 PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK), 536 GPIO_FN(DG4),
533 PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK), 537 GPIO_FN(ETH_RX_CLK),
534 PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK), 538 GPIO_FN(DG3),
535 PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK), 539 GPIO_FN(ETH_MDC),
536 PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK), 540 GPIO_FN(DG2),
537 PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK), 541 GPIO_FN(ETH_COL),
538 PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK), 542 GPIO_FN(DG1),
539 PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK), 543 GPIO_FN(ETH_TX_CLK),
540 PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK), 544 GPIO_FN(DG0),
541 PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK), 545 GPIO_FN(ETH_CRS),
542 PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK), 546 GPIO_FN(DCLKIN),
543 PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), 547 GPIO_FN(HSPI_RX),
544 PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK), 548 GPIO_FN(HSYNC),
545 PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), 549 GPIO_FN(HSPI_TX),
546 PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK), 550 GPIO_FN(DB5),
547 PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK), 551 GPIO_FN(ETH_RXD3),
548 PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK), 552 GPIO_FN(DB4),
549 PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK), 553 GPIO_FN(ETH_RXD2),
550 PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK), 554 GPIO_FN(DB3),
551 PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK), 555 GPIO_FN(ETH_RXD1),
552 PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK), 556 GPIO_FN(DB2),
553 PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK), 557 GPIO_FN(ETH_RXD0),
554 PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK), 558 GPIO_FN(DB1),
555 PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK), 559 GPIO_FN(ETH_RX_DV),
556 PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK), 560 GPIO_FN(DB0),
557 PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK), 561 GPIO_FN(ETH_RX_ER),
558 PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK), 562 GPIO_FN(DCLKOUT),
559 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), 563 GPIO_FN(SCIF1_SCK),
560 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), 564 GPIO_FN(SCIF1_RXD),
561 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), 565 GPIO_FN(SCIF1_TXD),
562 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 566 GPIO_FN(DACK1),
563 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), 567 GPIO_FN(BACK),
564 PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), 568 GPIO_FN(FALE),
565 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 569 GPIO_FN(DACK0),
566 PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), 570 GPIO_FN(FCLE),
567 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 571 GPIO_FN(DREQ1),
568 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), 572 GPIO_FN(BREQ),
569 PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK), 573 GPIO_FN(USB_OVC1),
570 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 574 GPIO_FN(DREQ0),
571 PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK), 575 GPIO_FN(USB_OVC0),
572 PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK), 576 GPIO_FN(USB_PENC1),
573 PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK), 577 GPIO_FN(USB_PENC0),
574 PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), 578 GPIO_FN(HAC1_SDOUT),
575 PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), 579 GPIO_FN(SSI1_SDATA),
576 PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK), 580 GPIO_FN(SDIF1CMD),
577 PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), 581 GPIO_FN(HAC1_SDIN),
578 PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), 582 GPIO_FN(SSI1_SCK),
579 PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK), 583 GPIO_FN(SDIF1CD),
580 PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), 584 GPIO_FN(HAC1_SYNC),
581 PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), 585 GPIO_FN(SSI1_WS),
582 PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK), 586 GPIO_FN(SDIF1WP),
583 PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), 587 GPIO_FN(HAC1_BITCLK),
584 PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), 588 GPIO_FN(SSI1_CLK),
585 PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK), 589 GPIO_FN(SDIF1CLK),
586 PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), 590 GPIO_FN(HAC0_SDOUT),
587 PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), 591 GPIO_FN(SSI0_SDATA),
588 PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK), 592 GPIO_FN(SDIF1D3),
589 PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), 593 GPIO_FN(HAC0_SDIN),
590 PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), 594 GPIO_FN(SSI0_SCK),
591 PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK), 595 GPIO_FN(SDIF1D2),
592 PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), 596 GPIO_FN(HAC0_SYNC),
593 PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), 597 GPIO_FN(SSI0_WS),
594 PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK), 598 GPIO_FN(SDIF1D1),
595 PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), 599 GPIO_FN(HAC0_BITCLK),
596 PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), 600 GPIO_FN(SSI0_CLK),
597 PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK), 601 GPIO_FN(SDIF1D0),
598 PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), 602 GPIO_FN(SCIF3_SCK),
599 PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK), 603 GPIO_FN(SSI2_SDATA),
600 PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), 604 GPIO_FN(SCIF3_RXD),
601 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), 605 GPIO_FN(TCLK),
602 PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK), 606 GPIO_FN(SSI2_SCK),
603 PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), 607 GPIO_FN(SCIF3_TXD),
604 PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), 608 GPIO_FN(HAC_RES),
605 PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK), 609 GPIO_FN(SSI2_WS),
606 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), 610 GPIO_FN(DACK3),
607 PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK), 611 GPIO_FN(SDIF0CMD),
608 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), 612 GPIO_FN(DACK2),
609 PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK), 613 GPIO_FN(SDIF0CD),
610 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), 614 GPIO_FN(DREQ3),
611 PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK), 615 GPIO_FN(SDIF0WP),
612 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), 616 GPIO_FN(SCIF0_CTS),
613 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), 617 GPIO_FN(DREQ2),
614 PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK), 618 GPIO_FN(SDIF0CLK),
615 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), 619 GPIO_FN(SCIF0_RTS),
616 PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), 620 GPIO_FN(IRL7),
617 PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK), 621 GPIO_FN(SDIF0D3),
618 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), 622 GPIO_FN(SCIF0_SCK),
619 PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), 623 GPIO_FN(IRL6),
620 PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK), 624 GPIO_FN(SDIF0D2),
621 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), 625 GPIO_FN(SCIF0_RXD),
622 PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), 626 GPIO_FN(IRL5),
623 PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK), 627 GPIO_FN(SDIF0D1),
624 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), 628 GPIO_FN(SCIF0_TXD),
625 PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), 629 GPIO_FN(IRL4),
626 PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK), 630 GPIO_FN(SDIF0D0),
627 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), 631 GPIO_FN(SCIF5_SCK),
628 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 632 GPIO_FN(FRB),
629 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), 633 GPIO_FN(SCIF5_RXD),
630 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 634 GPIO_FN(IOIS16),
631 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), 635 GPIO_FN(SCIF5_TXD),
632 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 636 GPIO_FN(CE2B),
633 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), 637 GPIO_FN(DRAK3),
634 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 638 GPIO_FN(CE2A),
635 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), 639 GPIO_FN(SCIF4_SCK),
636 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), 640 GPIO_FN(DRAK2),
637 PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK), 641 GPIO_FN(SSI3_WS),
638 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), 642 GPIO_FN(SCIF4_RXD),
639 PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), 643 GPIO_FN(DRAK1),
640 PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK), 644 GPIO_FN(SSI3_SDATA),
641 PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK), 645 GPIO_FN(FSTATUS),
642 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), 646 GPIO_FN(SCIF4_TXD),
643 PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), 647 GPIO_FN(DRAK0),
644 PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK), 648 GPIO_FN(SSI3_SCK),
645 PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), 649 GPIO_FN(FSE),
646}; 650};
647 651
648static struct pinmux_cfg_reg pinmux_config_regs[] = { 652static const struct pinmux_cfg_reg pinmux_config_regs[] = {
649 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) { 653 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
650 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, 654 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
651 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, 655 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -775,7 +779,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
775 {} 779 {}
776}; 780};
777 781
778static struct pinmux_data_reg pinmux_data_regs[] = { 782static const struct pinmux_data_reg pinmux_data_regs[] = {
779 { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) { 783 { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
780 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 784 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
781 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } 785 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
@@ -815,20 +819,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
815 { }, 819 { },
816}; 820};
817 821
818struct sh_pfc_soc_info sh7786_pinmux_info = { 822const struct sh_pfc_soc_info sh7786_pinmux_info = {
819 .name = "sh7786_pfc", 823 .name = "sh7786_pfc",
820 .reserved_id = PINMUX_RESERVED,
821 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
822 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 824 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
823 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 825 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
824 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 826 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
825 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
826 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 827 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
827 828
828 .first_gpio = GPIO_PA7, 829 .pins = pinmux_pins,
829 .last_gpio = GPIO_FN_IRL4, 830 .nr_pins = ARRAY_SIZE(pinmux_pins),
831 .func_gpios = pinmux_func_gpios,
832 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
830 833
831 .gpios = pinmux_gpios,
832 .cfg_regs = pinmux_config_regs, 834 .cfg_regs = pinmux_config_regs,
833 .data_regs = pinmux_data_regs, 835 .data_regs = pinmux_data_regs,
834 836
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index ccf6918b03c6..6594c8c48747 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -147,7 +147,7 @@ enum {
147 PINMUX_MARK_END, 147 PINMUX_MARK_END,
148}; 148};
149 149
150static pinmux_enum_t shx3_pinmux_data[] = { 150static const pinmux_enum_t shx3_pinmux_data[] = {
151 151
152 /* PA GPIO */ 152 /* PA GPIO */
153 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), 153 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -306,7 +306,7 @@ static pinmux_enum_t shx3_pinmux_data[] = {
306 PINMUX_DATA(IRQOUT_MARK, PH0_FN), 306 PINMUX_DATA(IRQOUT_MARK, PH0_FN),
307}; 307};
308 308
309static struct pinmux_gpio shx3_pinmux_gpios[] = { 309static struct sh_pfc_pin shx3_pinmux_pins[] = {
310 /* PA */ 310 /* PA */
311 PINMUX_GPIO(GPIO_PA7, PA7_DATA), 311 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
312 PINMUX_GPIO(GPIO_PA6, PA6_DATA), 312 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -384,73 +384,77 @@ static struct pinmux_gpio shx3_pinmux_gpios[] = {
384 PINMUX_GPIO(GPIO_PH2, PH2_DATA), 384 PINMUX_GPIO(GPIO_PH2, PH2_DATA),
385 PINMUX_GPIO(GPIO_PH1, PH1_DATA), 385 PINMUX_GPIO(GPIO_PH1, PH1_DATA),
386 PINMUX_GPIO(GPIO_PH0, PH0_DATA), 386 PINMUX_GPIO(GPIO_PH0, PH0_DATA),
387};
388
389#define PINMUX_FN_BASE ARRAY_SIZE(shx3_pinmux_pins)
387 390
391static const struct pinmux_func shx3_pinmux_func_gpios[] = {
388 /* FN */ 392 /* FN */
389 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 393 GPIO_FN(D31),
390 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 394 GPIO_FN(D30),
391 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 395 GPIO_FN(D29),
392 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 396 GPIO_FN(D28),
393 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 397 GPIO_FN(D27),
394 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 398 GPIO_FN(D26),
395 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 399 GPIO_FN(D25),
396 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 400 GPIO_FN(D24),
397 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 401 GPIO_FN(D23),
398 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 402 GPIO_FN(D22),
399 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 403 GPIO_FN(D21),
400 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 404 GPIO_FN(D20),
401 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 405 GPIO_FN(D19),
402 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 406 GPIO_FN(D18),
403 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 407 GPIO_FN(D17),
404 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 408 GPIO_FN(D16),
405 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), 409 GPIO_FN(BACK),
406 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), 410 GPIO_FN(BREQ),
407 PINMUX_GPIO(GPIO_FN_WE3, WE3_MARK), 411 GPIO_FN(WE3),
408 PINMUX_GPIO(GPIO_FN_WE2, WE2_MARK), 412 GPIO_FN(WE2),
409 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), 413 GPIO_FN(CS6),
410 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), 414 GPIO_FN(CS5),
411 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), 415 GPIO_FN(CS4),
412 PINMUX_GPIO(GPIO_FN_CLKOUTENB, CLKOUTENB_MARK), 416 GPIO_FN(CLKOUTENB),
413 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), 417 GPIO_FN(DACK3),
414 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), 418 GPIO_FN(DACK2),
415 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 419 GPIO_FN(DACK1),
416 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 420 GPIO_FN(DACK0),
417 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), 421 GPIO_FN(DREQ3),
418 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), 422 GPIO_FN(DREQ2),
419 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 423 GPIO_FN(DREQ1),
420 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 424 GPIO_FN(DREQ0),
421 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), 425 GPIO_FN(IRQ3),
422 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), 426 GPIO_FN(IRQ2),
423 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), 427 GPIO_FN(IRQ1),
424 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), 428 GPIO_FN(IRQ0),
425 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), 429 GPIO_FN(DRAK3),
426 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), 430 GPIO_FN(DRAK2),
427 PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), 431 GPIO_FN(DRAK1),
428 PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), 432 GPIO_FN(DRAK0),
429 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), 433 GPIO_FN(SCK3),
430 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 434 GPIO_FN(SCK2),
431 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), 435 GPIO_FN(SCK1),
432 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), 436 GPIO_FN(SCK0),
433 PINMUX_GPIO(GPIO_FN_IRL3, IRL3_MARK), 437 GPIO_FN(IRL3),
434 PINMUX_GPIO(GPIO_FN_IRL2, IRL2_MARK), 438 GPIO_FN(IRL2),
435 PINMUX_GPIO(GPIO_FN_IRL1, IRL1_MARK), 439 GPIO_FN(IRL1),
436 PINMUX_GPIO(GPIO_FN_IRL0, IRL0_MARK), 440 GPIO_FN(IRL0),
437 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 441 GPIO_FN(TXD3),
438 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 442 GPIO_FN(TXD2),
439 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), 443 GPIO_FN(TXD1),
440 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), 444 GPIO_FN(TXD0),
441 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 445 GPIO_FN(RXD3),
442 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 446 GPIO_FN(RXD2),
443 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), 447 GPIO_FN(RXD1),
444 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), 448 GPIO_FN(RXD0),
445 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 449 GPIO_FN(CE2B),
446 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 450 GPIO_FN(CE2A),
447 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 451 GPIO_FN(IOIS16),
448 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), 452 GPIO_FN(STATUS1),
449 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 453 GPIO_FN(STATUS0),
450 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), 454 GPIO_FN(IRQOUT),
451}; 455};
452 456
453static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { 457static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
454 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) { 458 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
455 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, 459 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
456 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, 460 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -526,7 +530,7 @@ static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
526 { }, 530 { },
527}; 531};
528 532
529static struct pinmux_data_reg shx3_pinmux_data_regs[] = { 533static const struct pinmux_data_reg shx3_pinmux_data_regs[] = {
530 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) { 534 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
531 0, 0, 0, 0, 0, 0, 0, 0, 535 0, 0, 0, 0, 0, 0, 0, 0,
532 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 536 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
@@ -562,19 +566,17 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
562 { }, 566 { },
563}; 567};
564 568
565struct sh_pfc_soc_info shx3_pinmux_info = { 569const struct sh_pfc_soc_info shx3_pinmux_info = {
566 .name = "shx3_pfc", 570 .name = "shx3_pfc",
567 .reserved_id = PINMUX_RESERVED,
568 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
569 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 571 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
570 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, 572 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
571 PINMUX_INPUT_PULLUP_END }, 573 PINMUX_INPUT_PULLUP_END },
572 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 574 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
573 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
574 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 575 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
575 .first_gpio = GPIO_PA7, 576 .pins = shx3_pinmux_pins,
576 .last_gpio = GPIO_FN_STATUS0, 577 .nr_pins = ARRAY_SIZE(shx3_pinmux_pins),
577 .gpios = shx3_pinmux_gpios, 578 .func_gpios = shx3_pinmux_func_gpios,
579 .nr_func_gpios = ARRAY_SIZE(shx3_pinmux_func_gpios),
578 .gpio_data = shx3_pinmux_data, 580 .gpio_data = shx3_pinmux_data,
579 .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data), 581 .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
580 .cfg_regs = shx3_pinmux_config_regs, 582 .cfg_regs = shx3_pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 11e0e1374d65..aef268bc17ba 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -9,7 +9,6 @@
9 */ 9 */
10 10
11#define DRV_NAME "sh-pfc" 11#define DRV_NAME "sh-pfc"
12#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt
13 12
14#include <linux/device.h> 13#include <linux/device.h>
15#include <linux/err.h> 14#include <linux/err.h>
@@ -24,25 +23,28 @@
24#include <linux/spinlock.h> 23#include <linux/spinlock.h>
25 24
26#include "core.h" 25#include "core.h"
26#include "../core.h"
27#include "../pinconf.h"
28
29struct sh_pfc_pin_config {
30 u32 type;
31};
27 32
28struct sh_pfc_pinctrl { 33struct sh_pfc_pinctrl {
29 struct pinctrl_dev *pctl; 34 struct pinctrl_dev *pctl;
30 struct sh_pfc *pfc; 35 struct pinctrl_desc pctl_desc;
31
32 struct pinmux_gpio **functions;
33 unsigned int nr_functions;
34 36
35 struct pinctrl_pin_desc *pads; 37 struct sh_pfc *pfc;
36 unsigned int nr_pads;
37 38
38 spinlock_t lock; 39 struct pinctrl_pin_desc *pins;
40 struct sh_pfc_pin_config *configs;
39}; 41};
40 42
41static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) 43static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
42{ 44{
43 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 45 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
44 46
45 return pmx->nr_pads; 47 return pmx->pfc->info->nr_groups;
46} 48}
47 49
48static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, 50static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
@@ -50,16 +52,16 @@ static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
50{ 52{
51 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 53 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
52 54
53 return pmx->pads[selector].name; 55 return pmx->pfc->info->groups[selector].name;
54} 56}
55 57
56static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 58static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
57 const unsigned **pins, unsigned *num_pins) 59 const unsigned **pins, unsigned *num_pins)
58{ 60{
59 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 61 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
60 62
61 *pins = &pmx->pads[group].number; 63 *pins = pmx->pfc->info->groups[selector].pins;
62 *num_pins = 1; 64 *num_pins = pmx->pfc->info->groups[selector].nr_pins;
63 65
64 return 0; 66 return 0;
65} 67}
@@ -70,7 +72,7 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
70 seq_printf(s, "%s", DRV_NAME); 72 seq_printf(s, "%s", DRV_NAME);
71} 73}
72 74
73static struct pinctrl_ops sh_pfc_pinctrl_ops = { 75static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
74 .get_groups_count = sh_pfc_get_groups_count, 76 .get_groups_count = sh_pfc_get_groups_count,
75 .get_group_name = sh_pfc_get_group_name, 77 .get_group_name = sh_pfc_get_group_name,
76 .get_group_pins = sh_pfc_get_group_pins, 78 .get_group_pins = sh_pfc_get_group_pins,
@@ -81,7 +83,7 @@ static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
81{ 83{
82 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 84 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
83 85
84 return pmx->nr_functions; 86 return pmx->pfc->info->nr_functions;
85} 87}
86 88
87static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, 89static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
@@ -89,136 +91,102 @@ static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
89{ 91{
90 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 92 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
91 93
92 return pmx->functions[selector]->name; 94 return pmx->pfc->info->functions[selector].name;
93} 95}
94 96
95static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func, 97static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
98 unsigned selector,
96 const char * const **groups, 99 const char * const **groups,
97 unsigned * const num_groups) 100 unsigned * const num_groups)
98{ 101{
99 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 102 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
100 103
101 *groups = &pmx->functions[func]->name; 104 *groups = pmx->pfc->info->functions[selector].groups;
102 *num_groups = 1; 105 *num_groups = pmx->pfc->info->functions[selector].nr_groups;
103 106
104 return 0; 107 return 0;
105} 108}
106 109
107static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func, 110static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
108 unsigned group) 111 unsigned group)
109{ 112{
110 return 0; 113 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
111} 114 struct sh_pfc *pfc = pmx->pfc;
115 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
116 unsigned long flags;
117 unsigned int i;
118 int ret = 0;
112 119
113static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func, 120 spin_lock_irqsave(&pfc->lock, flags);
114 unsigned group)
115{
116}
117 121
118static int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset) 122 for (i = 0; i < grp->nr_pins; ++i) {
119{ 123 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
120 if (sh_pfc_config_gpio(pfc, offset, 124 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
121 PINMUX_TYPE_FUNCTION,
122 GPIO_CFG_DRYRUN) != 0)
123 return -EINVAL;
124 125
125 if (sh_pfc_config_gpio(pfc, offset, 126 if (cfg->type != PINMUX_TYPE_NONE) {
126 PINMUX_TYPE_FUNCTION, 127 ret = -EBUSY;
127 GPIO_CFG_REQ) != 0) 128 goto done;
128 return -EINVAL; 129 }
130 }
129 131
130 return 0; 132 for (i = 0; i < grp->nr_pins; ++i) {
133 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
134 if (ret < 0)
135 break;
136 }
137
138done:
139 spin_unlock_irqrestore(&pfc->lock, flags);
140 return ret;
131} 141}
132 142
133static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, 143static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
134 int new_type) 144 unsigned group)
135{ 145{
146 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
147 struct sh_pfc *pfc = pmx->pfc;
148 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
136 unsigned long flags; 149 unsigned long flags;
137 int pinmux_type; 150 unsigned int i;
138 int ret = -EINVAL;
139 151
140 spin_lock_irqsave(&pfc->lock, flags); 152 spin_lock_irqsave(&pfc->lock, flags);
141 153
142 pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; 154 for (i = 0; i < grp->nr_pins; ++i) {
155 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
156 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
143 157
144 /* 158 cfg->type = PINMUX_TYPE_NONE;
145 * See if the present config needs to first be de-configured.
146 */
147 switch (pinmux_type) {
148 case PINMUX_TYPE_GPIO:
149 break;
150 case PINMUX_TYPE_OUTPUT:
151 case PINMUX_TYPE_INPUT:
152 case PINMUX_TYPE_INPUT_PULLUP:
153 case PINMUX_TYPE_INPUT_PULLDOWN:
154 sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
155 break;
156 default:
157 goto err;
158 } 159 }
159 160
160 /*
161 * Dry run
162 */
163 if (sh_pfc_config_gpio(pfc, offset, new_type,
164 GPIO_CFG_DRYRUN) != 0)
165 goto err;
166
167 /*
168 * Request
169 */
170 if (sh_pfc_config_gpio(pfc, offset, new_type,
171 GPIO_CFG_REQ) != 0)
172 goto err;
173
174 pfc->info->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
175 pfc->info->gpios[offset].flags |= new_type;
176
177 ret = 0;
178
179err:
180 spin_unlock_irqrestore(&pfc->lock, flags); 161 spin_unlock_irqrestore(&pfc->lock, flags);
181
182 return ret;
183} 162}
184 163
185
186static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, 164static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
187 struct pinctrl_gpio_range *range, 165 struct pinctrl_gpio_range *range,
188 unsigned offset) 166 unsigned offset)
189{ 167{
190 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 168 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
191 struct sh_pfc *pfc = pmx->pfc; 169 struct sh_pfc *pfc = pmx->pfc;
170 int idx = sh_pfc_get_pin_index(pfc, offset);
171 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
192 unsigned long flags; 172 unsigned long flags;
193 int ret, pinmux_type; 173 int ret;
194 174
195 spin_lock_irqsave(&pfc->lock, flags); 175 spin_lock_irqsave(&pfc->lock, flags);
196 176
197 pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; 177 if (cfg->type != PINMUX_TYPE_NONE) {
198 178 dev_err(pfc->dev,
199 switch (pinmux_type) { 179 "Pin %u is busy, can't configure it as GPIO.\n",
200 case PINMUX_TYPE_FUNCTION: 180 offset);
201 pr_notice_once("Use of GPIO API for function requests is " 181 ret = -EBUSY;
202 "deprecated, convert to pinctrl\n"); 182 goto done;
203 /* handle for now */
204 ret = sh_pfc_config_function(pfc, offset);
205 if (unlikely(ret < 0))
206 goto err;
207
208 break;
209 case PINMUX_TYPE_GPIO:
210 case PINMUX_TYPE_INPUT:
211 case PINMUX_TYPE_OUTPUT:
212 break;
213 default:
214 pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
215 ret = -ENOTSUPP;
216 goto err;
217 } 183 }
218 184
185 cfg->type = PINMUX_TYPE_GPIO;
186
219 ret = 0; 187 ret = 0;
220 188
221err: 189done:
222 spin_unlock_irqrestore(&pfc->lock, flags); 190 spin_unlock_irqrestore(&pfc->lock, flags);
223 191
224 return ret; 192 return ret;
@@ -230,15 +198,12 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
230{ 198{
231 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 199 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
232 struct sh_pfc *pfc = pmx->pfc; 200 struct sh_pfc *pfc = pmx->pfc;
201 int idx = sh_pfc_get_pin_index(pfc, offset);
202 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
233 unsigned long flags; 203 unsigned long flags;
234 int pinmux_type;
235 204
236 spin_lock_irqsave(&pfc->lock, flags); 205 spin_lock_irqsave(&pfc->lock, flags);
237 206 cfg->type = PINMUX_TYPE_NONE;
238 pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
239
240 sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
241
242 spin_unlock_irqrestore(&pfc->lock, flags); 207 spin_unlock_irqrestore(&pfc->lock, flags);
243} 208}
244 209
@@ -247,207 +212,242 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
247 unsigned offset, bool input) 212 unsigned offset, bool input)
248{ 213{
249 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 214 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
250 int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; 215 struct sh_pfc *pfc = pmx->pfc;
216 int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
217 int idx = sh_pfc_get_pin_index(pfc, offset);
218 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
219 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
220 unsigned long flags;
221 unsigned int dir;
222 int ret;
223
224 /* Check if the requested direction is supported by the pin. Not all SoC
225 * provide pin config data, so perform the check conditionally.
226 */
227 if (pin->configs) {
228 dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
229 if (!(pin->configs & dir))
230 return -EINVAL;
231 }
232
233 spin_lock_irqsave(&pfc->lock, flags);
234
235 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
236 if (ret < 0)
237 goto done;
238
239 cfg->type = new_type;
251 240
252 return sh_pfc_reconfig_pin(pmx->pfc, offset, type); 241done:
242 spin_unlock_irqrestore(&pfc->lock, flags);
243 return ret;
253} 244}
254 245
255static struct pinmux_ops sh_pfc_pinmux_ops = { 246static const struct pinmux_ops sh_pfc_pinmux_ops = {
256 .get_functions_count = sh_pfc_get_functions_count, 247 .get_functions_count = sh_pfc_get_functions_count,
257 .get_function_name = sh_pfc_get_function_name, 248 .get_function_name = sh_pfc_get_function_name,
258 .get_function_groups = sh_pfc_get_function_groups, 249 .get_function_groups = sh_pfc_get_function_groups,
259 .enable = sh_pfc_noop_enable, 250 .enable = sh_pfc_func_enable,
260 .disable = sh_pfc_noop_disable, 251 .disable = sh_pfc_func_disable,
261 .gpio_request_enable = sh_pfc_gpio_request_enable, 252 .gpio_request_enable = sh_pfc_gpio_request_enable,
262 .gpio_disable_free = sh_pfc_gpio_disable_free, 253 .gpio_disable_free = sh_pfc_gpio_disable_free,
263 .gpio_set_direction = sh_pfc_gpio_set_direction, 254 .gpio_set_direction = sh_pfc_gpio_set_direction,
264}; 255};
265 256
266static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, 257/* Check whether the requested parameter is supported for a pin. */
267 unsigned long *config) 258static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
259 enum pin_config_param param)
268{ 260{
269 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 261 int idx = sh_pfc_get_pin_index(pfc, _pin);
270 struct sh_pfc *pfc = pmx->pfc; 262 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
271 263
272 *config = pfc->info->gpios[pin].flags & PINMUX_FLAG_TYPE; 264 switch (param) {
265 case PIN_CONFIG_BIAS_DISABLE:
266 return true;
273 267
274 return 0; 268 case PIN_CONFIG_BIAS_PULL_UP:
275} 269 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
276 270
277static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, 271 case PIN_CONFIG_BIAS_PULL_DOWN:
278 unsigned long config) 272 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
279{
280 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
281
282 /* Validate the new type */
283 if (config >= PINMUX_FLAG_TYPE)
284 return -EINVAL;
285 273
286 return sh_pfc_reconfig_pin(pmx->pfc, pin, config); 274 default:
275 return false;
276 }
287} 277}
288 278
289static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev, 279static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
290 struct seq_file *s, unsigned pin) 280 unsigned long *config)
291{ 281{
292 const char *pinmux_type_str[] = { 282 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
293 [PINMUX_TYPE_NONE] = "none", 283 struct sh_pfc *pfc = pmx->pfc;
294 [PINMUX_TYPE_FUNCTION] = "function", 284 enum pin_config_param param = pinconf_to_config_param(*config);
295 [PINMUX_TYPE_GPIO] = "gpio", 285 unsigned long flags;
296 [PINMUX_TYPE_OUTPUT] = "output", 286 unsigned int bias;
297 [PINMUX_TYPE_INPUT] = "input",
298 [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up",
299 [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down",
300 };
301 unsigned long config;
302 int rc;
303
304 rc = sh_pfc_pinconf_get(pctldev, pin, &config);
305 if (unlikely(rc != 0))
306 return;
307
308 seq_printf(s, " %s", pinmux_type_str[config]);
309}
310 287
311static struct pinconf_ops sh_pfc_pinconf_ops = { 288 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
312 .pin_config_get = sh_pfc_pinconf_get, 289 return -ENOTSUPP;
313 .pin_config_set = sh_pfc_pinconf_set,
314 .pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
315};
316 290
317static struct pinctrl_gpio_range sh_pfc_gpio_range = { 291 switch (param) {
318 .name = DRV_NAME, 292 case PIN_CONFIG_BIAS_DISABLE:
319 .id = 0, 293 case PIN_CONFIG_BIAS_PULL_UP:
320}; 294 case PIN_CONFIG_BIAS_PULL_DOWN:
295 if (!pfc->info->ops || !pfc->info->ops->get_bias)
296 return -ENOTSUPP;
321 297
322static struct pinctrl_desc sh_pfc_pinctrl_desc = { 298 spin_lock_irqsave(&pfc->lock, flags);
323 .name = DRV_NAME, 299 bias = pfc->info->ops->get_bias(pfc, _pin);
324 .owner = THIS_MODULE, 300 spin_unlock_irqrestore(&pfc->lock, flags);
325 .pctlops = &sh_pfc_pinctrl_ops,
326 .pmxops = &sh_pfc_pinmux_ops,
327 .confops = &sh_pfc_pinconf_ops,
328};
329 301
330static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx, 302 if (bias != param)
331 struct pinmux_gpio *gpio, unsigned offset) 303 return -EINVAL;
332{
333 struct pinmux_data_reg *dummy;
334 unsigned long flags;
335 int bit;
336
337 gpio->flags &= ~PINMUX_FLAG_TYPE;
338 304
339 if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0) 305 *config = 0;
340 gpio->flags |= PINMUX_TYPE_GPIO; 306 break;
341 else {
342 gpio->flags |= PINMUX_TYPE_FUNCTION;
343 307
344 spin_lock_irqsave(&pmx->lock, flags); 308 default:
345 pmx->nr_functions++; 309 return -ENOTSUPP;
346 spin_unlock_irqrestore(&pmx->lock, flags);
347 } 310 }
311
312 return 0;
348} 313}
349 314
350/* pinmux ranges -> pinctrl pin descs */ 315static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
351static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 316 unsigned long config)
352{ 317{
318 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
319 struct sh_pfc *pfc = pmx->pfc;
320 enum pin_config_param param = pinconf_to_config_param(config);
353 unsigned long flags; 321 unsigned long flags;
354 int i;
355 322
356 pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1; 323 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
324 return -ENOTSUPP;
357 325
358 pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads, 326 switch (param) {
359 GFP_KERNEL); 327 case PIN_CONFIG_BIAS_PULL_UP:
360 if (unlikely(!pmx->pads)) { 328 case PIN_CONFIG_BIAS_PULL_DOWN:
361 pmx->nr_pads = 0; 329 case PIN_CONFIG_BIAS_DISABLE:
362 return -ENOMEM; 330 if (!pfc->info->ops || !pfc->info->ops->set_bias)
363 } 331 return -ENOTSUPP;
364 332
365 spin_lock_irqsave(&pfc->lock, flags); 333 spin_lock_irqsave(&pfc->lock, flags);
334 pfc->info->ops->set_bias(pfc, _pin, param);
335 spin_unlock_irqrestore(&pfc->lock, flags);
366 336
367 /* 337 break;
368 * We don't necessarily have a 1:1 mapping between pin and linux
369 * GPIO number, as the latter maps to the associated enum_id.
370 * Care needs to be taken to translate back to pin space when
371 * dealing with any pin configurations.
372 */
373 for (i = 0; i < pmx->nr_pads; i++) {
374 struct pinctrl_pin_desc *pin = pmx->pads + i;
375 struct pinmux_gpio *gpio = pfc->info->gpios + i;
376 338
377 pin->number = pfc->info->first_gpio + i; 339 default:
378 pin->name = gpio->name; 340 return -ENOTSUPP;
341 }
379 342
380 /* XXX */ 343 return 0;
381 if (unlikely(!gpio->enum_id)) 344}
382 continue;
383 345
384 sh_pfc_map_one_gpio(pfc, pmx, gpio, i); 346static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
385 } 347 unsigned long config)
348{
349 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
350 const unsigned int *pins;
351 unsigned int num_pins;
352 unsigned int i;
386 353
387 spin_unlock_irqrestore(&pfc->lock, flags); 354 pins = pmx->pfc->info->groups[group].pins;
355 num_pins = pmx->pfc->info->groups[group].nr_pins;
388 356
389 sh_pfc_pinctrl_desc.pins = pmx->pads; 357 for (i = 0; i < num_pins; ++i)
390 sh_pfc_pinctrl_desc.npins = pmx->nr_pads; 358 sh_pfc_pinconf_set(pctldev, pins[i], config);
391 359
392 return 0; 360 return 0;
393} 361}
394 362
395static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 363static const struct pinconf_ops sh_pfc_pinconf_ops = {
364 .is_generic = true,
365 .pin_config_get = sh_pfc_pinconf_get,
366 .pin_config_set = sh_pfc_pinconf_set,
367 .pin_config_group_set = sh_pfc_pinconf_group_set,
368 .pin_config_config_dbg_show = pinconf_generic_dump_config,
369};
370
371/* PFC ranges -> pinctrl pin descs */
372static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
396{ 373{
397 unsigned long flags; 374 const struct pinmux_range *ranges;
398 int i, fn; 375 struct pinmux_range def_range;
376 unsigned int nr_ranges;
377 unsigned int nr_pins;
378 unsigned int i;
379
380 if (pfc->info->ranges == NULL) {
381 def_range.begin = 0;
382 def_range.end = pfc->info->nr_pins - 1;
383 ranges = &def_range;
384 nr_ranges = 1;
385 } else {
386 ranges = pfc->info->ranges;
387 nr_ranges = pfc->info->nr_ranges;
388 }
399 389
400 pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions * 390 pmx->pins = devm_kzalloc(pfc->dev,
401 sizeof(*pmx->functions), GFP_KERNEL); 391 sizeof(*pmx->pins) * pfc->info->nr_pins,
402 if (unlikely(!pmx->functions)) 392 GFP_KERNEL);
393 if (unlikely(!pmx->pins))
403 return -ENOMEM; 394 return -ENOMEM;
404 395
405 spin_lock_irqsave(&pmx->lock, flags); 396 pmx->configs = devm_kzalloc(pfc->dev,
406 397 sizeof(*pmx->configs) * pfc->info->nr_pins,
407 for (i = fn = 0; i < pmx->nr_pads; i++) { 398 GFP_KERNEL);
408 struct pinmux_gpio *gpio = pfc->info->gpios + i; 399 if (unlikely(!pmx->configs))
400 return -ENOMEM;
409 401
410 if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION) 402 for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
411 pmx->functions[fn++] = gpio; 403 const struct pinmux_range *range = &ranges[i];
404 unsigned int number;
405
406 for (number = range->begin; number <= range->end;
407 number++, nr_pins++) {
408 struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
409 struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
410 const struct sh_pfc_pin *info =
411 &pfc->info->pins[nr_pins];
412
413 pin->number = number;
414 pin->name = info->name;
415 cfg->type = PINMUX_TYPE_NONE;
416 }
412 } 417 }
413 418
414 spin_unlock_irqrestore(&pmx->lock, flags); 419 pfc->nr_pins = ranges[nr_ranges-1].end + 1;
415 420
416 return 0; 421 return nr_ranges;
417} 422}
418 423
419int sh_pfc_register_pinctrl(struct sh_pfc *pfc) 424int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
420{ 425{
421 struct sh_pfc_pinctrl *pmx; 426 struct sh_pfc_pinctrl *pmx;
422 int ret; 427 int nr_ranges;
423 428
424 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); 429 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
425 if (unlikely(!pmx)) 430 if (unlikely(!pmx))
426 return -ENOMEM; 431 return -ENOMEM;
427 432
428 spin_lock_init(&pmx->lock);
429
430 pmx->pfc = pfc; 433 pmx->pfc = pfc;
431 pfc->pinctrl = pmx; 434 pfc->pinctrl = pmx;
432 435
433 ret = sh_pfc_map_gpios(pfc, pmx); 436 nr_ranges = sh_pfc_map_pins(pfc, pmx);
434 if (unlikely(ret != 0)) 437 if (unlikely(nr_ranges < 0))
435 return ret; 438 return nr_ranges;
436 439
437 ret = sh_pfc_map_functions(pfc, pmx); 440 pmx->pctl_desc.name = DRV_NAME;
438 if (unlikely(ret != 0)) 441 pmx->pctl_desc.owner = THIS_MODULE;
439 return ret; 442 pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
443 pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
444 pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
445 pmx->pctl_desc.pins = pmx->pins;
446 pmx->pctl_desc.npins = pfc->info->nr_pins;
440 447
441 pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, pfc->dev, pmx); 448 pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
442 if (IS_ERR(pmx->pctl)) 449 if (pmx->pctl == NULL)
443 return PTR_ERR(pmx->pctl); 450 return -EINVAL;
444
445 sh_pfc_gpio_range.npins = pfc->info->last_gpio
446 - pfc->info->first_gpio + 1;
447 sh_pfc_gpio_range.base = pfc->info->first_gpio;
448 sh_pfc_gpio_range.pin_base = pfc->info->first_gpio;
449
450 pinctrl_add_gpio_range(pmx->pctl, &sh_pfc_gpio_range);
451 451
452 return 0; 452 return 0;
453} 453}
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 13049c4c8d30..3b785fc428d5 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -15,7 +15,8 @@
15#include <asm-generic/gpio.h> 15#include <asm-generic/gpio.h>
16 16
17typedef unsigned short pinmux_enum_t; 17typedef unsigned short pinmux_enum_t;
18typedef unsigned short pinmux_flag_t; 18
19#define SH_PFC_MARK_INVALID ((pinmux_enum_t)-1)
19 20
20enum { 21enum {
21 PINMUX_TYPE_NONE, 22 PINMUX_TYPE_NONE,
@@ -30,44 +31,81 @@ enum {
30 PINMUX_FLAG_TYPE, /* must be last */ 31 PINMUX_FLAG_TYPE, /* must be last */
31}; 32};
32 33
33#define PINMUX_FLAG_DBIT_SHIFT 5 34#define SH_PFC_PIN_CFG_INPUT (1 << 0)
34#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT) 35#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
35#define PINMUX_FLAG_DREG_SHIFT 10 36#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
36#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT) 37#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
37 38
38struct pinmux_gpio { 39struct sh_pfc_pin {
39 pinmux_enum_t enum_id; 40 const pinmux_enum_t enum_id;
40 pinmux_flag_t flags;
41 const char *name; 41 const char *name;
42 unsigned int configs;
42}; 43};
43 44
44#define PINMUX_GPIO(gpio, data_or_mark) \ 45#define SH_PFC_PIN_GROUP(n) \
45 [gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE } 46 { \
47 .name = #n, \
48 .pins = n##_pins, \
49 .mux = n##_mux, \
50 .nr_pins = ARRAY_SIZE(n##_pins), \
51 }
52
53struct sh_pfc_pin_group {
54 const char *name;
55 const unsigned int *pins;
56 const unsigned int *mux;
57 unsigned int nr_pins;
58};
59
60#define SH_PFC_FUNCTION(n) \
61 { \
62 .name = #n, \
63 .groups = n##_groups, \
64 .nr_groups = ARRAY_SIZE(n##_groups), \
65 }
66
67struct sh_pfc_function {
68 const char *name;
69 const char * const *groups;
70 unsigned int nr_groups;
71};
72
73struct pinmux_func {
74 const pinmux_enum_t enum_id;
75 const char *name;
76};
77
78#define PINMUX_GPIO(gpio, data_or_mark) \
79 [gpio] = { \
80 .name = __stringify(gpio), \
81 .enum_id = data_or_mark, \
82 }
83#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
84 [gpio - (base)] = { \
85 .name = __stringify(gpio), \
86 .enum_id = data_or_mark, \
87 }
46 88
47#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 89#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
48 90
49struct pinmux_cfg_reg { 91struct pinmux_cfg_reg {
50 unsigned long reg, reg_width, field_width; 92 unsigned long reg, reg_width, field_width;
51 unsigned long *cnt; 93 const pinmux_enum_t *enum_ids;
52 pinmux_enum_t *enum_ids; 94 const unsigned long *var_field_width;
53 unsigned long *var_field_width;
54}; 95};
55 96
56#define PINMUX_CFG_REG(name, r, r_width, f_width) \ 97#define PINMUX_CFG_REG(name, r, r_width, f_width) \
57 .reg = r, .reg_width = r_width, .field_width = f_width, \ 98 .reg = r, .reg_width = r_width, .field_width = f_width, \
58 .cnt = (unsigned long [r_width / f_width]) {}, \
59 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) 99 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
60 100
61#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ 101#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
62 .reg = r, .reg_width = r_width, \ 102 .reg = r, .reg_width = r_width, \
63 .cnt = (unsigned long [r_width]) {}, \
64 .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ 103 .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
65 .enum_ids = (pinmux_enum_t []) 104 .enum_ids = (pinmux_enum_t [])
66 105
67struct pinmux_data_reg { 106struct pinmux_data_reg {
68 unsigned long reg, reg_width, reg_shadow; 107 unsigned long reg, reg_width;
69 pinmux_enum_t *enum_ids; 108 const pinmux_enum_t *enum_ids;
70 void __iomem *mapped_reg;
71}; 109};
72 110
73#define PINMUX_DATA_REG(name, r, r_width) \ 111#define PINMUX_DATA_REG(name, r, r_width) \
@@ -76,11 +114,11 @@ struct pinmux_data_reg {
76 114
77struct pinmux_irq { 115struct pinmux_irq {
78 int irq; 116 int irq;
79 pinmux_enum_t *enum_ids; 117 unsigned short *gpios;
80}; 118};
81 119
82#define PINMUX_IRQ(irq_nr, ids...) \ 120#define PINMUX_IRQ(irq_nr, ids...) \
83 { .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \ 121 { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \
84 122
85struct pinmux_range { 123struct pinmux_range {
86 pinmux_enum_t begin; 124 pinmux_enum_t begin;
@@ -88,33 +126,49 @@ struct pinmux_range {
88 pinmux_enum_t force; 126 pinmux_enum_t force;
89}; 127};
90 128
129struct sh_pfc;
130
131struct sh_pfc_soc_operations {
132 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
133 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
134 unsigned int bias);
135};
136
91struct sh_pfc_soc_info { 137struct sh_pfc_soc_info {
92 char *name; 138 const char *name;
93 pinmux_enum_t reserved_id; 139 const struct sh_pfc_soc_operations *ops;
94 struct pinmux_range data; 140
95 struct pinmux_range input; 141 struct pinmux_range input;
96 struct pinmux_range input_pd; 142 struct pinmux_range input_pd;
97 struct pinmux_range input_pu; 143 struct pinmux_range input_pu;
98 struct pinmux_range output; 144 struct pinmux_range output;
99 struct pinmux_range mark;
100 struct pinmux_range function; 145 struct pinmux_range function;
101 146
102 unsigned first_gpio, last_gpio; 147 const struct sh_pfc_pin *pins;
148 unsigned int nr_pins;
149 const struct pinmux_range *ranges;
150 unsigned int nr_ranges;
151 const struct sh_pfc_pin_group *groups;
152 unsigned int nr_groups;
153 const struct sh_pfc_function *functions;
154 unsigned int nr_functions;
155
156 const struct pinmux_func *func_gpios;
157 unsigned int nr_func_gpios;
103 158
104 struct pinmux_gpio *gpios; 159 const struct pinmux_cfg_reg *cfg_regs;
105 struct pinmux_cfg_reg *cfg_regs; 160 const struct pinmux_data_reg *data_regs;
106 struct pinmux_data_reg *data_regs;
107 161
108 pinmux_enum_t *gpio_data; 162 const pinmux_enum_t *gpio_data;
109 unsigned int gpio_data_size; 163 unsigned int gpio_data_size;
110 164
111 struct pinmux_irq *gpio_irq; 165 const struct pinmux_irq *gpio_irq;
112 unsigned int gpio_irq_size; 166 unsigned int gpio_irq_size;
113 167
114 unsigned long unlock_reg; 168 unsigned long unlock_reg;
115}; 169};
116 170
117enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; 171enum { GPIO_CFG_REQ, GPIO_CFG_FREE };
118 172
119/* helper macro for port */ 173/* helper macro for port */
120#define PORT_1(fn, pfx, sfx) fn(pfx, sfx) 174#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
@@ -126,6 +180,23 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
126 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ 180 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
127 PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) 181 PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
128 182
183#define PORT_10_REV(fn, pfx, sfx) \
184 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
185 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
186 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
187 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
188 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
189
190#define PORT_32(fn, pfx, sfx) \
191 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
192 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
193 PORT_1(fn, pfx##31, sfx)
194
195#define PORT_32_REV(fn, pfx, sfx) \
196 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
197 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
198 PORT_10_REV(fn, pfx, sfx)
199
129#define PORT_90(fn, pfx, sfx) \ 200#define PORT_90(fn, pfx, sfx) \
130 PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ 201 PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
131 PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ 202 PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
@@ -137,7 +208,7 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
137#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) 208#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
138#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) 209#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
139#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused) 210#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
140#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) 211#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
141 212
142/* helper macro for pinmux_enum_t */ 213/* helper macro for pinmux_enum_t */
143#define PORT_DATA_I(nr) \ 214#define PORT_DATA_I(nr) \
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-28 10:35:47 -0500