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authorBastian Hecht <hechtb@gmail.com>2013-04-09 06:48:50 -0400
committerSimon Horman <horms+renesas@verge.net.au>2013-06-04 08:03:58 -0400
commit09bbc1fd031da5a9c2550b334eb06df86ab537c2 (patch)
treee5ef5977be8787759ec339cde1e689a7054b6c0e /drivers/pinctrl
parent58c229e18b7754dfe505f3bc1688feb28c84f42a (diff)
sh-pfc: Add entries for INTC external IRQs
We add all necessary entries to support the external IRQs from the INTC. Signed-off-by: Bastian Hecht <hechtb+renesas@gmail.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c174
1 files changed, 174 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index bbd87d29bfd0..d95040c3ccaa 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -30,6 +30,22 @@
30 PORT_10(fn, pfx##20, sfx), \ 30 PORT_10(fn, pfx##20, sfx), \
31 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) 31 PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx)
32 32
33#define IRQC_PIN_MUX(irq, pin) \
34static const unsigned int intc_irq##irq##_pins[] = { \
35 pin, \
36}; \
37static const unsigned int intc_irq##irq##_mux[] = { \
38 IRQ##irq##_MARK, \
39}
40
41#define IRQC_PINS_MUX(irq, idx, pin) \
42static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
43 pin, \
44}; \
45static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
46 IRQ##irq##_PORT##pin##_MARK, \
47}
48
33enum { 49enum {
34 PINMUX_RESERVED = 0, 50 PINMUX_RESERVED = 0,
35 51
@@ -1658,6 +1674,59 @@ static struct sh_pfc_pin pinmux_pins[] = {
1658 GPIO_PORT_ALL(), 1674 GPIO_PORT_ALL(),
1659}; 1675};
1660 1676
1677/* - INTC ------------------------------------------------------------------- */
1678IRQC_PINS_MUX(0, 0, 2);
1679IRQC_PINS_MUX(0, 1, 13);
1680IRQC_PIN_MUX(1, 20);
1681IRQC_PINS_MUX(2, 0, 11);
1682IRQC_PINS_MUX(2, 1, 12);
1683IRQC_PINS_MUX(3, 0, 10);
1684IRQC_PINS_MUX(3, 1, 14);
1685IRQC_PINS_MUX(4, 0, 15);
1686IRQC_PINS_MUX(4, 1, 172);
1687IRQC_PINS_MUX(5, 0, 0);
1688IRQC_PINS_MUX(5, 1, 1);
1689IRQC_PINS_MUX(6, 0, 121);
1690IRQC_PINS_MUX(6, 1, 173);
1691IRQC_PINS_MUX(7, 0, 120);
1692IRQC_PINS_MUX(7, 1, 209);
1693IRQC_PIN_MUX(8, 119);
1694IRQC_PINS_MUX(9, 0, 118);
1695IRQC_PINS_MUX(9, 1, 210);
1696IRQC_PIN_MUX(10, 19);
1697IRQC_PIN_MUX(11, 104);
1698IRQC_PINS_MUX(12, 0, 42);
1699IRQC_PINS_MUX(12, 1, 97);
1700IRQC_PINS_MUX(13, 0, 64);
1701IRQC_PINS_MUX(13, 1, 98);
1702IRQC_PINS_MUX(14, 0, 63);
1703IRQC_PINS_MUX(14, 1, 99);
1704IRQC_PINS_MUX(15, 0, 62);
1705IRQC_PINS_MUX(15, 1, 100);
1706IRQC_PINS_MUX(16, 0, 68);
1707IRQC_PINS_MUX(16, 1, 211);
1708IRQC_PIN_MUX(17, 69);
1709IRQC_PIN_MUX(18, 70);
1710IRQC_PIN_MUX(19, 71);
1711IRQC_PIN_MUX(20, 67);
1712IRQC_PIN_MUX(21, 202);
1713IRQC_PIN_MUX(22, 95);
1714IRQC_PIN_MUX(23, 96);
1715IRQC_PIN_MUX(24, 180);
1716IRQC_PIN_MUX(25, 38);
1717IRQC_PINS_MUX(26, 0, 58);
1718IRQC_PINS_MUX(26, 1, 81);
1719IRQC_PINS_MUX(27, 0, 57);
1720IRQC_PINS_MUX(27, 1, 168);
1721IRQC_PINS_MUX(28, 0, 56);
1722IRQC_PINS_MUX(28, 1, 169);
1723IRQC_PINS_MUX(29, 0, 50);
1724IRQC_PINS_MUX(29, 1, 170);
1725IRQC_PINS_MUX(30, 0, 49);
1726IRQC_PINS_MUX(30, 1, 171);
1727IRQC_PINS_MUX(31, 0, 41);
1728IRQC_PINS_MUX(31, 1, 167);
1729
1661/* - LCD0 ------------------------------------------------------------------- */ 1730/* - LCD0 ------------------------------------------------------------------- */
1662static const unsigned int lcd0_data8_pins[] = { 1731static const unsigned int lcd0_data8_pins[] = {
1663 /* D[0:7] */ 1732 /* D[0:7] */
@@ -2054,6 +2123,57 @@ static const unsigned int sdhi2_wp_1_mux[] = {
2054}; 2123};
2055 2124
2056static const struct sh_pfc_pin_group pinmux_groups[] = { 2125static const struct sh_pfc_pin_group pinmux_groups[] = {
2126 SH_PFC_PIN_GROUP(intc_irq0_0),
2127 SH_PFC_PIN_GROUP(intc_irq0_1),
2128 SH_PFC_PIN_GROUP(intc_irq1),
2129 SH_PFC_PIN_GROUP(intc_irq2_0),
2130 SH_PFC_PIN_GROUP(intc_irq2_1),
2131 SH_PFC_PIN_GROUP(intc_irq3_0),
2132 SH_PFC_PIN_GROUP(intc_irq3_1),
2133 SH_PFC_PIN_GROUP(intc_irq4_0),
2134 SH_PFC_PIN_GROUP(intc_irq4_1),
2135 SH_PFC_PIN_GROUP(intc_irq5_0),
2136 SH_PFC_PIN_GROUP(intc_irq5_1),
2137 SH_PFC_PIN_GROUP(intc_irq6_0),
2138 SH_PFC_PIN_GROUP(intc_irq6_1),
2139 SH_PFC_PIN_GROUP(intc_irq7_0),
2140 SH_PFC_PIN_GROUP(intc_irq7_1),
2141 SH_PFC_PIN_GROUP(intc_irq8),
2142 SH_PFC_PIN_GROUP(intc_irq9_0),
2143 SH_PFC_PIN_GROUP(intc_irq9_1),
2144 SH_PFC_PIN_GROUP(intc_irq10),
2145 SH_PFC_PIN_GROUP(intc_irq11),
2146 SH_PFC_PIN_GROUP(intc_irq12_0),
2147 SH_PFC_PIN_GROUP(intc_irq12_1),
2148 SH_PFC_PIN_GROUP(intc_irq13_0),
2149 SH_PFC_PIN_GROUP(intc_irq13_1),
2150 SH_PFC_PIN_GROUP(intc_irq14_0),
2151 SH_PFC_PIN_GROUP(intc_irq14_1),
2152 SH_PFC_PIN_GROUP(intc_irq15_0),
2153 SH_PFC_PIN_GROUP(intc_irq15_1),
2154 SH_PFC_PIN_GROUP(intc_irq16_0),
2155 SH_PFC_PIN_GROUP(intc_irq16_1),
2156 SH_PFC_PIN_GROUP(intc_irq17),
2157 SH_PFC_PIN_GROUP(intc_irq18),
2158 SH_PFC_PIN_GROUP(intc_irq19),
2159 SH_PFC_PIN_GROUP(intc_irq20),
2160 SH_PFC_PIN_GROUP(intc_irq21),
2161 SH_PFC_PIN_GROUP(intc_irq22),
2162 SH_PFC_PIN_GROUP(intc_irq23),
2163 SH_PFC_PIN_GROUP(intc_irq24),
2164 SH_PFC_PIN_GROUP(intc_irq25),
2165 SH_PFC_PIN_GROUP(intc_irq26_0),
2166 SH_PFC_PIN_GROUP(intc_irq26_1),
2167 SH_PFC_PIN_GROUP(intc_irq27_0),
2168 SH_PFC_PIN_GROUP(intc_irq27_1),
2169 SH_PFC_PIN_GROUP(intc_irq28_0),
2170 SH_PFC_PIN_GROUP(intc_irq28_1),
2171 SH_PFC_PIN_GROUP(intc_irq29_0),
2172 SH_PFC_PIN_GROUP(intc_irq29_1),
2173 SH_PFC_PIN_GROUP(intc_irq30_0),
2174 SH_PFC_PIN_GROUP(intc_irq30_1),
2175 SH_PFC_PIN_GROUP(intc_irq31_0),
2176 SH_PFC_PIN_GROUP(intc_irq31_1),
2057 SH_PFC_PIN_GROUP(lcd0_data8), 2177 SH_PFC_PIN_GROUP(lcd0_data8),
2058 SH_PFC_PIN_GROUP(lcd0_data9), 2178 SH_PFC_PIN_GROUP(lcd0_data9),
2059 SH_PFC_PIN_GROUP(lcd0_data12), 2179 SH_PFC_PIN_GROUP(lcd0_data12),
@@ -2103,6 +2223,60 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2103 SH_PFC_PIN_GROUP(sdhi2_wp_1), 2223 SH_PFC_PIN_GROUP(sdhi2_wp_1),
2104}; 2224};
2105 2225
2226static const char * const intc_groups[] = {
2227 "intc_irq0_0",
2228 "intc_irq0_1",
2229 "intc_irq1",
2230 "intc_irq2_0",
2231 "intc_irq2_1",
2232 "intc_irq3_0",
2233 "intc_irq3_1",
2234 "intc_irq4_0",
2235 "intc_irq4_1",
2236 "intc_irq5_0",
2237 "intc_irq5_1",
2238 "intc_irq6_0",
2239 "intc_irq6_1",
2240 "intc_irq7_0",
2241 "intc_irq7_1",
2242 "intc_irq8",
2243 "intc_irq9_0",
2244 "intc_irq9_1",
2245 "intc_irq10",
2246 "intc_irq11",
2247 "intc_irq12_0",
2248 "intc_irq12_1",
2249 "intc_irq13_0",
2250 "intc_irq13_1",
2251 "intc_irq14_0",
2252 "intc_irq14_1",
2253 "intc_irq15_0",
2254 "intc_irq15_1",
2255 "intc_irq16_0",
2256 "intc_irq16_1",
2257 "intc_irq17",
2258 "intc_irq18",
2259 "intc_irq19",
2260 "intc_irq20",
2261 "intc_irq21",
2262 "intc_irq22",
2263 "intc_irq23",
2264 "intc_irq24",
2265 "intc_irq25",
2266 "intc_irq26_0",
2267 "intc_irq26_1",
2268 "intc_irq27_0",
2269 "intc_irq27_1",
2270 "intc_irq28_0",
2271 "intc_irq28_1",
2272 "intc_irq29_0",
2273 "intc_irq29_1",
2274 "intc_irq30_0",
2275 "intc_irq30_1",
2276 "intc_irq31_0",
2277 "intc_irq31_1",
2278};
2279
2106static const char * const lcd0_groups[] = { 2280static const char * const lcd0_groups[] = {
2107 "lcd0_data8", 2281 "lcd0_data8",
2108 "lcd0_data9", 2282 "lcd0_data9",
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-15 02:24:29 -0400