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authorLinus Torvalds <torvalds@linux-foundation.org>2015-04-14 20:58:15 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-04-14 20:58:15 -0400
commit07e492eb8921a8aa53fd2bf637bee3da94cc03fe (patch)
treef1c1c5004146cbf5ddd3a0c27c05d79627bff775 /drivers/pinctrl
parentb240452a0f5846280e25be7c5a507a99b382fd10 (diff)
parent1dfe0d159dc7f7b6d1734b2010aabda2bbe87d5a (diff)
Merge tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pincontrol updates from Linus Walleij: "This is the bulk of pin control changes for the v4.1 development cycle. Nothing really exciting this time: we basically added a few new drivers and subdrivers and stabilized them in linux-next. Some cleanups too. With sunrisepoint Intel has a real fine fully featured pin control driver for contemporary hardware, and the AMD driver is also for large deployments. Most of the others are ARM devices. New drivers: - Intel Sunrisepoint - AMD KERNCZ GPIO - Broadcom Cygnus IOMUX New subdrivers: - Marvell MVEBU Armada 39x SoCs - Samsung Exynos 5433 - nVidia Tegra 210 - Mediatek MT8135 - Mediatek MT8173 - AMLogic Meson8b - Qualcomm PM8916 On top of this cleanups and development history for the above drivers as issues were fixed after merging" * tag 'pinctrl-v4.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (71 commits) pinctrl: sirf: move sgpio lock into state container pinctrl: Add support for PM8916 GPIO's and MPP's pinctrl: bcm2835: Fix support for threaded level triggered IRQs sh-pfc: r8a7790: add EtherAVB pin groups pinctrl: Document "function" + "pins" pinmux binding pinctrl: intel: Add Intel Sunrisepoint pin controller and GPIO support pinctrl: fsl: imx: Check for 0 config register pinctrl: Add support for Meson8b documentation: Extend pinctrl docs for Meson8b pinctrl: Cleanup Meson8 driver Fix inconsistent spinlock of AMD GPIO driver which can be recognized by static analysis tool smatch. Declare constant Variables with Sparse's suggestion. pinctrl: at91: convert __raw to endian agnostic IO pinctrl: constify of_device_id array pinctrl: pinconf-generic: add dt node names to error messages pinctrl: pinconf-generic: scan also referenced phandle node pinctrl: mvebu: add suspend/resume support to Armada XP pinctrl driver pinctrl: st: Display pin's function when printing pinctrl debug information pinctrl: st: Show correct pin direction also in GPIO mode pinctrl: st: Supply a GPIO get_direction() call-back pinctrl: st: Move st_get_pio_control() further up the source file ...
Diffstat (limited to 'drivers/pinctrl')
-rw-r--r--drivers/pinctrl/Kconfig31
-rw-r--r--drivers/pinctrl/Makefile6
-rw-r--r--drivers/pinctrl/bcm/Kconfig56
-rw-r--r--drivers/pinctrl/bcm/Makefile6
-rw-r--r--drivers/pinctrl/bcm/pinctrl-bcm281xx.c (renamed from drivers/pinctrl/pinctrl-bcm281xx.c)4
-rw-r--r--drivers/pinctrl/bcm/pinctrl-bcm2835.c (renamed from drivers/pinctrl/pinctrl-bcm2835.c)28
-rw-r--r--drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c907
-rw-r--r--drivers/pinctrl/bcm/pinctrl-cygnus-mux.c1022
-rw-r--r--drivers/pinctrl/freescale/pinctrl-imx.c15
-rw-r--r--drivers/pinctrl/freescale/pinctrl-vf610.c2
-rw-r--r--drivers/pinctrl/intel/Kconfig17
-rw-r--r--drivers/pinctrl/intel/Makefile2
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.c1149
-rw-r--r--drivers/pinctrl/intel/pinctrl-intel.h128
-rw-r--r--drivers/pinctrl/intel/pinctrl-sunrisepoint.c336
-rw-r--r--drivers/pinctrl/mediatek/Kconfig23
-rw-r--r--drivers/pinctrl/mediatek/Makefile6
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8135.c376
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8173.c455
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.c1257
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.h229
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h2114
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h1226
-rw-r--r--drivers/pinctrl/meson/Makefile2
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.c9
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson.h9
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson8.c1050
-rw-r--r--drivers/pinctrl/meson/pinctrl-meson8b.c899
-rw-r--r--drivers/pinctrl/mvebu/Kconfig4
-rw-r--r--drivers/pinctrl/mvebu/Makefile1
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-370.c2
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-375.c2
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-38x.c2
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-39x.c432
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-xp.c42
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-kirkwood.c2
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-orion.c2
-rw-r--r--drivers/pinctrl/pinconf-generic.c54
-rw-r--r--drivers/pinctrl/pinctrl-amd.c869
-rw-r--r--drivers/pinctrl/pinctrl-amd.h261
-rw-r--r--drivers/pinctrl/pinctrl-as3722.c2
-rw-r--r--drivers/pinctrl/pinctrl-at91.c60
-rw-r--r--drivers/pinctrl/pinctrl-lantiq.h2
-rw-r--r--drivers/pinctrl/pinctrl-palmas.c2
-rw-r--r--drivers/pinctrl/pinctrl-single.c4
-rw-r--r--drivers/pinctrl/pinctrl-st.c85
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c28
-rw-r--r--drivers/pinctrl/pinctrl-tegra.h43
-rw-r--r--drivers/pinctrl/pinctrl-tegra114.c17
-rw-r--r--drivers/pinctrl/pinctrl-tegra124.c32
-rw-r--r--drivers/pinctrl/pinctrl-tegra20.c3
-rw-r--r--drivers/pinctrl/pinctrl-tegra210.c1588
-rw-r--r--drivers/pinctrl/pinctrl-tegra30.c116
-rw-r--r--drivers/pinctrl/pinctrl-tz1090-pdc.c2
-rw-r--r--drivers/pinctrl/pinctrl-tz1090.c2
-rw-r--r--drivers/pinctrl/qcom/pinctrl-msm.c17
-rw-r--r--drivers/pinctrl/qcom/pinctrl-spmi-gpio.c1
-rw-r--r--drivers/pinctrl/qcom/pinctrl-spmi-mpp.c1
-rw-r--r--drivers/pinctrl/samsung/pinctrl-exynos.c154
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.c2
-rw-r--r--drivers/pinctrl/samsung/pinctrl-samsung.h1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c79
-rw-r--r--drivers/pinctrl/sh-pfc/core.h7
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c31
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c91
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h37
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c26
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c2
-rw-r--r--drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c2
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-vt8500.c2
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8505.c2
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8650.c2
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8750.c2
-rw-r--r--drivers/pinctrl/vt8500/pinctrl-wm8850.c2
82 files changed, 14568 insertions, 932 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ee9f44ad7f02..c6f299ba25cb 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -67,23 +67,20 @@ config PINCTRL_AT91
67 help 67 help
68 Say Y here to enable the at91 pinctrl driver 68 Say Y here to enable the at91 pinctrl driver
69 69
70config PINCTRL_BCM2835 70config PINCTRL_AMD
71 bool 71 bool "AMD GPIO pin control"
72 select PINMUX 72 depends on GPIOLIB
73 select PINCONF 73 select GPIOLIB_IRQCHIP
74
75config PINCTRL_BCM281XX
76 bool "Broadcom BCM281xx pinctrl driver"
77 depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST)
78 select PINMUX
79 select PINCONF 74 select PINCONF
80 select GENERIC_PINCONF 75 select GENERIC_PINCONF
81 select REGMAP_MMIO
82 help 76 help
83 Say Y here to support Broadcom BCM281xx pinctrl driver, which is used 77 driver for memory mapped GPIO functionality on AMD platforms
84 for the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351, 78 (x86 or arm).Most pins are usually muxed to some other
85 BCM28145, and BCM28155 SoCs. This driver requires the pinctrl 79 functionality by firmware,so only a small amount is available
86 framework. GPIO is provided by a separate GPIO driver. 80 for gpio use.
81
82 Requires ACPI/FDT device enumeration code to set up a platform
83 device.
87 84
88config PINCTRL_LANTIQ 85config PINCTRL_LANTIQ
89 bool 86 bool
@@ -154,6 +151,10 @@ config PINCTRL_TEGRA124
154 bool 151 bool
155 select PINCTRL_TEGRA 152 select PINCTRL_TEGRA
156 153
154config PINCTRL_TEGRA210
155 bool
156 select PINCTRL_TEGRA
157
157config PINCTRL_TEGRA_XUSB 158config PINCTRL_TEGRA_XUSB
158 def_bool y if ARCH_TEGRA 159 def_bool y if ARCH_TEGRA
159 select GENERIC_PHY 160 select GENERIC_PHY
@@ -207,6 +208,7 @@ config PINCTRL_ZYNQ
207 help 208 help
208 This selectes the pinctrl driver for Xilinx Zynq. 209 This selectes the pinctrl driver for Xilinx Zynq.
209 210
211source "drivers/pinctrl/bcm/Kconfig"
210source "drivers/pinctrl/berlin/Kconfig" 212source "drivers/pinctrl/berlin/Kconfig"
211source "drivers/pinctrl/freescale/Kconfig" 213source "drivers/pinctrl/freescale/Kconfig"
212source "drivers/pinctrl/intel/Kconfig" 214source "drivers/pinctrl/intel/Kconfig"
@@ -218,6 +220,7 @@ source "drivers/pinctrl/sh-pfc/Kconfig"
218source "drivers/pinctrl/spear/Kconfig" 220source "drivers/pinctrl/spear/Kconfig"
219source "drivers/pinctrl/sunxi/Kconfig" 221source "drivers/pinctrl/sunxi/Kconfig"
220source "drivers/pinctrl/vt8500/Kconfig" 222source "drivers/pinctrl/vt8500/Kconfig"
223source "drivers/pinctrl/mediatek/Kconfig"
221 224
222config PINCTRL_XWAY 225config PINCTRL_XWAY
223 bool 226 bool
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 0475206dd600..6eadf04a33b3 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -14,8 +14,7 @@ obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
14obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o 14obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
15obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o 15obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
16obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o 16obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
17obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 17obj-$(CONFIG_PINCTRL_AMD) += pinctrl-amd.o
18obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
19obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 18obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
20obj-$(CONFIG_PINCTRL_MESON) += meson/ 19obj-$(CONFIG_PINCTRL_MESON) += meson/
21obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o 20obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
@@ -27,6 +26,7 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
27obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o 26obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
28obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o 27obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
29obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o 28obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o
29obj-$(CONFIG_PINCTRL_TEGRA210) += pinctrl-tegra210.o
30obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o 30obj-$(CONFIG_PINCTRL_TEGRA_XUSB) += pinctrl-tegra-xusb.o
31obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o 31obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
32obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o 32obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o
@@ -38,6 +38,7 @@ obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
38obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o 38obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
39obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o 39obj-$(CONFIG_PINCTRL_ZYNQ) += pinctrl-zynq.o
40 40
41obj-$(CONFIG_ARCH_BCM) += bcm/
41obj-$(CONFIG_ARCH_BERLIN) += berlin/ 42obj-$(CONFIG_ARCH_BERLIN) += berlin/
42obj-y += freescale/ 43obj-y += freescale/
43obj-$(CONFIG_X86) += intel/ 44obj-$(CONFIG_X86) += intel/
@@ -49,3 +50,4 @@ obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/
49obj-$(CONFIG_PLAT_SPEAR) += spear/ 50obj-$(CONFIG_PLAT_SPEAR) += spear/
50obj-$(CONFIG_ARCH_SUNXI) += sunxi/ 51obj-$(CONFIG_ARCH_SUNXI) += sunxi/
51obj-$(CONFIG_ARCH_VT8500) += vt8500/ 52obj-$(CONFIG_ARCH_VT8500) += vt8500/
53obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
diff --git a/drivers/pinctrl/bcm/Kconfig b/drivers/pinctrl/bcm/Kconfig
new file mode 100644
index 000000000000..cd11d4d9ad58
--- /dev/null
+++ b/drivers/pinctrl/bcm/Kconfig
@@ -0,0 +1,56 @@
1#
2# Broadcom pinctrl drivers
3#
4
5config PINCTRL_BCM281XX
6 bool "Broadcom BCM281xx pinctrl driver"
7 depends on OF && (ARCH_BCM_MOBILE || COMPILE_TEST)
8 select PINMUX
9 select PINCONF
10 select GENERIC_PINCONF
11 select REGMAP_MMIO
12 help
13 Say Y here to support Broadcom BCM281xx pinctrl driver, which is used
14 for the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351,
15 BCM28145, and BCM28155 SoCs. This driver requires the pinctrl
16 framework. GPIO is provided by a separate GPIO driver.
17
18config PINCTRL_BCM2835
19 bool
20 select PINMUX
21 select PINCONF
22
23config PINCTRL_CYGNUS_GPIO
24 bool "Broadcom Cygnus GPIO (with PINCONF) driver"
25 depends on OF_GPIO && ARCH_BCM_CYGNUS
26 select GPIOLIB_IRQCHIP
27 select PINCONF
28 select GENERIC_PINCONF
29 default ARCH_BCM_CYGNUS
30 help
31 Say yes here to enable the Broadcom Cygnus GPIO driver.
32
33 The Broadcom Cygnus SoC has 3 GPIO controllers including the ASIU
34 GPIO controller (ASIU), the chipCommonG GPIO controller (CCM), and
35 the always-ON GPIO controller (CRMU/AON). All 3 GPIO controllers are
36 supported by this driver.
37
38 All 3 Cygnus GPIO controllers support basic PINCONF functions such
39 as bias pull up, pull down, and drive strength configurations, when
40 these pins are muxed to GPIO.
41
42 Pins from the ASIU GPIO can be individually muxed to GPIO function,
43 through interaction with the Cygnus IOMUX controller.
44
45config PINCTRL_CYGNUS_MUX
46 bool "Broadcom Cygnus IOMUX driver"
47 depends on (ARCH_BCM_CYGNUS || COMPILE_TEST)
48 select PINMUX
49 select GENERIC_PINCONF
50 default ARCH_BCM_CYGNUS
51 help
52 Say yes here to enable the Broadcom Cygnus IOMUX driver.
53
54 The Broadcom Cygnus IOMUX driver supports group based IOMUX
55 configuration, with the exception that certain individual pins
56 can be overrided to GPIO function
diff --git a/drivers/pinctrl/bcm/Makefile b/drivers/pinctrl/bcm/Makefile
new file mode 100644
index 000000000000..2b2f70ee804c
--- /dev/null
+++ b/drivers/pinctrl/bcm/Makefile
@@ -0,0 +1,6 @@
1# Broadcom pinctrl support
2
3obj-$(CONFIG_PINCTRL_BCM281XX) += pinctrl-bcm281xx.o
4obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
5obj-$(CONFIG_PINCTRL_CYGNUS_GPIO) += pinctrl-cygnus-gpio.o
6obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
diff --git a/drivers/pinctrl/pinctrl-bcm281xx.c b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c
index b88cfe5ed55a..9641f1c7617e 100644
--- a/drivers/pinctrl/pinctrl-bcm281xx.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm281xx.c
@@ -21,8 +21,8 @@
21#include <linux/pinctrl/pinconf-generic.h> 21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/regmap.h> 22#include <linux/regmap.h>
23#include <linux/slab.h> 23#include <linux/slab.h>
24#include "core.h" 24#include "../core.h"
25#include "pinctrl-utils.h" 25#include "../pinctrl-utils.h"
26 26
27/* BCM281XX Pin Control Registers Definitions */ 27/* BCM281XX Pin Control Registers Definitions */
28 28
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
index 9aa8a3f10b10..8d908e3f42c3 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c
@@ -403,15 +403,7 @@ static irqreturn_t bcm2835_gpio_irq_handler(int irq, void *dev_id)
403 gpio = (32 * bank) + offset; 403 gpio = (32 * bank) + offset;
404 type = pc->irq_type[gpio]; 404 type = pc->irq_type[gpio];
405 405
406 /* ack edge triggered IRQs immediately */
407 if (!(type & IRQ_TYPE_LEVEL_MASK))
408 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
409
410 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio)); 406 generic_handle_irq(irq_linear_revmap(pc->irq_domain, gpio));
411
412 /* ack level triggered IRQ after handling them */
413 if (type & IRQ_TYPE_LEVEL_MASK)
414 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
415 } 407 }
416 return events ? IRQ_HANDLED : IRQ_NONE; 408 return events ? IRQ_HANDLED : IRQ_NONE;
417} 409}
@@ -591,16 +583,32 @@ static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
591 else 583 else
592 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type); 584 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
593 585
586 if (type & IRQ_TYPE_EDGE_BOTH)
587 __irq_set_handler_locked(data->irq, handle_edge_irq);
588 else
589 __irq_set_handler_locked(data->irq, handle_level_irq);
590
594 spin_unlock_irqrestore(&pc->irq_lock[bank], flags); 591 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
595 592
596 return ret; 593 return ret;
597} 594}
598 595
596static void bcm2835_gpio_irq_ack(struct irq_data *data)
597{
598 struct bcm2835_pinctrl *pc = irq_data_get_irq_chip_data(data);
599 unsigned gpio = irqd_to_hwirq(data);
600
601 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
602}
603
599static struct irq_chip bcm2835_gpio_irq_chip = { 604static struct irq_chip bcm2835_gpio_irq_chip = {
600 .name = MODULE_NAME, 605 .name = MODULE_NAME,
601 .irq_enable = bcm2835_gpio_irq_enable, 606 .irq_enable = bcm2835_gpio_irq_enable,
602 .irq_disable = bcm2835_gpio_irq_disable, 607 .irq_disable = bcm2835_gpio_irq_disable,
603 .irq_set_type = bcm2835_gpio_irq_set_type, 608 .irq_set_type = bcm2835_gpio_irq_set_type,
609 .irq_ack = bcm2835_gpio_irq_ack,
610 .irq_mask = bcm2835_gpio_irq_disable,
611 .irq_unmask = bcm2835_gpio_irq_enable,
604}; 612};
605 613
606static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev) 614static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
@@ -977,7 +985,7 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev)
977 int irq = irq_create_mapping(pc->irq_domain, i); 985 int irq = irq_create_mapping(pc->irq_domain, i);
978 irq_set_lockdep_class(irq, &gpio_lock_class); 986 irq_set_lockdep_class(irq, &gpio_lock_class);
979 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip, 987 irq_set_chip_and_handler(irq, &bcm2835_gpio_irq_chip,
980 handle_simple_irq); 988 handle_level_irq);
981 irq_set_chip_data(irq, pc); 989 irq_set_chip_data(irq, pc);
982 set_irq_flags(irq, IRQF_VALID); 990 set_irq_flags(irq, IRQF_VALID);
983 } 991 }
@@ -1051,7 +1059,7 @@ static int bcm2835_pinctrl_remove(struct platform_device *pdev)
1051 return 0; 1059 return 0;
1052} 1060}
1053 1061
1054static struct of_device_id bcm2835_pinctrl_match[] = { 1062static const struct of_device_id bcm2835_pinctrl_match[] = {
1055 { .compatible = "brcm,bcm2835-gpio" }, 1063 { .compatible = "brcm,bcm2835-gpio" },
1056 {} 1064 {}
1057}; 1065};
diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c
new file mode 100644
index 000000000000..4ad5c1a996e3
--- /dev/null
+++ b/drivers/pinctrl/bcm/pinctrl-cygnus-gpio.c
@@ -0,0 +1,907 @@
1/*
2 * Copyright (C) 2014-2015 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * This file contains the Broadcom Cygnus GPIO driver that supports 3
14 * GPIO controllers on Cygnus including the ASIU GPIO controller, the
15 * chipCommonG GPIO controller, and the always-on GPIO controller. Basic
16 * PINCONF such as bias pull up/down, and drive strength are also supported
17 * in this driver.
18 *
19 * Pins from the ASIU GPIO can be individually muxed to GPIO function,
20 * through the interaction with the Cygnus IOMUX controller
21 */
22
23#include <linux/kernel.h>
24#include <linux/slab.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/gpio.h>
28#include <linux/ioport.h>
29#include <linux/of_device.h>
30#include <linux/of_irq.h>
31#include <linux/pinctrl/pinctrl.h>
32#include <linux/pinctrl/pinmux.h>
33#include <linux/pinctrl/pinconf.h>
34#include <linux/pinctrl/pinconf-generic.h>
35
36#include "../pinctrl-utils.h"
37
38#define CYGNUS_GPIO_DATA_IN_OFFSET 0x00
39#define CYGNUS_GPIO_DATA_OUT_OFFSET 0x04
40#define CYGNUS_GPIO_OUT_EN_OFFSET 0x08
41#define CYGNUS_GPIO_IN_TYPE_OFFSET 0x0c
42#define CYGNUS_GPIO_INT_DE_OFFSET 0x10
43#define CYGNUS_GPIO_INT_EDGE_OFFSET 0x14
44#define CYGNUS_GPIO_INT_MSK_OFFSET 0x18
45#define CYGNUS_GPIO_INT_STAT_OFFSET 0x1c
46#define CYGNUS_GPIO_INT_MSTAT_OFFSET 0x20
47#define CYGNUS_GPIO_INT_CLR_OFFSET 0x24
48#define CYGNUS_GPIO_PAD_RES_OFFSET 0x34
49#define CYGNUS_GPIO_RES_EN_OFFSET 0x38
50
51/* drive strength control for ASIU GPIO */
52#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
53
54/* drive strength control for CCM/CRMU (AON) GPIO */
55#define CYGNUS_GPIO_DRV0_CTRL_OFFSET 0x00
56
57#define GPIO_BANK_SIZE 0x200
58#define NGPIOS_PER_BANK 32
59#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
60
61#define CYGNUS_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
62#define CYGNUS_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
63
64#define GPIO_DRV_STRENGTH_BIT_SHIFT 20
65#define GPIO_DRV_STRENGTH_BITS 3
66#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
67
68/*
69 * Cygnus GPIO core
70 *
71 * @dev: pointer to device
72 * @base: I/O register base for Cygnus GPIO controller
73 * @io_ctrl: I/O register base for certain type of Cygnus GPIO controller that
74 * has the PINCONF support implemented outside of the GPIO block
75 * @lock: lock to protect access to I/O registers
76 * @gc: GPIO chip
77 * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
78 * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
79 * that can be individually muxed to GPIO
80 * @pctl: pointer to pinctrl_dev
81 * @pctldesc: pinctrl descriptor
82 */
83struct cygnus_gpio {
84 struct device *dev;
85
86 void __iomem *base;
87 void __iomem *io_ctrl;
88
89 spinlock_t lock;
90
91 struct gpio_chip gc;
92 unsigned num_banks;
93
94 bool pinmux_is_supported;
95
96 struct pinctrl_dev *pctl;
97 struct pinctrl_desc pctldesc;
98};
99
100static inline struct cygnus_gpio *to_cygnus_gpio(struct gpio_chip *gc)
101{
102 return container_of(gc, struct cygnus_gpio, gc);
103}
104
105/*
106 * Mapping from PINCONF pins to GPIO pins is 1-to-1
107 */
108static inline unsigned cygnus_pin_to_gpio(unsigned pin)
109{
110 return pin;
111}
112
113/**
114 * cygnus_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
115 * Cygnus GPIO register
116 *
117 * @cygnus_gpio: Cygnus GPIO device
118 * @reg: register offset
119 * @gpio: GPIO pin
120 * @set: set or clear
121 */
122static inline void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg,
123 unsigned gpio, bool set)
124{
125 unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
126 unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
127 u32 val;
128
129 val = readl(chip->base + offset);
130 if (set)
131 val |= BIT(shift);
132 else
133 val &= ~BIT(shift);
134 writel(val, chip->base + offset);
135}
136
137static inline bool cygnus_get_bit(struct cygnus_gpio *chip, unsigned int reg,
138 unsigned gpio)
139{
140 unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
141 unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
142
143 return !!(readl(chip->base + offset) & BIT(shift));
144}
145
146static void cygnus_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
147{
148 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
149 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
150 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
151 int i, bit;
152
153 chained_irq_enter(irq_chip, desc);
154
155 /* go through the entire GPIO banks and handle all interrupts */
156 for (i = 0; i < chip->num_banks; i++) {
157 unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
158 CYGNUS_GPIO_INT_MSTAT_OFFSET);
159
160 for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
161 unsigned pin = NGPIOS_PER_BANK * i + bit;
162 int child_irq = irq_find_mapping(gc->irqdomain, pin);
163
164 /*
165 * Clear the interrupt before invoking the
166 * handler, so we do not leave any window
167 */
168 writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
169 CYGNUS_GPIO_INT_CLR_OFFSET);
170
171 generic_handle_irq(child_irq);
172 }
173 }
174
175 chained_irq_exit(irq_chip, desc);
176}
177
178
179static void cygnus_gpio_irq_ack(struct irq_data *d)
180{
181 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
182 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
183 unsigned gpio = d->hwirq;
184 unsigned int offset = CYGNUS_GPIO_REG(gpio,
185 CYGNUS_GPIO_INT_CLR_OFFSET);
186 unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
187 u32 val = BIT(shift);
188
189 writel(val, chip->base + offset);
190}
191
192/**
193 * cygnus_gpio_irq_set_mask - mask/unmask a GPIO interrupt
194 *
195 * @d: IRQ chip data
196 * @unmask: mask/unmask GPIO interrupt
197 */
198static void cygnus_gpio_irq_set_mask(struct irq_data *d, bool unmask)
199{
200 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
201 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
202 unsigned gpio = d->hwirq;
203
204 cygnus_set_bit(chip, CYGNUS_GPIO_INT_MSK_OFFSET, gpio, unmask);
205}
206
207static void cygnus_gpio_irq_mask(struct irq_data *d)
208{
209 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
210 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
211 unsigned long flags;
212
213 spin_lock_irqsave(&chip->lock, flags);
214 cygnus_gpio_irq_set_mask(d, false);
215 spin_unlock_irqrestore(&chip->lock, flags);
216}
217
218static void cygnus_gpio_irq_unmask(struct irq_data *d)
219{
220 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
221 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
222 unsigned long flags;
223
224 spin_lock_irqsave(&chip->lock, flags);
225 cygnus_gpio_irq_set_mask(d, true);
226 spin_unlock_irqrestore(&chip->lock, flags);
227}
228
229static int cygnus_gpio_irq_set_type(struct irq_data *d, unsigned int type)
230{
231 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
232 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
233 unsigned gpio = d->hwirq;
234 bool level_triggered = false;
235 bool dual_edge = false;
236 bool rising_or_high = false;
237 unsigned long flags;
238
239 switch (type & IRQ_TYPE_SENSE_MASK) {
240 case IRQ_TYPE_EDGE_RISING:
241 rising_or_high = true;
242 break;
243
244 case IRQ_TYPE_EDGE_FALLING:
245 break;
246
247 case IRQ_TYPE_EDGE_BOTH:
248 dual_edge = true;
249 break;
250
251 case IRQ_TYPE_LEVEL_HIGH:
252 level_triggered = true;
253 rising_or_high = true;
254 break;
255
256 case IRQ_TYPE_LEVEL_LOW:
257 level_triggered = true;
258 break;
259
260 default:
261 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
262 type);
263 return -EINVAL;
264 }
265
266 spin_lock_irqsave(&chip->lock, flags);
267 cygnus_set_bit(chip, CYGNUS_GPIO_IN_TYPE_OFFSET, gpio,
268 level_triggered);
269 cygnus_set_bit(chip, CYGNUS_GPIO_INT_DE_OFFSET, gpio, dual_edge);
270 cygnus_set_bit(chip, CYGNUS_GPIO_INT_EDGE_OFFSET, gpio,
271 rising_or_high);
272 spin_unlock_irqrestore(&chip->lock, flags);
273
274 dev_dbg(chip->dev,
275 "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
276 gpio, level_triggered, dual_edge, rising_or_high);
277
278 return 0;
279}
280
281static struct irq_chip cygnus_gpio_irq_chip = {
282 .name = "bcm-cygnus-gpio",
283 .irq_ack = cygnus_gpio_irq_ack,
284 .irq_mask = cygnus_gpio_irq_mask,
285 .irq_unmask = cygnus_gpio_irq_unmask,
286 .irq_set_type = cygnus_gpio_irq_set_type,
287};
288
289/*
290 * Request the Cygnus IOMUX pinmux controller to mux individual pins to GPIO
291 */
292static int cygnus_gpio_request(struct gpio_chip *gc, unsigned offset)
293{
294 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
295 unsigned gpio = gc->base + offset;
296
297 /* not all Cygnus GPIO pins can be muxed individually */
298 if (!chip->pinmux_is_supported)
299 return 0;
300
301 return pinctrl_request_gpio(gpio);
302}
303
304static void cygnus_gpio_free(struct gpio_chip *gc, unsigned offset)
305{
306 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
307 unsigned gpio = gc->base + offset;
308
309 if (!chip->pinmux_is_supported)
310 return;
311
312 pinctrl_free_gpio(gpio);
313}
314
315static int cygnus_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
316{
317 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
318 unsigned long flags;
319
320 spin_lock_irqsave(&chip->lock, flags);
321 cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, false);
322 spin_unlock_irqrestore(&chip->lock, flags);
323
324 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
325
326 return 0;
327}
328
329static int cygnus_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
330 int val)
331{
332 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
333 unsigned long flags;
334
335 spin_lock_irqsave(&chip->lock, flags);
336 cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, true);
337 cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
338 spin_unlock_irqrestore(&chip->lock, flags);
339
340 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
341
342 return 0;
343}
344
345static void cygnus_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
346{
347 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
348 unsigned long flags;
349
350 spin_lock_irqsave(&chip->lock, flags);
351 cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
352 spin_unlock_irqrestore(&chip->lock, flags);
353
354 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
355}
356
357static int cygnus_gpio_get(struct gpio_chip *gc, unsigned gpio)
358{
359 struct cygnus_gpio *chip = to_cygnus_gpio(gc);
360 unsigned int offset = CYGNUS_GPIO_REG(gpio,
361 CYGNUS_GPIO_DATA_IN_OFFSET);
362 unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
363
364 return !!(readl(chip->base + offset) & BIT(shift));
365}
366
367static int cygnus_get_groups_count(struct pinctrl_dev *pctldev)
368{
369 return 1;
370}
371
372/*
373 * Only one group: "gpio_grp", since this local pinctrl device only performs
374 * GPIO specific PINCONF configurations
375 */
376static const char *cygnus_get_group_name(struct pinctrl_dev *pctldev,
377 unsigned selector)
378{
379 return "gpio_grp";
380}
381
382static const struct pinctrl_ops cygnus_pctrl_ops = {
383 .get_groups_count = cygnus_get_groups_count,
384 .get_group_name = cygnus_get_group_name,
385 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
386 .dt_free_map = pinctrl_utils_dt_free_map,
387};
388
389static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio,
390 bool disable, bool pull_up)
391{
392 unsigned long flags;
393
394 spin_lock_irqsave(&chip->lock, flags);
395
396 if (disable) {
397 cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, false);
398 } else {
399 cygnus_set_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio,
400 pull_up);
401 cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, true);
402 }
403
404 spin_unlock_irqrestore(&chip->lock, flags);
405
406 dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
407
408 return 0;
409}
410
411static void cygnus_gpio_get_pull(struct cygnus_gpio *chip, unsigned gpio,
412 bool *disable, bool *pull_up)
413{
414 unsigned long flags;
415
416 spin_lock_irqsave(&chip->lock, flags);
417 *disable = !cygnus_get_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio);
418 *pull_up = cygnus_get_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio);
419 spin_unlock_irqrestore(&chip->lock, flags);
420}
421
422static int cygnus_gpio_set_strength(struct cygnus_gpio *chip, unsigned gpio,
423 unsigned strength)
424{
425 void __iomem *base;
426 unsigned int i, offset, shift;
427 u32 val;
428 unsigned long flags;
429
430 /* make sure drive strength is supported */
431 if (strength < 2 || strength > 16 || (strength % 2))
432 return -ENOTSUPP;
433
434 if (chip->io_ctrl) {
435 base = chip->io_ctrl;
436 offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET;
437 } else {
438 base = chip->base;
439 offset = CYGNUS_GPIO_REG(gpio,
440 CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET);
441 }
442
443 shift = CYGNUS_GPIO_SHIFT(gpio);
444
445 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
446 strength);
447
448 spin_lock_irqsave(&chip->lock, flags);
449 strength = (strength / 2) - 1;
450 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
451 val = readl(base + offset);
452 val &= ~BIT(shift);
453 val |= ((strength >> i) & 0x1) << shift;
454 writel(val, base + offset);
455 offset += 4;
456 }
457 spin_unlock_irqrestore(&chip->lock, flags);
458
459 return 0;
460}
461
462static int cygnus_gpio_get_strength(struct cygnus_gpio *chip, unsigned gpio,
463 u16 *strength)
464{
465 void __iomem *base;
466 unsigned int i, offset, shift;
467 u32 val;
468 unsigned long flags;
469
470 if (chip->io_ctrl) {
471 base = chip->io_ctrl;
472 offset = CYGNUS_GPIO_DRV0_CTRL_OFFSET;
473 } else {
474 base = chip->base;
475 offset = CYGNUS_GPIO_REG(gpio,
476 CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET);
477 }
478
479 shift = CYGNUS_GPIO_SHIFT(gpio);
480
481 spin_lock_irqsave(&chip->lock, flags);
482 *strength = 0;
483 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
484 val = readl(base + offset) & BIT(shift);
485 val >>= shift;
486 *strength += (val << i);
487 offset += 4;
488 }
489
490 /* convert to mA */
491 *strength = (*strength + 1) * 2;
492 spin_unlock_irqrestore(&chip->lock, flags);
493
494 return 0;
495}
496
497static int cygnus_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
498 unsigned long *config)
499{
500 struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
501 enum pin_config_param param = pinconf_to_config_param(*config);
502 unsigned gpio = cygnus_pin_to_gpio(pin);
503 u16 arg;
504 bool disable, pull_up;
505 int ret;
506
507 switch (param) {
508 case PIN_CONFIG_BIAS_DISABLE:
509 cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up);
510 if (disable)
511 return 0;
512 else
513 return -EINVAL;
514
515 case PIN_CONFIG_BIAS_PULL_UP:
516 cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up);
517 if (!disable && pull_up)
518 return 0;
519 else
520 return -EINVAL;
521
522 case PIN_CONFIG_BIAS_PULL_DOWN:
523 cygnus_gpio_get_pull(chip, gpio, &disable, &pull_up);
524 if (!disable && !pull_up)
525 return 0;
526 else
527 return -EINVAL;
528
529 case PIN_CONFIG_DRIVE_STRENGTH:
530 ret = cygnus_gpio_get_strength(chip, gpio, &arg);
531 if (ret)
532 return ret;
533 else
534 *config = pinconf_to_config_packed(param, arg);
535
536 return 0;
537
538 default:
539 return -ENOTSUPP;
540 }
541
542 return -ENOTSUPP;
543}
544
545static int cygnus_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
546 unsigned long *configs, unsigned num_configs)
547{
548 struct cygnus_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
549 enum pin_config_param param;
550 u16 arg;
551 unsigned i, gpio = cygnus_pin_to_gpio(pin);
552 int ret = -ENOTSUPP;
553
554 for (i = 0; i < num_configs; i++) {
555 param = pinconf_to_config_param(configs[i]);
556 arg = pinconf_to_config_argument(configs[i]);
557
558 switch (param) {
559 case PIN_CONFIG_BIAS_DISABLE:
560 ret = cygnus_gpio_set_pull(chip, gpio, true, false);
561 if (ret < 0)
562 goto out;
563 break;
564
565 case PIN_CONFIG_BIAS_PULL_UP:
566 ret = cygnus_gpio_set_pull(chip, gpio, false, true);
567 if (ret < 0)
568 goto out;
569 break;
570
571 case PIN_CONFIG_BIAS_PULL_DOWN:
572 ret = cygnus_gpio_set_pull(chip, gpio, false, false);
573 if (ret < 0)
574 goto out;
575 break;
576
577 case PIN_CONFIG_DRIVE_STRENGTH:
578 ret = cygnus_gpio_set_strength(chip, gpio, arg);
579 if (ret < 0)
580 goto out;
581 break;
582
583 default:
584 dev_err(chip->dev, "invalid configuration\n");
585 return -ENOTSUPP;
586 }
587 } /* for each config */
588
589out:
590 return ret;
591}
592
593static const struct pinconf_ops cygnus_pconf_ops = {
594 .is_generic = true,
595 .pin_config_get = cygnus_pin_config_get,
596 .pin_config_set = cygnus_pin_config_set,
597};
598
599/*
600 * Map a GPIO in the local gpio_chip pin space to a pin in the Cygnus IOMUX
601 * pinctrl pin space
602 */
603struct cygnus_gpio_pin_range {
604 unsigned offset;
605 unsigned pin_base;
606 unsigned num_pins;
607};
608
609#define CYGNUS_PINRANGE(o, p, n) { .offset = o, .pin_base = p, .num_pins = n }
610
611/*
612 * Pin mapping table for mapping local GPIO pins to Cygnus IOMUX pinctrl pins
613 */
614static const struct cygnus_gpio_pin_range cygnus_gpio_pintable[] = {
615 CYGNUS_PINRANGE(0, 42, 1),
616 CYGNUS_PINRANGE(1, 44, 3),
617 CYGNUS_PINRANGE(4, 48, 1),
618 CYGNUS_PINRANGE(5, 50, 3),
619 CYGNUS_PINRANGE(8, 126, 1),
620 CYGNUS_PINRANGE(9, 155, 1),
621 CYGNUS_PINRANGE(10, 152, 1),
622 CYGNUS_PINRANGE(11, 154, 1),
623 CYGNUS_PINRANGE(12, 153, 1),
624 CYGNUS_PINRANGE(13, 127, 3),
625 CYGNUS_PINRANGE(16, 140, 1),
626 CYGNUS_PINRANGE(17, 145, 7),
627 CYGNUS_PINRANGE(24, 130, 10),
628 CYGNUS_PINRANGE(34, 141, 4),
629 CYGNUS_PINRANGE(38, 54, 1),
630 CYGNUS_PINRANGE(39, 56, 3),
631 CYGNUS_PINRANGE(42, 60, 3),
632 CYGNUS_PINRANGE(45, 64, 3),
633 CYGNUS_PINRANGE(48, 68, 2),
634 CYGNUS_PINRANGE(50, 84, 6),
635 CYGNUS_PINRANGE(56, 94, 6),
636 CYGNUS_PINRANGE(62, 72, 1),
637 CYGNUS_PINRANGE(63, 70, 1),
638 CYGNUS_PINRANGE(64, 80, 1),
639 CYGNUS_PINRANGE(65, 74, 3),
640 CYGNUS_PINRANGE(68, 78, 1),
641 CYGNUS_PINRANGE(69, 82, 1),
642 CYGNUS_PINRANGE(70, 156, 17),
643 CYGNUS_PINRANGE(87, 104, 12),
644 CYGNUS_PINRANGE(99, 102, 2),
645 CYGNUS_PINRANGE(101, 90, 4),
646 CYGNUS_PINRANGE(105, 116, 10),
647 CYGNUS_PINRANGE(123, 11, 1),
648 CYGNUS_PINRANGE(124, 38, 4),
649 CYGNUS_PINRANGE(128, 43, 1),
650 CYGNUS_PINRANGE(129, 47, 1),
651 CYGNUS_PINRANGE(130, 49, 1),
652 CYGNUS_PINRANGE(131, 53, 1),
653 CYGNUS_PINRANGE(132, 55, 1),
654 CYGNUS_PINRANGE(133, 59, 1),
655 CYGNUS_PINRANGE(134, 63, 1),
656 CYGNUS_PINRANGE(135, 67, 1),
657 CYGNUS_PINRANGE(136, 71, 1),
658 CYGNUS_PINRANGE(137, 73, 1),
659 CYGNUS_PINRANGE(138, 77, 1),
660 CYGNUS_PINRANGE(139, 79, 1),
661 CYGNUS_PINRANGE(140, 81, 1),
662 CYGNUS_PINRANGE(141, 83, 1),
663 CYGNUS_PINRANGE(142, 10, 1)
664};
665
666/*
667 * The Cygnus IOMUX controller mainly supports group based mux configuration,
668 * but certain pins can be muxed to GPIO individually. Only the ASIU GPIO
669 * controller can support this, so it's an optional configuration
670 *
671 * Return -ENODEV means no support and that's fine
672 */
673static int cygnus_gpio_pinmux_add_range(struct cygnus_gpio *chip)
674{
675 struct device_node *node = chip->dev->of_node;
676 struct device_node *pinmux_node;
677 struct platform_device *pinmux_pdev;
678 struct gpio_chip *gc = &chip->gc;
679 int i, ret = 0;
680
681 /* parse DT to find the phandle to the pinmux controller */
682 pinmux_node = of_parse_phandle(node, "pinmux", 0);
683 if (!pinmux_node)
684 return -ENODEV;
685
686 pinmux_pdev = of_find_device_by_node(pinmux_node);
687 /* no longer need the pinmux node */
688 of_node_put(pinmux_node);
689 if (!pinmux_pdev) {
690 dev_err(chip->dev, "failed to get pinmux device\n");
691 return -EINVAL;
692 }
693
694 /* now need to create the mapping between local GPIO and PINMUX pins */
695 for (i = 0; i < ARRAY_SIZE(cygnus_gpio_pintable); i++) {
696 ret = gpiochip_add_pin_range(gc, dev_name(&pinmux_pdev->dev),
697 cygnus_gpio_pintable[i].offset,
698 cygnus_gpio_pintable[i].pin_base,
699 cygnus_gpio_pintable[i].num_pins);
700 if (ret) {
701 dev_err(chip->dev, "unable to add GPIO pin range\n");
702 goto err_put_device;
703 }
704 }
705
706 chip->pinmux_is_supported = true;
707
708 /* no need for pinmux_pdev device reference anymore */
709 put_device(&pinmux_pdev->dev);
710 return 0;
711
712err_put_device:
713 put_device(&pinmux_pdev->dev);
714 gpiochip_remove_pin_ranges(gc);
715 return ret;
716}
717
718/*
719 * Cygnus GPIO controller supports some PINCONF related configurations such as
720 * pull up, pull down, and drive strength, when the pin is configured to GPIO
721 *
722 * Here a local pinctrl device is created with simple 1-to-1 pin mapping to the
723 * local GPIO pins
724 */
725static int cygnus_gpio_register_pinconf(struct cygnus_gpio *chip)
726{
727 struct pinctrl_desc *pctldesc = &chip->pctldesc;
728 struct pinctrl_pin_desc *pins;
729 struct gpio_chip *gc = &chip->gc;
730 int i;
731
732 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
733 if (!pins)
734 return -ENOMEM;
735
736 for (i = 0; i < gc->ngpio; i++) {
737 pins[i].number = i;
738 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
739 "gpio-%d", i);
740 if (!pins[i].name)
741 return -ENOMEM;
742 }
743
744 pctldesc->name = dev_name(chip->dev);
745 pctldesc->pctlops = &cygnus_pctrl_ops;
746 pctldesc->pins = pins;
747 pctldesc->npins = gc->ngpio;
748 pctldesc->confops = &cygnus_pconf_ops;
749
750 chip->pctl = pinctrl_register(pctldesc, chip->dev, chip);
751 if (!chip->pctl) {
752 dev_err(chip->dev, "unable to register pinctrl device\n");
753 return -EINVAL;
754 }
755
756 return 0;
757}
758
759static void cygnus_gpio_unregister_pinconf(struct cygnus_gpio *chip)
760{
761 if (chip->pctl)
762 pinctrl_unregister(chip->pctl);
763}
764
765struct cygnus_gpio_data {
766 unsigned num_gpios;
767};
768
769static const struct cygnus_gpio_data cygnus_cmm_gpio_data = {
770 .num_gpios = 24,
771};
772
773static const struct cygnus_gpio_data cygnus_asiu_gpio_data = {
774 .num_gpios = 146,
775};
776
777static const struct cygnus_gpio_data cygnus_crmu_gpio_data = {
778 .num_gpios = 6,
779};
780
781static const struct of_device_id cygnus_gpio_of_match[] = {
782 {
783 .compatible = "brcm,cygnus-ccm-gpio",
784 .data = &cygnus_cmm_gpio_data,
785 },
786 {
787 .compatible = "brcm,cygnus-asiu-gpio",
788 .data = &cygnus_asiu_gpio_data,
789 },
790 {
791 .compatible = "brcm,cygnus-crmu-gpio",
792 .data = &cygnus_crmu_gpio_data,
793 }
794};
795
796static int cygnus_gpio_probe(struct platform_device *pdev)
797{
798 struct device *dev = &pdev->dev;
799 struct resource *res;
800 struct cygnus_gpio *chip;
801 struct gpio_chip *gc;
802 u32 ngpios;
803 int irq, ret;
804 const struct of_device_id *match;
805 const struct cygnus_gpio_data *gpio_data;
806
807 match = of_match_device(cygnus_gpio_of_match, dev);
808 if (!match)
809 return -ENODEV;
810 gpio_data = match->data;
811 ngpios = gpio_data->num_gpios;
812
813 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
814 if (!chip)
815 return -ENOMEM;
816
817 chip->dev = dev;
818 platform_set_drvdata(pdev, chip);
819
820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
821 chip->base = devm_ioremap_resource(dev, res);
822 if (IS_ERR(chip->base)) {
823 dev_err(dev, "unable to map I/O memory\n");
824 return PTR_ERR(chip->base);
825 }
826
827 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
828 if (res) {
829 chip->io_ctrl = devm_ioremap_resource(dev, res);
830 if (IS_ERR(chip->io_ctrl)) {
831 dev_err(dev, "unable to map I/O memory\n");
832 return PTR_ERR(chip->io_ctrl);
833 }
834 }
835
836 spin_lock_init(&chip->lock);
837
838 gc = &chip->gc;
839 gc->base = -1;
840 gc->ngpio = ngpios;
841 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
842 gc->label = dev_name(dev);
843 gc->dev = dev;
844 gc->of_node = dev->of_node;
845 gc->request = cygnus_gpio_request;
846 gc->free = cygnus_gpio_free;
847 gc->direction_input = cygnus_gpio_direction_input;
848 gc->direction_output = cygnus_gpio_direction_output;
849 gc->set = cygnus_gpio_set;
850 gc->get = cygnus_gpio_get;
851
852 ret = gpiochip_add(gc);
853 if (ret < 0) {
854 dev_err(dev, "unable to add GPIO chip\n");
855 return ret;
856 }
857
858 ret = cygnus_gpio_pinmux_add_range(chip);
859 if (ret && ret != -ENODEV) {
860 dev_err(dev, "unable to add GPIO pin range\n");
861 goto err_rm_gpiochip;
862 }
863
864 ret = cygnus_gpio_register_pinconf(chip);
865 if (ret) {
866 dev_err(dev, "unable to register pinconf\n");
867 goto err_rm_gpiochip;
868 }
869
870 /* optional GPIO interrupt support */
871 irq = platform_get_irq(pdev, 0);
872 if (irq) {
873 ret = gpiochip_irqchip_add(gc, &cygnus_gpio_irq_chip, 0,
874 handle_simple_irq, IRQ_TYPE_NONE);
875 if (ret) {
876 dev_err(dev, "no GPIO irqchip\n");
877 goto err_unregister_pinconf;
878 }
879
880 gpiochip_set_chained_irqchip(gc, &cygnus_gpio_irq_chip, irq,
881 cygnus_gpio_irq_handler);
882 }
883
884 return 0;
885
886err_unregister_pinconf:
887 cygnus_gpio_unregister_pinconf(chip);
888
889err_rm_gpiochip:
890 gpiochip_remove(gc);
891
892 return ret;
893}
894
895static struct platform_driver cygnus_gpio_driver = {
896 .driver = {
897 .name = "cygnus-gpio",
898 .of_match_table = cygnus_gpio_of_match,
899 },
900 .probe = cygnus_gpio_probe,
901};
902
903static int __init cygnus_gpio_init(void)
904{
905 return platform_driver_probe(&cygnus_gpio_driver, cygnus_gpio_probe);
906}
907arch_initcall_sync(cygnus_gpio_init);
diff --git a/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
new file mode 100644
index 000000000000..f9a9283caf81
--- /dev/null
+++ b/drivers/pinctrl/bcm/pinctrl-cygnus-mux.c
@@ -0,0 +1,1022 @@
1/* Copyright (C) 2014-2015 Broadcom Corporation
2 *
3 * This program is free software; you can redistribute it and/or
4 * modify it under the terms of the GNU General Public License as
5 * published by the Free Software Foundation version 2.
6 *
7 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
8 * kind, whether express or implied; without even the implied warranty
9 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * This file contains the Cygnus IOMUX driver that supports group based PINMUX
13 * configuration. Although PINMUX configuration is mainly group based, the
14 * Cygnus IOMUX controller allows certain pins to be individually muxed to GPIO
15 * function, and therefore be controlled by the Cygnus ASIU GPIO controller
16 */
17
18#include <linux/err.h>
19#include <linux/io.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/slab.h>
23#include <linux/platform_device.h>
24#include <linux/pinctrl/pinctrl.h>
25#include <linux/pinctrl/pinmux.h>
26#include <linux/pinctrl/pinconf.h>
27#include <linux/pinctrl/pinconf-generic.h>
28#include "../core.h"
29#include "../pinctrl-utils.h"
30
31#define CYGNUS_NUM_IOMUX_REGS 8
32#define CYGNUS_NUM_MUX_PER_REG 8
33#define CYGNUS_NUM_IOMUX (CYGNUS_NUM_IOMUX_REGS * \
34 CYGNUS_NUM_MUX_PER_REG)
35
36/*
37 * Cygnus IOMUX register description
38 *
39 * @offset: register offset for mux configuration of a group
40 * @shift: bit shift for mux configuration of a group
41 * @alt: alternate function to set to
42 */
43struct cygnus_mux {
44 unsigned int offset;
45 unsigned int shift;
46 unsigned int alt;
47};
48
49/*
50 * Keep track of Cygnus IOMUX configuration and prevent double configuration
51 *
52 * @cygnus_mux: Cygnus IOMUX register description
53 * @is_configured: flag to indicate whether a mux setting has already been
54 * configured
55 */
56struct cygnus_mux_log {
57 struct cygnus_mux mux;
58 bool is_configured;
59};
60
61/*
62 * Group based IOMUX configuration
63 *
64 * @name: name of the group
65 * @pins: array of pins used by this group
66 * @num_pins: total number of pins used by this group
67 * @mux: Cygnus group based IOMUX configuration
68 */
69struct cygnus_pin_group {
70 const char *name;
71 const unsigned *pins;
72 unsigned num_pins;
73 struct cygnus_mux mux;
74};
75
76/*
77 * Cygnus mux function and supported pin groups
78 *
79 * @name: name of the function
80 * @groups: array of groups that can be supported by this function
81 * @num_groups: total number of groups that can be supported by this function
82 */
83struct cygnus_pin_function {
84 const char *name;
85 const char * const *groups;
86 unsigned num_groups;
87};
88
89/*
90 * Cygnus IOMUX pinctrl core
91 *
92 * @pctl: pointer to pinctrl_dev
93 * @dev: pointer to device
94 * @base0: first I/O register base of the Cygnus IOMUX controller
95 * @base1: second I/O register base
96 * @groups: pointer to array of groups
97 * @num_groups: total number of groups
98 * @functions: pointer to array of functions
99 * @num_functions: total number of functions
100 * @mux_log: pointer to the array of mux logs
101 * @lock: lock to protect register access
102 */
103struct cygnus_pinctrl {
104 struct pinctrl_dev *pctl;
105 struct device *dev;
106 void __iomem *base0;
107 void __iomem *base1;
108
109 const struct cygnus_pin_group *groups;
110 unsigned num_groups;
111
112 const struct cygnus_pin_function *functions;
113 unsigned num_functions;
114
115 struct cygnus_mux_log *mux_log;
116
117 spinlock_t lock;
118};
119
120/*
121 * Certain pins can be individually muxed to GPIO function
122 *
123 * @is_supported: flag to indicate GPIO mux is supported for this pin
124 * @offset: register offset for GPIO mux override of a pin
125 * @shift: bit shift for GPIO mux override of a pin
126 */
127struct cygnus_gpio_mux {
128 int is_supported;
129 unsigned int offset;
130 unsigned int shift;
131};
132
133/*
134 * Description of a pin in Cygnus
135 *
136 * @pin: pin number
137 * @name: pin name
138 * @gpio_mux: GPIO override related information
139 */
140struct cygnus_pin {
141 unsigned pin;
142 char *name;
143 struct cygnus_gpio_mux gpio_mux;
144};
145
146#define CYGNUS_PIN_DESC(p, n, i, o, s) \
147{ \
148 .pin = p, \
149 .name = n, \
150 .gpio_mux = { \
151 .is_supported = i, \
152 .offset = o, \
153 .shift = s, \
154 }, \
155}
156
157/*
158 * List of pins in Cygnus
159 */
160static struct cygnus_pin cygnus_pins[] = {
161 CYGNUS_PIN_DESC(0, "ext_device_reset_n", 0, 0, 0),
162 CYGNUS_PIN_DESC(1, "chip_mode0", 0, 0, 0),
163 CYGNUS_PIN_DESC(2, "chip_mode1", 0, 0, 0),
164 CYGNUS_PIN_DESC(3, "chip_mode2", 0, 0, 0),
165 CYGNUS_PIN_DESC(4, "chip_mode3", 0, 0, 0),
166 CYGNUS_PIN_DESC(5, "chip_mode4", 0, 0, 0),
167 CYGNUS_PIN_DESC(6, "bsc0_scl", 0, 0, 0),
168 CYGNUS_PIN_DESC(7, "bsc0_sda", 0, 0, 0),
169 CYGNUS_PIN_DESC(8, "bsc1_scl", 0, 0, 0),
170 CYGNUS_PIN_DESC(9, "bsc1_sda", 0, 0, 0),
171 CYGNUS_PIN_DESC(10, "d1w_dq", 1, 0x28, 0),
172 CYGNUS_PIN_DESC(11, "d1wowstz_l", 1, 0x4, 28),
173 CYGNUS_PIN_DESC(12, "gpio0", 0, 0, 0),
174 CYGNUS_PIN_DESC(13, "gpio1", 0, 0, 0),
175 CYGNUS_PIN_DESC(14, "gpio2", 0, 0, 0),
176 CYGNUS_PIN_DESC(15, "gpio3", 0, 0, 0),
177 CYGNUS_PIN_DESC(16, "gpio4", 0, 0, 0),
178 CYGNUS_PIN_DESC(17, "gpio5", 0, 0, 0),
179 CYGNUS_PIN_DESC(18, "gpio6", 0, 0, 0),
180 CYGNUS_PIN_DESC(19, "gpio7", 0, 0, 0),
181 CYGNUS_PIN_DESC(20, "gpio8", 0, 0, 0),
182 CYGNUS_PIN_DESC(21, "gpio9", 0, 0, 0),
183 CYGNUS_PIN_DESC(22, "gpio10", 0, 0, 0),
184 CYGNUS_PIN_DESC(23, "gpio11", 0, 0, 0),
185 CYGNUS_PIN_DESC(24, "gpio12", 0, 0, 0),
186 CYGNUS_PIN_DESC(25, "gpio13", 0, 0, 0),
187 CYGNUS_PIN_DESC(26, "gpio14", 0, 0, 0),
188 CYGNUS_PIN_DESC(27, "gpio15", 0, 0, 0),
189 CYGNUS_PIN_DESC(28, "gpio16", 0, 0, 0),
190 CYGNUS_PIN_DESC(29, "gpio17", 0, 0, 0),
191 CYGNUS_PIN_DESC(30, "gpio18", 0, 0, 0),
192 CYGNUS_PIN_DESC(31, "gpio19", 0, 0, 0),
193 CYGNUS_PIN_DESC(32, "gpio20", 0, 0, 0),
194 CYGNUS_PIN_DESC(33, "gpio21", 0, 0, 0),
195 CYGNUS_PIN_DESC(34, "gpio22", 0, 0, 0),
196 CYGNUS_PIN_DESC(35, "gpio23", 0, 0, 0),
197 CYGNUS_PIN_DESC(36, "mdc", 0, 0, 0),
198 CYGNUS_PIN_DESC(37, "mdio", 0, 0, 0),
199 CYGNUS_PIN_DESC(38, "pwm0", 1, 0x10, 30),
200 CYGNUS_PIN_DESC(39, "pwm1", 1, 0x10, 28),
201 CYGNUS_PIN_DESC(40, "pwm2", 1, 0x10, 26),
202 CYGNUS_PIN_DESC(41, "pwm3", 1, 0x10, 24),
203 CYGNUS_PIN_DESC(42, "sc0_clk", 1, 0x10, 22),
204 CYGNUS_PIN_DESC(43, "sc0_cmdvcc_l", 1, 0x10, 20),
205 CYGNUS_PIN_DESC(44, "sc0_detect", 1, 0x10, 18),
206 CYGNUS_PIN_DESC(45, "sc0_fcb", 1, 0x10, 16),
207 CYGNUS_PIN_DESC(46, "sc0_io", 1, 0x10, 14),
208 CYGNUS_PIN_DESC(47, "sc0_rst_l", 1, 0x10, 12),
209 CYGNUS_PIN_DESC(48, "sc1_clk", 1, 0x10, 10),
210 CYGNUS_PIN_DESC(49, "sc1_cmdvcc_l", 1, 0x10, 8),
211 CYGNUS_PIN_DESC(50, "sc1_detect", 1, 0x10, 6),
212 CYGNUS_PIN_DESC(51, "sc1_fcb", 1, 0x10, 4),
213 CYGNUS_PIN_DESC(52, "sc1_io", 1, 0x10, 2),
214 CYGNUS_PIN_DESC(53, "sc1_rst_l", 1, 0x10, 0),
215 CYGNUS_PIN_DESC(54, "spi0_clk", 1, 0x18, 10),
216 CYGNUS_PIN_DESC(55, "spi0_mosi", 1, 0x18, 6),
217 CYGNUS_PIN_DESC(56, "spi0_miso", 1, 0x18, 8),
218 CYGNUS_PIN_DESC(57, "spi0_ss", 1, 0x18, 4),
219 CYGNUS_PIN_DESC(58, "spi1_clk", 1, 0x18, 2),
220 CYGNUS_PIN_DESC(59, "spi1_mosi", 1, 0x1c, 30),
221 CYGNUS_PIN_DESC(60, "spi1_miso", 1, 0x18, 0),
222 CYGNUS_PIN_DESC(61, "spi1_ss", 1, 0x1c, 28),
223 CYGNUS_PIN_DESC(62, "spi2_clk", 1, 0x1c, 26),
224 CYGNUS_PIN_DESC(63, "spi2_mosi", 1, 0x1c, 22),
225 CYGNUS_PIN_DESC(64, "spi2_miso", 1, 0x1c, 24),
226 CYGNUS_PIN_DESC(65, "spi2_ss", 1, 0x1c, 20),
227 CYGNUS_PIN_DESC(66, "spi3_clk", 1, 0x1c, 18),
228 CYGNUS_PIN_DESC(67, "spi3_mosi", 1, 0x1c, 14),
229 CYGNUS_PIN_DESC(68, "spi3_miso", 1, 0x1c, 16),
230 CYGNUS_PIN_DESC(69, "spi3_ss", 1, 0x1c, 12),
231 CYGNUS_PIN_DESC(70, "uart0_cts", 1, 0x1c, 10),
232 CYGNUS_PIN_DESC(71, "uart0_rts", 1, 0x1c, 8),
233 CYGNUS_PIN_DESC(72, "uart0_rx", 1, 0x1c, 6),
234 CYGNUS_PIN_DESC(73, "uart0_tx", 1, 0x1c, 4),
235 CYGNUS_PIN_DESC(74, "uart1_cts", 1, 0x1c, 2),
236 CYGNUS_PIN_DESC(75, "uart1_dcd", 1, 0x1c, 0),
237 CYGNUS_PIN_DESC(76, "uart1_dsr", 1, 0x20, 14),
238 CYGNUS_PIN_DESC(77, "uart1_dtr", 1, 0x20, 12),
239 CYGNUS_PIN_DESC(78, "uart1_ri", 1, 0x20, 10),
240 CYGNUS_PIN_DESC(79, "uart1_rts", 1, 0x20, 8),
241 CYGNUS_PIN_DESC(80, "uart1_rx", 1, 0x20, 6),
242 CYGNUS_PIN_DESC(81, "uart1_tx", 1, 0x20, 4),
243 CYGNUS_PIN_DESC(82, "uart3_rx", 1, 0x20, 2),
244 CYGNUS_PIN_DESC(83, "uart3_tx", 1, 0x20, 0),
245 CYGNUS_PIN_DESC(84, "sdio1_clk_sdcard", 1, 0x14, 6),
246 CYGNUS_PIN_DESC(85, "sdio1_cmd", 1, 0x14, 4),
247 CYGNUS_PIN_DESC(86, "sdio1_data0", 1, 0x14, 2),
248 CYGNUS_PIN_DESC(87, "sdio1_data1", 1, 0x14, 0),
249 CYGNUS_PIN_DESC(88, "sdio1_data2", 1, 0x18, 30),
250 CYGNUS_PIN_DESC(89, "sdio1_data3", 1, 0x18, 28),
251 CYGNUS_PIN_DESC(90, "sdio1_wp_n", 1, 0x18, 24),
252 CYGNUS_PIN_DESC(91, "sdio1_card_rst", 1, 0x14, 10),
253 CYGNUS_PIN_DESC(92, "sdio1_led_on", 1, 0x18, 26),
254 CYGNUS_PIN_DESC(93, "sdio1_cd", 1, 0x14, 8),
255 CYGNUS_PIN_DESC(94, "sdio0_clk_sdcard", 1, 0x14, 26),
256 CYGNUS_PIN_DESC(95, "sdio0_cmd", 1, 0x14, 24),
257 CYGNUS_PIN_DESC(96, "sdio0_data0", 1, 0x14, 22),
258 CYGNUS_PIN_DESC(97, "sdio0_data1", 1, 0x14, 20),
259 CYGNUS_PIN_DESC(98, "sdio0_data2", 1, 0x14, 18),
260 CYGNUS_PIN_DESC(99, "sdio0_data3", 1, 0x14, 16),
261 CYGNUS_PIN_DESC(100, "sdio0_wp_n", 1, 0x14, 12),
262 CYGNUS_PIN_DESC(101, "sdio0_card_rst", 1, 0x14, 30),
263 CYGNUS_PIN_DESC(102, "sdio0_led_on", 1, 0x14, 14),
264 CYGNUS_PIN_DESC(103, "sdio0_cd", 1, 0x14, 28),
265 CYGNUS_PIN_DESC(104, "sflash_clk", 1, 0x18, 22),
266 CYGNUS_PIN_DESC(105, "sflash_cs_l", 1, 0x18, 20),
267 CYGNUS_PIN_DESC(106, "sflash_mosi", 1, 0x18, 14),
268 CYGNUS_PIN_DESC(107, "sflash_miso", 1, 0x18, 16),
269 CYGNUS_PIN_DESC(108, "sflash_wp_n", 1, 0x18, 12),
270 CYGNUS_PIN_DESC(109, "sflash_hold_n", 1, 0x18, 18),
271 CYGNUS_PIN_DESC(110, "nand_ale", 1, 0xc, 30),
272 CYGNUS_PIN_DESC(111, "nand_ce0_l", 1, 0xc, 28),
273 CYGNUS_PIN_DESC(112, "nand_ce1_l", 1, 0xc, 26),
274 CYGNUS_PIN_DESC(113, "nand_cle", 1, 0xc, 24),
275 CYGNUS_PIN_DESC(114, "nand_dq0", 1, 0xc, 22),
276 CYGNUS_PIN_DESC(115, "nand_dq1", 1, 0xc, 20),
277 CYGNUS_PIN_DESC(116, "nand_dq2", 1, 0xc, 18),
278 CYGNUS_PIN_DESC(117, "nand_dq3", 1, 0xc, 16),
279 CYGNUS_PIN_DESC(118, "nand_dq4", 1, 0xc, 14),
280 CYGNUS_PIN_DESC(119, "nand_dq5", 1, 0xc, 12),
281 CYGNUS_PIN_DESC(120, "nand_dq6", 1, 0xc, 10),
282 CYGNUS_PIN_DESC(121, "nand_dq7", 1, 0xc, 8),
283 CYGNUS_PIN_DESC(122, "nand_rb_l", 1, 0xc, 6),
284 CYGNUS_PIN_DESC(123, "nand_re_l", 1, 0xc, 4),
285 CYGNUS_PIN_DESC(124, "nand_we_l", 1, 0xc, 2),
286 CYGNUS_PIN_DESC(125, "nand_wp_l", 1, 0xc, 0),
287 CYGNUS_PIN_DESC(126, "lcd_clac", 1, 0x4, 26),
288 CYGNUS_PIN_DESC(127, "lcd_clcp", 1, 0x4, 24),
289 CYGNUS_PIN_DESC(128, "lcd_cld0", 1, 0x4, 22),
290 CYGNUS_PIN_DESC(129, "lcd_cld1", 1, 0x4, 0),
291 CYGNUS_PIN_DESC(130, "lcd_cld10", 1, 0x4, 20),
292 CYGNUS_PIN_DESC(131, "lcd_cld11", 1, 0x4, 18),
293 CYGNUS_PIN_DESC(132, "lcd_cld12", 1, 0x4, 16),
294 CYGNUS_PIN_DESC(133, "lcd_cld13", 1, 0x4, 14),
295 CYGNUS_PIN_DESC(134, "lcd_cld14", 1, 0x4, 12),
296 CYGNUS_PIN_DESC(135, "lcd_cld15", 1, 0x4, 10),
297 CYGNUS_PIN_DESC(136, "lcd_cld16", 1, 0x4, 8),
298 CYGNUS_PIN_DESC(137, "lcd_cld17", 1, 0x4, 6),
299 CYGNUS_PIN_DESC(138, "lcd_cld18", 1, 0x4, 4),
300 CYGNUS_PIN_DESC(139, "lcd_cld19", 1, 0x4, 2),
301 CYGNUS_PIN_DESC(140, "lcd_cld2", 1, 0x8, 22),
302 CYGNUS_PIN_DESC(141, "lcd_cld20", 1, 0x8, 30),
303 CYGNUS_PIN_DESC(142, "lcd_cld21", 1, 0x8, 28),
304 CYGNUS_PIN_DESC(143, "lcd_cld22", 1, 0x8, 26),
305 CYGNUS_PIN_DESC(144, "lcd_cld23", 1, 0x8, 24),
306 CYGNUS_PIN_DESC(145, "lcd_cld3", 1, 0x8, 20),
307 CYGNUS_PIN_DESC(146, "lcd_cld4", 1, 0x8, 18),
308 CYGNUS_PIN_DESC(147, "lcd_cld5", 1, 0x8, 16),
309 CYGNUS_PIN_DESC(148, "lcd_cld6", 1, 0x8, 14),
310 CYGNUS_PIN_DESC(149, "lcd_cld7", 1, 0x8, 12),
311 CYGNUS_PIN_DESC(150, "lcd_cld8", 1, 0x8, 10),
312 CYGNUS_PIN_DESC(151, "lcd_cld9", 1, 0x8, 8),
313 CYGNUS_PIN_DESC(152, "lcd_clfp", 1, 0x8, 6),
314 CYGNUS_PIN_DESC(153, "lcd_clle", 1, 0x8, 4),
315 CYGNUS_PIN_DESC(154, "lcd_cllp", 1, 0x8, 2),
316 CYGNUS_PIN_DESC(155, "lcd_clpower", 1, 0x8, 0),
317 CYGNUS_PIN_DESC(156, "camera_vsync", 1, 0x4, 30),
318 CYGNUS_PIN_DESC(157, "camera_trigger", 1, 0x0, 0),
319 CYGNUS_PIN_DESC(158, "camera_strobe", 1, 0x0, 2),
320 CYGNUS_PIN_DESC(159, "camera_standby", 1, 0x0, 4),
321 CYGNUS_PIN_DESC(160, "camera_reset_n", 1, 0x0, 6),
322 CYGNUS_PIN_DESC(161, "camera_pixdata9", 1, 0x0, 8),
323 CYGNUS_PIN_DESC(162, "camera_pixdata8", 1, 0x0, 10),
324 CYGNUS_PIN_DESC(163, "camera_pixdata7", 1, 0x0, 12),
325 CYGNUS_PIN_DESC(164, "camera_pixdata6", 1, 0x0, 14),
326 CYGNUS_PIN_DESC(165, "camera_pixdata5", 1, 0x0, 16),
327 CYGNUS_PIN_DESC(166, "camera_pixdata4", 1, 0x0, 18),
328 CYGNUS_PIN_DESC(167, "camera_pixdata3", 1, 0x0, 20),
329 CYGNUS_PIN_DESC(168, "camera_pixdata2", 1, 0x0, 22),
330 CYGNUS_PIN_DESC(169, "camera_pixdata1", 1, 0x0, 24),
331 CYGNUS_PIN_DESC(170, "camera_pixdata0", 1, 0x0, 26),
332 CYGNUS_PIN_DESC(171, "camera_pixclk", 1, 0x0, 28),
333 CYGNUS_PIN_DESC(172, "camera_hsync", 1, 0x0, 30),
334 CYGNUS_PIN_DESC(173, "camera_pll_ref_clk", 0, 0, 0),
335 CYGNUS_PIN_DESC(174, "usb_id_indication", 0, 0, 0),
336 CYGNUS_PIN_DESC(175, "usb_vbus_indication", 0, 0, 0),
337 CYGNUS_PIN_DESC(176, "gpio0_3p3", 0, 0, 0),
338 CYGNUS_PIN_DESC(177, "gpio1_3p3", 0, 0, 0),
339 CYGNUS_PIN_DESC(178, "gpio2_3p3", 0, 0, 0),
340 CYGNUS_PIN_DESC(179, "gpio3_3p3", 0, 0, 0),
341};
342
343/*
344 * List of groups of pins
345 */
346static const unsigned bsc1_pins[] = { 8, 9 };
347static const unsigned pcie_clkreq_pins[] = { 8, 9 };
348
349static const unsigned i2s2_0_pins[] = { 12 };
350static const unsigned i2s2_1_pins[] = { 13 };
351static const unsigned i2s2_2_pins[] = { 14 };
352static const unsigned i2s2_3_pins[] = { 15 };
353static const unsigned i2s2_4_pins[] = { 16 };
354
355static const unsigned pwm4_pins[] = { 17 };
356static const unsigned pwm5_pins[] = { 18 };
357
358static const unsigned key0_pins[] = { 20 };
359static const unsigned key1_pins[] = { 21 };
360static const unsigned key2_pins[] = { 22 };
361static const unsigned key3_pins[] = { 23 };
362static const unsigned key4_pins[] = { 24 };
363static const unsigned key5_pins[] = { 25 };
364
365static const unsigned key6_pins[] = { 26 };
366static const unsigned audio_dte0_pins[] = { 26 };
367
368static const unsigned key7_pins[] = { 27 };
369static const unsigned audio_dte1_pins[] = { 27 };
370
371static const unsigned key8_pins[] = { 28 };
372static const unsigned key9_pins[] = { 29 };
373static const unsigned key10_pins[] = { 30 };
374static const unsigned key11_pins[] = { 31 };
375static const unsigned key12_pins[] = { 32 };
376static const unsigned key13_pins[] = { 33 };
377
378static const unsigned key14_pins[] = { 34 };
379static const unsigned audio_dte2_pins[] = { 34 };
380
381static const unsigned key15_pins[] = { 35 };
382static const unsigned audio_dte3_pins[] = { 35 };
383
384static const unsigned pwm0_pins[] = { 38 };
385static const unsigned pwm1_pins[] = { 39 };
386static const unsigned pwm2_pins[] = { 40 };
387static const unsigned pwm3_pins[] = { 41 };
388
389static const unsigned sdio0_pins[] = { 94, 95, 96, 97, 98, 99 };
390
391static const unsigned smart_card0_pins[] = { 42, 43, 44, 46, 47 };
392static const unsigned i2s0_0_pins[] = { 42, 43, 44, 46 };
393static const unsigned spdif_pins[] = { 47 };
394
395static const unsigned smart_card1_pins[] = { 48, 49, 50, 52, 53 };
396static const unsigned i2s1_0_pins[] = { 48, 49, 50, 52 };
397
398static const unsigned spi0_pins[] = { 54, 55, 56, 57 };
399
400static const unsigned spi1_pins[] = { 58, 59, 60, 61 };
401
402static const unsigned spi2_pins[] = { 62, 63, 64, 65 };
403
404static const unsigned spi3_pins[] = { 66, 67, 68, 69 };
405static const unsigned sw_led0_0_pins[] = { 66, 67, 68, 69 };
406
407static const unsigned d1w_pins[] = { 10, 11 };
408static const unsigned uart4_pins[] = { 10, 11 };
409static const unsigned sw_led2_0_pins[] = { 10, 11 };
410
411static const unsigned lcd_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,
412 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
413 148, 149, 150, 151, 152, 153, 154, 155 };
414static const unsigned sram_0_pins[] = { 126, 127, 128, 129, 130, 131, 132, 133,
415 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147,
416 148, 149, 150, 151, 152, 153, 154, 155 };
417static const unsigned spi5_pins[] = { 141, 142, 143, 144 };
418
419static const unsigned uart0_pins[] = { 70, 71, 72, 73 };
420static const unsigned sw_led0_1_pins[] = { 70, 71, 72, 73 };
421
422static const unsigned uart1_dte_pins[] = { 75, 76, 77, 78 };
423static const unsigned uart2_pins[] = { 75, 76, 77, 78 };
424
425static const unsigned uart1_pins[] = { 74, 79, 80, 81 };
426
427static const unsigned uart3_pins[] = { 82, 83 };
428
429static const unsigned qspi_0_pins[] = { 104, 105, 106, 107 };
430
431static const unsigned nand_pins[] = { 110, 111, 112, 113, 114, 115, 116, 117,
432 118, 119, 120, 121, 122, 123, 124, 125 };
433
434static const unsigned sdio0_cd_pins[] = { 103 };
435
436static const unsigned sdio0_mmc_pins[] = { 100, 101, 102 };
437
438static const unsigned sdio1_data_0_pins[] = { 86, 87 };
439static const unsigned can0_pins[] = { 86, 87 };
440static const unsigned spi4_0_pins[] = { 86, 87 };
441
442static const unsigned sdio1_data_1_pins[] = { 88, 89 };
443static const unsigned can1_pins[] = { 88, 89 };
444static const unsigned spi4_1_pins[] = { 88, 89 };
445
446static const unsigned sdio1_cd_pins[] = { 93 };
447
448static const unsigned sdio1_led_pins[] = { 84, 85 };
449static const unsigned sw_led2_1_pins[] = { 84, 85 };
450
451static const unsigned sdio1_mmc_pins[] = { 90, 91, 92 };
452
453static const unsigned cam_led_pins[] = { 156, 157, 158, 159, 160 };
454static const unsigned sw_led1_pins[] = { 156, 157, 158, 159 };
455
456static const unsigned cam_0_pins[] = { 169, 170, 171, 169, 170 };
457
458static const unsigned cam_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,
459 168 };
460static const unsigned sram_1_pins[] = { 161, 162, 163, 164, 165, 166, 167,
461 168 };
462
463static const unsigned qspi_1_pins[] = { 108, 109 };
464
465static const unsigned smart_card0_fcb_pins[] = { 45 };
466static const unsigned i2s0_1_pins[] = { 45 };
467
468static const unsigned smart_card1_fcb_pins[] = { 51 };
469static const unsigned i2s1_1_pins[] = { 51 };
470
471static const unsigned gpio0_3p3_pins[] = { 176 };
472static const unsigned usb0_oc_pins[] = { 176 };
473
474static const unsigned gpio1_3p3_pins[] = { 177 };
475static const unsigned usb1_oc_pins[] = { 177 };
476
477static const unsigned gpio2_3p3_pins[] = { 178 };
478static const unsigned usb2_oc_pins[] = { 178 };
479
480#define CYGNUS_PIN_GROUP(group_name, off, sh, al) \
481{ \
482 .name = __stringify(group_name) "_grp", \
483 .pins = group_name ## _pins, \
484 .num_pins = ARRAY_SIZE(group_name ## _pins), \
485 .mux = { \
486 .offset = off, \
487 .shift = sh, \
488 .alt = al, \
489 } \
490}
491
492/*
493 * List of Cygnus pin groups
494 */
495static const struct cygnus_pin_group cygnus_pin_groups[] = {
496 CYGNUS_PIN_GROUP(i2s2_0, 0x0, 0, 2),
497 CYGNUS_PIN_GROUP(i2s2_1, 0x0, 4, 2),
498 CYGNUS_PIN_GROUP(i2s2_2, 0x0, 8, 2),
499 CYGNUS_PIN_GROUP(i2s2_3, 0x0, 12, 2),
500 CYGNUS_PIN_GROUP(i2s2_4, 0x0, 16, 2),
501 CYGNUS_PIN_GROUP(pwm4, 0x0, 20, 0),
502 CYGNUS_PIN_GROUP(pwm5, 0x0, 24, 2),
503 CYGNUS_PIN_GROUP(key0, 0x4, 0, 1),
504 CYGNUS_PIN_GROUP(key1, 0x4, 4, 1),
505 CYGNUS_PIN_GROUP(key2, 0x4, 8, 1),
506 CYGNUS_PIN_GROUP(key3, 0x4, 12, 1),
507 CYGNUS_PIN_GROUP(key4, 0x4, 16, 1),
508 CYGNUS_PIN_GROUP(key5, 0x4, 20, 1),
509 CYGNUS_PIN_GROUP(key6, 0x4, 24, 1),
510 CYGNUS_PIN_GROUP(audio_dte0, 0x4, 24, 2),
511 CYGNUS_PIN_GROUP(key7, 0x4, 28, 1),
512 CYGNUS_PIN_GROUP(audio_dte1, 0x4, 28, 2),
513 CYGNUS_PIN_GROUP(key8, 0x8, 0, 1),
514 CYGNUS_PIN_GROUP(key9, 0x8, 4, 1),
515 CYGNUS_PIN_GROUP(key10, 0x8, 8, 1),
516 CYGNUS_PIN_GROUP(key11, 0x8, 12, 1),
517 CYGNUS_PIN_GROUP(key12, 0x8, 16, 1),
518 CYGNUS_PIN_GROUP(key13, 0x8, 20, 1),
519 CYGNUS_PIN_GROUP(key14, 0x8, 24, 1),
520 CYGNUS_PIN_GROUP(audio_dte2, 0x8, 24, 2),
521 CYGNUS_PIN_GROUP(key15, 0x8, 28, 1),
522 CYGNUS_PIN_GROUP(audio_dte3, 0x8, 28, 2),
523 CYGNUS_PIN_GROUP(pwm0, 0xc, 0, 0),
524 CYGNUS_PIN_GROUP(pwm1, 0xc, 4, 0),
525 CYGNUS_PIN_GROUP(pwm2, 0xc, 8, 0),
526 CYGNUS_PIN_GROUP(pwm3, 0xc, 12, 0),
527 CYGNUS_PIN_GROUP(sdio0, 0xc, 16, 0),
528 CYGNUS_PIN_GROUP(smart_card0, 0xc, 20, 0),
529 CYGNUS_PIN_GROUP(i2s0_0, 0xc, 20, 1),
530 CYGNUS_PIN_GROUP(spdif, 0xc, 20, 1),
531 CYGNUS_PIN_GROUP(smart_card1, 0xc, 24, 0),
532 CYGNUS_PIN_GROUP(i2s1_0, 0xc, 24, 1),
533 CYGNUS_PIN_GROUP(spi0, 0x10, 0, 0),
534 CYGNUS_PIN_GROUP(spi1, 0x10, 4, 0),
535 CYGNUS_PIN_GROUP(spi2, 0x10, 8, 0),
536 CYGNUS_PIN_GROUP(spi3, 0x10, 12, 0),
537 CYGNUS_PIN_GROUP(sw_led0_0, 0x10, 12, 2),
538 CYGNUS_PIN_GROUP(d1w, 0x10, 16, 0),
539 CYGNUS_PIN_GROUP(uart4, 0x10, 16, 1),
540 CYGNUS_PIN_GROUP(sw_led2_0, 0x10, 16, 2),
541 CYGNUS_PIN_GROUP(lcd, 0x10, 20, 0),
542 CYGNUS_PIN_GROUP(sram_0, 0x10, 20, 1),
543 CYGNUS_PIN_GROUP(spi5, 0x10, 20, 2),
544 CYGNUS_PIN_GROUP(uart0, 0x14, 0, 0),
545 CYGNUS_PIN_GROUP(sw_led0_1, 0x14, 0, 2),
546 CYGNUS_PIN_GROUP(uart1_dte, 0x14, 4, 0),
547 CYGNUS_PIN_GROUP(uart2, 0x14, 4, 1),
548 CYGNUS_PIN_GROUP(uart1, 0x14, 8, 0),
549 CYGNUS_PIN_GROUP(uart3, 0x14, 12, 0),
550 CYGNUS_PIN_GROUP(qspi_0, 0x14, 16, 0),
551 CYGNUS_PIN_GROUP(nand, 0x14, 20, 0),
552 CYGNUS_PIN_GROUP(sdio0_cd, 0x18, 0, 0),
553 CYGNUS_PIN_GROUP(sdio0_mmc, 0x18, 4, 0),
554 CYGNUS_PIN_GROUP(sdio1_data_0, 0x18, 8, 0),
555 CYGNUS_PIN_GROUP(can0, 0x18, 8, 1),
556 CYGNUS_PIN_GROUP(spi4_0, 0x18, 8, 2),
557 CYGNUS_PIN_GROUP(sdio1_data_1, 0x18, 12, 0),
558 CYGNUS_PIN_GROUP(can1, 0x18, 12, 1),
559 CYGNUS_PIN_GROUP(spi4_1, 0x18, 12, 2),
560 CYGNUS_PIN_GROUP(sdio1_cd, 0x18, 16, 0),
561 CYGNUS_PIN_GROUP(sdio1_led, 0x18, 20, 0),
562 CYGNUS_PIN_GROUP(sw_led2_1, 0x18, 20, 2),
563 CYGNUS_PIN_GROUP(sdio1_mmc, 0x18, 24, 0),
564 CYGNUS_PIN_GROUP(cam_led, 0x1c, 0, 0),
565 CYGNUS_PIN_GROUP(sw_led1, 0x1c, 0, 1),
566 CYGNUS_PIN_GROUP(cam_0, 0x1c, 4, 0),
567 CYGNUS_PIN_GROUP(cam_1, 0x1c, 8, 0),
568 CYGNUS_PIN_GROUP(sram_1, 0x1c, 8, 1),
569 CYGNUS_PIN_GROUP(qspi_1, 0x1c, 12, 0),
570 CYGNUS_PIN_GROUP(bsc1, 0x1c, 16, 0),
571 CYGNUS_PIN_GROUP(pcie_clkreq, 0x1c, 16, 1),
572 CYGNUS_PIN_GROUP(smart_card0_fcb, 0x20, 0, 0),
573 CYGNUS_PIN_GROUP(i2s0_1, 0x20, 0, 1),
574 CYGNUS_PIN_GROUP(smart_card1_fcb, 0x20, 4, 0),
575 CYGNUS_PIN_GROUP(i2s1_1, 0x20, 4, 1),
576 CYGNUS_PIN_GROUP(gpio0_3p3, 0x28, 0, 0),
577 CYGNUS_PIN_GROUP(usb0_oc, 0x28, 0, 1),
578 CYGNUS_PIN_GROUP(gpio1_3p3, 0x28, 4, 0),
579 CYGNUS_PIN_GROUP(usb1_oc, 0x28, 4, 1),
580 CYGNUS_PIN_GROUP(gpio2_3p3, 0x28, 8, 0),
581 CYGNUS_PIN_GROUP(usb2_oc, 0x28, 8, 1),
582};
583
584/*
585 * List of groups supported by functions
586 */
587static const char * const i2s0_grps[] = { "i2s0_0_grp", "i2s0_1_grp" };
588static const char * const i2s1_grps[] = { "i2s1_0_grp", "i2s1_1_grp" };
589static const char * const i2s2_grps[] = { "i2s2_0_grp", "i2s2_1_grp",
590 "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" };
591static const char * const spdif_grps[] = { "spdif_grp" };
592static const char * const pwm0_grps[] = { "pwm0_grp" };
593static const char * const pwm1_grps[] = { "pwm1_grp" };
594static const char * const pwm2_grps[] = { "pwm2_grp" };
595static const char * const pwm3_grps[] = { "pwm3_grp" };
596static const char * const pwm4_grps[] = { "pwm4_grp" };
597static const char * const pwm5_grps[] = { "pwm5_grp" };
598static const char * const key_grps[] = { "key0_grp", "key1_grp", "key2_grp",
599 "key3_grp", "key4_grp", "key5_grp", "key6_grp", "key7_grp", "key8_grp",
600 "key9_grp", "key10_grp", "key11_grp", "key12_grp", "key13_grp",
601 "key14_grp", "key15_grp" };
602static const char * const audio_dte_grps[] = { "audio_dte0_grp",
603 "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" };
604static const char * const smart_card0_grps[] = { "smart_card0_grp",
605 "smart_card0_fcb_grp" };
606static const char * const smart_card1_grps[] = { "smart_card1_grp",
607 "smart_card1_fcb_grp" };
608static const char * const spi0_grps[] = { "spi0_grp" };
609static const char * const spi1_grps[] = { "spi1_grp" };
610static const char * const spi2_grps[] = { "spi2_grp" };
611static const char * const spi3_grps[] = { "spi3_grp" };
612static const char * const spi4_grps[] = { "spi4_0_grp", "spi4_1_grp" };
613static const char * const spi5_grps[] = { "spi5_grp" };
614
615static const char * const sw_led0_grps[] = { "sw_led0_0_grp",
616 "sw_led0_1_grp" };
617static const char * const sw_led1_grps[] = { "sw_led1_grp" };
618static const char * const sw_led2_grps[] = { "sw_led2_0_grp",
619 "sw_led2_1_grp" };
620static const char * const d1w_grps[] = { "d1w_grp" };
621static const char * const lcd_grps[] = { "lcd_grp" };
622static const char * const sram_grps[] = { "sram_0_grp", "sram_1_grp" };
623
624static const char * const uart0_grps[] = { "uart0_grp" };
625static const char * const uart1_grps[] = { "uart1_grp", "uart1_dte_grp" };
626static const char * const uart2_grps[] = { "uart2_grp" };
627static const char * const uart3_grps[] = { "uart3_grp" };
628static const char * const uart4_grps[] = { "uart4_grp" };
629static const char * const qspi_grps[] = { "qspi_0_grp", "qspi_1_grp" };
630static const char * const nand_grps[] = { "nand_grp" };
631static const char * const sdio0_grps[] = { "sdio0_grp", "sdio0_cd_grp",
632 "sdio0_mmc_grp" };
633static const char * const sdio1_grps[] = { "sdio1_data_0_grp",
634 "sdio1_data_1_grp", "sdio1_cd_grp", "sdio1_led_grp", "sdio1_mmc_grp" };
635static const char * const can0_grps[] = { "can0_grp" };
636static const char * const can1_grps[] = { "can1_grp" };
637static const char * const cam_grps[] = { "cam_led_grp", "cam_0_grp",
638 "cam_1_grp" };
639static const char * const bsc1_grps[] = { "bsc1_grp" };
640static const char * const pcie_clkreq_grps[] = { "pcie_clkreq_grp" };
641static const char * const usb0_oc_grps[] = { "usb0_oc_grp" };
642static const char * const usb1_oc_grps[] = { "usb1_oc_grp" };
643static const char * const usb2_oc_grps[] = { "usb2_oc_grp" };
644
645#define CYGNUS_PIN_FUNCTION(func) \
646{ \
647 .name = #func, \
648 .groups = func ## _grps, \
649 .num_groups = ARRAY_SIZE(func ## _grps), \
650}
651
652/*
653 * List of supported functions in Cygnus
654 */
655static const struct cygnus_pin_function cygnus_pin_functions[] = {
656 CYGNUS_PIN_FUNCTION(i2s0),
657 CYGNUS_PIN_FUNCTION(i2s1),
658 CYGNUS_PIN_FUNCTION(i2s2),
659 CYGNUS_PIN_FUNCTION(spdif),
660 CYGNUS_PIN_FUNCTION(pwm0),
661 CYGNUS_PIN_FUNCTION(pwm1),
662 CYGNUS_PIN_FUNCTION(pwm2),
663 CYGNUS_PIN_FUNCTION(pwm3),
664 CYGNUS_PIN_FUNCTION(pwm4),
665 CYGNUS_PIN_FUNCTION(pwm5),
666 CYGNUS_PIN_FUNCTION(key),
667 CYGNUS_PIN_FUNCTION(audio_dte),
668 CYGNUS_PIN_FUNCTION(smart_card0),
669 CYGNUS_PIN_FUNCTION(smart_card1),
670 CYGNUS_PIN_FUNCTION(spi0),
671 CYGNUS_PIN_FUNCTION(spi1),
672 CYGNUS_PIN_FUNCTION(spi2),
673 CYGNUS_PIN_FUNCTION(spi3),
674 CYGNUS_PIN_FUNCTION(spi4),
675 CYGNUS_PIN_FUNCTION(spi5),
676 CYGNUS_PIN_FUNCTION(sw_led0),
677 CYGNUS_PIN_FUNCTION(sw_led1),
678 CYGNUS_PIN_FUNCTION(sw_led2),
679 CYGNUS_PIN_FUNCTION(d1w),
680 CYGNUS_PIN_FUNCTION(lcd),
681 CYGNUS_PIN_FUNCTION(sram),
682 CYGNUS_PIN_FUNCTION(uart0),
683 CYGNUS_PIN_FUNCTION(uart1),
684 CYGNUS_PIN_FUNCTION(uart2),
685 CYGNUS_PIN_FUNCTION(uart3),
686 CYGNUS_PIN_FUNCTION(uart4),
687 CYGNUS_PIN_FUNCTION(qspi),
688 CYGNUS_PIN_FUNCTION(nand),
689 CYGNUS_PIN_FUNCTION(sdio0),
690 CYGNUS_PIN_FUNCTION(sdio1),
691 CYGNUS_PIN_FUNCTION(can0),
692 CYGNUS_PIN_FUNCTION(can1),
693 CYGNUS_PIN_FUNCTION(cam),
694 CYGNUS_PIN_FUNCTION(bsc1),
695 CYGNUS_PIN_FUNCTION(pcie_clkreq),
696 CYGNUS_PIN_FUNCTION(usb0_oc),
697 CYGNUS_PIN_FUNCTION(usb1_oc),
698 CYGNUS_PIN_FUNCTION(usb2_oc),
699};
700
701static int cygnus_get_groups_count(struct pinctrl_dev *pctrl_dev)
702{
703 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
704
705 return pinctrl->num_groups;
706}
707
708static const char *cygnus_get_group_name(struct pinctrl_dev *pctrl_dev,
709 unsigned selector)
710{
711 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
712
713 return pinctrl->groups[selector].name;
714}
715
716static int cygnus_get_group_pins(struct pinctrl_dev *pctrl_dev,
717 unsigned selector, const unsigned **pins,
718 unsigned *num_pins)
719{
720 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
721
722 *pins = pinctrl->groups[selector].pins;
723 *num_pins = pinctrl->groups[selector].num_pins;
724
725 return 0;
726}
727
728static void cygnus_pin_dbg_show(struct pinctrl_dev *pctrl_dev,
729 struct seq_file *s, unsigned offset)
730{
731 seq_printf(s, " %s", dev_name(pctrl_dev->dev));
732}
733
734static const struct pinctrl_ops cygnus_pinctrl_ops = {
735 .get_groups_count = cygnus_get_groups_count,
736 .get_group_name = cygnus_get_group_name,
737 .get_group_pins = cygnus_get_group_pins,
738 .pin_dbg_show = cygnus_pin_dbg_show,
739 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
740 .dt_free_map = pinctrl_utils_dt_free_map,
741};
742
743static int cygnus_get_functions_count(struct pinctrl_dev *pctrl_dev)
744{
745 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
746
747 return pinctrl->num_functions;
748}
749
750static const char *cygnus_get_function_name(struct pinctrl_dev *pctrl_dev,
751 unsigned selector)
752{
753 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
754
755 return pinctrl->functions[selector].name;
756}
757
758static int cygnus_get_function_groups(struct pinctrl_dev *pctrl_dev,
759 unsigned selector,
760 const char * const **groups,
761 unsigned * const num_groups)
762{
763 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
764
765 *groups = pinctrl->functions[selector].groups;
766 *num_groups = pinctrl->functions[selector].num_groups;
767
768 return 0;
769}
770
771static int cygnus_pinmux_set(struct cygnus_pinctrl *pinctrl,
772 const struct cygnus_pin_function *func,
773 const struct cygnus_pin_group *grp,
774 struct cygnus_mux_log *mux_log)
775{
776 const struct cygnus_mux *mux = &grp->mux;
777 int i;
778 u32 val, mask = 0x7;
779 unsigned long flags;
780
781 for (i = 0; i < CYGNUS_NUM_IOMUX; i++) {
782 if (mux->offset != mux_log[i].mux.offset ||
783 mux->shift != mux_log[i].mux.shift)
784 continue;
785
786 /* match found if we reach here */
787
788 /* if this is a new configuration, just do it! */
789 if (!mux_log[i].is_configured)
790 break;
791
792 /*
793 * IOMUX has been configured previously and one is trying to
794 * configure it to a different function
795 */
796 if (mux_log[i].mux.alt != mux->alt) {
797 dev_err(pinctrl->dev,
798 "double configuration error detected!\n");
799 dev_err(pinctrl->dev, "func:%s grp:%s\n",
800 func->name, grp->name);
801 return -EINVAL;
802 } else {
803 /*
804 * One tries to configure it to the same function.
805 * Just quit and don't bother
806 */
807 return 0;
808 }
809 }
810
811 mux_log[i].mux.alt = mux->alt;
812 mux_log[i].is_configured = true;
813
814 spin_lock_irqsave(&pinctrl->lock, flags);
815
816 val = readl(pinctrl->base0 + grp->mux.offset);
817 val &= ~(mask << grp->mux.shift);
818 val |= grp->mux.alt << grp->mux.shift;
819 writel(val, pinctrl->base0 + grp->mux.offset);
820
821 spin_unlock_irqrestore(&pinctrl->lock, flags);
822
823 return 0;
824}
825
826static int cygnus_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,
827 unsigned func_select, unsigned grp_select)
828{
829 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
830 const struct cygnus_pin_function *func =
831 &pinctrl->functions[func_select];
832 const struct cygnus_pin_group *grp = &pinctrl->groups[grp_select];
833
834 dev_dbg(pctrl_dev->dev, "func:%u name:%s grp:%u name:%s\n",
835 func_select, func->name, grp_select, grp->name);
836
837 dev_dbg(pctrl_dev->dev, "offset:0x%08x shift:%u alt:%u\n",
838 grp->mux.offset, grp->mux.shift, grp->mux.alt);
839
840 return cygnus_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
841}
842
843static int cygnus_gpio_request_enable(struct pinctrl_dev *pctrl_dev,
844 struct pinctrl_gpio_range *range,
845 unsigned pin)
846{
847 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
848 const struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;
849 u32 val;
850 unsigned long flags;
851
852 /* not all pins support GPIO pinmux override */
853 if (!mux->is_supported)
854 return -ENOTSUPP;
855
856 spin_lock_irqsave(&pinctrl->lock, flags);
857
858 val = readl(pinctrl->base1 + mux->offset);
859 val |= 0x3 << mux->shift;
860 writel(val, pinctrl->base1 + mux->offset);
861
862 spin_unlock_irqrestore(&pinctrl->lock, flags);
863
864 dev_dbg(pctrl_dev->dev,
865 "gpio request enable pin=%u offset=0x%x shift=%u\n",
866 pin, mux->offset, mux->shift);
867
868 return 0;
869}
870
871static void cygnus_gpio_disable_free(struct pinctrl_dev *pctrl_dev,
872 struct pinctrl_gpio_range *range,
873 unsigned pin)
874{
875 struct cygnus_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
876 struct cygnus_gpio_mux *mux = pctrl_dev->desc->pins[pin].drv_data;
877 u32 val;
878 unsigned long flags;
879
880 if (!mux->is_supported)
881 return;
882
883 spin_lock_irqsave(&pinctrl->lock, flags);
884
885 val = readl(pinctrl->base1 + mux->offset);
886 val &= ~(0x3 << mux->shift);
887 writel(val, pinctrl->base1 + mux->offset);
888
889 spin_unlock_irqrestore(&pinctrl->lock, flags);
890
891 dev_err(pctrl_dev->dev,
892 "gpio disable free pin=%u offset=0x%x shift=%u\n",
893 pin, mux->offset, mux->shift);
894}
895
896static const struct pinmux_ops cygnus_pinmux_ops = {
897 .get_functions_count = cygnus_get_functions_count,
898 .get_function_name = cygnus_get_function_name,
899 .get_function_groups = cygnus_get_function_groups,
900 .set_mux = cygnus_pinmux_set_mux,
901 .gpio_request_enable = cygnus_gpio_request_enable,
902 .gpio_disable_free = cygnus_gpio_disable_free,
903};
904
905static struct pinctrl_desc cygnus_pinctrl_desc = {
906 .name = "cygnus-pinmux",
907 .pctlops = &cygnus_pinctrl_ops,
908 .pmxops = &cygnus_pinmux_ops,
909};
910
911static int cygnus_mux_log_init(struct cygnus_pinctrl *pinctrl)
912{
913 struct cygnus_mux_log *log;
914 unsigned int i, j;
915
916 pinctrl->mux_log = devm_kcalloc(pinctrl->dev, CYGNUS_NUM_IOMUX,
917 sizeof(struct cygnus_mux_log),
918 GFP_KERNEL);
919 if (!pinctrl->mux_log)
920 return -ENOMEM;
921
922 log = pinctrl->mux_log;
923 for (i = 0; i < CYGNUS_NUM_IOMUX_REGS; i++) {
924 for (j = 0; j < CYGNUS_NUM_MUX_PER_REG; j++) {
925 log = &pinctrl->mux_log[i * CYGNUS_NUM_MUX_PER_REG
926 + j];
927 log->mux.offset = i * 4;
928 log->mux.shift = j * 4;
929 log->mux.alt = 0;
930 log->is_configured = false;
931 }
932 }
933
934 return 0;
935}
936
937static int cygnus_pinmux_probe(struct platform_device *pdev)
938{
939 struct cygnus_pinctrl *pinctrl;
940 struct resource *res;
941 int i, ret;
942 struct pinctrl_pin_desc *pins;
943 unsigned num_pins = ARRAY_SIZE(cygnus_pins);
944
945 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
946 if (!pinctrl)
947 return -ENOMEM;
948
949 pinctrl->dev = &pdev->dev;
950 platform_set_drvdata(pdev, pinctrl);
951 spin_lock_init(&pinctrl->lock);
952
953 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
954 pinctrl->base0 = devm_ioremap_resource(&pdev->dev, res);
955 if (IS_ERR(pinctrl->base0)) {
956 dev_err(&pdev->dev, "unable to map I/O space\n");
957 return PTR_ERR(pinctrl->base0);
958 }
959
960 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
961 pinctrl->base1 = devm_ioremap_resource(&pdev->dev, res);
962 if (IS_ERR(pinctrl->base1)) {
963 dev_err(&pdev->dev, "unable to map I/O space\n");
964 return PTR_ERR(pinctrl->base1);
965 }
966
967 ret = cygnus_mux_log_init(pinctrl);
968 if (ret) {
969 dev_err(&pdev->dev, "unable to initialize IOMUX log\n");
970 return ret;
971 }
972
973 pins = devm_kcalloc(&pdev->dev, num_pins, sizeof(*pins), GFP_KERNEL);
974 if (!pins)
975 return -ENOMEM;
976
977 for (i = 0; i < num_pins; i++) {
978 pins[i].number = cygnus_pins[i].pin;
979 pins[i].name = cygnus_pins[i].name;
980 pins[i].drv_data = &cygnus_pins[i].gpio_mux;
981 }
982
983 pinctrl->groups = cygnus_pin_groups;
984 pinctrl->num_groups = ARRAY_SIZE(cygnus_pin_groups);
985 pinctrl->functions = cygnus_pin_functions;
986 pinctrl->num_functions = ARRAY_SIZE(cygnus_pin_functions);
987 cygnus_pinctrl_desc.pins = pins;
988 cygnus_pinctrl_desc.npins = num_pins;
989
990 pinctrl->pctl = pinctrl_register(&cygnus_pinctrl_desc, &pdev->dev,
991 pinctrl);
992 if (!pinctrl->pctl) {
993 dev_err(&pdev->dev, "unable to register Cygnus IOMUX pinctrl\n");
994 return -EINVAL;
995 }
996
997 return 0;
998}
999
1000static const struct of_device_id cygnus_pinmux_of_match[] = {
1001 { .compatible = "brcm,cygnus-pinmux" },
1002 { }
1003};
1004
1005static struct platform_driver cygnus_pinmux_driver = {
1006 .driver = {
1007 .name = "cygnus-pinmux",
1008 .of_match_table = cygnus_pinmux_of_match,
1009 .suppress_bind_attrs = true,
1010 },
1011 .probe = cygnus_pinmux_probe,
1012};
1013
1014static int __init cygnus_pinmux_init(void)
1015{
1016 return platform_driver_register(&cygnus_pinmux_driver);
1017}
1018arch_initcall(cygnus_pinmux_init);
1019
1020MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1021MODULE_DESCRIPTION("Broadcom Cygnus IOMUX driver");
1022MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 448f10986c28..e261f1cf85c6 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -542,10 +542,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
542 struct imx_pin_reg *pin_reg; 542 struct imx_pin_reg *pin_reg;
543 struct imx_pin *pin = &grp->pins[i]; 543 struct imx_pin *pin = &grp->pins[i];
544 544
545 if (info->flags & SHARE_MUX_CONF_REG) 545 if (info->flags & SHARE_MUX_CONF_REG) {
546 conf_reg = mux_reg; 546 conf_reg = mux_reg;
547 else 547 } else {
548 conf_reg = be32_to_cpu(*list++); 548 conf_reg = be32_to_cpu(*list++);
549 if (!conf_reg)
550 conf_reg = -1;
551 }
549 552
550 pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; 553 pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
551 pin_reg = &info->pin_regs[pin_id]; 554 pin_reg = &info->pin_regs[pin_id];
@@ -645,7 +648,7 @@ int imx_pinctrl_probe(struct platform_device *pdev,
645{ 648{
646 struct imx_pinctrl *ipctl; 649 struct imx_pinctrl *ipctl;
647 struct resource *res; 650 struct resource *res;
648 int ret; 651 int ret, i;
649 652
650 if (!info || !info->pins || !info->npins) { 653 if (!info || !info->pins || !info->npins) {
651 dev_err(&pdev->dev, "wrong pinctrl info\n"); 654 dev_err(&pdev->dev, "wrong pinctrl info\n");
@@ -662,7 +665,11 @@ int imx_pinctrl_probe(struct platform_device *pdev,
662 info->npins, GFP_KERNEL); 665 info->npins, GFP_KERNEL);
663 if (!info->pin_regs) 666 if (!info->pin_regs)
664 return -ENOMEM; 667 return -ENOMEM;
665 memset(info->pin_regs, 0xff, sizeof(*info->pin_regs) * info->npins); 668
669 for (i = 0; i < info->npins; i++) {
670 info->pin_regs[i].mux_reg = -1;
671 info->pin_regs[i].conf_reg = -1;
672 }
666 673
667 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 674 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
668 ipctl->base = devm_ioremap_resource(&pdev->dev, res); 675 ipctl->base = devm_ioremap_resource(&pdev->dev, res);
diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c
index fc86276892fd..37a037543d29 100644
--- a/drivers/pinctrl/freescale/pinctrl-vf610.c
+++ b/drivers/pinctrl/freescale/pinctrl-vf610.c
@@ -302,7 +302,7 @@ static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
302 .flags = SHARE_MUX_CONF_REG, 302 .flags = SHARE_MUX_CONF_REG,
303}; 303};
304 304
305static struct of_device_id vf610_pinctrl_of_match[] = { 305static const struct of_device_id vf610_pinctrl_of_match[] = {
306 { .compatible = "fsl,vf610-iomuxc", }, 306 { .compatible = "fsl,vf610-iomuxc", },
307 { /* sentinel */ } 307 { /* sentinel */ }
308}; 308};
diff --git a/drivers/pinctrl/intel/Kconfig b/drivers/pinctrl/intel/Kconfig
index b801d869e91c..fe5e07db0a95 100644
--- a/drivers/pinctrl/intel/Kconfig
+++ b/drivers/pinctrl/intel/Kconfig
@@ -25,3 +25,20 @@ config PINCTRL_CHERRYVIEW
25 help 25 help
26 Cherryview/Braswell pinctrl driver provides an interface that 26 Cherryview/Braswell pinctrl driver provides an interface that
27 allows configuring of SoC pins and using them as GPIOs. 27 allows configuring of SoC pins and using them as GPIOs.
28
29config PINCTRL_INTEL
30 tristate
31 select PINMUX
32 select PINCONF
33 select GENERIC_PINCONF
34 select GPIOLIB
35 select GPIOLIB_IRQCHIP
36
37config PINCTRL_SUNRISEPOINT
38 tristate "Intel Sunrisepoint pinctrl and GPIO driver"
39 depends on ACPI
40 select PINCTRL_INTEL
41 help
42 Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
43 provides an interface that allows configuring of PCH pins and
44 using them as GPIOs.
diff --git a/drivers/pinctrl/intel/Makefile b/drivers/pinctrl/intel/Makefile
index 4c210e4139e2..fee756e1255b 100644
--- a/drivers/pinctrl/intel/Makefile
+++ b/drivers/pinctrl/intel/Makefile
@@ -2,3 +2,5 @@
2 2
3obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o 3obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
4obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o 4obj-$(CONFIG_PINCTRL_CHERRYVIEW) += pinctrl-cherryview.o
5obj-$(CONFIG_PINCTRL_INTEL) += pinctrl-intel.o
6obj-$(CONFIG_PINCTRL_SUNRISEPOINT) += pinctrl-sunrisepoint.o
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c
new file mode 100644
index 000000000000..00768e53deec
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-intel.c
@@ -0,0 +1,1149 @@
1/*
2 * Intel pinctrl/GPIO core driver.
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/acpi.h>
16#include <linux/gpio.h>
17#include <linux/gpio/driver.h>
18#include <linux/platform_device.h>
19#include <linux/pm.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/pinctrl/pinmux.h>
22#include <linux/pinctrl/pinconf.h>
23#include <linux/pinctrl/pinconf-generic.h>
24
25#include "pinctrl-intel.h"
26
27/* Maximum number of pads in each group */
28#define NPADS_IN_GPP 24
29
30/* Offset from regs */
31#define PADBAR 0x00c
32#define GPI_IS 0x100
33#define GPI_GPE_STS 0x140
34#define GPI_GPE_EN 0x160
35
36#define PADOWN_BITS 4
37#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
38#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
39
40/* Offset from pad_regs */
41#define PADCFG0 0x000
42#define PADCFG0_RXEVCFG_SHIFT 25
43#define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
44#define PADCFG0_RXEVCFG_LEVEL 0
45#define PADCFG0_RXEVCFG_EDGE 1
46#define PADCFG0_RXEVCFG_DISABLED 2
47#define PADCFG0_RXEVCFG_EDGE_BOTH 3
48#define PADCFG0_RXINV BIT(23)
49#define PADCFG0_GPIROUTIOXAPIC BIT(20)
50#define PADCFG0_GPIROUTSCI BIT(19)
51#define PADCFG0_GPIROUTSMI BIT(18)
52#define PADCFG0_GPIROUTNMI BIT(17)
53#define PADCFG0_PMODE_SHIFT 10
54#define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
55#define PADCFG0_GPIORXDIS BIT(9)
56#define PADCFG0_GPIOTXDIS BIT(8)
57#define PADCFG0_GPIORXSTATE BIT(1)
58#define PADCFG0_GPIOTXSTATE BIT(0)
59
60#define PADCFG1 0x004
61#define PADCFG1_TERM_UP BIT(13)
62#define PADCFG1_TERM_SHIFT 10
63#define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
64#define PADCFG1_TERM_20K 4
65#define PADCFG1_TERM_2K 3
66#define PADCFG1_TERM_5K 2
67#define PADCFG1_TERM_1K 1
68
69struct intel_pad_context {
70 u32 padcfg0;
71 u32 padcfg1;
72};
73
74struct intel_community_context {
75 u32 *intmask;
76};
77
78struct intel_pinctrl_context {
79 struct intel_pad_context *pads;
80 struct intel_community_context *communities;
81};
82
83/**
84 * struct intel_pinctrl - Intel pinctrl private structure
85 * @dev: Pointer to the device structure
86 * @lock: Lock to serialize register access
87 * @pctldesc: Pin controller description
88 * @pctldev: Pointer to the pin controller device
89 * @chip: GPIO chip in this pin controller
90 * @soc: SoC/PCH specific pin configuration data
91 * @communities: All communities in this pin controller
92 * @ncommunities: Number of communities in this pin controller
93 * @context: Configuration saved over system sleep
94 */
95struct intel_pinctrl {
96 struct device *dev;
97 spinlock_t lock;
98 struct pinctrl_desc pctldesc;
99 struct pinctrl_dev *pctldev;
100 struct gpio_chip chip;
101 const struct intel_pinctrl_soc_data *soc;
102 struct intel_community *communities;
103 size_t ncommunities;
104 struct intel_pinctrl_context context;
105};
106
107#define gpiochip_to_pinctrl(c) container_of(c, struct intel_pinctrl, chip)
108#define pin_to_padno(c, p) ((p) - (c)->pin_base)
109
110static struct intel_community *intel_get_community(struct intel_pinctrl *pctrl,
111 unsigned pin)
112{
113 struct intel_community *community;
114 int i;
115
116 for (i = 0; i < pctrl->ncommunities; i++) {
117 community = &pctrl->communities[i];
118 if (pin >= community->pin_base &&
119 pin < community->pin_base + community->npins)
120 return community;
121 }
122
123 dev_warn(pctrl->dev, "failed to find community for pin %u\n", pin);
124 return NULL;
125}
126
127static void __iomem *intel_get_padcfg(struct intel_pinctrl *pctrl, unsigned pin,
128 unsigned reg)
129{
130 const struct intel_community *community;
131 unsigned padno;
132
133 community = intel_get_community(pctrl, pin);
134 if (!community)
135 return NULL;
136
137 padno = pin_to_padno(community, pin);
138 return community->pad_regs + reg + padno * 8;
139}
140
141static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
142{
143 const struct intel_community *community;
144 unsigned padno, gpp, gpp_offset, offset;
145 void __iomem *padown;
146
147 community = intel_get_community(pctrl, pin);
148 if (!community)
149 return false;
150 if (!community->padown_offset)
151 return true;
152
153 padno = pin_to_padno(community, pin);
154 gpp = padno / NPADS_IN_GPP;
155 gpp_offset = padno % NPADS_IN_GPP;
156 offset = community->padown_offset + gpp * 16 + (gpp_offset / 8) * 4;
157 padown = community->regs + offset;
158
159 return !(readl(padown) & PADOWN_MASK(padno));
160}
161
162static bool intel_pad_reserved_for_acpi(struct intel_pinctrl *pctrl,
163 unsigned pin)
164{
165 const struct intel_community *community;
166 unsigned padno, gpp, offset;
167 void __iomem *hostown;
168
169 community = intel_get_community(pctrl, pin);
170 if (!community)
171 return true;
172 if (!community->hostown_offset)
173 return false;
174
175 padno = pin_to_padno(community, pin);
176 gpp = padno / NPADS_IN_GPP;
177 offset = community->hostown_offset + gpp * 4;
178 hostown = community->regs + offset;
179
180 return !(readl(hostown) & BIT(padno % NPADS_IN_GPP));
181}
182
183static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
184{
185 struct intel_community *community;
186 unsigned padno, gpp, offset;
187 u32 value;
188
189 community = intel_get_community(pctrl, pin);
190 if (!community)
191 return true;
192 if (!community->padcfglock_offset)
193 return false;
194
195 padno = pin_to_padno(community, pin);
196 gpp = padno / NPADS_IN_GPP;
197
198 /*
199 * If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
200 * the pad is considered unlocked. Any other case means that it is
201 * either fully or partially locked and we don't touch it.
202 */
203 offset = community->padcfglock_offset + gpp * 8;
204 value = readl(community->regs + offset);
205 if (value & BIT(pin % NPADS_IN_GPP))
206 return true;
207
208 offset = community->padcfglock_offset + 4 + gpp * 8;
209 value = readl(community->regs + offset);
210 if (value & BIT(pin % NPADS_IN_GPP))
211 return true;
212
213 return false;
214}
215
216static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
217{
218 return intel_pad_owned_by_host(pctrl, pin) &&
219 !intel_pad_reserved_for_acpi(pctrl, pin) &&
220 !intel_pad_locked(pctrl, pin);
221}
222
223static int intel_get_groups_count(struct pinctrl_dev *pctldev)
224{
225 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
226
227 return pctrl->soc->ngroups;
228}
229
230static const char *intel_get_group_name(struct pinctrl_dev *pctldev,
231 unsigned group)
232{
233 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
234
235 return pctrl->soc->groups[group].name;
236}
237
238static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
239 const unsigned **pins, unsigned *npins)
240{
241 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
242
243 *pins = pctrl->soc->groups[group].pins;
244 *npins = pctrl->soc->groups[group].npins;
245 return 0;
246}
247
248static void intel_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
249 unsigned pin)
250{
251 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
252 u32 cfg0, cfg1, mode;
253 bool locked, acpi;
254
255 if (!intel_pad_owned_by_host(pctrl, pin)) {
256 seq_puts(s, "not available");
257 return;
258 }
259
260 cfg0 = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
261 cfg1 = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
262
263 mode = (cfg0 & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
264 if (!mode)
265 seq_puts(s, "GPIO ");
266 else
267 seq_printf(s, "mode %d ", mode);
268
269 seq_printf(s, "0x%08x 0x%08x", cfg0, cfg1);
270
271 locked = intel_pad_locked(pctrl, pin);
272 acpi = intel_pad_reserved_for_acpi(pctrl, pin);
273
274 if (locked || acpi) {
275 seq_puts(s, " [");
276 if (locked) {
277 seq_puts(s, "LOCKED");
278 if (acpi)
279 seq_puts(s, ", ");
280 }
281 if (acpi)
282 seq_puts(s, "ACPI");
283 seq_puts(s, "]");
284 }
285}
286
287static const struct pinctrl_ops intel_pinctrl_ops = {
288 .get_groups_count = intel_get_groups_count,
289 .get_group_name = intel_get_group_name,
290 .get_group_pins = intel_get_group_pins,
291 .pin_dbg_show = intel_pin_dbg_show,
292};
293
294static int intel_get_functions_count(struct pinctrl_dev *pctldev)
295{
296 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
297
298 return pctrl->soc->nfunctions;
299}
300
301static const char *intel_get_function_name(struct pinctrl_dev *pctldev,
302 unsigned function)
303{
304 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
305
306 return pctrl->soc->functions[function].name;
307}
308
309static int intel_get_function_groups(struct pinctrl_dev *pctldev,
310 unsigned function,
311 const char * const **groups,
312 unsigned * const ngroups)
313{
314 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
315
316 *groups = pctrl->soc->functions[function].groups;
317 *ngroups = pctrl->soc->functions[function].ngroups;
318 return 0;
319}
320
321static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
322 unsigned group)
323{
324 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
325 const struct intel_pingroup *grp = &pctrl->soc->groups[group];
326 unsigned long flags;
327 int i;
328
329 spin_lock_irqsave(&pctrl->lock, flags);
330
331 /*
332 * All pins in the groups needs to be accessible and writable
333 * before we can enable the mux for this group.
334 */
335 for (i = 0; i < grp->npins; i++) {
336 if (!intel_pad_usable(pctrl, grp->pins[i])) {
337 spin_unlock_irqrestore(&pctrl->lock, flags);
338 return -EBUSY;
339 }
340 }
341
342 /* Now enable the mux setting for each pin in the group */
343 for (i = 0; i < grp->npins; i++) {
344 void __iomem *padcfg0;
345 u32 value;
346
347 padcfg0 = intel_get_padcfg(pctrl, grp->pins[i], PADCFG0);
348 value = readl(padcfg0);
349
350 value &= ~PADCFG0_PMODE_MASK;
351 value |= grp->mode << PADCFG0_PMODE_SHIFT;
352
353 writel(value, padcfg0);
354 }
355
356 spin_unlock_irqrestore(&pctrl->lock, flags);
357
358 return 0;
359}
360
361static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
362 struct pinctrl_gpio_range *range,
363 unsigned pin)
364{
365 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
366 void __iomem *padcfg0;
367 unsigned long flags;
368 u32 value;
369
370 spin_lock_irqsave(&pctrl->lock, flags);
371
372 if (!intel_pad_usable(pctrl, pin)) {
373 spin_unlock_irqrestore(&pctrl->lock, flags);
374 return -EBUSY;
375 }
376
377 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
378 /* Put the pad into GPIO mode */
379 value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
380 /* Disable SCI/SMI/NMI generation */
381 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
382 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
383 /* Disable TX buffer and enable RX (this will be input) */
384 value &= ~PADCFG0_GPIORXDIS;
385 value |= PADCFG0_GPIOTXDIS;
386 writel(value, padcfg0);
387
388 spin_unlock_irqrestore(&pctrl->lock, flags);
389
390 return 0;
391}
392
393static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
394 struct pinctrl_gpio_range *range,
395 unsigned pin, bool input)
396{
397 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
398 void __iomem *padcfg0;
399 unsigned long flags;
400 u32 value;
401
402 spin_lock_irqsave(&pctrl->lock, flags);
403
404 padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
405
406 value = readl(padcfg0);
407 if (input)
408 value |= PADCFG0_GPIOTXDIS;
409 else
410 value &= ~PADCFG0_GPIOTXDIS;
411 writel(value, padcfg0);
412
413 spin_unlock_irqrestore(&pctrl->lock, flags);
414
415 return 0;
416}
417
418static const struct pinmux_ops intel_pinmux_ops = {
419 .get_functions_count = intel_get_functions_count,
420 .get_function_name = intel_get_function_name,
421 .get_function_groups = intel_get_function_groups,
422 .set_mux = intel_pinmux_set_mux,
423 .gpio_request_enable = intel_gpio_request_enable,
424 .gpio_set_direction = intel_gpio_set_direction,
425};
426
427static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
428 unsigned long *config)
429{
430 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
431 enum pin_config_param param = pinconf_to_config_param(*config);
432 u32 value, term;
433 u16 arg = 0;
434
435 if (!intel_pad_owned_by_host(pctrl, pin))
436 return -ENOTSUPP;
437
438 value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
439 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
440
441 switch (param) {
442 case PIN_CONFIG_BIAS_DISABLE:
443 if (term)
444 return -EINVAL;
445 break;
446
447 case PIN_CONFIG_BIAS_PULL_UP:
448 if (!term || !(value & PADCFG1_TERM_UP))
449 return -EINVAL;
450
451 switch (term) {
452 case PADCFG1_TERM_1K:
453 arg = 1000;
454 break;
455 case PADCFG1_TERM_2K:
456 arg = 2000;
457 break;
458 case PADCFG1_TERM_5K:
459 arg = 5000;
460 break;
461 case PADCFG1_TERM_20K:
462 arg = 20000;
463 break;
464 }
465
466 break;
467
468 case PIN_CONFIG_BIAS_PULL_DOWN:
469 if (!term || value & PADCFG1_TERM_UP)
470 return -EINVAL;
471
472 switch (term) {
473 case PADCFG1_TERM_5K:
474 arg = 5000;
475 break;
476 case PADCFG1_TERM_20K:
477 arg = 20000;
478 break;
479 }
480
481 break;
482
483 default:
484 return -ENOTSUPP;
485 }
486
487 *config = pinconf_to_config_packed(param, arg);
488 return 0;
489}
490
491static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
492 unsigned long config)
493{
494 unsigned param = pinconf_to_config_param(config);
495 unsigned arg = pinconf_to_config_argument(config);
496 void __iomem *padcfg1;
497 unsigned long flags;
498 int ret = 0;
499 u32 value;
500
501 spin_lock_irqsave(&pctrl->lock, flags);
502
503 padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
504 value = readl(padcfg1);
505
506 switch (param) {
507 case PIN_CONFIG_BIAS_DISABLE:
508 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
509 break;
510
511 case PIN_CONFIG_BIAS_PULL_UP:
512 value &= ~PADCFG1_TERM_MASK;
513
514 value |= PADCFG1_TERM_UP;
515
516 switch (arg) {
517 case 20000:
518 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
519 break;
520 case 5000:
521 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
522 break;
523 case 2000:
524 value |= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
525 break;
526 case 1000:
527 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
528 break;
529 default:
530 ret = -EINVAL;
531 }
532
533 break;
534
535 case PIN_CONFIG_BIAS_PULL_DOWN:
536 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
537
538 switch (arg) {
539 case 20000:
540 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
541 break;
542 case 5000:
543 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
544 break;
545 default:
546 ret = -EINVAL;
547 }
548
549 break;
550 }
551
552 if (!ret)
553 writel(value, padcfg1);
554
555 spin_unlock_irqrestore(&pctrl->lock, flags);
556
557 return ret;
558}
559
560static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
561 unsigned long *configs, unsigned nconfigs)
562{
563 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
564 int i, ret;
565
566 if (!intel_pad_usable(pctrl, pin))
567 return -ENOTSUPP;
568
569 for (i = 0; i < nconfigs; i++) {
570 switch (pinconf_to_config_param(configs[i])) {
571 case PIN_CONFIG_BIAS_DISABLE:
572 case PIN_CONFIG_BIAS_PULL_UP:
573 case PIN_CONFIG_BIAS_PULL_DOWN:
574 ret = intel_config_set_pull(pctrl, pin, configs[i]);
575 if (ret)
576 return ret;
577 break;
578
579 default:
580 return -ENOTSUPP;
581 }
582 }
583
584 return 0;
585}
586
587static const struct pinconf_ops intel_pinconf_ops = {
588 .is_generic = true,
589 .pin_config_get = intel_config_get,
590 .pin_config_set = intel_config_set,
591};
592
593static const struct pinctrl_desc intel_pinctrl_desc = {
594 .pctlops = &intel_pinctrl_ops,
595 .pmxops = &intel_pinmux_ops,
596 .confops = &intel_pinconf_ops,
597 .owner = THIS_MODULE,
598};
599
600static int intel_gpio_request(struct gpio_chip *chip, unsigned offset)
601{
602 return pinctrl_request_gpio(chip->base + offset);
603}
604
605static void intel_gpio_free(struct gpio_chip *chip, unsigned offset)
606{
607 pinctrl_free_gpio(chip->base + offset);
608}
609
610static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
611{
612 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
613 void __iomem *reg;
614
615 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
616 if (!reg)
617 return -EINVAL;
618
619 return !!(readl(reg) & PADCFG0_GPIORXSTATE);
620}
621
622static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
623{
624 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(chip);
625 void __iomem *reg;
626
627 reg = intel_get_padcfg(pctrl, offset, PADCFG0);
628 if (reg) {
629 unsigned long flags;
630 u32 padcfg0;
631
632 spin_lock_irqsave(&pctrl->lock, flags);
633 padcfg0 = readl(reg);
634 if (value)
635 padcfg0 |= PADCFG0_GPIOTXSTATE;
636 else
637 padcfg0 &= ~PADCFG0_GPIOTXSTATE;
638 writel(padcfg0, reg);
639 spin_unlock_irqrestore(&pctrl->lock, flags);
640 }
641}
642
643static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
644{
645 return pinctrl_gpio_direction_input(chip->base + offset);
646}
647
648static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
649 int value)
650{
651 intel_gpio_set(chip, offset, value);
652 return pinctrl_gpio_direction_output(chip->base + offset);
653}
654
655static const struct gpio_chip intel_gpio_chip = {
656 .owner = THIS_MODULE,
657 .request = intel_gpio_request,
658 .free = intel_gpio_free,
659 .direction_input = intel_gpio_direction_input,
660 .direction_output = intel_gpio_direction_output,
661 .get = intel_gpio_get,
662 .set = intel_gpio_set,
663};
664
665static void intel_gpio_irq_ack(struct irq_data *d)
666{
667 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
668 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
669 const struct intel_community *community;
670 unsigned pin = irqd_to_hwirq(d);
671
672 spin_lock(&pctrl->lock);
673
674 community = intel_get_community(pctrl, pin);
675 if (community) {
676 unsigned padno = pin_to_padno(community, pin);
677 unsigned gpp_offset = padno % NPADS_IN_GPP;
678 unsigned gpp = padno / NPADS_IN_GPP;
679
680 writel(BIT(gpp_offset), community->regs + GPI_IS + gpp * 4);
681 }
682
683 spin_unlock(&pctrl->lock);
684}
685
686static void intel_gpio_irq_mask_unmask(struct irq_data *d, bool mask)
687{
688 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
689 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
690 const struct intel_community *community;
691 unsigned pin = irqd_to_hwirq(d);
692 unsigned long flags;
693
694 spin_lock_irqsave(&pctrl->lock, flags);
695
696 community = intel_get_community(pctrl, pin);
697 if (community) {
698 unsigned padno = pin_to_padno(community, pin);
699 unsigned gpp_offset = padno % NPADS_IN_GPP;
700 unsigned gpp = padno / NPADS_IN_GPP;
701 void __iomem *reg;
702 u32 value;
703
704 reg = community->regs + community->ie_offset + gpp * 4;
705 value = readl(reg);
706 if (mask)
707 value &= ~BIT(gpp_offset);
708 else
709 value |= BIT(gpp_offset);
710 writel(value, reg);
711 }
712
713 spin_unlock_irqrestore(&pctrl->lock, flags);
714}
715
716static void intel_gpio_irq_mask(struct irq_data *d)
717{
718 intel_gpio_irq_mask_unmask(d, true);
719}
720
721static void intel_gpio_irq_unmask(struct irq_data *d)
722{
723 intel_gpio_irq_mask_unmask(d, false);
724}
725
726static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
727{
728 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
729 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
730 unsigned pin = irqd_to_hwirq(d);
731 unsigned long flags;
732 void __iomem *reg;
733 u32 value;
734
735 reg = intel_get_padcfg(pctrl, pin, PADCFG0);
736 if (!reg)
737 return -EINVAL;
738
739 spin_lock_irqsave(&pctrl->lock, flags);
740
741 value = readl(reg);
742
743 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
744
745 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
746 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
747 } else if (type & IRQ_TYPE_EDGE_FALLING) {
748 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
749 value |= PADCFG0_RXINV;
750 } else if (type & IRQ_TYPE_EDGE_RISING) {
751 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
752 } else if (type & IRQ_TYPE_LEVEL_LOW) {
753 value |= PADCFG0_RXINV;
754 } else {
755 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
756 }
757
758 writel(value, reg);
759
760 if (type & IRQ_TYPE_EDGE_BOTH)
761 __irq_set_handler_locked(d->irq, handle_edge_irq);
762 else if (type & IRQ_TYPE_LEVEL_MASK)
763 __irq_set_handler_locked(d->irq, handle_level_irq);
764
765 spin_unlock_irqrestore(&pctrl->lock, flags);
766
767 return 0;
768}
769
770static int intel_gpio_irq_wake(struct irq_data *d, unsigned int on)
771{
772 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
773 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
774 const struct intel_community *community;
775 unsigned pin = irqd_to_hwirq(d);
776 unsigned padno, gpp, gpp_offset;
777 u32 gpe_en;
778
779 community = intel_get_community(pctrl, pin);
780 if (!community)
781 return -EINVAL;
782
783 padno = pin_to_padno(community, pin);
784 gpp = padno / NPADS_IN_GPP;
785 gpp_offset = padno % NPADS_IN_GPP;
786
787 /* Clear the existing wake status */
788 writel(BIT(gpp_offset), community->regs + GPI_GPE_STS + gpp * 4);
789
790 /*
791 * The controller will generate wake when GPE of the corresponding
792 * pad is enabled and it is not routed to SCI (GPIROUTSCI is not
793 * set).
794 */
795 gpe_en = readl(community->regs + GPI_GPE_EN + gpp * 4);
796 if (on)
797 gpe_en |= BIT(gpp_offset);
798 else
799 gpe_en &= ~BIT(gpp_offset);
800 writel(gpe_en, community->regs + GPI_GPE_EN + gpp * 4);
801
802 dev_dbg(pctrl->dev, "%sable wake for pin %u\n", on ? "en" : "dis", pin);
803 return 0;
804}
805
806static void intel_gpio_community_irq_handler(struct gpio_chip *gc,
807 const struct intel_community *community)
808{
809 int gpp;
810
811 for (gpp = 0; gpp < community->ngpps; gpp++) {
812 unsigned long pending, enabled, gpp_offset;
813
814 pending = readl(community->regs + GPI_IS + gpp * 4);
815 enabled = readl(community->regs + community->ie_offset +
816 gpp * 4);
817
818 /* Only interrupts that are enabled */
819 pending &= enabled;
820
821 for_each_set_bit(gpp_offset, &pending, NPADS_IN_GPP) {
822 unsigned padno, irq;
823
824 /*
825 * The last group in community can have less pins
826 * than NPADS_IN_GPP.
827 */
828 padno = gpp_offset + gpp * NPADS_IN_GPP;
829 if (padno >= community->npins)
830 break;
831
832 irq = irq_find_mapping(gc->irqdomain,
833 community->pin_base + padno);
834 generic_handle_irq(irq);
835 }
836 }
837}
838
839static void intel_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
840{
841 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
842 struct intel_pinctrl *pctrl = gpiochip_to_pinctrl(gc);
843 struct irq_chip *chip = irq_get_chip(irq);
844 int i;
845
846 chained_irq_enter(chip, desc);
847
848 /* Need to check all communities for pending interrupts */
849 for (i = 0; i < pctrl->ncommunities; i++)
850 intel_gpio_community_irq_handler(gc, &pctrl->communities[i]);
851
852 chained_irq_exit(chip, desc);
853}
854
855static struct irq_chip intel_gpio_irqchip = {
856 .name = "intel-gpio",
857 .irq_ack = intel_gpio_irq_ack,
858 .irq_mask = intel_gpio_irq_mask,
859 .irq_unmask = intel_gpio_irq_unmask,
860 .irq_set_type = intel_gpio_irq_type,
861 .irq_set_wake = intel_gpio_irq_wake,
862};
863
864static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
865{
866 size_t i;
867
868 for (i = 0; i < pctrl->ncommunities; i++) {
869 const struct intel_community *community;
870 void __iomem *base;
871 unsigned gpp;
872
873 community = &pctrl->communities[i];
874 base = community->regs;
875
876 for (gpp = 0; gpp < community->ngpps; gpp++) {
877 /* Mask and clear all interrupts */
878 writel(0, base + community->ie_offset + gpp * 4);
879 writel(0xffff, base + GPI_IS + gpp * 4);
880 }
881 }
882}
883
884static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
885{
886 int ret;
887
888 pctrl->chip = intel_gpio_chip;
889
890 pctrl->chip.ngpio = pctrl->soc->npins;
891 pctrl->chip.label = dev_name(pctrl->dev);
892 pctrl->chip.dev = pctrl->dev;
893 pctrl->chip.base = -1;
894
895 ret = gpiochip_add(&pctrl->chip);
896 if (ret) {
897 dev_err(pctrl->dev, "failed to register gpiochip\n");
898 return ret;
899 }
900
901 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
902 0, 0, pctrl->soc->npins);
903 if (ret) {
904 dev_err(pctrl->dev, "failed to add GPIO pin range\n");
905 gpiochip_remove(&pctrl->chip);
906 return ret;
907 }
908
909 ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
910 handle_simple_irq, IRQ_TYPE_NONE);
911 if (ret) {
912 dev_err(pctrl->dev, "failed to add irqchip\n");
913 gpiochip_remove(&pctrl->chip);
914 return ret;
915 }
916
917 gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
918 intel_gpio_irq_handler);
919 return 0;
920}
921
922static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
923{
924#ifdef CONFIG_PM_SLEEP
925 const struct intel_pinctrl_soc_data *soc = pctrl->soc;
926 struct intel_community_context *communities;
927 struct intel_pad_context *pads;
928 int i;
929
930 pads = devm_kcalloc(pctrl->dev, soc->npins, sizeof(*pads), GFP_KERNEL);
931 if (!pads)
932 return -ENOMEM;
933
934 communities = devm_kcalloc(pctrl->dev, pctrl->ncommunities,
935 sizeof(*communities), GFP_KERNEL);
936 if (!communities)
937 return -ENOMEM;
938
939
940 for (i = 0; i < pctrl->ncommunities; i++) {
941 struct intel_community *community = &pctrl->communities[i];
942 u32 *intmask;
943
944 intmask = devm_kcalloc(pctrl->dev, community->ngpps,
945 sizeof(*intmask), GFP_KERNEL);
946 if (!intmask)
947 return -ENOMEM;
948
949 communities[i].intmask = intmask;
950 }
951
952 pctrl->context.pads = pads;
953 pctrl->context.communities = communities;
954#endif
955
956 return 0;
957}
958
959int intel_pinctrl_probe(struct platform_device *pdev,
960 const struct intel_pinctrl_soc_data *soc_data)
961{
962 struct intel_pinctrl *pctrl;
963 int i, ret, irq;
964
965 if (!soc_data)
966 return -EINVAL;
967
968 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
969 if (!pctrl)
970 return -ENOMEM;
971
972 pctrl->dev = &pdev->dev;
973 pctrl->soc = soc_data;
974 spin_lock_init(&pctrl->lock);
975
976 /*
977 * Make a copy of the communities which we can use to hold pointers
978 * to the registers.
979 */
980 pctrl->ncommunities = pctrl->soc->ncommunities;
981 pctrl->communities = devm_kcalloc(&pdev->dev, pctrl->ncommunities,
982 sizeof(*pctrl->communities), GFP_KERNEL);
983 if (!pctrl->communities)
984 return -ENOMEM;
985
986 for (i = 0; i < pctrl->ncommunities; i++) {
987 struct intel_community *community = &pctrl->communities[i];
988 struct resource *res;
989 void __iomem *regs;
990 u32 padbar;
991
992 *community = pctrl->soc->communities[i];
993
994 res = platform_get_resource(pdev, IORESOURCE_MEM,
995 community->barno);
996 regs = devm_ioremap_resource(&pdev->dev, res);
997 if (IS_ERR(regs))
998 return PTR_ERR(regs);
999
1000 /* Read offset of the pad configuration registers */
1001 padbar = readl(regs + PADBAR);
1002
1003 community->regs = regs;
1004 community->pad_regs = regs + padbar;
1005 community->ngpps = DIV_ROUND_UP(community->npins, NPADS_IN_GPP);
1006 }
1007
1008 irq = platform_get_irq(pdev, 0);
1009 if (irq < 0) {
1010 dev_err(&pdev->dev, "failed to get interrupt number\n");
1011 return irq;
1012 }
1013
1014 ret = intel_pinctrl_pm_init(pctrl);
1015 if (ret)
1016 return ret;
1017
1018 pctrl->pctldesc = intel_pinctrl_desc;
1019 pctrl->pctldesc.name = dev_name(&pdev->dev);
1020 pctrl->pctldesc.pins = pctrl->soc->pins;
1021 pctrl->pctldesc.npins = pctrl->soc->npins;
1022
1023 pctrl->pctldev = pinctrl_register(&pctrl->pctldesc, &pdev->dev, pctrl);
1024 if (!pctrl->pctldev) {
1025 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1026 return -ENODEV;
1027 }
1028
1029 ret = intel_gpio_probe(pctrl, irq);
1030 if (ret) {
1031 pinctrl_unregister(pctrl->pctldev);
1032 return ret;
1033 }
1034
1035 platform_set_drvdata(pdev, pctrl);
1036
1037 return 0;
1038}
1039EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
1040
1041int intel_pinctrl_remove(struct platform_device *pdev)
1042{
1043 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1044
1045 gpiochip_remove(&pctrl->chip);
1046 pinctrl_unregister(pctrl->pctldev);
1047
1048 return 0;
1049}
1050EXPORT_SYMBOL_GPL(intel_pinctrl_remove);
1051
1052#ifdef CONFIG_PM_SLEEP
1053int intel_pinctrl_suspend(struct device *dev)
1054{
1055 struct platform_device *pdev = to_platform_device(dev);
1056 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1057 struct intel_community_context *communities;
1058 struct intel_pad_context *pads;
1059 int i;
1060
1061 pads = pctrl->context.pads;
1062 for (i = 0; i < pctrl->soc->npins; i++) {
1063 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1064 u32 val;
1065
1066 if (!intel_pad_usable(pctrl, desc->number))
1067 continue;
1068
1069 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG0));
1070 pads[i].padcfg0 = val & ~PADCFG0_GPIORXSTATE;
1071 val = readl(intel_get_padcfg(pctrl, desc->number, PADCFG1));
1072 pads[i].padcfg1 = val;
1073 }
1074
1075 communities = pctrl->context.communities;
1076 for (i = 0; i < pctrl->ncommunities; i++) {
1077 struct intel_community *community = &pctrl->communities[i];
1078 void __iomem *base;
1079 unsigned gpp;
1080
1081 base = community->regs + community->ie_offset;
1082 for (gpp = 0; gpp < community->ngpps; gpp++)
1083 communities[i].intmask[gpp] = readl(base + gpp * 4);
1084 }
1085
1086 return 0;
1087}
1088EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
1089
1090int intel_pinctrl_resume(struct device *dev)
1091{
1092 struct platform_device *pdev = to_platform_device(dev);
1093 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
1094 const struct intel_community_context *communities;
1095 const struct intel_pad_context *pads;
1096 int i;
1097
1098 /* Mask all interrupts */
1099 intel_gpio_irq_init(pctrl);
1100
1101 pads = pctrl->context.pads;
1102 for (i = 0; i < pctrl->soc->npins; i++) {
1103 const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1104 void __iomem *padcfg;
1105 u32 val;
1106
1107 if (!intel_pad_usable(pctrl, desc->number))
1108 continue;
1109
1110 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1111 val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1112 if (val != pads[i].padcfg0) {
1113 writel(pads[i].padcfg0, padcfg);
1114 dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1115 desc->number, readl(padcfg));
1116 }
1117
1118 padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1119 val = readl(padcfg);
1120 if (val != pads[i].padcfg1) {
1121 writel(pads[i].padcfg1, padcfg);
1122 dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1123 desc->number, readl(padcfg));
1124 }
1125 }
1126
1127 communities = pctrl->context.communities;
1128 for (i = 0; i < pctrl->ncommunities; i++) {
1129 struct intel_community *community = &pctrl->communities[i];
1130 void __iomem *base;
1131 unsigned gpp;
1132
1133 base = community->regs + community->ie_offset;
1134 for (gpp = 0; gpp < community->ngpps; gpp++) {
1135 writel(communities[i].intmask[gpp], base + gpp * 4);
1136 dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1137 readl(base + gpp * 4));
1138 }
1139 }
1140
1141 return 0;
1142}
1143EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
1144#endif
1145
1146MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
1147MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
1148MODULE_DESCRIPTION("Intel pinctrl/GPIO core driver");
1149MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/intel/pinctrl-intel.h b/drivers/pinctrl/intel/pinctrl-intel.h
new file mode 100644
index 000000000000..4ec8b572a288
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-intel.h
@@ -0,0 +1,128 @@
1/*
2 * Core pinctrl/GPIO driver for Intel GPIO controllers
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef PINCTRL_INTEL_H
14#define PINCTRL_INTEL_H
15
16struct pinctrl_pin_desc;
17struct platform_device;
18struct device;
19
20/**
21 * struct intel_pingroup - Description about group of pins
22 * @name: Name of the groups
23 * @pins: All pins in this group
24 * @npins: Number of pins in this groups
25 * @mode: Native mode in which the group is muxed out @pins
26 */
27struct intel_pingroup {
28 const char *name;
29 const unsigned *pins;
30 size_t npins;
31 unsigned short mode;
32};
33
34/**
35 * struct intel_function - Description about a function
36 * @name: Name of the function
37 * @groups: An array of groups for this function
38 * @ngroups: Number of groups in @groups
39 */
40struct intel_function {
41 const char *name;
42 const char * const *groups;
43 size_t ngroups;
44};
45
46/**
47 * struct intel_community - Intel pin community description
48 * @barno: MMIO BAR number where registers for this community reside
49 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
50 * then there is no support for owner.
51 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
52 * locking is not supported.
53 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
54 * is assumed that the host owns the pin (rather than
55 * ACPI).
56 * @ie_offset: Register offset of GPI_IE from @regs.
57 * @pin_base: Starting pin of pins in this community
58 * @npins: Number of pins in this community
59 * @regs: Community specific common registers (reserved for core driver)
60 * @pad_regs: Community specific pad registers (reserved for core driver)
61 * @ngpps: Number of groups (hw groups) in this community (reserved for
62 * core driver)
63 */
64struct intel_community {
65 unsigned barno;
66 unsigned padown_offset;
67 unsigned padcfglock_offset;
68 unsigned hostown_offset;
69 unsigned ie_offset;
70 unsigned pin_base;
71 size_t npins;
72 void __iomem *regs;
73 void __iomem *pad_regs;
74 size_t ngpps;
75};
76
77#define PIN_GROUP(n, p, m) \
78 { \
79 .name = (n), \
80 .pins = (p), \
81 .npins = ARRAY_SIZE((p)), \
82 .mode = (m), \
83 }
84
85#define FUNCTION(n, g) \
86 { \
87 .name = (n), \
88 .groups = (g), \
89 .ngroups = ARRAY_SIZE((g)), \
90 }
91
92/**
93 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
94 * @uid: ACPI _UID for the probe driver use if needed
95 * @pins: Array if pins this pinctrl controls
96 * @npins: Number of pins in the array
97 * @groups: Array of pin groups
98 * @ngroups: Number of groups in the array
99 * @functions: Array of functions
100 * @nfunctions: Number of functions in the array
101 * @communities: Array of communities this pinctrl handles
102 * @ncommunities: Number of communities in the array
103 *
104 * The @communities is used as a template by the core driver. It will make
105 * copy of all communities and fill in rest of the information.
106 */
107struct intel_pinctrl_soc_data {
108 const char *uid;
109 const struct pinctrl_pin_desc *pins;
110 size_t npins;
111 const struct intel_pingroup *groups;
112 size_t ngroups;
113 const struct intel_function *functions;
114 size_t nfunctions;
115 const struct intel_community *communities;
116 size_t ncommunities;
117};
118
119int intel_pinctrl_probe(struct platform_device *pdev,
120 const struct intel_pinctrl_soc_data *soc_data);
121int intel_pinctrl_remove(struct platform_device *pdev);
122
123#ifdef CONFIG_PM_SLEEP
124int intel_pinctrl_suspend(struct device *dev);
125int intel_pinctrl_resume(struct device *dev);
126#endif
127
128#endif /* PINCTRL_INTEL_H */
diff --git a/drivers/pinctrl/intel/pinctrl-sunrisepoint.c b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
new file mode 100644
index 000000000000..55d025dc89e8
--- /dev/null
+++ b/drivers/pinctrl/intel/pinctrl-sunrisepoint.c
@@ -0,0 +1,336 @@
1/*
2 * Intel Sunrisepoint PCH pinctrl/GPIO driver
3 *
4 * Copyright (C) 2015, Intel Corporation
5 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
6 * Mika Westerberg <mika.westerberg@linux.intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/acpi.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/pm.h>
17#include <linux/pinctrl/pinctrl.h>
18
19#include "pinctrl-intel.h"
20
21#define SPT_PAD_OWN 0x020
22#define SPT_PADCFGLOCK 0x0a0
23#define SPT_HOSTSW_OWN 0x0d0
24#define SPT_GPI_IE 0x120
25
26#define SPT_COMMUNITY(b, s, e) \
27 { \
28 .barno = (b), \
29 .padown_offset = SPT_PAD_OWN, \
30 .padcfglock_offset = SPT_PADCFGLOCK, \
31 .hostown_offset = SPT_HOSTSW_OWN, \
32 .ie_offset = SPT_GPI_IE, \
33 .pin_base = (s), \
34 .npins = ((e) - (s) + 1), \
35 }
36
37/* Sunrisepoint-LP */
38static const struct pinctrl_pin_desc sptlp_pins[] = {
39 /* GPP_A */
40 PINCTRL_PIN(0, "RCINB"),
41 PINCTRL_PIN(1, "LAD_0"),
42 PINCTRL_PIN(2, "LAD_1"),
43 PINCTRL_PIN(3, "LAD_2"),
44 PINCTRL_PIN(4, "LAD_3"),
45 PINCTRL_PIN(5, "LFRAMEB"),
46 PINCTRL_PIN(6, "SERIQ"),
47 PINCTRL_PIN(7, "PIRQAB"),
48 PINCTRL_PIN(8, "CLKRUNB"),
49 PINCTRL_PIN(9, "CLKOUT_LPC_0"),
50 PINCTRL_PIN(10, "CLKOUT_LPC_1"),
51 PINCTRL_PIN(11, "PMEB"),
52 PINCTRL_PIN(12, "BM_BUSYB"),
53 PINCTRL_PIN(13, "SUSWARNB_SUS_PWRDNACK"),
54 PINCTRL_PIN(14, "SUS_STATB"),
55 PINCTRL_PIN(15, "SUSACKB"),
56 PINCTRL_PIN(16, "SD_1P8_SEL"),
57 PINCTRL_PIN(17, "SD_PWR_EN_B"),
58 PINCTRL_PIN(18, "ISH_GP_0"),
59 PINCTRL_PIN(19, "ISH_GP_1"),
60 PINCTRL_PIN(20, "ISH_GP_2"),
61 PINCTRL_PIN(21, "ISH_GP_3"),
62 PINCTRL_PIN(22, "ISH_GP_4"),
63 PINCTRL_PIN(23, "ISH_GP_5"),
64 /* GPP_B */
65 PINCTRL_PIN(24, "CORE_VID_0"),
66 PINCTRL_PIN(25, "CORE_VID_1"),
67 PINCTRL_PIN(26, "VRALERTB"),
68 PINCTRL_PIN(27, "CPU_GP_2"),
69 PINCTRL_PIN(28, "CPU_GP_3"),
70 PINCTRL_PIN(29, "SRCCLKREQB_0"),
71 PINCTRL_PIN(30, "SRCCLKREQB_1"),
72 PINCTRL_PIN(31, "SRCCLKREQB_2"),
73 PINCTRL_PIN(32, "SRCCLKREQB_3"),
74 PINCTRL_PIN(33, "SRCCLKREQB_4"),
75 PINCTRL_PIN(34, "SRCCLKREQB_5"),
76 PINCTRL_PIN(35, "EXT_PWR_GATEB"),
77 PINCTRL_PIN(36, "SLP_S0B"),
78 PINCTRL_PIN(37, "PLTRSTB"),
79 PINCTRL_PIN(38, "SPKR"),
80 PINCTRL_PIN(39, "GSPI0_CSB"),
81 PINCTRL_PIN(40, "GSPI0_CLK"),
82 PINCTRL_PIN(41, "GSPI0_MISO"),
83 PINCTRL_PIN(42, "GSPI0_MOSI"),
84 PINCTRL_PIN(43, "GSPI1_CSB"),
85 PINCTRL_PIN(44, "GSPI1_CLK"),
86 PINCTRL_PIN(45, "GSPI1_MISO"),
87 PINCTRL_PIN(46, "GSPI1_MOSI"),
88 PINCTRL_PIN(47, "SML1ALERTB"),
89 /* GPP_C */
90 PINCTRL_PIN(48, "SMBCLK"),
91 PINCTRL_PIN(49, "SMBDATA"),
92 PINCTRL_PIN(50, "SMBALERTB"),
93 PINCTRL_PIN(51, "SML0CLK"),
94 PINCTRL_PIN(52, "SML0DATA"),
95 PINCTRL_PIN(53, "SML0ALERTB"),
96 PINCTRL_PIN(54, "SML1CLK"),
97 PINCTRL_PIN(55, "SML1DATA"),
98 PINCTRL_PIN(56, "UART0_RXD"),
99 PINCTRL_PIN(57, "UART0_TXD"),
100 PINCTRL_PIN(58, "UART0_RTSB"),
101 PINCTRL_PIN(59, "UART0_CTSB"),
102 PINCTRL_PIN(60, "UART1_RXD"),
103 PINCTRL_PIN(61, "UART1_TXD"),
104 PINCTRL_PIN(62, "UART1_RTSB"),
105 PINCTRL_PIN(63, "UART1_CTSB"),
106 PINCTRL_PIN(64, "I2C0_SDA"),
107 PINCTRL_PIN(65, "I2C0_SCL"),
108 PINCTRL_PIN(66, "I2C1_SDA"),
109 PINCTRL_PIN(67, "I2C1_SCL"),
110 PINCTRL_PIN(68, "UART2_RXD"),
111 PINCTRL_PIN(69, "UART2_TXD"),
112 PINCTRL_PIN(70, "UART2_RTSB"),
113 PINCTRL_PIN(71, "UART2_CTSB"),
114 /* GPP_D */
115 PINCTRL_PIN(72, "SPI1_CSB"),
116 PINCTRL_PIN(73, "SPI1_CLK"),
117 PINCTRL_PIN(74, "SPI1_MISO_IO_1"),
118 PINCTRL_PIN(75, "SPI1_MOSI_IO_0"),
119 PINCTRL_PIN(76, "FLASHTRIG"),
120 PINCTRL_PIN(77, "ISH_I2C0_SDA"),
121 PINCTRL_PIN(78, "ISH_I2C0_SCL"),
122 PINCTRL_PIN(79, "ISH_I2C1_SDA"),
123 PINCTRL_PIN(80, "ISH_I2C1_SCL"),
124 PINCTRL_PIN(81, "ISH_SPI_CSB"),
125 PINCTRL_PIN(82, "ISH_SPI_CLK"),
126 PINCTRL_PIN(83, "ISH_SPI_MISO"),
127 PINCTRL_PIN(84, "ISH_SPI_MOSI"),
128 PINCTRL_PIN(85, "ISH_UART0_RXD"),
129 PINCTRL_PIN(86, "ISH_UART0_TXD"),
130 PINCTRL_PIN(87, "ISH_UART0_RTSB"),
131 PINCTRL_PIN(88, "ISH_UART0_CTSB"),
132 PINCTRL_PIN(89, "DMIC_CLK_1"),
133 PINCTRL_PIN(90, "DMIC_DATA_1"),
134 PINCTRL_PIN(91, "DMIC_CLK_0"),
135 PINCTRL_PIN(92, "DMIC_DATA_0"),
136 PINCTRL_PIN(93, "SPI1_IO_2"),
137 PINCTRL_PIN(94, "SPI1_IO_3"),
138 PINCTRL_PIN(95, "SSP_MCLK"),
139 /* GPP_E */
140 PINCTRL_PIN(96, "SATAXPCIE_0"),
141 PINCTRL_PIN(97, "SATAXPCIE_1"),
142 PINCTRL_PIN(98, "SATAXPCIE_2"),
143 PINCTRL_PIN(99, "CPU_GP_0"),
144 PINCTRL_PIN(100, "SATA_DEVSLP_0"),
145 PINCTRL_PIN(101, "SATA_DEVSLP_1"),
146 PINCTRL_PIN(102, "SATA_DEVSLP_2"),
147 PINCTRL_PIN(103, "CPU_GP_1"),
148 PINCTRL_PIN(104, "SATA_LEDB"),
149 PINCTRL_PIN(105, "USB2_OCB_0"),
150 PINCTRL_PIN(106, "USB2_OCB_1"),
151 PINCTRL_PIN(107, "USB2_OCB_2"),
152 PINCTRL_PIN(108, "USB2_OCB_3"),
153 PINCTRL_PIN(109, "DDSP_HPD_0"),
154 PINCTRL_PIN(110, "DDSP_HPD_1"),
155 PINCTRL_PIN(111, "DDSP_HPD_2"),
156 PINCTRL_PIN(112, "DDSP_HPD_3"),
157 PINCTRL_PIN(113, "EDP_HPD"),
158 PINCTRL_PIN(114, "DDPB_CTRLCLK"),
159 PINCTRL_PIN(115, "DDPB_CTRLDATA"),
160 PINCTRL_PIN(116, "DDPC_CTRLCLK"),
161 PINCTRL_PIN(117, "DDPC_CTRLDATA"),
162 PINCTRL_PIN(118, "DDPD_CTRLCLK"),
163 PINCTRL_PIN(119, "DDPD_CTRLDATA"),
164 /* GPP_F */
165 PINCTRL_PIN(120, "SSP2_SCLK"),
166 PINCTRL_PIN(121, "SSP2_SFRM"),
167 PINCTRL_PIN(122, "SSP2_TXD"),
168 PINCTRL_PIN(123, "SSP2_RXD"),
169 PINCTRL_PIN(124, "I2C2_SDA"),
170 PINCTRL_PIN(125, "I2C2_SCL"),
171 PINCTRL_PIN(126, "I2C3_SDA"),
172 PINCTRL_PIN(127, "I2C3_SCL"),
173 PINCTRL_PIN(128, "I2C4_SDA"),
174 PINCTRL_PIN(129, "I2C4_SCL"),
175 PINCTRL_PIN(130, "I2C5_SDA"),
176 PINCTRL_PIN(131, "I2C5_SCL"),
177 PINCTRL_PIN(132, "EMMC_CMD"),
178 PINCTRL_PIN(133, "EMMC_DATA_0"),
179 PINCTRL_PIN(134, "EMMC_DATA_1"),
180 PINCTRL_PIN(135, "EMMC_DATA_2"),
181 PINCTRL_PIN(136, "EMMC_DATA_3"),
182 PINCTRL_PIN(137, "EMMC_DATA_4"),
183 PINCTRL_PIN(138, "EMMC_DATA_5"),
184 PINCTRL_PIN(139, "EMMC_DATA_6"),
185 PINCTRL_PIN(140, "EMMC_DATA_7"),
186 PINCTRL_PIN(141, "EMMC_RCLK"),
187 PINCTRL_PIN(142, "EMMC_CLK"),
188 PINCTRL_PIN(143, "GPP_F_23"),
189 /* GPP_G */
190 PINCTRL_PIN(144, "SD_CMD"),
191 PINCTRL_PIN(145, "SD_DATA_0"),
192 PINCTRL_PIN(146, "SD_DATA_1"),
193 PINCTRL_PIN(147, "SD_DATA_2"),
194 PINCTRL_PIN(148, "SD_DATA_3"),
195 PINCTRL_PIN(149, "SD_CDB"),
196 PINCTRL_PIN(150, "SD_CLK"),
197 PINCTRL_PIN(151, "SD_WP"),
198};
199
200static const unsigned sptlp_spi0_pins[] = { 39, 40, 41, 42 };
201static const unsigned sptlp_spi1_pins[] = { 43, 44, 45, 46 };
202static const unsigned sptlp_uart0_pins[] = { 56, 57, 58, 59 };
203static const unsigned sptlp_uart1_pins[] = { 60, 61, 62, 63 };
204static const unsigned sptlp_uart2_pins[] = { 68, 69, 71, 71 };
205static const unsigned sptlp_i2c0_pins[] = { 64, 65 };
206static const unsigned sptlp_i2c1_pins[] = { 66, 67 };
207static const unsigned sptlp_i2c2_pins[] = { 124, 125 };
208static const unsigned sptlp_i2c3_pins[] = { 126, 127 };
209static const unsigned sptlp_i2c4_pins[] = { 128, 129 };
210static const unsigned sptlp_i2c4b_pins[] = { 85, 86 };
211static const unsigned sptlp_i2c5_pins[] = { 130, 131 };
212static const unsigned sptlp_ssp2_pins[] = { 120, 121, 122, 123 };
213static const unsigned sptlp_emmc_pins[] = {
214 132, 133, 134, 135, 136, 137, 138, 139, 140, 141, 142,
215};
216static const unsigned sptlp_sd_pins[] = {
217 144, 145, 146, 147, 148, 149, 150, 151,
218};
219
220static const struct intel_pingroup sptlp_groups[] = {
221 PIN_GROUP("spi0_grp", sptlp_spi0_pins, 1),
222 PIN_GROUP("spi1_grp", sptlp_spi1_pins, 1),
223 PIN_GROUP("uart0_grp", sptlp_uart0_pins, 1),
224 PIN_GROUP("uart1_grp", sptlp_uart1_pins, 1),
225 PIN_GROUP("uart2_grp", sptlp_uart2_pins, 1),
226 PIN_GROUP("i2c0_grp", sptlp_i2c0_pins, 1),
227 PIN_GROUP("i2c1_grp", sptlp_i2c1_pins, 1),
228 PIN_GROUP("i2c2_grp", sptlp_i2c2_pins, 1),
229 PIN_GROUP("i2c3_grp", sptlp_i2c3_pins, 1),
230 PIN_GROUP("i2c4_grp", sptlp_i2c4_pins, 1),
231 PIN_GROUP("i2c4b_grp", sptlp_i2c4b_pins, 3),
232 PIN_GROUP("i2c5_grp", sptlp_i2c5_pins, 1),
233 PIN_GROUP("ssp2_grp", sptlp_ssp2_pins, 1),
234 PIN_GROUP("emmc_grp", sptlp_emmc_pins, 1),
235 PIN_GROUP("sd_grp", sptlp_sd_pins, 1),
236};
237
238static const char * const sptlp_spi0_groups[] = { "spi0_grp" };
239static const char * const sptlp_spi1_groups[] = { "spi0_grp" };
240static const char * const sptlp_uart0_groups[] = { "uart0_grp" };
241static const char * const sptlp_uart1_groups[] = { "uart1_grp" };
242static const char * const sptlp_uart2_groups[] = { "uart2_grp" };
243static const char * const sptlp_i2c0_groups[] = { "i2c0_grp" };
244static const char * const sptlp_i2c1_groups[] = { "i2c1_grp" };
245static const char * const sptlp_i2c2_groups[] = { "i2c2_grp" };
246static const char * const sptlp_i2c3_groups[] = { "i2c3_grp" };
247static const char * const sptlp_i2c4_groups[] = { "i2c4_grp", "i2c4b_grp" };
248static const char * const sptlp_i2c5_groups[] = { "i2c5_grp" };
249static const char * const sptlp_ssp2_groups[] = { "ssp2_grp" };
250static const char * const sptlp_emmc_groups[] = { "emmc_grp" };
251static const char * const sptlp_sd_groups[] = { "sd_grp" };
252
253static const struct intel_function sptlp_functions[] = {
254 FUNCTION("spi0", sptlp_spi0_groups),
255 FUNCTION("spi1", sptlp_spi1_groups),
256 FUNCTION("uart0", sptlp_uart0_groups),
257 FUNCTION("uart1", sptlp_uart1_groups),
258 FUNCTION("uart2", sptlp_uart2_groups),
259 FUNCTION("i2c0", sptlp_i2c0_groups),
260 FUNCTION("i2c1", sptlp_i2c1_groups),
261 FUNCTION("i2c2", sptlp_i2c2_groups),
262 FUNCTION("i2c3", sptlp_i2c3_groups),
263 FUNCTION("i2c4", sptlp_i2c4_groups),
264 FUNCTION("i2c5", sptlp_i2c5_groups),
265 FUNCTION("ssp2", sptlp_ssp2_groups),
266 FUNCTION("emmc", sptlp_emmc_groups),
267 FUNCTION("sd", sptlp_sd_groups),
268};
269
270static const struct intel_community sptlp_communities[] = {
271 SPT_COMMUNITY(0, 0, 47),
272 SPT_COMMUNITY(1, 48, 119),
273 SPT_COMMUNITY(2, 120, 151),
274};
275
276static const struct intel_pinctrl_soc_data sptlp_soc_data = {
277 .pins = sptlp_pins,
278 .npins = ARRAY_SIZE(sptlp_pins),
279 .groups = sptlp_groups,
280 .ngroups = ARRAY_SIZE(sptlp_groups),
281 .functions = sptlp_functions,
282 .nfunctions = ARRAY_SIZE(sptlp_functions),
283 .communities = sptlp_communities,
284 .ncommunities = ARRAY_SIZE(sptlp_communities),
285};
286
287static const struct acpi_device_id spt_pinctrl_acpi_match[] = {
288 { "INT344B", (kernel_ulong_t)&sptlp_soc_data },
289 { }
290};
291MODULE_DEVICE_TABLE(acpi, spt_pinctrl_acpi_match);
292
293static int spt_pinctrl_probe(struct platform_device *pdev)
294{
295 const struct intel_pinctrl_soc_data *soc_data;
296 const struct acpi_device_id *id;
297
298 id = acpi_match_device(spt_pinctrl_acpi_match, &pdev->dev);
299 if (!id || !id->driver_data)
300 return -ENODEV;
301
302 soc_data = (const struct intel_pinctrl_soc_data *)id->driver_data;
303 return intel_pinctrl_probe(pdev, soc_data);
304}
305
306static const struct dev_pm_ops spt_pinctrl_pm_ops = {
307 SET_LATE_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend,
308 intel_pinctrl_resume)
309};
310
311static struct platform_driver spt_pinctrl_driver = {
312 .probe = spt_pinctrl_probe,
313 .remove = intel_pinctrl_remove,
314 .driver = {
315 .name = "sunrisepoint-pinctrl",
316 .acpi_match_table = spt_pinctrl_acpi_match,
317 .pm = &spt_pinctrl_pm_ops,
318 },
319};
320
321static int __init spt_pinctrl_init(void)
322{
323 return platform_driver_register(&spt_pinctrl_driver);
324}
325subsys_initcall(spt_pinctrl_init);
326
327static void __exit spt_pinctrl_exit(void)
328{
329 platform_driver_unregister(&spt_pinctrl_driver);
330}
331module_exit(spt_pinctrl_exit);
332
333MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");
334MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
335MODULE_DESCRIPTION("Intel Sunrisepoint PCH pinctrl/GPIO driver");
336MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
new file mode 100644
index 000000000000..5983cf5b2c46
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -0,0 +1,23 @@
1if ARCH_MEDIATEK || COMPILE_TEST
2
3config PINCTRL_MTK_COMMON
4 bool
5 select PINMUX
6 select GENERIC_PINCONF
7 select GPIOLIB
8 select OF_GPIO
9
10# For ARMv7 SoCs
11config PINCTRL_MT8135
12 bool "Mediatek MT8135 pin control" if COMPILE_TEST && !MACH_MT8135
13 default MACH_MT8135
14 select PINCTRL_MTK_COMMON
15
16# For ARMv8 SoCs
17config PINCTRL_MT8173
18 bool "Mediatek MT8173 pin control"
19 depends on ARM64 || COMPILE_TEST
20 default ARM64 && ARCH_MEDIATEK
21 select PINCTRL_MTK_COMMON
22
23endif
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
new file mode 100644
index 000000000000..d8606a2179cf
--- /dev/null
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -0,0 +1,6 @@
1# Core
2obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o
3
4# SoC Drivers
5obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
6obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
new file mode 100644
index 000000000000..f1e1e187ce96
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
@@ -0,0 +1,376 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/regmap.h>
21#include <dt-bindings/pinctrl/mt65xx.h>
22
23#include "pinctrl-mtk-common.h"
24#include "pinctrl-mtk-mt8135.h"
25
26#define DRV_BASE1 0x500
27#define DRV_BASE2 0x510
28#define PUPD_BASE1 0x400
29#define PUPD_BASE2 0x450
30#define R0_BASE1 0x4d0
31#define R1_BASE1 0x200
32#define R1_BASE2 0x250
33
34struct mtk_spec_pull_set {
35 unsigned int pin;
36 unsigned int pupd_offset;
37 unsigned char pupd_bit;
38 unsigned int r0_offset;
39 unsigned char r0_bit;
40 unsigned int r1_offset;
41 unsigned char r1_bit;
42};
43
44#define SPEC_PULL(_pin, _pupd_offset, _pupd_bit, _r0_offset, \
45 _r0_bit, _r1_offset, _r1_bit) \
46 { \
47 .pin = _pin, \
48 .pupd_offset = _pupd_offset, \
49 .pupd_bit = _pupd_bit, \
50 .r0_offset = _r0_offset, \
51 .r0_bit = _r0_bit, \
52 .r1_offset = _r1_offset, \
53 .r1_bit = _r1_bit, \
54 }
55
56static const struct mtk_drv_group_desc mt8135_drv_grp[] = {
57 /* E8E4E2 2/4/6/8/10/12/14/16 */
58 MTK_DRV_GRP(2, 16, 0, 2, 2),
59 /* E8E4 4/8/12/16 */
60 MTK_DRV_GRP(4, 16, 1, 2, 4),
61 /* E4E2 2/4/6/8 */
62 MTK_DRV_GRP(2, 8, 0, 1, 2),
63 /* E16E8E4 4/8/12/16/20/24/28/32 */
64 MTK_DRV_GRP(4, 32, 0, 2, 4)
65};
66
67static const struct mtk_pin_drv_grp mt8135_pin_drv[] = {
68 MTK_PIN_DRV_GRP(0, DRV_BASE1, 0, 0),
69 MTK_PIN_DRV_GRP(1, DRV_BASE1, 0, 0),
70 MTK_PIN_DRV_GRP(2, DRV_BASE1, 0, 0),
71 MTK_PIN_DRV_GRP(3, DRV_BASE1, 0, 0),
72 MTK_PIN_DRV_GRP(4, DRV_BASE1, 4, 0),
73 MTK_PIN_DRV_GRP(5, DRV_BASE1, 8, 0),
74 MTK_PIN_DRV_GRP(6, DRV_BASE1, 0, 0),
75 MTK_PIN_DRV_GRP(7, DRV_BASE1, 0, 0),
76 MTK_PIN_DRV_GRP(8, DRV_BASE1, 0, 0),
77 MTK_PIN_DRV_GRP(9, DRV_BASE1, 0, 0),
78
79 MTK_PIN_DRV_GRP(10, DRV_BASE1, 12, 1),
80 MTK_PIN_DRV_GRP(11, DRV_BASE1, 12, 1),
81 MTK_PIN_DRV_GRP(12, DRV_BASE1, 12, 1),
82 MTK_PIN_DRV_GRP(13, DRV_BASE1, 12, 1),
83 MTK_PIN_DRV_GRP(14, DRV_BASE1, 12, 1),
84 MTK_PIN_DRV_GRP(15, DRV_BASE1, 12, 1),
85 MTK_PIN_DRV_GRP(16, DRV_BASE1, 12, 1),
86 MTK_PIN_DRV_GRP(17, DRV_BASE1, 16, 1),
87 MTK_PIN_DRV_GRP(18, DRV_BASE1, 16, 1),
88 MTK_PIN_DRV_GRP(19, DRV_BASE1, 16, 1),
89 MTK_PIN_DRV_GRP(20, DRV_BASE1, 16, 1),
90 MTK_PIN_DRV_GRP(21, DRV_BASE1, 16, 1),
91 MTK_PIN_DRV_GRP(22, DRV_BASE1, 16, 1),
92 MTK_PIN_DRV_GRP(23, DRV_BASE1, 16, 1),
93 MTK_PIN_DRV_GRP(24, DRV_BASE1, 16, 1),
94 MTK_PIN_DRV_GRP(33, DRV_BASE1, 24, 1),
95 MTK_PIN_DRV_GRP(34, DRV_BASE2, 12, 2),
96 MTK_PIN_DRV_GRP(37, DRV_BASE2, 20, 1),
97 MTK_PIN_DRV_GRP(38, DRV_BASE2, 20, 1),
98 MTK_PIN_DRV_GRP(39, DRV_BASE2, 20, 1),
99 MTK_PIN_DRV_GRP(40, DRV_BASE2, 24, 1),
100 MTK_PIN_DRV_GRP(41, DRV_BASE2, 24, 1),
101 MTK_PIN_DRV_GRP(42, DRV_BASE2, 24, 1),
102 MTK_PIN_DRV_GRP(43, DRV_BASE2, 28, 1),
103 MTK_PIN_DRV_GRP(44, DRV_BASE2, 28, 1),
104 MTK_PIN_DRV_GRP(45, DRV_BASE2, 28, 1),
105 MTK_PIN_DRV_GRP(46, DRV_BASE2, 28, 1),
106 MTK_PIN_DRV_GRP(47, DRV_BASE2, 28, 1),
107
108 MTK_PIN_DRV_GRP(49, DRV_BASE2+0x10, 0, 1),
109 MTK_PIN_DRV_GRP(50, DRV_BASE2+0x10, 4, 1),
110 MTK_PIN_DRV_GRP(51, DRV_BASE2+0x10, 8, 1),
111 MTK_PIN_DRV_GRP(52, DRV_BASE2+0x10, 12, 2),
112 MTK_PIN_DRV_GRP(53, DRV_BASE2+0x10, 16, 1),
113 MTK_PIN_DRV_GRP(54, DRV_BASE2+0x10, 20, 1),
114 MTK_PIN_DRV_GRP(55, DRV_BASE2+0x10, 24, 1),
115 MTK_PIN_DRV_GRP(56, DRV_BASE2+0x10, 28, 1),
116
117 MTK_PIN_DRV_GRP(57, DRV_BASE2+0x20, 0, 1),
118 MTK_PIN_DRV_GRP(58, DRV_BASE2+0x20, 0, 1),
119 MTK_PIN_DRV_GRP(59, DRV_BASE2+0x20, 0, 1),
120 MTK_PIN_DRV_GRP(60, DRV_BASE2+0x20, 0, 1),
121 MTK_PIN_DRV_GRP(61, DRV_BASE2+0x20, 0, 1),
122 MTK_PIN_DRV_GRP(62, DRV_BASE2+0x20, 0, 1),
123 MTK_PIN_DRV_GRP(63, DRV_BASE2+0x20, 4, 1),
124 MTK_PIN_DRV_GRP(64, DRV_BASE2+0x20, 8, 1),
125 MTK_PIN_DRV_GRP(65, DRV_BASE2+0x20, 12, 1),
126 MTK_PIN_DRV_GRP(66, DRV_BASE2+0x20, 16, 1),
127 MTK_PIN_DRV_GRP(67, DRV_BASE2+0x20, 20, 1),
128 MTK_PIN_DRV_GRP(68, DRV_BASE2+0x20, 24, 1),
129 MTK_PIN_DRV_GRP(69, DRV_BASE2+0x20, 28, 1),
130
131 MTK_PIN_DRV_GRP(70, DRV_BASE2+0x30, 0, 1),
132 MTK_PIN_DRV_GRP(71, DRV_BASE2+0x30, 4, 1),
133 MTK_PIN_DRV_GRP(72, DRV_BASE2+0x30, 8, 1),
134 MTK_PIN_DRV_GRP(73, DRV_BASE2+0x30, 12, 1),
135 MTK_PIN_DRV_GRP(74, DRV_BASE2+0x30, 16, 1),
136 MTK_PIN_DRV_GRP(75, DRV_BASE2+0x30, 20, 1),
137 MTK_PIN_DRV_GRP(76, DRV_BASE2+0x30, 24, 1),
138 MTK_PIN_DRV_GRP(77, DRV_BASE2+0x30, 28, 3),
139 MTK_PIN_DRV_GRP(78, DRV_BASE2+0x30, 28, 3),
140
141 MTK_PIN_DRV_GRP(79, DRV_BASE2+0x40, 0, 3),
142 MTK_PIN_DRV_GRP(80, DRV_BASE2+0x40, 4, 3),
143
144 MTK_PIN_DRV_GRP(81, DRV_BASE2+0x30, 28, 3),
145 MTK_PIN_DRV_GRP(82, DRV_BASE2+0x30, 28, 3),
146
147 MTK_PIN_DRV_GRP(83, DRV_BASE2+0x40, 8, 3),
148 MTK_PIN_DRV_GRP(84, DRV_BASE2+0x40, 8, 3),
149 MTK_PIN_DRV_GRP(85, DRV_BASE2+0x40, 12, 3),
150 MTK_PIN_DRV_GRP(86, DRV_BASE2+0x40, 16, 3),
151 MTK_PIN_DRV_GRP(87, DRV_BASE2+0x40, 8, 3),
152 MTK_PIN_DRV_GRP(88, DRV_BASE2+0x40, 8, 3),
153
154 MTK_PIN_DRV_GRP(89, DRV_BASE2+0x50, 12, 0),
155 MTK_PIN_DRV_GRP(90, DRV_BASE2+0x50, 12, 0),
156 MTK_PIN_DRV_GRP(91, DRV_BASE2+0x50, 12, 0),
157 MTK_PIN_DRV_GRP(92, DRV_BASE2+0x50, 12, 0),
158 MTK_PIN_DRV_GRP(93, DRV_BASE2+0x50, 12, 0),
159 MTK_PIN_DRV_GRP(94, DRV_BASE2+0x50, 12, 0),
160 MTK_PIN_DRV_GRP(95, DRV_BASE2+0x50, 12, 0),
161
162 MTK_PIN_DRV_GRP(96, DRV_BASE1+0xb0, 28, 0),
163
164 MTK_PIN_DRV_GRP(97, DRV_BASE2+0x50, 12, 0),
165 MTK_PIN_DRV_GRP(98, DRV_BASE2+0x50, 16, 0),
166 MTK_PIN_DRV_GRP(99, DRV_BASE2+0x50, 20, 1),
167 MTK_PIN_DRV_GRP(102, DRV_BASE2+0x50, 24, 1),
168 MTK_PIN_DRV_GRP(103, DRV_BASE2+0x50, 28, 1),
169
170
171 MTK_PIN_DRV_GRP(104, DRV_BASE2+0x60, 0, 1),
172 MTK_PIN_DRV_GRP(105, DRV_BASE2+0x60, 4, 1),
173 MTK_PIN_DRV_GRP(106, DRV_BASE2+0x60, 4, 1),
174 MTK_PIN_DRV_GRP(107, DRV_BASE2+0x60, 4, 1),
175 MTK_PIN_DRV_GRP(108, DRV_BASE2+0x60, 4, 1),
176 MTK_PIN_DRV_GRP(109, DRV_BASE2+0x60, 8, 2),
177 MTK_PIN_DRV_GRP(110, DRV_BASE2+0x60, 12, 2),
178 MTK_PIN_DRV_GRP(111, DRV_BASE2+0x60, 16, 2),
179 MTK_PIN_DRV_GRP(112, DRV_BASE2+0x60, 20, 2),
180 MTK_PIN_DRV_GRP(113, DRV_BASE2+0x60, 24, 2),
181 MTK_PIN_DRV_GRP(114, DRV_BASE2+0x60, 28, 2),
182
183 MTK_PIN_DRV_GRP(115, DRV_BASE2+0x70, 0, 2),
184 MTK_PIN_DRV_GRP(116, DRV_BASE2+0x70, 4, 2),
185 MTK_PIN_DRV_GRP(117, DRV_BASE2+0x70, 8, 2),
186 MTK_PIN_DRV_GRP(118, DRV_BASE2+0x70, 12, 2),
187 MTK_PIN_DRV_GRP(119, DRV_BASE2+0x70, 16, 2),
188 MTK_PIN_DRV_GRP(120, DRV_BASE2+0x70, 20, 2),
189
190 MTK_PIN_DRV_GRP(181, DRV_BASE1+0xa0, 12, 1),
191 MTK_PIN_DRV_GRP(182, DRV_BASE1+0xa0, 16, 1),
192 MTK_PIN_DRV_GRP(183, DRV_BASE1+0xa0, 20, 1),
193 MTK_PIN_DRV_GRP(184, DRV_BASE1+0xa0, 24, 1),
194 MTK_PIN_DRV_GRP(185, DRV_BASE1+0xa0, 28, 1),
195
196 MTK_PIN_DRV_GRP(186, DRV_BASE1+0xb0, 0, 2),
197 MTK_PIN_DRV_GRP(187, DRV_BASE1+0xb0, 0, 2),
198 MTK_PIN_DRV_GRP(188, DRV_BASE1+0xb0, 0, 2),
199 MTK_PIN_DRV_GRP(189, DRV_BASE1+0xb0, 0, 2),
200 MTK_PIN_DRV_GRP(190, DRV_BASE1+0xb0, 4, 1),
201 MTK_PIN_DRV_GRP(191, DRV_BASE1+0xb0, 8, 1),
202 MTK_PIN_DRV_GRP(192, DRV_BASE1+0xb0, 12, 1),
203
204 MTK_PIN_DRV_GRP(197, DRV_BASE1+0xb0, 16, 0),
205 MTK_PIN_DRV_GRP(198, DRV_BASE1+0xb0, 16, 0),
206 MTK_PIN_DRV_GRP(199, DRV_BASE1+0xb0, 20, 0),
207 MTK_PIN_DRV_GRP(200, DRV_BASE1+0xb0, 24, 0),
208 MTK_PIN_DRV_GRP(201, DRV_BASE1+0xb0, 16, 0),
209 MTK_PIN_DRV_GRP(202, DRV_BASE1+0xb0, 16, 0)
210};
211
212static const struct mtk_spec_pull_set spec_pupd[] = {
213 SPEC_PULL(0, PUPD_BASE1, 0, R0_BASE1, 9, R1_BASE1, 0),
214 SPEC_PULL(1, PUPD_BASE1, 1, R0_BASE1, 8, R1_BASE1, 1),
215 SPEC_PULL(2, PUPD_BASE1, 2, R0_BASE1, 7, R1_BASE1, 2),
216 SPEC_PULL(3, PUPD_BASE1, 3, R0_BASE1, 6, R1_BASE1, 3),
217 SPEC_PULL(4, PUPD_BASE1, 4, R0_BASE1, 1, R1_BASE1, 4),
218 SPEC_PULL(5, PUPD_BASE1, 5, R0_BASE1, 0, R1_BASE1, 5),
219 SPEC_PULL(6, PUPD_BASE1, 6, R0_BASE1, 5, R1_BASE1, 6),
220 SPEC_PULL(7, PUPD_BASE1, 7, R0_BASE1, 4, R1_BASE1, 7),
221 SPEC_PULL(8, PUPD_BASE1, 8, R0_BASE1, 3, R1_BASE1, 8),
222 SPEC_PULL(9, PUPD_BASE1, 9, R0_BASE1, 2, R1_BASE1, 9),
223 SPEC_PULL(89, PUPD_BASE2, 9, R0_BASE1, 18, R1_BASE2, 9),
224 SPEC_PULL(90, PUPD_BASE2, 10, R0_BASE1, 19, R1_BASE2, 10),
225 SPEC_PULL(91, PUPD_BASE2, 11, R0_BASE1, 23, R1_BASE2, 11),
226 SPEC_PULL(92, PUPD_BASE2, 12, R0_BASE1, 24, R1_BASE2, 12),
227 SPEC_PULL(93, PUPD_BASE2, 13, R0_BASE1, 25, R1_BASE2, 13),
228 SPEC_PULL(94, PUPD_BASE2, 14, R0_BASE1, 22, R1_BASE2, 14),
229 SPEC_PULL(95, PUPD_BASE2, 15, R0_BASE1, 20, R1_BASE2, 15),
230 SPEC_PULL(96, PUPD_BASE2+0x10, 0, R0_BASE1, 16, R1_BASE2+0x10, 0),
231 SPEC_PULL(97, PUPD_BASE2+0x10, 1, R0_BASE1, 21, R1_BASE2+0x10, 1),
232 SPEC_PULL(98, PUPD_BASE2+0x10, 2, R0_BASE1, 17, R1_BASE2+0x10, 2),
233 SPEC_PULL(197, PUPD_BASE1+0xc0, 5, R0_BASE1, 13, R1_BASE2+0xc0, 5),
234 SPEC_PULL(198, PUPD_BASE2+0xc0, 6, R0_BASE1, 14, R1_BASE2+0xc0, 6),
235 SPEC_PULL(199, PUPD_BASE2+0xc0, 7, R0_BASE1, 11, R1_BASE2+0xc0, 7),
236 SPEC_PULL(200, PUPD_BASE2+0xc0, 8, R0_BASE1, 10, R1_BASE2+0xc0, 8),
237 SPEC_PULL(201, PUPD_BASE2+0xc0, 9, R0_BASE1, 13, R1_BASE2+0xc0, 9),
238 SPEC_PULL(202, PUPD_BASE2+0xc0, 10, R0_BASE1, 12, R1_BASE2+0xc0, 10)
239};
240
241static int spec_pull_set(struct regmap *regmap, unsigned int pin,
242 unsigned char align, bool isup, unsigned int r1r0)
243{
244 unsigned int i;
245 unsigned int reg_pupd, reg_set_r0, reg_set_r1;
246 unsigned int reg_rst_r0, reg_rst_r1;
247 bool find = false;
248
249 for (i = 0; i < ARRAY_SIZE(spec_pupd); i++) {
250 if (pin == spec_pupd[i].pin) {
251 find = true;
252 break;
253 }
254 }
255
256 if (!find)
257 return -EINVAL;
258
259 if (isup)
260 reg_pupd = spec_pupd[i].pupd_offset + align;
261 else
262 reg_pupd = spec_pupd[i].pupd_offset + (align << 1);
263
264 regmap_write(regmap, reg_pupd, spec_pupd[i].pupd_bit);
265
266 reg_set_r0 = spec_pupd[i].r0_offset + align;
267 reg_rst_r0 = spec_pupd[i].r0_offset + (align << 1);
268 reg_set_r1 = spec_pupd[i].r1_offset + align;
269 reg_rst_r1 = spec_pupd[i].r1_offset + (align << 1);
270
271 switch (r1r0) {
272 case MTK_PUPD_SET_R1R0_00:
273 regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
274 regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
275 break;
276 case MTK_PUPD_SET_R1R0_01:
277 regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
278 regmap_write(regmap, reg_rst_r1, spec_pupd[i].r1_bit);
279 break;
280 case MTK_PUPD_SET_R1R0_10:
281 regmap_write(regmap, reg_rst_r0, spec_pupd[i].r0_bit);
282 regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
283 break;
284 case MTK_PUPD_SET_R1R0_11:
285 regmap_write(regmap, reg_set_r0, spec_pupd[i].r0_bit);
286 regmap_write(regmap, reg_set_r1, spec_pupd[i].r1_bit);
287 break;
288 default:
289 return -EINVAL;
290 }
291
292 return 0;
293}
294
295static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
296 .pins = mtk_pins_mt8135,
297 .npins = ARRAY_SIZE(mtk_pins_mt8135),
298 .grp_desc = mt8135_drv_grp,
299 .n_grp_cls = ARRAY_SIZE(mt8135_drv_grp),
300 .pin_drv_grp = mt8135_pin_drv,
301 .n_pin_drv_grps = ARRAY_SIZE(mt8135_pin_drv),
302 .spec_pull_set = spec_pull_set,
303 .dir_offset = 0x0000,
304 .ies_offset = 0x0100,
305 .pullen_offset = 0x0200,
306 .smt_offset = 0x0300,
307 .pullsel_offset = 0x0400,
308 .invser_offset = 0x0600,
309 .dout_offset = 0x0800,
310 .din_offset = 0x0A00,
311 .pinmux_offset = 0x0C00,
312 .type1_start = 34,
313 .type1_end = 149,
314 .port_shf = 4,
315 .port_mask = 0xf,
316 .port_align = 4,
317 .chip_type = MTK_CHIP_TYPE_BASE,
318 .eint_offsets = {
319 .name = "mt8135_eint",
320 .stat = 0x000,
321 .ack = 0x040,
322 .mask = 0x080,
323 .mask_set = 0x0c0,
324 .mask_clr = 0x100,
325 .sens = 0x140,
326 .sens_set = 0x180,
327 .sens_clr = 0x1c0,
328 .soft = 0x200,
329 .soft_set = 0x240,
330 .soft_clr = 0x280,
331 .pol = 0x300,
332 .pol_set = 0x340,
333 .pol_clr = 0x380,
334 .dom_en = 0x400,
335 .dbnc_ctrl = 0x500,
336 .dbnc_set = 0x600,
337 .dbnc_clr = 0x700,
338 .port_mask = 7,
339 .ports = 6,
340 },
341 .ap_num = 192,
342 .db_cnt = 16,
343};
344
345static int mt8135_pinctrl_probe(struct platform_device *pdev)
346{
347 return mtk_pctrl_init(pdev, &mt8135_pinctrl_data);
348}
349
350static const struct of_device_id mt8135_pctrl_match[] = {
351 {
352 .compatible = "mediatek,mt8135-pinctrl",
353 },
354 { }
355};
356MODULE_DEVICE_TABLE(of, mt8135_pctrl_match);
357
358static struct platform_driver mtk_pinctrl_driver = {
359 .probe = mt8135_pinctrl_probe,
360 .driver = {
361 .name = "mediatek-mt8135-pinctrl",
362 .owner = THIS_MODULE,
363 .of_match_table = mt8135_pctrl_match,
364 },
365};
366
367static int __init mtk_pinctrl_init(void)
368{
369 return platform_driver_register(&mtk_pinctrl_driver);
370}
371
372module_init(mtk_pinctrl_init);
373
374MODULE_LICENSE("GPL");
375MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
376MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
new file mode 100644
index 000000000000..412ea84836a1
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
@@ -0,0 +1,455 @@
1/*
2 * Copyright (c) 2014-2015 MediaTek Inc.
3 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/regmap.h>
21#include <dt-bindings/pinctrl/mt65xx.h>
22
23#include "pinctrl-mtk-common.h"
24#include "pinctrl-mtk-mt8173.h"
25
26#define DRV_BASE 0xb00
27
28/**
29 * struct mtk_pin_ies_smt_set - For special pins' ies and smt setting.
30 * @start: The start pin number of those special pins.
31 * @end: The end pin number of those special pins.
32 * @offset: The offset of special setting register.
33 * @bit: The bit of special setting register.
34 */
35struct mtk_pin_ies_smt_set {
36 unsigned int start;
37 unsigned int end;
38 unsigned int offset;
39 unsigned char bit;
40};
41
42#define MTK_PIN_IES_SMT_SET(_start, _end, _offset, _bit) \
43 { \
44 .start = _start, \
45 .end = _end, \
46 .bit = _bit, \
47 .offset = _offset, \
48 }
49
50/**
51 * struct mtk_pin_spec_pupd_set - For special pins' pull up/down setting.
52 * @pin: The pin number.
53 * @offset: The offset of special pull up/down setting register.
54 * @pupd_bit: The pull up/down bit in this register.
55 * @r0_bit: The r0 bit of pull resistor.
56 * @r1_bit: The r1 bit of pull resistor.
57 */
58struct mtk_pin_spec_pupd_set {
59 unsigned int pin;
60 unsigned int offset;
61 unsigned char pupd_bit;
62 unsigned char r1_bit;
63 unsigned char r0_bit;
64};
65
66#define MTK_PIN_PUPD_SPEC(_pin, _offset, _pupd, _r1, _r0) \
67 { \
68 .pin = _pin, \
69 .offset = _offset, \
70 .pupd_bit = _pupd, \
71 .r1_bit = _r1, \
72 .r0_bit = _r0, \
73 }
74
75static const struct mtk_pin_spec_pupd_set mt8173_spec_pupd[] = {
76 MTK_PIN_PUPD_SPEC(119, 0xe00, 2, 1, 0), /* KROW0 */
77 MTK_PIN_PUPD_SPEC(120, 0xe00, 6, 5, 4), /* KROW1 */
78 MTK_PIN_PUPD_SPEC(121, 0xe00, 10, 9, 8), /* KROW2 */
79 MTK_PIN_PUPD_SPEC(122, 0xe10, 2, 1, 0), /* KCOL0 */
80 MTK_PIN_PUPD_SPEC(123, 0xe10, 6, 5, 4), /* KCOL1 */
81 MTK_PIN_PUPD_SPEC(124, 0xe10, 10, 9, 8), /* KCOL2 */
82
83 MTK_PIN_PUPD_SPEC(67, 0xd10, 2, 1, 0), /* ms0 DS */
84 MTK_PIN_PUPD_SPEC(68, 0xd00, 2, 1, 0), /* ms0 RST */
85 MTK_PIN_PUPD_SPEC(66, 0xc10, 2, 1, 0), /* ms0 cmd */
86 MTK_PIN_PUPD_SPEC(65, 0xc00, 2, 1, 0), /* ms0 clk */
87 MTK_PIN_PUPD_SPEC(57, 0xc20, 2, 1, 0), /* ms0 data0 */
88 MTK_PIN_PUPD_SPEC(58, 0xc20, 2, 1, 0), /* ms0 data1 */
89 MTK_PIN_PUPD_SPEC(59, 0xc20, 2, 1, 0), /* ms0 data2 */
90 MTK_PIN_PUPD_SPEC(60, 0xc20, 2, 1, 0), /* ms0 data3 */
91 MTK_PIN_PUPD_SPEC(61, 0xc20, 2, 1, 0), /* ms0 data4 */
92 MTK_PIN_PUPD_SPEC(62, 0xc20, 2, 1, 0), /* ms0 data5 */
93 MTK_PIN_PUPD_SPEC(63, 0xc20, 2, 1, 0), /* ms0 data6 */
94 MTK_PIN_PUPD_SPEC(64, 0xc20, 2, 1, 0), /* ms0 data7 */
95
96 MTK_PIN_PUPD_SPEC(78, 0xc50, 2, 1, 0), /* ms1 cmd */
97 MTK_PIN_PUPD_SPEC(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
98 MTK_PIN_PUPD_SPEC(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
99 MTK_PIN_PUPD_SPEC(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
100 MTK_PIN_PUPD_SPEC(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
101 MTK_PIN_PUPD_SPEC(77, 0xc40, 2, 1, 0), /* ms1 clk */
102
103 MTK_PIN_PUPD_SPEC(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
104 MTK_PIN_PUPD_SPEC(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
105 MTK_PIN_PUPD_SPEC(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
106 MTK_PIN_PUPD_SPEC(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
107 MTK_PIN_PUPD_SPEC(104, 0xc80, 2, 1, 0), /* ms2 clk */
108 MTK_PIN_PUPD_SPEC(105, 0xc90, 2, 1, 0), /* ms2 cmd */
109
110 MTK_PIN_PUPD_SPEC(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
111 MTK_PIN_PUPD_SPEC(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
112 MTK_PIN_PUPD_SPEC(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
113 MTK_PIN_PUPD_SPEC(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
114 MTK_PIN_PUPD_SPEC(26, 0xcc0, 2, 1, 0), /* ms3 clk */
115 MTK_PIN_PUPD_SPEC(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
116};
117
118static int spec_pull_set(struct regmap *regmap, unsigned int pin,
119 unsigned char align, bool isup, unsigned int r1r0)
120{
121 unsigned int i;
122 unsigned int reg_pupd, reg_set, reg_rst;
123 unsigned int bit_pupd, bit_r0, bit_r1;
124 const struct mtk_pin_spec_pupd_set *spec_pupd_pin;
125 bool find = false;
126
127 for (i = 0; i < ARRAY_SIZE(mt8173_spec_pupd); i++) {
128 if (pin == mt8173_spec_pupd[i].pin) {
129 find = true;
130 break;
131 }
132 }
133
134 if (!find)
135 return -EINVAL;
136
137 spec_pupd_pin = mt8173_spec_pupd + i;
138 reg_set = spec_pupd_pin->offset + align;
139 reg_rst = spec_pupd_pin->offset + (align << 1);
140
141 if (isup)
142 reg_pupd = reg_rst;
143 else
144 reg_pupd = reg_set;
145
146 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
147 regmap_write(regmap, reg_pupd, bit_pupd);
148
149 bit_r0 = BIT(spec_pupd_pin->r0_bit);
150 bit_r1 = BIT(spec_pupd_pin->r1_bit);
151
152 switch (r1r0) {
153 case MTK_PUPD_SET_R1R0_00:
154 regmap_write(regmap, reg_rst, bit_r0);
155 regmap_write(regmap, reg_rst, bit_r1);
156 break;
157 case MTK_PUPD_SET_R1R0_01:
158 regmap_write(regmap, reg_set, bit_r0);
159 regmap_write(regmap, reg_rst, bit_r1);
160 break;
161 case MTK_PUPD_SET_R1R0_10:
162 regmap_write(regmap, reg_rst, bit_r0);
163 regmap_write(regmap, reg_set, bit_r1);
164 break;
165 case MTK_PUPD_SET_R1R0_11:
166 regmap_write(regmap, reg_set, bit_r0);
167 regmap_write(regmap, reg_set, bit_r1);
168 break;
169 default:
170 return -EINVAL;
171 }
172
173 return 0;
174}
175
176static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = {
177 MTK_PIN_IES_SMT_SET(0, 4, 0x930, 1),
178 MTK_PIN_IES_SMT_SET(5, 9, 0x930, 2),
179 MTK_PIN_IES_SMT_SET(10, 13, 0x930, 10),
180 MTK_PIN_IES_SMT_SET(14, 15, 0x940, 10),
181 MTK_PIN_IES_SMT_SET(16, 16, 0x930, 0),
182 MTK_PIN_IES_SMT_SET(17, 17, 0x950, 2),
183 MTK_PIN_IES_SMT_SET(18, 21, 0x940, 3),
184 MTK_PIN_IES_SMT_SET(29, 32, 0x930, 3),
185 MTK_PIN_IES_SMT_SET(33, 33, 0x930, 4),
186 MTK_PIN_IES_SMT_SET(34, 36, 0x930, 5),
187 MTK_PIN_IES_SMT_SET(37, 38, 0x930, 6),
188 MTK_PIN_IES_SMT_SET(39, 39, 0x930, 7),
189 MTK_PIN_IES_SMT_SET(40, 41, 0x930, 9),
190 MTK_PIN_IES_SMT_SET(42, 42, 0x940, 0),
191 MTK_PIN_IES_SMT_SET(43, 44, 0x930, 11),
192 MTK_PIN_IES_SMT_SET(45, 46, 0x930, 12),
193 MTK_PIN_IES_SMT_SET(57, 64, 0xc20, 13),
194 MTK_PIN_IES_SMT_SET(65, 65, 0xc10, 13),
195 MTK_PIN_IES_SMT_SET(66, 66, 0xc00, 13),
196 MTK_PIN_IES_SMT_SET(67, 67, 0xd10, 13),
197 MTK_PIN_IES_SMT_SET(68, 68, 0xd00, 13),
198 MTK_PIN_IES_SMT_SET(69, 72, 0x940, 14),
199 MTK_PIN_IES_SMT_SET(73, 76, 0xc60, 13),
200 MTK_PIN_IES_SMT_SET(77, 77, 0xc40, 13),
201 MTK_PIN_IES_SMT_SET(78, 78, 0xc50, 13),
202 MTK_PIN_IES_SMT_SET(79, 82, 0x940, 15),
203 MTK_PIN_IES_SMT_SET(83, 83, 0x950, 0),
204 MTK_PIN_IES_SMT_SET(84, 85, 0x950, 1),
205 MTK_PIN_IES_SMT_SET(86, 91, 0x950, 2),
206 MTK_PIN_IES_SMT_SET(92, 92, 0x930, 13),
207 MTK_PIN_IES_SMT_SET(93, 95, 0x930, 14),
208 MTK_PIN_IES_SMT_SET(96, 99, 0x930, 15),
209 MTK_PIN_IES_SMT_SET(100, 103, 0xca0, 13),
210 MTK_PIN_IES_SMT_SET(104, 104, 0xc80, 13),
211 MTK_PIN_IES_SMT_SET(105, 105, 0xc90, 13),
212 MTK_PIN_IES_SMT_SET(106, 107, 0x940, 4),
213 MTK_PIN_IES_SMT_SET(108, 112, 0x940, 1),
214 MTK_PIN_IES_SMT_SET(113, 116, 0x940, 2),
215 MTK_PIN_IES_SMT_SET(117, 118, 0x940, 5),
216 MTK_PIN_IES_SMT_SET(119, 124, 0x940, 6),
217 MTK_PIN_IES_SMT_SET(125, 126, 0x940, 7),
218 MTK_PIN_IES_SMT_SET(127, 127, 0x940, 0),
219 MTK_PIN_IES_SMT_SET(128, 128, 0x950, 8),
220 MTK_PIN_IES_SMT_SET(129, 130, 0x950, 9),
221 MTK_PIN_IES_SMT_SET(131, 132, 0x950, 8),
222 MTK_PIN_IES_SMT_SET(133, 134, 0x910, 8)
223};
224
225static int spec_ies_smt_set(struct regmap *regmap, unsigned int pin,
226 unsigned char align, int value)
227{
228 unsigned int i, reg_addr, bit;
229 bool find = false;
230
231 for (i = 0; i < ARRAY_SIZE(mt8173_ies_smt_set); i++) {
232 if (pin >= mt8173_ies_smt_set[i].start &&
233 pin <= mt8173_ies_smt_set[i].end) {
234 find = true;
235 break;
236 }
237 }
238
239 if (!find)
240 return -EINVAL;
241
242 if (value)
243 reg_addr = mt8173_ies_smt_set[i].offset + align;
244 else
245 reg_addr = mt8173_ies_smt_set[i].offset + (align << 1);
246
247 bit = BIT(mt8173_ies_smt_set[i].bit);
248 regmap_write(regmap, reg_addr, bit);
249 return 0;
250}
251
252static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
253 /* 0E4E8SR 4/8/12/16 */
254 MTK_DRV_GRP(4, 16, 1, 2, 4),
255 /* 0E2E4SR 2/4/6/8 */
256 MTK_DRV_GRP(2, 8, 1, 2, 2),
257 /* E8E4E2 2/4/6/8/10/12/14/16 */
258 MTK_DRV_GRP(2, 16, 0, 2, 2)
259};
260
261static const struct mtk_pin_drv_grp mt8173_pin_drv[] = {
262 MTK_PIN_DRV_GRP(0, DRV_BASE+0x20, 12, 0),
263 MTK_PIN_DRV_GRP(1, DRV_BASE+0x20, 12, 0),
264 MTK_PIN_DRV_GRP(2, DRV_BASE+0x20, 12, 0),
265 MTK_PIN_DRV_GRP(3, DRV_BASE+0x20, 12, 0),
266 MTK_PIN_DRV_GRP(4, DRV_BASE+0x20, 12, 0),
267 MTK_PIN_DRV_GRP(5, DRV_BASE+0x30, 0, 0),
268 MTK_PIN_DRV_GRP(6, DRV_BASE+0x30, 0, 0),
269 MTK_PIN_DRV_GRP(7, DRV_BASE+0x30, 0, 0),
270 MTK_PIN_DRV_GRP(8, DRV_BASE+0x30, 0, 0),
271 MTK_PIN_DRV_GRP(9, DRV_BASE+0x30, 0, 0),
272 MTK_PIN_DRV_GRP(10, DRV_BASE+0x30, 4, 1),
273 MTK_PIN_DRV_GRP(11, DRV_BASE+0x30, 4, 1),
274 MTK_PIN_DRV_GRP(12, DRV_BASE+0x30, 4, 1),
275 MTK_PIN_DRV_GRP(13, DRV_BASE+0x30, 4, 1),
276 MTK_PIN_DRV_GRP(14, DRV_BASE+0x40, 8, 1),
277 MTK_PIN_DRV_GRP(15, DRV_BASE+0x40, 8, 1),
278 MTK_PIN_DRV_GRP(16, DRV_BASE, 8, 1),
279 MTK_PIN_DRV_GRP(17, 0xce0, 8, 2),
280 MTK_PIN_DRV_GRP(22, 0xce0, 8, 2),
281 MTK_PIN_DRV_GRP(23, 0xce0, 8, 2),
282 MTK_PIN_DRV_GRP(24, 0xce0, 8, 2),
283 MTK_PIN_DRV_GRP(25, 0xce0, 8, 2),
284 MTK_PIN_DRV_GRP(26, 0xcc0, 8, 2),
285 MTK_PIN_DRV_GRP(27, 0xcd0, 8, 2),
286 MTK_PIN_DRV_GRP(28, 0xd70, 8, 2),
287 MTK_PIN_DRV_GRP(29, DRV_BASE+0x80, 12, 1),
288 MTK_PIN_DRV_GRP(30, DRV_BASE+0x80, 12, 1),
289 MTK_PIN_DRV_GRP(31, DRV_BASE+0x80, 12, 1),
290 MTK_PIN_DRV_GRP(32, DRV_BASE+0x80, 12, 1),
291 MTK_PIN_DRV_GRP(33, DRV_BASE+0x10, 12, 1),
292 MTK_PIN_DRV_GRP(34, DRV_BASE+0x10, 8, 1),
293 MTK_PIN_DRV_GRP(35, DRV_BASE+0x10, 8, 1),
294 MTK_PIN_DRV_GRP(36, DRV_BASE+0x10, 8, 1),
295 MTK_PIN_DRV_GRP(37, DRV_BASE+0x10, 4, 1),
296 MTK_PIN_DRV_GRP(38, DRV_BASE+0x10, 4, 1),
297 MTK_PIN_DRV_GRP(39, DRV_BASE+0x20, 0, 0),
298 MTK_PIN_DRV_GRP(40, DRV_BASE+0x20, 8, 0),
299 MTK_PIN_DRV_GRP(41, DRV_BASE+0x20, 8, 0),
300 MTK_PIN_DRV_GRP(42, DRV_BASE+0x50, 8, 1),
301 MTK_PIN_DRV_GRP(57, 0xc20, 8, 2),
302 MTK_PIN_DRV_GRP(58, 0xc20, 8, 2),
303 MTK_PIN_DRV_GRP(59, 0xc20, 8, 2),
304 MTK_PIN_DRV_GRP(60, 0xc20, 8, 2),
305 MTK_PIN_DRV_GRP(61, 0xc20, 8, 2),
306 MTK_PIN_DRV_GRP(62, 0xc20, 8, 2),
307 MTK_PIN_DRV_GRP(63, 0xc20, 8, 2),
308 MTK_PIN_DRV_GRP(64, 0xc20, 8, 2),
309 MTK_PIN_DRV_GRP(65, 0xc00, 8, 2),
310 MTK_PIN_DRV_GRP(66, 0xc10, 8, 2),
311 MTK_PIN_DRV_GRP(67, 0xd10, 8, 2),
312 MTK_PIN_DRV_GRP(68, 0xd00, 8, 2),
313 MTK_PIN_DRV_GRP(69, DRV_BASE+0x80, 0, 1),
314 MTK_PIN_DRV_GRP(70, DRV_BASE+0x80, 0, 1),
315 MTK_PIN_DRV_GRP(71, DRV_BASE+0x80, 0, 1),
316 MTK_PIN_DRV_GRP(72, DRV_BASE+0x80, 0, 1),
317 MTK_PIN_DRV_GRP(73, 0xc60, 8, 2),
318 MTK_PIN_DRV_GRP(74, 0xc60, 8, 2),
319 MTK_PIN_DRV_GRP(75, 0xc60, 8, 2),
320 MTK_PIN_DRV_GRP(76, 0xc60, 8, 2),
321 MTK_PIN_DRV_GRP(77, 0xc40, 8, 2),
322 MTK_PIN_DRV_GRP(78, 0xc50, 8, 2),
323 MTK_PIN_DRV_GRP(79, DRV_BASE+0x70, 12, 1),
324 MTK_PIN_DRV_GRP(80, DRV_BASE+0x70, 12, 1),
325 MTK_PIN_DRV_GRP(81, DRV_BASE+0x70, 12, 1),
326 MTK_PIN_DRV_GRP(82, DRV_BASE+0x70, 12, 1),
327 MTK_PIN_DRV_GRP(83, DRV_BASE, 4, 1),
328 MTK_PIN_DRV_GRP(84, DRV_BASE, 0, 1),
329 MTK_PIN_DRV_GRP(85, DRV_BASE, 0, 1),
330 MTK_PIN_DRV_GRP(85, DRV_BASE+0x60, 8, 1),
331 MTK_PIN_DRV_GRP(86, DRV_BASE+0x60, 8, 1),
332 MTK_PIN_DRV_GRP(87, DRV_BASE+0x60, 8, 1),
333 MTK_PIN_DRV_GRP(88, DRV_BASE+0x60, 8, 1),
334 MTK_PIN_DRV_GRP(89, DRV_BASE+0x60, 8, 1),
335 MTK_PIN_DRV_GRP(90, DRV_BASE+0x60, 8, 1),
336 MTK_PIN_DRV_GRP(91, DRV_BASE+0x60, 8, 1),
337 MTK_PIN_DRV_GRP(92, DRV_BASE+0x60, 4, 0),
338 MTK_PIN_DRV_GRP(93, DRV_BASE+0x60, 0, 0),
339 MTK_PIN_DRV_GRP(94, DRV_BASE+0x60, 0, 0),
340 MTK_PIN_DRV_GRP(95, DRV_BASE+0x60, 0, 0),
341 MTK_PIN_DRV_GRP(96, DRV_BASE+0x80, 8, 1),
342 MTK_PIN_DRV_GRP(97, DRV_BASE+0x80, 8, 1),
343 MTK_PIN_DRV_GRP(98, DRV_BASE+0x80, 8, 1),
344 MTK_PIN_DRV_GRP(99, DRV_BASE+0x80, 8, 1),
345 MTK_PIN_DRV_GRP(100, 0xca0, 8, 2),
346 MTK_PIN_DRV_GRP(101, 0xca0, 8, 2),
347 MTK_PIN_DRV_GRP(102, 0xca0, 8, 2),
348 MTK_PIN_DRV_GRP(103, 0xca0, 8, 2),
349 MTK_PIN_DRV_GRP(104, 0xc80, 8, 2),
350 MTK_PIN_DRV_GRP(105, 0xc90, 8, 2),
351 MTK_PIN_DRV_GRP(108, DRV_BASE+0x50, 0, 1),
352 MTK_PIN_DRV_GRP(109, DRV_BASE+0x50, 0, 1),
353 MTK_PIN_DRV_GRP(110, DRV_BASE+0x50, 0, 1),
354 MTK_PIN_DRV_GRP(111, DRV_BASE+0x50, 0, 1),
355 MTK_PIN_DRV_GRP(112, DRV_BASE+0x50, 0, 1),
356 MTK_PIN_DRV_GRP(113, DRV_BASE+0x80, 4, 1),
357 MTK_PIN_DRV_GRP(114, DRV_BASE+0x80, 4, 1),
358 MTK_PIN_DRV_GRP(115, DRV_BASE+0x80, 4, 1),
359 MTK_PIN_DRV_GRP(116, DRV_BASE+0x80, 4, 1),
360 MTK_PIN_DRV_GRP(117, DRV_BASE+0x90, 0, 1),
361 MTK_PIN_DRV_GRP(118, DRV_BASE+0x90, 0, 1),
362 MTK_PIN_DRV_GRP(119, DRV_BASE+0x50, 4, 1),
363 MTK_PIN_DRV_GRP(120, DRV_BASE+0x50, 4, 1),
364 MTK_PIN_DRV_GRP(121, DRV_BASE+0x50, 4, 1),
365 MTK_PIN_DRV_GRP(122, DRV_BASE+0x50, 4, 1),
366 MTK_PIN_DRV_GRP(123, DRV_BASE+0x50, 4, 1),
367 MTK_PIN_DRV_GRP(124, DRV_BASE+0x50, 4, 1),
368 MTK_PIN_DRV_GRP(125, DRV_BASE+0x30, 12, 1),
369 MTK_PIN_DRV_GRP(126, DRV_BASE+0x30, 12, 1),
370 MTK_PIN_DRV_GRP(127, DRV_BASE+0x50, 8, 1),
371 MTK_PIN_DRV_GRP(128, DRV_BASE+0x40, 0, 1),
372 MTK_PIN_DRV_GRP(129, DRV_BASE+0x40, 0, 1),
373 MTK_PIN_DRV_GRP(130, DRV_BASE+0x40, 0, 1),
374 MTK_PIN_DRV_GRP(131, DRV_BASE+0x40, 0, 1),
375 MTK_PIN_DRV_GRP(132, DRV_BASE+0x40, 0, 1)
376};
377
378static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
379 .pins = mtk_pins_mt8173,
380 .npins = ARRAY_SIZE(mtk_pins_mt8173),
381 .grp_desc = mt8173_drv_grp,
382 .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
383 .pin_drv_grp = mt8173_pin_drv,
384 .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
385 .spec_pull_set = spec_pull_set,
386 .spec_ies_smt_set = spec_ies_smt_set,
387 .dir_offset = 0x0000,
388 .pullen_offset = 0x0100,
389 .pullsel_offset = 0x0200,
390 .dout_offset = 0x0400,
391 .din_offset = 0x0500,
392 .pinmux_offset = 0x0600,
393 .type1_start = 135,
394 .type1_end = 135,
395 .port_shf = 4,
396 .port_mask = 0xf,
397 .port_align = 4,
398 .eint_offsets = {
399 .name = "mt8173_eint",
400 .stat = 0x000,
401 .ack = 0x040,
402 .mask = 0x080,
403 .mask_set = 0x0c0,
404 .mask_clr = 0x100,
405 .sens = 0x140,
406 .sens_set = 0x180,
407 .sens_clr = 0x1c0,
408 .soft = 0x200,
409 .soft_set = 0x240,
410 .soft_clr = 0x280,
411 .pol = 0x300,
412 .pol_set = 0x340,
413 .pol_clr = 0x380,
414 .dom_en = 0x400,
415 .dbnc_ctrl = 0x500,
416 .dbnc_set = 0x600,
417 .dbnc_clr = 0x700,
418 .port_mask = 7,
419 .ports = 6,
420 },
421 .ap_num = 224,
422 .db_cnt = 16,
423};
424
425static int mt8173_pinctrl_probe(struct platform_device *pdev)
426{
427 return mtk_pctrl_init(pdev, &mt8173_pinctrl_data);
428}
429
430static const struct of_device_id mt8173_pctrl_match[] = {
431 {
432 .compatible = "mediatek,mt8173-pinctrl",
433 },
434 { }
435};
436MODULE_DEVICE_TABLE(of, mt8173_pctrl_match);
437
438static struct platform_driver mtk_pinctrl_driver = {
439 .probe = mt8173_pinctrl_probe,
440 .driver = {
441 .name = "mediatek-mt8173-pinctrl",
442 .of_match_table = mt8173_pctrl_match,
443 },
444};
445
446static int __init mtk_pinctrl_init(void)
447{
448 return platform_driver_register(&mtk_pinctrl_driver);
449}
450
451module_init(mtk_pinctrl_init);
452
453MODULE_LICENSE("GPL v2");
454MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
455MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
new file mode 100644
index 000000000000..493294c0ebe6
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -0,0 +1,1257 @@
1/*
2 * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
3 * Copyright (c) 2014 MediaTek Inc.
4 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_device.h>
22#include <linux/of_irq.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/pinctrl/machine.h>
25#include <linux/pinctrl/pinconf.h>
26#include <linux/pinctrl/pinconf-generic.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include <linux/bitops.h>
32#include <linux/regmap.h>
33#include <linux/mfd/syscon.h>
34#include <linux/delay.h>
35#include <linux/interrupt.h>
36#include <dt-bindings/pinctrl/mt65xx.h>
37
38#include "../core.h"
39#include "../pinconf.h"
40#include "../pinctrl-utils.h"
41#include "pinctrl-mtk-common.h"
42
43#define MAX_GPIO_MODE_PER_REG 5
44#define GPIO_MODE_BITS 3
45
46static const char * const mtk_gpio_functions[] = {
47 "func0", "func1", "func2", "func3",
48 "func4", "func5", "func6", "func7",
49};
50
51/*
52 * There are two base address for pull related configuration
53 * in mt8135, and different GPIO pins use different base address.
54 * When pin number greater than type1_start and less than type1_end,
55 * should use the second base address.
56 */
57static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
58 unsigned long pin)
59{
60 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
61 return pctl->regmap2;
62 return pctl->regmap1;
63}
64
65static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
66{
67 /* Different SoC has different mask and port shift. */
68 return ((pin >> 4) & pctl->devdata->port_mask)
69 << pctl->devdata->port_shf;
70}
71
72static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
73 struct pinctrl_gpio_range *range, unsigned offset,
74 bool input)
75{
76 unsigned int reg_addr;
77 unsigned int bit;
78 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
79
80 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
81 bit = BIT(offset & 0xf);
82
83 if (input)
84 /* Different SoC has different alignment offset. */
85 reg_addr = CLR_ADDR(reg_addr, pctl);
86 else
87 reg_addr = SET_ADDR(reg_addr, pctl);
88
89 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
90 return 0;
91}
92
93static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
94{
95 unsigned int reg_addr;
96 unsigned int bit;
97 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
98
99 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
100 bit = BIT(offset & 0xf);
101
102 if (value)
103 reg_addr = SET_ADDR(reg_addr, pctl);
104 else
105 reg_addr = CLR_ADDR(reg_addr, pctl);
106
107 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
108}
109
110static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
111 int value, enum pin_config_param param)
112{
113 unsigned int reg_addr, offset;
114 unsigned int bit;
115 int ret;
116
117 /*
118 * Due to some pins are irregular, their input enable and smt
119 * control register are discontinuous, but they are mapping together.
120 * So we need this special handle.
121 */
122 if (pctl->devdata->spec_ies_smt_set) {
123 ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
124 pin, pctl->devdata->port_align, value);
125 if (!ret)
126 return;
127 }
128
129 bit = BIT(pin & 0xf);
130
131 if (param == PIN_CONFIG_INPUT_ENABLE)
132 offset = pctl->devdata->ies_offset;
133 else
134 offset = pctl->devdata->smt_offset;
135
136 if (value)
137 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
138 else
139 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
140
141 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
142}
143
144static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
145 struct mtk_pinctrl *pctl, unsigned long pin) {
146 int i;
147
148 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
149 const struct mtk_pin_drv_grp *pin_drv =
150 pctl->devdata->pin_drv_grp + i;
151 if (pin == pin_drv->pin)
152 return pin_drv;
153 }
154
155 return NULL;
156}
157
158static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
159 unsigned int pin, unsigned char driving)
160{
161 const struct mtk_pin_drv_grp *pin_drv;
162 unsigned int val;
163 unsigned int bits, mask, shift;
164 const struct mtk_drv_group_desc *drv_grp;
165
166 if (pin >= pctl->devdata->npins)
167 return -EINVAL;
168
169 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
170 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
171 return -EINVAL;
172
173 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
174 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
175 && !(driving % drv_grp->step)) {
176 val = driving / drv_grp->step - 1;
177 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
178 mask = BIT(bits) - 1;
179 shift = pin_drv->bit + drv_grp->low_bit;
180 mask <<= shift;
181 val <<= shift;
182 return regmap_update_bits(mtk_get_regmap(pctl, pin),
183 pin_drv->offset, mask, val);
184 }
185
186 return -EINVAL;
187}
188
189static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
190 unsigned int pin, bool enable, bool isup, unsigned int arg)
191{
192 unsigned int bit;
193 unsigned int reg_pullen, reg_pullsel;
194 int ret;
195
196 /* Some pins' pull setting are very different,
197 * they have separate pull up/down bit, R0 and R1
198 * resistor bit, so we need this special handle.
199 */
200 if (pctl->devdata->spec_pull_set) {
201 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
202 pin, pctl->devdata->port_align, isup, arg);
203 if (!ret)
204 return 0;
205 }
206
207 /* For generic pull config, default arg value should be 0 or 1. */
208 if (arg != 0 && arg != 1) {
209 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
210 arg, pin);
211 return -EINVAL;
212 }
213
214 bit = BIT(pin & 0xf);
215 if (enable)
216 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
217 pctl->devdata->pullen_offset, pctl);
218 else
219 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
220 pctl->devdata->pullen_offset, pctl);
221
222 if (isup)
223 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
224 pctl->devdata->pullsel_offset, pctl);
225 else
226 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
227 pctl->devdata->pullsel_offset, pctl);
228
229 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
230 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
231 return 0;
232}
233
234static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
235 unsigned int pin, enum pin_config_param param,
236 enum pin_config_param arg)
237{
238 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
239
240 switch (param) {
241 case PIN_CONFIG_BIAS_DISABLE:
242 mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
243 break;
244 case PIN_CONFIG_BIAS_PULL_UP:
245 mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
246 break;
247 case PIN_CONFIG_BIAS_PULL_DOWN:
248 mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
249 break;
250 case PIN_CONFIG_INPUT_ENABLE:
251 mtk_pconf_set_ies_smt(pctl, pin, arg, param);
252 break;
253 case PIN_CONFIG_OUTPUT:
254 mtk_gpio_set(pctl->chip, pin, arg);
255 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
256 break;
257 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
258 mtk_pconf_set_ies_smt(pctl, pin, arg, param);
259 break;
260 case PIN_CONFIG_DRIVE_STRENGTH:
261 mtk_pconf_set_driving(pctl, pin, arg);
262 break;
263 default:
264 return -EINVAL;
265 }
266
267 return 0;
268}
269
270static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
271 unsigned group,
272 unsigned long *config)
273{
274 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
275
276 *config = pctl->groups[group].config;
277
278 return 0;
279}
280
281static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
282 unsigned long *configs, unsigned num_configs)
283{
284 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
285 struct mtk_pinctrl_group *g = &pctl->groups[group];
286 int i;
287
288 for (i = 0; i < num_configs; i++) {
289 mtk_pconf_parse_conf(pctldev, g->pin,
290 pinconf_to_config_param(configs[i]),
291 pinconf_to_config_argument(configs[i]));
292
293 g->config = configs[i];
294 }
295
296 return 0;
297}
298
299static const struct pinconf_ops mtk_pconf_ops = {
300 .pin_config_group_get = mtk_pconf_group_get,
301 .pin_config_group_set = mtk_pconf_group_set,
302};
303
304static struct mtk_pinctrl_group *
305mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
306{
307 int i;
308
309 for (i = 0; i < pctl->ngroups; i++) {
310 struct mtk_pinctrl_group *grp = pctl->groups + i;
311
312 if (grp->pin == pin)
313 return grp;
314 }
315
316 return NULL;
317}
318
319static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
320 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
321{
322 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
323 const struct mtk_desc_function *func = pin->functions;
324
325 while (func && func->name) {
326 if (func->muxval == fnum)
327 return func;
328 func++;
329 }
330
331 return NULL;
332}
333
334static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
335 u32 pin_num, u32 fnum)
336{
337 int i;
338
339 for (i = 0; i < pctl->devdata->npins; i++) {
340 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
341
342 if (pin->pin.number == pin_num) {
343 const struct mtk_desc_function *func =
344 pin->functions;
345
346 while (func && func->name) {
347 if (func->muxval == fnum)
348 return true;
349 func++;
350 }
351
352 break;
353 }
354 }
355
356 return false;
357}
358
359static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
360 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
361 struct pinctrl_map **map, unsigned *reserved_maps,
362 unsigned *num_maps)
363{
364 bool ret;
365
366 if (*num_maps == *reserved_maps)
367 return -ENOSPC;
368
369 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
370 (*map)[*num_maps].data.mux.group = grp->name;
371
372 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
373 if (!ret) {
374 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
375 fnum, pin);
376 return -EINVAL;
377 }
378
379 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
380 (*num_maps)++;
381
382 return 0;
383}
384
385static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
386 struct device_node *node,
387 struct pinctrl_map **map,
388 unsigned *reserved_maps,
389 unsigned *num_maps)
390{
391 struct property *pins;
392 u32 pinfunc, pin, func;
393 int num_pins, num_funcs, maps_per_pin;
394 unsigned long *configs;
395 unsigned int num_configs;
396 bool has_config = 0;
397 int i, err;
398 unsigned reserve = 0;
399 struct mtk_pinctrl_group *grp;
400 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
401
402 pins = of_find_property(node, "pinmux", NULL);
403 if (!pins) {
404 dev_err(pctl->dev, "missing pins property in node %s .\n",
405 node->name);
406 return -EINVAL;
407 }
408
409 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
410 &num_configs);
411 if (num_configs)
412 has_config = 1;
413
414 num_pins = pins->length / sizeof(u32);
415 num_funcs = num_pins;
416 maps_per_pin = 0;
417 if (num_funcs)
418 maps_per_pin++;
419 if (has_config && num_pins >= 1)
420 maps_per_pin++;
421
422 if (!num_pins || !maps_per_pin)
423 return -EINVAL;
424
425 reserve = num_pins * maps_per_pin;
426
427 err = pinctrl_utils_reserve_map(pctldev, map,
428 reserved_maps, num_maps, reserve);
429 if (err < 0)
430 goto fail;
431
432 for (i = 0; i < num_pins; i++) {
433 err = of_property_read_u32_index(node, "pinmux",
434 i, &pinfunc);
435 if (err)
436 goto fail;
437
438 pin = MTK_GET_PIN_NO(pinfunc);
439 func = MTK_GET_PIN_FUNC(pinfunc);
440
441 if (pin >= pctl->devdata->npins ||
442 func >= ARRAY_SIZE(mtk_gpio_functions)) {
443 dev_err(pctl->dev, "invalid pins value.\n");
444 err = -EINVAL;
445 goto fail;
446 }
447
448 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
449 if (!grp) {
450 dev_err(pctl->dev, "unable to match pin %d to group\n",
451 pin);
452 return -EINVAL;
453 }
454
455 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
456 reserved_maps, num_maps);
457 if (err < 0)
458 goto fail;
459
460 if (has_config) {
461 err = pinctrl_utils_add_map_configs(pctldev, map,
462 reserved_maps, num_maps, grp->name,
463 configs, num_configs,
464 PIN_MAP_TYPE_CONFIGS_GROUP);
465 if (err < 0)
466 goto fail;
467 }
468 }
469
470 return 0;
471
472fail:
473 return err;
474}
475
476static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
477 struct device_node *np_config,
478 struct pinctrl_map **map, unsigned *num_maps)
479{
480 struct device_node *np;
481 unsigned reserved_maps;
482 int ret;
483
484 *map = NULL;
485 *num_maps = 0;
486 reserved_maps = 0;
487
488 for_each_child_of_node(np_config, np) {
489 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
490 &reserved_maps, num_maps);
491 if (ret < 0) {
492 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
493 return ret;
494 }
495 }
496
497 return 0;
498}
499
500static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
501{
502 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
503
504 return pctl->ngroups;
505}
506
507static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
508 unsigned group)
509{
510 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
511
512 return pctl->groups[group].name;
513}
514
515static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
516 unsigned group,
517 const unsigned **pins,
518 unsigned *num_pins)
519{
520 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
521
522 *pins = (unsigned *)&pctl->groups[group].pin;
523 *num_pins = 1;
524
525 return 0;
526}
527
528static const struct pinctrl_ops mtk_pctrl_ops = {
529 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
530 .dt_free_map = pinctrl_utils_dt_free_map,
531 .get_groups_count = mtk_pctrl_get_groups_count,
532 .get_group_name = mtk_pctrl_get_group_name,
533 .get_group_pins = mtk_pctrl_get_group_pins,
534};
535
536static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
537{
538 return ARRAY_SIZE(mtk_gpio_functions);
539}
540
541static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
542 unsigned selector)
543{
544 return mtk_gpio_functions[selector];
545}
546
547static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
548 unsigned function,
549 const char * const **groups,
550 unsigned * const num_groups)
551{
552 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
553
554 *groups = pctl->grp_names;
555 *num_groups = pctl->ngroups;
556
557 return 0;
558}
559
560static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
561 unsigned long pin, unsigned long mode)
562{
563 unsigned int reg_addr;
564 unsigned char bit;
565 unsigned int val;
566 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
567 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
568
569 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
570 + pctl->devdata->pinmux_offset;
571
572 bit = pin % MAX_GPIO_MODE_PER_REG;
573 mask <<= (GPIO_MODE_BITS * bit);
574 val = (mode << (GPIO_MODE_BITS * bit));
575 return regmap_update_bits(mtk_get_regmap(pctl, pin),
576 reg_addr, mask, val);
577}
578
579static const struct mtk_desc_pin *
580mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
581{
582 int i;
583 const struct mtk_desc_pin *pin;
584
585 for (i = 0; i < pctl->devdata->npins; i++) {
586 pin = pctl->devdata->pins + i;
587 if (pin->eint.eintnum == eint_num)
588 return pin;
589 }
590
591 return NULL;
592}
593
594static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
595 unsigned function,
596 unsigned group)
597{
598 bool ret;
599 const struct mtk_desc_function *desc;
600 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
601 struct mtk_pinctrl_group *g = pctl->groups + group;
602
603 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
604 if (!ret) {
605 dev_err(pctl->dev, "invaild function %d on group %d .\n",
606 function, group);
607 return -EINVAL;
608 }
609
610 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
611 if (!desc)
612 return -EINVAL;
613 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
614 return 0;
615}
616
617static const struct pinmux_ops mtk_pmx_ops = {
618 .get_functions_count = mtk_pmx_get_funcs_cnt,
619 .get_function_name = mtk_pmx_get_func_name,
620 .get_function_groups = mtk_pmx_get_func_groups,
621 .set_mux = mtk_pmx_set_mux,
622 .gpio_set_direction = mtk_pmx_gpio_set_direction,
623};
624
625static int mtk_gpio_request(struct gpio_chip *chip, unsigned offset)
626{
627 return pinctrl_request_gpio(chip->base + offset);
628}
629
630static void mtk_gpio_free(struct gpio_chip *chip, unsigned offset)
631{
632 pinctrl_free_gpio(chip->base + offset);
633}
634
635static int mtk_gpio_direction_input(struct gpio_chip *chip,
636 unsigned offset)
637{
638 return pinctrl_gpio_direction_input(chip->base + offset);
639}
640
641static int mtk_gpio_direction_output(struct gpio_chip *chip,
642 unsigned offset, int value)
643{
644 mtk_gpio_set(chip, offset, value);
645 return pinctrl_gpio_direction_output(chip->base + offset);
646}
647
648static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
649{
650 unsigned int reg_addr;
651 unsigned int bit;
652 unsigned int read_val = 0;
653
654 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
655
656 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
657 bit = BIT(offset & 0xf);
658 regmap_read(pctl->regmap1, reg_addr, &read_val);
659 return !!(read_val & bit);
660}
661
662static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
663{
664 unsigned int reg_addr;
665 unsigned int bit;
666 unsigned int read_val = 0;
667 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
668
669 if (mtk_gpio_get_direction(chip, offset))
670 reg_addr = mtk_get_port(pctl, offset) +
671 pctl->devdata->dout_offset;
672 else
673 reg_addr = mtk_get_port(pctl, offset) +
674 pctl->devdata->din_offset;
675
676 bit = BIT(offset & 0xf);
677 regmap_read(pctl->regmap1, reg_addr, &read_val);
678 return !!(read_val & bit);
679}
680
681static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
682{
683 const struct mtk_desc_pin *pin;
684 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
685 int irq;
686
687 pin = pctl->devdata->pins + offset;
688 if (pin->eint.eintnum == NO_EINT_SUPPORT)
689 return -EINVAL;
690
691 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
692 if (!irq)
693 return -EINVAL;
694
695 return irq;
696}
697
698static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
699{
700 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
701 const struct mtk_desc_pin *pin;
702 int ret;
703
704 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
705
706 if (!pin) {
707 dev_err(pctl->dev, "Can not find pin\n");
708 return -EINVAL;
709 }
710
711 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
712 if (ret) {
713 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
714 irqd_to_hwirq(d));
715 return ret;
716 }
717
718 /* set mux to INT mode */
719 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
720
721 return 0;
722}
723
724static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
725{
726 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
727 const struct mtk_desc_pin *pin;
728
729 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
730
731 if (!pin) {
732 dev_err(pctl->dev, "Can not find pin\n");
733 return;
734 }
735
736 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
737}
738
739static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
740 unsigned int eint_num, unsigned int offset)
741{
742 unsigned int eint_base = 0;
743 void __iomem *reg;
744
745 if (eint_num >= pctl->devdata->ap_num)
746 eint_base = pctl->devdata->ap_num;
747
748 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
749
750 return reg;
751}
752
753/*
754 * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
755 * @eint_num: the EINT number to setmtk_pinctrl
756 */
757static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
758 unsigned int eint_num)
759{
760 unsigned int sens;
761 unsigned int bit = BIT(eint_num % 32);
762 const struct mtk_eint_offsets *eint_offsets =
763 &pctl->devdata->eint_offsets;
764
765 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
766 eint_offsets->sens);
767
768 if (readl(reg) & bit)
769 sens = MT_LEVEL_SENSITIVE;
770 else
771 sens = MT_EDGE_SENSITIVE;
772
773 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
774 return 1;
775 else
776 return 0;
777}
778
779/*
780 * mtk_eint_get_mask: To get the eint mask
781 * @eint_num: the EINT number to get
782 */
783static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
784 unsigned int eint_num)
785{
786 unsigned int bit = BIT(eint_num % 32);
787 const struct mtk_eint_offsets *eint_offsets =
788 &pctl->devdata->eint_offsets;
789
790 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
791 eint_offsets->mask);
792
793 return !!(readl(reg) & bit);
794}
795
796static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
797{
798 int start_level, curr_level;
799 unsigned int reg_offset;
800 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
801 u32 mask = 1 << (hwirq & 0x1f);
802 u32 port = (hwirq >> 5) & eint_offsets->port_mask;
803 void __iomem *reg = pctl->eint_reg_base + (port << 2);
804 const struct mtk_desc_pin *pin;
805
806 pin = mtk_find_pin_by_eint_num(pctl, hwirq);
807 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
808 do {
809 start_level = curr_level;
810 if (start_level)
811 reg_offset = eint_offsets->pol_clr;
812 else
813 reg_offset = eint_offsets->pol_set;
814 writel(mask, reg + reg_offset);
815
816 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
817 } while (start_level != curr_level);
818
819 return start_level;
820}
821
822static void mtk_eint_mask(struct irq_data *d)
823{
824 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
825 const struct mtk_eint_offsets *eint_offsets =
826 &pctl->devdata->eint_offsets;
827 u32 mask = BIT(d->hwirq & 0x1f);
828 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
829 eint_offsets->mask_set);
830
831 writel(mask, reg);
832}
833
834static void mtk_eint_unmask(struct irq_data *d)
835{
836 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
837 const struct mtk_eint_offsets *eint_offsets =
838 &pctl->devdata->eint_offsets;
839 u32 mask = BIT(d->hwirq & 0x1f);
840 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
841 eint_offsets->mask_clr);
842
843 writel(mask, reg);
844
845 if (pctl->eint_dual_edges[d->hwirq])
846 mtk_eint_flip_edge(pctl, d->hwirq);
847}
848
849static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
850 unsigned debounce)
851{
852 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
853 int eint_num, virq, eint_offset;
854 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
855 static const unsigned int dbnc_arr[] = {0 , 1, 16, 32, 64, 128, 256};
856 const struct mtk_desc_pin *pin;
857 struct irq_data *d;
858
859 pin = pctl->devdata->pins + offset;
860 if (pin->eint.eintnum == NO_EINT_SUPPORT)
861 return -EINVAL;
862
863 eint_num = pin->eint.eintnum;
864 virq = irq_find_mapping(pctl->domain, eint_num);
865 eint_offset = (eint_num % 4) * 8;
866 d = irq_get_irq_data(virq);
867
868 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
869 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
870 if (!mtk_eint_can_en_debounce(pctl, eint_num))
871 return -ENOSYS;
872
873 dbnc = ARRAY_SIZE(dbnc_arr);
874 for (i = 0; i < ARRAY_SIZE(dbnc_arr); i++) {
875 if (debounce <= dbnc_arr[i]) {
876 dbnc = i;
877 break;
878 }
879 }
880
881 if (!mtk_eint_get_mask(pctl, eint_num)) {
882 mtk_eint_mask(d);
883 unmask = 1;
884 }
885
886 clr_bit = 0xff << eint_offset;
887 writel(clr_bit, pctl->eint_reg_base + clr_offset);
888
889 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
890 eint_offset;
891 rst = EINT_DBNC_RST_BIT << eint_offset;
892 writel(rst | bit, pctl->eint_reg_base + set_offset);
893
894 /* Delay a while (more than 2T) to wait for hw debounce counter reset
895 work correctly */
896 udelay(1);
897 if (unmask == 1)
898 mtk_eint_unmask(d);
899
900 return 0;
901}
902
903static struct gpio_chip mtk_gpio_chip = {
904 .owner = THIS_MODULE,
905 .request = mtk_gpio_request,
906 .free = mtk_gpio_free,
907 .direction_input = mtk_gpio_direction_input,
908 .direction_output = mtk_gpio_direction_output,
909 .get = mtk_gpio_get,
910 .set = mtk_gpio_set,
911 .to_irq = mtk_gpio_to_irq,
912 .set_debounce = mtk_gpio_set_debounce,
913 .of_gpio_n_cells = 2,
914};
915
916static int mtk_eint_set_type(struct irq_data *d,
917 unsigned int type)
918{
919 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
920 const struct mtk_eint_offsets *eint_offsets =
921 &pctl->devdata->eint_offsets;
922 u32 mask = BIT(d->hwirq & 0x1f);
923 void __iomem *reg;
924
925 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
926 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
927 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
928 d->irq, d->hwirq, type);
929 return -EINVAL;
930 }
931
932 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
933 pctl->eint_dual_edges[d->hwirq] = 1;
934 else
935 pctl->eint_dual_edges[d->hwirq] = 0;
936
937 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
938 reg = mtk_eint_get_offset(pctl, d->hwirq,
939 eint_offsets->pol_clr);
940 writel(mask, reg);
941 } else {
942 reg = mtk_eint_get_offset(pctl, d->hwirq,
943 eint_offsets->pol_set);
944 writel(mask, reg);
945 }
946
947 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
948 reg = mtk_eint_get_offset(pctl, d->hwirq,
949 eint_offsets->sens_clr);
950 writel(mask, reg);
951 } else {
952 reg = mtk_eint_get_offset(pctl, d->hwirq,
953 eint_offsets->sens_set);
954 writel(mask, reg);
955 }
956
957 if (pctl->eint_dual_edges[d->hwirq])
958 mtk_eint_flip_edge(pctl, d->hwirq);
959
960 return 0;
961}
962
963static void mtk_eint_ack(struct irq_data *d)
964{
965 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
966 const struct mtk_eint_offsets *eint_offsets =
967 &pctl->devdata->eint_offsets;
968 u32 mask = BIT(d->hwirq & 0x1f);
969 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
970 eint_offsets->ack);
971
972 writel(mask, reg);
973}
974
975static struct irq_chip mtk_pinctrl_irq_chip = {
976 .name = "mt-eint",
977 .irq_mask = mtk_eint_mask,
978 .irq_unmask = mtk_eint_unmask,
979 .irq_ack = mtk_eint_ack,
980 .irq_set_type = mtk_eint_set_type,
981 .irq_request_resources = mtk_pinctrl_irq_request_resources,
982 .irq_release_resources = mtk_pinctrl_irq_release_resources,
983};
984
985static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
986{
987 const struct mtk_eint_offsets *eint_offsets =
988 &pctl->devdata->eint_offsets;
989 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
990 unsigned int i;
991
992 for (i = 0; i < pctl->devdata->ap_num; i += 32) {
993 writel(0xffffffff, reg);
994 reg += 4;
995 }
996 return 0;
997}
998
999static inline void
1000mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
1001{
1002 unsigned int rst, ctrl_offset;
1003 unsigned int bit, dbnc;
1004 const struct mtk_eint_offsets *eint_offsets =
1005 &pctl->devdata->eint_offsets;
1006
1007 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
1008 dbnc = readl(pctl->eint_reg_base + ctrl_offset);
1009 bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
1010 if ((bit & dbnc) > 0) {
1011 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
1012 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
1013 writel(rst, pctl->eint_reg_base + ctrl_offset);
1014 }
1015}
1016
1017static void mtk_eint_irq_handler(unsigned irq, struct irq_desc *desc)
1018{
1019 struct irq_chip *chip = irq_get_chip(irq);
1020 struct mtk_pinctrl *pctl = irq_get_handler_data(irq);
1021 unsigned int status, eint_num;
1022 int offset, index, virq;
1023 const struct mtk_eint_offsets *eint_offsets =
1024 &pctl->devdata->eint_offsets;
1025 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
1026 int dual_edges, start_level, curr_level;
1027 const struct mtk_desc_pin *pin;
1028
1029 chained_irq_enter(chip, desc);
1030 for (eint_num = 0; eint_num < pctl->devdata->ap_num; eint_num += 32) {
1031 status = readl(reg);
1032 reg += 4;
1033 while (status) {
1034 offset = __ffs(status);
1035 index = eint_num + offset;
1036 virq = irq_find_mapping(pctl->domain, index);
1037 status &= ~BIT(offset);
1038
1039 dual_edges = pctl->eint_dual_edges[index];
1040 if (dual_edges) {
1041 /* Clear soft-irq in case we raised it
1042 last time */
1043 writel(BIT(offset), reg - eint_offsets->stat +
1044 eint_offsets->soft_clr);
1045
1046 pin = mtk_find_pin_by_eint_num(pctl, index);
1047 start_level = mtk_gpio_get(pctl->chip,
1048 pin->pin.number);
1049 }
1050
1051 generic_handle_irq(virq);
1052
1053 if (dual_edges) {
1054 curr_level = mtk_eint_flip_edge(pctl, index);
1055
1056 /* If level changed, we might lost one edge
1057 interrupt, raised it through soft-irq */
1058 if (start_level != curr_level)
1059 writel(BIT(offset), reg -
1060 eint_offsets->stat +
1061 eint_offsets->soft_set);
1062 }
1063
1064 if (index < pctl->devdata->db_cnt)
1065 mtk_eint_debounce_process(pctl , index);
1066 }
1067 }
1068 chained_irq_exit(chip, desc);
1069}
1070
1071static int mtk_pctrl_build_state(struct platform_device *pdev)
1072{
1073 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
1074 int i;
1075
1076 pctl->ngroups = pctl->devdata->npins;
1077
1078 /* Allocate groups */
1079 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1080 sizeof(*pctl->groups), GFP_KERNEL);
1081 if (!pctl->groups)
1082 return -ENOMEM;
1083
1084 /* We assume that one pin is one group, use pin name as group name. */
1085 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1086 sizeof(*pctl->grp_names), GFP_KERNEL);
1087 if (!pctl->grp_names)
1088 return -ENOMEM;
1089
1090 for (i = 0; i < pctl->devdata->npins; i++) {
1091 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
1092 struct mtk_pinctrl_group *group = pctl->groups + i;
1093
1094 group->name = pin->pin.name;
1095 group->pin = pin->pin.number;
1096
1097 pctl->grp_names[i] = pin->pin.name;
1098 }
1099
1100 return 0;
1101}
1102
1103static struct pinctrl_desc mtk_pctrl_desc = {
1104 .confops = &mtk_pconf_ops,
1105 .pctlops = &mtk_pctrl_ops,
1106 .pmxops = &mtk_pmx_ops,
1107};
1108
1109int mtk_pctrl_init(struct platform_device *pdev,
1110 const struct mtk_pinctrl_devdata *data)
1111{
1112 struct pinctrl_pin_desc *pins;
1113 struct mtk_pinctrl *pctl;
1114 struct device_node *np = pdev->dev.of_node, *node;
1115 struct property *prop;
1116 struct resource *res;
1117 int i, ret, irq;
1118
1119 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1120 if (!pctl)
1121 return -ENOMEM;
1122
1123 platform_set_drvdata(pdev, pctl);
1124
1125 prop = of_find_property(np, "pins-are-numbered", NULL);
1126 if (!prop) {
1127 dev_err(&pdev->dev, "only support pins-are-numbered format\n");
1128 return -EINVAL;
1129 }
1130
1131 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1132 if (node) {
1133 pctl->regmap1 = syscon_node_to_regmap(node);
1134 if (IS_ERR(pctl->regmap1))
1135 return PTR_ERR(pctl->regmap1);
1136 }
1137
1138 /* Only 8135 has two base addr, other SoCs have only one. */
1139 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1140 if (node) {
1141 pctl->regmap2 = syscon_node_to_regmap(node);
1142 if (IS_ERR(pctl->regmap2))
1143 return PTR_ERR(pctl->regmap2);
1144 }
1145
1146 pctl->devdata = data;
1147 ret = mtk_pctrl_build_state(pdev);
1148 if (ret) {
1149 dev_err(&pdev->dev, "build state failed: %d\n", ret);
1150 return -EINVAL;
1151 }
1152
1153 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
1154 GFP_KERNEL);
1155 if (!pins)
1156 return -ENOMEM;
1157
1158 for (i = 0; i < pctl->devdata->npins; i++)
1159 pins[i] = pctl->devdata->pins[i].pin;
1160 mtk_pctrl_desc.name = dev_name(&pdev->dev);
1161 mtk_pctrl_desc.owner = THIS_MODULE;
1162 mtk_pctrl_desc.pins = pins;
1163 mtk_pctrl_desc.npins = pctl->devdata->npins;
1164 pctl->dev = &pdev->dev;
1165 pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl);
1166 if (!pctl->pctl_dev) {
1167 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1168 return -EINVAL;
1169 }
1170
1171 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1172 if (!pctl->chip) {
1173 ret = -ENOMEM;
1174 goto pctrl_error;
1175 }
1176
1177 pctl->chip = &mtk_gpio_chip;
1178 pctl->chip->ngpio = pctl->devdata->npins;
1179 pctl->chip->label = dev_name(&pdev->dev);
1180 pctl->chip->dev = &pdev->dev;
1181 pctl->chip->base = 0;
1182
1183 ret = gpiochip_add(pctl->chip);
1184 if (ret) {
1185 ret = -EINVAL;
1186 goto pctrl_error;
1187 }
1188
1189 /* Register the GPIO to pin mappings. */
1190 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1191 0, 0, pctl->devdata->npins);
1192 if (ret) {
1193 ret = -EINVAL;
1194 goto chip_error;
1195 }
1196
1197 /* Get EINT register base from dts. */
1198 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1199 if (!res) {
1200 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
1201 ret = -EINVAL;
1202 goto chip_error;
1203 }
1204
1205 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
1206 if (IS_ERR(pctl->eint_reg_base)) {
1207 ret = -EINVAL;
1208 goto chip_error;
1209 }
1210
1211 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
1212 sizeof(int), GFP_KERNEL);
1213 if (!pctl->eint_dual_edges) {
1214 ret = -ENOMEM;
1215 goto chip_error;
1216 }
1217
1218 irq = irq_of_parse_and_map(np, 0);
1219 if (!irq) {
1220 dev_err(&pdev->dev, "couldn't parse and map irq\n");
1221 ret = -EINVAL;
1222 goto chip_error;
1223 }
1224
1225 pctl->domain = irq_domain_add_linear(np,
1226 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
1227 if (!pctl->domain) {
1228 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1229 ret = -ENOMEM;
1230 goto chip_error;
1231 }
1232
1233 mtk_eint_init(pctl);
1234 for (i = 0; i < pctl->devdata->ap_num; i++) {
1235 int virq = irq_create_mapping(pctl->domain, i);
1236
1237 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1238 handle_level_irq);
1239 irq_set_chip_data(virq, pctl);
1240 set_irq_flags(virq, IRQF_VALID);
1241 };
1242
1243 irq_set_chained_handler(irq, mtk_eint_irq_handler);
1244 irq_set_handler_data(irq, pctl);
1245 set_irq_flags(irq, IRQF_VALID);
1246 return 0;
1247
1248chip_error:
1249 gpiochip_remove(pctl->chip);
1250pctrl_error:
1251 pinctrl_unregister(pctl->pctl_dev);
1252 return ret;
1253}
1254
1255MODULE_LICENSE("GPL");
1256MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
1257MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
new file mode 100644
index 000000000000..375771db9bd0
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -0,0 +1,229 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __PINCTRL_MTK_COMMON_H
16#define __PINCTRL_MTK_COMMON_H
17
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/regmap.h>
20
21#define NO_EINT_SUPPORT 255
22#define MTK_CHIP_TYPE_BASE 0
23#define MTK_CHIP_TYPE_PMIC 1
24#define MT_EDGE_SENSITIVE 0
25#define MT_LEVEL_SENSITIVE 1
26#define EINT_DBNC_SET_DBNC_BITS 4
27#define EINT_DBNC_RST_BIT (0x1 << 1)
28#define EINT_DBNC_SET_EN (0x1 << 0)
29
30struct mtk_desc_function {
31 const char *name;
32 unsigned char muxval;
33};
34
35struct mtk_desc_eint {
36 unsigned char eintmux;
37 unsigned char eintnum;
38};
39
40struct mtk_desc_pin {
41 struct pinctrl_pin_desc pin;
42 const char *chip;
43 const struct mtk_desc_eint eint;
44 const struct mtk_desc_function *functions;
45};
46
47#define MTK_PIN(_pin, _pad, _chip, _eint, ...) \
48 { \
49 .pin = _pin, \
50 .chip = _chip, \
51 .eint = _eint, \
52 .functions = (struct mtk_desc_function[]){ \
53 __VA_ARGS__, { } }, \
54 }
55
56#define MTK_EINT_FUNCTION(_eintmux, _eintnum) \
57 { \
58 .eintmux = _eintmux, \
59 .eintnum = _eintnum, \
60 }
61
62#define MTK_FUNCTION(_val, _name) \
63 { \
64 .muxval = _val, \
65 .name = _name, \
66 }
67
68#define SET_ADDR(x, y) (x + (y->devdata->port_align))
69#define CLR_ADDR(x, y) (x + (y->devdata->port_align << 1))
70
71struct mtk_pinctrl_group {
72 const char *name;
73 unsigned long config;
74 unsigned pin;
75};
76
77/**
78 * struct mtk_drv_group_desc - Provide driving group data.
79 * @max_drv: The maximum current of this group.
80 * @min_drv: The minimum current of this group.
81 * @low_bit: The lowest bit of this group.
82 * @high_bit: The highest bit of this group.
83 * @step: The step current of this group.
84 */
85struct mtk_drv_group_desc {
86 unsigned char min_drv;
87 unsigned char max_drv;
88 unsigned char low_bit;
89 unsigned char high_bit;
90 unsigned char step;
91};
92
93#define MTK_DRV_GRP(_min, _max, _low, _high, _step) \
94 { \
95 .min_drv = _min, \
96 .max_drv = _max, \
97 .low_bit = _low, \
98 .high_bit = _high, \
99 .step = _step, \
100 }
101
102/**
103 * struct mtk_pin_drv_grp - Provide each pin driving info.
104 * @pin: The pin number.
105 * @offset: The offset of driving register for this pin.
106 * @bit: The bit of driving register for this pin.
107 * @grp: The group for this pin belongs to.
108 */
109struct mtk_pin_drv_grp {
110 unsigned int pin;
111 unsigned int offset;
112 unsigned char bit;
113 unsigned char grp;
114};
115
116#define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \
117 { \
118 .pin = _pin, \
119 .offset = _offset, \
120 .bit = _bit, \
121 .grp = _grp, \
122 }
123
124struct mtk_eint_offsets {
125 const char *name;
126 unsigned int stat;
127 unsigned int ack;
128 unsigned int mask;
129 unsigned int mask_set;
130 unsigned int mask_clr;
131 unsigned int sens;
132 unsigned int sens_set;
133 unsigned int sens_clr;
134 unsigned int soft;
135 unsigned int soft_set;
136 unsigned int soft_clr;
137 unsigned int pol;
138 unsigned int pol_set;
139 unsigned int pol_clr;
140 unsigned int dom_en;
141 unsigned int dbnc_ctrl;
142 unsigned int dbnc_set;
143 unsigned int dbnc_clr;
144 u8 port_mask;
145 u8 ports;
146};
147
148/**
149 * struct mtk_pinctrl_devdata - Provide HW GPIO related data.
150 * @pins: An array describing all pins the pin controller affects.
151 * @npins: The number of entries in @pins.
152 *
153 * @grp_desc: The driving group info.
154 * @pin_drv_grp: The driving group for all pins.
155 * @spec_pull_set: Each SoC may have special pins for pull up/down setting,
156 * these pins' pull setting are very different, they have separate pull
157 * up/down bit, R0 and R1 resistor bit, so they need special pull setting.
158 * If special setting is success, this should return 0, otherwise it should
159 * return non-zero value.
160 * @spec_ies_smt_set: Some pins are irregular, their input enable and smt
161 * control register are discontinuous, but they are mapping together. That
162 * means when user set smt, input enable is set at the same time. So they
163 * also need special control. If special control is success, this should
164 * return 0, otherwise return non-zero value.
165 *
166 * @dir_offset: The direction register offset.
167 * @pullen_offset: The pull-up/pull-down enable register offset.
168 * @pinmux_offset: The pinmux register offset.
169 *
170 * @type1_start: Some chips have two base addresses for pull select register,
171 * that means some pins use the first address and others use the second. This
172 * member record the start of pin number to use the second address.
173 * @type1_end: The end of pin number to use the second address.
174 *
175 * @port_shf: The shift between two registers.
176 * @port_mask: The mask of register.
177 * @port_align: Provide clear register and set register step.
178 */
179struct mtk_pinctrl_devdata {
180 const struct mtk_desc_pin *pins;
181 unsigned int npins;
182 const struct mtk_drv_group_desc *grp_desc;
183 unsigned int n_grp_cls;
184 const struct mtk_pin_drv_grp *pin_drv_grp;
185 unsigned int n_pin_drv_grps;
186 int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
187 unsigned char align, bool isup, unsigned int arg);
188 int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
189 unsigned char align, int value);
190 unsigned int dir_offset;
191 unsigned int ies_offset;
192 unsigned int smt_offset;
193 unsigned int pullen_offset;
194 unsigned int pullsel_offset;
195 unsigned int drv_offset;
196 unsigned int invser_offset;
197 unsigned int dout_offset;
198 unsigned int din_offset;
199 unsigned int pinmux_offset;
200 unsigned short type1_start;
201 unsigned short type1_end;
202 unsigned char port_shf;
203 unsigned char port_mask;
204 unsigned char port_align;
205 unsigned char chip_type;
206 struct mtk_eint_offsets eint_offsets;
207 unsigned int ap_num;
208 unsigned int db_cnt;
209};
210
211struct mtk_pinctrl {
212 struct regmap *regmap1;
213 struct regmap *regmap2;
214 struct device *dev;
215 struct gpio_chip *chip;
216 struct mtk_pinctrl_group *groups;
217 unsigned ngroups;
218 const char **grp_names;
219 struct pinctrl_dev *pctl_dev;
220 const struct mtk_pinctrl_devdata *devdata;
221 void __iomem *eint_reg_base;
222 struct irq_domain *domain;
223 int *eint_dual_edges;
224};
225
226int mtk_pctrl_init(struct platform_device *pdev,
227 const struct mtk_pinctrl_devdata *data);
228
229#endif /* __PINCTRL_MTK_COMMON_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
new file mode 100644
index 000000000000..e17aedb73c8d
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8135.h
@@ -0,0 +1,2114 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __PINCTRL_MTK_MT8135_H
16#define __PINCTRL_MTK_MT8135_H
17
18#include <linux/pinctrl/pinctrl.h>
19#include "pinctrl-mtk-common.h"
20
21static const struct mtk_desc_pin mtk_pins_mt8135[] = {
22 MTK_PIN(
23 PINCTRL_PIN(0, "MSDC0_DAT7"),
24 "D21", "mt8135",
25 MTK_EINT_FUNCTION(2, 49),
26 MTK_FUNCTION(0, "GPIO0"),
27 MTK_FUNCTION(1, "MSDC0_DAT7"),
28 MTK_FUNCTION(2, "EINT49"),
29 MTK_FUNCTION(3, "I2SOUT_DAT"),
30 MTK_FUNCTION(4, "DAC_DAT_OUT"),
31 MTK_FUNCTION(5, "PCM1_DO"),
32 MTK_FUNCTION(6, "SPI1_MO"),
33 MTK_FUNCTION(7, "NALE")
34 ),
35 MTK_PIN(
36 PINCTRL_PIN(1, "MSDC0_DAT6"),
37 "D22", "mt8135",
38 MTK_EINT_FUNCTION(2, 48),
39 MTK_FUNCTION(0, "GPIO1"),
40 MTK_FUNCTION(1, "MSDC0_DAT6"),
41 MTK_FUNCTION(2, "EINT48"),
42 MTK_FUNCTION(3, "I2SIN_WS"),
43 MTK_FUNCTION(4, "DAC_WS"),
44 MTK_FUNCTION(5, "PCM1_WS"),
45 MTK_FUNCTION(6, "SPI1_CSN"),
46 MTK_FUNCTION(7, "NCLE")
47 ),
48 MTK_PIN(
49 PINCTRL_PIN(2, "MSDC0_DAT5"),
50 "E22", "mt8135",
51 MTK_EINT_FUNCTION(2, 47),
52 MTK_FUNCTION(0, "GPIO2"),
53 MTK_FUNCTION(1, "MSDC0_DAT5"),
54 MTK_FUNCTION(2, "EINT47"),
55 MTK_FUNCTION(3, "I2SIN_CK"),
56 MTK_FUNCTION(4, "DAC_CK"),
57 MTK_FUNCTION(5, "PCM1_CK"),
58 MTK_FUNCTION(6, "SPI1_CLK"),
59 MTK_FUNCTION(7, "NLD4")
60 ),
61 MTK_PIN(
62 PINCTRL_PIN(3, "MSDC0_DAT4"),
63 "F21", "mt8135",
64 MTK_EINT_FUNCTION(2, 46),
65 MTK_FUNCTION(0, "GPIO3"),
66 MTK_FUNCTION(1, "MSDC0_DAT4"),
67 MTK_FUNCTION(2, "EINT46"),
68 MTK_FUNCTION(3, "A_FUNC_CK"),
69 MTK_FUNCTION(6, "LSCE1B_2X"),
70 MTK_FUNCTION(7, "NLD5")
71 ),
72 MTK_PIN(
73 PINCTRL_PIN(4, "MSDC0_CMD"),
74 "F20", "mt8135",
75 MTK_EINT_FUNCTION(2, 41),
76 MTK_FUNCTION(0, "GPIO4"),
77 MTK_FUNCTION(1, "MSDC0_CMD"),
78 MTK_FUNCTION(2, "EINT41"),
79 MTK_FUNCTION(3, "A_FUNC_DOUT[0]"),
80 MTK_FUNCTION(5, "USB_TEST_IO[0]"),
81 MTK_FUNCTION(6, "LRSTB_2X"),
82 MTK_FUNCTION(7, "NRNB")
83 ),
84 MTK_PIN(
85 PINCTRL_PIN(5, "MSDC0_CLK"),
86 "G18", "mt8135",
87 MTK_EINT_FUNCTION(2, 40),
88 MTK_FUNCTION(0, "GPIO5"),
89 MTK_FUNCTION(1, "MSDC0_CLK"),
90 MTK_FUNCTION(2, "EINT40"),
91 MTK_FUNCTION(3, "A_FUNC_DOUT[1]"),
92 MTK_FUNCTION(5, "USB_TEST_IO[1]"),
93 MTK_FUNCTION(6, "LPTE"),
94 MTK_FUNCTION(7, "NREB")
95 ),
96 MTK_PIN(
97 PINCTRL_PIN(6, "MSDC0_DAT3"),
98 "G21", "mt8135",
99 MTK_EINT_FUNCTION(2, 45),
100 MTK_FUNCTION(0, "GPIO6"),
101 MTK_FUNCTION(1, "MSDC0_DAT3"),
102 MTK_FUNCTION(2, "EINT45"),
103 MTK_FUNCTION(3, "A_FUNC_DOUT[2]"),
104 MTK_FUNCTION(5, "USB_TEST_IO[2]"),
105 MTK_FUNCTION(6, "LSCE0B_2X"),
106 MTK_FUNCTION(7, "NLD7")
107 ),
108 MTK_PIN(
109 PINCTRL_PIN(7, "MSDC0_DAT2"),
110 "E21", "mt8135",
111 MTK_EINT_FUNCTION(2, 44),
112 MTK_FUNCTION(0, "GPIO7"),
113 MTK_FUNCTION(1, "MSDC0_DAT2"),
114 MTK_FUNCTION(2, "EINT44"),
115 MTK_FUNCTION(3, "A_FUNC_DOUT[3]"),
116 MTK_FUNCTION(5, "USB_TEST_IO[3]"),
117 MTK_FUNCTION(6, "LSA0_2X"),
118 MTK_FUNCTION(7, "NLD14")
119 ),
120 MTK_PIN(
121 PINCTRL_PIN(8, "MSDC0_DAT1"),
122 "E23", "mt8135",
123 MTK_EINT_FUNCTION(2, 43),
124 MTK_FUNCTION(0, "GPIO8"),
125 MTK_FUNCTION(1, "MSDC0_DAT1"),
126 MTK_FUNCTION(2, "EINT43"),
127 MTK_FUNCTION(5, "USB_TEST_IO[4]"),
128 MTK_FUNCTION(6, "LSCK_2X"),
129 MTK_FUNCTION(7, "NLD11")
130 ),
131 MTK_PIN(
132 PINCTRL_PIN(9, "MSDC0_DAT0"),
133 "F22", "mt8135",
134 MTK_EINT_FUNCTION(2, 42),
135 MTK_FUNCTION(0, "GPIO9"),
136 MTK_FUNCTION(1, "MSDC0_DAT0"),
137 MTK_FUNCTION(2, "EINT42"),
138 MTK_FUNCTION(5, "USB_TEST_IO[5]"),
139 MTK_FUNCTION(6, "LSDA_2X")
140 ),
141 MTK_PIN(
142 PINCTRL_PIN(10, "NCEB0"),
143 "G20", "mt8135",
144 MTK_EINT_FUNCTION(2, 139),
145 MTK_FUNCTION(0, "GPIO10"),
146 MTK_FUNCTION(1, "NCEB0"),
147 MTK_FUNCTION(2, "EINT139"),
148 MTK_FUNCTION(7, "TESTA_OUT4")
149 ),
150 MTK_PIN(
151 PINCTRL_PIN(11, "NCEB1"),
152 "L17", "mt8135",
153 MTK_EINT_FUNCTION(2, 140),
154 MTK_FUNCTION(0, "GPIO11"),
155 MTK_FUNCTION(1, "NCEB1"),
156 MTK_FUNCTION(2, "EINT140"),
157 MTK_FUNCTION(6, "USB_DRVVBUS"),
158 MTK_FUNCTION(7, "TESTA_OUT5")
159 ),
160 MTK_PIN(
161 PINCTRL_PIN(12, "NRNB"),
162 "G19", "mt8135",
163 MTK_EINT_FUNCTION(2, 141),
164 MTK_FUNCTION(0, "GPIO12"),
165 MTK_FUNCTION(1, "NRNB"),
166 MTK_FUNCTION(2, "EINT141"),
167 MTK_FUNCTION(3, "A_FUNC_DOUT[4]"),
168 MTK_FUNCTION(7, "TESTA_OUT6")
169 ),
170 MTK_PIN(
171 PINCTRL_PIN(13, "NCLE"),
172 "J18", "mt8135",
173 MTK_EINT_FUNCTION(2, 142),
174 MTK_FUNCTION(0, "GPIO13"),
175 MTK_FUNCTION(1, "NCLE"),
176 MTK_FUNCTION(2, "EINT142"),
177 MTK_FUNCTION(3, "A_FUNC_DOUT[5]"),
178 MTK_FUNCTION(4, "CM2PDN_1X"),
179 MTK_FUNCTION(6, "NALE"),
180 MTK_FUNCTION(7, "TESTA_OUT7")
181 ),
182 MTK_PIN(
183 PINCTRL_PIN(14, "NALE"),
184 "J19", "mt8135",
185 MTK_EINT_FUNCTION(2, 143),
186 MTK_FUNCTION(0, "GPIO14"),
187 MTK_FUNCTION(1, "NALE"),
188 MTK_FUNCTION(2, "EINT143"),
189 MTK_FUNCTION(3, "A_FUNC_DOUT[6]"),
190 MTK_FUNCTION(4, "CM2MCLK_1X"),
191 MTK_FUNCTION(5, "IRDA_RXD"),
192 MTK_FUNCTION(6, "NCLE"),
193 MTK_FUNCTION(7, "TESTA_OUT8")
194 ),
195 MTK_PIN(
196 PINCTRL_PIN(15, "NREB"),
197 "L18", "mt8135",
198 MTK_EINT_FUNCTION(2, 144),
199 MTK_FUNCTION(0, "GPIO15"),
200 MTK_FUNCTION(1, "NREB"),
201 MTK_FUNCTION(2, "EINT144"),
202 MTK_FUNCTION(3, "A_FUNC_DOUT[7]"),
203 MTK_FUNCTION(4, "CM2RST_1X"),
204 MTK_FUNCTION(5, "IRDA_TXD"),
205 MTK_FUNCTION(7, "TESTA_OUT9")
206 ),
207 MTK_PIN(
208 PINCTRL_PIN(16, "NWEB"),
209 "J20", "mt8135",
210 MTK_EINT_FUNCTION(2, 145),
211 MTK_FUNCTION(0, "GPIO16"),
212 MTK_FUNCTION(1, "NWEB"),
213 MTK_FUNCTION(2, "EINT145"),
214 MTK_FUNCTION(3, "A_FUNC_DIN[0]"),
215 MTK_FUNCTION(4, "CM2PCLK_1X"),
216 MTK_FUNCTION(5, "IRDA_PDN"),
217 MTK_FUNCTION(7, "TESTA_OUT10")
218 ),
219 MTK_PIN(
220 PINCTRL_PIN(17, "NLD0"),
221 "K21", "mt8135",
222 MTK_EINT_FUNCTION(2, 146),
223 MTK_FUNCTION(0, "GPIO17"),
224 MTK_FUNCTION(1, "NLD0"),
225 MTK_FUNCTION(2, "EINT146"),
226 MTK_FUNCTION(3, "A_FUNC_DIN[1]"),
227 MTK_FUNCTION(4, "CM2DAT_1X[0]"),
228 MTK_FUNCTION(5, "I2SIN_CK"),
229 MTK_FUNCTION(6, "DAC_CK"),
230 MTK_FUNCTION(7, "TESTA_OUT11")
231 ),
232 MTK_PIN(
233 PINCTRL_PIN(18, "NLD1"),
234 "K22", "mt8135",
235 MTK_EINT_FUNCTION(2, 147),
236 MTK_FUNCTION(0, "GPIO18"),
237 MTK_FUNCTION(1, "NLD1"),
238 MTK_FUNCTION(2, "EINT147"),
239 MTK_FUNCTION(3, "A_FUNC_DIN[2]"),
240 MTK_FUNCTION(4, "CM2DAT_1X[1]"),
241 MTK_FUNCTION(5, "I2SIN_WS"),
242 MTK_FUNCTION(6, "DAC_WS"),
243 MTK_FUNCTION(7, "TESTA_OUT12")
244 ),
245 MTK_PIN(
246 PINCTRL_PIN(19, "NLD2"),
247 "J21", "mt8135",
248 MTK_EINT_FUNCTION(2, 148),
249 MTK_FUNCTION(0, "GPIO19"),
250 MTK_FUNCTION(1, "NLD2"),
251 MTK_FUNCTION(2, "EINT148"),
252 MTK_FUNCTION(3, "A_FUNC_DIN[3]"),
253 MTK_FUNCTION(4, "CM2DAT_1X[2]"),
254 MTK_FUNCTION(5, "I2SOUT_DAT"),
255 MTK_FUNCTION(6, "DAC_DAT_OUT"),
256 MTK_FUNCTION(7, "TESTA_OUT13")
257 ),
258 MTK_PIN(
259 PINCTRL_PIN(20, "NLD3"),
260 "J23", "mt8135",
261 MTK_EINT_FUNCTION(2, 149),
262 MTK_FUNCTION(0, "GPIO20"),
263 MTK_FUNCTION(1, "NLD3"),
264 MTK_FUNCTION(2, "EINT149"),
265 MTK_FUNCTION(3, "A_FUNC_DIN[4]"),
266 MTK_FUNCTION(4, "CM2DAT_1X[3]"),
267 MTK_FUNCTION(7, "TESTA_OUT14")
268 ),
269 MTK_PIN(
270 PINCTRL_PIN(21, "NLD4"),
271 "J22", "mt8135",
272 MTK_EINT_FUNCTION(2, 150),
273 MTK_FUNCTION(0, "GPIO21"),
274 MTK_FUNCTION(1, "NLD4"),
275 MTK_FUNCTION(2, "EINT150"),
276 MTK_FUNCTION(3, "A_FUNC_DIN[5]"),
277 MTK_FUNCTION(4, "CM2DAT_1X[4]"),
278 MTK_FUNCTION(7, "TESTA_OUT15")
279 ),
280 MTK_PIN(
281 PINCTRL_PIN(22, "NLD5"),
282 "H21", "mt8135",
283 MTK_EINT_FUNCTION(2, 151),
284 MTK_FUNCTION(0, "GPIO22"),
285 MTK_FUNCTION(1, "NLD5"),
286 MTK_FUNCTION(2, "EINT151"),
287 MTK_FUNCTION(3, "A_FUNC_DIN[6]"),
288 MTK_FUNCTION(4, "CM2DAT_1X[5]"),
289 MTK_FUNCTION(7, "TESTA_OUT16")
290 ),
291 MTK_PIN(
292 PINCTRL_PIN(23, "NLD6"),
293 "H22", "mt8135",
294 MTK_EINT_FUNCTION(2, 152),
295 MTK_FUNCTION(0, "GPIO23"),
296 MTK_FUNCTION(1, "NLD6"),
297 MTK_FUNCTION(2, "EINT152"),
298 MTK_FUNCTION(3, "A_FUNC_DIN[7]"),
299 MTK_FUNCTION(4, "CM2DAT_1X[6]"),
300 MTK_FUNCTION(7, "TESTA_OUT17")
301 ),
302 MTK_PIN(
303 PINCTRL_PIN(24, "NLD7"),
304 "H20", "mt8135",
305 MTK_EINT_FUNCTION(2, 153),
306 MTK_FUNCTION(0, "GPIO24"),
307 MTK_FUNCTION(1, "NLD7"),
308 MTK_FUNCTION(2, "EINT153"),
309 MTK_FUNCTION(3, "A_FUNC_DIN[8]"),
310 MTK_FUNCTION(4, "CM2DAT_1X[7]"),
311 MTK_FUNCTION(7, "TESTA_OUT18")
312 ),
313 MTK_PIN(
314 PINCTRL_PIN(25, "NLD8"),
315 NULL, "mt8135",
316 MTK_EINT_FUNCTION(2, 154),
317 MTK_FUNCTION(0, "GPIO25"),
318 MTK_FUNCTION(1, "NLD8"),
319 MTK_FUNCTION(2, "EINT154"),
320 MTK_FUNCTION(4, "CM2DAT_1X[8]")
321 ),
322 MTK_PIN(
323 PINCTRL_PIN(26, "NLD9"),
324 NULL, "mt8135",
325 MTK_EINT_FUNCTION(2, 155),
326 MTK_FUNCTION(0, "GPIO26"),
327 MTK_FUNCTION(1, "NLD9"),
328 MTK_FUNCTION(2, "EINT155"),
329 MTK_FUNCTION(4, "CM2DAT_1X[9]"),
330 MTK_FUNCTION(5, "PWM1")
331 ),
332 MTK_PIN(
333 PINCTRL_PIN(27, "NLD10"),
334 NULL, "mt8135",
335 MTK_EINT_FUNCTION(2, 156),
336 MTK_FUNCTION(0, "GPIO27"),
337 MTK_FUNCTION(1, "NLD10"),
338 MTK_FUNCTION(2, "EINT156"),
339 MTK_FUNCTION(4, "CM2VSYNC_1X"),
340 MTK_FUNCTION(5, "PWM2")
341 ),
342 MTK_PIN(
343 PINCTRL_PIN(28, "NLD11"),
344 NULL, "mt8135",
345 MTK_EINT_FUNCTION(2, 157),
346 MTK_FUNCTION(0, "GPIO28"),
347 MTK_FUNCTION(1, "NLD11"),
348 MTK_FUNCTION(2, "EINT157"),
349 MTK_FUNCTION(4, "CM2HSYNC_1X"),
350 MTK_FUNCTION(5, "PWM3")
351 ),
352 MTK_PIN(
353 PINCTRL_PIN(29, "NLD12"),
354 NULL, "mt8135",
355 MTK_EINT_FUNCTION(2, 158),
356 MTK_FUNCTION(0, "GPIO29"),
357 MTK_FUNCTION(1, "NLD12"),
358 MTK_FUNCTION(2, "EINT158"),
359 MTK_FUNCTION(3, "I2SIN_CK"),
360 MTK_FUNCTION(4, "DAC_CK"),
361 MTK_FUNCTION(5, "PCM1_CK")
362 ),
363 MTK_PIN(
364 PINCTRL_PIN(30, "NLD13"),
365 NULL, "mt8135",
366 MTK_EINT_FUNCTION(2, 159),
367 MTK_FUNCTION(0, "GPIO30"),
368 MTK_FUNCTION(1, "NLD13"),
369 MTK_FUNCTION(2, "EINT159"),
370 MTK_FUNCTION(3, "I2SIN_WS"),
371 MTK_FUNCTION(4, "DAC_WS"),
372 MTK_FUNCTION(5, "PCM1_WS")
373 ),
374 MTK_PIN(
375 PINCTRL_PIN(31, "NLD14"),
376 NULL, "mt8135",
377 MTK_EINT_FUNCTION(2, 160),
378 MTK_FUNCTION(0, "GPIO31"),
379 MTK_FUNCTION(1, "NLD14"),
380 MTK_FUNCTION(2, "EINT160"),
381 MTK_FUNCTION(3, "I2SOUT_DAT"),
382 MTK_FUNCTION(4, "DAC_DAT_OUT"),
383 MTK_FUNCTION(5, "PCM1_DO")
384 ),
385 MTK_PIN(
386 PINCTRL_PIN(32, "NLD15"),
387 NULL, "mt8135",
388 MTK_EINT_FUNCTION(2, 161),
389 MTK_FUNCTION(0, "GPIO32"),
390 MTK_FUNCTION(1, "NLD15"),
391 MTK_FUNCTION(2, "EINT161"),
392 MTK_FUNCTION(3, "DISP_PWM"),
393 MTK_FUNCTION(4, "PWM4"),
394 MTK_FUNCTION(5, "PCM1_DI")
395 ),
396 MTK_PIN(
397 PINCTRL_PIN(33, "MSDC0_RSTB"),
398 "G22", "mt8135",
399 MTK_EINT_FUNCTION(2, 50),
400 MTK_FUNCTION(0, "GPIO33"),
401 MTK_FUNCTION(1, "MSDC0_RSTB"),
402 MTK_FUNCTION(2, "EINT50"),
403 MTK_FUNCTION(3, "I2SIN_DAT"),
404 MTK_FUNCTION(5, "PCM1_DI"),
405 MTK_FUNCTION(6, "SPI1_MI"),
406 MTK_FUNCTION(7, "NLD10")
407 ),
408 MTK_PIN(
409 PINCTRL_PIN(34, "IDDIG"),
410 "N17", "mt8135",
411 MTK_EINT_FUNCTION(2, 34),
412 MTK_FUNCTION(0, "GPIO34"),
413 MTK_FUNCTION(1, "IDDIG"),
414 MTK_FUNCTION(2, "EINT34")
415 ),
416 MTK_PIN(
417 PINCTRL_PIN(35, "SCL3"),
418 "L19", "mt8135",
419 MTK_EINT_FUNCTION(2, 96),
420 MTK_FUNCTION(0, "GPIO35"),
421 MTK_FUNCTION(1, "SCL3"),
422 MTK_FUNCTION(2, "EINT96"),
423 MTK_FUNCTION(3, "CLKM6"),
424 MTK_FUNCTION(4, "PWM6")
425 ),
426 MTK_PIN(
427 PINCTRL_PIN(36, "SDA3"),
428 "L20", "mt8135",
429 MTK_EINT_FUNCTION(2, 97),
430 MTK_FUNCTION(0, "GPIO36"),
431 MTK_FUNCTION(1, "SDA3"),
432 MTK_FUNCTION(2, "EINT97")
433 ),
434 MTK_PIN(
435 PINCTRL_PIN(37, "AUD_CLK_MOSI"),
436 "L21", "mt8135",
437 MTK_EINT_FUNCTION(4, 19),
438 MTK_FUNCTION(0, "GPIO37"),
439 MTK_FUNCTION(1, "AUD_CLK"),
440 MTK_FUNCTION(2, "ADC_CK"),
441 MTK_FUNCTION(3, " HDMI_SDATA0"),
442 MTK_FUNCTION(4, "EINT19"),
443 MTK_FUNCTION(5, "USB_TEST_IO[6]"),
444 MTK_FUNCTION(7, "TESTA_OUT19")
445 ),
446 MTK_PIN(
447 PINCTRL_PIN(38, "AUD_DAT_MOSI"),
448 "L23", "mt8135",
449 MTK_EINT_FUNCTION(4, 21),
450 MTK_FUNCTION(0, "GPIO38"),
451 MTK_FUNCTION(1, "AUD_DAT_MOSI"),
452 MTK_FUNCTION(2, "ADC_WS"),
453 MTK_FUNCTION(3, "AUD_DAT_MISO"),
454 MTK_FUNCTION(4, "EINT21"),
455 MTK_FUNCTION(5, "USB_TEST_IO[7]"),
456 MTK_FUNCTION(7, "TESTA_OUT20")
457 ),
458 MTK_PIN(
459 PINCTRL_PIN(39, "AUD_DAT_MISO"),
460 "L22", "mt8135",
461 MTK_EINT_FUNCTION(4, 20),
462 MTK_FUNCTION(0, "GPIO39"),
463 MTK_FUNCTION(1, "AUD_DAT_MISO"),
464 MTK_FUNCTION(2, "ADC_DAT_IN"),
465 MTK_FUNCTION(3, "AUD_DAT_MOSI"),
466 MTK_FUNCTION(4, "EINT20"),
467 MTK_FUNCTION(5, "USB_TEST_IO[8]"),
468 MTK_FUNCTION(7, "TESTA_OUT21")
469 ),
470 MTK_PIN(
471 PINCTRL_PIN(40, "DAC_CLK"),
472 "P21", "mt8135",
473 MTK_EINT_FUNCTION(2, 22),
474 MTK_FUNCTION(0, "GPIO40"),
475 MTK_FUNCTION(1, "DAC_CK"),
476 MTK_FUNCTION(2, "EINT22"),
477 MTK_FUNCTION(3, " HDMI_SDATA1"),
478 MTK_FUNCTION(5, "USB_TEST_IO[9]"),
479 MTK_FUNCTION(7, "TESTA_OUT22")
480 ),
481 MTK_PIN(
482 PINCTRL_PIN(41, "DAC_WS"),
483 "N18", "mt8135",
484 MTK_EINT_FUNCTION(2, 24),
485 MTK_FUNCTION(0, "GPIO41"),
486 MTK_FUNCTION(1, "DAC_WS"),
487 MTK_FUNCTION(2, "EINT24"),
488 MTK_FUNCTION(3, " HDMI_SDATA2"),
489 MTK_FUNCTION(5, "USB_TEST_IO[10]"),
490 MTK_FUNCTION(7, "TESTA_OUT23")
491 ),
492 MTK_PIN(
493 PINCTRL_PIN(42, "DAC_DAT_OUT"),
494 "N22", "mt8135",
495 MTK_EINT_FUNCTION(2, 23),
496 MTK_FUNCTION(0, "GPIO42"),
497 MTK_FUNCTION(1, "DAC_DAT_OUT"),
498 MTK_FUNCTION(2, "EINT23"),
499 MTK_FUNCTION(3, " HDMI_SDATA3"),
500 MTK_FUNCTION(5, "USB_TEST_IO[11]"),
501 MTK_FUNCTION(7, "TESTA_OUT24")
502 ),
503 MTK_PIN(
504 PINCTRL_PIN(43, "PWRAP_SPI0_MO"),
505 "M22", "mt8135",
506 MTK_EINT_FUNCTION(2, 29),
507 MTK_FUNCTION(0, "GPIO43"),
508 MTK_FUNCTION(1, "PWRAP_SPIDI"),
509 MTK_FUNCTION(2, "EINT29")
510 ),
511 MTK_PIN(
512 PINCTRL_PIN(44, "PWRAP_SPI0_MI"),
513 "P23", "mt8135",
514 MTK_EINT_FUNCTION(2, 28),
515 MTK_FUNCTION(0, "GPIO44"),
516 MTK_FUNCTION(1, "PWRAP_SPIDO"),
517 MTK_FUNCTION(2, "EINT28")
518 ),
519 MTK_PIN(
520 PINCTRL_PIN(45, "PWRAP_SPI0_CSN"),
521 "M21", "mt8135",
522 MTK_EINT_FUNCTION(2, 27),
523 MTK_FUNCTION(0, "GPIO45"),
524 MTK_FUNCTION(1, "PWRAP_SPICS_B_I"),
525 MTK_FUNCTION(2, "EINT27")
526 ),
527 MTK_PIN(
528 PINCTRL_PIN(46, "PWRAP_SPI0_CLK"),
529 "P22", "mt8135",
530 MTK_EINT_FUNCTION(2, 26),
531 MTK_FUNCTION(0, "GPIO46"),
532 MTK_FUNCTION(1, "PWRAP_SPICK_I"),
533 MTK_FUNCTION(2, "EINT26")
534 ),
535 MTK_PIN(
536 PINCTRL_PIN(47, "PWRAP_EVENT"),
537 "M23", "mt8135",
538 MTK_EINT_FUNCTION(2, 25),
539 MTK_FUNCTION(0, "GPIO47"),
540 MTK_FUNCTION(1, "PWRAP_EVENT_IN"),
541 MTK_FUNCTION(2, "EINT25"),
542 MTK_FUNCTION(7, "TESTA_OUT2")
543 ),
544 MTK_PIN(
545 PINCTRL_PIN(48, "RTC32K_CK"),
546 "N20", "mt8135",
547 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
548 MTK_FUNCTION(0, "GPIO48"),
549 MTK_FUNCTION(1, "RTC32K_CK")
550 ),
551 MTK_PIN(
552 PINCTRL_PIN(49, "WATCHDOG"),
553 "R22", "mt8135",
554 MTK_EINT_FUNCTION(2, 36),
555 MTK_FUNCTION(0, "GPIO49"),
556 MTK_FUNCTION(1, "WATCHDOG"),
557 MTK_FUNCTION(2, "EINT36")
558 ),
559 MTK_PIN(
560 PINCTRL_PIN(50, "SRCLKENA"),
561 "T22", "mt8135",
562 MTK_EINT_FUNCTION(2, 38),
563 MTK_FUNCTION(0, "GPIO50"),
564 MTK_FUNCTION(1, "SRCLKENA"),
565 MTK_FUNCTION(2, "EINT38")
566 ),
567 MTK_PIN(
568 PINCTRL_PIN(51, "SRCVOLTEN"),
569 "T23", "mt8135",
570 MTK_EINT_FUNCTION(2, 37),
571 MTK_FUNCTION(0, "GPIO51"),
572 MTK_FUNCTION(1, "SRCVOLTEN"),
573 MTK_FUNCTION(2, "EINT37")
574 ),
575 MTK_PIN(
576 PINCTRL_PIN(52, "EINT0"),
577 "T21", "mt8135",
578 MTK_EINT_FUNCTION(1, 0),
579 MTK_FUNCTION(0, "GPIO52"),
580 MTK_FUNCTION(1, "EINT0"),
581 MTK_FUNCTION(2, "PWM1"),
582 MTK_FUNCTION(3, "CLKM0"),
583 MTK_FUNCTION(4, " SPDIF_OUT"),
584 MTK_FUNCTION(5, "USB_TEST_IO[12]"),
585 MTK_FUNCTION(7, "USB_SCL")
586 ),
587 MTK_PIN(
588 PINCTRL_PIN(53, "URXD2"),
589 "R18", "mt8135",
590 MTK_EINT_FUNCTION(2, 83),
591 MTK_FUNCTION(0, "GPIO53"),
592 MTK_FUNCTION(1, "URXD2"),
593 MTK_FUNCTION(2, "EINT83"),
594 MTK_FUNCTION(4, " HDMI_LRCK"),
595 MTK_FUNCTION(5, "CLKM3"),
596 MTK_FUNCTION(7, "UTXD2")
597 ),
598 MTK_PIN(
599 PINCTRL_PIN(54, "UTXD2"),
600 "R17", "mt8135",
601 MTK_EINT_FUNCTION(2, 82),
602 MTK_FUNCTION(0, "GPIO54"),
603 MTK_FUNCTION(1, "UTXD2"),
604 MTK_FUNCTION(2, "EINT82"),
605 MTK_FUNCTION(4, " HDMI_BCK_OUT"),
606 MTK_FUNCTION(5, "CLKM2"),
607 MTK_FUNCTION(7, "URXD2")
608 ),
609 MTK_PIN(
610 PINCTRL_PIN(55, "UCTS2"),
611 "R20", "mt8135",
612 MTK_EINT_FUNCTION(2, 84),
613 MTK_FUNCTION(0, "GPIO55"),
614 MTK_FUNCTION(1, "UCTS2"),
615 MTK_FUNCTION(2, "EINT84"),
616 MTK_FUNCTION(5, "PWM1"),
617 MTK_FUNCTION(7, "URTS2")
618 ),
619 MTK_PIN(
620 PINCTRL_PIN(56, "URTS2"),
621 "R19", "mt8135",
622 MTK_EINT_FUNCTION(2, 85),
623 MTK_FUNCTION(0, "GPIO56"),
624 MTK_FUNCTION(1, "URTS2"),
625 MTK_FUNCTION(2, "EINT85"),
626 MTK_FUNCTION(5, "PWM2"),
627 MTK_FUNCTION(7, "UCTS2")
628 ),
629 MTK_PIN(
630 PINCTRL_PIN(57, "JTCK"),
631 "V17", "mt8135",
632 MTK_EINT_FUNCTION(2, 188),
633 MTK_FUNCTION(0, "GPIO57"),
634 MTK_FUNCTION(1, "JTCK"),
635 MTK_FUNCTION(2, "EINT188"),
636 MTK_FUNCTION(3, "DSP1_ICK")
637 ),
638 MTK_PIN(
639 PINCTRL_PIN(58, "JTDO"),
640 "T16", "mt8135",
641 MTK_EINT_FUNCTION(2, 190),
642 MTK_FUNCTION(0, "GPIO58"),
643 MTK_FUNCTION(1, "JTDO"),
644 MTK_FUNCTION(2, "EINT190"),
645 MTK_FUNCTION(3, "DSP2_IMS")
646 ),
647 MTK_PIN(
648 PINCTRL_PIN(59, "JTRST_B"),
649 "T19", "mt8135",
650 MTK_EINT_FUNCTION(2, 0),
651 MTK_FUNCTION(0, "GPIO59"),
652 MTK_FUNCTION(1, "JTRST_B"),
653 MTK_FUNCTION(2, "EINT0"),
654 MTK_FUNCTION(3, "DSP2_ICK")
655 ),
656 MTK_PIN(
657 PINCTRL_PIN(60, "JTDI"),
658 "T18", "mt8135",
659 MTK_EINT_FUNCTION(2, 189),
660 MTK_FUNCTION(0, "GPIO60"),
661 MTK_FUNCTION(1, "JTDI"),
662 MTK_FUNCTION(2, "EINT189"),
663 MTK_FUNCTION(3, "DSP1_IMS")
664 ),
665 MTK_PIN(
666 PINCTRL_PIN(61, "JRTCK"),
667 "T20", "mt8135",
668 MTK_EINT_FUNCTION(2, 187),
669 MTK_FUNCTION(0, "GPIO61"),
670 MTK_FUNCTION(1, "JRTCK"),
671 MTK_FUNCTION(2, "EINT187"),
672 MTK_FUNCTION(3, "DSP1_ID")
673 ),
674 MTK_PIN(
675 PINCTRL_PIN(62, "JTMS"),
676 "T17", "mt8135",
677 MTK_EINT_FUNCTION(2, 191),
678 MTK_FUNCTION(0, "GPIO62"),
679 MTK_FUNCTION(1, "JTMS"),
680 MTK_FUNCTION(2, "EINT191"),
681 MTK_FUNCTION(3, "DSP2_ID")
682 ),
683 MTK_PIN(
684 PINCTRL_PIN(63, "MSDC1_INSI"),
685 "V18", "mt8135",
686 MTK_EINT_FUNCTION(1, 15),
687 MTK_FUNCTION(0, "GPIO63"),
688 MTK_FUNCTION(1, "MSDC1_INSI"),
689 MTK_FUNCTION(3, "SCL5"),
690 MTK_FUNCTION(4, "PWM6"),
691 MTK_FUNCTION(5, "CLKM5"),
692 MTK_FUNCTION(7, "TESTB_OUT6")
693 ),
694 MTK_PIN(
695 PINCTRL_PIN(64, "MSDC1_SDWPI"),
696 "W18", "mt8135",
697 MTK_EINT_FUNCTION(2, 58),
698 MTK_FUNCTION(0, "GPIO64"),
699 MTK_FUNCTION(1, "MSDC1_SDWPI"),
700 MTK_FUNCTION(2, "EINT58"),
701 MTK_FUNCTION(3, "SDA5"),
702 MTK_FUNCTION(4, "PWM7"),
703 MTK_FUNCTION(5, "CLKM6"),
704 MTK_FUNCTION(7, "TESTB_OUT7")
705 ),
706 MTK_PIN(
707 PINCTRL_PIN(65, "MSDC2_INSI"),
708 "U22", "mt8135",
709 MTK_EINT_FUNCTION(1, 14),
710 MTK_FUNCTION(0, "GPIO65"),
711 MTK_FUNCTION(1, "MSDC2_INSI"),
712 MTK_FUNCTION(5, "USB_TEST_IO[27]"),
713 MTK_FUNCTION(7, "TESTA_OUT3")
714 ),
715 MTK_PIN(
716 PINCTRL_PIN(66, "MSDC2_SDWPI"),
717 "U21", "mt8135",
718 MTK_EINT_FUNCTION(2, 66),
719 MTK_FUNCTION(0, "GPIO66"),
720 MTK_FUNCTION(1, "MSDC2_SDWPI"),
721 MTK_FUNCTION(2, "EINT66"),
722 MTK_FUNCTION(5, "USB_TEST_IO[28]")
723 ),
724 MTK_PIN(
725 PINCTRL_PIN(67, "URXD4"),
726 "V23", "mt8135",
727 MTK_EINT_FUNCTION(2, 89),
728 MTK_FUNCTION(0, "GPIO67"),
729 MTK_FUNCTION(1, "URXD4"),
730 MTK_FUNCTION(2, "EINT89"),
731 MTK_FUNCTION(3, "URXD1"),
732 MTK_FUNCTION(6, "UTXD4"),
733 MTK_FUNCTION(7, "TESTB_OUT10")
734 ),
735 MTK_PIN(
736 PINCTRL_PIN(68, "UTXD4"),
737 "V22", "mt8135",
738 MTK_EINT_FUNCTION(2, 88),
739 MTK_FUNCTION(0, "GPIO68"),
740 MTK_FUNCTION(1, "UTXD4"),
741 MTK_FUNCTION(2, "EINT88"),
742 MTK_FUNCTION(3, "UTXD1"),
743 MTK_FUNCTION(6, "URXD4"),
744 MTK_FUNCTION(7, "TESTB_OUT11")
745 ),
746 MTK_PIN(
747 PINCTRL_PIN(69, "URXD1"),
748 "W22", "mt8135",
749 MTK_EINT_FUNCTION(2, 79),
750 MTK_FUNCTION(0, "GPIO69"),
751 MTK_FUNCTION(1, "URXD1"),
752 MTK_FUNCTION(2, "EINT79"),
753 MTK_FUNCTION(3, "URXD4"),
754 MTK_FUNCTION(6, "UTXD1"),
755 MTK_FUNCTION(7, "TESTB_OUT24")
756 ),
757 MTK_PIN(
758 PINCTRL_PIN(70, "UTXD1"),
759 "V21", "mt8135",
760 MTK_EINT_FUNCTION(2, 78),
761 MTK_FUNCTION(0, "GPIO70"),
762 MTK_FUNCTION(1, "UTXD1"),
763 MTK_FUNCTION(2, "EINT78"),
764 MTK_FUNCTION(3, "UTXD4"),
765 MTK_FUNCTION(6, "URXD1"),
766 MTK_FUNCTION(7, "TESTB_OUT25")
767 ),
768 MTK_PIN(
769 PINCTRL_PIN(71, "UCTS1"),
770 "V19", "mt8135",
771 MTK_EINT_FUNCTION(2, 80),
772 MTK_FUNCTION(0, "GPIO71"),
773 MTK_FUNCTION(1, "UCTS1"),
774 MTK_FUNCTION(2, "EINT80"),
775 MTK_FUNCTION(5, "CLKM0"),
776 MTK_FUNCTION(6, "URTS1"),
777 MTK_FUNCTION(7, "TESTB_OUT31")
778 ),
779 MTK_PIN(
780 PINCTRL_PIN(72, "URTS1"),
781 "V20", "mt8135",
782 MTK_EINT_FUNCTION(2, 81),
783 MTK_FUNCTION(0, "GPIO72"),
784 MTK_FUNCTION(1, "URTS1"),
785 MTK_FUNCTION(2, "EINT81"),
786 MTK_FUNCTION(5, "CLKM1"),
787 MTK_FUNCTION(6, "UCTS1"),
788 MTK_FUNCTION(7, "TESTB_OUT21")
789 ),
790 MTK_PIN(
791 PINCTRL_PIN(73, "PWM1"),
792 "W17", "mt8135",
793 MTK_EINT_FUNCTION(2, 73),
794 MTK_FUNCTION(0, "GPIO73"),
795 MTK_FUNCTION(1, "PWM1"),
796 MTK_FUNCTION(2, "EINT73"),
797 MTK_FUNCTION(5, "USB_DRVVBUS"),
798 MTK_FUNCTION(6, "DISP_PWM"),
799 MTK_FUNCTION(7, "TESTB_OUT8")
800 ),
801 MTK_PIN(
802 PINCTRL_PIN(74, "PWM2"),
803 "Y17", "mt8135",
804 MTK_EINT_FUNCTION(2, 74),
805 MTK_FUNCTION(0, "GPIO74"),
806 MTK_FUNCTION(1, "PWM2"),
807 MTK_FUNCTION(2, "EINT74"),
808 MTK_FUNCTION(3, "DPI33_CK"),
809 MTK_FUNCTION(4, "PWM5"),
810 MTK_FUNCTION(5, "URXD2"),
811 MTK_FUNCTION(6, "DISP_PWM"),
812 MTK_FUNCTION(7, "TESTB_OUT9")
813 ),
814 MTK_PIN(
815 PINCTRL_PIN(75, "PWM3"),
816 "Y19", "mt8135",
817 MTK_EINT_FUNCTION(2, 75),
818 MTK_FUNCTION(0, "GPIO75"),
819 MTK_FUNCTION(1, "PWM3"),
820 MTK_FUNCTION(2, "EINT75"),
821 MTK_FUNCTION(3, "DPI33_D0"),
822 MTK_FUNCTION(4, "PWM6"),
823 MTK_FUNCTION(5, "UTXD2"),
824 MTK_FUNCTION(6, "DISP_PWM"),
825 MTK_FUNCTION(7, "TESTB_OUT12")
826 ),
827 MTK_PIN(
828 PINCTRL_PIN(76, "PWM4"),
829 "W19", "mt8135",
830 MTK_EINT_FUNCTION(2, 76),
831 MTK_FUNCTION(0, "GPIO76"),
832 MTK_FUNCTION(1, "PWM4"),
833 MTK_FUNCTION(2, "EINT76"),
834 MTK_FUNCTION(3, "DPI33_D1"),
835 MTK_FUNCTION(4, "PWM7"),
836 MTK_FUNCTION(6, "DISP_PWM"),
837 MTK_FUNCTION(7, "TESTB_OUT13")
838 ),
839 MTK_PIN(
840 PINCTRL_PIN(77, "MSDC2_DAT2"),
841 "W21", "mt8135",
842 MTK_EINT_FUNCTION(2, 63),
843 MTK_FUNCTION(0, "GPIO77"),
844 MTK_FUNCTION(1, "MSDC2_DAT2"),
845 MTK_FUNCTION(2, "EINT63"),
846 MTK_FUNCTION(4, "DSP2_IMS"),
847 MTK_FUNCTION(6, "DPI33_D6"),
848 MTK_FUNCTION(7, "TESTA_OUT25")
849 ),
850 MTK_PIN(
851 PINCTRL_PIN(78, "MSDC2_DAT3"),
852 "AA23", "mt8135",
853 MTK_EINT_FUNCTION(2, 64),
854 MTK_FUNCTION(0, "GPIO78"),
855 MTK_FUNCTION(1, "MSDC2_DAT3"),
856 MTK_FUNCTION(2, "EINT64"),
857 MTK_FUNCTION(4, "DSP2_ID"),
858 MTK_FUNCTION(6, "DPI33_D7"),
859 MTK_FUNCTION(7, "TESTA_OUT26")
860 ),
861 MTK_PIN(
862 PINCTRL_PIN(79, "MSDC2_CMD"),
863 "Y22", "mt8135",
864 MTK_EINT_FUNCTION(2, 60),
865 MTK_FUNCTION(0, "GPIO79"),
866 MTK_FUNCTION(1, "MSDC2_CMD"),
867 MTK_FUNCTION(2, "EINT60"),
868 MTK_FUNCTION(4, "DSP1_IMS"),
869 MTK_FUNCTION(5, "PCM1_WS"),
870 MTK_FUNCTION(6, "DPI33_D3"),
871 MTK_FUNCTION(7, "TESTA_OUT0")
872 ),
873 MTK_PIN(
874 PINCTRL_PIN(80, "MSDC2_CLK"),
875 "AA22", "mt8135",
876 MTK_EINT_FUNCTION(2, 59),
877 MTK_FUNCTION(0, "GPIO80"),
878 MTK_FUNCTION(1, "MSDC2_CLK"),
879 MTK_FUNCTION(2, "EINT59"),
880 MTK_FUNCTION(4, "DSP1_ICK"),
881 MTK_FUNCTION(5, "PCM1_CK"),
882 MTK_FUNCTION(6, "DPI33_D2"),
883 MTK_FUNCTION(7, "TESTA_OUT1")
884 ),
885 MTK_PIN(
886 PINCTRL_PIN(81, "MSDC2_DAT1"),
887 "Y21", "mt8135",
888 MTK_EINT_FUNCTION(2, 62),
889 MTK_FUNCTION(0, "GPIO81"),
890 MTK_FUNCTION(1, "MSDC2_DAT1"),
891 MTK_FUNCTION(2, "EINT62"),
892 MTK_FUNCTION(4, "DSP2_ICK"),
893 MTK_FUNCTION(5, "PCM1_DO"),
894 MTK_FUNCTION(6, "DPI33_D5")
895 ),
896 MTK_PIN(
897 PINCTRL_PIN(82, "MSDC2_DAT0"),
898 "AB22", "mt8135",
899 MTK_EINT_FUNCTION(2, 61),
900 MTK_FUNCTION(0, "GPIO82"),
901 MTK_FUNCTION(1, "MSDC2_DAT0"),
902 MTK_FUNCTION(2, "EINT61"),
903 MTK_FUNCTION(4, "DSP1_ID"),
904 MTK_FUNCTION(5, "PCM1_DI"),
905 MTK_FUNCTION(6, "DPI33_D4")
906 ),
907 MTK_PIN(
908 PINCTRL_PIN(83, "MSDC1_DAT0"),
909 "AC19", "mt8135",
910 MTK_EINT_FUNCTION(2, 53),
911 MTK_FUNCTION(0, "GPIO83"),
912 MTK_FUNCTION(1, "MSDC1_DAT0"),
913 MTK_FUNCTION(2, "EINT53"),
914 MTK_FUNCTION(3, "SCL1"),
915 MTK_FUNCTION(4, "PWM2"),
916 MTK_FUNCTION(5, "CLKM1"),
917 MTK_FUNCTION(7, "TESTB_OUT2")
918 ),
919 MTK_PIN(
920 PINCTRL_PIN(84, "MSDC1_DAT1"),
921 "AA19", "mt8135",
922 MTK_EINT_FUNCTION(2, 54),
923 MTK_FUNCTION(0, "GPIO84"),
924 MTK_FUNCTION(1, "MSDC1_DAT1"),
925 MTK_FUNCTION(2, "EINT54"),
926 MTK_FUNCTION(3, "SDA1"),
927 MTK_FUNCTION(4, "PWM3"),
928 MTK_FUNCTION(5, "CLKM2"),
929 MTK_FUNCTION(7, "TESTB_OUT3")
930 ),
931 MTK_PIN(
932 PINCTRL_PIN(85, "MSDC1_CMD"),
933 "AA20", "mt8135",
934 MTK_EINT_FUNCTION(2, 52),
935 MTK_FUNCTION(0, "GPIO85"),
936 MTK_FUNCTION(1, "MSDC1_CMD"),
937 MTK_FUNCTION(2, "EINT52"),
938 MTK_FUNCTION(3, "SDA0"),
939 MTK_FUNCTION(4, "PWM1"),
940 MTK_FUNCTION(5, "CLKM0"),
941 MTK_FUNCTION(7, "TESTB_OUT1")
942 ),
943 MTK_PIN(
944 PINCTRL_PIN(86, "MSDC1_CLK"),
945 "AB19", "mt8135",
946 MTK_EINT_FUNCTION(2, 51),
947 MTK_FUNCTION(0, "GPIO86"),
948 MTK_FUNCTION(1, "MSDC1_CLK"),
949 MTK_FUNCTION(2, "EINT51"),
950 MTK_FUNCTION(3, "SCL0"),
951 MTK_FUNCTION(4, "DISP_PWM"),
952 MTK_FUNCTION(7, "TESTB_OUT0")
953 ),
954 MTK_PIN(
955 PINCTRL_PIN(87, "MSDC1_DAT2"),
956 "AA21", "mt8135",
957 MTK_EINT_FUNCTION(2, 55),
958 MTK_FUNCTION(0, "GPIO87"),
959 MTK_FUNCTION(1, "MSDC1_DAT2"),
960 MTK_FUNCTION(2, "EINT55"),
961 MTK_FUNCTION(3, "SCL4"),
962 MTK_FUNCTION(4, "PWM4"),
963 MTK_FUNCTION(5, "CLKM3"),
964 MTK_FUNCTION(7, "TESTB_OUT4")
965 ),
966 MTK_PIN(
967 PINCTRL_PIN(88, "MSDC1_DAT3"),
968 "AB20", "mt8135",
969 MTK_EINT_FUNCTION(2, 56),
970 MTK_FUNCTION(0, "GPIO88"),
971 MTK_FUNCTION(1, "MSDC1_DAT3"),
972 MTK_FUNCTION(2, "EINT56"),
973 MTK_FUNCTION(3, "SDA4"),
974 MTK_FUNCTION(4, "PWM5"),
975 MTK_FUNCTION(5, "CLKM4"),
976 MTK_FUNCTION(7, "TESTB_OUT5")
977 ),
978 MTK_PIN(
979 PINCTRL_PIN(89, "MSDC4_DAT0"),
980 "AB8", "mt8135",
981 MTK_EINT_FUNCTION(2, 133),
982 MTK_FUNCTION(0, "GPIO89"),
983 MTK_FUNCTION(1, "MSDC4_DAT0"),
984 MTK_FUNCTION(2, "EINT133"),
985 MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
986 MTK_FUNCTION(5, "USB_DRVVBUS"),
987 MTK_FUNCTION(6, "A_FUNC_DIN[9]"),
988 MTK_FUNCTION(7, "LPTE")
989 ),
990 MTK_PIN(
991 PINCTRL_PIN(90, "MSDC4_DAT1"),
992 "AB7", "mt8135",
993 MTK_EINT_FUNCTION(2, 134),
994 MTK_FUNCTION(0, "GPIO90"),
995 MTK_FUNCTION(1, "MSDC4_DAT1"),
996 MTK_FUNCTION(2, "EINT134"),
997 MTK_FUNCTION(6, "A_FUNC_DIN[10]"),
998 MTK_FUNCTION(7, "LRSTB_1X")
999 ),
1000 MTK_PIN(
1001 PINCTRL_PIN(91, "MSDC4_DAT5"),
1002 "AA8", "mt8135",
1003 MTK_EINT_FUNCTION(2, 136),
1004 MTK_FUNCTION(0, "GPIO91"),
1005 MTK_FUNCTION(1, "MSDC4_DAT5"),
1006 MTK_FUNCTION(2, "EINT136"),
1007 MTK_FUNCTION(3, "I2SIN_WS"),
1008 MTK_FUNCTION(4, "DAC_WS"),
1009 MTK_FUNCTION(5, "PCM1_WS"),
1010 MTK_FUNCTION(6, "A_FUNC_DIN[11]"),
1011 MTK_FUNCTION(7, "SPI1_CSN")
1012 ),
1013 MTK_PIN(
1014 PINCTRL_PIN(92, "MSDC4_DAT6"),
1015 "AC4", "mt8135",
1016 MTK_EINT_FUNCTION(2, 137),
1017 MTK_FUNCTION(0, "GPIO92"),
1018 MTK_FUNCTION(1, "MSDC4_DAT6"),
1019 MTK_FUNCTION(2, "EINT137"),
1020 MTK_FUNCTION(3, "I2SOUT_DAT"),
1021 MTK_FUNCTION(4, "DAC_DAT_OUT"),
1022 MTK_FUNCTION(5, "PCM1_DO"),
1023 MTK_FUNCTION(6, "A_FUNC_DIN[12]"),
1024 MTK_FUNCTION(7, "SPI1_MO")
1025 ),
1026 MTK_PIN(
1027 PINCTRL_PIN(93, "MSDC4_DAT7"),
1028 "AC6", "mt8135",
1029 MTK_EINT_FUNCTION(2, 138),
1030 MTK_FUNCTION(0, "GPIO93"),
1031 MTK_FUNCTION(1, "MSDC4_DAT7"),
1032 MTK_FUNCTION(2, "EINT138"),
1033 MTK_FUNCTION(3, "I2SIN_DAT"),
1034 MTK_FUNCTION(5, "PCM1_DI"),
1035 MTK_FUNCTION(6, "A_FUNC_DIN[13]"),
1036 MTK_FUNCTION(7, "SPI1_MI")
1037 ),
1038 MTK_PIN(
1039 PINCTRL_PIN(94, "MSDC4_DAT4"),
1040 "AA7", "mt8135",
1041 MTK_EINT_FUNCTION(2, 135),
1042 MTK_FUNCTION(0, "GPIO94"),
1043 MTK_FUNCTION(1, "MSDC4_DAT4"),
1044 MTK_FUNCTION(2, "EINT135"),
1045 MTK_FUNCTION(3, "I2SIN_CK"),
1046 MTK_FUNCTION(4, "DAC_CK"),
1047 MTK_FUNCTION(5, "PCM1_CK"),
1048 MTK_FUNCTION(6, "A_FUNC_DIN[14]"),
1049 MTK_FUNCTION(7, "SPI1_CLK")
1050 ),
1051 MTK_PIN(
1052 PINCTRL_PIN(95, "MSDC4_DAT2"),
1053 "AB6", "mt8135",
1054 MTK_EINT_FUNCTION(2, 131),
1055 MTK_FUNCTION(0, "GPIO95"),
1056 MTK_FUNCTION(1, "MSDC4_DAT2"),
1057 MTK_FUNCTION(2, "EINT131"),
1058 MTK_FUNCTION(3, "I2SIN_WS"),
1059 MTK_FUNCTION(4, "CM2PDN_2X"),
1060 MTK_FUNCTION(5, "DAC_WS"),
1061 MTK_FUNCTION(6, "PCM1_WS"),
1062 MTK_FUNCTION(7, "LSCE0B_1X")
1063 ),
1064 MTK_PIN(
1065 PINCTRL_PIN(96, "MSDC4_CLK"),
1066 "AB5", "mt8135",
1067 MTK_EINT_FUNCTION(2, 129),
1068 MTK_FUNCTION(0, "GPIO96"),
1069 MTK_FUNCTION(1, "MSDC4_CLK"),
1070 MTK_FUNCTION(2, "EINT129"),
1071 MTK_FUNCTION(3, "DPI1_CK_2X"),
1072 MTK_FUNCTION(4, "CM2PCLK_2X"),
1073 MTK_FUNCTION(5, "PWM4"),
1074 MTK_FUNCTION(6, "PCM1_DI"),
1075 MTK_FUNCTION(7, "LSCK_1X")
1076 ),
1077 MTK_PIN(
1078 PINCTRL_PIN(97, "MSDC4_DAT3"),
1079 "Y8", "mt8135",
1080 MTK_EINT_FUNCTION(2, 132),
1081 MTK_FUNCTION(0, "GPIO97"),
1082 MTK_FUNCTION(1, "MSDC4_DAT3"),
1083 MTK_FUNCTION(2, "EINT132"),
1084 MTK_FUNCTION(3, "I2SOUT_DAT"),
1085 MTK_FUNCTION(4, "CM2RST_2X"),
1086 MTK_FUNCTION(5, "DAC_DAT_OUT"),
1087 MTK_FUNCTION(6, "PCM1_DO"),
1088 MTK_FUNCTION(7, "LSCE1B_1X")
1089 ),
1090 MTK_PIN(
1091 PINCTRL_PIN(98, "MSDC4_CMD"),
1092 "AC3", "mt8135",
1093 MTK_EINT_FUNCTION(2, 128),
1094 MTK_FUNCTION(0, "GPIO98"),
1095 MTK_FUNCTION(1, "MSDC4_CMD"),
1096 MTK_FUNCTION(2, "EINT128"),
1097 MTK_FUNCTION(3, "DPI1_DE_2X"),
1098 MTK_FUNCTION(5, "PWM3"),
1099 MTK_FUNCTION(7, "LSDA_1X")
1100 ),
1101 MTK_PIN(
1102 PINCTRL_PIN(99, "MSDC4_RSTB"),
1103 "AB4", "mt8135",
1104 MTK_EINT_FUNCTION(2, 130),
1105 MTK_FUNCTION(0, "GPIO99"),
1106 MTK_FUNCTION(1, "MSDC4_RSTB"),
1107 MTK_FUNCTION(2, "EINT130"),
1108 MTK_FUNCTION(3, "I2SIN_CK"),
1109 MTK_FUNCTION(4, "CM2MCLK_2X"),
1110 MTK_FUNCTION(5, "DAC_CK"),
1111 MTK_FUNCTION(6, "PCM1_CK"),
1112 MTK_FUNCTION(7, "LSA0_1X")
1113 ),
1114 MTK_PIN(
1115 PINCTRL_PIN(100, "SDA0"),
1116 "W9", "mt8135",
1117 MTK_EINT_FUNCTION(2, 91),
1118 MTK_FUNCTION(0, "GPIO100"),
1119 MTK_FUNCTION(1, "SDA0"),
1120 MTK_FUNCTION(2, "EINT91"),
1121 MTK_FUNCTION(3, "CLKM1"),
1122 MTK_FUNCTION(4, "PWM1"),
1123 MTK_FUNCTION(7, "A_FUNC_DIN[15]")
1124 ),
1125 MTK_PIN(
1126 PINCTRL_PIN(101, "SCL0"),
1127 "W11", "mt8135",
1128 MTK_EINT_FUNCTION(2, 90),
1129 MTK_FUNCTION(0, "GPIO101"),
1130 MTK_FUNCTION(1, "SCL0"),
1131 MTK_FUNCTION(2, "EINT90"),
1132 MTK_FUNCTION(3, "CLKM0"),
1133 MTK_FUNCTION(4, "DISP_PWM"),
1134 MTK_FUNCTION(7, "A_FUNC_DIN[16]")
1135 ),
1136 MTK_PIN(
1137 PINCTRL_PIN(102, "EINT10_AUXIN2"),
1138 "AA3", "mt8135",
1139 MTK_EINT_FUNCTION(1, 10),
1140 MTK_FUNCTION(0, "GPIO102"),
1141 MTK_FUNCTION(1, "EINT10"),
1142 MTK_FUNCTION(5, "USB_TEST_IO[16]"),
1143 MTK_FUNCTION(6, "TESTB_OUT16"),
1144 MTK_FUNCTION(7, "A_FUNC_DIN[17]")
1145 ),
1146 MTK_PIN(
1147 PINCTRL_PIN(103, "EINT11_AUXIN3"),
1148 "AB2", "mt8135",
1149 MTK_EINT_FUNCTION(1, 11),
1150 MTK_FUNCTION(0, "GPIO103"),
1151 MTK_FUNCTION(1, "EINT11"),
1152 MTK_FUNCTION(5, "USB_TEST_IO[17]"),
1153 MTK_FUNCTION(6, "TESTB_OUT17"),
1154 MTK_FUNCTION(7, "A_FUNC_DIN[18]")
1155 ),
1156 MTK_PIN(
1157 PINCTRL_PIN(104, "EINT16_AUXIN4"),
1158 "AB3", "mt8135",
1159 MTK_EINT_FUNCTION(1, 16),
1160 MTK_FUNCTION(0, "GPIO104"),
1161 MTK_FUNCTION(1, "EINT16"),
1162 MTK_FUNCTION(5, "USB_TEST_IO[18]"),
1163 MTK_FUNCTION(6, "TESTB_OUT18"),
1164 MTK_FUNCTION(7, "A_FUNC_DIN[19]")
1165 ),
1166 MTK_PIN(
1167 PINCTRL_PIN(105, "I2S_CLK"),
1168 "W6", "mt8135",
1169 MTK_EINT_FUNCTION(2, 10),
1170 MTK_FUNCTION(0, "GPIO105"),
1171 MTK_FUNCTION(1, "I2SIN_CK"),
1172 MTK_FUNCTION(2, "EINT10"),
1173 MTK_FUNCTION(3, "DAC_CK"),
1174 MTK_FUNCTION(4, "PCM1_CK"),
1175 MTK_FUNCTION(5, "USB_TEST_IO[19]"),
1176 MTK_FUNCTION(6, "TESTB_OUT19"),
1177 MTK_FUNCTION(7, "A_FUNC_DIN[20]")
1178 ),
1179 MTK_PIN(
1180 PINCTRL_PIN(106, "I2S_WS"),
1181 "AA6", "mt8135",
1182 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1183 MTK_FUNCTION(0, "GPIO106"),
1184 MTK_FUNCTION(1, "I2SIN_WS"),
1185 MTK_FUNCTION(3, "DAC_WS"),
1186 MTK_FUNCTION(4, "PCM1_WS"),
1187 MTK_FUNCTION(5, "USB_TEST_IO[20]"),
1188 MTK_FUNCTION(6, "TESTB_OUT20"),
1189 MTK_FUNCTION(7, "A_FUNC_DIN[21]")
1190 ),
1191 MTK_PIN(
1192 PINCTRL_PIN(107, "I2S_DATA_IN"),
1193 "AA5", "mt8135",
1194 MTK_EINT_FUNCTION(2, 11),
1195 MTK_FUNCTION(0, "GPIO107"),
1196 MTK_FUNCTION(1, "I2SIN_DAT"),
1197 MTK_FUNCTION(2, "EINT11"),
1198 MTK_FUNCTION(4, "PCM1_DI"),
1199 MTK_FUNCTION(5, "USB_TEST_IO[21]"),
1200 MTK_FUNCTION(6, "TESTB_OUT22"),
1201 MTK_FUNCTION(7, "A_FUNC_DIN[22]")
1202 ),
1203 MTK_PIN(
1204 PINCTRL_PIN(108, "I2S_DATA_OUT"),
1205 "AA4", "mt8135",
1206 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1207 MTK_FUNCTION(0, "GPIO108"),
1208 MTK_FUNCTION(1, "I2SOUT_DAT"),
1209 MTK_FUNCTION(3, "DAC_DAT_OUT"),
1210 MTK_FUNCTION(4, "PCM1_DO"),
1211 MTK_FUNCTION(5, "USB_TEST_IO[22]"),
1212 MTK_FUNCTION(6, "TESTB_OUT23"),
1213 MTK_FUNCTION(7, "A_FUNC_DIN[23]")
1214 ),
1215 MTK_PIN(
1216 PINCTRL_PIN(109, "EINT5"),
1217 "W5", "mt8135",
1218 MTK_EINT_FUNCTION(1, 5),
1219 MTK_FUNCTION(0, "GPIO109"),
1220 MTK_FUNCTION(1, "EINT5"),
1221 MTK_FUNCTION(2, "PWM5"),
1222 MTK_FUNCTION(3, "CLKM3"),
1223 MTK_FUNCTION(4, "GPU_JTRSTB"),
1224 MTK_FUNCTION(5, "USB_TEST_IO[23]"),
1225 MTK_FUNCTION(6, "TESTB_OUT26"),
1226 MTK_FUNCTION(7, "A_FUNC_DIN[24]")
1227 ),
1228 MTK_PIN(
1229 PINCTRL_PIN(110, "EINT6"),
1230 "V5", "mt8135",
1231 MTK_EINT_FUNCTION(1, 6),
1232 MTK_FUNCTION(0, "GPIO110"),
1233 MTK_FUNCTION(1, "EINT6"),
1234 MTK_FUNCTION(2, "PWM6"),
1235 MTK_FUNCTION(3, "CLKM4"),
1236 MTK_FUNCTION(4, "GPU_JTMS"),
1237 MTK_FUNCTION(5, "USB_TEST_IO[24]"),
1238 MTK_FUNCTION(6, "TESTB_OUT27"),
1239 MTK_FUNCTION(7, "A_FUNC_DIN[25]")
1240 ),
1241 MTK_PIN(
1242 PINCTRL_PIN(111, "EINT7"),
1243 "W3", "mt8135",
1244 MTK_EINT_FUNCTION(1, 7),
1245 MTK_FUNCTION(0, "GPIO111"),
1246 MTK_FUNCTION(1, "EINT7"),
1247 MTK_FUNCTION(2, "PWM7"),
1248 MTK_FUNCTION(3, "CLKM5"),
1249 MTK_FUNCTION(4, "GPU_JTDO"),
1250 MTK_FUNCTION(5, "USB_TEST_IO[25]"),
1251 MTK_FUNCTION(6, "TESTB_OUT28"),
1252 MTK_FUNCTION(7, "A_FUNC_DIN[26]")
1253 ),
1254 MTK_PIN(
1255 PINCTRL_PIN(112, "EINT8"),
1256 "V6", "mt8135",
1257 MTK_EINT_FUNCTION(1, 8),
1258 MTK_FUNCTION(0, "GPIO112"),
1259 MTK_FUNCTION(1, "EINT8"),
1260 MTK_FUNCTION(2, "DISP_PWM"),
1261 MTK_FUNCTION(3, "CLKM6"),
1262 MTK_FUNCTION(4, "GPU_JTDI"),
1263 MTK_FUNCTION(5, "USB_TEST_IO[26]"),
1264 MTK_FUNCTION(6, "TESTB_OUT29"),
1265 MTK_FUNCTION(7, "EXT_FRAME_SYNC")
1266 ),
1267 MTK_PIN(
1268 PINCTRL_PIN(113, "EINT9"),
1269 "W8", "mt8135",
1270 MTK_EINT_FUNCTION(1, 9),
1271 MTK_FUNCTION(0, "GPIO113"),
1272 MTK_FUNCTION(1, "EINT9"),
1273 MTK_FUNCTION(4, "GPU_JTCK"),
1274 MTK_FUNCTION(5, "USB_DRVVBUS"),
1275 MTK_FUNCTION(6, "TESTB_OUT30"),
1276 MTK_FUNCTION(7, "A_FUNC_DIN[27]")
1277 ),
1278 MTK_PIN(
1279 PINCTRL_PIN(114, "LPCE1B"),
1280 "W4", "mt8135",
1281 MTK_EINT_FUNCTION(2, 127),
1282 MTK_FUNCTION(0, "GPIO114"),
1283 MTK_FUNCTION(1, "LPCE1B"),
1284 MTK_FUNCTION(2, "EINT127"),
1285 MTK_FUNCTION(5, "PWM2"),
1286 MTK_FUNCTION(6, "TESTB_OUT14"),
1287 MTK_FUNCTION(7, "A_FUNC_DIN[28]")
1288 ),
1289 MTK_PIN(
1290 PINCTRL_PIN(115, "LPCE0B"),
1291 "T5", "mt8135",
1292 MTK_EINT_FUNCTION(2, 126),
1293 MTK_FUNCTION(0, "GPIO115"),
1294 MTK_FUNCTION(1, "LPCE0B"),
1295 MTK_FUNCTION(2, "EINT126"),
1296 MTK_FUNCTION(5, "PWM1"),
1297 MTK_FUNCTION(6, "TESTB_OUT15"),
1298 MTK_FUNCTION(7, "A_FUNC_DIN[29]")
1299 ),
1300 MTK_PIN(
1301 PINCTRL_PIN(116, "DISP_PWM"),
1302 "V4", "mt8135",
1303 MTK_EINT_FUNCTION(2, 77),
1304 MTK_FUNCTION(0, "GPIO116"),
1305 MTK_FUNCTION(1, "DISP_PWM"),
1306 MTK_FUNCTION(2, "EINT77"),
1307 MTK_FUNCTION(3, "LSDI"),
1308 MTK_FUNCTION(4, "PWM1"),
1309 MTK_FUNCTION(5, "PWM2"),
1310 MTK_FUNCTION(7, "PWM3")
1311 ),
1312 MTK_PIN(
1313 PINCTRL_PIN(117, "EINT1"),
1314 "T6", "mt8135",
1315 MTK_EINT_FUNCTION(1, 1),
1316 MTK_FUNCTION(0, "GPIO117"),
1317 MTK_FUNCTION(1, "EINT1"),
1318 MTK_FUNCTION(2, "PWM2"),
1319 MTK_FUNCTION(3, "CLKM1"),
1320 MTK_FUNCTION(5, "USB_TEST_IO[13]"),
1321 MTK_FUNCTION(7, "USB_SDA")
1322 ),
1323 MTK_PIN(
1324 PINCTRL_PIN(118, "EINT2"),
1325 "T4", "mt8135",
1326 MTK_EINT_FUNCTION(1, 2),
1327 MTK_FUNCTION(0, "GPIO118"),
1328 MTK_FUNCTION(1, "EINT2"),
1329 MTK_FUNCTION(2, "PWM3"),
1330 MTK_FUNCTION(3, "CLKM2"),
1331 MTK_FUNCTION(5, "USB_TEST_IO[14]"),
1332 MTK_FUNCTION(6, "SRCLKENAI2"),
1333 MTK_FUNCTION(7, "A_FUNC_DIN[30]")
1334 ),
1335 MTK_PIN(
1336 PINCTRL_PIN(119, "EINT3"),
1337 "R4", "mt8135",
1338 MTK_EINT_FUNCTION(1, 3),
1339 MTK_FUNCTION(0, "GPIO119"),
1340 MTK_FUNCTION(1, "EINT3"),
1341 MTK_FUNCTION(5, "USB_TEST_IO[15]"),
1342 MTK_FUNCTION(6, "SRCLKENAI1"),
1343 MTK_FUNCTION(7, "EXT_26M_CK")
1344 ),
1345 MTK_PIN(
1346 PINCTRL_PIN(120, "EINT4"),
1347 "R5", "mt8135",
1348 MTK_EINT_FUNCTION(1, 4),
1349 MTK_FUNCTION(0, "GPIO120"),
1350 MTK_FUNCTION(1, "EINT4"),
1351 MTK_FUNCTION(2, "PWM4"),
1352 MTK_FUNCTION(5, "USB_DRVVBUS"),
1353 MTK_FUNCTION(7, "A_FUNC_DIN[31]")
1354 ),
1355 MTK_PIN(
1356 PINCTRL_PIN(121, "DPIDE"),
1357 NULL, "mt8135",
1358 MTK_EINT_FUNCTION(2, 100),
1359 MTK_FUNCTION(0, "GPIO121"),
1360 MTK_FUNCTION(1, "DPI0_DE"),
1361 MTK_FUNCTION(2, "EINT100"),
1362 MTK_FUNCTION(3, "I2SOUT_DAT"),
1363 MTK_FUNCTION(4, "DAC_DAT_OUT"),
1364 MTK_FUNCTION(5, "PCM1_DO"),
1365 MTK_FUNCTION(6, "IRDA_TXD")
1366 ),
1367 MTK_PIN(
1368 PINCTRL_PIN(122, "DPICK"),
1369 NULL, "mt8135",
1370 MTK_EINT_FUNCTION(2, 101),
1371 MTK_FUNCTION(0, "GPIO122"),
1372 MTK_FUNCTION(1, "DPI0_CK"),
1373 MTK_FUNCTION(2, "EINT101"),
1374 MTK_FUNCTION(3, "I2SIN_DAT"),
1375 MTK_FUNCTION(5, "PCM1_DI"),
1376 MTK_FUNCTION(6, "IRDA_PDN")
1377 ),
1378 MTK_PIN(
1379 PINCTRL_PIN(123, "DPIG4"),
1380 NULL, "mt8135",
1381 MTK_EINT_FUNCTION(2, 114),
1382 MTK_FUNCTION(0, "GPIO123"),
1383 MTK_FUNCTION(1, "DPI0_G4"),
1384 MTK_FUNCTION(2, "EINT114"),
1385 MTK_FUNCTION(4, "CM2DAT_2X[0]"),
1386 MTK_FUNCTION(5, "DSP2_ID")
1387 ),
1388 MTK_PIN(
1389 PINCTRL_PIN(124, "DPIG5"),
1390 NULL, "mt8135",
1391 MTK_EINT_FUNCTION(2, 115),
1392 MTK_FUNCTION(0, "GPIO124"),
1393 MTK_FUNCTION(1, "DPI0_G5"),
1394 MTK_FUNCTION(2, "EINT115"),
1395 MTK_FUNCTION(4, "CM2DAT_2X[1]"),
1396 MTK_FUNCTION(5, "DSP2_ICK")
1397 ),
1398 MTK_PIN(
1399 PINCTRL_PIN(125, "DPIR3"),
1400 NULL, "mt8135",
1401 MTK_EINT_FUNCTION(2, 121),
1402 MTK_FUNCTION(0, "GPIO125"),
1403 MTK_FUNCTION(1, "DPI0_R3"),
1404 MTK_FUNCTION(2, "EINT121"),
1405 MTK_FUNCTION(4, "CM2DAT_2X[7]")
1406 ),
1407 MTK_PIN(
1408 PINCTRL_PIN(126, "DPIG1"),
1409 NULL, "mt8135",
1410 MTK_EINT_FUNCTION(2, 111),
1411 MTK_FUNCTION(0, "GPIO126"),
1412 MTK_FUNCTION(1, "DPI0_G1"),
1413 MTK_FUNCTION(2, "EINT111"),
1414 MTK_FUNCTION(5, "DSP1_ICK")
1415 ),
1416 MTK_PIN(
1417 PINCTRL_PIN(127, "DPIVSYNC"),
1418 NULL, "mt8135",
1419 MTK_EINT_FUNCTION(2, 98),
1420 MTK_FUNCTION(0, "GPIO127"),
1421 MTK_FUNCTION(1, "DPI0_VSYNC"),
1422 MTK_FUNCTION(2, "EINT98"),
1423 MTK_FUNCTION(3, "I2SIN_CK"),
1424 MTK_FUNCTION(4, "DAC_CK"),
1425 MTK_FUNCTION(5, "PCM1_CK")
1426 ),
1427 MTK_PIN(
1428 PINCTRL_PIN(128, "DPIHSYNC"),
1429 NULL, "mt8135",
1430 MTK_EINT_FUNCTION(2, 99),
1431 MTK_FUNCTION(0, "GPIO128"),
1432 MTK_FUNCTION(1, "DPI0_HSYNC"),
1433 MTK_FUNCTION(2, "EINT99"),
1434 MTK_FUNCTION(3, "I2SIN_WS"),
1435 MTK_FUNCTION(4, "DAC_WS"),
1436 MTK_FUNCTION(5, "PCM1_WS"),
1437 MTK_FUNCTION(6, "IRDA_RXD")
1438 ),
1439 MTK_PIN(
1440 PINCTRL_PIN(129, "DPIB0"),
1441 NULL, "mt8135",
1442 MTK_EINT_FUNCTION(2, 102),
1443 MTK_FUNCTION(0, "GPIO129"),
1444 MTK_FUNCTION(1, "DPI0_B0"),
1445 MTK_FUNCTION(2, "EINT102"),
1446 MTK_FUNCTION(4, "SCL0"),
1447 MTK_FUNCTION(5, "DISP_PWM")
1448 ),
1449 MTK_PIN(
1450 PINCTRL_PIN(130, "DPIB1"),
1451 NULL, "mt8135",
1452 MTK_EINT_FUNCTION(2, 103),
1453 MTK_FUNCTION(0, "GPIO130"),
1454 MTK_FUNCTION(1, "DPI0_B1"),
1455 MTK_FUNCTION(2, "EINT103"),
1456 MTK_FUNCTION(3, "CLKM0"),
1457 MTK_FUNCTION(4, "SDA0"),
1458 MTK_FUNCTION(5, "PWM1")
1459 ),
1460 MTK_PIN(
1461 PINCTRL_PIN(131, "DPIB2"),
1462 NULL, "mt8135",
1463 MTK_EINT_FUNCTION(2, 104),
1464 MTK_FUNCTION(0, "GPIO131"),
1465 MTK_FUNCTION(1, "DPI0_B2"),
1466 MTK_FUNCTION(2, "EINT104"),
1467 MTK_FUNCTION(3, "CLKM1"),
1468 MTK_FUNCTION(4, "SCL1"),
1469 MTK_FUNCTION(5, "PWM2")
1470 ),
1471 MTK_PIN(
1472 PINCTRL_PIN(132, "DPIB3"),
1473 NULL, "mt8135",
1474 MTK_EINT_FUNCTION(2, 105),
1475 MTK_FUNCTION(0, "GPIO132"),
1476 MTK_FUNCTION(1, "DPI0_B3"),
1477 MTK_FUNCTION(2, "EINT105"),
1478 MTK_FUNCTION(3, "CLKM2"),
1479 MTK_FUNCTION(4, "SDA1"),
1480 MTK_FUNCTION(5, "PWM3")
1481 ),
1482 MTK_PIN(
1483 PINCTRL_PIN(133, "DPIB4"),
1484 NULL, "mt8135",
1485 MTK_EINT_FUNCTION(2, 106),
1486 MTK_FUNCTION(0, "GPIO133"),
1487 MTK_FUNCTION(1, "DPI0_B4"),
1488 MTK_FUNCTION(2, "EINT106"),
1489 MTK_FUNCTION(3, "CLKM3"),
1490 MTK_FUNCTION(4, "SCL2"),
1491 MTK_FUNCTION(5, "PWM4")
1492 ),
1493 MTK_PIN(
1494 PINCTRL_PIN(134, "DPIB5"),
1495 NULL, "mt8135",
1496 MTK_EINT_FUNCTION(2, 107),
1497 MTK_FUNCTION(0, "GPIO134"),
1498 MTK_FUNCTION(1, "DPI0_B5"),
1499 MTK_FUNCTION(2, "EINT107"),
1500 MTK_FUNCTION(3, "CLKM4"),
1501 MTK_FUNCTION(4, "SDA2"),
1502 MTK_FUNCTION(5, "PWM5")
1503 ),
1504 MTK_PIN(
1505 PINCTRL_PIN(135, "DPIB6"),
1506 NULL, "mt8135",
1507 MTK_EINT_FUNCTION(2, 108),
1508 MTK_FUNCTION(0, "GPIO135"),
1509 MTK_FUNCTION(1, "DPI0_B6"),
1510 MTK_FUNCTION(2, "EINT108"),
1511 MTK_FUNCTION(3, "CLKM5"),
1512 MTK_FUNCTION(4, "SCL3"),
1513 MTK_FUNCTION(5, "PWM6")
1514 ),
1515 MTK_PIN(
1516 PINCTRL_PIN(136, "DPIB7"),
1517 NULL, "mt8135",
1518 MTK_EINT_FUNCTION(2, 109),
1519 MTK_FUNCTION(0, "GPIO136"),
1520 MTK_FUNCTION(1, "DPI0_B7"),
1521 MTK_FUNCTION(2, "EINT109"),
1522 MTK_FUNCTION(3, "CLKM6"),
1523 MTK_FUNCTION(4, "SDA3"),
1524 MTK_FUNCTION(5, "PWM7")
1525 ),
1526 MTK_PIN(
1527 PINCTRL_PIN(137, "DPIG0"),
1528 NULL, "mt8135",
1529 MTK_EINT_FUNCTION(2, 110),
1530 MTK_FUNCTION(0, "GPIO137"),
1531 MTK_FUNCTION(1, "DPI0_G0"),
1532 MTK_FUNCTION(2, "EINT110"),
1533 MTK_FUNCTION(5, "DSP1_ID")
1534 ),
1535 MTK_PIN(
1536 PINCTRL_PIN(138, "DPIG2"),
1537 NULL, "mt8135",
1538 MTK_EINT_FUNCTION(2, 112),
1539 MTK_FUNCTION(0, "GPIO138"),
1540 MTK_FUNCTION(1, "DPI0_G2"),
1541 MTK_FUNCTION(2, "EINT112"),
1542 MTK_FUNCTION(5, "DSP1_IMS")
1543 ),
1544 MTK_PIN(
1545 PINCTRL_PIN(139, "DPIG3"),
1546 NULL, "mt8135",
1547 MTK_EINT_FUNCTION(2, 113),
1548 MTK_FUNCTION(0, "GPIO139"),
1549 MTK_FUNCTION(1, "DPI0_G3"),
1550 MTK_FUNCTION(2, "EINT113"),
1551 MTK_FUNCTION(5, "DSP2_IMS")
1552 ),
1553 MTK_PIN(
1554 PINCTRL_PIN(140, "DPIG6"),
1555 NULL, "mt8135",
1556 MTK_EINT_FUNCTION(2, 116),
1557 MTK_FUNCTION(0, "GPIO140"),
1558 MTK_FUNCTION(1, "DPI0_G6"),
1559 MTK_FUNCTION(2, "EINT116"),
1560 MTK_FUNCTION(4, "CM2DAT_2X[2]")
1561 ),
1562 MTK_PIN(
1563 PINCTRL_PIN(141, "DPIG7"),
1564 NULL, "mt8135",
1565 MTK_EINT_FUNCTION(2, 117),
1566 MTK_FUNCTION(0, "GPIO141"),
1567 MTK_FUNCTION(1, "DPI0_G7"),
1568 MTK_FUNCTION(2, "EINT117"),
1569 MTK_FUNCTION(4, "CM2DAT_2X[3]")
1570 ),
1571 MTK_PIN(
1572 PINCTRL_PIN(142, "DPIR0"),
1573 NULL, "mt8135",
1574 MTK_EINT_FUNCTION(2, 118),
1575 MTK_FUNCTION(0, "GPIO142"),
1576 MTK_FUNCTION(1, "DPI0_R0"),
1577 MTK_FUNCTION(2, "EINT118"),
1578 MTK_FUNCTION(4, "CM2DAT_2X[4]")
1579 ),
1580 MTK_PIN(
1581 PINCTRL_PIN(143, "DPIR1"),
1582 NULL, "mt8135",
1583 MTK_EINT_FUNCTION(2, 119),
1584 MTK_FUNCTION(0, "GPIO143"),
1585 MTK_FUNCTION(1, "DPI0_R1"),
1586 MTK_FUNCTION(2, "EINT119"),
1587 MTK_FUNCTION(4, "CM2DAT_2X[5]")
1588 ),
1589 MTK_PIN(
1590 PINCTRL_PIN(144, "DPIR2"),
1591 NULL, "mt8135",
1592 MTK_EINT_FUNCTION(2, 120),
1593 MTK_FUNCTION(0, "GPIO144"),
1594 MTK_FUNCTION(1, "DPI0_R2"),
1595 MTK_FUNCTION(2, "EINT120"),
1596 MTK_FUNCTION(4, "CM2DAT_2X[6]")
1597 ),
1598 MTK_PIN(
1599 PINCTRL_PIN(145, "DPIR4"),
1600 NULL, "mt8135",
1601 MTK_EINT_FUNCTION(2, 122),
1602 MTK_FUNCTION(0, "GPIO145"),
1603 MTK_FUNCTION(1, "DPI0_R4"),
1604 MTK_FUNCTION(2, "EINT122"),
1605 MTK_FUNCTION(4, "CM2DAT_2X[8]")
1606 ),
1607 MTK_PIN(
1608 PINCTRL_PIN(146, "DPIR5"),
1609 NULL, "mt8135",
1610 MTK_EINT_FUNCTION(2, 123),
1611 MTK_FUNCTION(0, "GPIO146"),
1612 MTK_FUNCTION(1, "DPI0_R5"),
1613 MTK_FUNCTION(2, "EINT123"),
1614 MTK_FUNCTION(4, "CM2DAT_2X[9]")
1615 ),
1616 MTK_PIN(
1617 PINCTRL_PIN(147, "DPIR6"),
1618 NULL, "mt8135",
1619 MTK_EINT_FUNCTION(2, 124),
1620 MTK_FUNCTION(0, "GPIO147"),
1621 MTK_FUNCTION(1, "DPI0_R6"),
1622 MTK_FUNCTION(2, "EINT124"),
1623 MTK_FUNCTION(4, "CM2VSYNC_2X")
1624 ),
1625 MTK_PIN(
1626 PINCTRL_PIN(148, "DPIR7"),
1627 NULL, "mt8135",
1628 MTK_EINT_FUNCTION(2, 125),
1629 MTK_FUNCTION(0, "GPIO148"),
1630 MTK_FUNCTION(1, "DPI0_R7"),
1631 MTK_FUNCTION(2, "EINT125"),
1632 MTK_FUNCTION(4, "CM2HSYNC_2X")
1633 ),
1634 MTK_PIN(
1635 PINCTRL_PIN(149, "TDN3/LVDS(TDN3)"),
1636 "AA2", "mt8135",
1637 MTK_EINT_FUNCTION(2, 36),
1638 MTK_FUNCTION(0, "GPIO149"),
1639 MTK_FUNCTION(2, "EINT36")
1640 ),
1641 MTK_PIN(
1642 PINCTRL_PIN(150, "TDP3/LVDS(TDP3)"),
1643 "AA1", "mt8135",
1644 MTK_EINT_FUNCTION(2, 35),
1645 MTK_FUNCTION(0, "GPIO150"),
1646 MTK_FUNCTION(2, "EINT35")
1647 ),
1648 MTK_PIN(
1649 PINCTRL_PIN(151, "TDN2/LVDS(TCN)"),
1650 "Y2", "mt8135",
1651 MTK_EINT_FUNCTION(2, 169),
1652 MTK_FUNCTION(0, "GPIO151"),
1653 MTK_FUNCTION(2, "EINT169")
1654 ),
1655 MTK_PIN(
1656 PINCTRL_PIN(152, "TDP2/LVDS(TCP)"),
1657 "Y1", "mt8135",
1658 MTK_EINT_FUNCTION(2, 168),
1659 MTK_FUNCTION(0, "GPIO152"),
1660 MTK_FUNCTION(2, "EINT168")
1661 ),
1662 MTK_PIN(
1663 PINCTRL_PIN(153, "TCN/LVDS(TDN2)"),
1664 "W2", "mt8135",
1665 MTK_EINT_FUNCTION(2, 163),
1666 MTK_FUNCTION(0, "GPIO153"),
1667 MTK_FUNCTION(2, "EINT163")
1668 ),
1669 MTK_PIN(
1670 PINCTRL_PIN(154, "TCP/LVDS(TDP2)"),
1671 "W1", "mt8135",
1672 MTK_EINT_FUNCTION(2, 162),
1673 MTK_FUNCTION(0, "GPIO154"),
1674 MTK_FUNCTION(2, "EINT162")
1675 ),
1676 MTK_PIN(
1677 PINCTRL_PIN(155, "TDN1/LVDS(TDN1)"),
1678 "V3", "mt8135",
1679 MTK_EINT_FUNCTION(2, 167),
1680 MTK_FUNCTION(0, "GPIO155"),
1681 MTK_FUNCTION(2, "EINT167")
1682 ),
1683 MTK_PIN(
1684 PINCTRL_PIN(156, "TDP1/LVDS(TDP1)"),
1685 "V2", "mt8135",
1686 MTK_EINT_FUNCTION(2, 166),
1687 MTK_FUNCTION(0, "GPIO156"),
1688 MTK_FUNCTION(2, "EINT166")
1689 ),
1690 MTK_PIN(
1691 PINCTRL_PIN(157, "TDN0/LVDS(TDN0)"),
1692 "U3", "mt8135",
1693 MTK_EINT_FUNCTION(2, 165),
1694 MTK_FUNCTION(0, "GPIO157"),
1695 MTK_FUNCTION(2, "EINT165")
1696 ),
1697 MTK_PIN(
1698 PINCTRL_PIN(158, "TDP0/LVDS(TDP0)"),
1699 "U2", "mt8135",
1700 MTK_EINT_FUNCTION(2, 164),
1701 MTK_FUNCTION(0, "GPIO158"),
1702 MTK_FUNCTION(2, "EINT164")
1703 ),
1704 MTK_PIN(
1705 PINCTRL_PIN(159, "RDN3"),
1706 "N5", "mt8135",
1707 MTK_EINT_FUNCTION(2, 18),
1708 MTK_FUNCTION(0, "GPIO159"),
1709 MTK_FUNCTION(2, "EINT18")
1710 ),
1711 MTK_PIN(
1712 PINCTRL_PIN(160, "RDP3"),
1713 "N4", "mt8135",
1714 MTK_EINT_FUNCTION(2, 30),
1715 MTK_FUNCTION(0, "GPIO160"),
1716 MTK_FUNCTION(2, "EINT30")
1717 ),
1718 MTK_PIN(
1719 PINCTRL_PIN(161, "RDN2"),
1720 "T2", "mt8135",
1721 MTK_EINT_FUNCTION(2, 31),
1722 MTK_FUNCTION(0, "GPIO161"),
1723 MTK_FUNCTION(2, "EINT31")
1724 ),
1725 MTK_PIN(
1726 PINCTRL_PIN(162, "RDP2"),
1727 "T3", "mt8135",
1728 MTK_EINT_FUNCTION(2, 32),
1729 MTK_FUNCTION(0, "GPIO162"),
1730 MTK_FUNCTION(2, "EINT32")
1731 ),
1732 MTK_PIN(
1733 PINCTRL_PIN(163, "RCN"),
1734 "P2", "mt8135",
1735 MTK_EINT_FUNCTION(2, 33),
1736 MTK_FUNCTION(0, "GPIO163"),
1737 MTK_FUNCTION(2, "EINT33")
1738 ),
1739 MTK_PIN(
1740 PINCTRL_PIN(164, "RCP"),
1741 "P3", "mt8135",
1742 MTK_EINT_FUNCTION(2, 39),
1743 MTK_FUNCTION(0, "GPIO164"),
1744 MTK_FUNCTION(2, "EINT39")
1745 ),
1746 MTK_PIN(
1747 PINCTRL_PIN(165, "RDN1"),
1748 "R3", "mt8135",
1749 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1750 MTK_FUNCTION(0, "GPIO165")
1751 ),
1752 MTK_PIN(
1753 PINCTRL_PIN(166, "RDP1"),
1754 "R2", "mt8135",
1755 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1756 MTK_FUNCTION(0, "GPIO166")
1757 ),
1758 MTK_PIN(
1759 PINCTRL_PIN(167, "RDN0"),
1760 "N3", "mt8135",
1761 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1762 MTK_FUNCTION(0, "GPIO167")
1763 ),
1764 MTK_PIN(
1765 PINCTRL_PIN(168, "RDP0"),
1766 "N2", "mt8135",
1767 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1768 MTK_FUNCTION(0, "GPIO168")
1769 ),
1770 MTK_PIN(
1771 PINCTRL_PIN(169, "RDN1_A"),
1772 "M4", "mt8135",
1773 MTK_EINT_FUNCTION(2, 175),
1774 MTK_FUNCTION(0, "GPIO169"),
1775 MTK_FUNCTION(1, "CMDAT6"),
1776 MTK_FUNCTION(2, "EINT175")
1777 ),
1778 MTK_PIN(
1779 PINCTRL_PIN(170, "RDP1_A"),
1780 "M3", "mt8135",
1781 MTK_EINT_FUNCTION(2, 174),
1782 MTK_FUNCTION(0, "GPIO170"),
1783 MTK_FUNCTION(1, "CMDAT7"),
1784 MTK_FUNCTION(2, "EINT174")
1785 ),
1786 MTK_PIN(
1787 PINCTRL_PIN(171, "RCN_A"),
1788 "L3", "mt8135",
1789 MTK_EINT_FUNCTION(2, 171),
1790 MTK_FUNCTION(0, "GPIO171"),
1791 MTK_FUNCTION(1, "CMDAT8"),
1792 MTK_FUNCTION(2, "EINT171")
1793 ),
1794 MTK_PIN(
1795 PINCTRL_PIN(172, "RCP_A"),
1796 "L2", "mt8135",
1797 MTK_EINT_FUNCTION(2, 170),
1798 MTK_FUNCTION(0, "GPIO172"),
1799 MTK_FUNCTION(1, "CMDAT9"),
1800 MTK_FUNCTION(2, "EINT170")
1801 ),
1802 MTK_PIN(
1803 PINCTRL_PIN(173, "RDN0_A"),
1804 "M2", "mt8135",
1805 MTK_EINT_FUNCTION(2, 173),
1806 MTK_FUNCTION(0, "GPIO173"),
1807 MTK_FUNCTION(1, "CMHSYNC"),
1808 MTK_FUNCTION(2, "EINT173")
1809 ),
1810 MTK_PIN(
1811 PINCTRL_PIN(174, "RDP0_A"),
1812 "M1", "mt8135",
1813 MTK_EINT_FUNCTION(2, 172),
1814 MTK_FUNCTION(0, "GPIO174"),
1815 MTK_FUNCTION(1, "CMVSYNC"),
1816 MTK_FUNCTION(2, "EINT172")
1817 ),
1818 MTK_PIN(
1819 PINCTRL_PIN(175, "RDN1_B"),
1820 "H2", "mt8135",
1821 MTK_EINT_FUNCTION(2, 181),
1822 MTK_FUNCTION(0, "GPIO175"),
1823 MTK_FUNCTION(1, "CMDAT2"),
1824 MTK_FUNCTION(2, "EINT181"),
1825 MTK_FUNCTION(3, "CMCSD2")
1826 ),
1827 MTK_PIN(
1828 PINCTRL_PIN(176, "RDP1_B"),
1829 "H1", "mt8135",
1830 MTK_EINT_FUNCTION(2, 180),
1831 MTK_FUNCTION(0, "GPIO176"),
1832 MTK_FUNCTION(1, "CMDAT3"),
1833 MTK_FUNCTION(2, "EINT180"),
1834 MTK_FUNCTION(3, "CMCSD3")
1835 ),
1836 MTK_PIN(
1837 PINCTRL_PIN(177, "RCN_B"),
1838 "K3", "mt8135",
1839 MTK_EINT_FUNCTION(2, 177),
1840 MTK_FUNCTION(0, "GPIO177"),
1841 MTK_FUNCTION(1, "CMDAT4"),
1842 MTK_FUNCTION(2, "EINT177")
1843 ),
1844 MTK_PIN(
1845 PINCTRL_PIN(178, "RCP_B"),
1846 "K2", "mt8135",
1847 MTK_EINT_FUNCTION(2, 176),
1848 MTK_FUNCTION(0, "GPIO178"),
1849 MTK_FUNCTION(1, "CMDAT5"),
1850 MTK_FUNCTION(2, "EINT176")
1851 ),
1852 MTK_PIN(
1853 PINCTRL_PIN(179, "RDN0_B"),
1854 "J3", "mt8135",
1855 MTK_EINT_FUNCTION(2, 179),
1856 MTK_FUNCTION(0, "GPIO179"),
1857 MTK_FUNCTION(1, "CMDAT0"),
1858 MTK_FUNCTION(2, "EINT179"),
1859 MTK_FUNCTION(3, "CMCSD0")
1860 ),
1861 MTK_PIN(
1862 PINCTRL_PIN(180, "RDP0_B"),
1863 "J2", "mt8135",
1864 MTK_EINT_FUNCTION(2, 178),
1865 MTK_FUNCTION(0, "GPIO180"),
1866 MTK_FUNCTION(1, "CMDAT1"),
1867 MTK_FUNCTION(2, "EINT178"),
1868 MTK_FUNCTION(3, "CMCSD1")
1869 ),
1870 MTK_PIN(
1871 PINCTRL_PIN(181, "CMPCLK"),
1872 "K4", "mt8135",
1873 MTK_EINT_FUNCTION(2, 182),
1874 MTK_FUNCTION(0, "GPIO181"),
1875 MTK_FUNCTION(1, "CMPCLK"),
1876 MTK_FUNCTION(2, "EINT182"),
1877 MTK_FUNCTION(3, "CMCSK"),
1878 MTK_FUNCTION(4, "CM2MCLK_4X"),
1879 MTK_FUNCTION(5, "TS_AUXADC_SEL[3]"),
1880 MTK_FUNCTION(6, "VENC_TEST_CK"),
1881 MTK_FUNCTION(7, "TESTA_OUT27")
1882 ),
1883 MTK_PIN(
1884 PINCTRL_PIN(182, "CMMCLK"),
1885 "J5", "mt8135",
1886 MTK_EINT_FUNCTION(2, 183),
1887 MTK_FUNCTION(0, "GPIO182"),
1888 MTK_FUNCTION(1, "CMMCLK"),
1889 MTK_FUNCTION(2, "EINT183"),
1890 MTK_FUNCTION(5, "TS_AUXADC_SEL[2]"),
1891 MTK_FUNCTION(7, "TESTA_OUT28")
1892 ),
1893 MTK_PIN(
1894 PINCTRL_PIN(183, "CMRST"),
1895 "J6", "mt8135",
1896 MTK_EINT_FUNCTION(2, 185),
1897 MTK_FUNCTION(0, "GPIO183"),
1898 MTK_FUNCTION(1, "CMRST"),
1899 MTK_FUNCTION(2, "EINT185"),
1900 MTK_FUNCTION(5, "TS_AUXADC_SEL[1]"),
1901 MTK_FUNCTION(7, "TESTA_OUT30")
1902 ),
1903 MTK_PIN(
1904 PINCTRL_PIN(184, "CMPDN"),
1905 "J4", "mt8135",
1906 MTK_EINT_FUNCTION(2, 184),
1907 MTK_FUNCTION(0, "GPIO184"),
1908 MTK_FUNCTION(1, "CMPDN"),
1909 MTK_FUNCTION(2, "EINT184"),
1910 MTK_FUNCTION(5, "TS_AUXADC_SEL[0]"),
1911 MTK_FUNCTION(7, "TESTA_OUT29")
1912 ),
1913 MTK_PIN(
1914 PINCTRL_PIN(185, "CMFLASH"),
1915 "G4", "mt8135",
1916 MTK_EINT_FUNCTION(2, 186),
1917 MTK_FUNCTION(0, "GPIO185"),
1918 MTK_FUNCTION(1, "CMFLASH"),
1919 MTK_FUNCTION(2, "EINT186"),
1920 MTK_FUNCTION(3, "CM2MCLK_3X"),
1921 MTK_FUNCTION(6, "MFG_TEST_CK_1"),
1922 MTK_FUNCTION(7, "TESTA_OUT31")
1923 ),
1924 MTK_PIN(
1925 PINCTRL_PIN(186, "MRG_I2S_PCM_CLK"),
1926 "F5", "mt8135",
1927 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1928 MTK_FUNCTION(0, "GPIO186"),
1929 MTK_FUNCTION(1, "MRG_I2S_PCM_CLK"),
1930 MTK_FUNCTION(3, "I2SIN_CK"),
1931 MTK_FUNCTION(4, "PCM0_CK"),
1932 MTK_FUNCTION(5, "DSP2_ICK"),
1933 MTK_FUNCTION(6, "IMG_TEST_CK"),
1934 MTK_FUNCTION(7, "USB_SCL")
1935 ),
1936 MTK_PIN(
1937 PINCTRL_PIN(187, "MRG_I2S_PCM_SYNC"),
1938 "G6", "mt8135",
1939 MTK_EINT_FUNCTION(2, 16),
1940 MTK_FUNCTION(0, "GPIO187"),
1941 MTK_FUNCTION(1, "MRG_I2S_PCM_SYNC"),
1942 MTK_FUNCTION(2, "EINT16"),
1943 MTK_FUNCTION(3, "I2SIN_WS"),
1944 MTK_FUNCTION(4, "PCM0_WS"),
1945 MTK_FUNCTION(6, "DISP_TEST_CK")
1946 ),
1947 MTK_PIN(
1948 PINCTRL_PIN(188, "MRG_I2S_PCM_RX"),
1949 "G3", "mt8135",
1950 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1951 MTK_FUNCTION(0, "GPIO188"),
1952 MTK_FUNCTION(1, "MRG_I2S_PCM_RX"),
1953 MTK_FUNCTION(3, "I2SIN_DAT"),
1954 MTK_FUNCTION(4, "PCM0_DI"),
1955 MTK_FUNCTION(5, "DSP2_ID"),
1956 MTK_FUNCTION(6, "MFG_TEST_CK"),
1957 MTK_FUNCTION(7, "USB_SDA")
1958 ),
1959 MTK_PIN(
1960 PINCTRL_PIN(189, "MRG_I2S_PCM_TX"),
1961 "G5", "mt8135",
1962 MTK_EINT_FUNCTION(2, 17),
1963 MTK_FUNCTION(0, "GPIO189"),
1964 MTK_FUNCTION(1, "MRG_I2S_PCM_TX"),
1965 MTK_FUNCTION(2, "EINT17"),
1966 MTK_FUNCTION(3, "I2SOUT_DAT"),
1967 MTK_FUNCTION(4, "PCM0_DO"),
1968 MTK_FUNCTION(6, "VDEC_TEST_CK")
1969 ),
1970 MTK_PIN(
1971 PINCTRL_PIN(190, "SRCLKENAI"),
1972 "K5", "mt8135",
1973 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1974 MTK_FUNCTION(0, "GPIO190"),
1975 MTK_FUNCTION(1, "SRCLKENAI")
1976 ),
1977 MTK_PIN(
1978 PINCTRL_PIN(191, "URXD3"),
1979 "C3", "mt8135",
1980 MTK_EINT_FUNCTION(2, 87),
1981 MTK_FUNCTION(0, "GPIO191"),
1982 MTK_FUNCTION(1, "URXD3"),
1983 MTK_FUNCTION(2, "EINT87"),
1984 MTK_FUNCTION(3, "UTXD3"),
1985 MTK_FUNCTION(5, "TS_AUX_ST"),
1986 MTK_FUNCTION(6, "PWM4")
1987 ),
1988 MTK_PIN(
1989 PINCTRL_PIN(192, "UTXD3"),
1990 "B2", "mt8135",
1991 MTK_EINT_FUNCTION(2, 86),
1992 MTK_FUNCTION(0, "GPIO192"),
1993 MTK_FUNCTION(1, "UTXD3"),
1994 MTK_FUNCTION(2, "EINT86"),
1995 MTK_FUNCTION(3, "URXD3"),
1996 MTK_FUNCTION(5, "TS_AUX_CS_B"),
1997 MTK_FUNCTION(6, "PWM3")
1998 ),
1999 MTK_PIN(
2000 PINCTRL_PIN(193, "SDA2"),
2001 "G2", "mt8135",
2002 MTK_EINT_FUNCTION(2, 95),
2003 MTK_FUNCTION(0, "GPIO193"),
2004 MTK_FUNCTION(1, "SDA2"),
2005 MTK_FUNCTION(2, "EINT95"),
2006 MTK_FUNCTION(3, "CLKM5"),
2007 MTK_FUNCTION(4, "PWM5"),
2008 MTK_FUNCTION(5, "TS_AUX_PWDB")
2009 ),
2010 MTK_PIN(
2011 PINCTRL_PIN(194, "SCL2"),
2012 "F4", "mt8135",
2013 MTK_EINT_FUNCTION(2, 94),
2014 MTK_FUNCTION(0, "GPIO194"),
2015 MTK_FUNCTION(1, "SCL2"),
2016 MTK_FUNCTION(2, "EINT94"),
2017 MTK_FUNCTION(3, "CLKM4"),
2018 MTK_FUNCTION(4, "PWM4"),
2019 MTK_FUNCTION(5, "TS_AUXADC_TEST_CK")
2020 ),
2021 MTK_PIN(
2022 PINCTRL_PIN(195, "SDA1"),
2023 "F2", "mt8135",
2024 MTK_EINT_FUNCTION(2, 93),
2025 MTK_FUNCTION(0, "GPIO195"),
2026 MTK_FUNCTION(1, "SDA1"),
2027 MTK_FUNCTION(2, "EINT93"),
2028 MTK_FUNCTION(3, "CLKM3"),
2029 MTK_FUNCTION(4, "PWM3"),
2030 MTK_FUNCTION(5, "TS_AUX_SCLK_PWDB")
2031 ),
2032 MTK_PIN(
2033 PINCTRL_PIN(196, "SCL1"),
2034 "F3", "mt8135",
2035 MTK_EINT_FUNCTION(2, 92),
2036 MTK_FUNCTION(0, "GPIO196"),
2037 MTK_FUNCTION(1, "SCL1"),
2038 MTK_FUNCTION(2, "EINT92"),
2039 MTK_FUNCTION(3, "CLKM2"),
2040 MTK_FUNCTION(4, "PWM2"),
2041 MTK_FUNCTION(5, "TS_AUX_DIN")
2042 ),
2043 MTK_PIN(
2044 PINCTRL_PIN(197, "MSDC3_DAT2"),
2045 "E1", "mt8135",
2046 MTK_EINT_FUNCTION(2, 71),
2047 MTK_FUNCTION(0, "GPIO197"),
2048 MTK_FUNCTION(1, "MSDC3_DAT2"),
2049 MTK_FUNCTION(2, "EINT71"),
2050 MTK_FUNCTION(3, "SCL6"),
2051 MTK_FUNCTION(4, "PWM5"),
2052 MTK_FUNCTION(5, "CLKM4"),
2053 MTK_FUNCTION(6, "MFG_TEST_CK_2")
2054 ),
2055 MTK_PIN(
2056 PINCTRL_PIN(198, "MSDC3_DAT3"),
2057 "C2", "mt8135",
2058 MTK_EINT_FUNCTION(2, 72),
2059 MTK_FUNCTION(0, "GPIO198"),
2060 MTK_FUNCTION(1, "MSDC3_DAT3"),
2061 MTK_FUNCTION(2, "EINT72"),
2062 MTK_FUNCTION(3, "SDA6"),
2063 MTK_FUNCTION(4, "PWM6"),
2064 MTK_FUNCTION(5, "CLKM5"),
2065 MTK_FUNCTION(6, "MFG_TEST_CK_3")
2066 ),
2067 MTK_PIN(
2068 PINCTRL_PIN(199, "MSDC3_CMD"),
2069 "D2", "mt8135",
2070 MTK_EINT_FUNCTION(2, 68),
2071 MTK_FUNCTION(0, "GPIO199"),
2072 MTK_FUNCTION(1, "MSDC3_CMD"),
2073 MTK_FUNCTION(2, "EINT68"),
2074 MTK_FUNCTION(3, "SDA2"),
2075 MTK_FUNCTION(4, "PWM2"),
2076 MTK_FUNCTION(5, "CLKM1"),
2077 MTK_FUNCTION(6, "MFG_TEST_CK_4")
2078 ),
2079 MTK_PIN(
2080 PINCTRL_PIN(200, "MSDC3_CLK"),
2081 "E2", "mt8135",
2082 MTK_EINT_FUNCTION(2, 67),
2083 MTK_FUNCTION(0, "GPIO200"),
2084 MTK_FUNCTION(1, "MSDC3_CLK"),
2085 MTK_FUNCTION(2, "EINT67"),
2086 MTK_FUNCTION(3, "SCL2"),
2087 MTK_FUNCTION(4, "PWM1"),
2088 MTK_FUNCTION(5, "CLKM0")
2089 ),
2090 MTK_PIN(
2091 PINCTRL_PIN(201, "MSDC3_DAT1"),
2092 "D3", "mt8135",
2093 MTK_EINT_FUNCTION(2, 70),
2094 MTK_FUNCTION(0, "GPIO201"),
2095 MTK_FUNCTION(1, "MSDC3_DAT1"),
2096 MTK_FUNCTION(2, "EINT70"),
2097 MTK_FUNCTION(3, "SDA3"),
2098 MTK_FUNCTION(4, "PWM4"),
2099 MTK_FUNCTION(5, "CLKM3")
2100 ),
2101 MTK_PIN(
2102 PINCTRL_PIN(202, "MSDC3_DAT0"),
2103 "E3", "mt8135",
2104 MTK_EINT_FUNCTION(2, 69),
2105 MTK_FUNCTION(0, "GPIO202"),
2106 MTK_FUNCTION(1, "MSDC3_DAT0"),
2107 MTK_FUNCTION(2, "EINT69"),
2108 MTK_FUNCTION(3, "SCL3"),
2109 MTK_FUNCTION(4, "PWM3"),
2110 MTK_FUNCTION(5, "CLKM2")
2111 ),
2112};
2113
2114#endif /* __PINCTRL_MTK_MT8135_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h
new file mode 100644
index 000000000000..13e5b68bfe1b
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8173.h
@@ -0,0 +1,1226 @@
1/*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __PINCTRL_MTK_MT8173_H
16#define __PINCTRL_MTK_MT8173_H
17
18#include <linux/pinctrl/pinctrl.h>
19#include "pinctrl-mtk-common.h"
20
21static const struct mtk_desc_pin mtk_pins_mt8173[] = {
22 MTK_PIN(
23 PINCTRL_PIN(0, "EINT0"),
24 NULL, "mt8173",
25 MTK_EINT_FUNCTION(0, 0),
26 MTK_FUNCTION(0, "GPIO0"),
27 MTK_FUNCTION(1, "IRDA_PDN"),
28 MTK_FUNCTION(2, "I2S1_WS"),
29 MTK_FUNCTION(3, "AUD_SPDIF"),
30 MTK_FUNCTION(4, "UTXD0"),
31 MTK_FUNCTION(7, "DBG_MON_A_20_")
32 ),
33 MTK_PIN(
34 PINCTRL_PIN(1, "EINT1"),
35 NULL, "mt8173",
36 MTK_EINT_FUNCTION(0, 1),
37 MTK_FUNCTION(0, "GPIO1"),
38 MTK_FUNCTION(1, "IRDA_RXD"),
39 MTK_FUNCTION(2, "I2S1_BCK"),
40 MTK_FUNCTION(3, "SDA5"),
41 MTK_FUNCTION(4, "URXD0"),
42 MTK_FUNCTION(7, "DBG_MON_A_21_")
43 ),
44 MTK_PIN(
45 PINCTRL_PIN(2, "EINT2"),
46 NULL, "mt8173",
47 MTK_EINT_FUNCTION(0, 2),
48 MTK_FUNCTION(0, "GPIO2"),
49 MTK_FUNCTION(1, "IRDA_TXD"),
50 MTK_FUNCTION(2, "I2S1_MCK"),
51 MTK_FUNCTION(3, "SCL5"),
52 MTK_FUNCTION(4, "UTXD3"),
53 MTK_FUNCTION(7, "DBG_MON_A_22_")
54 ),
55 MTK_PIN(
56 PINCTRL_PIN(3, "EINT3"),
57 NULL, "mt8173",
58 MTK_EINT_FUNCTION(0, 3),
59 MTK_FUNCTION(0, "GPIO3"),
60 MTK_FUNCTION(1, "DSI1_TE"),
61 MTK_FUNCTION(2, "I2S1_DO_1"),
62 MTK_FUNCTION(3, "SDA3"),
63 MTK_FUNCTION(4, "URXD3"),
64 MTK_FUNCTION(7, "DBG_MON_A_23_")
65 ),
66 MTK_PIN(
67 PINCTRL_PIN(4, "EINT4"),
68 NULL, "mt8173",
69 MTK_EINT_FUNCTION(0, 4),
70 MTK_FUNCTION(0, "GPIO4"),
71 MTK_FUNCTION(1, "DISP_PWM1"),
72 MTK_FUNCTION(2, "I2S1_DO_2"),
73 MTK_FUNCTION(3, "SCL3"),
74 MTK_FUNCTION(4, "UCTS3"),
75 MTK_FUNCTION(6, "SFWP_B")
76 ),
77 MTK_PIN(
78 PINCTRL_PIN(5, "EINT5"),
79 NULL, "mt8173",
80 MTK_EINT_FUNCTION(0, 5),
81 MTK_FUNCTION(0, "GPIO5"),
82 MTK_FUNCTION(1, "PCM1_CLK"),
83 MTK_FUNCTION(2, "I2S2_WS"),
84 MTK_FUNCTION(3, "SPI_CK_3_"),
85 MTK_FUNCTION(4, "URTS3"),
86 MTK_FUNCTION(5, "AP_MD32_JTAG_TMS"),
87 MTK_FUNCTION(6, "SFOUT")
88 ),
89 MTK_PIN(
90 PINCTRL_PIN(6, "EINT6"),
91 NULL, "mt8173",
92 MTK_EINT_FUNCTION(0, 6),
93 MTK_FUNCTION(0, "GPIO6"),
94 MTK_FUNCTION(1, "PCM1_SYNC"),
95 MTK_FUNCTION(2, "I2S2_BCK"),
96 MTK_FUNCTION(3, "SPI_MI_3_"),
97 MTK_FUNCTION(5, "AP_MD32_JTAG_TCK"),
98 MTK_FUNCTION(6, "SFCS0")
99 ),
100 MTK_PIN(
101 PINCTRL_PIN(7, "EINT7"),
102 NULL, "mt8173",
103 MTK_EINT_FUNCTION(0, 7),
104 MTK_FUNCTION(0, "GPIO7"),
105 MTK_FUNCTION(1, "PCM1_DI"),
106 MTK_FUNCTION(2, "I2S2_DI_1"),
107 MTK_FUNCTION(3, "SPI_MO_3_"),
108 MTK_FUNCTION(5, "AP_MD32_JTAG_TDI"),
109 MTK_FUNCTION(6, "SFHOLD")
110 ),
111 MTK_PIN(
112 PINCTRL_PIN(8, "EINT8"),
113 NULL, "mt8173",
114 MTK_EINT_FUNCTION(0, 8),
115 MTK_FUNCTION(0, "GPIO8"),
116 MTK_FUNCTION(1, "PCM1_DO"),
117 MTK_FUNCTION(2, "I2S2_DI_2"),
118 MTK_FUNCTION(3, "SPI_CS_3_"),
119 MTK_FUNCTION(4, "AUD_SPDIF"),
120 MTK_FUNCTION(5, "AP_MD32_JTAG_TDO"),
121 MTK_FUNCTION(6, "SFIN")
122 ),
123 MTK_PIN(
124 PINCTRL_PIN(9, "EINT9"),
125 NULL, "mt8173",
126 MTK_EINT_FUNCTION(0, 9),
127 MTK_FUNCTION(0, "GPIO9"),
128 MTK_FUNCTION(1, "USB_DRVVBUS_P0"),
129 MTK_FUNCTION(2, "I2S2_MCK"),
130 MTK_FUNCTION(4, "USB_DRVVBUS_P1"),
131 MTK_FUNCTION(5, "AP_MD32_JTAG_TRST"),
132 MTK_FUNCTION(6, "SFCK")
133 ),
134 MTK_PIN(
135 PINCTRL_PIN(10, "EINT10"),
136 NULL, "mt8173",
137 MTK_EINT_FUNCTION(0, 10),
138 MTK_FUNCTION(0, "GPIO10"),
139 MTK_FUNCTION(1, "CLKM0"),
140 MTK_FUNCTION(2, "DSI1_TE"),
141 MTK_FUNCTION(3, "DISP_PWM1"),
142 MTK_FUNCTION(4, "PWM4"),
143 MTK_FUNCTION(5, "IRDA_RXD")
144 ),
145 MTK_PIN(
146 PINCTRL_PIN(11, "EINT11"),
147 NULL, "mt8173",
148 MTK_EINT_FUNCTION(0, 11),
149 MTK_FUNCTION(0, "GPIO11"),
150 MTK_FUNCTION(1, "CLKM1"),
151 MTK_FUNCTION(2, "I2S3_WS"),
152 MTK_FUNCTION(3, "USB_DRVVBUS_P0"),
153 MTK_FUNCTION(4, "PWM5"),
154 MTK_FUNCTION(5, "IRDA_TXD"),
155 MTK_FUNCTION(6, "USB_DRVVBUS_P1"),
156 MTK_FUNCTION(7, "DBG_MON_B_30_")
157 ),
158 MTK_PIN(
159 PINCTRL_PIN(12, "EINT12"),
160 NULL, "mt8173",
161 MTK_EINT_FUNCTION(0, 12),
162 MTK_FUNCTION(0, "GPIO12"),
163 MTK_FUNCTION(1, "CLKM2"),
164 MTK_FUNCTION(2, "I2S3_BCK"),
165 MTK_FUNCTION(3, "SRCLKENA0"),
166 MTK_FUNCTION(5, "I2S2_WS"),
167 MTK_FUNCTION(7, "DBG_MON_B_32_")
168 ),
169 MTK_PIN(
170 PINCTRL_PIN(13, "EINT13"),
171 NULL, "mt8173",
172 MTK_EINT_FUNCTION(0, 13),
173 MTK_FUNCTION(0, "GPIO13"),
174 MTK_FUNCTION(1, "CLKM3"),
175 MTK_FUNCTION(2, "I2S3_MCK"),
176 MTK_FUNCTION(3, "SRCLKENA0"),
177 MTK_FUNCTION(5, "I2S2_BCK"),
178 MTK_FUNCTION(7, "DBG_MON_A_32_")
179 ),
180 MTK_PIN(
181 PINCTRL_PIN(14, "EINT14"),
182 NULL, "mt8173",
183 MTK_EINT_FUNCTION(0, 14),
184 MTK_FUNCTION(0, "GPIO14"),
185 MTK_FUNCTION(1, "CMDAT0"),
186 MTK_FUNCTION(2, "CMCSD0"),
187 MTK_FUNCTION(4, "CLKM2"),
188 MTK_FUNCTION(7, "DBG_MON_B_6_")
189 ),
190 MTK_PIN(
191 PINCTRL_PIN(15, "EINT15"),
192 NULL, "mt8173",
193 MTK_EINT_FUNCTION(0, 15),
194 MTK_FUNCTION(0, "GPIO15"),
195 MTK_FUNCTION(1, "CMDAT1"),
196 MTK_FUNCTION(2, "CMCSD1"),
197 MTK_FUNCTION(3, "CMFLASH"),
198 MTK_FUNCTION(4, "CLKM3"),
199 MTK_FUNCTION(7, "DBG_MON_B_29_")
200 ),
201 MTK_PIN(
202 PINCTRL_PIN(16, "IDDIG"),
203 NULL, "mt8173",
204 MTK_EINT_FUNCTION(0, 16),
205 MTK_FUNCTION(0, "GPIO16"),
206 MTK_FUNCTION(1, "IDDIG"),
207 MTK_FUNCTION(2, "CMFLASH"),
208 MTK_FUNCTION(4, "PWM5")
209 ),
210 MTK_PIN(
211 PINCTRL_PIN(17, "WATCHDOG"),
212 NULL, "mt8173",
213 MTK_EINT_FUNCTION(0, 17),
214 MTK_FUNCTION(0, "GPIO17"),
215 MTK_FUNCTION(1, "WATCHDOG_AO")
216 ),
217 MTK_PIN(
218 PINCTRL_PIN(18, "CEC"),
219 NULL, "mt8173",
220 MTK_EINT_FUNCTION(0, 18),
221 MTK_FUNCTION(0, "GPIO18"),
222 MTK_FUNCTION(1, "CEC")
223 ),
224 MTK_PIN(
225 PINCTRL_PIN(19, "HDMISCK"),
226 NULL, "mt8173",
227 MTK_EINT_FUNCTION(0, 19),
228 MTK_FUNCTION(0, "GPIO19"),
229 MTK_FUNCTION(1, "HDMISCK"),
230 MTK_FUNCTION(2, "HDCP_SCL")
231 ),
232 MTK_PIN(
233 PINCTRL_PIN(20, "HDMISD"),
234 NULL, "mt8173",
235 MTK_EINT_FUNCTION(0, 20),
236 MTK_FUNCTION(0, "GPIO20"),
237 MTK_FUNCTION(1, "HDMISD"),
238 MTK_FUNCTION(2, "HDCP_SDA")
239 ),
240 MTK_PIN(
241 PINCTRL_PIN(21, "HTPLG"),
242 NULL, "mt8173",
243 MTK_EINT_FUNCTION(0, 21),
244 MTK_FUNCTION(0, "GPIO21"),
245 MTK_FUNCTION(1, "HTPLG")
246 ),
247 MTK_PIN(
248 PINCTRL_PIN(22, "MSDC3_DAT0"),
249 NULL, "mt8173",
250 MTK_EINT_FUNCTION(0, 22),
251 MTK_FUNCTION(0, "GPIO22"),
252 MTK_FUNCTION(1, "MSDC3_DAT0")
253 ),
254 MTK_PIN(
255 PINCTRL_PIN(23, "MSDC3_DAT1"),
256 NULL, "mt8173",
257 MTK_EINT_FUNCTION(0, 23),
258 MTK_FUNCTION(0, "GPIO23"),
259 MTK_FUNCTION(1, "MSDC3_DAT1")
260 ),
261 MTK_PIN(
262 PINCTRL_PIN(24, "MSDC3_DAT2"),
263 NULL, "mt8173",
264 MTK_EINT_FUNCTION(0, 24),
265 MTK_FUNCTION(0, "GPIO24"),
266 MTK_FUNCTION(1, "MSDC3_DAT2")
267 ),
268 MTK_PIN(
269 PINCTRL_PIN(25, "MSDC3_DAT3"),
270 NULL, "mt8173",
271 MTK_EINT_FUNCTION(0, 25),
272 MTK_FUNCTION(0, "GPIO25"),
273 MTK_FUNCTION(1, "MSDC3_DAT3")
274 ),
275 MTK_PIN(
276 PINCTRL_PIN(26, "MSDC3_CLK"),
277 NULL, "mt8173",
278 MTK_EINT_FUNCTION(0, 26),
279 MTK_FUNCTION(0, "GPIO26"),
280 MTK_FUNCTION(1, "MSDC3_CLK")
281 ),
282 MTK_PIN(
283 PINCTRL_PIN(27, "MSDC3_CMD"),
284 NULL, "mt8173",
285 MTK_EINT_FUNCTION(0, 27),
286 MTK_FUNCTION(0, "GPIO27"),
287 MTK_FUNCTION(1, "MSDC3_CMD")
288 ),
289 MTK_PIN(
290 PINCTRL_PIN(28, "MSDC3_DSL"),
291 NULL, "mt8173",
292 MTK_EINT_FUNCTION(0, 28),
293 MTK_FUNCTION(0, "GPIO28"),
294 MTK_FUNCTION(1, "MSDC3_DSL")
295 ),
296 MTK_PIN(
297 PINCTRL_PIN(29, "UCTS2"),
298 NULL, "mt8173",
299 MTK_EINT_FUNCTION(0, 29),
300 MTK_FUNCTION(0, "GPIO29"),
301 MTK_FUNCTION(1, "UCTS2")
302 ),
303 MTK_PIN(
304 PINCTRL_PIN(30, "URTS2"),
305 NULL, "mt8173",
306 MTK_EINT_FUNCTION(0, 30),
307 MTK_FUNCTION(0, "GPIO30"),
308 MTK_FUNCTION(1, "URTS2")
309 ),
310 MTK_PIN(
311 PINCTRL_PIN(31, "URXD2"),
312 NULL, "mt8173",
313 MTK_EINT_FUNCTION(0, 31),
314 MTK_FUNCTION(0, "GPIO31"),
315 MTK_FUNCTION(1, "URXD2"),
316 MTK_FUNCTION(2, "UTXD2")
317 ),
318 MTK_PIN(
319 PINCTRL_PIN(32, "UTXD2"),
320 NULL, "mt8173",
321 MTK_EINT_FUNCTION(0, 32),
322 MTK_FUNCTION(0, "GPIO32"),
323 MTK_FUNCTION(1, "UTXD2"),
324 MTK_FUNCTION(2, "URXD2")
325 ),
326 MTK_PIN(
327 PINCTRL_PIN(33, "DAICLK"),
328 NULL, "mt8173",
329 MTK_EINT_FUNCTION(0, 33),
330 MTK_FUNCTION(0, "GPIO33"),
331 MTK_FUNCTION(1, " MRG_CLK"),
332 MTK_FUNCTION(2, "PCM0_CLK")
333 ),
334 MTK_PIN(
335 PINCTRL_PIN(34, "DAIPCMIN"),
336 NULL, "mt8173",
337 MTK_EINT_FUNCTION(0, 34),
338 MTK_FUNCTION(0, "GPIO34"),
339 MTK_FUNCTION(1, " MRG_DI"),
340 MTK_FUNCTION(2, "PCM0_DI")
341 ),
342 MTK_PIN(
343 PINCTRL_PIN(35, "DAIPCMOUT"),
344 NULL, "mt8173",
345 MTK_EINT_FUNCTION(0, 35),
346 MTK_FUNCTION(0, "GPIO35"),
347 MTK_FUNCTION(1, " MRG_DO"),
348 MTK_FUNCTION(2, "PCM0_DO")
349 ),
350 MTK_PIN(
351 PINCTRL_PIN(36, "DAISYNC"),
352 NULL, "mt8173",
353 MTK_EINT_FUNCTION(0, 36),
354 MTK_FUNCTION(0, "GPIO36"),
355 MTK_FUNCTION(1, " MRG_SYNC"),
356 MTK_FUNCTION(2, "PCM0_SYNC")
357 ),
358 MTK_PIN(
359 PINCTRL_PIN(37, "EINT16"),
360 NULL, "mt8173",
361 MTK_EINT_FUNCTION(0, 37),
362 MTK_FUNCTION(0, "GPIO37"),
363 MTK_FUNCTION(1, "USB_DRVVBUS_P0"),
364 MTK_FUNCTION(2, "USB_DRVVBUS_P1"),
365 MTK_FUNCTION(3, "PWM0"),
366 MTK_FUNCTION(4, "PWM1"),
367 MTK_FUNCTION(5, "PWM2"),
368 MTK_FUNCTION(6, "CLKM0")
369 ),
370 MTK_PIN(
371 PINCTRL_PIN(38, "CONN_RST"),
372 NULL, "mt8173",
373 MTK_EINT_FUNCTION(0, 38),
374 MTK_FUNCTION(0, "GPIO38"),
375 MTK_FUNCTION(1, "USB_DRVVBUS_P0"),
376 MTK_FUNCTION(2, "USB_DRVVBUS_P1"),
377 MTK_FUNCTION(6, "CLKM1")
378 ),
379 MTK_PIN(
380 PINCTRL_PIN(39, "CM2MCLK"),
381 NULL, "mt8173",
382 MTK_EINT_FUNCTION(0, 39),
383 MTK_FUNCTION(0, "GPIO39"),
384 MTK_FUNCTION(1, "CM2MCLK"),
385 MTK_FUNCTION(2, "CMCSD0"),
386 MTK_FUNCTION(7, "DBG_MON_A_17_")
387 ),
388 MTK_PIN(
389 PINCTRL_PIN(40, "CMPCLK"),
390 NULL, "mt8173",
391 MTK_EINT_FUNCTION(0, 40),
392 MTK_FUNCTION(0, "GPIO40"),
393 MTK_FUNCTION(1, "CMPCLK"),
394 MTK_FUNCTION(2, "CMCSK"),
395 MTK_FUNCTION(3, "CMCSD2"),
396 MTK_FUNCTION(7, "DBG_MON_A_18_")
397 ),
398 MTK_PIN(
399 PINCTRL_PIN(41, "CMMCLK"),
400 NULL, "mt8173",
401 MTK_EINT_FUNCTION(0, 41),
402 MTK_FUNCTION(0, "GPIO41"),
403 MTK_FUNCTION(1, "CMMCLK"),
404 MTK_FUNCTION(7, "DBG_MON_A_19_")
405 ),
406 MTK_PIN(
407 PINCTRL_PIN(42, "DSI_TE"),
408 NULL, "mt8173",
409 MTK_EINT_FUNCTION(0, 42),
410 MTK_FUNCTION(0, "GPIO42"),
411 MTK_FUNCTION(1, "DSI_TE")
412 ),
413 MTK_PIN(
414 PINCTRL_PIN(43, "SDA2"),
415 NULL, "mt8173",
416 MTK_EINT_FUNCTION(0, 43),
417 MTK_FUNCTION(0, "GPIO43"),
418 MTK_FUNCTION(1, "SDA2")
419 ),
420 MTK_PIN(
421 PINCTRL_PIN(44, "SCL2"),
422 NULL, "mt8173",
423 MTK_EINT_FUNCTION(0, 44),
424 MTK_FUNCTION(0, "GPIO44"),
425 MTK_FUNCTION(1, "SCL2")
426 ),
427 MTK_PIN(
428 PINCTRL_PIN(45, "SDA0"),
429 NULL, "mt8173",
430 MTK_EINT_FUNCTION(0, 45),
431 MTK_FUNCTION(0, "GPIO45"),
432 MTK_FUNCTION(1, "SDA0")
433 ),
434 MTK_PIN(
435 PINCTRL_PIN(46, "SCL0"),
436 NULL, "mt8173",
437 MTK_EINT_FUNCTION(0, 46),
438 MTK_FUNCTION(0, "GPIO46"),
439 MTK_FUNCTION(1, "SCL0")
440 ),
441 MTK_PIN(
442 PINCTRL_PIN(47, "RDN0_A"),
443 NULL, "mt8173",
444 MTK_EINT_FUNCTION(0, 47),
445 MTK_FUNCTION(0, "GPIO47"),
446 MTK_FUNCTION(1, "CMDAT2")
447 ),
448 MTK_PIN(
449 PINCTRL_PIN(48, "RDP0_A"),
450 NULL, "mt8173",
451 MTK_EINT_FUNCTION(0, 48),
452 MTK_FUNCTION(0, "GPIO48"),
453 MTK_FUNCTION(1, "CMDAT3")
454 ),
455 MTK_PIN(
456 PINCTRL_PIN(49, "RDN1_A"),
457 NULL, "mt8173",
458 MTK_EINT_FUNCTION(0, 49),
459 MTK_FUNCTION(0, "GPIO49"),
460 MTK_FUNCTION(1, "CMDAT4")
461 ),
462 MTK_PIN(
463 PINCTRL_PIN(50, "RDP1_A"),
464 NULL, "mt8173",
465 MTK_EINT_FUNCTION(0, 50),
466 MTK_FUNCTION(0, "GPIO50"),
467 MTK_FUNCTION(1, "CMDAT5")
468 ),
469 MTK_PIN(
470 PINCTRL_PIN(51, "RCN_A"),
471 NULL, "mt8173",
472 MTK_EINT_FUNCTION(0, 51),
473 MTK_FUNCTION(0, "GPIO51"),
474 MTK_FUNCTION(1, "CMDAT6")
475 ),
476 MTK_PIN(
477 PINCTRL_PIN(52, "RCP_A"),
478 NULL, "mt8173",
479 MTK_EINT_FUNCTION(0, 52),
480 MTK_FUNCTION(0, "GPIO52"),
481 MTK_FUNCTION(1, "CMDAT7")
482 ),
483 MTK_PIN(
484 PINCTRL_PIN(53, "RDN2_A"),
485 NULL, "mt8173",
486 MTK_EINT_FUNCTION(0, 53),
487 MTK_FUNCTION(0, "GPIO53"),
488 MTK_FUNCTION(1, "CMDAT8"),
489 MTK_FUNCTION(2, "CMCSD3")
490 ),
491 MTK_PIN(
492 PINCTRL_PIN(54, "RDP2_A"),
493 NULL, "mt8173",
494 MTK_EINT_FUNCTION(0, 54),
495 MTK_FUNCTION(0, "GPIO54"),
496 MTK_FUNCTION(1, "CMDAT9"),
497 MTK_FUNCTION(2, "CMCSD2")
498 ),
499 MTK_PIN(
500 PINCTRL_PIN(55, "RDN3_A"),
501 NULL, "mt8173",
502 MTK_EINT_FUNCTION(0, 55),
503 MTK_FUNCTION(0, "GPIO55"),
504 MTK_FUNCTION(1, "CMHSYNC"),
505 MTK_FUNCTION(2, "CMCSD1")
506 ),
507 MTK_PIN(
508 PINCTRL_PIN(56, "RDP3_A"),
509 NULL, "mt8173",
510 MTK_EINT_FUNCTION(0, 56),
511 MTK_FUNCTION(0, "GPIO56"),
512 MTK_FUNCTION(1, "CMVSYNC"),
513 MTK_FUNCTION(2, "CMCSD0")
514 ),
515 MTK_PIN(
516 PINCTRL_PIN(57, "MSDC0_DAT0"),
517 NULL, "mt8173",
518 MTK_EINT_FUNCTION(0, 57),
519 MTK_FUNCTION(0, "GPIO57"),
520 MTK_FUNCTION(1, "MSDC0_DAT0"),
521 MTK_FUNCTION(2, "I2S1_WS"),
522 MTK_FUNCTION(7, "DBG_MON_B_7_")
523 ),
524 MTK_PIN(
525 PINCTRL_PIN(58, "MSDC0_DAT1"),
526 NULL, "mt8173",
527 MTK_EINT_FUNCTION(0, 58),
528 MTK_FUNCTION(0, "GPIO58"),
529 MTK_FUNCTION(1, "MSDC0_DAT1"),
530 MTK_FUNCTION(2, "I2S1_BCK"),
531 MTK_FUNCTION(7, "DBG_MON_B_8_")
532 ),
533 MTK_PIN(
534 PINCTRL_PIN(59, "MSDC0_DAT2"),
535 NULL, "mt8173",
536 MTK_EINT_FUNCTION(0, 59),
537 MTK_FUNCTION(0, "GPIO59"),
538 MTK_FUNCTION(1, "MSDC0_DAT2"),
539 MTK_FUNCTION(2, "I2S1_MCK"),
540 MTK_FUNCTION(7, "DBG_MON_B_9_")
541 ),
542 MTK_PIN(
543 PINCTRL_PIN(60, "MSDC0_DAT3"),
544 NULL, "mt8173",
545 MTK_EINT_FUNCTION(0, 60),
546 MTK_FUNCTION(0, "GPIO60"),
547 MTK_FUNCTION(1, "MSDC0_DAT3"),
548 MTK_FUNCTION(2, "I2S1_DO_1"),
549 MTK_FUNCTION(7, "DBG_MON_B_10_")
550 ),
551 MTK_PIN(
552 PINCTRL_PIN(61, "MSDC0_DAT4"),
553 NULL, "mt8173",
554 MTK_EINT_FUNCTION(0, 61),
555 MTK_FUNCTION(0, "GPIO61"),
556 MTK_FUNCTION(1, "MSDC0_DAT4"),
557 MTK_FUNCTION(2, "I2S1_DO_2"),
558 MTK_FUNCTION(7, "DBG_MON_B_11_")
559 ),
560 MTK_PIN(
561 PINCTRL_PIN(62, "MSDC0_DAT5"),
562 NULL, "mt8173",
563 MTK_EINT_FUNCTION(0, 62),
564 MTK_FUNCTION(0, "GPIO62"),
565 MTK_FUNCTION(1, "MSDC0_DAT5"),
566 MTK_FUNCTION(2, "I2S2_WS"),
567 MTK_FUNCTION(7, "DBG_MON_B_12_")
568 ),
569 MTK_PIN(
570 PINCTRL_PIN(63, "MSDC0_DAT6"),
571 NULL, "mt8173",
572 MTK_EINT_FUNCTION(0, 63),
573 MTK_FUNCTION(0, "GPIO63"),
574 MTK_FUNCTION(1, "MSDC0_DAT6"),
575 MTK_FUNCTION(2, "I2S2_BCK"),
576 MTK_FUNCTION(7, "DBG_MON_B_13_")
577 ),
578 MTK_PIN(
579 PINCTRL_PIN(64, "MSDC0_DAT7"),
580 NULL, "mt8173",
581 MTK_EINT_FUNCTION(0, 64),
582 MTK_FUNCTION(0, "GPIO64"),
583 MTK_FUNCTION(1, "MSDC0_DAT7"),
584 MTK_FUNCTION(2, "I2S2_DI_1"),
585 MTK_FUNCTION(7, "DBG_MON_B_14_")
586 ),
587 MTK_PIN(
588 PINCTRL_PIN(65, "MSDC0_CLK"),
589 NULL, "mt8173",
590 MTK_EINT_FUNCTION(0, 65),
591 MTK_FUNCTION(0, "GPIO65"),
592 MTK_FUNCTION(1, "MSDC0_CLK"),
593 MTK_FUNCTION(7, "DBG_MON_B_16_")
594 ),
595 MTK_PIN(
596 PINCTRL_PIN(66, "MSDC0_CMD"),
597 NULL, "mt8173",
598 MTK_EINT_FUNCTION(0, 66),
599 MTK_FUNCTION(0, "GPIO66"),
600 MTK_FUNCTION(1, "MSDC0_CMD"),
601 MTK_FUNCTION(2, "I2S2_DI_2"),
602 MTK_FUNCTION(7, "DBG_MON_B_15_")
603 ),
604 MTK_PIN(
605 PINCTRL_PIN(67, "MSDC0_DSL"),
606 NULL, "mt8173",
607 MTK_EINT_FUNCTION(0, 67),
608 MTK_FUNCTION(0, "GPIO67"),
609 MTK_FUNCTION(1, "MSDC0_DSL"),
610 MTK_FUNCTION(7, "DBG_MON_B_17_")
611 ),
612 MTK_PIN(
613 PINCTRL_PIN(68, "MSDC0_RST_"),
614 NULL, "mt8173",
615 MTK_EINT_FUNCTION(0, 68),
616 MTK_FUNCTION(0, "GPIO68"),
617 MTK_FUNCTION(1, "MSDC0_RSTB"),
618 MTK_FUNCTION(2, "I2S2_MCK"),
619 MTK_FUNCTION(7, "DBG_MON_B_18_")
620 ),
621 MTK_PIN(
622 PINCTRL_PIN(69, "SPI_CK"),
623 NULL, "mt8173",
624 MTK_EINT_FUNCTION(0, 69),
625 MTK_FUNCTION(0, "GPIO69"),
626 MTK_FUNCTION(1, "SPI_CK_0_"),
627 MTK_FUNCTION(2, "I2S3_DO_1"),
628 MTK_FUNCTION(3, "PWM0"),
629 MTK_FUNCTION(4, "PWM5"),
630 MTK_FUNCTION(5, "I2S2_MCK"),
631 MTK_FUNCTION(7, "DBG_MON_B_19_")
632 ),
633 MTK_PIN(
634 PINCTRL_PIN(70, "SPI_MI"),
635 NULL, "mt8173",
636 MTK_EINT_FUNCTION(0, 70),
637 MTK_FUNCTION(0, "GPIO70"),
638 MTK_FUNCTION(1, "SPI_MI_0_"),
639 MTK_FUNCTION(2, "I2S3_DO_2"),
640 MTK_FUNCTION(3, "PWM1"),
641 MTK_FUNCTION(4, "SPI_MO_0_"),
642 MTK_FUNCTION(5, "I2S2_DI_1"),
643 MTK_FUNCTION(6, "DSI1_TE"),
644 MTK_FUNCTION(7, "DBG_MON_B_20_")
645 ),
646 MTK_PIN(
647 PINCTRL_PIN(71, "SPI_MO"),
648 NULL, "mt8173",
649 MTK_EINT_FUNCTION(0, 71),
650 MTK_FUNCTION(0, "GPIO71"),
651 MTK_FUNCTION(1, "SPI_MO_0_"),
652 MTK_FUNCTION(2, "I2S3_DO_3"),
653 MTK_FUNCTION(3, "PWM2"),
654 MTK_FUNCTION(4, "SPI_MI_0_"),
655 MTK_FUNCTION(5, "I2S2_DI_2"),
656 MTK_FUNCTION(7, "DBG_MON_B_21_")
657 ),
658 MTK_PIN(
659 PINCTRL_PIN(72, "SPI_CS"),
660 NULL, "mt8173",
661 MTK_EINT_FUNCTION(0, 72),
662 MTK_FUNCTION(0, "GPIO72"),
663 MTK_FUNCTION(1, "SPI_CS_0_"),
664 MTK_FUNCTION(2, "I2S3_DO_4"),
665 MTK_FUNCTION(3, "PWM3"),
666 MTK_FUNCTION(4, "PWM6"),
667 MTK_FUNCTION(5, "DISP_PWM1"),
668 MTK_FUNCTION(7, "DBG_MON_B_22_")
669 ),
670 MTK_PIN(
671 PINCTRL_PIN(73, "MSDC1_DAT0"),
672 NULL, "mt8173",
673 MTK_EINT_FUNCTION(0, 73),
674 MTK_FUNCTION(0, "GPIO73"),
675 MTK_FUNCTION(1, "MSDC1_DAT0"),
676 MTK_FUNCTION(7, "DBG_MON_B_24_")
677 ),
678 MTK_PIN(
679 PINCTRL_PIN(74, "MSDC1_DAT1"),
680 NULL, "mt8173",
681 MTK_EINT_FUNCTION(0, 74),
682 MTK_FUNCTION(0, "GPIO74"),
683 MTK_FUNCTION(1, "MSDC1_DAT1"),
684 MTK_FUNCTION(7, "DBG_MON_B_25_")
685 ),
686 MTK_PIN(
687 PINCTRL_PIN(75, "MSDC1_DAT2"),
688 NULL, "mt8173",
689 MTK_EINT_FUNCTION(0, 75),
690 MTK_FUNCTION(0, "GPIO75"),
691 MTK_FUNCTION(1, "MSDC1_DAT2"),
692 MTK_FUNCTION(7, "DBG_MON_B_26_")
693 ),
694 MTK_PIN(
695 PINCTRL_PIN(76, "MSDC1_DAT3"),
696 NULL, "mt8173",
697 MTK_EINT_FUNCTION(0, 76),
698 MTK_FUNCTION(0, "GPIO76"),
699 MTK_FUNCTION(1, "MSDC1_DAT3"),
700 MTK_FUNCTION(7, "DBG_MON_B_27_")
701 ),
702 MTK_PIN(
703 PINCTRL_PIN(77, "MSDC1_CLK"),
704 NULL, "mt8173",
705 MTK_EINT_FUNCTION(0, 77),
706 MTK_FUNCTION(0, "GPIO77"),
707 MTK_FUNCTION(1, "MSDC1_CLK"),
708 MTK_FUNCTION(7, "DBG_MON_B_28_")
709 ),
710 MTK_PIN(
711 PINCTRL_PIN(78, "MSDC1_CMD"),
712 NULL, "mt8173",
713 MTK_EINT_FUNCTION(0, 78),
714 MTK_FUNCTION(0, "GPIO78"),
715 MTK_FUNCTION(1, "MSDC1_CMD"),
716 MTK_FUNCTION(7, "DBG_MON_B_23_")
717 ),
718 MTK_PIN(
719 PINCTRL_PIN(79, "PWRAP_SPI0_MI"),
720 NULL, "mt8173",
721 MTK_EINT_FUNCTION(0, 79),
722 MTK_FUNCTION(0, "GPIO79"),
723 MTK_FUNCTION(1, "PWRAP_SPIMI"),
724 MTK_FUNCTION(2, "PWRAP_SPIMO")
725 ),
726 MTK_PIN(
727 PINCTRL_PIN(80, "PWRAP_SPI0_MO"),
728 NULL, "mt8173",
729 MTK_EINT_FUNCTION(0, 80),
730 MTK_FUNCTION(0, "GPIO80"),
731 MTK_FUNCTION(1, "PWRAP_SPIMO"),
732 MTK_FUNCTION(2, "PWRAP_SPIMI")
733 ),
734 MTK_PIN(
735 PINCTRL_PIN(81, "PWRAP_SPI0_CK"),
736 NULL, "mt8173",
737 MTK_EINT_FUNCTION(0, 81),
738 MTK_FUNCTION(0, "GPIO81"),
739 MTK_FUNCTION(1, "PWRAP_SPICK")
740 ),
741 MTK_PIN(
742 PINCTRL_PIN(82, "PWRAP_SPI0_CSN"),
743 NULL, "mt8173",
744 MTK_EINT_FUNCTION(0, 82),
745 MTK_FUNCTION(0, "GPIO82"),
746 MTK_FUNCTION(1, "PWRAP_SPICS")
747 ),
748 MTK_PIN(
749 PINCTRL_PIN(83, "AUD_CLK_MOSI"),
750 NULL, "mt8173",
751 MTK_EINT_FUNCTION(0, 83),
752 MTK_FUNCTION(0, "GPIO83"),
753 MTK_FUNCTION(1, "AUD_CLK_MOSI")
754 ),
755 MTK_PIN(
756 PINCTRL_PIN(84, "AUD_DAT_MISO"),
757 NULL, "mt8173",
758 MTK_EINT_FUNCTION(0, 84),
759 MTK_FUNCTION(0, "GPIO84"),
760 MTK_FUNCTION(1, "AUD_DAT_MISO"),
761 MTK_FUNCTION(2, "AUD_DAT_MOSI")
762 ),
763 MTK_PIN(
764 PINCTRL_PIN(85, "AUD_DAT_MOSI"),
765 NULL, "mt8173",
766 MTK_EINT_FUNCTION(0, 85),
767 MTK_FUNCTION(0, "GPIO85"),
768 MTK_FUNCTION(1, "AUD_DAT_MOSI"),
769 MTK_FUNCTION(2, "AUD_DAT_MISO")
770 ),
771 MTK_PIN(
772 PINCTRL_PIN(86, "RTC32K_CK"),
773 NULL, "mt8173",
774 MTK_EINT_FUNCTION(0, 86),
775 MTK_FUNCTION(0, "GPIO86"),
776 MTK_FUNCTION(1, "RTC32K_CK")
777 ),
778 MTK_PIN(
779 PINCTRL_PIN(87, "DISP_PWM0"),
780 NULL, "mt8173",
781 MTK_EINT_FUNCTION(0, 87),
782 MTK_FUNCTION(0, "GPIO87"),
783 MTK_FUNCTION(1, "DISP_PWM0"),
784 MTK_FUNCTION(2, "DISP_PWM1"),
785 MTK_FUNCTION(7, "DBG_MON_B_31_")
786 ),
787 MTK_PIN(
788 PINCTRL_PIN(88, "SRCLKENAI"),
789 NULL, "mt8173",
790 MTK_EINT_FUNCTION(0, 88),
791 MTK_FUNCTION(0, "GPIO88"),
792 MTK_FUNCTION(1, "SRCLKENAI")
793 ),
794 MTK_PIN(
795 PINCTRL_PIN(89, "SRCLKENAI2"),
796 NULL, "mt8173",
797 MTK_EINT_FUNCTION(0, 89),
798 MTK_FUNCTION(0, "GPIO89"),
799 MTK_FUNCTION(1, "SRCLKENAI2")
800 ),
801 MTK_PIN(
802 PINCTRL_PIN(90, "SRCLKENA0"),
803 NULL, "mt8173",
804 MTK_EINT_FUNCTION(0, 90),
805 MTK_FUNCTION(0, "GPIO90"),
806 MTK_FUNCTION(1, "SRCLKENA0")
807 ),
808 MTK_PIN(
809 PINCTRL_PIN(91, "SRCLKENA1"),
810 NULL, "mt8173",
811 MTK_EINT_FUNCTION(0, 91),
812 MTK_FUNCTION(0, "GPIO91"),
813 MTK_FUNCTION(1, "SRCLKENA1")
814 ),
815 MTK_PIN(
816 PINCTRL_PIN(92, "PCM_CLK"),
817 NULL, "mt8173",
818 MTK_EINT_FUNCTION(0, 92),
819 MTK_FUNCTION(0, "GPIO92"),
820 MTK_FUNCTION(1, "PCM1_CLK"),
821 MTK_FUNCTION(2, "I2S0_BCK"),
822 MTK_FUNCTION(7, "DBG_MON_A_24_")
823 ),
824 MTK_PIN(
825 PINCTRL_PIN(93, "PCM_SYNC"),
826 NULL, "mt8173",
827 MTK_EINT_FUNCTION(0, 93),
828 MTK_FUNCTION(0, "GPIO93"),
829 MTK_FUNCTION(1, "PCM1_SYNC"),
830 MTK_FUNCTION(2, "I2S0_WS"),
831 MTK_FUNCTION(7, "DBG_MON_A_25_")
832 ),
833 MTK_PIN(
834 PINCTRL_PIN(94, "PCM_RX"),
835 NULL, "mt8173",
836 MTK_EINT_FUNCTION(0, 94),
837 MTK_FUNCTION(0, "GPIO94"),
838 MTK_FUNCTION(1, "PCM1_DI"),
839 MTK_FUNCTION(2, "I2S0_DI"),
840 MTK_FUNCTION(7, "DBG_MON_A_26_")
841 ),
842 MTK_PIN(
843 PINCTRL_PIN(95, "PCM_TX"),
844 NULL, "mt8173",
845 MTK_EINT_FUNCTION(0, 95),
846 MTK_FUNCTION(0, "GPIO95"),
847 MTK_FUNCTION(1, "PCM1_DO"),
848 MTK_FUNCTION(2, "I2S0_DO"),
849 MTK_FUNCTION(7, "DBG_MON_A_27_")
850 ),
851 MTK_PIN(
852 PINCTRL_PIN(96, "URXD1"),
853 NULL, "mt8173",
854 MTK_EINT_FUNCTION(0, 96),
855 MTK_FUNCTION(0, "GPIO96"),
856 MTK_FUNCTION(1, "URXD1"),
857 MTK_FUNCTION(2, "UTXD1"),
858 MTK_FUNCTION(7, "DBG_MON_A_28_")
859 ),
860 MTK_PIN(
861 PINCTRL_PIN(97, "UTXD1"),
862 NULL, "mt8173",
863 MTK_EINT_FUNCTION(0, 97),
864 MTK_FUNCTION(0, "GPIO97"),
865 MTK_FUNCTION(1, "UTXD1"),
866 MTK_FUNCTION(2, "URXD1"),
867 MTK_FUNCTION(7, "DBG_MON_A_29_")
868 ),
869 MTK_PIN(
870 PINCTRL_PIN(98, "URTS1"),
871 NULL, "mt8173",
872 MTK_EINT_FUNCTION(0, 98),
873 MTK_FUNCTION(0, "GPIO98"),
874 MTK_FUNCTION(1, "URTS1"),
875 MTK_FUNCTION(2, "UCTS1"),
876 MTK_FUNCTION(7, "DBG_MON_A_30_")
877 ),
878 MTK_PIN(
879 PINCTRL_PIN(99, "UCTS1"),
880 NULL, "mt8173",
881 MTK_EINT_FUNCTION(0, 99),
882 MTK_FUNCTION(0, "GPIO99"),
883 MTK_FUNCTION(1, "UCTS1"),
884 MTK_FUNCTION(2, "URTS1"),
885 MTK_FUNCTION(7, "DBG_MON_A_31_")
886 ),
887 MTK_PIN(
888 PINCTRL_PIN(100, "MSDC2_DAT0"),
889 NULL, "mt8173",
890 MTK_EINT_FUNCTION(0, 100),
891 MTK_FUNCTION(0, "GPIO100"),
892 MTK_FUNCTION(1, "MSDC2_DAT0"),
893 MTK_FUNCTION(3, "USB_DRVVBUS_P0"),
894 MTK_FUNCTION(4, "SDA5"),
895 MTK_FUNCTION(5, "USB_DRVVBUS_P1"),
896 MTK_FUNCTION(7, "DBG_MON_B_0_")
897 ),
898 MTK_PIN(
899 PINCTRL_PIN(101, "MSDC2_DAT1"),
900 NULL, "mt8173",
901 MTK_EINT_FUNCTION(0, 101),
902 MTK_FUNCTION(0, "GPIO101"),
903 MTK_FUNCTION(1, "MSDC2_DAT1"),
904 MTK_FUNCTION(3, "AUD_SPDIF"),
905 MTK_FUNCTION(4, "SCL5"),
906 MTK_FUNCTION(7, "DBG_MON_B_1_")
907 ),
908 MTK_PIN(
909 PINCTRL_PIN(102, "MSDC2_DAT2"),
910 NULL, "mt8173",
911 MTK_EINT_FUNCTION(0, 102),
912 MTK_FUNCTION(0, "GPIO102"),
913 MTK_FUNCTION(1, "MSDC2_DAT2"),
914 MTK_FUNCTION(3, "UTXD0"),
915 MTK_FUNCTION(5, "PWM0"),
916 MTK_FUNCTION(6, "SPI_CK_1_"),
917 MTK_FUNCTION(7, "DBG_MON_B_2_")
918 ),
919 MTK_PIN(
920 PINCTRL_PIN(103, "MSDC2_DAT3"),
921 NULL, "mt8173",
922 MTK_EINT_FUNCTION(0, 103),
923 MTK_FUNCTION(0, "GPIO103"),
924 MTK_FUNCTION(1, "MSDC2_DAT3"),
925 MTK_FUNCTION(3, "URXD0"),
926 MTK_FUNCTION(5, "PWM1"),
927 MTK_FUNCTION(6, "SPI_MI_1_"),
928 MTK_FUNCTION(7, "DBG_MON_B_3_")
929 ),
930 MTK_PIN(
931 PINCTRL_PIN(104, "MSDC2_CLK"),
932 NULL, "mt8173",
933 MTK_EINT_FUNCTION(0, 104),
934 MTK_FUNCTION(0, "GPIO104"),
935 MTK_FUNCTION(1, "MSDC2_CLK"),
936 MTK_FUNCTION(3, "UTXD3"),
937 MTK_FUNCTION(4, "SDA3"),
938 MTK_FUNCTION(5, "PWM2"),
939 MTK_FUNCTION(6, "SPI_MO_1_"),
940 MTK_FUNCTION(7, "DBG_MON_B_4_")
941 ),
942 MTK_PIN(
943 PINCTRL_PIN(105, "MSDC2_CMD"),
944 NULL, "mt8173",
945 MTK_EINT_FUNCTION(0, 105),
946 MTK_FUNCTION(0, "GPIO105"),
947 MTK_FUNCTION(1, "MSDC2_CMD"),
948 MTK_FUNCTION(3, "URXD3"),
949 MTK_FUNCTION(4, "SCL3"),
950 MTK_FUNCTION(5, "PWM3"),
951 MTK_FUNCTION(6, "SPI_CS_1_"),
952 MTK_FUNCTION(7, "DBG_MON_B_5_")
953 ),
954 MTK_PIN(
955 PINCTRL_PIN(106, "SDA3"),
956 NULL, "mt8173",
957 MTK_EINT_FUNCTION(0, 106),
958 MTK_FUNCTION(0, "GPIO106"),
959 MTK_FUNCTION(1, "SDA3")
960 ),
961 MTK_PIN(
962 PINCTRL_PIN(107, "SCL3"),
963 NULL, "mt8173",
964 MTK_EINT_FUNCTION(0, 107),
965 MTK_FUNCTION(0, "GPIO107"),
966 MTK_FUNCTION(1, "SCL3")
967 ),
968 MTK_PIN(
969 PINCTRL_PIN(108, "JTMS"),
970 NULL, "mt8173",
971 MTK_EINT_FUNCTION(0, 108),
972 MTK_FUNCTION(0, "GPIO108"),
973 MTK_FUNCTION(1, "JTMS"),
974 MTK_FUNCTION(2, " MFG_JTAG_TMS"),
975 MTK_FUNCTION(5, "AP_MD32_JTAG_TMS"),
976 MTK_FUNCTION(6, "DFD_TMS")
977 ),
978 MTK_PIN(
979 PINCTRL_PIN(109, "JTCK"),
980 NULL, "mt8173",
981 MTK_EINT_FUNCTION(0, 109),
982 MTK_FUNCTION(0, "GPIO109"),
983 MTK_FUNCTION(1, "JTCK"),
984 MTK_FUNCTION(2, " MFG_JTAG_TCK"),
985 MTK_FUNCTION(5, "AP_MD32_JTAG_TCK"),
986 MTK_FUNCTION(6, "DFD_TCK")
987 ),
988 MTK_PIN(
989 PINCTRL_PIN(110, "JTDI"),
990 NULL, "mt8173",
991 MTK_EINT_FUNCTION(0, 110),
992 MTK_FUNCTION(0, "GPIO110"),
993 MTK_FUNCTION(1, "JTDI"),
994 MTK_FUNCTION(2, " MFG_JTAG_TDI"),
995 MTK_FUNCTION(5, "AP_MD32_JTAG_TDI"),
996 MTK_FUNCTION(6, "DFD_TDI")
997 ),
998 MTK_PIN(
999 PINCTRL_PIN(111, "JTDO"),
1000 NULL, "mt8173",
1001 MTK_EINT_FUNCTION(0, 111),
1002 MTK_FUNCTION(0, "GPIO111"),
1003 MTK_FUNCTION(1, "JTDO"),
1004 MTK_FUNCTION(2, "MFG_JTAG_TDO"),
1005 MTK_FUNCTION(5, "AP_MD32_JTAG_TDO"),
1006 MTK_FUNCTION(6, "DFD_TDO")
1007 ),
1008 MTK_PIN(
1009 PINCTRL_PIN(112, "JTRST_B"),
1010 NULL, "mt8173",
1011 MTK_EINT_FUNCTION(0, 112),
1012 MTK_FUNCTION(0, "GPIO112"),
1013 MTK_FUNCTION(1, "JTRST_B"),
1014 MTK_FUNCTION(2, " MFG_JTAG_TRSTN"),
1015 MTK_FUNCTION(5, "AP_MD32_JTAG_TRST"),
1016 MTK_FUNCTION(6, "DFD_NTRST")
1017 ),
1018 MTK_PIN(
1019 PINCTRL_PIN(113, "URXD0"),
1020 NULL, "mt8173",
1021 MTK_EINT_FUNCTION(0, 113),
1022 MTK_FUNCTION(0, "GPIO113"),
1023 MTK_FUNCTION(1, "URXD0"),
1024 MTK_FUNCTION(2, "UTXD0"),
1025 MTK_FUNCTION(6, "I2S2_WS"),
1026 MTK_FUNCTION(7, "DBG_MON_A_0_")
1027 ),
1028 MTK_PIN(
1029 PINCTRL_PIN(114, "UTXD0"),
1030 NULL, "mt8173",
1031 MTK_EINT_FUNCTION(0, 114),
1032 MTK_FUNCTION(0, "GPIO114"),
1033 MTK_FUNCTION(1, "UTXD0"),
1034 MTK_FUNCTION(2, "URXD0"),
1035 MTK_FUNCTION(6, "I2S2_BCK"),
1036 MTK_FUNCTION(7, "DBG_MON_A_1_")
1037 ),
1038 MTK_PIN(
1039 PINCTRL_PIN(115, "URTS0"),
1040 NULL, "mt8173",
1041 MTK_EINT_FUNCTION(0, 115),
1042 MTK_FUNCTION(0, "GPIO115"),
1043 MTK_FUNCTION(1, "URTS0"),
1044 MTK_FUNCTION(2, "UCTS0"),
1045 MTK_FUNCTION(6, "I2S2_MCK"),
1046 MTK_FUNCTION(7, "DBG_MON_A_2_")
1047 ),
1048 MTK_PIN(
1049 PINCTRL_PIN(116, "UCTS0"),
1050 NULL, "mt8173",
1051 MTK_EINT_FUNCTION(0, 116),
1052 MTK_FUNCTION(0, "GPIO116"),
1053 MTK_FUNCTION(1, "UCTS0"),
1054 MTK_FUNCTION(2, "URTS0"),
1055 MTK_FUNCTION(6, "I2S2_DI_1"),
1056 MTK_FUNCTION(7, "DBG_MON_A_3_")
1057 ),
1058 MTK_PIN(
1059 PINCTRL_PIN(117, "URXD3"),
1060 NULL, "mt8173",
1061 MTK_EINT_FUNCTION(0, 117),
1062 MTK_FUNCTION(0, "GPIO117"),
1063 MTK_FUNCTION(1, "URXD3"),
1064 MTK_FUNCTION(2, "UTXD3"),
1065 MTK_FUNCTION(7, "DBG_MON_A_9_")
1066 ),
1067 MTK_PIN(
1068 PINCTRL_PIN(118, "UTXD3"),
1069 NULL, "mt8173",
1070 MTK_EINT_FUNCTION(0, 118),
1071 MTK_FUNCTION(0, "GPIO118"),
1072 MTK_FUNCTION(1, "UTXD3"),
1073 MTK_FUNCTION(2, "URXD3"),
1074 MTK_FUNCTION(7, "DBG_MON_A_10_")
1075 ),
1076 MTK_PIN(
1077 PINCTRL_PIN(119, "KPROW0"),
1078 NULL, "mt8173",
1079 MTK_EINT_FUNCTION(0, 119),
1080 MTK_FUNCTION(0, "GPIO119"),
1081 MTK_FUNCTION(1, "KROW0"),
1082 MTK_FUNCTION(7, "DBG_MON_A_11_")
1083 ),
1084 MTK_PIN(
1085 PINCTRL_PIN(120, "KPROW1"),
1086 NULL, "mt8173",
1087 MTK_EINT_FUNCTION(0, 120),
1088 MTK_FUNCTION(0, "GPIO120"),
1089 MTK_FUNCTION(1, "KROW1"),
1090 MTK_FUNCTION(3, "PWM6"),
1091 MTK_FUNCTION(7, "DBG_MON_A_12_")
1092 ),
1093 MTK_PIN(
1094 PINCTRL_PIN(121, "KPROW2"),
1095 NULL, "mt8173",
1096 MTK_EINT_FUNCTION(0, 121),
1097 MTK_FUNCTION(0, "GPIO121"),
1098 MTK_FUNCTION(1, "KROW2"),
1099 MTK_FUNCTION(2, "IRDA_PDN"),
1100 MTK_FUNCTION(3, "USB_DRVVBUS_P0"),
1101 MTK_FUNCTION(4, "PWM4"),
1102 MTK_FUNCTION(5, "USB_DRVVBUS_P1"),
1103 MTK_FUNCTION(7, "DBG_MON_A_13_")
1104 ),
1105 MTK_PIN(
1106 PINCTRL_PIN(122, "KPCOL0"),
1107 NULL, "mt8173",
1108 MTK_EINT_FUNCTION(0, 122),
1109 MTK_FUNCTION(0, "GPIO122"),
1110 MTK_FUNCTION(1, "KCOL0"),
1111 MTK_FUNCTION(7, "DBG_MON_A_14_")
1112 ),
1113 MTK_PIN(
1114 PINCTRL_PIN(123, "KPCOL1"),
1115 NULL, "mt8173",
1116 MTK_EINT_FUNCTION(0, 123),
1117 MTK_FUNCTION(0, "GPIO123"),
1118 MTK_FUNCTION(1, "KCOL1"),
1119 MTK_FUNCTION(2, "IRDA_RXD"),
1120 MTK_FUNCTION(3, "PWM5"),
1121 MTK_FUNCTION(7, "DBG_MON_A_15_")
1122 ),
1123 MTK_PIN(
1124 PINCTRL_PIN(124, "KPCOL2"),
1125 NULL, "mt8173",
1126 MTK_EINT_FUNCTION(0, 124),
1127 MTK_FUNCTION(0, "GPIO124"),
1128 MTK_FUNCTION(1, "KCOL2"),
1129 MTK_FUNCTION(2, "IRDA_TXD"),
1130 MTK_FUNCTION(3, "USB_DRVVBUS_P0"),
1131 MTK_FUNCTION(4, "PWM3"),
1132 MTK_FUNCTION(5, "USB_DRVVBUS_P1"),
1133 MTK_FUNCTION(7, "DBG_MON_A_16_")
1134 ),
1135 MTK_PIN(
1136 PINCTRL_PIN(125, "SDA1"),
1137 NULL, "mt8173",
1138 MTK_EINT_FUNCTION(0, 125),
1139 MTK_FUNCTION(0, "GPIO125"),
1140 MTK_FUNCTION(1, "SDA1")
1141 ),
1142 MTK_PIN(
1143 PINCTRL_PIN(126, "SCL1"),
1144 NULL, "mt8173",
1145 MTK_EINT_FUNCTION(0, 126),
1146 MTK_FUNCTION(0, "GPIO126"),
1147 MTK_FUNCTION(1, "SCL1")
1148 ),
1149 MTK_PIN(
1150 PINCTRL_PIN(127, "LCM_RST"),
1151 NULL, "mt8173",
1152 MTK_EINT_FUNCTION(0, 127),
1153 MTK_FUNCTION(0, "GPIO127"),
1154 MTK_FUNCTION(1, "LCM_RST")
1155 ),
1156 MTK_PIN(
1157 PINCTRL_PIN(128, "I2S0_LRCK"),
1158 NULL, "mt8173",
1159 MTK_EINT_FUNCTION(0, 128),
1160 MTK_FUNCTION(0, "GPIO128"),
1161 MTK_FUNCTION(1, "I2S0_WS"),
1162 MTK_FUNCTION(2, "I2S1_WS"),
1163 MTK_FUNCTION(3, "I2S2_WS"),
1164 MTK_FUNCTION(5, "SPI_CK_2_"),
1165 MTK_FUNCTION(7, "DBG_MON_A_4_")
1166 ),
1167 MTK_PIN(
1168 PINCTRL_PIN(129, "I2S0_BCK"),
1169 NULL, "mt8173",
1170 MTK_EINT_FUNCTION(0, 129),
1171 MTK_FUNCTION(0, "GPIO129"),
1172 MTK_FUNCTION(1, "I2S0_BCK"),
1173 MTK_FUNCTION(2, "I2S1_BCK"),
1174 MTK_FUNCTION(3, "I2S2_BCK"),
1175 MTK_FUNCTION(5, "SPI_MI_2_"),
1176 MTK_FUNCTION(7, "DBG_MON_A_5_")
1177 ),
1178 MTK_PIN(
1179 PINCTRL_PIN(130, "I2S0_MCK"),
1180 NULL, "mt8173",
1181 MTK_EINT_FUNCTION(0, 130),
1182 MTK_FUNCTION(0, "GPIO130"),
1183 MTK_FUNCTION(1, "I2S0_MCK"),
1184 MTK_FUNCTION(2, "I2S1_MCK"),
1185 MTK_FUNCTION(3, "I2S2_MCK"),
1186 MTK_FUNCTION(5, "SPI_MO_2_"),
1187 MTK_FUNCTION(7, "DBG_MON_A_6_")
1188 ),
1189 MTK_PIN(
1190 PINCTRL_PIN(131, "I2S0_DATA0"),
1191 NULL, "mt8173",
1192 MTK_EINT_FUNCTION(0, 131),
1193 MTK_FUNCTION(0, "GPIO131"),
1194 MTK_FUNCTION(1, "I2S0_DO"),
1195 MTK_FUNCTION(2, "I2S1_DO_1"),
1196 MTK_FUNCTION(3, "I2S2_DI_1"),
1197 MTK_FUNCTION(5, "SPI_CS_2_"),
1198 MTK_FUNCTION(7, "DBG_MON_A_7_")
1199 ),
1200 MTK_PIN(
1201 PINCTRL_PIN(132, "I2S0_DATA1"),
1202 NULL, "mt8173",
1203 MTK_EINT_FUNCTION(0, 132),
1204 MTK_FUNCTION(0, "GPIO132"),
1205 MTK_FUNCTION(1, "I2S0_DI"),
1206 MTK_FUNCTION(2, "I2S1_DO_2"),
1207 MTK_FUNCTION(3, "I2S2_DI_2"),
1208 MTK_FUNCTION(7, "DBG_MON_A_8_")
1209 ),
1210 MTK_PIN(
1211 PINCTRL_PIN(133, "SDA4"),
1212 NULL, "mt8173",
1213 MTK_EINT_FUNCTION(0, 133),
1214 MTK_FUNCTION(0, "GPIO133"),
1215 MTK_FUNCTION(1, "SDA4")
1216 ),
1217 MTK_PIN(
1218 PINCTRL_PIN(134, "SCL4"),
1219 NULL, "mt8173",
1220 MTK_EINT_FUNCTION(0, 134),
1221 MTK_FUNCTION(0, "GPIO134"),
1222 MTK_FUNCTION(1, "SCL4")
1223 ),
1224};
1225
1226#endif /* __PINCTRL_MTK_MT8173_H */
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index eafc216067a4..c751d22fdf29 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -1,2 +1,2 @@
1obj-y += pinctrl-meson8.o 1obj-y += pinctrl-meson8.o pinctrl-meson8b.o
2obj-y += pinctrl-meson.o 2obj-y += pinctrl-meson.o
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index a2bf49ce16e7..edcd140e0899 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -13,8 +13,9 @@
13 13
14/* 14/*
15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO, 15 * The available pins are organized in banks (A,B,C,D,E,X,Y,Z,AO,
16 * BOOT,CARD for meson6 and X,Y,DV,H,Z,AO,BOOT,CARD for meson8) and 16 * BOOT,CARD for meson6, X,Y,DV,H,Z,AO,BOOT,CARD for meson8 and
17 * each bank has a variable number of pins. 17 * X,Y,DV,H,AO,BOOT,CARD,DIF for meson8b) and each bank has a
18 * variable number of pins.
18 * 19 *
19 * The AO bank is special because it belongs to the Always-On power 20 * The AO bank is special because it belongs to the Always-On power
20 * domain which can't be powered off; the bank also uses a set of 21 * domain which can't be powered off; the bank also uses a set of
@@ -544,6 +545,10 @@ static const struct of_device_id meson_pinctrl_dt_match[] = {
544 .compatible = "amlogic,meson8-pinctrl", 545 .compatible = "amlogic,meson8-pinctrl",
545 .data = &meson8_pinctrl_data, 546 .data = &meson8_pinctrl_data,
546 }, 547 },
548 {
549 .compatible = "amlogic,meson8b-pinctrl",
550 .data = &meson8b_pinctrl_data,
551 },
547 { }, 552 { },
548}; 553};
549MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match); 554MODULE_DEVICE_TABLE(of, meson_pinctrl_dt_match);
diff --git a/drivers/pinctrl/meson/pinctrl-meson.h b/drivers/pinctrl/meson/pinctrl-meson.h
index bfea8adc7953..0fe7d53849ce 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.h
+++ b/drivers/pinctrl/meson/pinctrl-meson.h
@@ -155,6 +155,8 @@ struct meson_pinctrl {
155 struct meson_domain *domains; 155 struct meson_domain *domains;
156}; 156};
157 157
158#define PIN(x, b) (b + x)
159
158#define GROUP(grp, r, b) \ 160#define GROUP(grp, r, b) \
159 { \ 161 { \
160 .name = #grp, \ 162 .name = #grp, \
@@ -165,10 +167,10 @@ struct meson_pinctrl {
165 .domain = 0, \ 167 .domain = 0, \
166 } 168 }
167 169
168#define GPIO_GROUP(gpio) \ 170#define GPIO_GROUP(gpio, b) \
169 { \ 171 { \
170 .name = #gpio, \ 172 .name = #gpio, \
171 .pins = (const unsigned int[]){ PIN_ ## gpio}, \ 173 .pins = (const unsigned int[]){ PIN(gpio, b) }, \
172 .num_pins = 1, \ 174 .num_pins = 1, \
173 .is_gpio = true, \ 175 .is_gpio = true, \
174 } 176 }
@@ -204,6 +206,7 @@ struct meson_pinctrl {
204 }, \ 206 }, \
205 } 207 }
206 208
207#define MESON_PIN(x) PINCTRL_PIN(PIN_ ## x, #x) 209#define MESON_PIN(x, b) PINCTRL_PIN(PIN(x, b), #x)
208 210
209extern struct meson_pinctrl_data meson8_pinctrl_data; 211extern struct meson_pinctrl_data meson8_pinctrl_data;
212extern struct meson_pinctrl_data meson8b_pinctrl_data;
diff --git a/drivers/pinctrl/meson/pinctrl-meson8.c b/drivers/pinctrl/meson/pinctrl-meson8.c
index f8aa3a281767..7b1cc91733ef 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8.c
@@ -14,620 +14,482 @@
14#include <dt-bindings/gpio/meson8-gpio.h> 14#include <dt-bindings/gpio/meson8-gpio.h>
15#include "pinctrl-meson.h" 15#include "pinctrl-meson.h"
16 16
17#define AO_OFFSET 120 17#define AO_OFF 120
18
19#define PIN_GPIOX_0 GPIOX_0
20#define PIN_GPIOX_1 GPIOX_1
21#define PIN_GPIOX_2 GPIOX_2
22#define PIN_GPIOX_3 GPIOX_3
23#define PIN_GPIOX_4 GPIOX_4
24#define PIN_GPIOX_5 GPIOX_5
25#define PIN_GPIOX_6 GPIOX_6
26#define PIN_GPIOX_7 GPIOX_7
27#define PIN_GPIOX_8 GPIOX_8
28#define PIN_GPIOX_9 GPIOX_9
29#define PIN_GPIOX_10 GPIOX_10
30#define PIN_GPIOX_11 GPIOX_11
31#define PIN_GPIOX_12 GPIOX_12
32#define PIN_GPIOX_13 GPIOX_13
33#define PIN_GPIOX_14 GPIOX_14
34#define PIN_GPIOX_15 GPIOX_15
35#define PIN_GPIOX_16 GPIOX_16
36#define PIN_GPIOX_17 GPIOX_17
37#define PIN_GPIOX_18 GPIOX_18
38#define PIN_GPIOX_19 GPIOX_19
39#define PIN_GPIOX_20 GPIOX_20
40#define PIN_GPIOX_21 GPIOX_21
41#define PIN_GPIOY_0 GPIOY_0
42#define PIN_GPIOY_1 GPIOY_1
43#define PIN_GPIOY_2 GPIOY_2
44#define PIN_GPIOY_3 GPIOY_3
45#define PIN_GPIOY_4 GPIOY_4
46#define PIN_GPIOY_5 GPIOY_5
47#define PIN_GPIOY_6 GPIOY_6
48#define PIN_GPIOY_7 GPIOY_7
49#define PIN_GPIOY_8 GPIOY_8
50#define PIN_GPIOY_9 GPIOY_9
51#define PIN_GPIOY_10 GPIOY_10
52#define PIN_GPIOY_11 GPIOY_11
53#define PIN_GPIOY_12 GPIOY_12
54#define PIN_GPIOY_13 GPIOY_13
55#define PIN_GPIOY_14 GPIOY_14
56#define PIN_GPIOY_15 GPIOY_15
57#define PIN_GPIOY_16 GPIOY_16
58#define PIN_GPIODV_0 GPIODV_0
59#define PIN_GPIODV_1 GPIODV_1
60#define PIN_GPIODV_2 GPIODV_2
61#define PIN_GPIODV_3 GPIODV_3
62#define PIN_GPIODV_4 GPIODV_4
63#define PIN_GPIODV_5 GPIODV_5
64#define PIN_GPIODV_6 GPIODV_6
65#define PIN_GPIODV_7 GPIODV_7
66#define PIN_GPIODV_8 GPIODV_8
67#define PIN_GPIODV_9 GPIODV_9
68#define PIN_GPIODV_10 GPIODV_10
69#define PIN_GPIODV_11 GPIODV_11
70#define PIN_GPIODV_12 GPIODV_12
71#define PIN_GPIODV_13 GPIODV_13
72#define PIN_GPIODV_14 GPIODV_14
73#define PIN_GPIODV_15 GPIODV_15
74#define PIN_GPIODV_16 GPIODV_16
75#define PIN_GPIODV_17 GPIODV_17
76#define PIN_GPIODV_18 GPIODV_18
77#define PIN_GPIODV_19 GPIODV_19
78#define PIN_GPIODV_20 GPIODV_20
79#define PIN_GPIODV_21 GPIODV_21
80#define PIN_GPIODV_22 GPIODV_22
81#define PIN_GPIODV_23 GPIODV_23
82#define PIN_GPIODV_24 GPIODV_24
83#define PIN_GPIODV_25 GPIODV_25
84#define PIN_GPIODV_26 GPIODV_26
85#define PIN_GPIODV_27 GPIODV_27
86#define PIN_GPIODV_28 GPIODV_28
87#define PIN_GPIODV_29 GPIODV_29
88#define PIN_GPIOH_0 GPIOH_0
89#define PIN_GPIOH_1 GPIOH_1
90#define PIN_GPIOH_2 GPIOH_2
91#define PIN_GPIOH_3 GPIOH_3
92#define PIN_GPIOH_4 GPIOH_4
93#define PIN_GPIOH_5 GPIOH_5
94#define PIN_GPIOH_6 GPIOH_6
95#define PIN_GPIOH_7 GPIOH_7
96#define PIN_GPIOH_8 GPIOH_8
97#define PIN_GPIOH_9 GPIOH_9
98#define PIN_GPIOZ_0 GPIOZ_0
99#define PIN_GPIOZ_1 GPIOZ_1
100#define PIN_GPIOZ_2 GPIOZ_2
101#define PIN_GPIOZ_3 GPIOZ_3
102#define PIN_GPIOZ_4 GPIOZ_4
103#define PIN_GPIOZ_5 GPIOZ_5
104#define PIN_GPIOZ_6 GPIOZ_6
105#define PIN_GPIOZ_7 GPIOZ_7
106#define PIN_GPIOZ_8 GPIOZ_8
107#define PIN_GPIOZ_9 GPIOZ_9
108#define PIN_GPIOZ_10 GPIOZ_10
109#define PIN_GPIOZ_11 GPIOZ_11
110#define PIN_GPIOZ_12 GPIOZ_12
111#define PIN_GPIOZ_13 GPIOZ_13
112#define PIN_GPIOZ_14 GPIOZ_14
113#define PIN_CARD_0 CARD_0
114#define PIN_CARD_1 CARD_1
115#define PIN_CARD_2 CARD_2
116#define PIN_CARD_3 CARD_3
117#define PIN_CARD_4 CARD_4
118#define PIN_CARD_5 CARD_5
119#define PIN_CARD_6 CARD_6
120#define PIN_BOOT_0 BOOT_0
121#define PIN_BOOT_1 BOOT_1
122#define PIN_BOOT_2 BOOT_2
123#define PIN_BOOT_3 BOOT_3
124#define PIN_BOOT_4 BOOT_4
125#define PIN_BOOT_5 BOOT_5
126#define PIN_BOOT_6 BOOT_6
127#define PIN_BOOT_7 BOOT_7
128#define PIN_BOOT_8 BOOT_8
129#define PIN_BOOT_9 BOOT_9
130#define PIN_BOOT_10 BOOT_10
131#define PIN_BOOT_11 BOOT_11
132#define PIN_BOOT_12 BOOT_12
133#define PIN_BOOT_13 BOOT_13
134#define PIN_BOOT_14 BOOT_14
135#define PIN_BOOT_15 BOOT_15
136#define PIN_BOOT_16 BOOT_16
137#define PIN_BOOT_17 BOOT_17
138#define PIN_BOOT_18 BOOT_18
139
140#define PIN_GPIOAO_0 (AO_OFFSET + GPIOAO_0)
141#define PIN_GPIOAO_1 (AO_OFFSET + GPIOAO_1)
142#define PIN_GPIOAO_2 (AO_OFFSET + GPIOAO_2)
143#define PIN_GPIOAO_3 (AO_OFFSET + GPIOAO_3)
144#define PIN_GPIOAO_4 (AO_OFFSET + GPIOAO_4)
145#define PIN_GPIOAO_5 (AO_OFFSET + GPIOAO_5)
146#define PIN_GPIOAO_6 (AO_OFFSET + GPIOAO_6)
147#define PIN_GPIOAO_7 (AO_OFFSET + GPIOAO_7)
148#define PIN_GPIOAO_8 (AO_OFFSET + GPIOAO_8)
149#define PIN_GPIOAO_9 (AO_OFFSET + GPIOAO_9)
150#define PIN_GPIOAO_10 (AO_OFFSET + GPIOAO_10)
151#define PIN_GPIOAO_11 (AO_OFFSET + GPIOAO_11)
152#define PIN_GPIOAO_12 (AO_OFFSET + GPIOAO_12)
153#define PIN_GPIOAO_13 (AO_OFFSET + GPIOAO_13)
154#define PIN_GPIO_BSD_EN (AO_OFFSET + GPIO_BSD_EN)
155#define PIN_GPIO_TEST_N (AO_OFFSET + GPIO_TEST_N)
156 18
157static const struct pinctrl_pin_desc meson8_pins[] = { 19static const struct pinctrl_pin_desc meson8_pins[] = {
158 MESON_PIN(GPIOX_0), 20 MESON_PIN(GPIOX_0, 0),
159 MESON_PIN(GPIOX_1), 21 MESON_PIN(GPIOX_1, 0),
160 MESON_PIN(GPIOX_2), 22 MESON_PIN(GPIOX_2, 0),
161 MESON_PIN(GPIOX_3), 23 MESON_PIN(GPIOX_3, 0),
162 MESON_PIN(GPIOX_4), 24 MESON_PIN(GPIOX_4, 0),
163 MESON_PIN(GPIOX_5), 25 MESON_PIN(GPIOX_5, 0),
164 MESON_PIN(GPIOX_6), 26 MESON_PIN(GPIOX_6, 0),
165 MESON_PIN(GPIOX_7), 27 MESON_PIN(GPIOX_7, 0),
166 MESON_PIN(GPIOX_8), 28 MESON_PIN(GPIOX_8, 0),
167 MESON_PIN(GPIOX_9), 29 MESON_PIN(GPIOX_9, 0),
168 MESON_PIN(GPIOX_10), 30 MESON_PIN(GPIOX_10, 0),
169 MESON_PIN(GPIOX_11), 31 MESON_PIN(GPIOX_11, 0),
170 MESON_PIN(GPIOX_12), 32 MESON_PIN(GPIOX_12, 0),
171 MESON_PIN(GPIOX_13), 33 MESON_PIN(GPIOX_13, 0),
172 MESON_PIN(GPIOX_14), 34 MESON_PIN(GPIOX_14, 0),
173 MESON_PIN(GPIOX_15), 35 MESON_PIN(GPIOX_15, 0),
174 MESON_PIN(GPIOX_16), 36 MESON_PIN(GPIOX_16, 0),
175 MESON_PIN(GPIOX_17), 37 MESON_PIN(GPIOX_17, 0),
176 MESON_PIN(GPIOX_18), 38 MESON_PIN(GPIOX_18, 0),
177 MESON_PIN(GPIOX_19), 39 MESON_PIN(GPIOX_19, 0),
178 MESON_PIN(GPIOX_20), 40 MESON_PIN(GPIOX_20, 0),
179 MESON_PIN(GPIOX_21), 41 MESON_PIN(GPIOX_21, 0),
180 MESON_PIN(GPIOY_0), 42 MESON_PIN(GPIOY_0, 0),
181 MESON_PIN(GPIOY_1), 43 MESON_PIN(GPIOY_1, 0),
182 MESON_PIN(GPIOY_2), 44 MESON_PIN(GPIOY_2, 0),
183 MESON_PIN(GPIOY_3), 45 MESON_PIN(GPIOY_3, 0),
184 MESON_PIN(GPIOY_4), 46 MESON_PIN(GPIOY_4, 0),
185 MESON_PIN(GPIOY_5), 47 MESON_PIN(GPIOY_5, 0),
186 MESON_PIN(GPIOY_6), 48 MESON_PIN(GPIOY_6, 0),
187 MESON_PIN(GPIOY_7), 49 MESON_PIN(GPIOY_7, 0),
188 MESON_PIN(GPIOY_8), 50 MESON_PIN(GPIOY_8, 0),
189 MESON_PIN(GPIOY_9), 51 MESON_PIN(GPIOY_9, 0),
190 MESON_PIN(GPIOY_10), 52 MESON_PIN(GPIOY_10, 0),
191 MESON_PIN(GPIOY_11), 53 MESON_PIN(GPIOY_11, 0),
192 MESON_PIN(GPIOY_12), 54 MESON_PIN(GPIOY_12, 0),
193 MESON_PIN(GPIOY_13), 55 MESON_PIN(GPIOY_13, 0),
194 MESON_PIN(GPIOY_14), 56 MESON_PIN(GPIOY_14, 0),
195 MESON_PIN(GPIOY_15), 57 MESON_PIN(GPIOY_15, 0),
196 MESON_PIN(GPIOY_16), 58 MESON_PIN(GPIOY_16, 0),
197 MESON_PIN(GPIODV_0), 59 MESON_PIN(GPIODV_0, 0),
198 MESON_PIN(GPIODV_1), 60 MESON_PIN(GPIODV_1, 0),
199 MESON_PIN(GPIODV_2), 61 MESON_PIN(GPIODV_2, 0),
200 MESON_PIN(GPIODV_3), 62 MESON_PIN(GPIODV_3, 0),
201 MESON_PIN(GPIODV_4), 63 MESON_PIN(GPIODV_4, 0),
202 MESON_PIN(GPIODV_5), 64 MESON_PIN(GPIODV_5, 0),
203 MESON_PIN(GPIODV_6), 65 MESON_PIN(GPIODV_6, 0),
204 MESON_PIN(GPIODV_7), 66 MESON_PIN(GPIODV_7, 0),
205 MESON_PIN(GPIODV_8), 67 MESON_PIN(GPIODV_8, 0),
206 MESON_PIN(GPIODV_9), 68 MESON_PIN(GPIODV_9, 0),
207 MESON_PIN(GPIODV_10), 69 MESON_PIN(GPIODV_10, 0),
208 MESON_PIN(GPIODV_11), 70 MESON_PIN(GPIODV_11, 0),
209 MESON_PIN(GPIODV_12), 71 MESON_PIN(GPIODV_12, 0),
210 MESON_PIN(GPIODV_13), 72 MESON_PIN(GPIODV_13, 0),
211 MESON_PIN(GPIODV_14), 73 MESON_PIN(GPIODV_14, 0),
212 MESON_PIN(GPIODV_15), 74 MESON_PIN(GPIODV_15, 0),
213 MESON_PIN(GPIODV_16), 75 MESON_PIN(GPIODV_16, 0),
214 MESON_PIN(GPIODV_17), 76 MESON_PIN(GPIODV_17, 0),
215 MESON_PIN(GPIODV_18), 77 MESON_PIN(GPIODV_18, 0),
216 MESON_PIN(GPIODV_19), 78 MESON_PIN(GPIODV_19, 0),
217 MESON_PIN(GPIODV_20), 79 MESON_PIN(GPIODV_20, 0),
218 MESON_PIN(GPIODV_21), 80 MESON_PIN(GPIODV_21, 0),
219 MESON_PIN(GPIODV_22), 81 MESON_PIN(GPIODV_22, 0),
220 MESON_PIN(GPIODV_23), 82 MESON_PIN(GPIODV_23, 0),
221 MESON_PIN(GPIODV_24), 83 MESON_PIN(GPIODV_24, 0),
222 MESON_PIN(GPIODV_25), 84 MESON_PIN(GPIODV_25, 0),
223 MESON_PIN(GPIODV_26), 85 MESON_PIN(GPIODV_26, 0),
224 MESON_PIN(GPIODV_27), 86 MESON_PIN(GPIODV_27, 0),
225 MESON_PIN(GPIODV_28), 87 MESON_PIN(GPIODV_28, 0),
226 MESON_PIN(GPIODV_29), 88 MESON_PIN(GPIODV_29, 0),
227 MESON_PIN(GPIOH_0), 89 MESON_PIN(GPIOH_0, 0),
228 MESON_PIN(GPIOH_1), 90 MESON_PIN(GPIOH_1, 0),
229 MESON_PIN(GPIOH_2), 91 MESON_PIN(GPIOH_2, 0),
230 MESON_PIN(GPIOH_3), 92 MESON_PIN(GPIOH_3, 0),
231 MESON_PIN(GPIOH_4), 93 MESON_PIN(GPIOH_4, 0),
232 MESON_PIN(GPIOH_5), 94 MESON_PIN(GPIOH_5, 0),
233 MESON_PIN(GPIOH_6), 95 MESON_PIN(GPIOH_6, 0),
234 MESON_PIN(GPIOH_7), 96 MESON_PIN(GPIOH_7, 0),
235 MESON_PIN(GPIOH_8), 97 MESON_PIN(GPIOH_8, 0),
236 MESON_PIN(GPIOH_9), 98 MESON_PIN(GPIOH_9, 0),
237 MESON_PIN(GPIOZ_0), 99 MESON_PIN(GPIOZ_0, 0),
238 MESON_PIN(GPIOZ_1), 100 MESON_PIN(GPIOZ_1, 0),
239 MESON_PIN(GPIOZ_2), 101 MESON_PIN(GPIOZ_2, 0),
240 MESON_PIN(GPIOZ_3), 102 MESON_PIN(GPIOZ_3, 0),
241 MESON_PIN(GPIOZ_4), 103 MESON_PIN(GPIOZ_4, 0),
242 MESON_PIN(GPIOZ_5), 104 MESON_PIN(GPIOZ_5, 0),
243 MESON_PIN(GPIOZ_6), 105 MESON_PIN(GPIOZ_6, 0),
244 MESON_PIN(GPIOZ_7), 106 MESON_PIN(GPIOZ_7, 0),
245 MESON_PIN(GPIOZ_8), 107 MESON_PIN(GPIOZ_8, 0),
246 MESON_PIN(GPIOZ_9), 108 MESON_PIN(GPIOZ_9, 0),
247 MESON_PIN(GPIOZ_10), 109 MESON_PIN(GPIOZ_10, 0),
248 MESON_PIN(GPIOZ_11), 110 MESON_PIN(GPIOZ_11, 0),
249 MESON_PIN(GPIOZ_12), 111 MESON_PIN(GPIOZ_12, 0),
250 MESON_PIN(GPIOZ_13), 112 MESON_PIN(GPIOZ_13, 0),
251 MESON_PIN(GPIOZ_14), 113 MESON_PIN(GPIOZ_14, 0),
252 MESON_PIN(CARD_0), 114 MESON_PIN(CARD_0, 0),
253 MESON_PIN(CARD_1), 115 MESON_PIN(CARD_1, 0),
254 MESON_PIN(CARD_2), 116 MESON_PIN(CARD_2, 0),
255 MESON_PIN(CARD_3), 117 MESON_PIN(CARD_3, 0),
256 MESON_PIN(CARD_4), 118 MESON_PIN(CARD_4, 0),
257 MESON_PIN(CARD_5), 119 MESON_PIN(CARD_5, 0),
258 MESON_PIN(CARD_6), 120 MESON_PIN(CARD_6, 0),
259 MESON_PIN(BOOT_0), 121 MESON_PIN(BOOT_0, 0),
260 MESON_PIN(BOOT_1), 122 MESON_PIN(BOOT_1, 0),
261 MESON_PIN(BOOT_2), 123 MESON_PIN(BOOT_2, 0),
262 MESON_PIN(BOOT_3), 124 MESON_PIN(BOOT_3, 0),
263 MESON_PIN(BOOT_4), 125 MESON_PIN(BOOT_4, 0),
264 MESON_PIN(BOOT_5), 126 MESON_PIN(BOOT_5, 0),
265 MESON_PIN(BOOT_6), 127 MESON_PIN(BOOT_6, 0),
266 MESON_PIN(BOOT_7), 128 MESON_PIN(BOOT_7, 0),
267 MESON_PIN(BOOT_8), 129 MESON_PIN(BOOT_8, 0),
268 MESON_PIN(BOOT_9), 130 MESON_PIN(BOOT_9, 0),
269 MESON_PIN(BOOT_10), 131 MESON_PIN(BOOT_10, 0),
270 MESON_PIN(BOOT_11), 132 MESON_PIN(BOOT_11, 0),
271 MESON_PIN(BOOT_12), 133 MESON_PIN(BOOT_12, 0),
272 MESON_PIN(BOOT_13), 134 MESON_PIN(BOOT_13, 0),
273 MESON_PIN(BOOT_14), 135 MESON_PIN(BOOT_14, 0),
274 MESON_PIN(BOOT_15), 136 MESON_PIN(BOOT_15, 0),
275 MESON_PIN(BOOT_16), 137 MESON_PIN(BOOT_16, 0),
276 MESON_PIN(BOOT_17), 138 MESON_PIN(BOOT_17, 0),
277 MESON_PIN(BOOT_18), 139 MESON_PIN(BOOT_18, 0),
278 MESON_PIN(GPIOAO_0), 140 MESON_PIN(GPIOAO_0, AO_OFF),
279 MESON_PIN(GPIOAO_1), 141 MESON_PIN(GPIOAO_1, AO_OFF),
280 MESON_PIN(GPIOAO_2), 142 MESON_PIN(GPIOAO_2, AO_OFF),
281 MESON_PIN(GPIOAO_3), 143 MESON_PIN(GPIOAO_3, AO_OFF),
282 MESON_PIN(GPIOAO_4), 144 MESON_PIN(GPIOAO_4, AO_OFF),
283 MESON_PIN(GPIOAO_5), 145 MESON_PIN(GPIOAO_5, AO_OFF),
284 MESON_PIN(GPIOAO_6), 146 MESON_PIN(GPIOAO_6, AO_OFF),
285 MESON_PIN(GPIOAO_7), 147 MESON_PIN(GPIOAO_7, AO_OFF),
286 MESON_PIN(GPIOAO_8), 148 MESON_PIN(GPIOAO_8, AO_OFF),
287 MESON_PIN(GPIOAO_9), 149 MESON_PIN(GPIOAO_9, AO_OFF),
288 MESON_PIN(GPIOAO_10), 150 MESON_PIN(GPIOAO_10, AO_OFF),
289 MESON_PIN(GPIOAO_11), 151 MESON_PIN(GPIOAO_11, AO_OFF),
290 MESON_PIN(GPIOAO_12), 152 MESON_PIN(GPIOAO_12, AO_OFF),
291 MESON_PIN(GPIOAO_13), 153 MESON_PIN(GPIOAO_13, AO_OFF),
292 MESON_PIN(GPIO_BSD_EN), 154 MESON_PIN(GPIO_BSD_EN, AO_OFF),
293 MESON_PIN(GPIO_TEST_N), 155 MESON_PIN(GPIO_TEST_N, AO_OFF),
294}; 156};
295 157
296/* bank X */ 158/* bank X */
297static const unsigned int sd_d0_a_pins[] = { PIN_GPIOX_0 }; 159static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) };
298static const unsigned int sd_d1_a_pins[] = { PIN_GPIOX_1 }; 160static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) };
299static const unsigned int sd_d2_a_pins[] = { PIN_GPIOX_2 }; 161static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) };
300static const unsigned int sd_d3_a_pins[] = { PIN_GPIOX_3 }; 162static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) };
301static const unsigned int sd_clk_a_pins[] = { PIN_GPIOX_8 }; 163static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) };
302static const unsigned int sd_cmd_a_pins[] = { PIN_GPIOX_9 }; 164static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
303 165
304static const unsigned int sdxc_d0_a_pins[] = { PIN_GPIOX_0 }; 166static const unsigned int sdxc_d0_a_pins[] = { PIN(GPIOX_0, 0) };
305static const unsigned int sdxc_d13_a_pins[] = { PIN_GPIOX_1, PIN_GPIOX_2, 167static const unsigned int sdxc_d13_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0),
306 PIN_GPIOX_3 }; 168 PIN(GPIOX_3, 0) };
307static const unsigned int sdxc_d47_a_pins[] = { PIN_GPIOX_4, PIN_GPIOX_5, 169static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0),
308 PIN_GPIOX_6, PIN_GPIOX_7 }; 170 PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) };
309static const unsigned int sdxc_clk_a_pins[] = { PIN_GPIOX_8 }; 171static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) };
310static const unsigned int sdxc_cmd_a_pins[] = { PIN_GPIOX_9 }; 172static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
311 173
312static const unsigned int pcm_out_a_pins[] = { PIN_GPIOX_4 }; 174static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) };
313static const unsigned int pcm_in_a_pins[] = { PIN_GPIOX_5 }; 175static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) };
314static const unsigned int pcm_fs_a_pins[] = { PIN_GPIOX_6 }; 176static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) };
315static const unsigned int pcm_clk_a_pins[] = { PIN_GPIOX_7 }; 177static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) };
316 178
317static const unsigned int uart_tx_a0_pins[] = { PIN_GPIOX_4 }; 179static const unsigned int uart_tx_a0_pins[] = { PIN(GPIOX_4, 0) };
318static const unsigned int uart_rx_a0_pins[] = { PIN_GPIOX_5 }; 180static const unsigned int uart_rx_a0_pins[] = { PIN(GPIOX_5, 0) };
319static const unsigned int uart_cts_a0_pins[] = { PIN_GPIOX_6 }; 181static const unsigned int uart_cts_a0_pins[] = { PIN(GPIOX_6, 0) };
320static const unsigned int uart_rts_a0_pins[] = { PIN_GPIOX_7 }; 182static const unsigned int uart_rts_a0_pins[] = { PIN(GPIOX_7, 0) };
321 183
322static const unsigned int uart_tx_a1_pins[] = { PIN_GPIOX_12 }; 184static const unsigned int uart_tx_a1_pins[] = { PIN(GPIOX_12, 0) };
323static const unsigned int uart_rx_a1_pins[] = { PIN_GPIOX_13 }; 185static const unsigned int uart_rx_a1_pins[] = { PIN(GPIOX_13, 0) };
324static const unsigned int uart_cts_a1_pins[] = { PIN_GPIOX_14 }; 186static const unsigned int uart_cts_a1_pins[] = { PIN(GPIOX_14, 0) };
325static const unsigned int uart_rts_a1_pins[] = { PIN_GPIOX_15 }; 187static const unsigned int uart_rts_a1_pins[] = { PIN(GPIOX_15, 0) };
326 188
327static const unsigned int uart_tx_b0_pins[] = { PIN_GPIOX_16 }; 189static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) };
328static const unsigned int uart_rx_b0_pins[] = { PIN_GPIOX_17 }; 190static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) };
329static const unsigned int uart_cts_b0_pins[] = { PIN_GPIOX_18 }; 191static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) };
330static const unsigned int uart_rts_b0_pins[] = { PIN_GPIOX_19 }; 192static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) };
331 193
332static const unsigned int iso7816_det_pins[] = { PIN_GPIOX_16 }; 194static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) };
333static const unsigned int iso7816_reset_pins[] = { PIN_GPIOX_17 }; 195static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) };
334static const unsigned int iso7816_clk_pins[] = { PIN_GPIOX_18 }; 196static const unsigned int iso7816_clk_pins[] = { PIN(GPIOX_18, 0) };
335static const unsigned int iso7816_data_pins[] = { PIN_GPIOX_19 }; 197static const unsigned int iso7816_data_pins[] = { PIN(GPIOX_19, 0) };
336 198
337static const unsigned int i2c_sda_d0_pins[] = { PIN_GPIOX_16 }; 199static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) };
338static const unsigned int i2c_sck_d0_pins[] = { PIN_GPIOX_17 }; 200static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) };
339 201
340static const unsigned int xtal_32k_out_pins[] = { PIN_GPIOX_10 }; 202static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) };
341static const unsigned int xtal_24m_out_pins[] = { PIN_GPIOX_11 }; 203static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) };
342 204
343/* bank Y */ 205/* bank Y */
344static const unsigned int uart_tx_c_pins[] = { PIN_GPIOY_0 }; 206static const unsigned int uart_tx_c_pins[] = { PIN(GPIOY_0, 0) };
345static const unsigned int uart_rx_c_pins[] = { PIN_GPIOY_1 }; 207static const unsigned int uart_rx_c_pins[] = { PIN(GPIOY_1, 0) };
346static const unsigned int uart_cts_c_pins[] = { PIN_GPIOY_2 }; 208static const unsigned int uart_cts_c_pins[] = { PIN(GPIOY_2, 0) };
347static const unsigned int uart_rts_c_pins[] = { PIN_GPIOY_3 }; 209static const unsigned int uart_rts_c_pins[] = { PIN(GPIOY_3, 0) };
348 210
349static const unsigned int pcm_out_b_pins[] = { PIN_GPIOY_4 }; 211static const unsigned int pcm_out_b_pins[] = { PIN(GPIOY_4, 0) };
350static const unsigned int pcm_in_b_pins[] = { PIN_GPIOY_5 }; 212static const unsigned int pcm_in_b_pins[] = { PIN(GPIOY_5, 0) };
351static const unsigned int pcm_fs_b_pins[] = { PIN_GPIOY_6 }; 213static const unsigned int pcm_fs_b_pins[] = { PIN(GPIOY_6, 0) };
352static const unsigned int pcm_clk_b_pins[] = { PIN_GPIOY_7 }; 214static const unsigned int pcm_clk_b_pins[] = { PIN(GPIOY_7, 0) };
353 215
354static const unsigned int i2c_sda_c0_pins[] = { PIN_GPIOY_0 }; 216static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIOY_0, 0) };
355static const unsigned int i2c_sck_c0_pins[] = { PIN_GPIOY_1 }; 217static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIOY_1, 0) };
356 218
357/* bank DV */ 219/* bank DV */
358static const unsigned int dvin_rgb_pins[] = { PIN_GPIODV_0, PIN_GPIODV_1, 220static const unsigned int dvin_rgb_pins[] = { PIN(GPIODV_0, 0), PIN(GPIODV_1, 0),
359 PIN_GPIODV_2, PIN_GPIODV_3, 221 PIN(GPIODV_2, 0), PIN(GPIODV_3, 0),
360 PIN_GPIODV_4, PIN_GPIODV_5, 222 PIN(GPIODV_4, 0), PIN(GPIODV_5, 0),
361 PIN_GPIODV_6, PIN_GPIODV_7, 223 PIN(GPIODV_6, 0), PIN(GPIODV_7, 0),
362 PIN_GPIODV_8, PIN_GPIODV_9, 224 PIN(GPIODV_8, 0), PIN(GPIODV_9, 0),
363 PIN_GPIODV_10, PIN_GPIODV_11, 225 PIN(GPIODV_10, 0), PIN(GPIODV_11, 0),
364 PIN_GPIODV_12, PIN_GPIODV_13, 226 PIN(GPIODV_12, 0), PIN(GPIODV_13, 0),
365 PIN_GPIODV_14, PIN_GPIODV_15, 227 PIN(GPIODV_14, 0), PIN(GPIODV_15, 0),
366 PIN_GPIODV_16, PIN_GPIODV_17, 228 PIN(GPIODV_16, 0), PIN(GPIODV_17, 0),
367 PIN_GPIODV_18, PIN_GPIODV_19, 229 PIN(GPIODV_18, 0), PIN(GPIODV_19, 0),
368 PIN_GPIODV_20, PIN_GPIODV_21, 230 PIN(GPIODV_20, 0), PIN(GPIODV_21, 0),
369 PIN_GPIODV_22, PIN_GPIODV_23 }; 231 PIN(GPIODV_22, 0), PIN(GPIODV_23, 0) };
370static const unsigned int dvin_vs_pins[] = { PIN_GPIODV_24 }; 232static const unsigned int dvin_vs_pins[] = { PIN(GPIODV_24, 0) };
371static const unsigned int dvin_hs_pins[] = { PIN_GPIODV_25 }; 233static const unsigned int dvin_hs_pins[] = { PIN(GPIODV_25, 0) };
372static const unsigned int dvin_clk_pins[] = { PIN_GPIODV_26 }; 234static const unsigned int dvin_clk_pins[] = { PIN(GPIODV_26, 0) };
373static const unsigned int dvin_de_pins[] = { PIN_GPIODV_27 }; 235static const unsigned int dvin_de_pins[] = { PIN(GPIODV_27, 0) };
374 236
375static const unsigned int enc_0_pins[] = { PIN_GPIODV_0 }; 237static const unsigned int enc_0_pins[] = { PIN(GPIODV_0, 0) };
376static const unsigned int enc_1_pins[] = { PIN_GPIODV_1 }; 238static const unsigned int enc_1_pins[] = { PIN(GPIODV_1, 0) };
377static const unsigned int enc_2_pins[] = { PIN_GPIODV_2 }; 239static const unsigned int enc_2_pins[] = { PIN(GPIODV_2, 0) };
378static const unsigned int enc_3_pins[] = { PIN_GPIODV_3 }; 240static const unsigned int enc_3_pins[] = { PIN(GPIODV_3, 0) };
379static const unsigned int enc_4_pins[] = { PIN_GPIODV_4 }; 241static const unsigned int enc_4_pins[] = { PIN(GPIODV_4, 0) };
380static const unsigned int enc_5_pins[] = { PIN_GPIODV_5 }; 242static const unsigned int enc_5_pins[] = { PIN(GPIODV_5, 0) };
381static const unsigned int enc_6_pins[] = { PIN_GPIODV_6 }; 243static const unsigned int enc_6_pins[] = { PIN(GPIODV_6, 0) };
382static const unsigned int enc_7_pins[] = { PIN_GPIODV_7 }; 244static const unsigned int enc_7_pins[] = { PIN(GPIODV_7, 0) };
383static const unsigned int enc_8_pins[] = { PIN_GPIODV_8 }; 245static const unsigned int enc_8_pins[] = { PIN(GPIODV_8, 0) };
384static const unsigned int enc_9_pins[] = { PIN_GPIODV_9 }; 246static const unsigned int enc_9_pins[] = { PIN(GPIODV_9, 0) };
385static const unsigned int enc_10_pins[] = { PIN_GPIODV_10 }; 247static const unsigned int enc_10_pins[] = { PIN(GPIODV_10, 0) };
386static const unsigned int enc_11_pins[] = { PIN_GPIODV_11 }; 248static const unsigned int enc_11_pins[] = { PIN(GPIODV_11, 0) };
387static const unsigned int enc_12_pins[] = { PIN_GPIODV_12 }; 249static const unsigned int enc_12_pins[] = { PIN(GPIODV_12, 0) };
388static const unsigned int enc_13_pins[] = { PIN_GPIODV_13 }; 250static const unsigned int enc_13_pins[] = { PIN(GPIODV_13, 0) };
389static const unsigned int enc_14_pins[] = { PIN_GPIODV_14 }; 251static const unsigned int enc_14_pins[] = { PIN(GPIODV_14, 0) };
390static const unsigned int enc_15_pins[] = { PIN_GPIODV_15 }; 252static const unsigned int enc_15_pins[] = { PIN(GPIODV_15, 0) };
391static const unsigned int enc_16_pins[] = { PIN_GPIODV_16 }; 253static const unsigned int enc_16_pins[] = { PIN(GPIODV_16, 0) };
392static const unsigned int enc_17_pins[] = { PIN_GPIODV_17 }; 254static const unsigned int enc_17_pins[] = { PIN(GPIODV_17, 0) };
393 255
394static const unsigned int uart_tx_b1_pins[] = { PIN_GPIODV_24 }; 256static const unsigned int uart_tx_b1_pins[] = { PIN(GPIODV_24, 0) };
395static const unsigned int uart_rx_b1_pins[] = { PIN_GPIODV_25 }; 257static const unsigned int uart_rx_b1_pins[] = { PIN(GPIODV_25, 0) };
396static const unsigned int uart_cts_b1_pins[] = { PIN_GPIODV_26 }; 258static const unsigned int uart_cts_b1_pins[] = { PIN(GPIODV_26, 0) };
397static const unsigned int uart_rts_b1_pins[] = { PIN_GPIODV_27 }; 259static const unsigned int uart_rts_b1_pins[] = { PIN(GPIODV_27, 0) };
398 260
399static const unsigned int vga_vs_pins[] = { PIN_GPIODV_24 }; 261static const unsigned int vga_vs_pins[] = { PIN(GPIODV_24, 0) };
400static const unsigned int vga_hs_pins[] = { PIN_GPIODV_25 }; 262static const unsigned int vga_hs_pins[] = { PIN(GPIODV_25, 0) };
401 263
402/* bank H */ 264/* bank H */
403static const unsigned int hdmi_hpd_pins[] = { PIN_GPIOH_0 }; 265static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) };
404static const unsigned int hdmi_sda_pins[] = { PIN_GPIOH_1 }; 266static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) };
405static const unsigned int hdmi_scl_pins[] = { PIN_GPIOH_2 }; 267static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) };
406static const unsigned int hdmi_cec_pins[] = { PIN_GPIOH_3 }; 268static const unsigned int hdmi_cec_pins[] = { PIN(GPIOH_3, 0) };
407 269
408static const unsigned int spi_ss0_0_pins[] = { PIN_GPIOH_3 }; 270static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOH_3, 0) };
409static const unsigned int spi_miso_0_pins[] = { PIN_GPIOH_4 }; 271static const unsigned int spi_miso_0_pins[] = { PIN(GPIOH_4, 0) };
410static const unsigned int spi_mosi_0_pins[] = { PIN_GPIOH_5 }; 272static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOH_5, 0) };
411static const unsigned int spi_sclk_0_pins[] = { PIN_GPIOH_6 }; 273static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOH_6, 0) };
412 274
413static const unsigned int i2c_sda_d1_pins[] = { PIN_GPIOH_7 }; 275static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) };
414static const unsigned int i2c_sck_d1_pins[] = { PIN_GPIOH_8 }; 276static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) };
415 277
416/* bank Z */ 278/* bank Z */
417static const unsigned int spi_ss0_1_pins[] = { PIN_GPIOZ_9 }; 279static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOZ_9, 0) };
418static const unsigned int spi_ss1_1_pins[] = { PIN_GPIOZ_10 }; 280static const unsigned int spi_ss1_1_pins[] = { PIN(GPIOZ_10, 0) };
419static const unsigned int spi_sclk_1_pins[] = { PIN_GPIOZ_11 }; 281static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOZ_11, 0) };
420static const unsigned int spi_mosi_1_pins[] = { PIN_GPIOZ_12 }; 282static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOZ_12, 0) };
421static const unsigned int spi_miso_1_pins[] = { PIN_GPIOZ_13 }; 283static const unsigned int spi_miso_1_pins[] = { PIN(GPIOZ_13, 0) };
422static const unsigned int spi_ss2_1_pins[] = { PIN_GPIOZ_14 }; 284static const unsigned int spi_ss2_1_pins[] = { PIN(GPIOZ_14, 0) };
423 285
424static const unsigned int eth_tx_clk_50m_pins[] = { PIN_GPIOZ_4 }; 286static const unsigned int eth_tx_clk_50m_pins[] = { PIN(GPIOZ_4, 0) };
425static const unsigned int eth_tx_en_pins[] = { PIN_GPIOZ_5 }; 287static const unsigned int eth_tx_en_pins[] = { PIN(GPIOZ_5, 0) };
426static const unsigned int eth_txd1_pins[] = { PIN_GPIOZ_6 }; 288static const unsigned int eth_txd1_pins[] = { PIN(GPIOZ_6, 0) };
427static const unsigned int eth_txd0_pins[] = { PIN_GPIOZ_7 }; 289static const unsigned int eth_txd0_pins[] = { PIN(GPIOZ_7, 0) };
428static const unsigned int eth_rx_clk_in_pins[] = { PIN_GPIOZ_8 }; 290static const unsigned int eth_rx_clk_in_pins[] = { PIN(GPIOZ_8, 0) };
429static const unsigned int eth_rx_dv_pins[] = { PIN_GPIOZ_9 }; 291static const unsigned int eth_rx_dv_pins[] = { PIN(GPIOZ_9, 0) };
430static const unsigned int eth_rxd1_pins[] = { PIN_GPIOZ_10 }; 292static const unsigned int eth_rxd1_pins[] = { PIN(GPIOZ_10, 0) };
431static const unsigned int eth_rxd0_pins[] = { PIN_GPIOZ_11 }; 293static const unsigned int eth_rxd0_pins[] = { PIN(GPIOZ_11, 0) };
432static const unsigned int eth_mdio_pins[] = { PIN_GPIOZ_12 }; 294static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_12, 0) };
433static const unsigned int eth_mdc_pins[] = { PIN_GPIOZ_13 }; 295static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_13, 0) };
434 296
435static const unsigned int i2c_sda_a0_pins[] = { PIN_GPIOZ_0 }; 297static const unsigned int i2c_sda_a0_pins[] = { PIN(GPIOZ_0, 0) };
436static const unsigned int i2c_sck_a0_pins[] = { PIN_GPIOZ_1 }; 298static const unsigned int i2c_sck_a0_pins[] = { PIN(GPIOZ_1, 0) };
437 299
438static const unsigned int i2c_sda_b_pins[] = { PIN_GPIOZ_2 }; 300static const unsigned int i2c_sda_b_pins[] = { PIN(GPIOZ_2, 0) };
439static const unsigned int i2c_sck_b_pins[] = { PIN_GPIOZ_3 }; 301static const unsigned int i2c_sck_b_pins[] = { PIN(GPIOZ_3, 0) };
440 302
441static const unsigned int i2c_sda_c1_pins[] = { PIN_GPIOZ_4 }; 303static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOZ_4, 0) };
442static const unsigned int i2c_sck_c1_pins[] = { PIN_GPIOZ_5 }; 304static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOZ_5, 0) };
443 305
444static const unsigned int i2c_sda_a1_pins[] = { PIN_GPIOZ_0 }; 306static const unsigned int i2c_sda_a1_pins[] = { PIN(GPIOZ_0, 0) };
445static const unsigned int i2c_sck_a1_pins[] = { PIN_GPIOZ_1 }; 307static const unsigned int i2c_sck_a1_pins[] = { PIN(GPIOZ_1, 0) };
446 308
447static const unsigned int i2c_sda_a2_pins[] = { PIN_GPIOZ_0 }; 309static const unsigned int i2c_sda_a2_pins[] = { PIN(GPIOZ_0, 0) };
448static const unsigned int i2c_sck_a2_pins[] = { PIN_GPIOZ_1 }; 310static const unsigned int i2c_sck_a2_pins[] = { PIN(GPIOZ_1, 0) };
449 311
450/* bank BOOT */ 312/* bank BOOT */
451static const unsigned int sd_d0_c_pins[] = { PIN_BOOT_0 }; 313static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) };
452static const unsigned int sd_d1_c_pins[] = { PIN_BOOT_1 }; 314static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) };
453static const unsigned int sd_d2_c_pins[] = { PIN_BOOT_2 }; 315static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) };
454static const unsigned int sd_d3_c_pins[] = { PIN_BOOT_3 }; 316static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) };
455static const unsigned int sd_cmd_c_pins[] = { PIN_BOOT_16 }; 317static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_16, 0) };
456static const unsigned int sd_clk_c_pins[] = { PIN_BOOT_17 }; 318static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_17, 0) };
457 319
458static const unsigned int sdxc_d0_c_pins[] = { PIN_BOOT_0}; 320static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)};
459static const unsigned int sdxc_d13_c_pins[] = { PIN_BOOT_1, PIN_BOOT_2, 321static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0),
460 PIN_BOOT_3 }; 322 PIN(BOOT_3, 0) };
461static const unsigned int sdxc_d47_c_pins[] = { PIN_BOOT_4, PIN_BOOT_5, 323static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0),
462 PIN_BOOT_6, PIN_BOOT_7 }; 324 PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
463static const unsigned int sdxc_cmd_c_pins[] = { PIN_BOOT_16 }; 325static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_16, 0) };
464static const unsigned int sdxc_clk_c_pins[] = { PIN_BOOT_17 }; 326static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_17, 0) };
465 327
466static const unsigned int nand_io_pins[] = { PIN_BOOT_0, PIN_BOOT_1, 328static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0),
467 PIN_BOOT_2, PIN_BOOT_3, 329 PIN(BOOT_2, 0), PIN(BOOT_3, 0),
468 PIN_BOOT_4, PIN_BOOT_5, 330 PIN(BOOT_4, 0), PIN(BOOT_5, 0),
469 PIN_BOOT_6, PIN_BOOT_7 }; 331 PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
470static const unsigned int nand_io_ce0_pins[] = { PIN_BOOT_8 }; 332static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) };
471static const unsigned int nand_io_ce1_pins[] = { PIN_BOOT_9 }; 333static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) };
472static const unsigned int nand_io_rb0_pins[] = { PIN_BOOT_10 }; 334static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) };
473static const unsigned int nand_ale_pins[] = { PIN_BOOT_11 }; 335static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) };
474static const unsigned int nand_cle_pins[] = { PIN_BOOT_12 }; 336static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) };
475static const unsigned int nand_wen_clk_pins[] = { PIN_BOOT_13 }; 337static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) };
476static const unsigned int nand_ren_clk_pins[] = { PIN_BOOT_14 }; 338static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) };
477static const unsigned int nand_dqs_pins[] = { PIN_BOOT_15 }; 339static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, 0) };
478static const unsigned int nand_ce2_pins[] = { PIN_BOOT_16 }; 340static const unsigned int nand_ce2_pins[] = { PIN(BOOT_16, 0) };
479static const unsigned int nand_ce3_pins[] = { PIN_BOOT_17 }; 341static const unsigned int nand_ce3_pins[] = { PIN(BOOT_17, 0) };
480 342
481static const unsigned int nor_d_pins[] = { PIN_BOOT_11 }; 343static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) };
482static const unsigned int nor_q_pins[] = { PIN_BOOT_12 }; 344static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) };
483static const unsigned int nor_c_pins[] = { PIN_BOOT_13 }; 345static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) };
484static const unsigned int nor_cs_pins[] = { PIN_BOOT_18 }; 346static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) };
485 347
486/* bank CARD */ 348/* bank CARD */
487static const unsigned int sd_d1_b_pins[] = { PIN_CARD_0 }; 349static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) };
488static const unsigned int sd_d0_b_pins[] = { PIN_CARD_1 }; 350static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) };
489static const unsigned int sd_clk_b_pins[] = { PIN_CARD_2 }; 351static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) };
490static const unsigned int sd_cmd_b_pins[] = { PIN_CARD_3 }; 352static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) };
491static const unsigned int sd_d3_b_pins[] = { PIN_CARD_4 }; 353static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) };
492static const unsigned int sd_d2_b_pins[] = { PIN_CARD_5 }; 354static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) };
493 355
494static const unsigned int sdxc_d13_b_pins[] = { PIN_CARD_0, PIN_CARD_4, 356static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0),
495 PIN_CARD_5 }; 357 PIN(CARD_5, 0) };
496static const unsigned int sdxc_d0_b_pins[] = { PIN_CARD_1 }; 358static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) };
497static const unsigned int sdxc_clk_b_pins[] = { PIN_CARD_2 }; 359static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) };
498static const unsigned int sdxc_cmd_b_pins[] = { PIN_CARD_3 }; 360static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) };
499 361
500/* bank AO */ 362/* bank AO */
501static const unsigned int uart_tx_ao_a_pins[] = { PIN_GPIOAO_0 }; 363static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) };
502static const unsigned int uart_rx_ao_a_pins[] = { PIN_GPIOAO_1 }; 364static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) };
503static const unsigned int uart_cts_ao_a_pins[] = { PIN_GPIOAO_2 }; 365static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) };
504static const unsigned int uart_rts_ao_a_pins[] = { PIN_GPIOAO_3 }; 366static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) };
505 367
506static const unsigned int remote_input_pins[] = { PIN_GPIOAO_7 }; 368static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) };
507 369
508static const unsigned int i2c_slave_sck_ao_pins[] = { PIN_GPIOAO_4 }; 370static const unsigned int i2c_slave_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
509static const unsigned int i2c_slave_sda_ao_pins[] = { PIN_GPIOAO_5 }; 371static const unsigned int i2c_slave_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
510 372
511static const unsigned int uart_tx_ao_b0_pins[] = { PIN_GPIOAO_0 }; 373static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) };
512static const unsigned int uart_rx_ao_b0_pins[] = { PIN_GPIOAO_1 }; 374static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) };
513 375
514static const unsigned int uart_tx_ao_b1_pins[] = { PIN_GPIOAO_4 }; 376static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) };
515static const unsigned int uart_rx_ao_b1_pins[] = { PIN_GPIOAO_5 }; 377static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) };
516 378
517static const unsigned int i2c_mst_sck_ao_pins[] = { PIN_GPIOAO_4 }; 379static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
518static const unsigned int i2c_mst_sda_ao_pins[] = { PIN_GPIOAO_5 }; 380static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
519 381
520static struct meson_pmx_group meson8_groups[] = { 382static struct meson_pmx_group meson8_groups[] = {
521 GPIO_GROUP(GPIOX_0), 383 GPIO_GROUP(GPIOX_0, 0),
522 GPIO_GROUP(GPIOX_1), 384 GPIO_GROUP(GPIOX_1, 0),
523 GPIO_GROUP(GPIOX_2), 385 GPIO_GROUP(GPIOX_2, 0),
524 GPIO_GROUP(GPIOX_3), 386 GPIO_GROUP(GPIOX_3, 0),
525 GPIO_GROUP(GPIOX_4), 387 GPIO_GROUP(GPIOX_4, 0),
526 GPIO_GROUP(GPIOX_5), 388 GPIO_GROUP(GPIOX_5, 0),
527 GPIO_GROUP(GPIOX_6), 389 GPIO_GROUP(GPIOX_6, 0),
528 GPIO_GROUP(GPIOX_7), 390 GPIO_GROUP(GPIOX_7, 0),
529 GPIO_GROUP(GPIOX_8), 391 GPIO_GROUP(GPIOX_8, 0),
530 GPIO_GROUP(GPIOX_9), 392 GPIO_GROUP(GPIOX_9, 0),
531 GPIO_GROUP(GPIOX_10), 393 GPIO_GROUP(GPIOX_10, 0),
532 GPIO_GROUP(GPIOX_11), 394 GPIO_GROUP(GPIOX_11, 0),
533 GPIO_GROUP(GPIOX_12), 395 GPIO_GROUP(GPIOX_12, 0),
534 GPIO_GROUP(GPIOX_13), 396 GPIO_GROUP(GPIOX_13, 0),
535 GPIO_GROUP(GPIOX_14), 397 GPIO_GROUP(GPIOX_14, 0),
536 GPIO_GROUP(GPIOX_15), 398 GPIO_GROUP(GPIOX_15, 0),
537 GPIO_GROUP(GPIOX_16), 399 GPIO_GROUP(GPIOX_16, 0),
538 GPIO_GROUP(GPIOX_17), 400 GPIO_GROUP(GPIOX_17, 0),
539 GPIO_GROUP(GPIOX_18), 401 GPIO_GROUP(GPIOX_18, 0),
540 GPIO_GROUP(GPIOX_19), 402 GPIO_GROUP(GPIOX_19, 0),
541 GPIO_GROUP(GPIOX_20), 403 GPIO_GROUP(GPIOX_20, 0),
542 GPIO_GROUP(GPIOX_21), 404 GPIO_GROUP(GPIOX_21, 0),
543 GPIO_GROUP(GPIOY_0), 405 GPIO_GROUP(GPIOY_0, 0),
544 GPIO_GROUP(GPIOY_1), 406 GPIO_GROUP(GPIOY_1, 0),
545 GPIO_GROUP(GPIOY_2), 407 GPIO_GROUP(GPIOY_2, 0),
546 GPIO_GROUP(GPIOY_3), 408 GPIO_GROUP(GPIOY_3, 0),
547 GPIO_GROUP(GPIOY_4), 409 GPIO_GROUP(GPIOY_4, 0),
548 GPIO_GROUP(GPIOY_5), 410 GPIO_GROUP(GPIOY_5, 0),
549 GPIO_GROUP(GPIOY_6), 411 GPIO_GROUP(GPIOY_6, 0),
550 GPIO_GROUP(GPIOY_7), 412 GPIO_GROUP(GPIOY_7, 0),
551 GPIO_GROUP(GPIOY_8), 413 GPIO_GROUP(GPIOY_8, 0),
552 GPIO_GROUP(GPIOY_9), 414 GPIO_GROUP(GPIOY_9, 0),
553 GPIO_GROUP(GPIOY_10), 415 GPIO_GROUP(GPIOY_10, 0),
554 GPIO_GROUP(GPIOY_11), 416 GPIO_GROUP(GPIOY_11, 0),
555 GPIO_GROUP(GPIOY_12), 417 GPIO_GROUP(GPIOY_12, 0),
556 GPIO_GROUP(GPIOY_13), 418 GPIO_GROUP(GPIOY_13, 0),
557 GPIO_GROUP(GPIOY_14), 419 GPIO_GROUP(GPIOY_14, 0),
558 GPIO_GROUP(GPIOY_15), 420 GPIO_GROUP(GPIOY_15, 0),
559 GPIO_GROUP(GPIOY_16), 421 GPIO_GROUP(GPIOY_16, 0),
560 GPIO_GROUP(GPIODV_0), 422 GPIO_GROUP(GPIODV_0, 0),
561 GPIO_GROUP(GPIODV_1), 423 GPIO_GROUP(GPIODV_1, 0),
562 GPIO_GROUP(GPIODV_2), 424 GPIO_GROUP(GPIODV_2, 0),
563 GPIO_GROUP(GPIODV_3), 425 GPIO_GROUP(GPIODV_3, 0),
564 GPIO_GROUP(GPIODV_4), 426 GPIO_GROUP(GPIODV_4, 0),
565 GPIO_GROUP(GPIODV_5), 427 GPIO_GROUP(GPIODV_5, 0),
566 GPIO_GROUP(GPIODV_6), 428 GPIO_GROUP(GPIODV_6, 0),
567 GPIO_GROUP(GPIODV_7), 429 GPIO_GROUP(GPIODV_7, 0),
568 GPIO_GROUP(GPIODV_8), 430 GPIO_GROUP(GPIODV_8, 0),
569 GPIO_GROUP(GPIODV_9), 431 GPIO_GROUP(GPIODV_9, 0),
570 GPIO_GROUP(GPIODV_10), 432 GPIO_GROUP(GPIODV_10, 0),
571 GPIO_GROUP(GPIODV_11), 433 GPIO_GROUP(GPIODV_11, 0),
572 GPIO_GROUP(GPIODV_12), 434 GPIO_GROUP(GPIODV_12, 0),
573 GPIO_GROUP(GPIODV_13), 435 GPIO_GROUP(GPIODV_13, 0),
574 GPIO_GROUP(GPIODV_14), 436 GPIO_GROUP(GPIODV_14, 0),
575 GPIO_GROUP(GPIODV_15), 437 GPIO_GROUP(GPIODV_15, 0),
576 GPIO_GROUP(GPIODV_16), 438 GPIO_GROUP(GPIODV_16, 0),
577 GPIO_GROUP(GPIODV_17), 439 GPIO_GROUP(GPIODV_17, 0),
578 GPIO_GROUP(GPIODV_18), 440 GPIO_GROUP(GPIODV_18, 0),
579 GPIO_GROUP(GPIODV_19), 441 GPIO_GROUP(GPIODV_19, 0),
580 GPIO_GROUP(GPIODV_20), 442 GPIO_GROUP(GPIODV_20, 0),
581 GPIO_GROUP(GPIODV_21), 443 GPIO_GROUP(GPIODV_21, 0),
582 GPIO_GROUP(GPIODV_22), 444 GPIO_GROUP(GPIODV_22, 0),
583 GPIO_GROUP(GPIODV_23), 445 GPIO_GROUP(GPIODV_23, 0),
584 GPIO_GROUP(GPIODV_24), 446 GPIO_GROUP(GPIODV_24, 0),
585 GPIO_GROUP(GPIODV_25), 447 GPIO_GROUP(GPIODV_25, 0),
586 GPIO_GROUP(GPIODV_26), 448 GPIO_GROUP(GPIODV_26, 0),
587 GPIO_GROUP(GPIODV_27), 449 GPIO_GROUP(GPIODV_27, 0),
588 GPIO_GROUP(GPIODV_28), 450 GPIO_GROUP(GPIODV_28, 0),
589 GPIO_GROUP(GPIODV_29), 451 GPIO_GROUP(GPIODV_29, 0),
590 GPIO_GROUP(GPIOH_0), 452 GPIO_GROUP(GPIOH_0, 0),
591 GPIO_GROUP(GPIOH_1), 453 GPIO_GROUP(GPIOH_1, 0),
592 GPIO_GROUP(GPIOH_2), 454 GPIO_GROUP(GPIOH_2, 0),
593 GPIO_GROUP(GPIOH_3), 455 GPIO_GROUP(GPIOH_3, 0),
594 GPIO_GROUP(GPIOH_4), 456 GPIO_GROUP(GPIOH_4, 0),
595 GPIO_GROUP(GPIOH_5), 457 GPIO_GROUP(GPIOH_5, 0),
596 GPIO_GROUP(GPIOH_6), 458 GPIO_GROUP(GPIOH_6, 0),
597 GPIO_GROUP(GPIOH_7), 459 GPIO_GROUP(GPIOH_7, 0),
598 GPIO_GROUP(GPIOH_8), 460 GPIO_GROUP(GPIOH_8, 0),
599 GPIO_GROUP(GPIOH_9), 461 GPIO_GROUP(GPIOH_9, 0),
600 GPIO_GROUP(GPIOZ_0), 462 GPIO_GROUP(GPIOZ_0, 0),
601 GPIO_GROUP(GPIOZ_1), 463 GPIO_GROUP(GPIOZ_1, 0),
602 GPIO_GROUP(GPIOZ_2), 464 GPIO_GROUP(GPIOZ_2, 0),
603 GPIO_GROUP(GPIOZ_3), 465 GPIO_GROUP(GPIOZ_3, 0),
604 GPIO_GROUP(GPIOZ_4), 466 GPIO_GROUP(GPIOZ_4, 0),
605 GPIO_GROUP(GPIOZ_5), 467 GPIO_GROUP(GPIOZ_5, 0),
606 GPIO_GROUP(GPIOZ_6), 468 GPIO_GROUP(GPIOZ_6, 0),
607 GPIO_GROUP(GPIOZ_7), 469 GPIO_GROUP(GPIOZ_7, 0),
608 GPIO_GROUP(GPIOZ_8), 470 GPIO_GROUP(GPIOZ_8, 0),
609 GPIO_GROUP(GPIOZ_9), 471 GPIO_GROUP(GPIOZ_9, 0),
610 GPIO_GROUP(GPIOZ_10), 472 GPIO_GROUP(GPIOZ_10, 0),
611 GPIO_GROUP(GPIOZ_11), 473 GPIO_GROUP(GPIOZ_11, 0),
612 GPIO_GROUP(GPIOZ_12), 474 GPIO_GROUP(GPIOZ_12, 0),
613 GPIO_GROUP(GPIOZ_13), 475 GPIO_GROUP(GPIOZ_13, 0),
614 GPIO_GROUP(GPIOZ_14), 476 GPIO_GROUP(GPIOZ_14, 0),
615 GPIO_GROUP(GPIOAO_0), 477 GPIO_GROUP(GPIOAO_0, AO_OFF),
616 GPIO_GROUP(GPIOAO_1), 478 GPIO_GROUP(GPIOAO_1, AO_OFF),
617 GPIO_GROUP(GPIOAO_2), 479 GPIO_GROUP(GPIOAO_2, AO_OFF),
618 GPIO_GROUP(GPIOAO_3), 480 GPIO_GROUP(GPIOAO_3, AO_OFF),
619 GPIO_GROUP(GPIOAO_4), 481 GPIO_GROUP(GPIOAO_4, AO_OFF),
620 GPIO_GROUP(GPIOAO_5), 482 GPIO_GROUP(GPIOAO_5, AO_OFF),
621 GPIO_GROUP(GPIOAO_6), 483 GPIO_GROUP(GPIOAO_6, AO_OFF),
622 GPIO_GROUP(GPIOAO_7), 484 GPIO_GROUP(GPIOAO_7, AO_OFF),
623 GPIO_GROUP(GPIOAO_8), 485 GPIO_GROUP(GPIOAO_8, AO_OFF),
624 GPIO_GROUP(GPIOAO_9), 486 GPIO_GROUP(GPIOAO_9, AO_OFF),
625 GPIO_GROUP(GPIOAO_10), 487 GPIO_GROUP(GPIOAO_10, AO_OFF),
626 GPIO_GROUP(GPIOAO_11), 488 GPIO_GROUP(GPIOAO_11, AO_OFF),
627 GPIO_GROUP(GPIOAO_12), 489 GPIO_GROUP(GPIOAO_12, AO_OFF),
628 GPIO_GROUP(GPIOAO_13), 490 GPIO_GROUP(GPIOAO_13, AO_OFF),
629 GPIO_GROUP(GPIO_BSD_EN), 491 GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
630 GPIO_GROUP(GPIO_TEST_N), 492 GPIO_GROUP(GPIO_TEST_N, AO_OFF),
631 493
632 /* bank X */ 494 /* bank X */
633 GROUP(sd_d0_a, 8, 5), 495 GROUP(sd_d0_a, 8, 5),
@@ -1045,19 +907,19 @@ static struct meson_pmx_func meson8_functions[] = {
1045}; 907};
1046 908
1047static struct meson_bank meson8_banks[] = { 909static struct meson_bank meson8_banks[] = {
1048 /* name first last pullen pull dir out in */ 910 /* name first last pullen pull dir out in */
1049 BANK("X", PIN_GPIOX_0, PIN_GPIOX_21, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), 911 BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
1050 BANK("Y", PIN_GPIOY_0, PIN_GPIOY_16, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), 912 BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_16, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
1051 BANK("DV", PIN_GPIODV_0, PIN_GPIODV_29, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), 913 BANK("DV", PIN(GPIODV_0, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
1052 BANK("H", PIN_GPIOH_0, PIN_GPIOH_9, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), 914 BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
1053 BANK("Z", PIN_GPIOZ_0, PIN_GPIOZ_14, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17), 915 BANK("Z", PIN(GPIOZ_0, 0), PIN(GPIOZ_14, 0), 1, 0, 1, 0, 3, 17, 4, 17, 5, 17),
1054 BANK("CARD", PIN_CARD_0, PIN_CARD_6, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), 916 BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
1055 BANK("BOOT", PIN_BOOT_0, PIN_BOOT_18, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), 917 BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
1056}; 918};
1057 919
1058static struct meson_bank meson8_ao_banks[] = { 920static struct meson_bank meson8_ao_banks[] = {
1059 /* name first last pullen pull dir out in */ 921 /* name first last pullen pull dir out in */
1060 BANK("AO", PIN_GPIOAO_0, PIN_GPIO_TEST_N, 0, 0, 0, 16, 0, 0, 0, 16, 1, 0), 922 BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
1061}; 923};
1062 924
1063static struct meson_domain_data meson8_domain_data[] = { 925static struct meson_domain_data meson8_domain_data[] = {
diff --git a/drivers/pinctrl/meson/pinctrl-meson8b.c b/drivers/pinctrl/meson/pinctrl-meson8b.c
new file mode 100644
index 000000000000..2f7ea6229880
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson8b.c
@@ -0,0 +1,899 @@
1/*
2 * Pin controller and GPIO driver for Amlogic Meson8b.
3 *
4 * Copyright (C) 2015 Endless Mobile, Inc.
5 * Author: Carlo Caione <carlo@endlessm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program. If not, see <http://www.gnu.org/licenses/>.
13 */
14
15#include <dt-bindings/gpio/meson8b-gpio.h>
16#include "pinctrl-meson.h"
17
18#define AO_OFF 130
19
20static const struct pinctrl_pin_desc meson8b_pins[] = {
21 MESON_PIN(GPIOX_0, 0),
22 MESON_PIN(GPIOX_1, 0),
23 MESON_PIN(GPIOX_2, 0),
24 MESON_PIN(GPIOX_3, 0),
25 MESON_PIN(GPIOX_4, 0),
26 MESON_PIN(GPIOX_5, 0),
27 MESON_PIN(GPIOX_6, 0),
28 MESON_PIN(GPIOX_7, 0),
29 MESON_PIN(GPIOX_8, 0),
30 MESON_PIN(GPIOX_9, 0),
31 MESON_PIN(GPIOX_10, 0),
32 MESON_PIN(GPIOX_11, 0),
33 MESON_PIN(GPIOX_16, 0),
34 MESON_PIN(GPIOX_17, 0),
35 MESON_PIN(GPIOX_18, 0),
36 MESON_PIN(GPIOX_19, 0),
37 MESON_PIN(GPIOX_20, 0),
38 MESON_PIN(GPIOX_21, 0),
39
40 MESON_PIN(GPIOY_0, 0),
41 MESON_PIN(GPIOY_1, 0),
42 MESON_PIN(GPIOY_3, 0),
43 MESON_PIN(GPIOY_6, 0),
44 MESON_PIN(GPIOY_7, 0),
45 MESON_PIN(GPIOY_8, 0),
46 MESON_PIN(GPIOY_9, 0),
47 MESON_PIN(GPIOY_10, 0),
48 MESON_PIN(GPIOY_11, 0),
49 MESON_PIN(GPIOY_12, 0),
50 MESON_PIN(GPIOY_13, 0),
51 MESON_PIN(GPIOY_14, 0),
52
53 MESON_PIN(GPIODV_9, 0),
54 MESON_PIN(GPIODV_24, 0),
55 MESON_PIN(GPIODV_25, 0),
56 MESON_PIN(GPIODV_26, 0),
57 MESON_PIN(GPIODV_27, 0),
58 MESON_PIN(GPIODV_28, 0),
59 MESON_PIN(GPIODV_29, 0),
60
61 MESON_PIN(GPIOH_0, 0),
62 MESON_PIN(GPIOH_1, 0),
63 MESON_PIN(GPIOH_2, 0),
64 MESON_PIN(GPIOH_3, 0),
65 MESON_PIN(GPIOH_4, 0),
66 MESON_PIN(GPIOH_5, 0),
67 MESON_PIN(GPIOH_6, 0),
68 MESON_PIN(GPIOH_7, 0),
69 MESON_PIN(GPIOH_8, 0),
70 MESON_PIN(GPIOH_9, 0),
71
72 MESON_PIN(CARD_0, 0),
73 MESON_PIN(CARD_1, 0),
74 MESON_PIN(CARD_2, 0),
75 MESON_PIN(CARD_3, 0),
76 MESON_PIN(CARD_4, 0),
77 MESON_PIN(CARD_5, 0),
78 MESON_PIN(CARD_6, 0),
79
80 MESON_PIN(BOOT_0, 0),
81 MESON_PIN(BOOT_1, 0),
82 MESON_PIN(BOOT_2, 0),
83 MESON_PIN(BOOT_3, 0),
84 MESON_PIN(BOOT_4, 0),
85 MESON_PIN(BOOT_5, 0),
86 MESON_PIN(BOOT_6, 0),
87 MESON_PIN(BOOT_7, 0),
88 MESON_PIN(BOOT_8, 0),
89 MESON_PIN(BOOT_9, 0),
90 MESON_PIN(BOOT_10, 0),
91 MESON_PIN(BOOT_11, 0),
92 MESON_PIN(BOOT_12, 0),
93 MESON_PIN(BOOT_13, 0),
94 MESON_PIN(BOOT_14, 0),
95 MESON_PIN(BOOT_15, 0),
96 MESON_PIN(BOOT_16, 0),
97 MESON_PIN(BOOT_17, 0),
98 MESON_PIN(BOOT_18, 0),
99
100 MESON_PIN(DIF_0_P, 0),
101 MESON_PIN(DIF_0_N, 0),
102 MESON_PIN(DIF_1_P, 0),
103 MESON_PIN(DIF_1_N, 0),
104 MESON_PIN(DIF_2_P, 0),
105 MESON_PIN(DIF_2_N, 0),
106 MESON_PIN(DIF_3_P, 0),
107 MESON_PIN(DIF_3_N, 0),
108 MESON_PIN(DIF_4_P, 0),
109 MESON_PIN(DIF_4_N, 0),
110
111 MESON_PIN(GPIOAO_0, AO_OFF),
112 MESON_PIN(GPIOAO_1, AO_OFF),
113 MESON_PIN(GPIOAO_2, AO_OFF),
114 MESON_PIN(GPIOAO_3, AO_OFF),
115 MESON_PIN(GPIOAO_4, AO_OFF),
116 MESON_PIN(GPIOAO_5, AO_OFF),
117 MESON_PIN(GPIOAO_6, AO_OFF),
118 MESON_PIN(GPIOAO_7, AO_OFF),
119 MESON_PIN(GPIOAO_8, AO_OFF),
120 MESON_PIN(GPIOAO_9, AO_OFF),
121 MESON_PIN(GPIOAO_10, AO_OFF),
122 MESON_PIN(GPIOAO_11, AO_OFF),
123 MESON_PIN(GPIOAO_12, AO_OFF),
124 MESON_PIN(GPIOAO_13, AO_OFF),
125 MESON_PIN(GPIO_BSD_EN, AO_OFF),
126 MESON_PIN(GPIO_TEST_N, AO_OFF),
127};
128
129/* bank X */
130static const unsigned int sd_d0_a_pins[] = { PIN(GPIOX_0, 0) };
131static const unsigned int sd_d1_a_pins[] = { PIN(GPIOX_1, 0) };
132static const unsigned int sd_d2_a_pins[] = { PIN(GPIOX_2, 0) };
133static const unsigned int sd_d3_a_pins[] = { PIN(GPIOX_3, 0) };
134static const unsigned int sdxc_d0_0_a_pins[] = { PIN(GPIOX_4, 0) };
135static const unsigned int sdxc_d47_a_pins[] = { PIN(GPIOX_4, 0), PIN(GPIOX_5, 0),
136 PIN(GPIOX_6, 0), PIN(GPIOX_7, 0) };
137static const unsigned int sdxc_d13_0_a_pins[] = { PIN(GPIOX_5, 0), PIN(GPIOX_6, 0),
138 PIN(GPIOX_7, 0) };
139static const unsigned int sd_clk_a_pins[] = { PIN(GPIOX_8, 0) };
140static const unsigned int sd_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
141static const unsigned int xtal_32k_out_pins[] = { PIN(GPIOX_10, 0) };
142static const unsigned int xtal_24m_out_pins[] = { PIN(GPIOX_11, 0) };
143static const unsigned int uart_tx_b0_pins[] = { PIN(GPIOX_16, 0) };
144static const unsigned int uart_rx_b0_pins[] = { PIN(GPIOX_17, 0) };
145static const unsigned int uart_cts_b0_pins[] = { PIN(GPIOX_18, 0) };
146static const unsigned int uart_rts_b0_pins[] = { PIN(GPIOX_19, 0) };
147
148static const unsigned int sdxc_d0_1_a_pins[] = { PIN(GPIOX_0, 0) };
149static const unsigned int sdxc_d13_1_a_pins[] = { PIN(GPIOX_1, 0), PIN(GPIOX_2, 0),
150 PIN(GPIOX_3, 0) };
151static const unsigned int pcm_out_a_pins[] = { PIN(GPIOX_4, 0) };
152static const unsigned int pcm_in_a_pins[] = { PIN(GPIOX_5, 0) };
153static const unsigned int pcm_fs_a_pins[] = { PIN(GPIOX_6, 0) };
154static const unsigned int pcm_clk_a_pins[] = { PIN(GPIOX_7, 0) };
155static const unsigned int sdxc_clk_a_pins[] = { PIN(GPIOX_8, 0) };
156static const unsigned int sdxc_cmd_a_pins[] = { PIN(GPIOX_9, 0) };
157static const unsigned int pwm_vs_0_pins[] = { PIN(GPIOX_10, 0) };
158static const unsigned int pwm_e_pins[] = { PIN(GPIOX_10, 0) };
159static const unsigned int pwm_vs_1_pins[] = { PIN(GPIOX_11, 0) };
160
161static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_4, 0) };
162static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_5, 0) };
163static const unsigned int uart_cts_a_pins[] = { PIN(GPIOX_6, 0) };
164static const unsigned int uart_rts_a_pins[] = { PIN(GPIOX_7, 0) };
165static const unsigned int uart_tx_b1_pins[] = { PIN(GPIOX_8, 0) };
166static const unsigned int uart_rx_b1_pins[] = { PIN(GPIOX_9, 0) };
167static const unsigned int uart_cts_b1_pins[] = { PIN(GPIOX_10, 0) };
168static const unsigned int uart_rts_b1_pins[] = { PIN(GPIOX_20, 0) };
169
170static const unsigned int iso7816_0_clk_pins[] = { PIN(GPIOX_6, 0) };
171static const unsigned int iso7816_0_data_pins[] = { PIN(GPIOX_7, 0) };
172static const unsigned int spi_sclk_0_pins[] = { PIN(GPIOX_8, 0) };
173static const unsigned int spi_miso_0_pins[] = { PIN(GPIOX_9, 0) };
174static const unsigned int spi_mosi_0_pins[] = { PIN(GPIOX_10, 0) };
175static const unsigned int iso7816_det_pins[] = { PIN(GPIOX_16, 0) };
176static const unsigned int iso7816_reset_pins[] = { PIN(GPIOX_17, 0) };
177static const unsigned int iso7816_1_clk_pins[] = { PIN(GPIOX_18, 0) };
178static const unsigned int iso7816_1_data_pins[] = { PIN(GPIOX_19, 0) };
179static const unsigned int spi_ss0_0_pins[] = { PIN(GPIOX_20, 0) };
180
181static const unsigned int tsin_clk_b_pins[] = { PIN(GPIOX_8, 0) };
182static const unsigned int tsin_sop_b_pins[] = { PIN(GPIOX_9, 0) };
183static const unsigned int tsin_d0_b_pins[] = { PIN(GPIOX_10, 0) };
184static const unsigned int pwm_b_pins[] = { PIN(GPIOX_11, 0) };
185static const unsigned int i2c_sda_d0_pins[] = { PIN(GPIOX_16, 0) };
186static const unsigned int i2c_sck_d0_pins[] = { PIN(GPIOX_17, 0) };
187static const unsigned int tsin_d_valid_b_pins[] = { PIN(GPIOX_20, 0) };
188
189/* bank Y */
190static const unsigned int tsin_d_valid_a_pins[] = { PIN(GPIOY_0, 0) };
191static const unsigned int tsin_sop_a_pins[] = { PIN(GPIOY_1, 0) };
192static const unsigned int tsin_d17_a_pins[] = { PIN(GPIOY_6, 0), PIN(GPIOY_7, 0),
193 PIN(GPIOY_10, 0), PIN(GPIOY_11, 0),
194 PIN(GPIOY_12, 0), PIN(GPIOY_13, 0),
195 PIN(GPIOY_14, 0) };
196static const unsigned int tsin_clk_a_pins[] = { PIN(GPIOY_8, 0) };
197static const unsigned int tsin_d0_a_pins[] = { PIN(GPIOY_9, 0) };
198
199static const unsigned int spdif_out_0_pins[] = { PIN(GPIOY_3, 0) };
200
201static const unsigned int xtal_24m_pins[] = { PIN(GPIOY_3, 0) };
202static const unsigned int iso7816_2_clk_pins[] = { PIN(GPIOY_13, 0) };
203static const unsigned int iso7816_2_data_pins[] = { PIN(GPIOY_14, 0) };
204
205/* bank DV */
206static const unsigned int pwm_d_pins[] = { PIN(GPIODV_28, 0) };
207static const unsigned int pwm_c0_pins[] = { PIN(GPIODV_29, 0) };
208
209static const unsigned int pwm_vs_2_pins[] = { PIN(GPIODV_9, 0) };
210static const unsigned int pwm_vs_3_pins[] = { PIN(GPIODV_28, 0) };
211static const unsigned int pwm_vs_4_pins[] = { PIN(GPIODV_29, 0) };
212
213static const unsigned int xtal24_out_pins[] = { PIN(GPIODV_29, 0) };
214
215static const unsigned int uart_tx_c_pins[] = { PIN(GPIODV_24, 0) };
216static const unsigned int uart_rx_c_pins[] = { PIN(GPIODV_25, 0) };
217static const unsigned int uart_cts_c_pins[] = { PIN(GPIODV_26, 0) };
218static const unsigned int uart_rts_c_pins[] = { PIN(GPIODV_27, 0) };
219
220static const unsigned int pwm_c1_pins[] = { PIN(GPIODV_9, 0) };
221
222static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, 0) };
223static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, 0) };
224static const unsigned int i2c_sda_b0_pins[] = { PIN(GPIODV_26, 0) };
225static const unsigned int i2c_sck_b0_pins[] = { PIN(GPIODV_27, 0) };
226static const unsigned int i2c_sda_c0_pins[] = { PIN(GPIODV_28, 0) };
227static const unsigned int i2c_sck_c0_pins[] = { PIN(GPIODV_29, 0) };
228
229/* bank H */
230static const unsigned int hdmi_hpd_pins[] = { PIN(GPIOH_0, 0) };
231static const unsigned int hdmi_sda_pins[] = { PIN(GPIOH_1, 0) };
232static const unsigned int hdmi_scl_pins[] = { PIN(GPIOH_2, 0) };
233static const unsigned int hdmi_cec_0_pins[] = { PIN(GPIOH_3, 0) };
234static const unsigned int eth_txd1_0_pins[] = { PIN(GPIOH_5, 0) };
235static const unsigned int eth_txd0_0_pins[] = { PIN(GPIOH_6, 0) };
236static const unsigned int clk_24m_out_pins[] = { PIN(GPIOH_9, 0) };
237
238static const unsigned int spi_ss1_pins[] = { PIN(GPIOH_0, 0) };
239static const unsigned int spi_ss2_pins[] = { PIN(GPIOH_1, 0) };
240static const unsigned int spi_ss0_1_pins[] = { PIN(GPIOH_3, 0) };
241static const unsigned int spi_miso_1_pins[] = { PIN(GPIOH_4, 0) };
242static const unsigned int spi_mosi_1_pins[] = { PIN(GPIOH_5, 0) };
243static const unsigned int spi_sclk_1_pins[] = { PIN(GPIOH_6, 0) };
244
245static const unsigned int eth_txd3_pins[] = { PIN(GPIOH_7, 0) };
246static const unsigned int eth_txd2_pins[] = { PIN(GPIOH_8, 0) };
247static const unsigned int eth_tx_clk_pins[] = { PIN(GPIOH_9, 0) };
248
249static const unsigned int i2c_sda_b1_pins[] = { PIN(GPIOH_3, 0) };
250static const unsigned int i2c_sck_b1_pins[] = { PIN(GPIOH_4, 0) };
251static const unsigned int i2c_sda_c1_pins[] = { PIN(GPIOH_5, 0) };
252static const unsigned int i2c_sck_c1_pins[] = { PIN(GPIOH_6, 0) };
253static const unsigned int i2c_sda_d1_pins[] = { PIN(GPIOH_7, 0) };
254static const unsigned int i2c_sck_d1_pins[] = { PIN(GPIOH_8, 0) };
255
256/* bank BOOT */
257static const unsigned int nand_io_pins[] = { PIN(BOOT_0, 0), PIN(BOOT_1, 0),
258 PIN(BOOT_2, 0), PIN(BOOT_3, 0),
259 PIN(BOOT_4, 0), PIN(BOOT_5, 0),
260 PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
261static const unsigned int nand_io_ce0_pins[] = { PIN(BOOT_8, 0) };
262static const unsigned int nand_io_ce1_pins[] = { PIN(BOOT_9, 0) };
263static const unsigned int nand_io_rb0_pins[] = { PIN(BOOT_10, 0) };
264static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, 0) };
265static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, 0) };
266static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, 0) };
267static const unsigned int nand_ren_clk_pins[] = { PIN(BOOT_14, 0) };
268static const unsigned int nand_dqs_0_pins[] = { PIN(BOOT_15, 0) };
269static const unsigned int nand_dqs_1_pins[] = { PIN(BOOT_18, 0) };
270
271static const unsigned int sdxc_d0_c_pins[] = { PIN(BOOT_0, 0)};
272static const unsigned int sdxc_d13_c_pins[] = { PIN(BOOT_1, 0), PIN(BOOT_2, 0),
273 PIN(BOOT_3, 0) };
274static const unsigned int sdxc_d47_c_pins[] = { PIN(BOOT_4, 0), PIN(BOOT_5, 0),
275 PIN(BOOT_6, 0), PIN(BOOT_7, 0) };
276static const unsigned int sdxc_clk_c_pins[] = { PIN(BOOT_8, 0) };
277static const unsigned int sdxc_cmd_c_pins[] = { PIN(BOOT_10, 0) };
278static const unsigned int nor_d_pins[] = { PIN(BOOT_11, 0) };
279static const unsigned int nor_q_pins[] = { PIN(BOOT_12, 0) };
280static const unsigned int nor_c_pins[] = { PIN(BOOT_13, 0) };
281static const unsigned int nor_cs_pins[] = { PIN(BOOT_18, 0) };
282
283static const unsigned int sd_d0_c_pins[] = { PIN(BOOT_0, 0) };
284static const unsigned int sd_d1_c_pins[] = { PIN(BOOT_1, 0) };
285static const unsigned int sd_d2_c_pins[] = { PIN(BOOT_2, 0) };
286static const unsigned int sd_d3_c_pins[] = { PIN(BOOT_3, 0) };
287static const unsigned int sd_cmd_c_pins[] = { PIN(BOOT_8, 0) };
288static const unsigned int sd_clk_c_pins[] = { PIN(BOOT_10, 0) };
289
290/* bank CARD */
291static const unsigned int sd_d1_b_pins[] = { PIN(CARD_0, 0) };
292static const unsigned int sd_d0_b_pins[] = { PIN(CARD_1, 0) };
293static const unsigned int sd_clk_b_pins[] = { PIN(CARD_2, 0) };
294static const unsigned int sd_cmd_b_pins[] = { PIN(CARD_3, 0) };
295static const unsigned int sd_d3_b_pins[] = { PIN(CARD_4, 0) };
296static const unsigned int sd_d2_b_pins[] = { PIN(CARD_5, 0) };
297
298static const unsigned int sdxc_d13_b_pins[] = { PIN(CARD_0, 0), PIN(CARD_4, 0),
299 PIN(CARD_5, 0) };
300static const unsigned int sdxc_d0_b_pins[] = { PIN(CARD_1, 0) };
301static const unsigned int sdxc_clk_b_pins[] = { PIN(CARD_2, 0) };
302static const unsigned int sdxc_cmd_b_pins[] = { PIN(CARD_3, 0) };
303
304/* bank AO */
305static const unsigned int uart_tx_ao_a_pins[] = { PIN(GPIOAO_0, AO_OFF) };
306static const unsigned int uart_rx_ao_a_pins[] = { PIN(GPIOAO_1, AO_OFF) };
307static const unsigned int uart_cts_ao_a_pins[] = { PIN(GPIOAO_2, AO_OFF) };
308static const unsigned int uart_rts_ao_a_pins[] = { PIN(GPIOAO_3, AO_OFF) };
309static const unsigned int i2c_mst_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
310static const unsigned int i2c_mst_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
311static const unsigned int clk_32k_in_out_pins[] = { PIN(GPIOAO_6, AO_OFF) };
312static const unsigned int remote_input_pins[] = { PIN(GPIOAO_7, AO_OFF) };
313static const unsigned int hdmi_cec_1_pins[] = { PIN(GPIOAO_12, AO_OFF) };
314static const unsigned int ir_blaster_pins[] = { PIN(GPIOAO_13, AO_OFF) };
315
316static const unsigned int pwm_c2_pins[] = { PIN(GPIOAO_3, AO_OFF) };
317static const unsigned int i2c_sck_ao_pins[] = { PIN(GPIOAO_4, AO_OFF) };
318static const unsigned int i2c_sda_ao_pins[] = { PIN(GPIOAO_5, AO_OFF) };
319static const unsigned int ir_remote_out_pins[] = { PIN(GPIOAO_7, AO_OFF) };
320static const unsigned int i2s_am_clk_out_pins[] = { PIN(GPIOAO_8, AO_OFF) };
321static const unsigned int i2s_ao_clk_out_pins[] = { PIN(GPIOAO_9, AO_OFF) };
322static const unsigned int i2s_lr_clk_out_pins[] = { PIN(GPIOAO_10, AO_OFF) };
323static const unsigned int i2s_out_01_pins[] = { PIN(GPIOAO_11, AO_OFF) };
324
325static const unsigned int uart_tx_ao_b0_pins[] = { PIN(GPIOAO_0, AO_OFF) };
326static const unsigned int uart_rx_ao_b0_pins[] = { PIN(GPIOAO_1, AO_OFF) };
327static const unsigned int uart_cts_ao_b_pins[] = { PIN(GPIOAO_2, AO_OFF) };
328static const unsigned int uart_rts_ao_b_pins[] = { PIN(GPIOAO_3, AO_OFF) };
329static const unsigned int uart_tx_ao_b1_pins[] = { PIN(GPIOAO_4, AO_OFF) };
330static const unsigned int uart_rx_ao_b1_pins[] = { PIN(GPIOAO_5, AO_OFF) };
331static const unsigned int spdif_out_1_pins[] = { PIN(GPIOAO_6, AO_OFF) };
332
333static const unsigned int i2s_in_ch01_pins[] = { PIN(GPIOAO_6, AO_OFF) };
334static const unsigned int i2s_ao_clk_in_pins[] = { PIN(GPIOAO_9, AO_OFF) };
335static const unsigned int i2s_lr_clk_in_pins[] = { PIN(GPIOAO_10, AO_OFF) };
336
337/* bank DIF */
338static const unsigned int eth_rxd1_pins[] = { PIN(DIF_0_P, 0) };
339static const unsigned int eth_rxd0_pins[] = { PIN(DIF_0_N, 0) };
340static const unsigned int eth_rx_dv_pins[] = { PIN(DIF_1_P, 0) };
341static const unsigned int eth_rx_clk_pins[] = { PIN(DIF_1_N, 0) };
342static const unsigned int eth_txd0_1_pins[] = { PIN(DIF_2_P, 0) };
343static const unsigned int eth_txd1_1_pins[] = { PIN(DIF_2_N, 0) };
344static const unsigned int eth_tx_en_pins[] = { PIN(DIF_3_P, 0) };
345static const unsigned int eth_ref_clk_pins[] = { PIN(DIF_3_N, 0) };
346static const unsigned int eth_mdc_pins[] = { PIN(DIF_4_P, 0) };
347static const unsigned int eth_mdio_en_pins[] = { PIN(DIF_4_N, 0) };
348
349static struct meson_pmx_group meson8b_groups[] = {
350 GPIO_GROUP(GPIOX_0, 0),
351 GPIO_GROUP(GPIOX_1, 0),
352 GPIO_GROUP(GPIOX_2, 0),
353 GPIO_GROUP(GPIOX_3, 0),
354 GPIO_GROUP(GPIOX_4, 0),
355 GPIO_GROUP(GPIOX_5, 0),
356 GPIO_GROUP(GPIOX_6, 0),
357 GPIO_GROUP(GPIOX_7, 0),
358 GPIO_GROUP(GPIOX_8, 0),
359 GPIO_GROUP(GPIOX_9, 0),
360 GPIO_GROUP(GPIOX_10, 0),
361 GPIO_GROUP(GPIOX_11, 0),
362 GPIO_GROUP(GPIOX_16, 0),
363 GPIO_GROUP(GPIOX_17, 0),
364 GPIO_GROUP(GPIOX_18, 0),
365 GPIO_GROUP(GPIOX_19, 0),
366 GPIO_GROUP(GPIOX_20, 0),
367 GPIO_GROUP(GPIOX_21, 0),
368
369 GPIO_GROUP(GPIOY_0, 0),
370 GPIO_GROUP(GPIOY_1, 0),
371 GPIO_GROUP(GPIOY_3, 0),
372 GPIO_GROUP(GPIOY_6, 0),
373 GPIO_GROUP(GPIOY_7, 0),
374 GPIO_GROUP(GPIOY_8, 0),
375 GPIO_GROUP(GPIOY_9, 0),
376 GPIO_GROUP(GPIOY_10, 0),
377 GPIO_GROUP(GPIOY_11, 0),
378 GPIO_GROUP(GPIOY_12, 0),
379 GPIO_GROUP(GPIOY_13, 0),
380 GPIO_GROUP(GPIOY_14, 0),
381
382 GPIO_GROUP(GPIODV_9, 0),
383 GPIO_GROUP(GPIODV_24, 0),
384 GPIO_GROUP(GPIODV_25, 0),
385 GPIO_GROUP(GPIODV_26, 0),
386 GPIO_GROUP(GPIODV_27, 0),
387 GPIO_GROUP(GPIODV_28, 0),
388 GPIO_GROUP(GPIODV_29, 0),
389
390 GPIO_GROUP(GPIOH_0, 0),
391 GPIO_GROUP(GPIOH_1, 0),
392 GPIO_GROUP(GPIOH_2, 0),
393 GPIO_GROUP(GPIOH_3, 0),
394 GPIO_GROUP(GPIOH_4, 0),
395 GPIO_GROUP(GPIOH_5, 0),
396 GPIO_GROUP(GPIOH_6, 0),
397 GPIO_GROUP(GPIOH_7, 0),
398 GPIO_GROUP(GPIOH_8, 0),
399 GPIO_GROUP(GPIOH_9, 0),
400
401 GPIO_GROUP(DIF_0_P, 0),
402 GPIO_GROUP(DIF_0_N, 0),
403 GPIO_GROUP(DIF_1_P, 0),
404 GPIO_GROUP(DIF_1_N, 0),
405 GPIO_GROUP(DIF_2_P, 0),
406 GPIO_GROUP(DIF_2_N, 0),
407 GPIO_GROUP(DIF_3_P, 0),
408 GPIO_GROUP(DIF_3_N, 0),
409 GPIO_GROUP(DIF_4_P, 0),
410 GPIO_GROUP(DIF_4_N, 0),
411
412 GPIO_GROUP(GPIOAO_0, AO_OFF),
413 GPIO_GROUP(GPIOAO_1, AO_OFF),
414 GPIO_GROUP(GPIOAO_2, AO_OFF),
415 GPIO_GROUP(GPIOAO_3, AO_OFF),
416 GPIO_GROUP(GPIOAO_4, AO_OFF),
417 GPIO_GROUP(GPIOAO_5, AO_OFF),
418 GPIO_GROUP(GPIOAO_6, AO_OFF),
419 GPIO_GROUP(GPIOAO_7, AO_OFF),
420 GPIO_GROUP(GPIOAO_8, AO_OFF),
421 GPIO_GROUP(GPIOAO_9, AO_OFF),
422 GPIO_GROUP(GPIOAO_10, AO_OFF),
423 GPIO_GROUP(GPIOAO_11, AO_OFF),
424 GPIO_GROUP(GPIOAO_12, AO_OFF),
425 GPIO_GROUP(GPIOAO_13, AO_OFF),
426 GPIO_GROUP(GPIO_BSD_EN, AO_OFF),
427 GPIO_GROUP(GPIO_TEST_N, AO_OFF),
428
429 /* bank X */
430 GROUP(sd_d0_a, 8, 5),
431 GROUP(sd_d1_a, 8, 4),
432 GROUP(sd_d2_a, 8, 3),
433 GROUP(sd_d3_a, 8, 2),
434 GROUP(sdxc_d0_0_a, 5, 29),
435 GROUP(sdxc_d47_a, 5, 12),
436 GROUP(sdxc_d13_0_a, 5, 28),
437 GROUP(sd_clk_a, 8, 1),
438 GROUP(sd_cmd_a, 8, 0),
439 GROUP(xtal_32k_out, 3, 22),
440 GROUP(xtal_24m_out, 3, 20),
441 GROUP(uart_tx_b0, 4, 9),
442 GROUP(uart_rx_b0, 4, 8),
443 GROUP(uart_cts_b0, 4, 7),
444 GROUP(uart_rts_b0, 4, 6),
445 GROUP(sdxc_d0_1_a, 5, 14),
446 GROUP(sdxc_d13_1_a, 5, 13),
447 GROUP(pcm_out_a, 3, 30),
448 GROUP(pcm_in_a, 3, 29),
449 GROUP(pcm_fs_a, 3, 28),
450 GROUP(pcm_clk_a, 3, 27),
451 GROUP(sdxc_clk_a, 5, 11),
452 GROUP(sdxc_cmd_a, 5, 10),
453 GROUP(pwm_vs_0, 7, 31),
454 GROUP(pwm_e, 9, 19),
455 GROUP(pwm_vs_1, 7, 30),
456 GROUP(uart_tx_a, 4, 17),
457 GROUP(uart_rx_a, 4, 16),
458 GROUP(uart_cts_a, 4, 15),
459 GROUP(uart_rts_a, 4, 14),
460 GROUP(uart_tx_b1, 6, 19),
461 GROUP(uart_rx_b1, 6, 18),
462 GROUP(uart_cts_b1, 6, 17),
463 GROUP(uart_rts_b1, 6, 16),
464 GROUP(iso7816_0_clk, 5, 9),
465 GROUP(iso7816_0_data, 5, 8),
466 GROUP(spi_sclk_0, 4, 22),
467 GROUP(spi_miso_0, 4, 24),
468 GROUP(spi_mosi_0, 4, 23),
469 GROUP(iso7816_det, 4, 21),
470 GROUP(iso7816_reset, 4, 20),
471 GROUP(iso7816_1_clk, 4, 19),
472 GROUP(iso7816_1_data, 4, 18),
473 GROUP(spi_ss0_0, 4, 25),
474 GROUP(tsin_clk_b, 3, 6),
475 GROUP(tsin_sop_b, 3, 7),
476 GROUP(tsin_d0_b, 3, 8),
477 GROUP(pwm_b, 2, 3),
478 GROUP(i2c_sda_d0, 4, 5),
479 GROUP(i2c_sck_d0, 4, 4),
480 GROUP(tsin_d_valid_b, 3, 9),
481
482 /* bank Y */
483 GROUP(tsin_d_valid_a, 3, 2),
484 GROUP(tsin_sop_a, 3, 1),
485 GROUP(tsin_d17_a, 3, 5),
486 GROUP(tsin_clk_a, 3, 0),
487 GROUP(tsin_d0_a, 3, 4),
488 GROUP(spdif_out_0, 1, 7),
489 GROUP(xtal_24m, 3, 18),
490 GROUP(iso7816_2_clk, 5, 7),
491 GROUP(iso7816_2_data, 5, 6),
492
493 /* bank DV */
494 GROUP(pwm_d, 3, 26),
495 GROUP(pwm_c0, 3, 25),
496 GROUP(pwm_vs_2, 7, 28),
497 GROUP(pwm_vs_3, 7, 27),
498 GROUP(pwm_vs_4, 7, 26),
499 GROUP(xtal24_out, 7, 25),
500 GROUP(uart_tx_c, 6, 23),
501 GROUP(uart_rx_c, 6, 22),
502 GROUP(uart_cts_c, 6, 21),
503 GROUP(uart_rts_c, 6, 20),
504 GROUP(pwm_c1, 3, 24),
505 GROUP(i2c_sda_a, 9, 31),
506 GROUP(i2c_sck_a, 9, 30),
507 GROUP(i2c_sda_b0, 9, 29),
508 GROUP(i2c_sck_b0, 9, 28),
509 GROUP(i2c_sda_c0, 9, 27),
510 GROUP(i2c_sck_c0, 9, 26),
511
512 /* bank H */
513 GROUP(hdmi_hpd, 1, 26),
514 GROUP(hdmi_sda, 1, 25),
515 GROUP(hdmi_scl, 1, 24),
516 GROUP(hdmi_cec_0, 1, 23),
517 GROUP(eth_txd1_0, 7, 21),
518 GROUP(eth_txd0_0, 7, 20),
519 GROUP(clk_24m_out, 4, 1),
520 GROUP(spi_ss1, 8, 11),
521 GROUP(spi_ss2, 8, 12),
522 GROUP(spi_ss0_1, 9, 13),
523 GROUP(spi_miso_1, 9, 12),
524 GROUP(spi_mosi_1, 9, 11),
525 GROUP(spi_sclk_1, 9, 10),
526 GROUP(eth_txd3, 6, 13),
527 GROUP(eth_txd2, 6, 12),
528 GROUP(eth_tx_clk, 6, 11),
529 GROUP(i2c_sda_b1, 5, 27),
530 GROUP(i2c_sck_b1, 5, 26),
531 GROUP(i2c_sda_c1, 5, 25),
532 GROUP(i2c_sck_c1, 5, 24),
533 GROUP(i2c_sda_d1, 4, 3),
534 GROUP(i2c_sck_d1, 4, 2),
535
536 /* bank BOOT */
537 GROUP(nand_io, 2, 26),
538 GROUP(nand_io_ce0, 2, 25),
539 GROUP(nand_io_ce1, 2, 24),
540 GROUP(nand_io_rb0, 2, 17),
541 GROUP(nand_ale, 2, 21),
542 GROUP(nand_cle, 2, 20),
543 GROUP(nand_wen_clk, 2, 19),
544 GROUP(nand_ren_clk, 2, 18),
545 GROUP(nand_dqs_0, 2, 27),
546 GROUP(nand_dqs_1, 2, 28),
547 GROUP(sdxc_d0_c, 4, 30),
548 GROUP(sdxc_d13_c, 4, 29),
549 GROUP(sdxc_d47_c, 4, 28),
550 GROUP(sdxc_clk_c, 7, 19),
551 GROUP(sdxc_cmd_c, 7, 18),
552 GROUP(nor_d, 5, 1),
553 GROUP(nor_q, 5, 3),
554 GROUP(nor_c, 5, 2),
555 GROUP(nor_cs, 5, 0),
556 GROUP(sd_d0_c, 6, 29),
557 GROUP(sd_d1_c, 6, 28),
558 GROUP(sd_d2_c, 6, 27),
559 GROUP(sd_d3_c, 6, 26),
560 GROUP(sd_cmd_c, 6, 30),
561 GROUP(sd_clk_c, 6, 31),
562
563 /* bank CARD */
564 GROUP(sd_d1_b, 2, 14),
565 GROUP(sd_d0_b, 2, 15),
566 GROUP(sd_clk_b, 2, 11),
567 GROUP(sd_cmd_b, 2, 10),
568 GROUP(sd_d3_b, 2, 12),
569 GROUP(sd_d2_b, 2, 13),
570 GROUP(sdxc_d13_b, 2, 6),
571 GROUP(sdxc_d0_b, 2, 7),
572 GROUP(sdxc_clk_b, 2, 5),
573 GROUP(sdxc_cmd_b, 2, 4),
574
575 /* bank AO */
576 GROUP(uart_tx_ao_a, 0, 12),
577 GROUP(uart_rx_ao_a, 0, 11),
578 GROUP(uart_cts_ao_a, 0, 10),
579 GROUP(uart_rts_ao_a, 0, 9),
580 GROUP(i2c_mst_sck_ao, 0, 6),
581 GROUP(i2c_mst_sda_ao, 0, 5),
582 GROUP(clk_32k_in_out, 0, 18),
583 GROUP(remote_input, 0, 0),
584 GROUP(hdmi_cec_1, 0, 17),
585 GROUP(ir_blaster, 0, 31),
586 GROUP(pwm_c2, 0, 22),
587 GROUP(i2c_sck_ao, 0, 2),
588 GROUP(i2c_sda_ao, 0, 1),
589 GROUP(ir_remote_out, 0, 21),
590 GROUP(i2s_am_clk_out, 0, 30),
591 GROUP(i2s_ao_clk_out, 0, 29),
592 GROUP(i2s_lr_clk_out, 0, 28),
593 GROUP(i2s_out_01, 0, 27),
594 GROUP(uart_tx_ao_b0, 0, 26),
595 GROUP(uart_rx_ao_b0, 0, 25),
596 GROUP(uart_cts_ao_b, 0, 8),
597 GROUP(uart_rts_ao_b, 0, 7),
598 GROUP(uart_tx_ao_b1, 0, 24),
599 GROUP(uart_rx_ao_b1, 0, 23),
600 GROUP(spdif_out_1, 0, 16),
601 GROUP(i2s_in_ch01, 0, 13),
602 GROUP(i2s_ao_clk_in, 0, 15),
603 GROUP(i2s_lr_clk_in, 0, 14),
604
605 /* bank DIF */
606 GROUP(eth_rxd1, 6, 0),
607 GROUP(eth_rxd0, 6, 1),
608 GROUP(eth_rx_dv, 6, 2),
609 GROUP(eth_rx_clk, 6, 3),
610 GROUP(eth_txd0_1, 6, 4),
611 GROUP(eth_txd1_1, 6, 5),
612 GROUP(eth_tx_en, 6, 0),
613 GROUP(eth_ref_clk, 6, 8),
614 GROUP(eth_mdc, 6, 9),
615 GROUP(eth_mdio_en, 6, 10),
616};
617
618static const char * const gpio_groups[] = {
619 "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
620 "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
621 "GPIOX_10", "GPIOX_11", "GPIOX_16", "GPIOX_17", "GPIOX_18",
622 "GPIOX_19", "GPIOX_20", "GPIOX_21",
623
624 "GPIOY_0", "GPIOY_1", "GPIOY_3", "GPIOY_6", "GPIOY_7",
625 "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11", "GPIOY_12",
626 "GPIOY_13", "GPIOY_14",
627
628 "GPIODV_9", "GPIODV_24", "GPIODV_25", "GPIODV_26",
629 "GPIODV_27", "GPIODV_28", "GPIODV_29",
630
631 "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
632 "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9",
633
634 "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4",
635 "CARD_5", "CARD_6",
636
637 "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4",
638 "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9",
639 "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14",
640 "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18",
641
642 "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3",
643 "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7",
644 "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11",
645 "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N",
646
647 "DIF_0_P", "DIF_0_N", "DIF_1_P", "DIF_1_N",
648 "DIF_2_P", "DIF_2_N", "DIF_3_P", "DIF_3_N",
649 "DIF_4_P", "DIF_4_N"
650};
651
652static const char * const sd_a_groups[] = {
653 "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a",
654 "sd_cmd_a"
655};
656
657static const char * const sdxc_a_groups[] = {
658 "sdxc_d0_0_a", "sdxc_d13_0_a", "sdxc_d47_a", "sdxc_clk_a",
659 "sdxc_cmd_a", "sdxc_d0_1_a", "sdxc_d0_13_1_a"
660};
661
662static const char * const pcm_a_groups[] = {
663 "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a"
664};
665
666static const char * const uart_a_groups[] = {
667 "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a"
668};
669
670static const char * const uart_b_groups[] = {
671 "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0",
672 "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1"
673};
674
675static const char * const iso7816_groups[] = {
676 "iso7816_det", "iso7816_reset", "iso7816_0_clk", "iso7816_0_data",
677 "iso7816_1_clk", "iso7816_1_data", "iso7816_2_clk", "iso7816_2_data"
678};
679
680static const char * const i2c_d_groups[] = {
681 "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1"
682};
683
684static const char * const xtal_groups[] = {
685 "xtal_32k_out", "xtal_24m_out", "xtal_24m", "xtal24_out"
686};
687
688static const char * const uart_c_groups[] = {
689 "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c"
690};
691
692static const char * const i2c_c_groups[] = {
693 "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1"
694};
695
696static const char * const hdmi_groups[] = {
697 "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec_0",
698 "hdmi_cec_1"
699};
700
701static const char * const spi_groups[] = {
702 "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0",
703 "spi_ss0_1", "spi_ss1", "spi_sclk_1", "spi_mosi_1",
704 "spi_miso_1", "spi_ss2"
705};
706
707static const char * const ethernet_groups[] = {
708 "eth_tx_clk", "eth_tx_en", "eth_txd1_0", "eth_txd1_1",
709 "eth_txd0_0", "eth_txd0_1", "eth_rx_clk", "eth_rx_dv",
710 "eth_rxd1", "eth_rxd0", "eth_mdio_en", "eth_mdc", "eth_ref_clk",
711 "eth_txd2", "eth_txd3"
712};
713
714static const char * const i2c_a_groups[] = {
715 "i2c_sda_a", "i2c_sck_a",
716};
717
718static const char * const i2c_b_groups[] = {
719 "i2c_sda_b0", "i2c_sck_b0", "i2c_sda_b1", "i2c_sck_b1"
720};
721
722static const char * const sd_c_groups[] = {
723 "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c",
724 "sd_cmd_c", "sd_clk_c"
725};
726
727static const char * const sdxc_c_groups[] = {
728 "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c",
729 "sdxc_clk_c"
730};
731
732static const char * const nand_groups[] = {
733 "nand_io", "nand_io_ce0", "nand_io_ce1",
734 "nand_io_rb0", "nand_ale", "nand_cle",
735 "nand_wen_clk", "nand_ren_clk", "nand_dqs0",
736 "nand_dqs1"
737};
738
739static const char * const nor_groups[] = {
740 "nor_d", "nor_q", "nor_c", "nor_cs"
741};
742
743static const char * const sd_b_groups[] = {
744 "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b",
745 "sd_d3_b", "sd_d2_b"
746};
747
748static const char * const sdxc_b_groups[] = {
749 "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b"
750};
751
752static const char * const uart_ao_groups[] = {
753 "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
754};
755
756static const char * const remote_groups[] = {
757 "remote_input", "ir_blaster", "ir_remote_out"
758};
759
760static const char * const i2c_slave_ao_groups[] = {
761 "i2c_sck_ao", "i2c_sda_ao"
762};
763
764static const char * const uart_ao_b_groups[] = {
765 "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1",
766 "uart_cts_ao_b", "uart_rts_ao_b"
767};
768
769static const char * const i2c_mst_ao_groups[] = {
770 "i2c_mst_sck_ao", "i2c_mst_sda_ao"
771};
772
773static const char * const clk_groups[] = {
774 "clk_24m_out", "clk_32k_in_out"
775};
776
777static const char * const spdif_groups[] = {
778 "spdif_out_1", "spdif_out_0"
779};
780
781static const char * const i2s_groups[] = {
782 "i2s_am_clk_out", "i2s_ao_clk_out", "i2s_lr_clk_out",
783 "i2s_out_01", "i2s_in_ch01", "i2s_ao_clk_in",
784 "i2s_lr_clk_in"
785};
786
787static const char * const pwm_b_groups[] = {
788 "pwm_b"
789};
790
791static const char * const pwm_c_groups[] = {
792 "pwm_c0", "pwm_c1", "pwm_c2"
793};
794
795static const char * const pwm_d_groups[] = {
796 "pwm_d"
797};
798
799static const char * const pwm_e_groups[] = {
800 "pwm_e"
801};
802
803static const char * const pwm_vs_groups[] = {
804 "pwm_vs_0", "pwm_vs_1", "pwm_vs_2",
805 "pwm_vs_3", "pwm_vs_4"
806};
807
808static const char * const tsin_a_groups[] = {
809 "tsin_d0_a", "tsin_d17_a", "tsin_clk_a", "tsin_sop_a",
810 "tsin_d_valid_a"
811};
812
813static const char * const tsin_b_groups[] = {
814 "tsin_d0_b", "tsin_clk_b", "tsin_sop_b", "tsin_d_valid_b"
815};
816
817static struct meson_pmx_func meson8b_functions[] = {
818 FUNCTION(gpio),
819 FUNCTION(sd_a),
820 FUNCTION(sdxc_a),
821 FUNCTION(pcm_a),
822 FUNCTION(uart_a),
823 FUNCTION(uart_b),
824 FUNCTION(iso7816),
825 FUNCTION(i2c_d),
826 FUNCTION(xtal),
827 FUNCTION(uart_c),
828 FUNCTION(i2c_c),
829 FUNCTION(hdmi),
830 FUNCTION(spi),
831 FUNCTION(ethernet),
832 FUNCTION(i2c_a),
833 FUNCTION(i2c_b),
834 FUNCTION(sd_c),
835 FUNCTION(sdxc_c),
836 FUNCTION(nand),
837 FUNCTION(nor),
838 FUNCTION(sd_b),
839 FUNCTION(sdxc_b),
840 FUNCTION(uart_ao),
841 FUNCTION(remote),
842 FUNCTION(i2c_slave_ao),
843 FUNCTION(uart_ao_b),
844 FUNCTION(i2c_mst_ao),
845 FUNCTION(clk),
846 FUNCTION(spdif),
847 FUNCTION(i2s),
848 FUNCTION(pwm_b),
849 FUNCTION(pwm_c),
850 FUNCTION(pwm_d),
851 FUNCTION(pwm_e),
852 FUNCTION(pwm_vs),
853 FUNCTION(tsin_a),
854 FUNCTION(tsin_b),
855};
856
857static struct meson_bank meson8b_banks[] = {
858 /* name first last pullen pull dir out in */
859 BANK("X", PIN(GPIOX_0, 0), PIN(GPIOX_21, 0), 4, 0, 4, 0, 0, 0, 1, 0, 2, 0),
860 BANK("Y", PIN(GPIOY_0, 0), PIN(GPIOY_14, 0), 3, 0, 3, 0, 3, 0, 4, 0, 5, 0),
861 BANK("DV", PIN(GPIODV_9, 0), PIN(GPIODV_29, 0), 0, 0, 0, 0, 7, 0, 8, 0, 9, 0),
862 BANK("H", PIN(GPIOH_0, 0), PIN(GPIOH_9, 0), 1, 16, 1, 16, 9, 19, 10, 19, 11, 19),
863 BANK("CARD", PIN(CARD_0, 0), PIN(CARD_6, 0), 2, 20, 2, 20, 0, 22, 1, 22, 2, 22),
864 BANK("BOOT", PIN(BOOT_0, 0), PIN(BOOT_18, 0), 2, 0, 2, 0, 9, 0, 10, 0, 11, 0),
865 BANK("DIF", PIN(DIF_0_P, 0), PIN(DIF_4_N, 0), 5, 8, 5, 8, 12, 12, 13, 12, 14, 12),
866};
867
868static struct meson_bank meson8b_ao_banks[] = {
869 /* name first last pullen pull dir out in */
870 BANK("AO", PIN(GPIOAO_0, AO_OFF), PIN(GPIO_TEST_N, AO_OFF), 0, 0, 0, 16, 0, 0, 0, 16, 1, 0),
871};
872
873static struct meson_domain_data meson8b_domain_data[] = {
874 {
875 .name = "banks",
876 .banks = meson8b_banks,
877 .num_banks = ARRAY_SIZE(meson8b_banks),
878 .pin_base = 0,
879 .num_pins = 83,
880 },
881 {
882 .name = "ao-bank",
883 .banks = meson8b_ao_banks,
884 .num_banks = ARRAY_SIZE(meson8b_ao_banks),
885 .pin_base = 83,
886 .num_pins = 16,
887 },
888};
889
890struct meson_pinctrl_data meson8b_pinctrl_data = {
891 .pins = meson8b_pins,
892 .groups = meson8b_groups,
893 .funcs = meson8b_functions,
894 .domain_data = meson8b_domain_data,
895 .num_pins = ARRAY_SIZE(meson8b_pins),
896 .num_groups = ARRAY_SIZE(meson8b_groups),
897 .num_funcs = ARRAY_SIZE(meson8b_functions),
898 .num_domains = ARRAY_SIZE(meson8b_domain_data),
899};
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index d6dd8358a6f6..170602407c0d 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -26,6 +26,10 @@ config PINCTRL_ARMADA_38X
26 bool 26 bool
27 select PINCTRL_MVEBU 27 select PINCTRL_MVEBU
28 28
29config PINCTRL_ARMADA_39X
30 bool
31 select PINCTRL_MVEBU
32
29config PINCTRL_ARMADA_XP 33config PINCTRL_ARMADA_XP
30 bool 34 bool
31 select PINCTRL_MVEBU 35 select PINCTRL_MVEBU
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index a0818e96374b..554d8af14eeb 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_PINCTRL_KIRKWOOD) += pinctrl-kirkwood.o
4obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o 4obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
5obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o 5obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
6obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o 6obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
7obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
7obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o 8obj-$(CONFIG_PINCTRL_ARMADA_XP) += pinctrl-armada-xp.o
8obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o 9obj-$(CONFIG_PINCTRL_ORION) += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c
index c4f51d0cd2cc..42f930f70de3 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c
@@ -379,7 +379,7 @@ static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
379 379
380static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info; 380static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;
381 381
382static struct of_device_id armada_370_pinctrl_of_match[] = { 382static const struct of_device_id armada_370_pinctrl_of_match[] = {
383 { .compatible = "marvell,mv88f6710-pinctrl" }, 383 { .compatible = "marvell,mv88f6710-pinctrl" },
384 { }, 384 { },
385}; 385};
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-375.c b/drivers/pinctrl/mvebu/pinctrl-armada-375.c
index cd7c8f51f7d9..ca1e7571fedb 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-375.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-375.c
@@ -399,7 +399,7 @@ static struct mvebu_mpp_mode mv88f6720_mpp_modes[] = {
399 399
400static struct mvebu_pinctrl_soc_info armada_375_pinctrl_info; 400static struct mvebu_pinctrl_soc_info armada_375_pinctrl_info;
401 401
402static struct of_device_id armada_375_pinctrl_of_match[] = { 402static const struct of_device_id armada_375_pinctrl_of_match[] = {
403 { .compatible = "marvell,mv88f6720-pinctrl" }, 403 { .compatible = "marvell,mv88f6720-pinctrl" },
404 { }, 404 { },
405}; 405};
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
index 7302f66f4f19..83bbcc72be1f 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-38x.c
@@ -389,7 +389,7 @@ static struct mvebu_mpp_mode armada_38x_mpp_modes[] = {
389 389
390static struct mvebu_pinctrl_soc_info armada_38x_pinctrl_info; 390static struct mvebu_pinctrl_soc_info armada_38x_pinctrl_info;
391 391
392static struct of_device_id armada_38x_pinctrl_of_match[] = { 392static const struct of_device_id armada_38x_pinctrl_of_match[] = {
393 { 393 {
394 .compatible = "marvell,mv88f6810-pinctrl", 394 .compatible = "marvell,mv88f6810-pinctrl",
395 .data = (void *) V_88F6810, 395 .data = (void *) V_88F6810,
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
new file mode 100644
index 000000000000..42491624d660
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
@@ -0,0 +1,432 @@
1/*
2 * Marvell Armada 39x pinctrl driver based on mvebu pinctrl core
3 *
4 * Copyright (C) 2015 Marvell
5 *
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/err.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/platform_device.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21#include <linux/pinctrl/pinctrl.h>
22
23#include "pinctrl-mvebu.h"
24
25static void __iomem *mpp_base;
26
27static int armada_39x_mpp_ctrl_get(unsigned pid, unsigned long *config)
28{
29 return default_mpp_ctrl_get(mpp_base, pid, config);
30}
31
32static int armada_39x_mpp_ctrl_set(unsigned pid, unsigned long config)
33{
34 return default_mpp_ctrl_set(mpp_base, pid, config);
35}
36
37enum {
38 V_88F6920 = BIT(0),
39 V_88F6928 = BIT(1),
40 V_88F6920_PLUS = (V_88F6920 | V_88F6928),
41};
42
43static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
44 MPP_MODE(0,
45 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
46 MPP_VAR_FUNCTION(1, "ua0", "rxd", V_88F6920_PLUS)),
47 MPP_MODE(1,
48 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
49 MPP_VAR_FUNCTION(1, "ua0", "txd", V_88F6920_PLUS)),
50 MPP_MODE(2,
51 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
52 MPP_VAR_FUNCTION(1, "i2c0", "sck", V_88F6920_PLUS)),
53 MPP_MODE(3,
54 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
55 MPP_VAR_FUNCTION(1, "i2c0", "sda", V_88F6920_PLUS)),
56 MPP_MODE(4,
57 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
58 MPP_VAR_FUNCTION(2, "ua1", "txd", V_88F6920_PLUS),
59 MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS),
60 MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)),
61 MPP_MODE(5,
62 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
63 MPP_VAR_FUNCTION(2, "ua1", "rxd", V_88F6920_PLUS),
64 MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS),
65 MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)),
66 MPP_MODE(6,
67 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
68 MPP_VAR_FUNCTION(5, "dev", "cs3", V_88F6920_PLUS),
69 MPP_VAR_FUNCTION(7, "xsmi", "mdio", V_88F6920_PLUS)),
70 MPP_MODE(7,
71 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
72 MPP_VAR_FUNCTION(5, "dev", "ad9", V_88F6920_PLUS),
73 MPP_VAR_FUNCTION(7, "xsmi", "mdc", V_88F6920_PLUS)),
74 MPP_MODE(8,
75 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
76 MPP_VAR_FUNCTION(5, "dev", "ad10", V_88F6920_PLUS),
77 MPP_VAR_FUNCTION(7, "ptp", "trig", V_88F6920_PLUS)),
78 MPP_MODE(9,
79 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
80 MPP_VAR_FUNCTION(5, "dev", "ad11", V_88F6920_PLUS),
81 MPP_VAR_FUNCTION(7, "ptp", "clk", V_88F6920_PLUS)),
82 MPP_MODE(10,
83 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
84 MPP_VAR_FUNCTION(5, "dev", "ad12", V_88F6920_PLUS),
85 MPP_VAR_FUNCTION(7, "ptp", "event", V_88F6920_PLUS)),
86 MPP_MODE(11,
87 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
88 MPP_VAR_FUNCTION(5, "dev", "ad13", V_88F6920_PLUS),
89 MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)),
90 MPP_MODE(12,
91 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
92 MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS),
93 MPP_VAR_FUNCTION(5, "dev", "ad14", V_88F6920_PLUS),
94 MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)),
95 MPP_MODE(13,
96 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
97 MPP_VAR_FUNCTION(5, "dev", "ad15", V_88F6920_PLUS),
98 MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)),
99 MPP_MODE(14,
100 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
101 MPP_VAR_FUNCTION(3, "m", "vtt", V_88F6920_PLUS),
102 MPP_VAR_FUNCTION(5, "dev", "wen1", V_88F6920_PLUS),
103 MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)),
104 MPP_MODE(15,
105 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
106 MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS),
107 MPP_VAR_FUNCTION(4, "spi0", "mosi", V_88F6920_PLUS),
108 MPP_VAR_FUNCTION(7, "i2c1", "sck", V_88F6920_PLUS)),
109 MPP_MODE(16,
110 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
111 MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS),
112 MPP_VAR_FUNCTION(4, "spi0", "miso", V_88F6920_PLUS),
113 MPP_VAR_FUNCTION(7, "i2c1", "sda", V_88F6920_PLUS)),
114 MPP_MODE(17,
115 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
116 MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS),
117 MPP_VAR_FUNCTION(4, "spi0", "sck", V_88F6920_PLUS),
118 MPP_VAR_FUNCTION(7, "smi", "mdio", V_88F6920_PLUS)),
119 MPP_MODE(18,
120 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
121 MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6920_PLUS),
122 MPP_VAR_FUNCTION(4, "spi0", "cs0", V_88F6920_PLUS),
123 MPP_VAR_FUNCTION(7, "i2c2", "sck", V_88F6920_PLUS)),
124 MPP_MODE(19,
125 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
126 MPP_VAR_FUNCTION(4, "sata1", "present", V_88F6928),
127 MPP_VAR_FUNCTION(5, "ua0", "cts", V_88F6920_PLUS),
128 MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS),
129 MPP_VAR_FUNCTION(7, "i2c2", "sda", V_88F6920_PLUS)),
130 MPP_MODE(20,
131 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
132 MPP_VAR_FUNCTION(4, "sata0", "present", V_88F6928),
133 MPP_VAR_FUNCTION(5, "ua0", "rts", V_88F6920_PLUS),
134 MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS),
135 MPP_VAR_FUNCTION(7, "smi", "mdc", V_88F6920_PLUS)),
136 MPP_MODE(21,
137 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
138 MPP_VAR_FUNCTION(1, "spi0", "cs1", V_88F6920_PLUS),
139 MPP_VAR_FUNCTION(3, "sata0", "present", V_88F6928),
140 MPP_VAR_FUNCTION(4, "sd", "cmd", V_88F6920_PLUS),
141 MPP_VAR_FUNCTION(5, "dev", "bootcs", V_88F6920_PLUS),
142 MPP_VAR_FUNCTION(8, "ge", "rxd0", V_88F6920_PLUS)),
143 MPP_MODE(22,
144 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
145 MPP_VAR_FUNCTION(1, "spi0", "mosi", V_88F6920_PLUS),
146 MPP_VAR_FUNCTION(5, "dev", "ad0", V_88F6920_PLUS)),
147 MPP_MODE(23,
148 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
149 MPP_VAR_FUNCTION(1, "spi0", "sck", V_88F6920_PLUS),
150 MPP_VAR_FUNCTION(5, "dev", "ad2", V_88F6920_PLUS)),
151 MPP_MODE(24,
152 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
153 MPP_VAR_FUNCTION(1, "spi0", "miso", V_88F6920_PLUS),
154 MPP_VAR_FUNCTION(2, "ua0", "cts", V_88F6920_PLUS),
155 MPP_VAR_FUNCTION(3, "ua1", "rxd", V_88F6920_PLUS),
156 MPP_VAR_FUNCTION(4, "sd", "d4", V_88F6920_PLUS),
157 MPP_VAR_FUNCTION(5, "dev", "readyn", V_88F6920_PLUS)),
158 MPP_MODE(25,
159 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
160 MPP_VAR_FUNCTION(1, "spi0", "cs0", V_88F6920_PLUS),
161 MPP_VAR_FUNCTION(2, "ua0", "rts", V_88F6920_PLUS),
162 MPP_VAR_FUNCTION(3, "ua1", "txd", V_88F6920_PLUS),
163 MPP_VAR_FUNCTION(4, "sd", "d5", V_88F6920_PLUS),
164 MPP_VAR_FUNCTION(5, "dev", "cs0", V_88F6920_PLUS)),
165 MPP_MODE(26,
166 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
167 MPP_VAR_FUNCTION(1, "spi0", "cs2", V_88F6920_PLUS),
168 MPP_VAR_FUNCTION(3, "i2c1", "sck", V_88F6920_PLUS),
169 MPP_VAR_FUNCTION(4, "sd", "d6", V_88F6920_PLUS),
170 MPP_VAR_FUNCTION(5, "dev", "cs1", V_88F6920_PLUS)),
171 MPP_MODE(27,
172 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
173 MPP_VAR_FUNCTION(1, "spi0", "cs3", V_88F6920_PLUS),
174 MPP_VAR_FUNCTION(3, "i2c1", "sda", V_88F6920_PLUS),
175 MPP_VAR_FUNCTION(4, "sd", "d7", V_88F6920_PLUS),
176 MPP_VAR_FUNCTION(5, "dev", "cs2", V_88F6920_PLUS),
177 MPP_VAR_FUNCTION(8, "ge", "txclkout", V_88F6920_PLUS)),
178 MPP_MODE(28,
179 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
180 MPP_VAR_FUNCTION(4, "sd", "clk", V_88F6920_PLUS),
181 MPP_VAR_FUNCTION(5, "dev", "ad5", V_88F6920_PLUS),
182 MPP_VAR_FUNCTION(8, "ge", "txd0", V_88F6920_PLUS)),
183 MPP_MODE(29,
184 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
185 MPP_VAR_FUNCTION(5, "dev", "ale0", V_88F6920_PLUS),
186 MPP_VAR_FUNCTION(8, "ge", "txd1", V_88F6920_PLUS)),
187 MPP_MODE(30,
188 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
189 MPP_VAR_FUNCTION(5, "dev", "oen", V_88F6920_PLUS),
190 MPP_VAR_FUNCTION(8, "ge", "txd2", V_88F6920_PLUS)),
191 MPP_MODE(31,
192 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
193 MPP_VAR_FUNCTION(5, "dev", "ale1", V_88F6920_PLUS),
194 MPP_VAR_FUNCTION(8, "ge", "txd3", V_88F6920_PLUS)),
195 MPP_MODE(32,
196 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
197 MPP_VAR_FUNCTION(5, "dev", "wen0", V_88F6920_PLUS),
198 MPP_VAR_FUNCTION(8, "ge", "txctl", V_88F6920_PLUS)),
199 MPP_MODE(33,
200 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
201 MPP_VAR_FUNCTION(1, "m", "decc", V_88F6920_PLUS),
202 MPP_VAR_FUNCTION(5, "dev", "ad3", V_88F6920_PLUS)),
203 MPP_MODE(34,
204 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
205 MPP_VAR_FUNCTION(5, "dev", "ad1", V_88F6920_PLUS)),
206 MPP_MODE(35,
207 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
208 MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS),
209 MPP_VAR_FUNCTION(5, "dev", "a1", V_88F6920_PLUS)),
210 MPP_MODE(36,
211 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
212 MPP_VAR_FUNCTION(5, "dev", "a0", V_88F6920_PLUS)),
213 MPP_MODE(37,
214 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
215 MPP_VAR_FUNCTION(4, "sd", "d3", V_88F6920_PLUS),
216 MPP_VAR_FUNCTION(5, "dev", "ad8", V_88F6920_PLUS),
217 MPP_VAR_FUNCTION(8, "ge", "rxclk", V_88F6920_PLUS)),
218 MPP_MODE(38,
219 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
220 MPP_VAR_FUNCTION(3, "ref", "clk", V_88F6920_PLUS),
221 MPP_VAR_FUNCTION(4, "sd", "d0", V_88F6920_PLUS),
222 MPP_VAR_FUNCTION(5, "dev", "ad4", V_88F6920_PLUS),
223 MPP_VAR_FUNCTION(8, "ge", "rxd1", V_88F6920_PLUS)),
224 MPP_MODE(39,
225 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
226 MPP_VAR_FUNCTION(1, "i2c1", "sck", V_88F6920_PLUS),
227 MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS),
228 MPP_VAR_FUNCTION(4, "sd", "d1", V_88F6920_PLUS),
229 MPP_VAR_FUNCTION(5, "dev", "a2", V_88F6920_PLUS),
230 MPP_VAR_FUNCTION(8, "ge", "rxd2", V_88F6920_PLUS)),
231 MPP_MODE(40,
232 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
233 MPP_VAR_FUNCTION(1, "i2c1", "sda", V_88F6920_PLUS),
234 MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS),
235 MPP_VAR_FUNCTION(4, "sd", "d2", V_88F6920_PLUS),
236 MPP_VAR_FUNCTION(5, "dev", "ad6", V_88F6920_PLUS),
237 MPP_VAR_FUNCTION(8, "ge", "rxd3", V_88F6920_PLUS)),
238 MPP_MODE(41,
239 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
240 MPP_VAR_FUNCTION(1, "ua1", "rxd", V_88F6920_PLUS),
241 MPP_VAR_FUNCTION(3, "ua0", "cts", V_88F6920_PLUS),
242 MPP_VAR_FUNCTION(4, "spi1", "cs3", V_88F6920_PLUS),
243 MPP_VAR_FUNCTION(5, "dev", "burstn", V_88F6920_PLUS),
244 MPP_VAR_FUNCTION(6, "nd", "rbn0", V_88F6920_PLUS),
245 MPP_VAR_FUNCTION(8, "ge", "rxctl", V_88F6920_PLUS)),
246 MPP_MODE(42,
247 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
248 MPP_VAR_FUNCTION(1, "ua1", "txd", V_88F6920_PLUS),
249 MPP_VAR_FUNCTION(3, "ua0", "rts", V_88F6920_PLUS),
250 MPP_VAR_FUNCTION(5, "dev", "ad7", V_88F6920_PLUS)),
251 MPP_MODE(43,
252 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
253 MPP_VAR_FUNCTION(1, "pcie0", "clkreq", V_88F6920_PLUS),
254 MPP_VAR_FUNCTION(2, "m", "vtt", V_88F6920_PLUS),
255 MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS),
256 MPP_VAR_FUNCTION(4, "spi1", "cs2", V_88F6920_PLUS),
257 MPP_VAR_FUNCTION(5, "dev", "clkout", V_88F6920_PLUS),
258 MPP_VAR_FUNCTION(6, "nd", "rbn1", V_88F6920_PLUS)),
259 MPP_MODE(44,
260 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
261 MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928),
262 MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928),
263 MPP_VAR_FUNCTION(7, "led", "clk", V_88F6920_PLUS)),
264 MPP_MODE(45,
265 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
266 MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS),
267 MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS),
268 MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS)),
269 MPP_MODE(46,
270 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
271 MPP_VAR_FUNCTION(1, "ref", "clk", V_88F6920_PLUS),
272 MPP_VAR_FUNCTION(2, "pcie0", "rstout", V_88F6920_PLUS),
273 MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS),
274 MPP_VAR_FUNCTION(7, "led", "stb", V_88F6920_PLUS)),
275 MPP_MODE(47,
276 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
277 MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928),
278 MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928),
279 MPP_VAR_FUNCTION(7, "led", "data", V_88F6920_PLUS)),
280 MPP_MODE(48,
281 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
282 MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928),
283 MPP_VAR_FUNCTION(2, "m", "vtt", V_88F6920_PLUS),
284 MPP_VAR_FUNCTION(3, "tdm", "pclk", V_88F6928),
285 MPP_VAR_FUNCTION(4, "audio", "mclk", V_88F6928),
286 MPP_VAR_FUNCTION(5, "sd", "d4", V_88F6920_PLUS),
287 MPP_VAR_FUNCTION(6, "pcie0", "clkreq", V_88F6920_PLUS),
288 MPP_VAR_FUNCTION(7, "ua1", "txd", V_88F6920_PLUS)),
289 MPP_MODE(49,
290 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
291 MPP_VAR_FUNCTION(3, "tdm", "fsync", V_88F6928),
292 MPP_VAR_FUNCTION(4, "audio", "lrclk", V_88F6928),
293 MPP_VAR_FUNCTION(5, "sd", "d5", V_88F6920_PLUS),
294 MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)),
295 MPP_MODE(50,
296 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
297 MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS),
298 MPP_VAR_FUNCTION(3, "tdm", "drx", V_88F6928),
299 MPP_VAR_FUNCTION(4, "audio", "extclk", V_88F6928),
300 MPP_VAR_FUNCTION(5, "sd", "cmd", V_88F6920_PLUS),
301 MPP_VAR_FUNCTION(7, "ua2", "rxd", V_88F6920_PLUS)),
302 MPP_MODE(51,
303 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
304 MPP_VAR_FUNCTION(3, "tdm", "dtx", V_88F6928),
305 MPP_VAR_FUNCTION(4, "audio", "sdo", V_88F6928),
306 MPP_VAR_FUNCTION(5, "m", "decc", V_88F6920_PLUS),
307 MPP_VAR_FUNCTION(7, "ua2", "txd", V_88F6920_PLUS)),
308 MPP_MODE(52,
309 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
310 MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS),
311 MPP_VAR_FUNCTION(3, "tdm", "intn", V_88F6928),
312 MPP_VAR_FUNCTION(4, "audio", "sdi", V_88F6928),
313 MPP_VAR_FUNCTION(5, "sd", "d6", V_88F6920_PLUS),
314 MPP_VAR_FUNCTION(7, "i2c3", "sck", V_88F6920_PLUS)),
315 MPP_MODE(53,
316 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
317 MPP_VAR_FUNCTION(1, "sata1", "present", V_88F6928),
318 MPP_VAR_FUNCTION(2, "sata0", "present", V_88F6928),
319 MPP_VAR_FUNCTION(3, "tdm", "rstn", V_88F6928),
320 MPP_VAR_FUNCTION(4, "audio", "bclk", V_88F6928),
321 MPP_VAR_FUNCTION(5, "sd", "d7", V_88F6920_PLUS),
322 MPP_VAR_FUNCTION(7, "i2c3", "sda", V_88F6920_PLUS)),
323 MPP_MODE(54,
324 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
325 MPP_VAR_FUNCTION(1, "sata0", "present", V_88F6928),
326 MPP_VAR_FUNCTION(2, "sata1", "present", V_88F6928),
327 MPP_VAR_FUNCTION(3, "pcie0", "rstout", V_88F6920_PLUS),
328 MPP_VAR_FUNCTION(5, "sd", "d3", V_88F6920_PLUS),
329 MPP_VAR_FUNCTION(7, "ua3", "txd", V_88F6920_PLUS)),
330 MPP_MODE(55,
331 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
332 MPP_VAR_FUNCTION(1, "ua1", "cts", V_88F6920_PLUS),
333 MPP_VAR_FUNCTION(4, "spi1", "cs1", V_88F6920_PLUS),
334 MPP_VAR_FUNCTION(5, "sd", "d0", V_88F6920_PLUS),
335 MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS),
336 MPP_VAR_FUNCTION(7, "ua3", "rxd", V_88F6920_PLUS)),
337 MPP_MODE(56,
338 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
339 MPP_VAR_FUNCTION(1, "ua1", "rts", V_88F6920_PLUS),
340 MPP_VAR_FUNCTION(3, "m", "decc", V_88F6920_PLUS),
341 MPP_VAR_FUNCTION(4, "spi1", "mosi", V_88F6920_PLUS),
342 MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)),
343 MPP_MODE(57,
344 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
345 MPP_VAR_FUNCTION(4, "spi1", "sck", V_88F6920_PLUS),
346 MPP_VAR_FUNCTION(5, "sd", "clk", V_88F6920_PLUS),
347 MPP_VAR_FUNCTION(6, "ua1", "txd", V_88F6920_PLUS)),
348 MPP_MODE(58,
349 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
350 MPP_VAR_FUNCTION(2, "i2c1", "sck", V_88F6920_PLUS),
351 MPP_VAR_FUNCTION(3, "pcie2", "clkreq", V_88F6920_PLUS),
352 MPP_VAR_FUNCTION(4, "spi1", "miso", V_88F6920_PLUS),
353 MPP_VAR_FUNCTION(5, "sd", "d1", V_88F6920_PLUS),
354 MPP_VAR_FUNCTION(6, "ua1", "rxd", V_88F6920_PLUS)),
355 MPP_MODE(59,
356 MPP_VAR_FUNCTION(0, "gpio", NULL, V_88F6920_PLUS),
357 MPP_VAR_FUNCTION(1, "pcie0", "rstout", V_88F6920_PLUS),
358 MPP_VAR_FUNCTION(2, "i2c1", "sda", V_88F6920_PLUS),
359 MPP_VAR_FUNCTION(4, "spi1", "cs0", V_88F6920_PLUS),
360 MPP_VAR_FUNCTION(5, "sd", "d2", V_88F6920_PLUS)),
361};
362
363static struct mvebu_pinctrl_soc_info armada_39x_pinctrl_info;
364
365static const struct of_device_id armada_39x_pinctrl_of_match[] = {
366 {
367 .compatible = "marvell,mv88f6920-pinctrl",
368 .data = (void *) V_88F6920,
369 },
370 {
371 .compatible = "marvell,mv88f6928-pinctrl",
372 .data = (void *) V_88F6928,
373 },
374 { },
375};
376
377static struct mvebu_mpp_ctrl armada_39x_mpp_controls[] = {
378 MPP_FUNC_CTRL(0, 59, NULL, armada_39x_mpp_ctrl),
379};
380
381static struct pinctrl_gpio_range armada_39x_mpp_gpio_ranges[] = {
382 MPP_GPIO_RANGE(0, 0, 0, 32),
383 MPP_GPIO_RANGE(1, 32, 32, 27),
384};
385
386static int armada_39x_pinctrl_probe(struct platform_device *pdev)
387{
388 struct mvebu_pinctrl_soc_info *soc = &armada_39x_pinctrl_info;
389 const struct of_device_id *match =
390 of_match_device(armada_39x_pinctrl_of_match, &pdev->dev);
391 struct resource *res;
392
393 if (!match)
394 return -ENODEV;
395
396 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
397 mpp_base = devm_ioremap_resource(&pdev->dev, res);
398 if (IS_ERR(mpp_base))
399 return PTR_ERR(mpp_base);
400
401 soc->variant = (unsigned) match->data & 0xff;
402 soc->controls = armada_39x_mpp_controls;
403 soc->ncontrols = ARRAY_SIZE(armada_39x_mpp_controls);
404 soc->gpioranges = armada_39x_mpp_gpio_ranges;
405 soc->ngpioranges = ARRAY_SIZE(armada_39x_mpp_gpio_ranges);
406 soc->modes = armada_39x_mpp_modes;
407 soc->nmodes = armada_39x_mpp_controls[0].npins;
408
409 pdev->dev.platform_data = soc;
410
411 return mvebu_pinctrl_probe(pdev);
412}
413
414static int armada_39x_pinctrl_remove(struct platform_device *pdev)
415{
416 return mvebu_pinctrl_remove(pdev);
417}
418
419static struct platform_driver armada_39x_pinctrl_driver = {
420 .driver = {
421 .name = "armada-39x-pinctrl",
422 .of_match_table = of_match_ptr(armada_39x_pinctrl_of_match),
423 },
424 .probe = armada_39x_pinctrl_probe,
425 .remove = armada_39x_pinctrl_remove,
426};
427
428module_platform_driver(armada_39x_pinctrl_driver);
429
430MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
431MODULE_DESCRIPTION("Marvell Armada 39x pinctrl driver");
432MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index fc3376147c18..578db9f033b2 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -34,6 +34,7 @@
34#include "pinctrl-mvebu.h" 34#include "pinctrl-mvebu.h"
35 35
36static void __iomem *mpp_base; 36static void __iomem *mpp_base;
37static u32 *mpp_saved_regs;
37 38
38static int armada_xp_mpp_ctrl_get(unsigned pid, unsigned long *config) 39static int armada_xp_mpp_ctrl_get(unsigned pid, unsigned long *config)
39{ 40{
@@ -361,7 +362,7 @@ static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
361 362
362static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info; 363static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
363 364
364static struct of_device_id armada_xp_pinctrl_of_match[] = { 365static const struct of_device_id armada_xp_pinctrl_of_match[] = {
365 { 366 {
366 .compatible = "marvell,mv78230-pinctrl", 367 .compatible = "marvell,mv78230-pinctrl",
367 .data = (void *) V_MV78230, 368 .data = (void *) V_MV78230,
@@ -406,12 +407,42 @@ static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
406 MPP_GPIO_RANGE(2, 64, 64, 3), 407 MPP_GPIO_RANGE(2, 64, 64, 3),
407}; 408};
408 409
410static int armada_xp_pinctrl_suspend(struct platform_device *pdev,
411 pm_message_t state)
412{
413 struct mvebu_pinctrl_soc_info *soc =
414 platform_get_drvdata(pdev);
415 int i, nregs;
416
417 nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
418
419 for (i = 0; i < nregs; i++)
420 mpp_saved_regs[i] = readl(mpp_base + i * 4);
421
422 return 0;
423}
424
425static int armada_xp_pinctrl_resume(struct platform_device *pdev)
426{
427 struct mvebu_pinctrl_soc_info *soc =
428 platform_get_drvdata(pdev);
429 int i, nregs;
430
431 nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
432
433 for (i = 0; i < nregs; i++)
434 writel(mpp_saved_regs[i], mpp_base + i * 4);
435
436 return 0;
437}
438
409static int armada_xp_pinctrl_probe(struct platform_device *pdev) 439static int armada_xp_pinctrl_probe(struct platform_device *pdev)
410{ 440{
411 struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info; 441 struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
412 const struct of_device_id *match = 442 const struct of_device_id *match =
413 of_match_device(armada_xp_pinctrl_of_match, &pdev->dev); 443 of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
414 struct resource *res; 444 struct resource *res;
445 int nregs;
415 446
416 if (!match) 447 if (!match)
417 return -ENODEV; 448 return -ENODEV;
@@ -459,6 +490,13 @@ static int armada_xp_pinctrl_probe(struct platform_device *pdev)
459 break; 490 break;
460 } 491 }
461 492
493 nregs = DIV_ROUND_UP(soc->nmodes, MVEBU_MPPS_PER_REG);
494
495 mpp_saved_regs = devm_kmalloc(&pdev->dev, nregs * sizeof(u32),
496 GFP_KERNEL);
497 if (!mpp_saved_regs)
498 return -ENOMEM;
499
462 pdev->dev.platform_data = soc; 500 pdev->dev.platform_data = soc;
463 501
464 return mvebu_pinctrl_probe(pdev); 502 return mvebu_pinctrl_probe(pdev);
@@ -476,6 +514,8 @@ static struct platform_driver armada_xp_pinctrl_driver = {
476 }, 514 },
477 .probe = armada_xp_pinctrl_probe, 515 .probe = armada_xp_pinctrl_probe,
478 .remove = armada_xp_pinctrl_remove, 516 .remove = armada_xp_pinctrl_remove,
517 .suspend = armada_xp_pinctrl_suspend,
518 .resume = armada_xp_pinctrl_resume,
479}; 519};
480 520
481module_platform_driver(armada_xp_pinctrl_driver); 521module_platform_driver(armada_xp_pinctrl_driver);
diff --git a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
index dbc673cf7131..0f07dc554a1d 100644
--- a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
+++ b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
@@ -456,7 +456,7 @@ static struct mvebu_pinctrl_soc_info mv98dx4122_info = {
456 .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges), 456 .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
457}; 457};
458 458
459static struct of_device_id kirkwood_pinctrl_of_match[] = { 459static const struct of_device_id kirkwood_pinctrl_of_match[] = {
460 { .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info }, 460 { .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info },
461 { .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info }, 461 { .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info },
462 { .compatible = "marvell,88f6192-pinctrl", .data = &mv88f6192_info }, 462 { .compatible = "marvell,88f6192-pinctrl", .data = &mv88f6192_info },
diff --git a/drivers/pinctrl/mvebu/pinctrl-orion.c b/drivers/pinctrl/mvebu/pinctrl-orion.c
index 3a632efb56bb..3b7122d826e4 100644
--- a/drivers/pinctrl/mvebu/pinctrl-orion.c
+++ b/drivers/pinctrl/mvebu/pinctrl-orion.c
@@ -211,7 +211,7 @@ static struct mvebu_pinctrl_soc_info mv88f5281_info = {
211 * There are multiple variants of the Orion SoCs, but in terms of pin 211 * There are multiple variants of the Orion SoCs, but in terms of pin
212 * muxing, they are identical. 212 * muxing, they are identical.
213 */ 213 */
214static struct of_device_id orion_pinctrl_of_match[] = { 214static const struct of_device_id orion_pinctrl_of_match[] = {
215 { .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info }, 215 { .compatible = "marvell,88f5181l-pinctrl", .data = &mv88f5181l_info },
216 { .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info }, 216 { .compatible = "marvell,88f5182-pinctrl", .data = &mv88f5182_info },
217 { .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info }, 217 { .compatible = "marvell,88f5281-pinctrl", .data = &mv88f5281_info },
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 4db92f64b4de..e63ad9fbd388 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -283,23 +283,40 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
283 struct device *dev = pctldev->dev; 283 struct device *dev = pctldev->dev;
284 unsigned long *configs = NULL; 284 unsigned long *configs = NULL;
285 unsigned num_configs = 0; 285 unsigned num_configs = 0;
286 unsigned reserve; 286 unsigned reserve, strings_count;
287 struct property *prop; 287 struct property *prop;
288 const char *group; 288 const char *group;
289 const char *subnode_target_type = "pins"; 289 const char *subnode_target_type = "pins";
290 290
291 ret = of_property_count_strings(np, "pins");
292 if (ret < 0) {
293 ret = of_property_count_strings(np, "groups");
294 if (ret < 0)
295 /* skip this node; may contain config child nodes */
296 return 0;
297 if (type == PIN_MAP_TYPE_INVALID)
298 type = PIN_MAP_TYPE_CONFIGS_GROUP;
299 subnode_target_type = "groups";
300 } else {
301 if (type == PIN_MAP_TYPE_INVALID)
302 type = PIN_MAP_TYPE_CONFIGS_PIN;
303 }
304 strings_count = ret;
305
291 ret = of_property_read_string(np, "function", &function); 306 ret = of_property_read_string(np, "function", &function);
292 if (ret < 0) { 307 if (ret < 0) {
293 /* EINVAL=missing, which is fine since it's optional */ 308 /* EINVAL=missing, which is fine since it's optional */
294 if (ret != -EINVAL) 309 if (ret != -EINVAL)
295 dev_err(dev, "could not parse property function\n"); 310 dev_err(dev, "%s: could not parse property function\n",
311 of_node_full_name(np));
296 function = NULL; 312 function = NULL;
297 } 313 }
298 314
299 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs, 315 ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
300 &num_configs); 316 &num_configs);
301 if (ret < 0) { 317 if (ret < 0) {
302 dev_err(dev, "could not parse node property\n"); 318 dev_err(dev, "%s: could not parse node property\n",
319 of_node_full_name(np));
303 return ret; 320 return ret;
304 } 321 }
305 322
@@ -309,21 +326,7 @@ int pinconf_generic_dt_subnode_to_map(struct pinctrl_dev *pctldev,
309 if (num_configs) 326 if (num_configs)
310 reserve++; 327 reserve++;
311 328
312 ret = of_property_count_strings(np, "pins"); 329 reserve *= strings_count;
313 if (ret < 0) {
314 ret = of_property_count_strings(np, "groups");
315 if (ret < 0) {
316 dev_err(dev, "could not parse property pins/groups\n");
317 goto exit;
318 }
319 if (type == PIN_MAP_TYPE_INVALID)
320 type = PIN_MAP_TYPE_CONFIGS_GROUP;
321 subnode_target_type = "groups";
322 } else {
323 if (type == PIN_MAP_TYPE_INVALID)
324 type = PIN_MAP_TYPE_CONFIGS_PIN;
325 }
326 reserve *= ret;
327 330
328 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, 331 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
329 num_maps, reserve); 332 num_maps, reserve);
@@ -367,15 +370,22 @@ int pinconf_generic_dt_node_to_map(struct pinctrl_dev *pctldev,
367 *map = NULL; 370 *map = NULL;
368 *num_maps = 0; 371 *num_maps = 0;
369 372
373 ret = pinconf_generic_dt_subnode_to_map(pctldev, np_config, map,
374 &reserved_maps, num_maps, type);
375 if (ret < 0)
376 goto exit;
377
370 for_each_child_of_node(np_config, np) { 378 for_each_child_of_node(np_config, np) {
371 ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map, 379 ret = pinconf_generic_dt_subnode_to_map(pctldev, np, map,
372 &reserved_maps, num_maps, type); 380 &reserved_maps, num_maps, type);
373 if (ret < 0) { 381 if (ret < 0)
374 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps); 382 goto exit;
375 return ret;
376 }
377 } 383 }
378 return 0; 384 return 0;
385
386exit:
387 pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
388 return ret;
379} 389}
380EXPORT_SYMBOL_GPL(pinconf_generic_dt_node_to_map); 390EXPORT_SYMBOL_GPL(pinconf_generic_dt_node_to_map);
381 391
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
new file mode 100644
index 000000000000..7de3b64bf142
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -0,0 +1,869 @@
1/*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13#include <linux/err.h>
14#include <linux/bug.h>
15#include <linux/kernel.h>
16#include <linux/module.h>
17#include <linux/spinlock.h>
18#include <linux/compiler.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/log2.h>
22#include <linux/io.h>
23#include <linux/gpio.h>
24#include <linux/slab.h>
25#include <linux/platform_device.h>
26#include <linux/mutex.h>
27#include <linux/acpi.h>
28#include <linux/seq_file.h>
29#include <linux/interrupt.h>
30#include <linux/list.h>
31#include <linux/bitops.h>
32#include <linux/pinctrl/pinconf.h>
33#include <linux/pinctrl/pinconf-generic.h>
34
35#include "pinctrl-utils.h"
36#include "pinctrl-amd.h"
37
38static inline struct amd_gpio *to_amd_gpio(struct gpio_chip *gc)
39{
40 return container_of(gc, struct amd_gpio, gc);
41}
42
43static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
44{
45 unsigned long flags;
46 u32 pin_reg;
47 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
48
49 spin_lock_irqsave(&gpio_dev->lock, flags);
50 pin_reg = readl(gpio_dev->base + offset * 4);
51 /*
52 * Suppose BIOS or Bootloader sets specific debounce for the
53 * GPIO. if not, set debounce to be 2.75ms and remove glitch.
54 */
55 if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
56 pin_reg |= 0xf;
57 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
58 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
59 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
60 }
61
62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
63 writel(pin_reg, gpio_dev->base + offset * 4);
64 spin_unlock_irqrestore(&gpio_dev->lock, flags);
65
66 return 0;
67}
68
69static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
70 int value)
71{
72 u32 pin_reg;
73 unsigned long flags;
74 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
75
76 spin_lock_irqsave(&gpio_dev->lock, flags);
77 pin_reg = readl(gpio_dev->base + offset * 4);
78 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
79 if (value)
80 pin_reg |= BIT(OUTPUT_VALUE_OFF);
81 else
82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
83 writel(pin_reg, gpio_dev->base + offset * 4);
84 spin_unlock_irqrestore(&gpio_dev->lock, flags);
85
86 return 0;
87}
88
89static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
90{
91 u32 pin_reg;
92 unsigned long flags;
93 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
94
95 spin_lock_irqsave(&gpio_dev->lock, flags);
96 pin_reg = readl(gpio_dev->base + offset * 4);
97 spin_unlock_irqrestore(&gpio_dev->lock, flags);
98
99 return !!(pin_reg & BIT(PIN_STS_OFF));
100}
101
102static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
103{
104 u32 pin_reg;
105 unsigned long flags;
106 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
107
108 spin_lock_irqsave(&gpio_dev->lock, flags);
109 pin_reg = readl(gpio_dev->base + offset * 4);
110 if (value)
111 pin_reg |= BIT(OUTPUT_VALUE_OFF);
112 else
113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
114 writel(pin_reg, gpio_dev->base + offset * 4);
115 spin_unlock_irqrestore(&gpio_dev->lock, flags);
116}
117
118static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
119 unsigned debounce)
120{
121 u32 time;
122 u32 pin_reg;
123 int ret = 0;
124 unsigned long flags;
125 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
126
127 spin_lock_irqsave(&gpio_dev->lock, flags);
128 pin_reg = readl(gpio_dev->base + offset * 4);
129
130 if (debounce) {
131 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
132 pin_reg &= ~DB_TMR_OUT_MASK;
133 /*
134 Debounce Debounce Timer Max
135 TmrLarge TmrOutUnit Unit Debounce
136 Time
137 0 0 61 usec (2 RtcClk) 976 usec
138 0 1 244 usec (8 RtcClk) 3.9 msec
139 1 0 15.6 msec (512 RtcClk) 250 msec
140 1 1 62.5 msec (2048 RtcClk) 1 sec
141 */
142
143 if (debounce < 61) {
144 pin_reg |= 1;
145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
147 } else if (debounce < 976) {
148 time = debounce / 61;
149 pin_reg |= time & DB_TMR_OUT_MASK;
150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
152 } else if (debounce < 3900) {
153 time = debounce / 244;
154 pin_reg |= time & DB_TMR_OUT_MASK;
155 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
157 } else if (debounce < 250000) {
158 time = debounce / 15600;
159 pin_reg |= time & DB_TMR_OUT_MASK;
160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
161 pin_reg |= BIT(DB_TMR_LARGE_OFF);
162 } else if (debounce < 1000000) {
163 time = debounce / 62500;
164 pin_reg |= time & DB_TMR_OUT_MASK;
165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
166 pin_reg |= BIT(DB_TMR_LARGE_OFF);
167 } else {
168 pin_reg &= ~DB_CNTRl_MASK;
169 ret = -EINVAL;
170 }
171 } else {
172 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
173 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
174 pin_reg &= ~DB_TMR_OUT_MASK;
175 pin_reg &= ~DB_CNTRl_MASK;
176 }
177 writel(pin_reg, gpio_dev->base + offset * 4);
178 spin_unlock_irqrestore(&gpio_dev->lock, flags);
179
180 return ret;
181}
182
183#ifdef CONFIG_DEBUG_FS
184static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
185{
186 u32 pin_reg;
187 unsigned long flags;
188 unsigned int bank, i, pin_num;
189 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
190
191 char *level_trig;
192 char *active_level;
193 char *interrupt_enable;
194 char *interrupt_mask;
195 char *wake_cntrl0;
196 char *wake_cntrl1;
197 char *wake_cntrl2;
198 char *pin_sts;
199 char *pull_up_sel;
200 char *pull_up_enable;
201 char *pull_down_enable;
202 char *output_value;
203 char *output_enable;
204
205 for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) {
206 seq_printf(s, "GPIO bank%d\t", bank);
207
208 switch (bank) {
209 case 0:
210 i = 0;
211 pin_num = AMD_GPIO_PINS_BANK0;
212 break;
213 case 1:
214 i = 64;
215 pin_num = AMD_GPIO_PINS_BANK1 + i;
216 break;
217 case 2:
218 i = 128;
219 pin_num = AMD_GPIO_PINS_BANK2 + i;
220 break;
221 }
222
223 for (; i < pin_num; i++) {
224 seq_printf(s, "pin%d\t", i);
225 spin_lock_irqsave(&gpio_dev->lock, flags);
226 pin_reg = readl(gpio_dev->base + i * 4);
227 spin_unlock_irqrestore(&gpio_dev->lock, flags);
228
229 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
230 interrupt_enable = "interrupt is enabled|";
231
232 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
233 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
234 active_level = "Active low|";
235 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
236 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
237 active_level = "Active high|";
238 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
239 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
240 active_level = "Active on both|";
241 else
242 active_level = "Unknow Active level|";
243
244 if (pin_reg & BIT(LEVEL_TRIG_OFF))
245 level_trig = "Level trigger|";
246 else
247 level_trig = "Edge trigger|";
248
249 } else {
250 interrupt_enable =
251 "interrupt is disabled|";
252 active_level = " ";
253 level_trig = " ";
254 }
255
256 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
257 interrupt_mask =
258 "interrupt is unmasked|";
259 else
260 interrupt_mask =
261 "interrupt is masked|";
262
263 if (pin_reg & BIT(WAKE_CNTRL_OFF))
264 wake_cntrl0 = "enable wakeup in S0i3 state|";
265 else
266 wake_cntrl0 = "disable wakeup in S0i3 state|";
267
268 if (pin_reg & BIT(WAKE_CNTRL_OFF))
269 wake_cntrl1 = "enable wakeup in S3 state|";
270 else
271 wake_cntrl1 = "disable wakeup in S3 state|";
272
273 if (pin_reg & BIT(WAKE_CNTRL_OFF))
274 wake_cntrl2 = "enable wakeup in S4/S5 state|";
275 else
276 wake_cntrl2 = "disable wakeup in S4/S5 state|";
277
278 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
279 pull_up_enable = "pull-up is enabled|";
280 if (pin_reg & BIT(PULL_UP_SEL_OFF))
281 pull_up_sel = "8k pull-up|";
282 else
283 pull_up_sel = "4k pull-up|";
284 } else {
285 pull_up_enable = "pull-up is disabled|";
286 pull_up_sel = " ";
287 }
288
289 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
290 pull_down_enable = "pull-down is enabled|";
291 else
292 pull_down_enable = "Pull-down is disabled|";
293
294 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
295 pin_sts = " ";
296 output_enable = "output is enabled|";
297 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
298 output_value = "output is high|";
299 else
300 output_value = "output is low|";
301 } else {
302 output_enable = "output is disabled|";
303 output_value = " ";
304
305 if (pin_reg & BIT(PIN_STS_OFF))
306 pin_sts = "input is high|";
307 else
308 pin_sts = "input is low|";
309 }
310
311 seq_printf(s, "%s %s %s %s %s %s\n"
312 " %s %s %s %s %s %s %s 0x%x\n",
313 level_trig, active_level, interrupt_enable,
314 interrupt_mask, wake_cntrl0, wake_cntrl1,
315 wake_cntrl2, pin_sts, pull_up_sel,
316 pull_up_enable, pull_down_enable,
317 output_value, output_enable, pin_reg);
318 }
319 }
320}
321#else
322#define amd_gpio_dbg_show NULL
323#endif
324
325static void amd_gpio_irq_enable(struct irq_data *d)
326{
327 u32 pin_reg;
328 unsigned long flags;
329 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
330 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
331
332 spin_lock_irqsave(&gpio_dev->lock, flags);
333 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
334 /*
335 Suppose BIOS or Bootloader sets specific debounce for the
336 GPIO. if not, set debounce to be 2.75ms.
337 */
338 if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
339 pin_reg |= 0xf;
340 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
341 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
342 }
343 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
344 pin_reg |= BIT(INTERRUPT_MASK_OFF);
345 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
346 spin_unlock_irqrestore(&gpio_dev->lock, flags);
347}
348
349static void amd_gpio_irq_disable(struct irq_data *d)
350{
351 u32 pin_reg;
352 unsigned long flags;
353 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
354 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
355
356 spin_lock_irqsave(&gpio_dev->lock, flags);
357 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
358 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
359 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
360 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
361 spin_unlock_irqrestore(&gpio_dev->lock, flags);
362}
363
364static void amd_gpio_irq_mask(struct irq_data *d)
365{
366 u32 pin_reg;
367 unsigned long flags;
368 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
369 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
370
371 spin_lock_irqsave(&gpio_dev->lock, flags);
372 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
373 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
374 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
375 spin_unlock_irqrestore(&gpio_dev->lock, flags);
376}
377
378static void amd_gpio_irq_unmask(struct irq_data *d)
379{
380 u32 pin_reg;
381 unsigned long flags;
382 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
383 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
384
385 spin_lock_irqsave(&gpio_dev->lock, flags);
386 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
387 pin_reg |= BIT(INTERRUPT_MASK_OFF);
388 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
389 spin_unlock_irqrestore(&gpio_dev->lock, flags);
390}
391
392static void amd_gpio_irq_eoi(struct irq_data *d)
393{
394 u32 reg;
395 unsigned long flags;
396 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
397 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
398
399 spin_lock_irqsave(&gpio_dev->lock, flags);
400 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
401 reg |= EOI_MASK;
402 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
403 spin_unlock_irqrestore(&gpio_dev->lock, flags);
404}
405
406static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
407{
408 int ret = 0;
409 u32 pin_reg;
410 unsigned long flags;
411 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
412 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
413
414 spin_lock_irqsave(&gpio_dev->lock, flags);
415 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
416
417 switch (type & IRQ_TYPE_SENSE_MASK) {
418 case IRQ_TYPE_EDGE_RISING:
419 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
420 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
421 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
422 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
423 __irq_set_handler_locked(d->irq, handle_edge_irq);
424 break;
425
426 case IRQ_TYPE_EDGE_FALLING:
427 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
428 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
429 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
430 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
431 __irq_set_handler_locked(d->irq, handle_edge_irq);
432 break;
433
434 case IRQ_TYPE_EDGE_BOTH:
435 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
436 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
437 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
438 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
439 __irq_set_handler_locked(d->irq, handle_edge_irq);
440 break;
441
442 case IRQ_TYPE_LEVEL_HIGH:
443 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
444 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
445 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
446 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
447 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
448 __irq_set_handler_locked(d->irq, handle_level_irq);
449 break;
450
451 case IRQ_TYPE_LEVEL_LOW:
452 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
453 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
454 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
455 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
456 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
457 __irq_set_handler_locked(d->irq, handle_level_irq);
458 break;
459
460 case IRQ_TYPE_NONE:
461 break;
462
463 default:
464 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
465 ret = -EINVAL;
466 }
467
468 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
469 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
470 spin_unlock_irqrestore(&gpio_dev->lock, flags);
471
472 return ret;
473}
474
475static void amd_irq_ack(struct irq_data *d)
476{
477 /*
478 * based on HW design,there is no need to ack HW
479 * before handle current irq. But this routine is
480 * necessary for handle_edge_irq
481 */
482}
483
484static struct irq_chip amd_gpio_irqchip = {
485 .name = "amd_gpio",
486 .irq_ack = amd_irq_ack,
487 .irq_enable = amd_gpio_irq_enable,
488 .irq_disable = amd_gpio_irq_disable,
489 .irq_mask = amd_gpio_irq_mask,
490 .irq_unmask = amd_gpio_irq_unmask,
491 .irq_eoi = amd_gpio_irq_eoi,
492 .irq_set_type = amd_gpio_irq_set_type,
493};
494
495static void amd_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
496{
497 u32 i;
498 u32 off;
499 u32 reg;
500 u32 pin_reg;
501 u64 reg64;
502 int handled = 0;
503 unsigned long flags;
504 struct irq_chip *chip = irq_get_chip(irq);
505 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
506 struct amd_gpio *gpio_dev = to_amd_gpio(gc);
507
508 chained_irq_enter(chip, desc);
509 /*enable GPIO interrupt again*/
510 spin_lock_irqsave(&gpio_dev->lock, flags);
511 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
512 reg64 = reg;
513 reg64 = reg64 << 32;
514
515 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
516 reg64 |= reg;
517 spin_unlock_irqrestore(&gpio_dev->lock, flags);
518
519 /*
520 * first 46 bits indicates interrupt status.
521 * one bit represents four interrupt sources.
522 */
523 for (off = 0; off < 46 ; off++) {
524 if (reg64 & BIT(off)) {
525 for (i = 0; i < 4; i++) {
526 pin_reg = readl(gpio_dev->base +
527 (off * 4 + i) * 4);
528 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
529 (pin_reg & BIT(WAKE_STS_OFF))) {
530 irq = irq_find_mapping(gc->irqdomain,
531 off * 4 + i);
532 generic_handle_irq(irq);
533 writel(pin_reg,
534 gpio_dev->base
535 + (off * 4 + i) * 4);
536 handled++;
537 }
538 }
539 }
540 }
541
542 if (handled == 0)
543 handle_bad_irq(irq, desc);
544
545 spin_lock_irqsave(&gpio_dev->lock, flags);
546 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
547 reg |= EOI_MASK;
548 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
549 spin_unlock_irqrestore(&gpio_dev->lock, flags);
550
551 chained_irq_exit(chip, desc);
552}
553
554static int amd_get_groups_count(struct pinctrl_dev *pctldev)
555{
556 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
557
558 return gpio_dev->ngroups;
559}
560
561static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
562 unsigned group)
563{
564 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
565
566 return gpio_dev->groups[group].name;
567}
568
569static int amd_get_group_pins(struct pinctrl_dev *pctldev,
570 unsigned group,
571 const unsigned **pins,
572 unsigned *num_pins)
573{
574 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
575
576 *pins = gpio_dev->groups[group].pins;
577 *num_pins = gpio_dev->groups[group].npins;
578 return 0;
579}
580
581static const struct pinctrl_ops amd_pinctrl_ops = {
582 .get_groups_count = amd_get_groups_count,
583 .get_group_name = amd_get_group_name,
584 .get_group_pins = amd_get_group_pins,
585#ifdef CONFIG_OF
586 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
587 .dt_free_map = pinctrl_utils_dt_free_map,
588#endif
589};
590
591static int amd_pinconf_get(struct pinctrl_dev *pctldev,
592 unsigned int pin,
593 unsigned long *config)
594{
595 u32 pin_reg;
596 unsigned arg;
597 unsigned long flags;
598 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
599 enum pin_config_param param = pinconf_to_config_param(*config);
600
601 spin_lock_irqsave(&gpio_dev->lock, flags);
602 pin_reg = readl(gpio_dev->base + pin*4);
603 spin_unlock_irqrestore(&gpio_dev->lock, flags);
604 switch (param) {
605 case PIN_CONFIG_INPUT_DEBOUNCE:
606 arg = pin_reg & DB_TMR_OUT_MASK;
607 break;
608
609 case PIN_CONFIG_BIAS_PULL_DOWN:
610 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
611 break;
612
613 case PIN_CONFIG_BIAS_PULL_UP:
614 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
615 break;
616
617 case PIN_CONFIG_DRIVE_STRENGTH:
618 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
619 break;
620
621 default:
622 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
623 param);
624 return -ENOTSUPP;
625 }
626
627 *config = pinconf_to_config_packed(param, arg);
628
629 return 0;
630}
631
632static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
633 unsigned long *configs, unsigned num_configs)
634{
635 int i;
636 u32 arg;
637 int ret = 0;
638 u32 pin_reg;
639 unsigned long flags;
640 enum pin_config_param param;
641 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
642
643 spin_lock_irqsave(&gpio_dev->lock, flags);
644 for (i = 0; i < num_configs; i++) {
645 param = pinconf_to_config_param(configs[i]);
646 arg = pinconf_to_config_argument(configs[i]);
647 pin_reg = readl(gpio_dev->base + pin*4);
648
649 switch (param) {
650 case PIN_CONFIG_INPUT_DEBOUNCE:
651 pin_reg &= ~DB_TMR_OUT_MASK;
652 pin_reg |= arg & DB_TMR_OUT_MASK;
653 break;
654
655 case PIN_CONFIG_BIAS_PULL_DOWN:
656 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
657 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
658 break;
659
660 case PIN_CONFIG_BIAS_PULL_UP:
661 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
662 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
663 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
664 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
665 break;
666
667 case PIN_CONFIG_DRIVE_STRENGTH:
668 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
669 << DRV_STRENGTH_SEL_OFF);
670 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
671 << DRV_STRENGTH_SEL_OFF;
672 break;
673
674 default:
675 dev_err(&gpio_dev->pdev->dev,
676 "Invalid config param %04x\n", param);
677 ret = -ENOTSUPP;
678 }
679
680 writel(pin_reg, gpio_dev->base + pin*4);
681 }
682 spin_unlock_irqrestore(&gpio_dev->lock, flags);
683
684 return ret;
685}
686
687static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
688 unsigned int group,
689 unsigned long *config)
690{
691 const unsigned *pins;
692 unsigned npins;
693 int ret;
694
695 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
696 if (ret)
697 return ret;
698
699 if (amd_pinconf_get(pctldev, pins[0], config))
700 return -ENOTSUPP;
701
702 return 0;
703}
704
705static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
706 unsigned group, unsigned long *configs,
707 unsigned num_configs)
708{
709 const unsigned *pins;
710 unsigned npins;
711 int i, ret;
712
713 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
714 if (ret)
715 return ret;
716 for (i = 0; i < npins; i++) {
717 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
718 return -ENOTSUPP;
719 }
720 return 0;
721}
722
723static const struct pinconf_ops amd_pinconf_ops = {
724 .pin_config_get = amd_pinconf_get,
725 .pin_config_set = amd_pinconf_set,
726 .pin_config_group_get = amd_pinconf_group_get,
727 .pin_config_group_set = amd_pinconf_group_set,
728};
729
730static struct pinctrl_desc amd_pinctrl_desc = {
731 .pins = kerncz_pins,
732 .npins = ARRAY_SIZE(kerncz_pins),
733 .pctlops = &amd_pinctrl_ops,
734 .confops = &amd_pinconf_ops,
735 .owner = THIS_MODULE,
736};
737
738static int amd_gpio_probe(struct platform_device *pdev)
739{
740 int ret = 0;
741 int irq_base;
742 struct resource *res;
743 struct amd_gpio *gpio_dev;
744
745 gpio_dev = devm_kzalloc(&pdev->dev,
746 sizeof(struct amd_gpio), GFP_KERNEL);
747 if (!gpio_dev)
748 return -ENOMEM;
749
750 spin_lock_init(&gpio_dev->lock);
751
752 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
753 if (!res) {
754 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
755 return -EINVAL;
756 }
757
758 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
759 resource_size(res));
760 if (IS_ERR(gpio_dev->base))
761 return PTR_ERR(gpio_dev->base);
762
763 irq_base = platform_get_irq(pdev, 0);
764 if (irq_base < 0) {
765 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
766 return -EINVAL;
767 }
768
769 gpio_dev->pdev = pdev;
770 gpio_dev->gc.direction_input = amd_gpio_direction_input;
771 gpio_dev->gc.direction_output = amd_gpio_direction_output;
772 gpio_dev->gc.get = amd_gpio_get_value;
773 gpio_dev->gc.set = amd_gpio_set_value;
774 gpio_dev->gc.set_debounce = amd_gpio_set_debounce;
775 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
776
777 gpio_dev->gc.base = 0;
778 gpio_dev->gc.label = pdev->name;
779 gpio_dev->gc.owner = THIS_MODULE;
780 gpio_dev->gc.dev = &pdev->dev;
781 gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS;
782#if defined(CONFIG_OF_GPIO)
783 gpio_dev->gc.of_node = pdev->dev.of_node;
784#endif
785
786 gpio_dev->groups = kerncz_groups;
787 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
788
789 amd_pinctrl_desc.name = dev_name(&pdev->dev);
790 gpio_dev->pctrl = pinctrl_register(&amd_pinctrl_desc,
791 &pdev->dev, gpio_dev);
792 if (!gpio_dev->pctrl) {
793 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
794 return -ENODEV;
795 }
796
797 ret = gpiochip_add(&gpio_dev->gc);
798 if (ret)
799 goto out1;
800
801 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
802 0, 0, TOTAL_NUMBER_OF_PINS);
803 if (ret) {
804 dev_err(&pdev->dev, "Failed to add pin range\n");
805 goto out2;
806 }
807
808 ret = gpiochip_irqchip_add(&gpio_dev->gc,
809 &amd_gpio_irqchip,
810 0,
811 handle_simple_irq,
812 IRQ_TYPE_NONE);
813 if (ret) {
814 dev_err(&pdev->dev, "could not add irqchip\n");
815 ret = -ENODEV;
816 goto out2;
817 }
818
819 gpiochip_set_chained_irqchip(&gpio_dev->gc,
820 &amd_gpio_irqchip,
821 irq_base,
822 amd_gpio_irq_handler);
823
824 platform_set_drvdata(pdev, gpio_dev);
825
826 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
827 return ret;
828
829out2:
830 gpiochip_remove(&gpio_dev->gc);
831
832out1:
833 pinctrl_unregister(gpio_dev->pctrl);
834 return ret;
835}
836
837static int amd_gpio_remove(struct platform_device *pdev)
838{
839 struct amd_gpio *gpio_dev;
840
841 gpio_dev = platform_get_drvdata(pdev);
842
843 gpiochip_remove(&gpio_dev->gc);
844 pinctrl_unregister(gpio_dev->pctrl);
845
846 return 0;
847}
848
849static const struct acpi_device_id amd_gpio_acpi_match[] = {
850 { "AMD0030", 0 },
851 { },
852};
853MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
854
855static struct platform_driver amd_gpio_driver = {
856 .driver = {
857 .name = "amd_gpio",
858 .owner = THIS_MODULE,
859 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
860 },
861 .probe = amd_gpio_probe,
862 .remove = amd_gpio_remove,
863};
864
865module_platform_driver(amd_gpio_driver);
866
867MODULE_LICENSE("GPL v2");
868MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
869MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h
new file mode 100644
index 000000000000..7bfea47dbb47
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-amd.h
@@ -0,0 +1,261 @@
1/*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 Ken Xue <Ken.Xue@amd.com>
5 * Jeff Wu <Jeff.Wu@amd.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 */
12
13#ifndef _PINCTRL_AMD_H
14#define _PINCTRL_AMD_H
15
16#define TOTAL_NUMBER_OF_PINS 192
17#define AMD_GPIO_PINS_PER_BANK 64
18#define AMD_GPIO_TOTAL_BANKS 3
19
20#define AMD_GPIO_PINS_BANK0 63
21#define AMD_GPIO_PINS_BANK1 64
22#define AMD_GPIO_PINS_BANK2 56
23
24#define WAKE_INT_MASTER_REG 0xfc
25#define EOI_MASK (1 << 29)
26
27#define WAKE_INT_STATUS_REG0 0x2f8
28#define WAKE_INT_STATUS_REG1 0x2fc
29
30#define DB_TMR_OUT_OFF 0
31#define DB_TMR_OUT_UNIT_OFF 4
32#define DB_CNTRL_OFF 5
33#define DB_TMR_LARGE_OFF 7
34#define LEVEL_TRIG_OFF 8
35#define ACTIVE_LEVEL_OFF 9
36#define INTERRUPT_ENABLE_OFF 11
37#define INTERRUPT_MASK_OFF 12
38#define WAKE_CNTRL_OFF 13
39#define PIN_STS_OFF 16
40#define DRV_STRENGTH_SEL_OFF 17
41#define PULL_UP_SEL_OFF 19
42#define PULL_UP_ENABLE_OFF 20
43#define PULL_DOWN_ENABLE_OFF 21
44#define OUTPUT_VALUE_OFF 22
45#define OUTPUT_ENABLE_OFF 23
46#define SW_CNTRL_IN_OFF 24
47#define SW_CNTRL_EN_OFF 25
48#define INTERRUPT_STS_OFF 28
49#define WAKE_STS_OFF 29
50
51#define DB_TMR_OUT_MASK 0xFUL
52#define DB_CNTRl_MASK 0x3UL
53#define ACTIVE_LEVEL_MASK 0x3UL
54#define DRV_STRENGTH_SEL_MASK 0x3UL
55
56#define DB_TYPE_NO_DEBOUNCE 0x0UL
57#define DB_TYPE_PRESERVE_LOW_GLITCH 0x1UL
58#define DB_TYPE_PRESERVE_HIGH_GLITCH 0x2UL
59#define DB_TYPE_REMOVE_GLITCH 0x3UL
60
61#define EDGE_TRAGGER 0x0UL
62#define LEVEL_TRIGGER 0x1UL
63
64#define ACTIVE_HIGH 0x0UL
65#define ACTIVE_LOW 0x1UL
66#define BOTH_EADGE 0x2UL
67
68#define ENABLE_INTERRUPT 0x1UL
69#define DISABLE_INTERRUPT 0x0UL
70
71#define ENABLE_INTERRUPT_MASK 0x0UL
72#define DISABLE_INTERRUPT_MASK 0x1UL
73
74#define CLR_INTR_STAT 0x1UL
75
76struct amd_pingroup {
77 const char *name;
78 const unsigned *pins;
79 unsigned npins;
80};
81
82struct amd_function {
83 const char *name;
84 const char * const *groups;
85 unsigned ngroups;
86};
87
88struct amd_gpio {
89 spinlock_t lock;
90 void __iomem *base;
91
92 const struct amd_pingroup *groups;
93 u32 ngroups;
94 struct pinctrl_dev *pctrl;
95 struct gpio_chip gc;
96 struct resource *res;
97 struct platform_device *pdev;
98};
99
100/* KERNCZ configuration*/
101static const struct pinctrl_pin_desc kerncz_pins[] = {
102 PINCTRL_PIN(0, "GPIO_0"),
103 PINCTRL_PIN(1, "GPIO_1"),
104 PINCTRL_PIN(2, "GPIO_2"),
105 PINCTRL_PIN(3, "GPIO_3"),
106 PINCTRL_PIN(4, "GPIO_4"),
107 PINCTRL_PIN(5, "GPIO_5"),
108 PINCTRL_PIN(6, "GPIO_6"),
109 PINCTRL_PIN(7, "GPIO_7"),
110 PINCTRL_PIN(8, "GPIO_8"),
111 PINCTRL_PIN(9, "GPIO_9"),
112 PINCTRL_PIN(10, "GPIO_10"),
113 PINCTRL_PIN(11, "GPIO_11"),
114 PINCTRL_PIN(12, "GPIO_12"),
115 PINCTRL_PIN(13, "GPIO_13"),
116 PINCTRL_PIN(14, "GPIO_14"),
117 PINCTRL_PIN(15, "GPIO_15"),
118 PINCTRL_PIN(16, "GPIO_16"),
119 PINCTRL_PIN(17, "GPIO_17"),
120 PINCTRL_PIN(18, "GPIO_18"),
121 PINCTRL_PIN(19, "GPIO_19"),
122 PINCTRL_PIN(20, "GPIO_20"),
123 PINCTRL_PIN(23, "GPIO_23"),
124 PINCTRL_PIN(24, "GPIO_24"),
125 PINCTRL_PIN(25, "GPIO_25"),
126 PINCTRL_PIN(26, "GPIO_26"),
127 PINCTRL_PIN(39, "GPIO_39"),
128 PINCTRL_PIN(40, "GPIO_40"),
129 PINCTRL_PIN(43, "GPIO_42"),
130 PINCTRL_PIN(46, "GPIO_46"),
131 PINCTRL_PIN(47, "GPIO_47"),
132 PINCTRL_PIN(48, "GPIO_48"),
133 PINCTRL_PIN(49, "GPIO_49"),
134 PINCTRL_PIN(50, "GPIO_50"),
135 PINCTRL_PIN(51, "GPIO_51"),
136 PINCTRL_PIN(52, "GPIO_52"),
137 PINCTRL_PIN(53, "GPIO_53"),
138 PINCTRL_PIN(54, "GPIO_54"),
139 PINCTRL_PIN(55, "GPIO_55"),
140 PINCTRL_PIN(56, "GPIO_56"),
141 PINCTRL_PIN(57, "GPIO_57"),
142 PINCTRL_PIN(58, "GPIO_58"),
143 PINCTRL_PIN(59, "GPIO_59"),
144 PINCTRL_PIN(60, "GPIO_60"),
145 PINCTRL_PIN(61, "GPIO_61"),
146 PINCTRL_PIN(62, "GPIO_62"),
147 PINCTRL_PIN(64, "GPIO_64"),
148 PINCTRL_PIN(65, "GPIO_65"),
149 PINCTRL_PIN(66, "GPIO_66"),
150 PINCTRL_PIN(68, "GPIO_68"),
151 PINCTRL_PIN(69, "GPIO_69"),
152 PINCTRL_PIN(70, "GPIO_70"),
153 PINCTRL_PIN(71, "GPIO_71"),
154 PINCTRL_PIN(72, "GPIO_72"),
155 PINCTRL_PIN(74, "GPIO_74"),
156 PINCTRL_PIN(75, "GPIO_75"),
157 PINCTRL_PIN(76, "GPIO_76"),
158 PINCTRL_PIN(84, "GPIO_84"),
159 PINCTRL_PIN(85, "GPIO_85"),
160 PINCTRL_PIN(86, "GPIO_86"),
161 PINCTRL_PIN(87, "GPIO_87"),
162 PINCTRL_PIN(88, "GPIO_88"),
163 PINCTRL_PIN(89, "GPIO_89"),
164 PINCTRL_PIN(90, "GPIO_90"),
165 PINCTRL_PIN(91, "GPIO_91"),
166 PINCTRL_PIN(92, "GPIO_92"),
167 PINCTRL_PIN(93, "GPIO_93"),
168 PINCTRL_PIN(95, "GPIO_95"),
169 PINCTRL_PIN(96, "GPIO_96"),
170 PINCTRL_PIN(97, "GPIO_97"),
171 PINCTRL_PIN(98, "GPIO_98"),
172 PINCTRL_PIN(99, "GPIO_99"),
173 PINCTRL_PIN(100, "GPIO_100"),
174 PINCTRL_PIN(101, "GPIO_101"),
175 PINCTRL_PIN(102, "GPIO_102"),
176 PINCTRL_PIN(113, "GPIO_113"),
177 PINCTRL_PIN(114, "GPIO_114"),
178 PINCTRL_PIN(115, "GPIO_115"),
179 PINCTRL_PIN(116, "GPIO_116"),
180 PINCTRL_PIN(117, "GPIO_117"),
181 PINCTRL_PIN(118, "GPIO_118"),
182 PINCTRL_PIN(119, "GPIO_119"),
183 PINCTRL_PIN(120, "GPIO_120"),
184 PINCTRL_PIN(121, "GPIO_121"),
185 PINCTRL_PIN(122, "GPIO_122"),
186 PINCTRL_PIN(126, "GPIO_126"),
187 PINCTRL_PIN(129, "GPIO_129"),
188 PINCTRL_PIN(130, "GPIO_130"),
189 PINCTRL_PIN(131, "GPIO_131"),
190 PINCTRL_PIN(132, "GPIO_132"),
191 PINCTRL_PIN(133, "GPIO_133"),
192 PINCTRL_PIN(135, "GPIO_135"),
193 PINCTRL_PIN(136, "GPIO_136"),
194 PINCTRL_PIN(137, "GPIO_137"),
195 PINCTRL_PIN(138, "GPIO_138"),
196 PINCTRL_PIN(139, "GPIO_139"),
197 PINCTRL_PIN(140, "GPIO_140"),
198 PINCTRL_PIN(141, "GPIO_141"),
199 PINCTRL_PIN(142, "GPIO_142"),
200 PINCTRL_PIN(143, "GPIO_143"),
201 PINCTRL_PIN(144, "GPIO_144"),
202 PINCTRL_PIN(145, "GPIO_145"),
203 PINCTRL_PIN(146, "GPIO_146"),
204 PINCTRL_PIN(147, "GPIO_147"),
205 PINCTRL_PIN(148, "GPIO_148"),
206 PINCTRL_PIN(166, "GPIO_166"),
207 PINCTRL_PIN(167, "GPIO_167"),
208 PINCTRL_PIN(168, "GPIO_168"),
209 PINCTRL_PIN(169, "GPIO_169"),
210 PINCTRL_PIN(170, "GPIO_170"),
211 PINCTRL_PIN(171, "GPIO_171"),
212 PINCTRL_PIN(172, "GPIO_172"),
213 PINCTRL_PIN(173, "GPIO_173"),
214 PINCTRL_PIN(174, "GPIO_174"),
215 PINCTRL_PIN(175, "GPIO_175"),
216 PINCTRL_PIN(176, "GPIO_176"),
217 PINCTRL_PIN(177, "GPIO_177"),
218};
219
220static const unsigned i2c0_pins[] = {145, 146};
221static const unsigned i2c1_pins[] = {147, 148};
222static const unsigned i2c2_pins[] = {113, 114};
223static const unsigned i2c3_pins[] = {19, 20};
224
225static const unsigned uart0_pins[] = {135, 136, 137, 138, 139};
226static const unsigned uart1_pins[] = {140, 141, 142, 143, 144};
227
228static const struct amd_pingroup kerncz_groups[] = {
229 {
230 .name = "i2c0",
231 .pins = i2c0_pins,
232 .npins = 2,
233 },
234 {
235 .name = "i2c1",
236 .pins = i2c1_pins,
237 .npins = 2,
238 },
239 {
240 .name = "i2c2",
241 .pins = i2c2_pins,
242 .npins = 2,
243 },
244 {
245 .name = "i2c3",
246 .pins = i2c3_pins,
247 .npins = 2,
248 },
249 {
250 .name = "uart0",
251 .pins = uart0_pins,
252 .npins = 9,
253 },
254 {
255 .name = "uart1",
256 .pins = uart1_pins,
257 .npins = 5,
258 },
259};
260
261#endif
diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c
index 169b1bfa00c8..db0571ffbe99 100644
--- a/drivers/pinctrl/pinctrl-as3722.c
+++ b/drivers/pinctrl/pinctrl-as3722.c
@@ -625,7 +625,7 @@ static int as3722_pinctrl_remove(struct platform_device *pdev)
625 return 0; 625 return 0;
626} 626}
627 627
628static struct of_device_id as3722_pinctrl_of_match[] = { 628static const struct of_device_id as3722_pinctrl_of_match[] = {
629 { .compatible = "ams,as3722-pinctrl", }, 629 { .compatible = "ams,as3722-pinctrl", },
630 { }, 630 { },
631}; 631};
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index a4814066ea08..2f797cb7e205 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -451,18 +451,18 @@ static enum at91_mux at91_mux_get_periph(void __iomem *pio, unsigned mask)
451 451
452static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin) 452static bool at91_mux_get_deglitch(void __iomem *pio, unsigned pin)
453{ 453{
454 return (__raw_readl(pio + PIO_IFSR) >> pin) & 0x1; 454 return (readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1;
455} 455}
456 456
457static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 457static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
458{ 458{
459 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 459 writel_relaxed(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
460} 460}
461 461
462static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin) 462static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
463{ 463{
464 if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) 464 if ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1)
465 return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); 465 return !((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
466 466
467 return false; 467 return false;
468} 468}
@@ -470,55 +470,55 @@ static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
470static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 470static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
471{ 471{
472 if (is_on) 472 if (is_on)
473 __raw_writel(mask, pio + PIO_IFSCDR); 473 writel_relaxed(mask, pio + PIO_IFSCDR);
474 at91_mux_set_deglitch(pio, mask, is_on); 474 at91_mux_set_deglitch(pio, mask, is_on);
475} 475}
476 476
477static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div) 477static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div)
478{ 478{
479 *div = __raw_readl(pio + PIO_SCDR); 479 *div = readl_relaxed(pio + PIO_SCDR);
480 480
481 return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) && 481 return ((readl_relaxed(pio + PIO_IFSR) >> pin) & 0x1) &&
482 ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1); 482 ((readl_relaxed(pio + PIO_IFSCSR) >> pin) & 0x1);
483} 483}
484 484
485static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, 485static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
486 bool is_on, u32 div) 486 bool is_on, u32 div)
487{ 487{
488 if (is_on) { 488 if (is_on) {
489 __raw_writel(mask, pio + PIO_IFSCER); 489 writel_relaxed(mask, pio + PIO_IFSCER);
490 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); 490 writel_relaxed(div & PIO_SCDR_DIV, pio + PIO_SCDR);
491 __raw_writel(mask, pio + PIO_IFER); 491 writel_relaxed(mask, pio + PIO_IFER);
492 } else 492 } else
493 __raw_writel(mask, pio + PIO_IFSCDR); 493 writel_relaxed(mask, pio + PIO_IFSCDR);
494} 494}
495 495
496static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) 496static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
497{ 497{
498 return !((__raw_readl(pio + PIO_PPDSR) >> pin) & 0x1); 498 return !((readl_relaxed(pio + PIO_PPDSR) >> pin) & 0x1);
499} 499}
500 500
501static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on) 501static void at91_mux_pio3_set_pulldown(void __iomem *pio, unsigned mask, bool is_on)
502{ 502{
503 if (is_on) 503 if (is_on)
504 __raw_writel(mask, pio + PIO_PUDR); 504 writel_relaxed(mask, pio + PIO_PUDR);
505 505
506 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 506 writel_relaxed(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
507} 507}
508 508
509static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask) 509static void at91_mux_pio3_disable_schmitt_trig(void __iomem *pio, unsigned mask)
510{ 510{
511 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); 511 writel_relaxed(readl_relaxed(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
512} 512}
513 513
514static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin) 514static bool at91_mux_pio3_get_schmitt_trig(void __iomem *pio, unsigned pin)
515{ 515{
516 return (__raw_readl(pio + PIO_SCHMITT) >> pin) & 0x1; 516 return (readl_relaxed(pio + PIO_SCHMITT) >> pin) & 0x1;
517} 517}
518 518
519static inline u32 read_drive_strength(void __iomem *reg, unsigned pin) 519static inline u32 read_drive_strength(void __iomem *reg, unsigned pin)
520{ 520{
521 unsigned tmp = __raw_readl(reg); 521 unsigned tmp = readl_relaxed(reg);
522 522
523 tmp = tmp >> two_bit_pin_value_shift_amount(pin); 523 tmp = tmp >> two_bit_pin_value_shift_amount(pin);
524 524
@@ -554,13 +554,13 @@ static unsigned at91_mux_sam9x5_get_drivestrength(void __iomem *pio,
554 554
555static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength) 555static void set_drive_strength(void __iomem *reg, unsigned pin, u32 strength)
556{ 556{
557 unsigned tmp = __raw_readl(reg); 557 unsigned tmp = readl_relaxed(reg);
558 unsigned shift = two_bit_pin_value_shift_amount(pin); 558 unsigned shift = two_bit_pin_value_shift_amount(pin);
559 559
560 tmp &= ~(DRIVE_STRENGTH_MASK << shift); 560 tmp &= ~(DRIVE_STRENGTH_MASK << shift);
561 tmp |= strength << shift; 561 tmp |= strength << shift;
562 562
563 __raw_writel(tmp, reg); 563 writel_relaxed(tmp, reg);
564} 564}
565 565
566static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin, 566static void at91_mux_sama5d3_set_drivestrength(void __iomem *pio, unsigned pin,
@@ -1114,7 +1114,7 @@ static int at91_pinctrl_parse_functions(struct device_node *np,
1114 return 0; 1114 return 0;
1115} 1115}
1116 1116
1117static struct of_device_id at91_pinctrl_of_match[] = { 1117static const struct of_device_id at91_pinctrl_of_match[] = {
1118 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops }, 1118 { .compatible = "atmel,sama5d3-pinctrl", .data = &sama5d3_ops },
1119 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops }, 1119 { .compatible = "atmel,at91sam9x5-pinctrl", .data = &at91sam9x5_ops },
1120 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops }, 1120 { .compatible = "atmel,at91rm9200-pinctrl", .data = &at91rm9200_ops },
@@ -1240,8 +1240,7 @@ static int at91_pinctrl_probe(struct platform_device *pdev)
1240 1240
1241 if (!info->pctl) { 1241 if (!info->pctl) {
1242 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n"); 1242 dev_err(&pdev->dev, "could not register AT91 pinctrl driver\n");
1243 ret = -EINVAL; 1243 return -EINVAL;
1244 goto err;
1245 } 1244 }
1246 1245
1247 /* We will handle a range of GPIO pins */ 1246 /* We will handle a range of GPIO pins */
@@ -1252,9 +1251,6 @@ static int at91_pinctrl_probe(struct platform_device *pdev)
1252 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n"); 1251 dev_info(&pdev->dev, "initialized AT91 pinctrl driver\n");
1253 1252
1254 return 0; 1253 return 0;
1255
1256err:
1257 return ret;
1258} 1254}
1259 1255
1260static int at91_pinctrl_remove(struct platform_device *pdev) 1256static int at91_pinctrl_remove(struct platform_device *pdev)
@@ -1535,9 +1531,9 @@ void at91_pinctrl_gpio_suspend(void)
1535 1531
1536 pio = gpio_chips[i]->regbase; 1532 pio = gpio_chips[i]->regbase;
1537 1533
1538 backups[i] = __raw_readl(pio + PIO_IMR); 1534 backups[i] = readl_relaxed(pio + PIO_IMR);
1539 __raw_writel(backups[i], pio + PIO_IDR); 1535 writel_relaxed(backups[i], pio + PIO_IDR);
1540 __raw_writel(wakeups[i], pio + PIO_IER); 1536 writel_relaxed(wakeups[i], pio + PIO_IER);
1541 1537
1542 if (!wakeups[i]) 1538 if (!wakeups[i])
1543 clk_disable_unprepare(gpio_chips[i]->clock); 1539 clk_disable_unprepare(gpio_chips[i]->clock);
@@ -1562,8 +1558,8 @@ void at91_pinctrl_gpio_resume(void)
1562 if (!wakeups[i]) 1558 if (!wakeups[i])
1563 clk_prepare_enable(gpio_chips[i]->clock); 1559 clk_prepare_enable(gpio_chips[i]->clock);
1564 1560
1565 __raw_writel(wakeups[i], pio + PIO_IDR); 1561 writel_relaxed(wakeups[i], pio + PIO_IDR);
1566 __raw_writel(backups[i], pio + PIO_IER); 1562 writel_relaxed(backups[i], pio + PIO_IER);
1567 } 1563 }
1568} 1564}
1569 1565
@@ -1694,7 +1690,7 @@ static struct gpio_chip at91_gpio_template = {
1694 .ngpio = MAX_NB_GPIO_PER_BANK, 1690 .ngpio = MAX_NB_GPIO_PER_BANK,
1695}; 1691};
1696 1692
1697static struct of_device_id at91_gpio_of_match[] = { 1693static const struct of_device_id at91_gpio_of_match[] = {
1698 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, }, 1694 { .compatible = "atmel,at91sam9x5-gpio", .data = &at91sam9x5_ops, },
1699 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops }, 1695 { .compatible = "atmel,at91rm9200-gpio", .data = &at91rm9200_ops },
1700 { /* sentinel */ } 1696 { /* sentinel */ }
diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h
index c7cfad5527d7..eb89ba045228 100644
--- a/drivers/pinctrl/pinctrl-lantiq.h
+++ b/drivers/pinctrl/pinctrl-lantiq.h
@@ -193,4 +193,4 @@ enum ltq_pin {
193extern int ltq_pinctrl_register(struct platform_device *pdev, 193extern int ltq_pinctrl_register(struct platform_device *pdev,
194 struct ltq_pinmux_info *info); 194 struct ltq_pinmux_info *info);
195extern int ltq_pinctrl_unregister(struct platform_device *pdev); 195extern int ltq_pinctrl_unregister(struct platform_device *pdev);
196#endif /* __PINCTRL_PXA3XX_H */ 196#endif /* __PINCTRL_LANTIQ_H */
diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c
index 26461e30f0ae..2631df0504bd 100644
--- a/drivers/pinctrl/pinctrl-palmas.c
+++ b/drivers/pinctrl/pinctrl-palmas.c
@@ -987,7 +987,7 @@ static struct palmas_pinctrl_data tps80036_pinctrl_data = {
987 .num_pin_groups = ARRAY_SIZE(tps80036_pingroups), 987 .num_pin_groups = ARRAY_SIZE(tps80036_pingroups),
988}; 988};
989 989
990static struct of_device_id palmas_pinctrl_of_match[] = { 990static const struct of_device_id palmas_pinctrl_of_match[] = {
991 { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data}, 991 { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data},
992 { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data}, 992 { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data},
993 { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data}, 993 { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data},
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 69e84427f913..13b45f297727 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -1501,7 +1501,7 @@ static void pcs_free_resources(struct pcs_device *pcs)
1501 } \ 1501 } \
1502 } while (0); 1502 } while (0);
1503 1503
1504static struct of_device_id pcs_of_match[]; 1504static const struct of_device_id pcs_of_match[];
1505 1505
1506static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) 1506static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1507{ 1507{
@@ -2000,7 +2000,7 @@ static const struct pcs_soc_data pinconf_single = {
2000 .flags = PCS_FEAT_PINCONF, 2000 .flags = PCS_FEAT_PINCONF,
2001}; 2001};
2002 2002
2003static struct of_device_id pcs_of_match[] = { 2003static const struct of_device_id pcs_of_match[] = {
2004 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, 2004 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
2005 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, 2005 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
2006 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, 2006 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 9e5ec00084bb..65bf73b70e34 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -206,6 +206,8 @@
206#define gpio_chip_to_bank(chip) \ 206#define gpio_chip_to_bank(chip) \
207 container_of(chip, struct st_gpio_bank, gpio_chip) 207 container_of(chip, struct st_gpio_bank, gpio_chip)
208 208
209#define pc_to_bank(pc) \
210 container_of(pc, struct st_gpio_bank, pc)
209 211
210enum st_retime_style { 212enum st_retime_style {
211 st_retime_style_none, 213 st_retime_style_none,
@@ -398,6 +400,16 @@ static const struct st_pctl_data stih407_flashdata = {
398 .rt = 100, 400 .rt = 100,
399}; 401};
400 402
403static struct st_pio_control *st_get_pio_control(
404 struct pinctrl_dev *pctldev, int pin)
405{
406 struct pinctrl_gpio_range *range =
407 pinctrl_find_gpio_range_from_pin(pctldev, pin);
408 struct st_gpio_bank *bank = gpio_range_to_bank(range);
409
410 return &bank->pc;
411}
412
401/* Low level functions.. */ 413/* Low level functions.. */
402static inline int st_gpio_bank(int gpio) 414static inline int st_gpio_bank(int gpio)
403{ 415{
@@ -460,6 +472,20 @@ static void st_pctl_set_function(struct st_pio_control *pc,
460 regmap_field_write(alt, val); 472 regmap_field_write(alt, val);
461} 473}
462 474
475static unsigned int st_pctl_get_pin_function(struct st_pio_control *pc, int pin)
476{
477 struct regmap_field *alt = pc->alt;
478 unsigned int val;
479 int offset = pin * 4;
480
481 if (!alt)
482 return 0;
483
484 regmap_field_read(alt, &val);
485
486 return (val >> offset) & 0xf;
487}
488
463static unsigned long st_pinconf_delay_to_bit(unsigned int delay, 489static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
464 const struct st_pctl_data *data, unsigned long config) 490 const struct st_pctl_data *data, unsigned long config)
465{ 491{
@@ -757,6 +783,35 @@ static int st_gpio_direction_output(struct gpio_chip *chip,
757 return 0; 783 return 0;
758} 784}
759 785
786static int st_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
787{
788 struct st_gpio_bank *bank = gpio_chip_to_bank(chip);
789 struct st_pio_control pc = bank->pc;
790 unsigned long config;
791 unsigned int direction = 0;
792 unsigned int function;
793 unsigned int value;
794 int i = 0;
795
796 /* Alternate function direction is handled by Pinctrl */
797 function = st_pctl_get_pin_function(&pc, offset);
798 if (function) {
799 st_pinconf_get_direction(&pc, offset, &config);
800 return !ST_PINCONF_UNPACK_OE(config);
801 }
802
803 /*
804 * GPIO direction is handled differently
805 * - See st_gpio_direction() above for an explanation
806 */
807 for (i = 0; i <= 2; i++) {
808 value = readl(bank->base + REG_PIO_PC(i));
809 direction |= ((value >> offset) & 0x1) << i;
810 }
811
812 return (direction == ST_GPIO_DIRECTION_IN);
813}
814
760static int st_gpio_xlate(struct gpio_chip *gc, 815static int st_gpio_xlate(struct gpio_chip *gc,
761 const struct of_phandle_args *gpiospec, u32 *flags) 816 const struct of_phandle_args *gpiospec, u32 *flags)
762{ 817{
@@ -904,16 +959,6 @@ static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
904 return 0; 959 return 0;
905} 960}
906 961
907static struct st_pio_control *st_get_pio_control(
908 struct pinctrl_dev *pctldev, int pin)
909{
910 struct pinctrl_gpio_range *range =
911 pinctrl_find_gpio_range_from_pin(pctldev, pin);
912 struct st_gpio_bank *bank = gpio_range_to_bank(range);
913
914 return &bank->pc;
915}
916
917static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, 962static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
918 unsigned group) 963 unsigned group)
919{ 964{
@@ -1011,17 +1056,30 @@ static int st_pinconf_get(struct pinctrl_dev *pctldev,
1011static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev, 1056static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1012 struct seq_file *s, unsigned pin_id) 1057 struct seq_file *s, unsigned pin_id)
1013{ 1058{
1059 struct st_pio_control *pc;
1014 unsigned long config; 1060 unsigned long config;
1061 unsigned int function;
1062 int offset = st_gpio_pin(pin_id);
1063 char f[16];
1015 1064
1016 mutex_unlock(&pctldev->mutex); 1065 mutex_unlock(&pctldev->mutex);
1066 pc = st_get_pio_control(pctldev, pin_id);
1017 st_pinconf_get(pctldev, pin_id, &config); 1067 st_pinconf_get(pctldev, pin_id, &config);
1018 mutex_lock(&pctldev->mutex); 1068 mutex_lock(&pctldev->mutex);
1019 seq_printf(s, "[OE:%ld,PU:%ld,OD:%ld]\n" 1069
1070 function = st_pctl_get_pin_function(pc, offset);
1071 if (function)
1072 snprintf(f, 10, "Alt Fn %d", function);
1073 else
1074 snprintf(f, 5, "GPIO");
1075
1076 seq_printf(s, "[OE:%d,PU:%ld,OD:%ld]\t%s\n"
1020 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld," 1077 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
1021 "de:%ld,rt-clk:%ld,rt-delay:%ld]", 1078 "de:%ld,rt-clk:%ld,rt-delay:%ld]",
1022 ST_PINCONF_UNPACK_OE(config), 1079 !st_gpio_get_direction(&pc_to_bank(pc)->gpio_chip, offset),
1023 ST_PINCONF_UNPACK_PU(config), 1080 ST_PINCONF_UNPACK_PU(config),
1024 ST_PINCONF_UNPACK_OD(config), 1081 ST_PINCONF_UNPACK_OD(config),
1082 f,
1025 ST_PINCONF_UNPACK_RT(config), 1083 ST_PINCONF_UNPACK_RT(config),
1026 ST_PINCONF_UNPACK_RT_INVERTCLK(config), 1084 ST_PINCONF_UNPACK_RT_INVERTCLK(config),
1027 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), 1085 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
@@ -1438,6 +1496,7 @@ static struct gpio_chip st_gpio_template = {
1438 .set = st_gpio_set, 1496 .set = st_gpio_set,
1439 .direction_input = st_gpio_direction_input, 1497 .direction_input = st_gpio_direction_input,
1440 .direction_output = st_gpio_direction_output, 1498 .direction_output = st_gpio_direction_output,
1499 .get_direction = st_gpio_get_direction,
1441 .ngpio = ST_GPIO_PINS_PER_BANK, 1500 .ngpio = ST_GPIO_PINS_PER_BANK,
1442 .of_gpio_n_cells = 1, 1501 .of_gpio_n_cells = 1,
1443 .of_xlate = st_gpio_xlate, 1502 .of_xlate = st_gpio_xlate,
@@ -1531,7 +1590,7 @@ static int st_gpiolib_register_bank(struct st_pinctrl *info,
1531 return 0; 1590 return 0;
1532} 1591}
1533 1592
1534static struct of_device_id st_pctl_of_match[] = { 1593static const struct of_device_id st_pctl_of_match[] = {
1535 { .compatible = "st,stih415-sbc-pinctrl", .data = &stih415_sbc_data }, 1594 { .compatible = "st,stih415-sbc-pinctrl", .data = &stih415_sbc_data },
1536 { .compatible = "st,stih415-rear-pinctrl", .data = &stih415_rear_data }, 1595 { .compatible = "st,stih415-rear-pinctrl", .data = &stih415_rear_data },
1537 { .compatible = "st,stih415-left-pinctrl", .data = &stih415_left_data }, 1596 { .compatible = "st,stih415-left-pinctrl", .data = &stih415_left_data },
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index e5949d51bc52..4c95c2024a1c 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -103,6 +103,7 @@ static const struct cfg_param {
103 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, 103 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
104 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, 104 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
105 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL}, 105 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
106 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
106 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, 107 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
107 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, 108 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
108 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, 109 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
@@ -348,14 +349,24 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
348 *width = 1; 349 *width = 1;
349 break; 350 break;
350 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE: 351 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
351 *bank = g->drv_bank; 352 if (pmx->soc->hsm_in_mux) {
352 *reg = g->drv_reg; 353 *bank = g->mux_bank;
354 *reg = g->mux_reg;
355 } else {
356 *bank = g->drv_bank;
357 *reg = g->drv_reg;
358 }
353 *bit = g->hsm_bit; 359 *bit = g->hsm_bit;
354 *width = 1; 360 *width = 1;
355 break; 361 break;
356 case TEGRA_PINCONF_PARAM_SCHMITT: 362 case TEGRA_PINCONF_PARAM_SCHMITT:
357 *bank = g->drv_bank; 363 if (pmx->soc->schmitt_in_mux) {
358 *reg = g->drv_reg; 364 *bank = g->mux_bank;
365 *reg = g->mux_reg;
366 } else {
367 *bank = g->drv_bank;
368 *reg = g->drv_reg;
369 }
359 *bit = g->schmitt_bit; 370 *bit = g->schmitt_bit;
360 *width = 1; 371 *width = 1;
361 break; 372 break;
@@ -390,8 +401,13 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx,
390 *width = g->slwr_width; 401 *width = g->slwr_width;
391 break; 402 break;
392 case TEGRA_PINCONF_PARAM_DRIVE_TYPE: 403 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
393 *bank = g->drv_bank; 404 if (pmx->soc->drvtype_in_mux) {
394 *reg = g->drv_reg; 405 *bank = g->mux_bank;
406 *reg = g->mux_reg;
407 } else {
408 *bank = g->drv_bank;
409 *reg = g->drv_reg;
410 }
395 *bit = g->drvtype_bit; 411 *bit = g->drvtype_bit;
396 *width = 2; 412 *width = 2;
397 break; 413 break;
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h
index 8d94d1332e7b..1615db7e3a4b 100644
--- a/drivers/pinctrl/pinctrl-tegra.h
+++ b/drivers/pinctrl/pinctrl-tegra.h
@@ -139,26 +139,26 @@ struct tegra_pingroup {
139 u32 pupd_bank:2; 139 u32 pupd_bank:2;
140 u32 tri_bank:2; 140 u32 tri_bank:2;
141 u32 drv_bank:2; 141 u32 drv_bank:2;
142 u32 mux_bit:6; 142 s32 mux_bit:6;
143 u32 pupd_bit:6; 143 s32 pupd_bit:6;
144 u32 tri_bit:6; 144 s32 tri_bit:6;
145 u32 einput_bit:6; 145 s32 einput_bit:6;
146 u32 odrain_bit:6; 146 s32 odrain_bit:6;
147 u32 lock_bit:6; 147 s32 lock_bit:6;
148 u32 ioreset_bit:6; 148 s32 ioreset_bit:6;
149 u32 rcv_sel_bit:6; 149 s32 rcv_sel_bit:6;
150 u32 hsm_bit:6; 150 s32 hsm_bit:6;
151 u32 schmitt_bit:6; 151 s32 schmitt_bit:6;
152 u32 lpmd_bit:6; 152 s32 lpmd_bit:6;
153 u32 drvdn_bit:6; 153 s32 drvdn_bit:6;
154 u32 drvup_bit:6; 154 s32 drvup_bit:6;
155 u32 slwr_bit:6; 155 s32 slwr_bit:6;
156 u32 slwf_bit:6; 156 s32 slwf_bit:6;
157 u32 drvtype_bit:6; 157 s32 drvtype_bit:6;
158 u32 drvdn_width:6; 158 s32 drvdn_width:6;
159 u32 drvup_width:6; 159 s32 drvup_width:6;
160 u32 slwr_width:6; 160 s32 slwr_width:6;
161 u32 slwf_width:6; 161 s32 slwf_width:6;
162}; 162};
163 163
164/** 164/**
@@ -182,6 +182,9 @@ struct tegra_pinctrl_soc_data {
182 unsigned nfunctions; 182 unsigned nfunctions;
183 const struct tegra_pingroup *groups; 183 const struct tegra_pingroup *groups;
184 unsigned ngroups; 184 unsigned ngroups;
185 bool hsm_in_mux;
186 bool schmitt_in_mux;
187 bool drvtype_in_mux;
185}; 188};
186 189
187int tegra_pinctrl_probe(struct platform_device *pdev, 190int tegra_pinctrl_probe(struct platform_device *pdev,
diff --git a/drivers/pinctrl/pinctrl-tegra114.c b/drivers/pinctrl/pinctrl-tegra114.c
index 52e4ec6386b4..05e49d5137ab 100644
--- a/drivers/pinctrl/pinctrl-tegra114.c
+++ b/drivers/pinctrl/pinctrl-tegra114.c
@@ -1547,6 +1547,7 @@ static struct tegra_function tegra114_functions[] = {
1547#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1547#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1548#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1548#define PINGROUP_REG_A 0x3000 /* bank 1 */
1549 1549
1550#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1550#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) 1551#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1551 1552
1552#define PINGROUP_BIT_Y(b) (b) 1553#define PINGROUP_BIT_Y(b) (b)
@@ -1572,20 +1573,17 @@ static struct tegra_function tegra114_functions[] = {
1572 .tri_reg = PINGROUP_REG(r), \ 1573 .tri_reg = PINGROUP_REG(r), \
1573 .tri_bank = 1, \ 1574 .tri_bank = 1, \
1574 .tri_bit = 4, \ 1575 .tri_bit = 4, \
1575 .einput_bit = PINGROUP_BIT_Y(5), \ 1576 .einput_bit = 5, \
1576 .odrain_bit = PINGROUP_BIT_##od(6), \ 1577 .odrain_bit = PINGROUP_BIT_##od(6), \
1577 .lock_bit = PINGROUP_BIT_Y(7), \ 1578 .lock_bit = 7, \
1578 .ioreset_bit = PINGROUP_BIT_##ior(8), \ 1579 .ioreset_bit = PINGROUP_BIT_##ior(8), \
1579 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \ 1580 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
1580 .drv_reg = -1, \ 1581 .drv_reg = -1, \
1581 } 1582 }
1582 1583
1583#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) 1584#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
1584 1585 drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
1585#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1586 slwf_b, slwf_w, drvtype) \
1586 drvdn_b, drvdn_w, drvup_b, drvup_w, \
1587 slwr_b, slwr_w, slwf_b, slwf_w, \
1588 drvtype) \
1589 { \ 1587 { \
1590 .name = "drive_" #pg_name, \ 1588 .name = "drive_" #pg_name, \
1591 .pins = drive_##pg_name##_pins, \ 1589 .pins = drive_##pg_name##_pins, \
@@ -1843,6 +1841,9 @@ static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {
1843 .nfunctions = ARRAY_SIZE(tegra114_functions), 1841 .nfunctions = ARRAY_SIZE(tegra114_functions),
1844 .groups = tegra114_groups, 1842 .groups = tegra114_groups,
1845 .ngroups = ARRAY_SIZE(tegra114_groups), 1843 .ngroups = ARRAY_SIZE(tegra114_groups),
1844 .hsm_in_mux = false,
1845 .schmitt_in_mux = false,
1846 .drvtype_in_mux = false,
1846}; 1847};
1847 1848
1848static int tegra114_pinctrl_probe(struct platform_device *pdev) 1849static int tegra114_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
index 2b20906c5356..7cd44c7c296d 100644
--- a/drivers/pinctrl/pinctrl-tegra124.c
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -1536,6 +1536,7 @@ enum tegra_mux {
1536 TEGRA_MUX_CLK, 1536 TEGRA_MUX_CLK,
1537 TEGRA_MUX_CLK12, 1537 TEGRA_MUX_CLK12,
1538 TEGRA_MUX_CPU, 1538 TEGRA_MUX_CPU,
1539 TEGRA_MUX_CSI,
1539 TEGRA_MUX_DAP, 1540 TEGRA_MUX_DAP,
1540 TEGRA_MUX_DAP1, 1541 TEGRA_MUX_DAP1,
1541 TEGRA_MUX_DAP2, 1542 TEGRA_MUX_DAP2,
@@ -1544,6 +1545,7 @@ enum tegra_mux {
1544 TEGRA_MUX_DISPLAYA_ALT, 1545 TEGRA_MUX_DISPLAYA_ALT,
1545 TEGRA_MUX_DISPLAYB, 1546 TEGRA_MUX_DISPLAYB,
1546 TEGRA_MUX_DP, 1547 TEGRA_MUX_DP,
1548 TEGRA_MUX_DSI_B,
1547 TEGRA_MUX_DTV, 1549 TEGRA_MUX_DTV,
1548 TEGRA_MUX_EXTPERIPH1, 1550 TEGRA_MUX_EXTPERIPH1,
1549 TEGRA_MUX_EXTPERIPH2, 1551 TEGRA_MUX_EXTPERIPH2,
@@ -1613,8 +1615,6 @@ enum tegra_mux {
1613 TEGRA_MUX_VI_ALT3, 1615 TEGRA_MUX_VI_ALT3,
1614 TEGRA_MUX_VIMCLK2, 1616 TEGRA_MUX_VIMCLK2,
1615 TEGRA_MUX_VIMCLK2_ALT, 1617 TEGRA_MUX_VIMCLK2_ALT,
1616 TEGRA_MUX_CSI,
1617 TEGRA_MUX_DSI_B,
1618}; 1618};
1619 1619
1620#define FUNCTION(fname) \ 1620#define FUNCTION(fname) \
@@ -1630,6 +1630,7 @@ static struct tegra_function tegra124_functions[] = {
1630 FUNCTION(clk), 1630 FUNCTION(clk),
1631 FUNCTION(clk12), 1631 FUNCTION(clk12),
1632 FUNCTION(cpu), 1632 FUNCTION(cpu),
1633 FUNCTION(csi),
1633 FUNCTION(dap), 1634 FUNCTION(dap),
1634 FUNCTION(dap1), 1635 FUNCTION(dap1),
1635 FUNCTION(dap2), 1636 FUNCTION(dap2),
@@ -1638,6 +1639,7 @@ static struct tegra_function tegra124_functions[] = {
1638 FUNCTION(displaya_alt), 1639 FUNCTION(displaya_alt),
1639 FUNCTION(displayb), 1640 FUNCTION(displayb),
1640 FUNCTION(dp), 1641 FUNCTION(dp),
1642 FUNCTION(dsi_b),
1641 FUNCTION(dtv), 1643 FUNCTION(dtv),
1642 FUNCTION(extperiph1), 1644 FUNCTION(extperiph1),
1643 FUNCTION(extperiph2), 1645 FUNCTION(extperiph2),
@@ -1707,15 +1709,15 @@ static struct tegra_function tegra124_functions[] = {
1707 FUNCTION(vi_alt3), 1709 FUNCTION(vi_alt3),
1708 FUNCTION(vimclk2), 1710 FUNCTION(vimclk2),
1709 FUNCTION(vimclk2_alt), 1711 FUNCTION(vimclk2_alt),
1710 FUNCTION(csi),
1711 FUNCTION(dsi_b),
1712}; 1712};
1713 1713
1714#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 1714#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
1715#define PINGROUP_REG_A 0x3000 /* bank 1 */ 1715#define PINGROUP_REG_A 0x3000 /* bank 1 */
1716#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */ 1716#define MIPI_PAD_CTRL_PINGROUP_REG_A 0x820 /* bank 2 */
1717 1717
1718#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1718#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) 1719#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1720#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
1719 1721
1720#define PINGROUP_BIT_Y(b) (b) 1722#define PINGROUP_BIT_Y(b) (b)
1721#define PINGROUP_BIT_N(b) (-1) 1723#define PINGROUP_BIT_N(b) (-1)
@@ -1740,20 +1742,17 @@ static struct tegra_function tegra124_functions[] = {
1740 .tri_reg = PINGROUP_REG(r), \ 1742 .tri_reg = PINGROUP_REG(r), \
1741 .tri_bank = 1, \ 1743 .tri_bank = 1, \
1742 .tri_bit = 4, \ 1744 .tri_bit = 4, \
1743 .einput_bit = PINGROUP_BIT_Y(5), \ 1745 .einput_bit = 5, \
1744 .odrain_bit = PINGROUP_BIT_##od(6), \ 1746 .odrain_bit = PINGROUP_BIT_##od(6), \
1745 .lock_bit = PINGROUP_BIT_Y(7), \ 1747 .lock_bit = 7, \
1746 .ioreset_bit = PINGROUP_BIT_##ior(8), \ 1748 .ioreset_bit = PINGROUP_BIT_##ior(8), \
1747 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \ 1749 .rcv_sel_bit = PINGROUP_BIT_##rcv_sel(9), \
1748 .drv_reg = -1, \ 1750 .drv_reg = -1, \
1749 } 1751 }
1750 1752
1751#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) 1753#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
1752 1754 drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
1753#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 1755 slwf_b, slwf_w, drvtype) \
1754 drvdn_b, drvdn_w, drvup_b, drvup_w, \
1755 slwr_b, slwr_w, slwf_b, slwf_w, \
1756 drvtype) \
1757 { \ 1756 { \
1758 .name = "drive_" #pg_name, \ 1757 .name = "drive_" #pg_name, \
1759 .pins = drive_##pg_name##_pins, \ 1758 .pins = drive_##pg_name##_pins, \
@@ -1782,8 +1781,6 @@ static struct tegra_function tegra124_functions[] = {
1782 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \ 1781 .drvtype_bit = PINGROUP_BIT_##drvtype(6), \
1783 } 1782 }
1784 1783
1785#define MIPI_PAD_CTRL_PINGROUP_REG_Y(r) ((r) - MIPI_PAD_CTRL_PINGROUP_REG_A)
1786
1787#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \ 1784#define MIPI_PAD_CTRL_PINGROUP(pg_name, r, b, f0, f1) \
1788 { \ 1785 { \
1789 .name = "mipi_pad_ctrl_" #pg_name, \ 1786 .name = "mipi_pad_ctrl_" #pg_name, \
@@ -2044,8 +2041,8 @@ static const struct tegra_pingroup tegra124_groups[] = {
2044 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N), 2041 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
2045 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y), 2042 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
2046 2043
2047 /* pg_name, r b f0, f1 */ 2044 /* pg_name, r, b, f0, f1 */
2048 MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B) 2045 MIPI_PAD_CTRL_PINGROUP(dsi_b, 0x820, 1, CSI, DSI_B),
2049}; 2046};
2050 2047
2051static const struct tegra_pinctrl_soc_data tegra124_pinctrl = { 2048static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
@@ -2056,6 +2053,9 @@ static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
2056 .nfunctions = ARRAY_SIZE(tegra124_functions), 2053 .nfunctions = ARRAY_SIZE(tegra124_functions),
2057 .groups = tegra124_groups, 2054 .groups = tegra124_groups,
2058 .ngroups = ARRAY_SIZE(tegra124_groups), 2055 .ngroups = ARRAY_SIZE(tegra124_groups),
2056 .hsm_in_mux = false,
2057 .schmitt_in_mux = false,
2058 .drvtype_in_mux = false,
2059}; 2059};
2060 2060
2061static int tegra124_pinctrl_probe(struct platform_device *pdev) 2061static int tegra124_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c
index d3a5722e4acb..4833db4433d9 100644
--- a/drivers/pinctrl/pinctrl-tegra20.c
+++ b/drivers/pinctrl/pinctrl-tegra20.c
@@ -2221,6 +2221,9 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {
2221 .nfunctions = ARRAY_SIZE(tegra20_functions), 2221 .nfunctions = ARRAY_SIZE(tegra20_functions),
2222 .groups = tegra20_groups, 2222 .groups = tegra20_groups,
2223 .ngroups = ARRAY_SIZE(tegra20_groups), 2223 .ngroups = ARRAY_SIZE(tegra20_groups),
2224 .hsm_in_mux = false,
2225 .schmitt_in_mux = false,
2226 .drvtype_in_mux = false,
2224}; 2227};
2225 2228
2226static int tegra20_pinctrl_probe(struct platform_device *pdev) 2229static int tegra20_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/pinctrl-tegra210.c b/drivers/pinctrl/pinctrl-tegra210.c
new file mode 100644
index 000000000000..252b464901c0
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-tegra210.c
@@ -0,0 +1,1588 @@
1/*
2 * Pinctrl data for the NVIDIA Tegra210 pinmux
3 *
4 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21
22#include "pinctrl-tegra.h"
23
24/*
25 * Most pins affected by the pinmux can also be GPIOs. Define these first.
26 * These must match how the GPIO driver names/numbers its pins.
27 */
28#define _GPIO(offset) (offset)
29
30#define TEGRA_PIN_PEX_L0_RST_N_PA0 _GPIO(0)
31#define TEGRA_PIN_PEX_L0_CLKREQ_N_PA1 _GPIO(1)
32#define TEGRA_PIN_PEX_WAKE_N_PA2 _GPIO(2)
33#define TEGRA_PIN_PEX_L1_RST_N_PA3 _GPIO(3)
34#define TEGRA_PIN_PEX_L1_CLKREQ_N_PA4 _GPIO(4)
35#define TEGRA_PIN_SATA_LED_ACTIVE_PA5 _GPIO(5)
36#define TEGRA_PIN_PA6 _GPIO(6)
37#define TEGRA_PIN_DAP1_FS_PB0 _GPIO(8)
38#define TEGRA_PIN_DAP1_DIN_PB1 _GPIO(9)
39#define TEGRA_PIN_DAP1_DOUT_PB2 _GPIO(10)
40#define TEGRA_PIN_DAP1_SCLK_PB3 _GPIO(11)
41#define TEGRA_PIN_SPI2_MOSI_PB4 _GPIO(12)
42#define TEGRA_PIN_SPI2_MISO_PB5 _GPIO(13)
43#define TEGRA_PIN_SPI2_SCK_PB6 _GPIO(14)
44#define TEGRA_PIN_SPI2_CS0_PB7 _GPIO(15)
45#define TEGRA_PIN_SPI1_MOSI_PC0 _GPIO(16)
46#define TEGRA_PIN_SPI1_MISO_PC1 _GPIO(17)
47#define TEGRA_PIN_SPI1_SCK_PC2 _GPIO(18)
48#define TEGRA_PIN_SPI1_CS0_PC3 _GPIO(19)
49#define TEGRA_PIN_SPI1_CS1_PC4 _GPIO(20)
50#define TEGRA_PIN_SPI4_SCK_PC5 _GPIO(21)
51#define TEGRA_PIN_SPI4_CS0_PC6 _GPIO(22)
52#define TEGRA_PIN_SPI4_MOSI_PC7 _GPIO(23)
53#define TEGRA_PIN_SPI4_MISO_PD0 _GPIO(24)
54#define TEGRA_PIN_UART3_TX_PD1 _GPIO(25)
55#define TEGRA_PIN_UART3_RX_PD2 _GPIO(26)
56#define TEGRA_PIN_UART3_RTS_PD3 _GPIO(27)
57#define TEGRA_PIN_UART3_CTS_PD4 _GPIO(28)
58#define TEGRA_PIN_DMIC1_CLK_PE0 _GPIO(32)
59#define TEGRA_PIN_DMIC1_DAT_PE1 _GPIO(33)
60#define TEGRA_PIN_DMIC2_CLK_PE2 _GPIO(34)
61#define TEGRA_PIN_DMIC2_DAT_PE3 _GPIO(35)
62#define TEGRA_PIN_DMIC3_CLK_PE4 _GPIO(36)
63#define TEGRA_PIN_DMIC3_DAT_PE5 _GPIO(37)
64#define TEGRA_PIN_PE6 _GPIO(38)
65#define TEGRA_PIN_PE7 _GPIO(39)
66#define TEGRA_PIN_GEN3_I2C_SCL_PF0 _GPIO(40)
67#define TEGRA_PIN_GEN3_I2C_SDA_PF1 _GPIO(41)
68#define TEGRA_PIN_UART2_TX_PG0 _GPIO(48)
69#define TEGRA_PIN_UART2_RX_PG1 _GPIO(49)
70#define TEGRA_PIN_UART2_RTS_PG2 _GPIO(50)
71#define TEGRA_PIN_UART2_CTS_PG3 _GPIO(51)
72#define TEGRA_PIN_WIFI_EN_PH0 _GPIO(56)
73#define TEGRA_PIN_WIFI_RST_PH1 _GPIO(57)
74#define TEGRA_PIN_WIFI_WAKE_AP_PH2 _GPIO(58)
75#define TEGRA_PIN_AP_WAKE_BT_PH3 _GPIO(59)
76#define TEGRA_PIN_BT_RST_PH4 _GPIO(60)
77#define TEGRA_PIN_BT_WAKE_AP_PH5 _GPIO(61)
78#define TEGRA_PIN_PH6 _GPIO(62)
79#define TEGRA_PIN_AP_WAKE_NFC_PH7 _GPIO(63)
80#define TEGRA_PIN_NFC_EN_PI0 _GPIO(64)
81#define TEGRA_PIN_NFC_INT_PI1 _GPIO(65)
82#define TEGRA_PIN_GPS_EN_PI2 _GPIO(66)
83#define TEGRA_PIN_GPS_RST_PI3 _GPIO(67)
84#define TEGRA_PIN_UART4_TX_PI4 _GPIO(68)
85#define TEGRA_PIN_UART4_RX_PI5 _GPIO(69)
86#define TEGRA_PIN_UART4_RTS_PI6 _GPIO(70)
87#define TEGRA_PIN_UART4_CTS_PI7 _GPIO(71)
88#define TEGRA_PIN_GEN1_I2C_SDA_PJ0 _GPIO(72)
89#define TEGRA_PIN_GEN1_I2C_SCL_PJ1 _GPIO(73)
90#define TEGRA_PIN_GEN2_I2C_SCL_PJ2 _GPIO(74)
91#define TEGRA_PIN_GEN2_I2C_SDA_PJ3 _GPIO(75)
92#define TEGRA_PIN_DAP4_FS_PJ4 _GPIO(76)
93#define TEGRA_PIN_DAP4_DIN_PJ5 _GPIO(77)
94#define TEGRA_PIN_DAP4_DOUT_PJ6 _GPIO(78)
95#define TEGRA_PIN_DAP4_SCLK_PJ7 _GPIO(79)
96#define TEGRA_PIN_PK0 _GPIO(80)
97#define TEGRA_PIN_PK1 _GPIO(81)
98#define TEGRA_PIN_PK2 _GPIO(82)
99#define TEGRA_PIN_PK3 _GPIO(83)
100#define TEGRA_PIN_PK4 _GPIO(84)
101#define TEGRA_PIN_PK5 _GPIO(85)
102#define TEGRA_PIN_PK6 _GPIO(86)
103#define TEGRA_PIN_PK7 _GPIO(87)
104#define TEGRA_PIN_PL0 _GPIO(88)
105#define TEGRA_PIN_PL1 _GPIO(89)
106#define TEGRA_PIN_SDMMC1_CLK_PM0 _GPIO(96)
107#define TEGRA_PIN_SDMMC1_CMD_PM1 _GPIO(97)
108#define TEGRA_PIN_SDMMC1_DAT3_PM2 _GPIO(98)
109#define TEGRA_PIN_SDMMC1_DAT2_PM3 _GPIO(99)
110#define TEGRA_PIN_SDMMC1_DAT1_PM4 _GPIO(100)
111#define TEGRA_PIN_SDMMC1_DAT0_PM5 _GPIO(101)
112#define TEGRA_PIN_SDMMC3_CLK_PP0 _GPIO(120)
113#define TEGRA_PIN_SDMMC3_CMD_PP1 _GPIO(121)
114#define TEGRA_PIN_SDMMC3_DAT3_PP2 _GPIO(122)
115#define TEGRA_PIN_SDMMC3_DAT2_PP3 _GPIO(123)
116#define TEGRA_PIN_SDMMC3_DAT1_PP4 _GPIO(124)
117#define TEGRA_PIN_SDMMC3_DAT0_PP5 _GPIO(125)
118#define TEGRA_PIN_CAM1_MCLK_PS0 _GPIO(144)
119#define TEGRA_PIN_CAM2_MCLK_PS1 _GPIO(145)
120#define TEGRA_PIN_CAM_I2C_SCL_PS2 _GPIO(146)
121#define TEGRA_PIN_CAM_I2C_SDA_PS3 _GPIO(147)
122#define TEGRA_PIN_CAM_RST_PS4 _GPIO(148)
123#define TEGRA_PIN_CAM_AF_EN_PS5 _GPIO(149)
124#define TEGRA_PIN_CAM_FLASH_EN_PS6 _GPIO(150)
125#define TEGRA_PIN_CAM1_PWDN_PS7 _GPIO(151)
126#define TEGRA_PIN_CAM2_PWDN_PT0 _GPIO(152)
127#define TEGRA_PIN_CAM1_STROBE_PT1 _GPIO(153)
128#define TEGRA_PIN_UART1_TX_PU0 _GPIO(160)
129#define TEGRA_PIN_UART1_RX_PU1 _GPIO(161)
130#define TEGRA_PIN_UART1_RTS_PU2 _GPIO(162)
131#define TEGRA_PIN_UART1_CTS_PU3 _GPIO(163)
132#define TEGRA_PIN_LCD_BL_PWM_PV0 _GPIO(168)
133#define TEGRA_PIN_LCD_BL_EN_PV1 _GPIO(169)
134#define TEGRA_PIN_LCD_RST_PV2 _GPIO(170)
135#define TEGRA_PIN_LCD_GPIO1_PV3 _GPIO(171)
136#define TEGRA_PIN_LCD_GPIO2_PV4 _GPIO(172)
137#define TEGRA_PIN_AP_READY_PV5 _GPIO(173)
138#define TEGRA_PIN_TOUCH_RST_PV6 _GPIO(174)
139#define TEGRA_PIN_TOUCH_CLK_PV7 _GPIO(175)
140#define TEGRA_PIN_MODEM_WAKE_AP_PX0 _GPIO(184)
141#define TEGRA_PIN_TOUCH_INT_PX1 _GPIO(185)
142#define TEGRA_PIN_MOTION_INT_PX2 _GPIO(186)
143#define TEGRA_PIN_ALS_PROX_INT_PX3 _GPIO(187)
144#define TEGRA_PIN_TEMP_ALERT_PX4 _GPIO(188)
145#define TEGRA_PIN_BUTTON_POWER_ON_PX5 _GPIO(189)
146#define TEGRA_PIN_BUTTON_VOL_UP_PX6 _GPIO(190)
147#define TEGRA_PIN_BUTTON_VOL_DOWN_PX7 _GPIO(191)
148#define TEGRA_PIN_BUTTON_SLIDE_SW_PY0 _GPIO(192)
149#define TEGRA_PIN_BUTTON_HOME_PY1 _GPIO(193)
150#define TEGRA_PIN_LCD_TE_PY2 _GPIO(194)
151#define TEGRA_PIN_PWR_I2C_SCL_PY3 _GPIO(195)
152#define TEGRA_PIN_PWR_I2C_SDA_PY4 _GPIO(196)
153#define TEGRA_PIN_CLK_32K_OUT_PY5 _GPIO(197)
154#define TEGRA_PIN_PZ0 _GPIO(200)
155#define TEGRA_PIN_PZ1 _GPIO(201)
156#define TEGRA_PIN_PZ2 _GPIO(202)
157#define TEGRA_PIN_PZ3 _GPIO(203)
158#define TEGRA_PIN_PZ4 _GPIO(204)
159#define TEGRA_PIN_PZ5 _GPIO(205)
160#define TEGRA_PIN_DAP2_FS_PAA0 _GPIO(208)
161#define TEGRA_PIN_DAP2_SCLK_PAA1 _GPIO(209)
162#define TEGRA_PIN_DAP2_DIN_PAA2 _GPIO(210)
163#define TEGRA_PIN_DAP2_DOUT_PAA3 _GPIO(211)
164#define TEGRA_PIN_AUD_MCLK_PBB0 _GPIO(216)
165#define TEGRA_PIN_DVFS_PWM_PBB1 _GPIO(217)
166#define TEGRA_PIN_DVFS_CLK_PBB2 _GPIO(218)
167#define TEGRA_PIN_GPIO_X1_AUD_PBB3 _GPIO(219)
168#define TEGRA_PIN_GPIO_X3_AUD_PBB4 _GPIO(220)
169#define TEGRA_PIN_HDMI_CEC_PCC0 _GPIO(224)
170#define TEGRA_PIN_HDMI_INT_DP_HPD_PCC1 _GPIO(225)
171#define TEGRA_PIN_SPDIF_OUT_PCC2 _GPIO(226)
172#define TEGRA_PIN_SPDIF_IN_PCC3 _GPIO(227)
173#define TEGRA_PIN_USB_VBUS_EN0_PCC4 _GPIO(228)
174#define TEGRA_PIN_USB_VBUS_EN1_PCC5 _GPIO(229)
175#define TEGRA_PIN_DP_HPD0_PCC6 _GPIO(230)
176#define TEGRA_PIN_PCC7 _GPIO(231)
177#define TEGRA_PIN_SPI2_CS1_PDD0 _GPIO(232)
178#define TEGRA_PIN_QSPI_SCK_PEE0 _GPIO(240)
179#define TEGRA_PIN_QSPI_CS_N_PEE1 _GPIO(241)
180#define TEGRA_PIN_QSPI_IO0_PEE2 _GPIO(242)
181#define TEGRA_PIN_QSPI_IO1_PEE3 _GPIO(243)
182#define TEGRA_PIN_QSPI_IO2_PEE4 _GPIO(244)
183#define TEGRA_PIN_QSPI_IO3_PEE5 _GPIO(245)
184
185/* All non-GPIO pins follow */
186#define NUM_GPIOS (TEGRA_PIN_QSPI_IO3_PEE5 + 1)
187#define _PIN(offset) (NUM_GPIOS + (offset))
188
189/* Non-GPIO pins */
190#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
191#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
192#define TEGRA_PIN_PWR_INT_N _PIN(2)
193#define TEGRA_PIN_CLK_32K_IN _PIN(3)
194#define TEGRA_PIN_JTAG_RTCK _PIN(4)
195#define TEGRA_PIN_BATT_BCL _PIN(5)
196#define TEGRA_PIN_CLK_REQ _PIN(6)
197#define TEGRA_PIN_SHUTDOWN _PIN(7)
198
199static const struct pinctrl_pin_desc tegra210_pins[] = {
200 PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PA0, "PEX_L0_RST_N PA0"),
201 PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PA1, "PEX_L0_CLKREQ_N PA1"),
202 PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PA2, "PEX_WAKE_N PA2"),
203 PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PA3, "PEX_L1_RST_N PA3"),
204 PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PA4, "PEX_L1_CLKREQ_N PA4"),
205 PINCTRL_PIN(TEGRA_PIN_SATA_LED_ACTIVE_PA5, "SATA_LED_ACTIVE PA5"),
206 PINCTRL_PIN(TEGRA_PIN_PA6, "PA6"),
207 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PB0, "DAP1_FS PB0"),
208 PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PB1, "DAP1_DIN PB1"),
209 PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PB2, "DAP1_DOUT PB2"),
210 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PB3, "DAP1_SCLK PB3"),
211 PINCTRL_PIN(TEGRA_PIN_SPI2_MOSI_PB4, "SPI2_MOSI PB4"),
212 PINCTRL_PIN(TEGRA_PIN_SPI2_MISO_PB5, "SPI2_MISO PB5"),
213 PINCTRL_PIN(TEGRA_PIN_SPI2_SCK_PB6, "SPI2_SCK PB6"),
214 PINCTRL_PIN(TEGRA_PIN_SPI2_CS0_PB7, "SPI2_CS0 PB7"),
215 PINCTRL_PIN(TEGRA_PIN_SPI1_MOSI_PC0, "SPI1_MOSI PC0"),
216 PINCTRL_PIN(TEGRA_PIN_SPI1_MISO_PC1, "SPI1_MISO PC1"),
217 PINCTRL_PIN(TEGRA_PIN_SPI1_SCK_PC2, "SPI1_SCK PC2"),
218 PINCTRL_PIN(TEGRA_PIN_SPI1_CS0_PC3, "SPI1_CS0 PC3"),
219 PINCTRL_PIN(TEGRA_PIN_SPI1_CS1_PC4, "SPI1_CS1 PC4"),
220 PINCTRL_PIN(TEGRA_PIN_SPI4_SCK_PC5, "SPI4_SCK PC5"),
221 PINCTRL_PIN(TEGRA_PIN_SPI4_CS0_PC6, "SPI4_CS0 PC6"),
222 PINCTRL_PIN(TEGRA_PIN_SPI4_MOSI_PC7, "SPI4_MOSI PC7"),
223 PINCTRL_PIN(TEGRA_PIN_SPI4_MISO_PD0, "SPI4_MISO PD0"),
224 PINCTRL_PIN(TEGRA_PIN_UART3_TX_PD1, "UART3_TX PD1"),
225 PINCTRL_PIN(TEGRA_PIN_UART3_RX_PD2, "UART3_RX PD2"),
226 PINCTRL_PIN(TEGRA_PIN_UART3_RTS_PD3, "UART3_RTS PD3"),
227 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_PD4, "UART3_CTS PD4"),
228 PINCTRL_PIN(TEGRA_PIN_DMIC1_CLK_PE0, "DMIC1_CLK PE0"),
229 PINCTRL_PIN(TEGRA_PIN_DMIC1_DAT_PE1, "DMIC1_DAT PE1"),
230 PINCTRL_PIN(TEGRA_PIN_DMIC2_CLK_PE2, "DMIC2_CLK PE2"),
231 PINCTRL_PIN(TEGRA_PIN_DMIC2_DAT_PE3, "DMIC2_DAT PE3"),
232 PINCTRL_PIN(TEGRA_PIN_DMIC3_CLK_PE4, "DMIC3_CLK PE4"),
233 PINCTRL_PIN(TEGRA_PIN_DMIC3_DAT_PE5, "DMIC3_DAT PE5"),
234 PINCTRL_PIN(TEGRA_PIN_PE6, "PE6"),
235 PINCTRL_PIN(TEGRA_PIN_PE7, "PE7"),
236 PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SCL_PF0, "GEN3_I2C_SCL PF0"),
237 PINCTRL_PIN(TEGRA_PIN_GEN3_I2C_SDA_PF1, "GEN3_I2C_SDA PF1"),
238 PINCTRL_PIN(TEGRA_PIN_UART2_TX_PG0, "UART2_TX PG0"),
239 PINCTRL_PIN(TEGRA_PIN_UART2_RX_PG1, "UART2_RX PG1"),
240 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_PG2, "UART2_RTS PG2"),
241 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_PG3, "UART2_CTS PG3"),
242 PINCTRL_PIN(TEGRA_PIN_WIFI_EN_PH0, "WIFI_EN PH0"),
243 PINCTRL_PIN(TEGRA_PIN_WIFI_RST_PH1, "WIFI_RST PH1"),
244 PINCTRL_PIN(TEGRA_PIN_WIFI_WAKE_AP_PH2, "WIFI_WAKE_AP PH2"),
245 PINCTRL_PIN(TEGRA_PIN_AP_WAKE_BT_PH3, "AP_WAKE_BT PH3"),
246 PINCTRL_PIN(TEGRA_PIN_BT_RST_PH4, "BT_RST PH4"),
247 PINCTRL_PIN(TEGRA_PIN_BT_WAKE_AP_PH5, "BT_WAKE_AP PH5"),
248 PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
249 PINCTRL_PIN(TEGRA_PIN_AP_WAKE_NFC_PH7, "AP_WAKE_NFC PH7"),
250 PINCTRL_PIN(TEGRA_PIN_NFC_EN_PI0, "NFC_EN PI0"),
251 PINCTRL_PIN(TEGRA_PIN_NFC_INT_PI1, "NFC_INT PI1"),
252 PINCTRL_PIN(TEGRA_PIN_GPS_EN_PI2, "GPS_EN PI2"),
253 PINCTRL_PIN(TEGRA_PIN_GPS_RST_PI3, "GPS_RST PI3"),
254 PINCTRL_PIN(TEGRA_PIN_UART4_TX_PI4, "UART4_TX PI4"),
255 PINCTRL_PIN(TEGRA_PIN_UART4_RX_PI5, "UART4_RX PI5"),
256 PINCTRL_PIN(TEGRA_PIN_UART4_RTS_PI6, "UART4_RTS PI6"),
257 PINCTRL_PIN(TEGRA_PIN_UART4_CTS_PI7, "UART4_CTS PI7"),
258 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PJ0, "GEN1_I2C_SDA PJ0"),
259 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PJ1, "GEN1_I2C_SCL PJ1"),
260 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PJ2, "GEN2_I2C_SCL PJ2"),
261 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PJ3, "GEN2_I2C_SDA PJ3"),
262 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PJ4, "DAP4_FS PJ4"),
263 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PJ5, "DAP4_DIN PJ5"),
264 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PJ6, "DAP4_DOUT PJ6"),
265 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PJ7, "DAP4_SCLK PJ7"),
266 PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
267 PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
268 PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
269 PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
270 PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
271 PINCTRL_PIN(TEGRA_PIN_PK5, "PK5"),
272 PINCTRL_PIN(TEGRA_PIN_PK6, "PK6"),
273 PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
274 PINCTRL_PIN(TEGRA_PIN_PL0, "PL0"),
275 PINCTRL_PIN(TEGRA_PIN_PL1, "PL1"),
276 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PM0, "SDMMC1_CLK PM0"),
277 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PM1, "SDMMC1_CMD PM1"),
278 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PM2, "SDMMC1_DAT3 PM2"),
279 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PM3, "SDMMC1_DAT2 PM3"),
280 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PM4, "SDMMC1_DAT1 PM4"),
281 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PM5, "SDMMC1_DAT0 PM5"),
282 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PP0, "SDMMC3_CLK PP0"),
283 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PP1, "SDMMC3_CMD PP1"),
284 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PP2, "SDMMC3_DAT3 PP2"),
285 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PP3, "SDMMC3_DAT2 PP3"),
286 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PP4, "SDMMC3_DAT1 PP4"),
287 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PP5, "SDMMC3_DAT0 PP5"),
288 PINCTRL_PIN(TEGRA_PIN_CAM1_MCLK_PS0, "CAM1_MCLK PS0"),
289 PINCTRL_PIN(TEGRA_PIN_CAM2_MCLK_PS1, "CAM2_MCLK PS1"),
290 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PS2, "CAM_I2C_SCL PS2"),
291 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PS3, "CAM_I2C_SDA PS3"),
292 PINCTRL_PIN(TEGRA_PIN_CAM_RST_PS4, "CAM_RST PS4"),
293 PINCTRL_PIN(TEGRA_PIN_CAM_AF_EN_PS5, "CAM_AF_EN PS5"),
294 PINCTRL_PIN(TEGRA_PIN_CAM_FLASH_EN_PS6, "CAM_FLASH_EN PS6"),
295 PINCTRL_PIN(TEGRA_PIN_CAM1_PWDN_PS7, "CAM1_PWDN PS7"),
296 PINCTRL_PIN(TEGRA_PIN_CAM2_PWDN_PT0, "CAM2_PWDN PT0"),
297 PINCTRL_PIN(TEGRA_PIN_CAM1_STROBE_PT1, "CAM1_STROBE PT1"),
298 PINCTRL_PIN(TEGRA_PIN_UART1_TX_PU0, "UART1_TX PU0"),
299 PINCTRL_PIN(TEGRA_PIN_UART1_RX_PU1, "UART1_RX PU1"),
300 PINCTRL_PIN(TEGRA_PIN_UART1_RTS_PU2, "UART1_RTS PU2"),
301 PINCTRL_PIN(TEGRA_PIN_UART1_CTS_PU3, "UART1_CTS PU3"),
302 PINCTRL_PIN(TEGRA_PIN_LCD_BL_PWM_PV0, "LCD_BL_PWM PV0"),
303 PINCTRL_PIN(TEGRA_PIN_LCD_BL_EN_PV1, "LCD_BL_EN PV1"),
304 PINCTRL_PIN(TEGRA_PIN_LCD_RST_PV2, "LCD_RST PV2"),
305 PINCTRL_PIN(TEGRA_PIN_LCD_GPIO1_PV3, "LCD_GPIO1 PV3"),
306 PINCTRL_PIN(TEGRA_PIN_LCD_GPIO2_PV4, "LCD_GPIO2 PV4"),
307 PINCTRL_PIN(TEGRA_PIN_AP_READY_PV5, "AP_READY PV5"),
308 PINCTRL_PIN(TEGRA_PIN_TOUCH_RST_PV6, "TOUCH_RST PV6"),
309 PINCTRL_PIN(TEGRA_PIN_TOUCH_CLK_PV7, "TOUCH_CLK PV7"),
310 PINCTRL_PIN(TEGRA_PIN_MODEM_WAKE_AP_PX0, "MODEM_WAKE_AP PX0"),
311 PINCTRL_PIN(TEGRA_PIN_TOUCH_INT_PX1, "TOUCH_INT PX1"),
312 PINCTRL_PIN(TEGRA_PIN_MOTION_INT_PX2, "MOTION_INT PX2"),
313 PINCTRL_PIN(TEGRA_PIN_ALS_PROX_INT_PX3, "ALS_PROX_INT PX3"),
314 PINCTRL_PIN(TEGRA_PIN_TEMP_ALERT_PX4, "TEMP_ALERT PX4"),
315 PINCTRL_PIN(TEGRA_PIN_BUTTON_POWER_ON_PX5, "BUTTON_POWER_ON PX5"),
316 PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_UP_PX6, "BUTTON_VOL_UP PX6"),
317 PINCTRL_PIN(TEGRA_PIN_BUTTON_VOL_DOWN_PX7, "BUTTON_VOL_DOWN PX7"),
318 PINCTRL_PIN(TEGRA_PIN_BUTTON_SLIDE_SW_PY0, "BUTTON_SLIDE_SW PY0"),
319 PINCTRL_PIN(TEGRA_PIN_BUTTON_HOME_PY1, "BUTTON_HOME PY1"),
320 PINCTRL_PIN(TEGRA_PIN_LCD_TE_PY2, "LCD_TE PY2"),
321 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PY3, "PWR_I2C_SCL PY3"),
322 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PY4, "PWR_I2C_SDA PY4"),
323 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PY5, "CLK_32K_OUT PY5"),
324 PINCTRL_PIN(TEGRA_PIN_PZ0, "PZ0"),
325 PINCTRL_PIN(TEGRA_PIN_PZ1, "PZ1"),
326 PINCTRL_PIN(TEGRA_PIN_PZ2, "PZ2"),
327 PINCTRL_PIN(TEGRA_PIN_PZ3, "PZ3"),
328 PINCTRL_PIN(TEGRA_PIN_PZ4, "PZ4"),
329 PINCTRL_PIN(TEGRA_PIN_PZ5, "PZ5"),
330 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PAA0, "DAP2_FS PAA0"),
331 PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PAA1, "DAP2_SCLK PAA1"),
332 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PAA2, "DAP2_DIN PAA2"),
333 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PAA3, "DAP2_DOUT PAA3"),
334 PINCTRL_PIN(TEGRA_PIN_AUD_MCLK_PBB0, "AUD_MCLK PBB0"),
335 PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PBB1, "DVFS_PWM PBB1"),
336 PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PBB2, "DVFS_CLK PBB2"),
337 PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PBB3, "GPIO_X1_AUD PBB3"),
338 PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PBB4, "GPIO_X3_AUD PBB4"),
339 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PCC0, "HDMI_CEC PCC0"),
340 PINCTRL_PIN(TEGRA_PIN_HDMI_INT_DP_HPD_PCC1, "HDMI_INT_DP_HPD PCC1"),
341 PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PCC2, "SPDIF_OUT PCC2"),
342 PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PCC3, "SPDIF_IN PCC3"),
343 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PCC4, "USB_VBUS_EN0 PCC4"),
344 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PCC5, "USB_VBUS_EN1 PCC5"),
345 PINCTRL_PIN(TEGRA_PIN_DP_HPD0_PCC6, "DP_HPD0 PCC6"),
346 PINCTRL_PIN(TEGRA_PIN_PCC7, "PCC7"),
347 PINCTRL_PIN(TEGRA_PIN_SPI2_CS1_PDD0, "SPI2_CS1 PDD0"),
348 PINCTRL_PIN(TEGRA_PIN_QSPI_SCK_PEE0, "QSPI_SCK PEE0"),
349 PINCTRL_PIN(TEGRA_PIN_QSPI_CS_N_PEE1, "QSPI_CS_N PEE1"),
350 PINCTRL_PIN(TEGRA_PIN_QSPI_IO0_PEE2, "QSPI_IO0 PEE2"),
351 PINCTRL_PIN(TEGRA_PIN_QSPI_IO1_PEE3, "QSPI_IO1 PEE3"),
352 PINCTRL_PIN(TEGRA_PIN_QSPI_IO2_PEE4, "QSPI_IO2 PEE4"),
353 PINCTRL_PIN(TEGRA_PIN_QSPI_IO3_PEE5, "QSPI_IO3 PEE5"),
354 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
355 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
356 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
357 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
358 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
359 PINCTRL_PIN(TEGRA_PIN_BATT_BCL, "BATT_BCL"),
360 PINCTRL_PIN(TEGRA_PIN_CLK_REQ, "CLK_REQ"),
361 PINCTRL_PIN(TEGRA_PIN_SHUTDOWN, "SHUTDOWN"),
362};
363
364static const unsigned pex_l0_rst_n_pa0_pins[] = {
365 TEGRA_PIN_PEX_L0_RST_N_PA0,
366};
367
368static const unsigned pex_l0_clkreq_n_pa1_pins[] = {
369 TEGRA_PIN_PEX_L0_CLKREQ_N_PA1,
370};
371
372static const unsigned pex_wake_n_pa2_pins[] = {
373 TEGRA_PIN_PEX_WAKE_N_PA2,
374};
375
376static const unsigned pex_l1_rst_n_pa3_pins[] = {
377 TEGRA_PIN_PEX_L1_RST_N_PA3,
378};
379
380static const unsigned pex_l1_clkreq_n_pa4_pins[] = {
381 TEGRA_PIN_PEX_L1_CLKREQ_N_PA4,
382};
383
384static const unsigned sata_led_active_pa5_pins[] = {
385 TEGRA_PIN_SATA_LED_ACTIVE_PA5,
386};
387
388static const unsigned pa6_pins[] = {
389 TEGRA_PIN_PA6,
390};
391
392static const unsigned dap1_fs_pb0_pins[] = {
393 TEGRA_PIN_DAP1_FS_PB0,
394};
395
396static const unsigned dap1_din_pb1_pins[] = {
397 TEGRA_PIN_DAP1_DIN_PB1,
398};
399
400static const unsigned dap1_dout_pb2_pins[] = {
401 TEGRA_PIN_DAP1_DOUT_PB2,
402};
403
404static const unsigned dap1_sclk_pb3_pins[] = {
405 TEGRA_PIN_DAP1_SCLK_PB3,
406};
407
408static const unsigned spi2_mosi_pb4_pins[] = {
409 TEGRA_PIN_SPI2_MOSI_PB4,
410};
411
412static const unsigned spi2_miso_pb5_pins[] = {
413 TEGRA_PIN_SPI2_MISO_PB5,
414};
415
416static const unsigned spi2_sck_pb6_pins[] = {
417 TEGRA_PIN_SPI2_SCK_PB6,
418};
419
420static const unsigned spi2_cs0_pb7_pins[] = {
421 TEGRA_PIN_SPI2_CS0_PB7,
422};
423
424static const unsigned spi1_mosi_pc0_pins[] = {
425 TEGRA_PIN_SPI1_MOSI_PC0,
426};
427
428static const unsigned spi1_miso_pc1_pins[] = {
429 TEGRA_PIN_SPI1_MISO_PC1,
430};
431
432static const unsigned spi1_sck_pc2_pins[] = {
433 TEGRA_PIN_SPI1_SCK_PC2,
434};
435
436static const unsigned spi1_cs0_pc3_pins[] = {
437 TEGRA_PIN_SPI1_CS0_PC3,
438};
439
440static const unsigned spi1_cs1_pc4_pins[] = {
441 TEGRA_PIN_SPI1_CS1_PC4,
442};
443
444static const unsigned spi4_sck_pc5_pins[] = {
445 TEGRA_PIN_SPI4_SCK_PC5,
446};
447
448static const unsigned spi4_cs0_pc6_pins[] = {
449 TEGRA_PIN_SPI4_CS0_PC6,
450};
451
452static const unsigned spi4_mosi_pc7_pins[] = {
453 TEGRA_PIN_SPI4_MOSI_PC7,
454};
455
456static const unsigned spi4_miso_pd0_pins[] = {
457 TEGRA_PIN_SPI4_MISO_PD0,
458};
459
460static const unsigned uart3_tx_pd1_pins[] = {
461 TEGRA_PIN_UART3_TX_PD1,
462};
463
464static const unsigned uart3_rx_pd2_pins[] = {
465 TEGRA_PIN_UART3_RX_PD2,
466};
467
468static const unsigned uart3_rts_pd3_pins[] = {
469 TEGRA_PIN_UART3_RTS_PD3,
470};
471
472static const unsigned uart3_cts_pd4_pins[] = {
473 TEGRA_PIN_UART3_CTS_PD4,
474};
475
476static const unsigned dmic1_clk_pe0_pins[] = {
477 TEGRA_PIN_DMIC1_CLK_PE0,
478};
479
480static const unsigned dmic1_dat_pe1_pins[] = {
481 TEGRA_PIN_DMIC1_DAT_PE1,
482};
483
484static const unsigned dmic2_clk_pe2_pins[] = {
485 TEGRA_PIN_DMIC2_CLK_PE2,
486};
487
488static const unsigned dmic2_dat_pe3_pins[] = {
489 TEGRA_PIN_DMIC2_DAT_PE3,
490};
491
492static const unsigned dmic3_clk_pe4_pins[] = {
493 TEGRA_PIN_DMIC3_CLK_PE4,
494};
495
496static const unsigned dmic3_dat_pe5_pins[] = {
497 TEGRA_PIN_DMIC3_DAT_PE5,
498};
499
500static const unsigned pe6_pins[] = {
501 TEGRA_PIN_PE6,
502};
503
504static const unsigned pe7_pins[] = {
505 TEGRA_PIN_PE7,
506};
507
508static const unsigned gen3_i2c_scl_pf0_pins[] = {
509 TEGRA_PIN_GEN3_I2C_SCL_PF0,
510};
511
512static const unsigned gen3_i2c_sda_pf1_pins[] = {
513 TEGRA_PIN_GEN3_I2C_SDA_PF1,
514};
515
516static const unsigned uart2_tx_pg0_pins[] = {
517 TEGRA_PIN_UART2_TX_PG0,
518};
519
520static const unsigned uart2_rx_pg1_pins[] = {
521 TEGRA_PIN_UART2_RX_PG1,
522};
523
524static const unsigned uart2_rts_pg2_pins[] = {
525 TEGRA_PIN_UART2_RTS_PG2,
526};
527
528static const unsigned uart2_cts_pg3_pins[] = {
529 TEGRA_PIN_UART2_CTS_PG3,
530};
531
532static const unsigned wifi_en_ph0_pins[] = {
533 TEGRA_PIN_WIFI_EN_PH0,
534};
535
536static const unsigned wifi_rst_ph1_pins[] = {
537 TEGRA_PIN_WIFI_RST_PH1,
538};
539
540static const unsigned wifi_wake_ap_ph2_pins[] = {
541 TEGRA_PIN_WIFI_WAKE_AP_PH2,
542};
543
544static const unsigned ap_wake_bt_ph3_pins[] = {
545 TEGRA_PIN_AP_WAKE_BT_PH3,
546};
547
548static const unsigned bt_rst_ph4_pins[] = {
549 TEGRA_PIN_BT_RST_PH4,
550};
551
552static const unsigned bt_wake_ap_ph5_pins[] = {
553 TEGRA_PIN_BT_WAKE_AP_PH5,
554};
555
556static const unsigned ph6_pins[] = {
557 TEGRA_PIN_PH6,
558};
559
560static const unsigned ap_wake_nfc_ph7_pins[] = {
561 TEGRA_PIN_AP_WAKE_NFC_PH7,
562};
563
564static const unsigned nfc_en_pi0_pins[] = {
565 TEGRA_PIN_NFC_EN_PI0,
566};
567
568static const unsigned nfc_int_pi1_pins[] = {
569 TEGRA_PIN_NFC_INT_PI1,
570};
571
572static const unsigned gps_en_pi2_pins[] = {
573 TEGRA_PIN_GPS_EN_PI2,
574};
575
576static const unsigned gps_rst_pi3_pins[] = {
577 TEGRA_PIN_GPS_RST_PI3,
578};
579
580static const unsigned uart4_tx_pi4_pins[] = {
581 TEGRA_PIN_UART4_TX_PI4,
582};
583
584static const unsigned uart4_rx_pi5_pins[] = {
585 TEGRA_PIN_UART4_RX_PI5,
586};
587
588static const unsigned uart4_rts_pi6_pins[] = {
589 TEGRA_PIN_UART4_RTS_PI6,
590};
591
592static const unsigned uart4_cts_pi7_pins[] = {
593 TEGRA_PIN_UART4_CTS_PI7,
594};
595
596static const unsigned gen1_i2c_sda_pj0_pins[] = {
597 TEGRA_PIN_GEN1_I2C_SDA_PJ0,
598};
599
600static const unsigned gen1_i2c_scl_pj1_pins[] = {
601 TEGRA_PIN_GEN1_I2C_SCL_PJ1,
602};
603
604static const unsigned gen2_i2c_scl_pj2_pins[] = {
605 TEGRA_PIN_GEN2_I2C_SCL_PJ2,
606};
607
608static const unsigned gen2_i2c_sda_pj3_pins[] = {
609 TEGRA_PIN_GEN2_I2C_SDA_PJ3,
610};
611
612static const unsigned dap4_fs_pj4_pins[] = {
613 TEGRA_PIN_DAP4_FS_PJ4,
614};
615
616static const unsigned dap4_din_pj5_pins[] = {
617 TEGRA_PIN_DAP4_DIN_PJ5,
618};
619
620static const unsigned dap4_dout_pj6_pins[] = {
621 TEGRA_PIN_DAP4_DOUT_PJ6,
622};
623
624static const unsigned dap4_sclk_pj7_pins[] = {
625 TEGRA_PIN_DAP4_SCLK_PJ7,
626};
627
628static const unsigned pk0_pins[] = {
629 TEGRA_PIN_PK0,
630};
631
632static const unsigned pk1_pins[] = {
633 TEGRA_PIN_PK1,
634};
635
636static const unsigned pk2_pins[] = {
637 TEGRA_PIN_PK2,
638};
639
640static const unsigned pk3_pins[] = {
641 TEGRA_PIN_PK3,
642};
643
644static const unsigned pk4_pins[] = {
645 TEGRA_PIN_PK4,
646};
647
648static const unsigned pk5_pins[] = {
649 TEGRA_PIN_PK5,
650};
651
652static const unsigned pk6_pins[] = {
653 TEGRA_PIN_PK6,
654};
655
656static const unsigned pk7_pins[] = {
657 TEGRA_PIN_PK7,
658};
659
660static const unsigned pl0_pins[] = {
661 TEGRA_PIN_PL0,
662};
663
664static const unsigned pl1_pins[] = {
665 TEGRA_PIN_PL1,
666};
667
668static const unsigned sdmmc1_clk_pm0_pins[] = {
669 TEGRA_PIN_SDMMC1_CLK_PM0,
670};
671
672static const unsigned sdmmc1_cmd_pm1_pins[] = {
673 TEGRA_PIN_SDMMC1_CMD_PM1,
674};
675
676static const unsigned sdmmc1_dat3_pm2_pins[] = {
677 TEGRA_PIN_SDMMC1_DAT3_PM2,
678};
679
680static const unsigned sdmmc1_dat2_pm3_pins[] = {
681 TEGRA_PIN_SDMMC1_DAT2_PM3,
682};
683
684static const unsigned sdmmc1_dat1_pm4_pins[] = {
685 TEGRA_PIN_SDMMC1_DAT1_PM4,
686};
687
688static const unsigned sdmmc1_dat0_pm5_pins[] = {
689 TEGRA_PIN_SDMMC1_DAT0_PM5,
690};
691
692static const unsigned sdmmc3_clk_pp0_pins[] = {
693 TEGRA_PIN_SDMMC3_CLK_PP0,
694};
695
696static const unsigned sdmmc3_cmd_pp1_pins[] = {
697 TEGRA_PIN_SDMMC3_CMD_PP1,
698};
699
700static const unsigned sdmmc3_dat3_pp2_pins[] = {
701 TEGRA_PIN_SDMMC3_DAT3_PP2,
702};
703
704static const unsigned sdmmc3_dat2_pp3_pins[] = {
705 TEGRA_PIN_SDMMC3_DAT2_PP3,
706};
707
708static const unsigned sdmmc3_dat1_pp4_pins[] = {
709 TEGRA_PIN_SDMMC3_DAT1_PP4,
710};
711
712static const unsigned sdmmc3_dat0_pp5_pins[] = {
713 TEGRA_PIN_SDMMC3_DAT0_PP5,
714};
715
716static const unsigned cam1_mclk_ps0_pins[] = {
717 TEGRA_PIN_CAM1_MCLK_PS0,
718};
719
720static const unsigned cam2_mclk_ps1_pins[] = {
721 TEGRA_PIN_CAM2_MCLK_PS1,
722};
723
724static const unsigned cam_i2c_scl_ps2_pins[] = {
725 TEGRA_PIN_CAM_I2C_SCL_PS2,
726};
727
728static const unsigned cam_i2c_sda_ps3_pins[] = {
729 TEGRA_PIN_CAM_I2C_SDA_PS3,
730};
731
732static const unsigned cam_rst_ps4_pins[] = {
733 TEGRA_PIN_CAM_RST_PS4,
734};
735
736static const unsigned cam_af_en_ps5_pins[] = {
737 TEGRA_PIN_CAM_AF_EN_PS5,
738};
739
740static const unsigned cam_flash_en_ps6_pins[] = {
741 TEGRA_PIN_CAM_FLASH_EN_PS6,
742};
743
744static const unsigned cam1_pwdn_ps7_pins[] = {
745 TEGRA_PIN_CAM1_PWDN_PS7,
746};
747
748static const unsigned cam2_pwdn_pt0_pins[] = {
749 TEGRA_PIN_CAM2_PWDN_PT0,
750};
751
752static const unsigned cam1_strobe_pt1_pins[] = {
753 TEGRA_PIN_CAM1_STROBE_PT1,
754};
755
756static const unsigned uart1_tx_pu0_pins[] = {
757 TEGRA_PIN_UART1_TX_PU0,
758};
759
760static const unsigned uart1_rx_pu1_pins[] = {
761 TEGRA_PIN_UART1_RX_PU1,
762};
763
764static const unsigned uart1_rts_pu2_pins[] = {
765 TEGRA_PIN_UART1_RTS_PU2,
766};
767
768static const unsigned uart1_cts_pu3_pins[] = {
769 TEGRA_PIN_UART1_CTS_PU3,
770};
771
772static const unsigned lcd_bl_pwm_pv0_pins[] = {
773 TEGRA_PIN_LCD_BL_PWM_PV0,
774};
775
776static const unsigned lcd_bl_en_pv1_pins[] = {
777 TEGRA_PIN_LCD_BL_EN_PV1,
778};
779
780static const unsigned lcd_rst_pv2_pins[] = {
781 TEGRA_PIN_LCD_RST_PV2,
782};
783
784static const unsigned lcd_gpio1_pv3_pins[] = {
785 TEGRA_PIN_LCD_GPIO1_PV3,
786};
787
788static const unsigned lcd_gpio2_pv4_pins[] = {
789 TEGRA_PIN_LCD_GPIO2_PV4,
790};
791
792static const unsigned ap_ready_pv5_pins[] = {
793 TEGRA_PIN_AP_READY_PV5,
794};
795
796static const unsigned touch_rst_pv6_pins[] = {
797 TEGRA_PIN_TOUCH_RST_PV6,
798};
799
800static const unsigned touch_clk_pv7_pins[] = {
801 TEGRA_PIN_TOUCH_CLK_PV7,
802};
803
804static const unsigned modem_wake_ap_px0_pins[] = {
805 TEGRA_PIN_MODEM_WAKE_AP_PX0,
806};
807
808static const unsigned touch_int_px1_pins[] = {
809 TEGRA_PIN_TOUCH_INT_PX1,
810};
811
812static const unsigned motion_int_px2_pins[] = {
813 TEGRA_PIN_MOTION_INT_PX2,
814};
815
816static const unsigned als_prox_int_px3_pins[] = {
817 TEGRA_PIN_ALS_PROX_INT_PX3,
818};
819
820static const unsigned temp_alert_px4_pins[] = {
821 TEGRA_PIN_TEMP_ALERT_PX4,
822};
823
824static const unsigned button_power_on_px5_pins[] = {
825 TEGRA_PIN_BUTTON_POWER_ON_PX5,
826};
827
828static const unsigned button_vol_up_px6_pins[] = {
829 TEGRA_PIN_BUTTON_VOL_UP_PX6,
830};
831
832static const unsigned button_vol_down_px7_pins[] = {
833 TEGRA_PIN_BUTTON_VOL_DOWN_PX7,
834};
835
836static const unsigned button_slide_sw_py0_pins[] = {
837 TEGRA_PIN_BUTTON_SLIDE_SW_PY0,
838};
839
840static const unsigned button_home_py1_pins[] = {
841 TEGRA_PIN_BUTTON_HOME_PY1,
842};
843
844static const unsigned lcd_te_py2_pins[] = {
845 TEGRA_PIN_LCD_TE_PY2,
846};
847
848static const unsigned pwr_i2c_scl_py3_pins[] = {
849 TEGRA_PIN_PWR_I2C_SCL_PY3,
850};
851
852static const unsigned pwr_i2c_sda_py4_pins[] = {
853 TEGRA_PIN_PWR_I2C_SDA_PY4,
854};
855
856static const unsigned clk_32k_out_py5_pins[] = {
857 TEGRA_PIN_CLK_32K_OUT_PY5,
858};
859
860static const unsigned pz0_pins[] = {
861 TEGRA_PIN_PZ0,
862};
863
864static const unsigned pz1_pins[] = {
865 TEGRA_PIN_PZ1,
866};
867
868static const unsigned pz2_pins[] = {
869 TEGRA_PIN_PZ2,
870};
871
872static const unsigned pz3_pins[] = {
873 TEGRA_PIN_PZ3,
874};
875
876static const unsigned pz4_pins[] = {
877 TEGRA_PIN_PZ4,
878};
879
880static const unsigned pz5_pins[] = {
881 TEGRA_PIN_PZ5,
882};
883
884static const unsigned dap2_fs_paa0_pins[] = {
885 TEGRA_PIN_DAP2_FS_PAA0,
886};
887
888static const unsigned dap2_sclk_paa1_pins[] = {
889 TEGRA_PIN_DAP2_SCLK_PAA1,
890};
891
892static const unsigned dap2_din_paa2_pins[] = {
893 TEGRA_PIN_DAP2_DIN_PAA2,
894};
895
896static const unsigned dap2_dout_paa3_pins[] = {
897 TEGRA_PIN_DAP2_DOUT_PAA3,
898};
899
900static const unsigned aud_mclk_pbb0_pins[] = {
901 TEGRA_PIN_AUD_MCLK_PBB0,
902};
903
904static const unsigned dvfs_pwm_pbb1_pins[] = {
905 TEGRA_PIN_DVFS_PWM_PBB1,
906};
907
908static const unsigned dvfs_clk_pbb2_pins[] = {
909 TEGRA_PIN_DVFS_CLK_PBB2,
910};
911
912static const unsigned gpio_x1_aud_pbb3_pins[] = {
913 TEGRA_PIN_GPIO_X1_AUD_PBB3,
914};
915
916static const unsigned gpio_x3_aud_pbb4_pins[] = {
917 TEGRA_PIN_GPIO_X3_AUD_PBB4,
918};
919
920static const unsigned hdmi_cec_pcc0_pins[] = {
921 TEGRA_PIN_HDMI_CEC_PCC0,
922};
923
924static const unsigned hdmi_int_dp_hpd_pcc1_pins[] = {
925 TEGRA_PIN_HDMI_INT_DP_HPD_PCC1,
926};
927
928static const unsigned spdif_out_pcc2_pins[] = {
929 TEGRA_PIN_SPDIF_OUT_PCC2,
930};
931
932static const unsigned spdif_in_pcc3_pins[] = {
933 TEGRA_PIN_SPDIF_IN_PCC3,
934};
935
936static const unsigned usb_vbus_en0_pcc4_pins[] = {
937 TEGRA_PIN_USB_VBUS_EN0_PCC4,
938};
939
940static const unsigned usb_vbus_en1_pcc5_pins[] = {
941 TEGRA_PIN_USB_VBUS_EN1_PCC5,
942};
943
944static const unsigned dp_hpd0_pcc6_pins[] = {
945 TEGRA_PIN_DP_HPD0_PCC6,
946};
947
948static const unsigned pcc7_pins[] = {
949 TEGRA_PIN_PCC7,
950};
951
952static const unsigned spi2_cs1_pdd0_pins[] = {
953 TEGRA_PIN_SPI2_CS1_PDD0,
954};
955
956static const unsigned qspi_sck_pee0_pins[] = {
957 TEGRA_PIN_QSPI_SCK_PEE0,
958};
959
960static const unsigned qspi_cs_n_pee1_pins[] = {
961 TEGRA_PIN_QSPI_CS_N_PEE1,
962};
963
964static const unsigned qspi_io0_pee2_pins[] = {
965 TEGRA_PIN_QSPI_IO0_PEE2,
966};
967
968static const unsigned qspi_io1_pee3_pins[] = {
969 TEGRA_PIN_QSPI_IO1_PEE3,
970};
971
972static const unsigned qspi_io2_pee4_pins[] = {
973 TEGRA_PIN_QSPI_IO2_PEE4,
974};
975
976static const unsigned qspi_io3_pee5_pins[] = {
977 TEGRA_PIN_QSPI_IO3_PEE5,
978};
979
980static const unsigned core_pwr_req_pins[] = {
981 TEGRA_PIN_CORE_PWR_REQ,
982};
983
984static const unsigned cpu_pwr_req_pins[] = {
985 TEGRA_PIN_CPU_PWR_REQ,
986};
987
988static const unsigned pwr_int_n_pins[] = {
989 TEGRA_PIN_PWR_INT_N,
990};
991
992static const unsigned clk_32k_in_pins[] = {
993 TEGRA_PIN_CLK_32K_IN,
994};
995
996static const unsigned jtag_rtck_pins[] = {
997 TEGRA_PIN_JTAG_RTCK,
998};
999
1000static const unsigned batt_bcl_pins[] = {
1001 TEGRA_PIN_BATT_BCL,
1002};
1003
1004static const unsigned clk_req_pins[] = {
1005 TEGRA_PIN_CLK_REQ,
1006};
1007
1008static const unsigned shutdown_pins[] = {
1009 TEGRA_PIN_SHUTDOWN,
1010};
1011
1012static const unsigned drive_pa6_pins[] = {
1013 TEGRA_PIN_PA6,
1014};
1015
1016static const unsigned drive_pcc7_pins[] = {
1017 TEGRA_PIN_PCC7,
1018};
1019
1020static const unsigned drive_pe6_pins[] = {
1021 TEGRA_PIN_PE6,
1022};
1023
1024static const unsigned drive_pe7_pins[] = {
1025 TEGRA_PIN_PE7,
1026};
1027
1028static const unsigned drive_ph6_pins[] = {
1029 TEGRA_PIN_PH6,
1030};
1031
1032static const unsigned drive_pk0_pins[] = {
1033 TEGRA_PIN_PK0,
1034};
1035
1036static const unsigned drive_pk1_pins[] = {
1037 TEGRA_PIN_PK1,
1038};
1039
1040static const unsigned drive_pk2_pins[] = {
1041 TEGRA_PIN_PK2,
1042};
1043
1044static const unsigned drive_pk3_pins[] = {
1045 TEGRA_PIN_PK3,
1046};
1047
1048static const unsigned drive_pk4_pins[] = {
1049 TEGRA_PIN_PK4,
1050};
1051
1052static const unsigned drive_pk5_pins[] = {
1053 TEGRA_PIN_PK5,
1054};
1055
1056static const unsigned drive_pk6_pins[] = {
1057 TEGRA_PIN_PK6,
1058};
1059
1060static const unsigned drive_pk7_pins[] = {
1061 TEGRA_PIN_PK7,
1062};
1063
1064static const unsigned drive_pl0_pins[] = {
1065 TEGRA_PIN_PL0,
1066};
1067
1068static const unsigned drive_pl1_pins[] = {
1069 TEGRA_PIN_PL1,
1070};
1071
1072static const unsigned drive_pz0_pins[] = {
1073 TEGRA_PIN_PZ0,
1074};
1075
1076static const unsigned drive_pz1_pins[] = {
1077 TEGRA_PIN_PZ1,
1078};
1079
1080static const unsigned drive_pz2_pins[] = {
1081 TEGRA_PIN_PZ2,
1082};
1083
1084static const unsigned drive_pz3_pins[] = {
1085 TEGRA_PIN_PZ3,
1086};
1087
1088static const unsigned drive_pz4_pins[] = {
1089 TEGRA_PIN_PZ4,
1090};
1091
1092static const unsigned drive_pz5_pins[] = {
1093 TEGRA_PIN_PZ5,
1094};
1095
1096static const unsigned drive_sdmmc1_pins[] = {
1097 TEGRA_PIN_SDMMC1_CLK_PM0,
1098 TEGRA_PIN_SDMMC1_CMD_PM1,
1099 TEGRA_PIN_SDMMC1_DAT3_PM2,
1100 TEGRA_PIN_SDMMC1_DAT2_PM3,
1101 TEGRA_PIN_SDMMC1_DAT1_PM4,
1102 TEGRA_PIN_SDMMC1_DAT0_PM5,
1103};
1104
1105static const unsigned drive_sdmmc2_pins[] = {
1106};
1107
1108static const unsigned drive_sdmmc3_pins[] = {
1109 TEGRA_PIN_SDMMC3_CLK_PP0,
1110 TEGRA_PIN_SDMMC3_CMD_PP1,
1111 TEGRA_PIN_SDMMC3_DAT3_PP2,
1112 TEGRA_PIN_SDMMC3_DAT2_PP3,
1113 TEGRA_PIN_SDMMC3_DAT1_PP4,
1114 TEGRA_PIN_SDMMC3_DAT0_PP5,
1115};
1116
1117static const unsigned drive_sdmmc4_pins[] = {
1118};
1119
1120enum tegra_mux {
1121 TEGRA_MUX_AUD,
1122 TEGRA_MUX_BCL,
1123 TEGRA_MUX_BLINK,
1124 TEGRA_MUX_CCLA,
1125 TEGRA_MUX_CEC,
1126 TEGRA_MUX_CLDVFS,
1127 TEGRA_MUX_CLK,
1128 TEGRA_MUX_CORE,
1129 TEGRA_MUX_CPU,
1130 TEGRA_MUX_DISPLAYA,
1131 TEGRA_MUX_DISPLAYB,
1132 TEGRA_MUX_DMIC1,
1133 TEGRA_MUX_DMIC2,
1134 TEGRA_MUX_DMIC3,
1135 TEGRA_MUX_DP,
1136 TEGRA_MUX_DTV,
1137 TEGRA_MUX_EXTPERIPH3,
1138 TEGRA_MUX_I2C1,
1139 TEGRA_MUX_I2C2,
1140 TEGRA_MUX_I2C3,
1141 TEGRA_MUX_I2CPMU,
1142 TEGRA_MUX_I2CVI,
1143 TEGRA_MUX_I2S1,
1144 TEGRA_MUX_I2S2,
1145 TEGRA_MUX_I2S3,
1146 TEGRA_MUX_I2S4A,
1147 TEGRA_MUX_I2S4B,
1148 TEGRA_MUX_I2S5A,
1149 TEGRA_MUX_I2S5B,
1150 TEGRA_MUX_IQC0,
1151 TEGRA_MUX_IQC1,
1152 TEGRA_MUX_JTAG,
1153 TEGRA_MUX_PE,
1154 TEGRA_MUX_PE0,
1155 TEGRA_MUX_PE1,
1156 TEGRA_MUX_PMI,
1157 TEGRA_MUX_PWM0,
1158 TEGRA_MUX_PWM1,
1159 TEGRA_MUX_PWM2,
1160 TEGRA_MUX_PWM3,
1161 TEGRA_MUX_QSPI,
1162 TEGRA_MUX_RSVD0,
1163 TEGRA_MUX_RSVD1,
1164 TEGRA_MUX_RSVD2,
1165 TEGRA_MUX_RSVD3,
1166 TEGRA_MUX_SATA,
1167 TEGRA_MUX_SDMMC1,
1168 TEGRA_MUX_SDMMC3,
1169 TEGRA_MUX_SHUTDOWN,
1170 TEGRA_MUX_SOC,
1171 TEGRA_MUX_SOR0,
1172 TEGRA_MUX_SOR1,
1173 TEGRA_MUX_SPDIF,
1174 TEGRA_MUX_SPI1,
1175 TEGRA_MUX_SPI2,
1176 TEGRA_MUX_SPI3,
1177 TEGRA_MUX_SPI4,
1178 TEGRA_MUX_SYS,
1179 TEGRA_MUX_TOUCH,
1180 TEGRA_MUX_UART,
1181 TEGRA_MUX_UARTA,
1182 TEGRA_MUX_UARTB,
1183 TEGRA_MUX_UARTC,
1184 TEGRA_MUX_UARTD,
1185 TEGRA_MUX_USB,
1186 TEGRA_MUX_VGP1,
1187 TEGRA_MUX_VGP2,
1188 TEGRA_MUX_VGP3,
1189 TEGRA_MUX_VGP4,
1190 TEGRA_MUX_VGP5,
1191 TEGRA_MUX_VGP6,
1192 TEGRA_MUX_VIMCLK,
1193 TEGRA_MUX_VIMCLK2,
1194};
1195
1196#define FUNCTION(fname) \
1197 { \
1198 .name = #fname, \
1199 }
1200
1201static struct tegra_function tegra210_functions[] = {
1202 FUNCTION(aud),
1203 FUNCTION(bcl),
1204 FUNCTION(blink),
1205 FUNCTION(ccla),
1206 FUNCTION(cec),
1207 FUNCTION(cldvfs),
1208 FUNCTION(clk),
1209 FUNCTION(core),
1210 FUNCTION(cpu),
1211 FUNCTION(displaya),
1212 FUNCTION(displayb),
1213 FUNCTION(dmic1),
1214 FUNCTION(dmic2),
1215 FUNCTION(dmic3),
1216 FUNCTION(dp),
1217 FUNCTION(dtv),
1218 FUNCTION(extperiph3),
1219 FUNCTION(i2c1),
1220 FUNCTION(i2c2),
1221 FUNCTION(i2c3),
1222 FUNCTION(i2cpmu),
1223 FUNCTION(i2cvi),
1224 FUNCTION(i2s1),
1225 FUNCTION(i2s2),
1226 FUNCTION(i2s3),
1227 FUNCTION(i2s4a),
1228 FUNCTION(i2s4b),
1229 FUNCTION(i2s5a),
1230 FUNCTION(i2s5b),
1231 FUNCTION(iqc0),
1232 FUNCTION(iqc1),
1233 FUNCTION(jtag),
1234 FUNCTION(pe),
1235 FUNCTION(pe0),
1236 FUNCTION(pe1),
1237 FUNCTION(pmi),
1238 FUNCTION(pwm0),
1239 FUNCTION(pwm1),
1240 FUNCTION(pwm2),
1241 FUNCTION(pwm3),
1242 FUNCTION(qspi),
1243 FUNCTION(rsvd0),
1244 FUNCTION(rsvd1),
1245 FUNCTION(rsvd2),
1246 FUNCTION(rsvd3),
1247 FUNCTION(sata),
1248 FUNCTION(sdmmc1),
1249 FUNCTION(sdmmc3),
1250 FUNCTION(shutdown),
1251 FUNCTION(soc),
1252 FUNCTION(sor0),
1253 FUNCTION(sor1),
1254 FUNCTION(spdif),
1255 FUNCTION(spi1),
1256 FUNCTION(spi2),
1257 FUNCTION(spi3),
1258 FUNCTION(spi4),
1259 FUNCTION(sys),
1260 FUNCTION(touch),
1261 FUNCTION(uart),
1262 FUNCTION(uarta),
1263 FUNCTION(uartb),
1264 FUNCTION(uartc),
1265 FUNCTION(uartd),
1266 FUNCTION(usb),
1267 FUNCTION(vgp1),
1268 FUNCTION(vgp2),
1269 FUNCTION(vgp3),
1270 FUNCTION(vgp4),
1271 FUNCTION(vgp5),
1272 FUNCTION(vgp6),
1273 FUNCTION(vimclk),
1274 FUNCTION(vimclk2),
1275};
1276
1277#define DRV_PINGROUP_REG_A 0x8d4 /* bank 0 */
1278#define PINGROUP_REG_A 0x3000 /* bank 1 */
1279
1280#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
1281#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
1282
1283#define PINGROUP_BIT_Y(b) (b)
1284#define PINGROUP_BIT_N(b) (-1)
1285
1286#define PINGROUP(pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, \
1287 rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, \
1288 slwr_w, slwf_b, slwf_w) \
1289 { \
1290 .name = #pg_name, \
1291 .pins = pg_name##_pins, \
1292 .npins = ARRAY_SIZE(pg_name##_pins), \
1293 .funcs = { \
1294 TEGRA_MUX_##f0, \
1295 TEGRA_MUX_##f1, \
1296 TEGRA_MUX_##f2, \
1297 TEGRA_MUX_##f3, \
1298 }, \
1299 .mux_reg = PINGROUP_REG(r), \
1300 .mux_bank = 1, \
1301 .mux_bit = 0, \
1302 .pupd_reg = PINGROUP_REG(r), \
1303 .pupd_bank = 1, \
1304 .pupd_bit = 2, \
1305 .tri_reg = PINGROUP_REG(r), \
1306 .tri_bank = 1, \
1307 .tri_bit = 4, \
1308 .einput_bit = 6, \
1309 .odrain_bit = 11, \
1310 .lock_bit = 7, \
1311 .ioreset_bit = -1, \
1312 .rcv_sel_bit = PINGROUP_BIT_##e_io_hv(10), \
1313 .hsm_bit = PINGROUP_BIT_##hsm(9), \
1314 .schmitt_bit = 12, \
1315 .drvtype_bit = PINGROUP_BIT_##drvtype(13), \
1316 .drv_reg = DRV_PINGROUP_REG(rdrv), \
1317 .drv_bank = 0, \
1318 .lpmd_bit = -1, \
1319 .drvdn_bit = drvdn_b, \
1320 .drvdn_width = drvdn_w, \
1321 .drvup_bit = drvup_b, \
1322 .drvup_width = drvup_w, \
1323 .slwr_bit = slwr_b, \
1324 .slwr_width = slwr_w, \
1325 .slwf_bit = slwf_b, \
1326 .slwf_width = slwf_w, \
1327 }
1328
1329#define DRV_PINGROUP(pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, \
1330 slwr_b, slwr_w, slwf_b, slwf_w) \
1331 { \
1332 .name = "drive_" #pg_name, \
1333 .pins = drive_##pg_name##_pins, \
1334 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
1335 .mux_reg = -1, \
1336 .pupd_reg = -1, \
1337 .tri_reg = -1, \
1338 .einput_bit = -1, \
1339 .odrain_bit = -1, \
1340 .lock_bit = -1, \
1341 .ioreset_bit = -1, \
1342 .rcv_sel_bit = -1, \
1343 .drv_reg = DRV_PINGROUP_REG(r), \
1344 .drv_bank = 0, \
1345 .hsm_bit = -1, \
1346 .schmitt_bit = -1, \
1347 .lpmd_bit = -1, \
1348 .drvdn_bit = drvdn_b, \
1349 .drvdn_width = drvdn_w, \
1350 .drvup_bit = drvup_b, \
1351 .drvup_width = drvup_w, \
1352 .slwr_bit = slwr_b, \
1353 .slwr_width = slwr_w, \
1354 .slwf_bit = slwf_b, \
1355 .slwf_width = slwf_w, \
1356 .drvtype_bit = -1, \
1357 }
1358
1359static const struct tegra_pingroup tegra210_groups[] = {
1360 /* pg_name, f0, f1, f2, f3, r, hsm, drvtype, e_io_hv, rdrv, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
1361 PINGROUP(sdmmc1_clk_pm0, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3000, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1362 PINGROUP(sdmmc1_cmd_pm1, SDMMC1, SPI3, RSVD2, RSVD3, 0x3004, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1363 PINGROUP(sdmmc1_dat3_pm2, SDMMC1, SPI3, RSVD2, RSVD3, 0x3008, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1364 PINGROUP(sdmmc1_dat2_pm3, SDMMC1, SPI3, RSVD2, RSVD3, 0x300c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1365 PINGROUP(sdmmc1_dat1_pm4, SDMMC1, SPI3, RSVD2, RSVD3, 0x3010, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1366 PINGROUP(sdmmc1_dat0_pm5, SDMMC1, RSVD1, RSVD2, RSVD3, 0x3014, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1367 PINGROUP(sdmmc3_clk_pp0, SDMMC3, RSVD1, RSVD2, RSVD3, 0x301c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1368 PINGROUP(sdmmc3_cmd_pp1, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3020, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1369 PINGROUP(sdmmc3_dat0_pp5, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3024, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1370 PINGROUP(sdmmc3_dat1_pp4, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3028, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1371 PINGROUP(sdmmc3_dat2_pp3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x302c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1372 PINGROUP(sdmmc3_dat3_pp2, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3030, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1373 PINGROUP(pex_l0_rst_n_pa0, PE0, RSVD1, RSVD2, RSVD3, 0x3038, N, N, Y, 0xa5c, 12, 5, 20, 5, -1, -1, -1, -1),
1374 PINGROUP(pex_l0_clkreq_n_pa1, PE0, RSVD1, RSVD2, RSVD3, 0x303c, N, N, Y, 0xa58, 12, 5, 20, 5, -1, -1, -1, -1),
1375 PINGROUP(pex_wake_n_pa2, PE, RSVD1, RSVD2, RSVD3, 0x3040, N, N, Y, 0xa68, 12, 5, 20, 5, -1, -1, -1, -1),
1376 PINGROUP(pex_l1_rst_n_pa3, PE1, RSVD1, RSVD2, RSVD3, 0x3044, N, N, Y, 0xa64, 12, 5, 20, 5, -1, -1, -1, -1),
1377 PINGROUP(pex_l1_clkreq_n_pa4, PE1, RSVD1, RSVD2, RSVD3, 0x3048, N, N, Y, 0xa60, 12, 5, 20, 5, -1, -1, -1, -1),
1378 PINGROUP(sata_led_active_pa5, SATA, RSVD1, RSVD2, RSVD3, 0x304c, N, N, N, 0xa94, 12, 5, 20, 5, -1, -1, -1, -1),
1379 PINGROUP(spi1_mosi_pc0, SPI1, RSVD1, RSVD2, RSVD3, 0x3050, Y, Y, N, 0xae0, -1, -1, -1, -1, 28, 2, 30, 2),
1380 PINGROUP(spi1_miso_pc1, SPI1, RSVD1, RSVD2, RSVD3, 0x3054, Y, Y, N, 0xadc, -1, -1, -1, -1, 28, 2, 30, 2),
1381 PINGROUP(spi1_sck_pc2, SPI1, RSVD1, RSVD2, RSVD3, 0x3058, Y, Y, N, 0xae4, -1, -1, -1, -1, 28, 2, 30, 2),
1382 PINGROUP(spi1_cs0_pc3, SPI1, RSVD1, RSVD2, RSVD3, 0x305c, Y, Y, N, 0xad4, -1, -1, -1, -1, 28, 2, 30, 2),
1383 PINGROUP(spi1_cs1_pc4, SPI1, RSVD1, RSVD2, RSVD3, 0x3060, Y, Y, N, 0xad8, -1, -1, -1, -1, 28, 2, 30, 2),
1384 PINGROUP(spi2_mosi_pb4, SPI2, DTV, RSVD2, RSVD3, 0x3064, Y, Y, N, 0xaf4, -1, -1, -1, -1, 28, 2, 30, 2),
1385 PINGROUP(spi2_miso_pb5, SPI2, DTV, RSVD2, RSVD3, 0x3068, Y, Y, N, 0xaf0, -1, -1, -1, -1, 28, 2, 30, 2),
1386 PINGROUP(spi2_sck_pb6, SPI2, DTV, RSVD2, RSVD3, 0x306c, Y, Y, N, 0xaf8, -1, -1, -1, -1, 28, 2, 30, 2),
1387 PINGROUP(spi2_cs0_pb7, SPI2, DTV, RSVD2, RSVD3, 0x3070, Y, Y, N, 0xae8, -1, -1, -1, -1, 28, 2, 30, 2),
1388 PINGROUP(spi2_cs1_pdd0, SPI2, RSVD1, RSVD2, RSVD3, 0x3074, Y, Y, N, 0xaec, -1, -1, -1, -1, 28, 2, 30, 2),
1389 PINGROUP(spi4_mosi_pc7, SPI4, RSVD1, RSVD2, RSVD3, 0x3078, Y, Y, N, 0xb04, -1, -1, -1, -1, 28, 2, 30, 2),
1390 PINGROUP(spi4_miso_pd0, SPI4, RSVD1, RSVD2, RSVD3, 0x307c, Y, Y, N, 0xb00, -1, -1, -1, -1, 28, 2, 30, 2),
1391 PINGROUP(spi4_sck_pc5, SPI4, RSVD1, RSVD2, RSVD3, 0x3080, Y, Y, N, 0xb08, -1, -1, -1, -1, 28, 2, 30, 2),
1392 PINGROUP(spi4_cs0_pc6, SPI4, RSVD1, RSVD2, RSVD3, 0x3084, Y, Y, N, 0xafc, -1, -1, -1, -1, 28, 2, 30, 2),
1393 PINGROUP(qspi_sck_pee0, QSPI, RSVD1, RSVD2, RSVD3, 0x3088, Y, Y, N, 0xa90, -1, -1, -1, -1, 28, 2, 30, 2),
1394 PINGROUP(qspi_cs_n_pee1, QSPI, RSVD1, RSVD2, RSVD3, 0x308c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1395 PINGROUP(qspi_io0_pee2, QSPI, RSVD1, RSVD2, RSVD3, 0x3090, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1396 PINGROUP(qspi_io1_pee3, QSPI, RSVD1, RSVD2, RSVD3, 0x3094, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1397 PINGROUP(qspi_io2_pee4, QSPI, RSVD1, RSVD2, RSVD3, 0x3098, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1398 PINGROUP(qspi_io3_pee5, QSPI, RSVD1, RSVD2, RSVD3, 0x309c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1399 PINGROUP(dmic1_clk_pe0, DMIC1, I2S3, RSVD2, RSVD3, 0x30a4, N, N, N, 0x984, 12, 5, 20, 5, -1, -1, -1, -1),
1400 PINGROUP(dmic1_dat_pe1, DMIC1, I2S3, RSVD2, RSVD3, 0x30a8, N, N, N, 0x988, 12, 5, 20, 5, -1, -1, -1, -1),
1401 PINGROUP(dmic2_clk_pe2, DMIC2, I2S3, RSVD2, RSVD3, 0x30ac, N, N, N, 0x98c, 12, 5, 20, 5, -1, -1, -1, -1),
1402 PINGROUP(dmic2_dat_pe3, DMIC2, I2S3, RSVD2, RSVD3, 0x30b0, N, N, N, 0x990, 12, 5, 20, 5, -1, -1, -1, -1),
1403 PINGROUP(dmic3_clk_pe4, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b4, N, N, N, 0x994, 12, 5, 20, 5, -1, -1, -1, -1),
1404 PINGROUP(dmic3_dat_pe5, DMIC3, I2S5A, RSVD2, RSVD3, 0x30b8, N, N, N, 0x998, 12, 5, 20, 5, -1, -1, -1, -1),
1405 PINGROUP(gen1_i2c_scl_pj1, I2C1, RSVD1, RSVD2, RSVD3, 0x30bc, N, N, Y, 0x9a8, 12, 5, 20, 5, -1, -1, -1, -1),
1406 PINGROUP(gen1_i2c_sda_pj0, I2C1, RSVD1, RSVD2, RSVD3, 0x30c0, N, N, Y, 0x9ac, 12, 5, 20, 5, -1, -1, -1, -1),
1407 PINGROUP(gen2_i2c_scl_pj2, I2C2, RSVD1, RSVD2, RSVD3, 0x30c4, N, N, Y, 0x9b0, 12, 5, 20, 5, -1, -1, -1, -1),
1408 PINGROUP(gen2_i2c_sda_pj3, I2C2, RSVD1, RSVD2, RSVD3, 0x30c8, N, N, Y, 0x9b4, 12, 5, 20, 5, -1, -1, -1, -1),
1409 PINGROUP(gen3_i2c_scl_pf0, I2C3, RSVD1, RSVD2, RSVD3, 0x30cc, N, N, Y, 0x9b8, 12, 5, 20, 5, -1, -1, -1, -1),
1410 PINGROUP(gen3_i2c_sda_pf1, I2C3, RSVD1, RSVD2, RSVD3, 0x30d0, N, N, Y, 0x9bc, 12, 5, 20, 5, -1, -1, -1, -1),
1411 PINGROUP(cam_i2c_scl_ps2, I2C3, I2CVI, RSVD2, RSVD3, 0x30d4, N, N, Y, 0x934, 12, 5, 20, 5, -1, -1, -1, -1),
1412 PINGROUP(cam_i2c_sda_ps3, I2C3, I2CVI, RSVD2, RSVD3, 0x30d8, N, N, Y, 0x938, 12, 5, 20, 5, -1, -1, -1, -1),
1413 PINGROUP(pwr_i2c_scl_py3, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30dc, N, N, Y, 0xa6c, 12, 5, 20, 5, -1, -1, -1, -1),
1414 PINGROUP(pwr_i2c_sda_py4, I2CPMU, RSVD1, RSVD2, RSVD3, 0x30e0, N, N, Y, 0xa70, 12, 5, 20, 5, -1, -1, -1, -1),
1415 PINGROUP(uart1_tx_pu0, UARTA, RSVD1, RSVD2, RSVD3, 0x30e4, N, N, N, 0xb28, 12, 5, 20, 5, -1, -1, -1, -1),
1416 PINGROUP(uart1_rx_pu1, UARTA, RSVD1, RSVD2, RSVD3, 0x30e8, N, N, N, 0xb24, 12, 5, 20, 5, -1, -1, -1, -1),
1417 PINGROUP(uart1_rts_pu2, UARTA, RSVD1, RSVD2, RSVD3, 0x30ec, N, N, N, 0xb20, 12, 5, 20, 5, -1, -1, -1, -1),
1418 PINGROUP(uart1_cts_pu3, UARTA, RSVD1, RSVD2, RSVD3, 0x30f0, N, N, N, 0xb1c, 12, 5, 20, 5, -1, -1, -1, -1),
1419 PINGROUP(uart2_tx_pg0, UARTB, I2S4A, SPDIF, UART, 0x30f4, N, N, N, 0xb38, 12, 5, 20, 5, -1, -1, -1, -1),
1420 PINGROUP(uart2_rx_pg1, UARTB, I2S4A, SPDIF, UART, 0x30f8, N, N, N, 0xb34, 12, 5, 20, 5, -1, -1, -1, -1),
1421 PINGROUP(uart2_rts_pg2, UARTB, I2S4A, RSVD2, UART, 0x30fc, N, N, N, 0xb30, 12, 5, 20, 5, -1, -1, -1, -1),
1422 PINGROUP(uart2_cts_pg3, UARTB, I2S4A, RSVD2, UART, 0x3100, N, N, N, 0xb2c, 12, 5, 20, 5, -1, -1, -1, -1),
1423 PINGROUP(uart3_tx_pd1, UARTC, SPI4, RSVD2, RSVD3, 0x3104, N, N, N, 0xb48, 12, 5, 20, 5, -1, -1, -1, -1),
1424 PINGROUP(uart3_rx_pd2, UARTC, SPI4, RSVD2, RSVD3, 0x3108, N, N, N, 0xb44, 12, 5, 20, 5, -1, -1, -1, -1),
1425 PINGROUP(uart3_rts_pd3, UARTC, SPI4, RSVD2, RSVD3, 0x310c, N, N, N, 0xb40, 12, 5, 20, 5, -1, -1, -1, -1),
1426 PINGROUP(uart3_cts_pd4, UARTC, SPI4, RSVD2, RSVD3, 0x3110, N, N, N, 0xb3c, 12, 5, 20, 5, -1, -1, -1, -1),
1427 PINGROUP(uart4_tx_pi4, UARTD, UART, RSVD2, RSVD3, 0x3114, N, N, N, 0xb58, 12, 5, 20, 5, -1, -1, -1, -1),
1428 PINGROUP(uart4_rx_pi5, UARTD, UART, RSVD2, RSVD3, 0x3118, N, N, N, 0xb54, 12, 5, 20, 5, -1, -1, -1, -1),
1429 PINGROUP(uart4_rts_pi6, UARTD, UART, RSVD2, RSVD3, 0x311c, N, N, N, 0xb50, 12, 5, 20, 5, -1, -1, -1, -1),
1430 PINGROUP(uart4_cts_pi7, UARTD, UART, RSVD2, RSVD3, 0x3120, N, N, N, 0xb4c, 12, 5, 20, 5, -1, -1, -1, -1),
1431 PINGROUP(dap1_fs_pb0, I2S1, RSVD1, RSVD2, RSVD3, 0x3124, Y, Y, N, 0x95c, -1, -1, -1, -1, 28, 2, 30, 2),
1432 PINGROUP(dap1_din_pb1, I2S1, RSVD1, RSVD2, RSVD3, 0x3128, Y, Y, N, 0x954, -1, -1, -1, -1, 28, 2, 30, 2),
1433 PINGROUP(dap1_dout_pb2, I2S1, RSVD1, RSVD2, RSVD3, 0x312c, Y, Y, N, 0x958, -1, -1, -1, -1, 28, 2, 30, 2),
1434 PINGROUP(dap1_sclk_pb3, I2S1, RSVD1, RSVD2, RSVD3, 0x3130, Y, Y, N, 0x960, -1, -1, -1, -1, 28, 2, 30, 2),
1435 PINGROUP(dap2_fs_paa0, I2S2, RSVD1, RSVD2, RSVD3, 0x3134, Y, Y, N, 0x96c, -1, -1, -1, -1, 28, 2, 30, 2),
1436 PINGROUP(dap2_din_paa2, I2S2, RSVD1, RSVD2, RSVD3, 0x3138, Y, Y, N, 0x964, -1, -1, -1, -1, 28, 2, 30, 2),
1437 PINGROUP(dap2_dout_paa3, I2S2, RSVD1, RSVD2, RSVD3, 0x313c, Y, Y, N, 0x968, -1, -1, -1, -1, 28, 2, 30, 2),
1438 PINGROUP(dap2_sclk_paa1, I2S2, RSVD1, RSVD2, RSVD3, 0x3140, Y, Y, N, 0x970, -1, -1, -1, -1, 28, 2, 30, 2),
1439 PINGROUP(dap4_fs_pj4, I2S4B, RSVD1, RSVD2, RSVD3, 0x3144, N, N, N, 0x97c, 12, 5, 20, 5, -1, -1, -1, -1),
1440 PINGROUP(dap4_din_pj5, I2S4B, RSVD1, RSVD2, RSVD3, 0x3148, N, N, N, 0x974, 12, 5, 20, 5, -1, -1, -1, -1),
1441 PINGROUP(dap4_dout_pj6, I2S4B, RSVD1, RSVD2, RSVD3, 0x314c, N, N, N, 0x978, 12, 5, 20, 5, -1, -1, -1, -1),
1442 PINGROUP(dap4_sclk_pj7, I2S4B, RSVD1, RSVD2, RSVD3, 0x3150, N, N, N, 0x980, 12, 5, 20, 5, -1, -1, -1, -1),
1443 PINGROUP(cam1_mclk_ps0, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3154, N, N, N, 0x918, 12, 5, 20, 5, -1, -1, -1, -1),
1444 PINGROUP(cam2_mclk_ps1, EXTPERIPH3, RSVD1, RSVD2, RSVD3, 0x3158, N, N, N, 0x924, 12, 5, 20, 5, -1, -1, -1, -1),
1445 PINGROUP(jtag_rtck, JTAG, RSVD1, RSVD2, RSVD3, 0x315c, N, N, N, 0xa2c, 12, 5, 20, 5, -1, -1, -1, -1),
1446 PINGROUP(clk_32k_in, CLK, RSVD1, RSVD2, RSVD3, 0x3160, N, N, N, 0x940, 12, 5, 20, 5, -1, -1, -1, -1),
1447 PINGROUP(clk_32k_out_py5, SOC, BLINK, RSVD2, RSVD3, 0x3164, N, N, N, 0x944, 12, 5, 20, 5, -1, -1, -1, -1),
1448 PINGROUP(batt_bcl, BCL, RSVD1, RSVD2, RSVD3, 0x3168, N, N, Y, 0x8f8, 12, 5, 20, 5, -1, -1, -1, -1),
1449 PINGROUP(clk_req, SYS, RSVD1, RSVD2, RSVD3, 0x316c, N, N, N, 0x948, 12, 5, 20, 5, -1, -1, -1, -1),
1450 PINGROUP(cpu_pwr_req, CPU, RSVD1, RSVD2, RSVD3, 0x3170, N, N, N, 0x950, 12, 5, 20, 5, -1, -1, -1, -1),
1451 PINGROUP(pwr_int_n, PMI, RSVD1, RSVD2, RSVD3, 0x3174, N, N, N, 0xa74, 12, 5, 20, 5, -1, -1, -1, -1),
1452 PINGROUP(shutdown, SHUTDOWN, RSVD1, RSVD2, RSVD3, 0x3178, N, N, N, 0xac8, 12, 5, 20, 5, -1, -1, -1, -1),
1453 PINGROUP(core_pwr_req, CORE, RSVD1, RSVD2, RSVD3, 0x317c, N, N, N, 0x94c, 12, 5, 20, 5, -1, -1, -1, -1),
1454 PINGROUP(aud_mclk_pbb0, AUD, RSVD1, RSVD2, RSVD3, 0x3180, N, N, N, 0x8f4, 12, 5, 20, 5, -1, -1, -1, -1),
1455 PINGROUP(dvfs_pwm_pbb1, RSVD0, CLDVFS, SPI3, RSVD3, 0x3184, N, N, N, 0x9a4, 12, 5, 20, 5, -1, -1, -1, -1),
1456 PINGROUP(dvfs_clk_pbb2, RSVD0, CLDVFS, SPI3, RSVD3, 0x3188, N, N, N, 0x9a0, 12, 5, 20, 5, -1, -1, -1, -1),
1457 PINGROUP(gpio_x1_aud_pbb3, RSVD0, RSVD1, SPI3, RSVD3, 0x318c, N, N, N, 0xa14, 12, 5, 20, 5, -1, -1, -1, -1),
1458 PINGROUP(gpio_x3_aud_pbb4, RSVD0, RSVD1, SPI3, RSVD3, 0x3190, N, N, N, 0xa18, 12, 5, 20, 5, -1, -1, -1, -1),
1459 PINGROUP(pcc7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3194, N, N, Y, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1460 PINGROUP(hdmi_cec_pcc0, CEC, RSVD1, RSVD2, RSVD3, 0x3198, N, N, Y, 0xa24, 12, 5, 20, 5, -1, -1, -1, -1),
1461 PINGROUP(hdmi_int_dp_hpd_pcc1, DP, RSVD1, RSVD2, RSVD3, 0x319c, N, N, Y, 0xa28, 12, 5, 20, 5, -1, -1, -1, -1),
1462 PINGROUP(spdif_out_pcc2, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a0, N, N, N, 0xad0, 12, 5, 20, 5, -1, -1, -1, -1),
1463 PINGROUP(spdif_in_pcc3, SPDIF, RSVD1, RSVD2, RSVD3, 0x31a4, N, N, N, 0xacc, 12, 5, 20, 5, -1, -1, -1, -1),
1464 PINGROUP(usb_vbus_en0_pcc4, USB, RSVD1, RSVD2, RSVD3, 0x31a8, N, N, Y, 0xb5c, 12, 5, 20, 5, -1, -1, -1, -1),
1465 PINGROUP(usb_vbus_en1_pcc5, USB, RSVD1, RSVD2, RSVD3, 0x31ac, N, N, Y, 0xb60, 12, 5, 20, 5, -1, -1, -1, -1),
1466 PINGROUP(dp_hpd0_pcc6, DP, RSVD1, RSVD2, RSVD3, 0x31b0, N, N, N, 0x99c, 12, 5, 20, 5, -1, -1, -1, -1),
1467 PINGROUP(wifi_en_ph0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b4, N, N, N, 0xb64, 12, 5, 20, 5, -1, -1, -1, -1),
1468 PINGROUP(wifi_rst_ph1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31b8, N, N, N, 0xb68, 12, 5, 20, 5, -1, -1, -1, -1),
1469 PINGROUP(wifi_wake_ap_ph2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31bc, N, N, N, 0xb6c, 12, 5, 20, 5, -1, -1, -1, -1),
1470 PINGROUP(ap_wake_bt_ph3, RSVD0, UARTB, SPDIF, RSVD3, 0x31c0, N, N, N, 0x8ec, 12, 5, 20, 5, -1, -1, -1, -1),
1471 PINGROUP(bt_rst_ph4, RSVD0, UARTB, SPDIF, RSVD3, 0x31c4, N, N, N, 0x8fc, 12, 5, 20, 5, -1, -1, -1, -1),
1472 PINGROUP(bt_wake_ap_ph5, RSVD0, RSVD1, RSVD2, RSVD3, 0x31c8, N, N, N, 0x900, 12, 5, 20, 5, -1, -1, -1, -1),
1473 PINGROUP(ap_wake_nfc_ph7, RSVD0, RSVD1, RSVD2, RSVD3, 0x31cc, N, N, N, 0x8f0, 12, 5, 20, 5, -1, -1, -1, -1),
1474 PINGROUP(nfc_en_pi0, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d0, N, N, N, 0xa50, 12, 5, 20, 5, -1, -1, -1, -1),
1475 PINGROUP(nfc_int_pi1, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d4, N, N, N, 0xa54, 12, 5, 20, 5, -1, -1, -1, -1),
1476 PINGROUP(gps_en_pi2, RSVD0, RSVD1, RSVD2, RSVD3, 0x31d8, N, N, N, 0xa1c, 12, 5, 20, 5, -1, -1, -1, -1),
1477 PINGROUP(gps_rst_pi3, RSVD0, RSVD1, RSVD2, RSVD3, 0x31dc, N, N, N, 0xa20, 12, 5, 20, 5, -1, -1, -1, -1),
1478 PINGROUP(cam_rst_ps4, VGP1, RSVD1, RSVD2, RSVD3, 0x31e0, N, N, N, 0x93c, 12, 5, 20, 5, -1, -1, -1, -1),
1479 PINGROUP(cam_af_en_ps5, VIMCLK, VGP2, RSVD2, RSVD3, 0x31e4, N, N, N, 0x92c, 12, 5, 20, 5, -1, -1, -1, -1),
1480 PINGROUP(cam_flash_en_ps6, VIMCLK, VGP3, RSVD2, RSVD3, 0x31e8, N, N, N, 0x930, 12, 5, 20, 5, -1, -1, -1, -1),
1481 PINGROUP(cam1_pwdn_ps7, VGP4, RSVD1, RSVD2, RSVD3, 0x31ec, N, N, N, 0x91c, 12, 5, 20, 5, -1, -1, -1, -1),
1482 PINGROUP(cam2_pwdn_pt0, VGP5, RSVD1, RSVD2, RSVD3, 0x31f0, N, N, N, 0x928, 12, 5, 20, 5, -1, -1, -1, -1),
1483 PINGROUP(cam1_strobe_pt1, VGP6, RSVD1, RSVD2, RSVD3, 0x31f4, N, N, N, 0x920, 12, 5, 20, 5, -1, -1, -1, -1),
1484 PINGROUP(lcd_te_py2, DISPLAYA, RSVD1, RSVD2, RSVD3, 0x31f8, N, N, N, 0xa44, 12, 5, 20, 5, -1, -1, -1, -1),
1485 PINGROUP(lcd_bl_pwm_pv0, DISPLAYA, PWM0, SOR0, RSVD3, 0x31fc, N, N, N, 0xa34, 12, 5, 20, 5, -1, -1, -1, -1),
1486 PINGROUP(lcd_bl_en_pv1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3200, N, N, N, 0xa30, 12, 5, 20, 5, -1, -1, -1, -1),
1487 PINGROUP(lcd_rst_pv2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3204, N, N, N, 0xa40, 12, 5, 20, 5, -1, -1, -1, -1),
1488 PINGROUP(lcd_gpio1_pv3, DISPLAYB, RSVD1, RSVD2, RSVD3, 0x3208, N, N, N, 0xa38, 12, 5, 20, 5, -1, -1, -1, -1),
1489 PINGROUP(lcd_gpio2_pv4, DISPLAYB, PWM1, RSVD2, SOR1, 0x320c, N, N, N, 0xa3c, 12, 5, 20, 5, -1, -1, -1, -1),
1490 PINGROUP(ap_ready_pv5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3210, N, N, N, 0x8e8, 12, 5, 20, 5, -1, -1, -1, -1),
1491 PINGROUP(touch_rst_pv6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3214, N, N, N, 0xb18, 12, 5, 20, 5, -1, -1, -1, -1),
1492 PINGROUP(touch_clk_pv7, TOUCH, RSVD1, RSVD2, RSVD3, 0x3218, N, N, N, 0xb10, 12, 5, 20, 5, -1, -1, -1, -1),
1493 PINGROUP(modem_wake_ap_px0, RSVD0, RSVD1, RSVD2, RSVD3, 0x321c, N, N, N, 0xa48, 12, 5, 20, 5, -1, -1, -1, -1),
1494 PINGROUP(touch_int_px1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3220, N, N, N, 0xb14, 12, 5, 20, 5, -1, -1, -1, -1),
1495 PINGROUP(motion_int_px2, RSVD0, RSVD1, RSVD2, RSVD3, 0x3224, N, N, N, 0xa4c, 12, 5, 20, 5, -1, -1, -1, -1),
1496 PINGROUP(als_prox_int_px3, RSVD0, RSVD1, RSVD2, RSVD3, 0x3228, N, N, N, 0x8e4, 12, 5, 20, 5, -1, -1, -1, -1),
1497 PINGROUP(temp_alert_px4, RSVD0, RSVD1, RSVD2, RSVD3, 0x322c, N, N, N, 0xb0c, 12, 5, 20, 5, -1, -1, -1, -1),
1498 PINGROUP(button_power_on_px5, RSVD0, RSVD1, RSVD2, RSVD3, 0x3230, N, N, N, 0x908, 12, 5, 20, 5, -1, -1, -1, -1),
1499 PINGROUP(button_vol_up_px6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3234, N, N, N, 0x914, 12, 5, 20, 5, -1, -1, -1, -1),
1500 PINGROUP(button_vol_down_px7, RSVD0, RSVD1, RSVD2, RSVD3, 0x3238, N, N, N, 0x910, 12, 5, 20, 5, -1, -1, -1, -1),
1501 PINGROUP(button_slide_sw_py0, RSVD0, RSVD1, RSVD2, RSVD3, 0x323c, N, N, N, 0x90c, 12, 5, 20, 5, -1, -1, -1, -1),
1502 PINGROUP(button_home_py1, RSVD0, RSVD1, RSVD2, RSVD3, 0x3240, N, N, N, 0x904, 12, 5, 20, 5, -1, -1, -1, -1),
1503 PINGROUP(pa6, SATA, RSVD1, RSVD2, RSVD3, 0x3244, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1504 PINGROUP(pe6, RSVD0, I2S5A, PWM2, RSVD3, 0x3248, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1505 PINGROUP(pe7, RSVD0, I2S5A, PWM3, RSVD3, 0x324c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1506 PINGROUP(ph6, RSVD0, RSVD1, RSVD2, RSVD3, 0x3250, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1507 PINGROUP(pk0, IQC0, I2S5B, RSVD2, RSVD3, 0x3254, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1508 PINGROUP(pk1, IQC0, I2S5B, RSVD2, RSVD3, 0x3258, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1509 PINGROUP(pk2, IQC0, I2S5B, RSVD2, RSVD3, 0x325c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1510 PINGROUP(pk3, IQC0, I2S5B, RSVD2, RSVD3, 0x3260, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1511 PINGROUP(pk4, IQC1, RSVD1, RSVD2, RSVD3, 0x3264, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1512 PINGROUP(pk5, IQC1, RSVD1, RSVD2, RSVD3, 0x3268, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1513 PINGROUP(pk6, IQC1, RSVD1, RSVD2, RSVD3, 0x326c, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1514 PINGROUP(pk7, IQC1, RSVD1, RSVD2, RSVD3, 0x3270, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1515 PINGROUP(pl0, RSVD0, RSVD1, RSVD2, RSVD3, 0x3274, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1516 PINGROUP(pl1, SOC, RSVD1, RSVD2, RSVD3, 0x3278, Y, Y, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1517 PINGROUP(pz0, VIMCLK2, RSVD1, RSVD2, RSVD3, 0x327c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1518 PINGROUP(pz1, VIMCLK2, SDMMC1, RSVD2, RSVD3, 0x3280, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1519 PINGROUP(pz2, SDMMC3, CCLA, RSVD2, RSVD3, 0x3284, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1520 PINGROUP(pz3, SDMMC3, RSVD1, RSVD2, RSVD3, 0x3288, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1521 PINGROUP(pz4, SDMMC1, RSVD1, RSVD2, RSVD3, 0x328c, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1522 PINGROUP(pz5, SOC, RSVD1, RSVD2, RSVD3, 0x3290, N, N, N, -1, -1, -1, -1, -1, -1, -1, -1, -1),
1523
1524 /* pg_name, r, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w */
1525 DRV_PINGROUP(pa6, 0x9c0, 12, 5, 20, 5, -1, -1, -1, -1),
1526 DRV_PINGROUP(pcc7, 0x9c4, 12, 5, 20, 5, -1, -1, -1, -1),
1527 DRV_PINGROUP(pe6, 0x9c8, 12, 5, 20, 5, -1, -1, -1, -1),
1528 DRV_PINGROUP(pe7, 0x9cc, 12, 5, 20, 5, -1, -1, -1, -1),
1529 DRV_PINGROUP(ph6, 0x9d0, 12, 5, 20, 5, -1, -1, -1, -1),
1530 DRV_PINGROUP(pk0, 0x9d4, -1, -1, -1, -1, 28, 2, 30, 2),
1531 DRV_PINGROUP(pk1, 0x9d8, -1, -1, -1, -1, 28, 2, 30, 2),
1532 DRV_PINGROUP(pk2, 0x9dc, -1, -1, -1, -1, 28, 2, 30, 2),
1533 DRV_PINGROUP(pk3, 0x9e0, -1, -1, -1, -1, 28, 2, 30, 2),
1534 DRV_PINGROUP(pk4, 0x9e4, -1, -1, -1, -1, 28, 2, 30, 2),
1535 DRV_PINGROUP(pk5, 0x9e8, -1, -1, -1, -1, 28, 2, 30, 2),
1536 DRV_PINGROUP(pk6, 0x9ec, -1, -1, -1, -1, 28, 2, 30, 2),
1537 DRV_PINGROUP(pk7, 0x9f0, -1, -1, -1, -1, 28, 2, 30, 2),
1538 DRV_PINGROUP(pl0, 0x9f4, -1, -1, -1, -1, 28, 2, 30, 2),
1539 DRV_PINGROUP(pl1, 0x9f8, -1, -1, -1, -1, 28, 2, 30, 2),
1540 DRV_PINGROUP(pz0, 0x9fc, 12, 7, 20, 7, -1, -1, -1, -1),
1541 DRV_PINGROUP(pz1, 0xa00, 12, 7, 20, 7, -1, -1, -1, -1),
1542 DRV_PINGROUP(pz2, 0xa04, 12, 7, 20, 7, -1, -1, -1, -1),
1543 DRV_PINGROUP(pz3, 0xa08, 12, 7, 20, 7, -1, -1, -1, -1),
1544 DRV_PINGROUP(pz4, 0xa0c, 12, 7, 20, 7, -1, -1, -1, -1),
1545 DRV_PINGROUP(pz5, 0xa10, 12, 7, 20, 7, -1, -1, -1, -1),
1546 DRV_PINGROUP(sdmmc1, 0xa98, 12, 7, 20, 7, 28, 2, 30, 2),
1547 DRV_PINGROUP(sdmmc2, 0xa9c, 2, 6, 8, 6, 28, 2, 30, 2),
1548 DRV_PINGROUP(sdmmc3, 0xab0, 12, 7, 20, 7, 28, 2, 30, 2),
1549 DRV_PINGROUP(sdmmc4, 0xab4, 2, 6, 8, 6, 28, 2, 30, 2),
1550};
1551
1552static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {
1553 .ngpios = NUM_GPIOS,
1554 .pins = tegra210_pins,
1555 .npins = ARRAY_SIZE(tegra210_pins),
1556 .functions = tegra210_functions,
1557 .nfunctions = ARRAY_SIZE(tegra210_functions),
1558 .groups = tegra210_groups,
1559 .ngroups = ARRAY_SIZE(tegra210_groups),
1560 .hsm_in_mux = true,
1561 .schmitt_in_mux = true,
1562 .drvtype_in_mux = true,
1563};
1564
1565static int tegra210_pinctrl_probe(struct platform_device *pdev)
1566{
1567 return tegra_pinctrl_probe(pdev, &tegra210_pinctrl);
1568}
1569
1570static const struct of_device_id tegra210_pinctrl_of_match[] = {
1571 { .compatible = "nvidia,tegra210-pinmux", },
1572 { },
1573};
1574MODULE_DEVICE_TABLE(of, tegra210_pinctrl_of_match);
1575
1576static struct platform_driver tegra210_pinctrl_driver = {
1577 .driver = {
1578 .name = "tegra210-pinctrl",
1579 .of_match_table = tegra210_pinctrl_of_match,
1580 },
1581 .probe = tegra210_pinctrl_probe,
1582 .remove = tegra_pinctrl_remove,
1583};
1584module_platform_driver(tegra210_pinctrl_driver);
1585
1586MODULE_AUTHOR("NVIDIA");
1587MODULE_DESCRIPTION("NVIDIA Tegra210 pinctrl driver");
1588MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c
index f6edc2ff5494..47b2fd8bb2e9 100644
--- a/drivers/pinctrl/pinctrl-tegra30.c
+++ b/drivers/pinctrl/pinctrl-tegra30.c
@@ -2108,70 +2108,69 @@ static struct tegra_function tegra30_functions[] = {
2108#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */ 2108#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2109#define PINGROUP_REG_A 0x3000 /* bank 1 */ 2109#define PINGROUP_REG_A 0x3000 /* bank 1 */
2110 2110
2111#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
2111#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A) 2112#define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
2112 2113
2113#define PINGROUP_BIT_Y(b) (b) 2114#define PINGROUP_BIT_Y(b) (b)
2114#define PINGROUP_BIT_N(b) (-1) 2115#define PINGROUP_BIT_N(b) (-1)
2115 2116
2116#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \ 2117#define PINGROUP(pg_name, f0, f1, f2, f3, r, od, ior) \
2117 { \ 2118 { \
2118 .name = #pg_name, \ 2119 .name = #pg_name, \
2119 .pins = pg_name##_pins, \ 2120 .pins = pg_name##_pins, \
2120 .npins = ARRAY_SIZE(pg_name##_pins), \ 2121 .npins = ARRAY_SIZE(pg_name##_pins), \
2121 .funcs = { \ 2122 .funcs = { \
2122 TEGRA_MUX_##f0, \ 2123 TEGRA_MUX_##f0, \
2123 TEGRA_MUX_##f1, \ 2124 TEGRA_MUX_##f1, \
2124 TEGRA_MUX_##f2, \ 2125 TEGRA_MUX_##f2, \
2125 TEGRA_MUX_##f3, \ 2126 TEGRA_MUX_##f3, \
2126 }, \ 2127 }, \
2127 .mux_reg = PINGROUP_REG(r), \ 2128 .mux_reg = PINGROUP_REG(r), \
2128 .mux_bank = 1, \ 2129 .mux_bank = 1, \
2129 .mux_bit = 0, \ 2130 .mux_bit = 0, \
2130 .pupd_reg = PINGROUP_REG(r), \ 2131 .pupd_reg = PINGROUP_REG(r), \
2131 .pupd_bank = 1, \ 2132 .pupd_bank = 1, \
2132 .pupd_bit = 2, \ 2133 .pupd_bit = 2, \
2133 .tri_reg = PINGROUP_REG(r), \ 2134 .tri_reg = PINGROUP_REG(r), \
2134 .tri_bank = 1, \ 2135 .tri_bank = 1, \
2135 .tri_bit = 4, \ 2136 .tri_bit = 4, \
2136 .einput_bit = PINGROUP_BIT_Y(5), \ 2137 .einput_bit = 5, \
2137 .odrain_bit = PINGROUP_BIT_##od(6), \ 2138 .odrain_bit = PINGROUP_BIT_##od(6), \
2138 .lock_bit = PINGROUP_BIT_Y(7), \ 2139 .lock_bit = 7, \
2139 .ioreset_bit = PINGROUP_BIT_##ior(8), \ 2140 .ioreset_bit = PINGROUP_BIT_##ior(8), \
2140 .rcv_sel_bit = -1, \ 2141 .rcv_sel_bit = -1, \
2141 .drv_reg = -1, \ 2142 .drv_reg = -1, \
2142 } 2143 }
2143 2144
2144#define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A) 2145#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, \
2145 2146 drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, \
2146#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \ 2147 slwf_b, slwf_w) \
2147 drvdn_b, drvdn_w, drvup_b, drvup_w, \ 2148 { \
2148 slwr_b, slwr_w, slwf_b, slwf_w) \ 2149 .name = "drive_" #pg_name, \
2149 { \ 2150 .pins = drive_##pg_name##_pins, \
2150 .name = "drive_" #pg_name, \ 2151 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
2151 .pins = drive_##pg_name##_pins, \ 2152 .mux_reg = -1, \
2152 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \ 2153 .pupd_reg = -1, \
2153 .mux_reg = -1, \ 2154 .tri_reg = -1, \
2154 .pupd_reg = -1, \ 2155 .einput_bit = -1, \
2155 .tri_reg = -1, \ 2156 .odrain_bit = -1, \
2156 .einput_bit = -1, \ 2157 .lock_bit = -1, \
2157 .odrain_bit = -1, \ 2158 .ioreset_bit = -1, \
2158 .lock_bit = -1, \ 2159 .rcv_sel_bit = -1, \
2159 .ioreset_bit = -1, \ 2160 .drv_reg = DRV_PINGROUP_REG(r), \
2160 .rcv_sel_bit = -1, \ 2161 .drv_bank = 0, \
2161 .drv_reg = DRV_PINGROUP_REG(r), \ 2162 .hsm_bit = hsm_b, \
2162 .drv_bank = 0, \ 2163 .schmitt_bit = schmitt_b, \
2163 .hsm_bit = hsm_b, \ 2164 .lpmd_bit = lpmd_b, \
2164 .schmitt_bit = schmitt_b, \ 2165 .drvdn_bit = drvdn_b, \
2165 .lpmd_bit = lpmd_b, \ 2166 .drvdn_width = drvdn_w, \
2166 .drvdn_bit = drvdn_b, \ 2167 .drvup_bit = drvup_b, \
2167 .drvdn_width = drvdn_w, \ 2168 .drvup_width = drvup_w, \
2168 .drvup_bit = drvup_b, \ 2169 .slwr_bit = slwr_b, \
2169 .drvup_width = drvup_w, \ 2170 .slwr_width = slwr_w, \
2170 .slwr_bit = slwr_b, \ 2171 .slwf_bit = slwf_b, \
2171 .slwr_width = slwr_w, \ 2172 .slwf_width = slwf_w, \
2172 .slwf_bit = slwf_b, \ 2173 .drvtype_bit = -1, \
2173 .slwf_width = slwf_w, \
2174 .drvtype_bit = -1, \
2175 } 2174 }
2176 2175
2177static const struct tegra_pingroup tegra30_groups[] = { 2176static const struct tegra_pingroup tegra30_groups[] = {
@@ -2477,6 +2476,9 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {
2477 .nfunctions = ARRAY_SIZE(tegra30_functions), 2476 .nfunctions = ARRAY_SIZE(tegra30_functions),
2478 .groups = tegra30_groups, 2477 .groups = tegra30_groups,
2479 .ngroups = ARRAY_SIZE(tegra30_groups), 2478 .ngroups = ARRAY_SIZE(tegra30_groups),
2479 .hsm_in_mux = false,
2480 .schmitt_in_mux = false,
2481 .drvtype_in_mux = false,
2480}; 2482};
2481 2483
2482static int tegra30_pinctrl_probe(struct platform_device *pdev) 2484static int tegra30_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/pinctrl-tz1090-pdc.c b/drivers/pinctrl/pinctrl-tz1090-pdc.c
index fab6aafa6a9f..8a8911bb883a 100644
--- a/drivers/pinctrl/pinctrl-tz1090-pdc.c
+++ b/drivers/pinctrl/pinctrl-tz1090-pdc.c
@@ -969,7 +969,7 @@ static int tz1090_pdc_pinctrl_remove(struct platform_device *pdev)
969 return 0; 969 return 0;
970} 970}
971 971
972static struct of_device_id tz1090_pdc_pinctrl_of_match[] = { 972static const struct of_device_id tz1090_pdc_pinctrl_of_match[] = {
973 { .compatible = "img,tz1090-pdc-pinctrl", }, 973 { .compatible = "img,tz1090-pdc-pinctrl", },
974 { }, 974 { },
975}; 975};
diff --git a/drivers/pinctrl/pinctrl-tz1090.c b/drivers/pinctrl/pinctrl-tz1090.c
index 8bd73075f9dd..fc5594a530c2 100644
--- a/drivers/pinctrl/pinctrl-tz1090.c
+++ b/drivers/pinctrl/pinctrl-tz1090.c
@@ -1984,7 +1984,7 @@ static int tz1090_pinctrl_remove(struct platform_device *pdev)
1984 return 0; 1984 return 0;
1985} 1985}
1986 1986
1987static struct of_device_id tz1090_pinctrl_of_match[] = { 1987static const struct of_device_id tz1090_pinctrl_of_match[] = {
1988 { .compatible = "img,tz1090-pinctrl", }, 1988 { .compatible = "img,tz1090-pinctrl", },
1989 { }, 1989 { },
1990}; 1990};
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index a535f9c23678..f3d800f796c2 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -193,11 +193,11 @@ static int msm_config_reg(struct msm_pinctrl *pctrl,
193 *mask = 7; 193 *mask = 7;
194 break; 194 break;
195 case PIN_CONFIG_OUTPUT: 195 case PIN_CONFIG_OUTPUT:
196 case PIN_CONFIG_INPUT_ENABLE:
196 *bit = g->oe_bit; 197 *bit = g->oe_bit;
197 *mask = 1; 198 *mask = 1;
198 break; 199 break;
199 default: 200 default:
200 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
201 return -ENOTSUPP; 201 return -ENOTSUPP;
202 } 202 }
203 203
@@ -261,10 +261,14 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev,
261 val = readl(pctrl->regs + g->io_reg); 261 val = readl(pctrl->regs + g->io_reg);
262 arg = !!(val & BIT(g->in_bit)); 262 arg = !!(val & BIT(g->in_bit));
263 break; 263 break;
264 case PIN_CONFIG_INPUT_ENABLE:
265 /* Pin is output */
266 if (arg)
267 return -EINVAL;
268 arg = 1;
269 break;
264 default: 270 default:
265 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 271 return -ENOTSUPP;
266 param);
267 return -EINVAL;
268 } 272 }
269 273
270 *config = pinconf_to_config_packed(param, arg); 274 *config = pinconf_to_config_packed(param, arg);
@@ -333,6 +337,10 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
333 /* enable output */ 337 /* enable output */
334 arg = 1; 338 arg = 1;
335 break; 339 break;
340 case PIN_CONFIG_INPUT_ENABLE:
341 /* disable output */
342 arg = 0;
343 break;
336 default: 344 default:
337 dev_err(pctrl->dev, "Unsupported config parameter: %x\n", 345 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
338 param); 346 param);
@@ -357,6 +365,7 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev,
357} 365}
358 366
359static const struct pinconf_ops msm_pinconf_ops = { 367static const struct pinconf_ops msm_pinconf_ops = {
368 .is_generic = true,
360 .pin_config_group_get = msm_config_group_get, 369 .pin_config_group_get = msm_config_group_get,
361 .pin_config_group_set = msm_config_group_set, 370 .pin_config_group_set = msm_config_group_set,
362}; 371};
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index 0f11a26d932b..b2d22218a258 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@ -810,6 +810,7 @@ static int pmic_gpio_remove(struct platform_device *pdev)
810} 810}
811 811
812static const struct of_device_id pmic_gpio_of_match[] = { 812static const struct of_device_id pmic_gpio_of_match[] = {
813 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */
813 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */ 814 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */
814 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ 815 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */
815 { }, 816 { },
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
index a8924dba335e..8f36c5f91949 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-mpp.c
@@ -925,6 +925,7 @@ static int pmic_mpp_remove(struct platform_device *pdev)
925 925
926static const struct of_device_id pmic_mpp_of_match[] = { 926static const struct of_device_id pmic_mpp_of_match[] = {
927 { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */ 927 { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */
928 { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */
928 { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */ 929 { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */
929 { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */ 930 { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */
930 { }, 931 { },
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index c8f83f96546c..0b7afa50121a 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1240,6 +1240,159 @@ const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
1240 }, 1240 },
1241}; 1241};
1242 1242
1243/* pin banks of exynos5433 pin-controller - ALIVE */
1244static const struct samsung_pin_bank_data exynos5433_pin_banks0[] = {
1245 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
1246 EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
1247 EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
1248 EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
1249};
1250
1251/* pin banks of exynos5433 pin-controller - AUD */
1252static const struct samsung_pin_bank_data exynos5433_pin_banks1[] = {
1253 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
1254 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
1255};
1256
1257/* pin banks of exynos5433 pin-controller - CPIF */
1258static const struct samsung_pin_bank_data exynos5433_pin_banks2[] = {
1259 EXYNOS_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
1260};
1261
1262/* pin banks of exynos5433 pin-controller - eSE */
1263static const struct samsung_pin_bank_data exynos5433_pin_banks3[] = {
1264 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
1265};
1266
1267/* pin banks of exynos5433 pin-controller - FINGER */
1268static const struct samsung_pin_bank_data exynos5433_pin_banks4[] = {
1269 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
1270};
1271
1272/* pin banks of exynos5433 pin-controller - FSYS */
1273static const struct samsung_pin_bank_data exynos5433_pin_banks5[] = {
1274 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
1275 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
1276 EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
1277 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
1278 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
1279 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
1280};
1281
1282/* pin banks of exynos5433 pin-controller - IMEM */
1283static const struct samsung_pin_bank_data exynos5433_pin_banks6[] = {
1284 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
1285};
1286
1287/* pin banks of exynos5433 pin-controller - NFC */
1288static const struct samsung_pin_bank_data exynos5433_pin_banks7[] = {
1289 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
1290};
1291
1292/* pin banks of exynos5433 pin-controller - PERIC */
1293static const struct samsung_pin_bank_data exynos5433_pin_banks8[] = {
1294 EXYNOS_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
1295 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
1296 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
1297 EXYNOS_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
1298 EXYNOS_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
1299 EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
1300 EXYNOS_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
1301 EXYNOS_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
1302 EXYNOS_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
1303 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
1304 EXYNOS_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
1305 EXYNOS_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
1306 EXYNOS_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
1307 EXYNOS_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
1308 EXYNOS_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
1309 EXYNOS_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
1310 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
1311};
1312
1313/* pin banks of exynos5433 pin-controller - TOUCH */
1314static const struct samsung_pin_bank_data exynos5433_pin_banks9[] = {
1315 EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
1316};
1317
1318/*
1319 * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
1320 * ten gpio/pin-mux/pinconfig controllers.
1321 */
1322const struct samsung_pin_ctrl exynos5433_pin_ctrl[] = {
1323 {
1324 /* pin-controller instance 0 data */
1325 .pin_banks = exynos5433_pin_banks0,
1326 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
1327 .eint_wkup_init = exynos_eint_wkup_init,
1328 .suspend = exynos_pinctrl_suspend,
1329 .resume = exynos_pinctrl_resume,
1330 }, {
1331 /* pin-controller instance 1 data */
1332 .pin_banks = exynos5433_pin_banks1,
1333 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1),
1334 .eint_gpio_init = exynos_eint_gpio_init,
1335 .suspend = exynos_pinctrl_suspend,
1336 .resume = exynos_pinctrl_resume,
1337 }, {
1338 /* pin-controller instance 2 data */
1339 .pin_banks = exynos5433_pin_banks2,
1340 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2),
1341 .eint_gpio_init = exynos_eint_gpio_init,
1342 .suspend = exynos_pinctrl_suspend,
1343 .resume = exynos_pinctrl_resume,
1344 }, {
1345 /* pin-controller instance 3 data */
1346 .pin_banks = exynos5433_pin_banks3,
1347 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3),
1348 .eint_gpio_init = exynos_eint_gpio_init,
1349 .suspend = exynos_pinctrl_suspend,
1350 .resume = exynos_pinctrl_resume,
1351 }, {
1352 /* pin-controller instance 4 data */
1353 .pin_banks = exynos5433_pin_banks4,
1354 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4),
1355 .eint_gpio_init = exynos_eint_gpio_init,
1356 .suspend = exynos_pinctrl_suspend,
1357 .resume = exynos_pinctrl_resume,
1358 }, {
1359 /* pin-controller instance 5 data */
1360 .pin_banks = exynos5433_pin_banks5,
1361 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5),
1362 .eint_gpio_init = exynos_eint_gpio_init,
1363 .suspend = exynos_pinctrl_suspend,
1364 .resume = exynos_pinctrl_resume,
1365 }, {
1366 /* pin-controller instance 6 data */
1367 .pin_banks = exynos5433_pin_banks6,
1368 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6),
1369 .eint_gpio_init = exynos_eint_gpio_init,
1370 .suspend = exynos_pinctrl_suspend,
1371 .resume = exynos_pinctrl_resume,
1372 }, {
1373 /* pin-controller instance 7 data */
1374 .pin_banks = exynos5433_pin_banks7,
1375 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7),
1376 .eint_gpio_init = exynos_eint_gpio_init,
1377 .suspend = exynos_pinctrl_suspend,
1378 .resume = exynos_pinctrl_resume,
1379 }, {
1380 /* pin-controller instance 8 data */
1381 .pin_banks = exynos5433_pin_banks8,
1382 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8),
1383 .eint_gpio_init = exynos_eint_gpio_init,
1384 .suspend = exynos_pinctrl_suspend,
1385 .resume = exynos_pinctrl_resume,
1386 }, {
1387 /* pin-controller instance 9 data */
1388 .pin_banks = exynos5433_pin_banks9,
1389 .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9),
1390 .eint_gpio_init = exynos_eint_gpio_init,
1391 .suspend = exynos_pinctrl_suspend,
1392 .resume = exynos_pinctrl_resume,
1393 },
1394};
1395
1243/* pin banks of exynos7 pin-controller - ALIVE */ 1396/* pin banks of exynos7 pin-controller - ALIVE */
1244static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = { 1397static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
1245 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00), 1398 EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
@@ -1324,7 +1477,6 @@ const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
1324 /* pin-controller instance 0 Alive data */ 1477 /* pin-controller instance 0 Alive data */
1325 .pin_banks = exynos7_pin_banks0, 1478 .pin_banks = exynos7_pin_banks0,
1326 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0), 1479 .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
1327 .eint_gpio_init = exynos_eint_gpio_init,
1328 .eint_wkup_init = exynos_eint_wkup_init, 1480 .eint_wkup_init = exynos_eint_wkup_init,
1329 }, { 1481 }, {
1330 /* pin-controller instance 1 BUS0 data */ 1482 /* pin-controller instance 1 BUS0 data */
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index ec580af35856..ed165ba2eb2f 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1239,6 +1239,8 @@ static const struct of_device_id samsung_pinctrl_dt_match[] = {
1239 .data = (void *)exynos5260_pin_ctrl }, 1239 .data = (void *)exynos5260_pin_ctrl },
1240 { .compatible = "samsung,exynos5420-pinctrl", 1240 { .compatible = "samsung,exynos5420-pinctrl",
1241 .data = (void *)exynos5420_pin_ctrl }, 1241 .data = (void *)exynos5420_pin_ctrl },
1242 { .compatible = "samsung,exynos5433-pinctrl",
1243 .data = (void *)exynos5433_pin_ctrl },
1242 { .compatible = "samsung,s5pv210-pinctrl", 1244 { .compatible = "samsung,s5pv210-pinctrl",
1243 .data = (void *)s5pv210_pin_ctrl }, 1245 .data = (void *)s5pv210_pin_ctrl },
1244 { .compatible = "samsung,exynos7-pinctrl", 1246 { .compatible = "samsung,exynos7-pinctrl",
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 1b8c0139d604..c1239ff6157d 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -271,6 +271,7 @@ extern const struct samsung_pin_ctrl exynos4415_pin_ctrl[];
271extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[]; 271extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[];
272extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[]; 272extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[];
273extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[]; 273extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[];
274extern const struct samsung_pin_ctrl exynos5433_pin_ctrl[];
274extern const struct samsung_pin_ctrl exynos7_pin_ctrl[]; 275extern const struct samsung_pin_ctrl exynos7_pin_ctrl[];
275extern const struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; 276extern const struct samsung_pin_ctrl s3c64xx_pin_ctrl[];
276extern const struct samsung_pin_ctrl s3c2412_pin_ctrl[]; 277extern const struct samsung_pin_ctrl s3c2412_pin_ctrl[];
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index a56280814a3f..7b2c9495c383 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -92,10 +92,10 @@ static int sh_pfc_map_resources(struct sh_pfc *pfc,
92 return 0; 92 return 0;
93} 93}
94 94
95static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, 95static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
96 unsigned long address)
97{ 96{
98 struct sh_pfc_window *window; 97 struct sh_pfc_window *window;
98 phys_addr_t address = reg;
99 unsigned int i; 99 unsigned int i;
100 100
101 /* scan through physical windows and convert address */ 101 /* scan through physical windows and convert address */
@@ -144,8 +144,7 @@ static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
144 return 1; 144 return 1;
145} 145}
146 146
147unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, 147u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
148 unsigned long reg_width)
149{ 148{
150 switch (reg_width) { 149 switch (reg_width) {
151 case 8: 150 case 8:
@@ -160,8 +159,8 @@ unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
160 return 0; 159 return 0;
161} 160}
162 161
163void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, 162void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
164 unsigned long data) 163 u32 data)
165{ 164{
166 switch (reg_width) { 165 switch (reg_width) {
167 case 8: 166 case 8:
@@ -180,10 +179,9 @@ void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
180 179
181static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, 180static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
182 const struct pinmux_cfg_reg *crp, 181 const struct pinmux_cfg_reg *crp,
183 unsigned long in_pos, 182 unsigned int in_pos,
184 void __iomem **mapped_regp, 183 void __iomem **mapped_regp, u32 *maskp,
185 unsigned long *maskp, 184 unsigned int *posp)
186 unsigned long *posp)
187{ 185{
188 unsigned int k; 186 unsigned int k;
189 187
@@ -202,15 +200,16 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
202 200
203static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 201static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
204 const struct pinmux_cfg_reg *crp, 202 const struct pinmux_cfg_reg *crp,
205 unsigned long field, unsigned long value) 203 unsigned int field, u32 value)
206{ 204{
207 void __iomem *mapped_reg; 205 void __iomem *mapped_reg;
208 unsigned long mask, pos, data; 206 unsigned int pos;
207 u32 mask, data;
209 208
210 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); 209 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
211 210
212 dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, " 211 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
213 "r_width = %ld, f_width = %ld\n", 212 "r_width = %u, f_width = %u\n",
214 crp->reg, value, field, crp->reg_width, crp->field_width); 213 crp->reg, value, field, crp->reg_width, crp->field_width);
215 214
216 mask = ~(mask << pos); 215 mask = ~(mask << pos);
@@ -229,26 +228,28 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
229} 228}
230 229
231static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, 230static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
232 const struct pinmux_cfg_reg **crp, int *fieldp, 231 const struct pinmux_cfg_reg **crp,
233 int *valuep) 232 unsigned int *fieldp, u32 *valuep)
234{ 233{
235 const struct pinmux_cfg_reg *config_reg; 234 unsigned int k = 0;
236 unsigned long r_width, f_width, curr_width, ncomb;
237 unsigned int k, m, n, pos, bit_pos;
238 235
239 k = 0;
240 while (1) { 236 while (1) {
241 config_reg = pfc->info->cfg_regs + k; 237 const struct pinmux_cfg_reg *config_reg =
242 238 pfc->info->cfg_regs + k;
243 r_width = config_reg->reg_width; 239 unsigned int r_width = config_reg->reg_width;
244 f_width = config_reg->field_width; 240 unsigned int f_width = config_reg->field_width;
241 unsigned int curr_width;
242 unsigned int bit_pos;
243 unsigned int pos = 0;
244 unsigned int m = 0;
245 245
246 if (!r_width) 246 if (!r_width)
247 break; 247 break;
248 248
249 pos = 0;
250 m = 0;
251 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { 249 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
250 u32 ncomb;
251 u32 n;
252
252 if (f_width) 253 if (f_width)
253 curr_width = f_width; 254 curr_width = f_width;
254 else 255 else
@@ -297,11 +298,8 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
297 298
298int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) 299int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
299{ 300{
300 const struct pinmux_cfg_reg *cr = NULL;
301 u16 enum_id;
302 const struct pinmux_range *range; 301 const struct pinmux_range *range;
303 int in_range, pos, field, value; 302 int pos = 0;
304 int ret;
305 303
306 switch (pinmux_type) { 304 switch (pinmux_type) {
307 case PINMUX_TYPE_GPIO: 305 case PINMUX_TYPE_GPIO:
@@ -321,13 +319,15 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
321 return -EINVAL; 319 return -EINVAL;
322 } 320 }
323 321
324 pos = 0;
325 enum_id = 0;
326 field = 0;
327 value = 0;
328
329 /* Iterate over all the configuration fields we need to update. */ 322 /* Iterate over all the configuration fields we need to update. */
330 while (1) { 323 while (1) {
324 const struct pinmux_cfg_reg *cr;
325 unsigned int field;
326 u16 enum_id;
327 u32 value;
328 int in_range;
329 int ret;
330
331 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); 331 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
332 if (pos < 0) 332 if (pos < 0)
333 return pos; 333 return pos;
@@ -579,9 +579,6 @@ static int sh_pfc_remove(struct platform_device *pdev)
579} 579}
580 580
581static const struct platform_device_id sh_pfc_id_table[] = { 581static const struct platform_device_id sh_pfc_id_table[] = {
582#ifdef CONFIG_PINCTRL_PFC_EMEV2
583 { "pfc-emev2", (kernel_ulong_t)&emev2_pinmux_info },
584#endif
585#ifdef CONFIG_PINCTRL_PFC_R8A73A4 582#ifdef CONFIG_PINCTRL_PFC_R8A73A4
586 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info }, 583 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
587#endif 584#endif
@@ -594,12 +591,6 @@ static const struct platform_device_id sh_pfc_id_table[] = {
594#ifdef CONFIG_PINCTRL_PFC_R8A7779 591#ifdef CONFIG_PINCTRL_PFC_R8A7779
595 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info }, 592 { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
596#endif 593#endif
597#ifdef CONFIG_PINCTRL_PFC_R8A7790
598 { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
599#endif
600#ifdef CONFIG_PINCTRL_PFC_R8A7791
601 { "pfc-r8a7791", (kernel_ulong_t)&r8a7791_pinmux_info },
602#endif
603#ifdef CONFIG_PINCTRL_PFC_SH7203 594#ifdef CONFIG_PINCTRL_PFC_SH7203
604 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, 595 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
605#endif 596#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 6b59d63b9c01..6dc8a6fc2746 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -57,10 +57,9 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
57int sh_pfc_register_pinctrl(struct sh_pfc *pfc); 57int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
58int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc); 58int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);
59 59
60unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, 60u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width);
61 unsigned long reg_width); 61void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
62void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width, 62 u32 data);
63 unsigned long data);
64 63
65int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin); 64int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
66int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type); 65int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 80f641ee4dea..ba353735ecf2 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -21,7 +21,7 @@
21 21
22struct sh_pfc_gpio_data_reg { 22struct sh_pfc_gpio_data_reg {
23 const struct pinmux_data_reg *info; 23 const struct pinmux_data_reg *info;
24 unsigned long shadow; 24 u32 shadow;
25}; 25};
26 26
27struct sh_pfc_gpio_pin { 27struct sh_pfc_gpio_pin {
@@ -59,19 +59,20 @@ static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
59 *bit = gpio_pin->dbit; 59 *bit = gpio_pin->dbit;
60} 60}
61 61
62static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip, 62static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
63 const struct pinmux_data_reg *dreg) 63 const struct pinmux_data_reg *dreg)
64{ 64{
65 void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; 65 phys_addr_t address = dreg->reg;
66 void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
66 67
67 return sh_pfc_read_raw_reg(mem, dreg->reg_width); 68 return sh_pfc_read_raw_reg(mem, dreg->reg_width);
68} 69}
69 70
70static void gpio_write_data_reg(struct sh_pfc_chip *chip, 71static void gpio_write_data_reg(struct sh_pfc_chip *chip,
71 const struct pinmux_data_reg *dreg, 72 const struct pinmux_data_reg *dreg, u32 value)
72 unsigned long value)
73{ 73{
74 void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; 74 phys_addr_t address = dreg->reg;
75 void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
75 76
76 sh_pfc_write_raw_reg(mem, dreg->reg_width, value); 77 sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
77} 78}
@@ -85,7 +86,7 @@ static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
85 unsigned int bit; 86 unsigned int bit;
86 unsigned int i; 87 unsigned int i;
87 88
88 for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) { 89 for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
89 for (bit = 0; bit < dreg->reg_width; bit++) { 90 for (bit = 0; bit < dreg->reg_width; bit++) {
90 if (dreg->enum_ids[bit] == pin->enum_id) { 91 if (dreg->enum_ids[bit] == pin->enum_id) {
91 gpio_pin->dreg = i; 92 gpio_pin->dreg = i;
@@ -154,17 +155,17 @@ static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
154 int value) 155 int value)
155{ 156{
156 struct sh_pfc_gpio_data_reg *reg; 157 struct sh_pfc_gpio_data_reg *reg;
157 unsigned long pos;
158 unsigned int bit; 158 unsigned int bit;
159 unsigned int pos;
159 160
160 gpio_get_data_reg(chip, offset, &reg, &bit); 161 gpio_get_data_reg(chip, offset, &reg, &bit);
161 162
162 pos = reg->info->reg_width - (bit + 1); 163 pos = reg->info->reg_width - (bit + 1);
163 164
164 if (value) 165 if (value)
165 set_bit(pos, &reg->shadow); 166 reg->shadow |= BIT(pos);
166 else 167 else
167 clear_bit(pos, &reg->shadow); 168 reg->shadow &= ~BIT(pos);
168 169
169 gpio_write_data_reg(chip, reg->info, reg->shadow); 170 gpio_write_data_reg(chip, reg->info, reg->shadow);
170} 171}
@@ -186,8 +187,8 @@ static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
186{ 187{
187 struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc); 188 struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
188 struct sh_pfc_gpio_data_reg *reg; 189 struct sh_pfc_gpio_data_reg *reg;
189 unsigned long pos;
190 unsigned int bit; 190 unsigned int bit;
191 unsigned int pos;
191 192
192 gpio_get_data_reg(chip, offset, &reg, &bit); 193 gpio_get_data_reg(chip, offset, &reg, &bit);
193 194
@@ -341,6 +342,7 @@ sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
341int sh_pfc_register_gpiochip(struct sh_pfc *pfc) 342int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
342{ 343{
343 struct sh_pfc_chip *chip; 344 struct sh_pfc_chip *chip;
345 phys_addr_t address;
344 unsigned int i; 346 unsigned int i;
345 int ret; 347 int ret;
346 348
@@ -352,11 +354,12 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
352 * that covers the data registers. In that case don't try to handle 354 * that covers the data registers. In that case don't try to handle
353 * GPIOs. 355 * GPIOs.
354 */ 356 */
357 address = pfc->info->data_regs[0].reg;
355 for (i = 0; i < pfc->num_windows; ++i) { 358 for (i = 0; i < pfc->num_windows; ++i) {
356 struct sh_pfc_window *window = &pfc->windows[i]; 359 struct sh_pfc_window *window = &pfc->windows[i];
357 360
358 if (pfc->info->data_regs[0].reg >= window->phys && 361 if (address >= window->phys &&
359 pfc->info->data_regs[0].reg < window->phys + window->size) 362 address < window->phys + window->size)
360 break; 363 break;
361 } 364 }
362 365
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 80c1843bb6ad..22a5470889f5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -1799,6 +1799,81 @@ static const unsigned int audio_clkout_d_pins[] = {
1799static const unsigned int audio_clkout_d_mux[] = { 1799static const unsigned int audio_clkout_d_mux[] = {
1800 AUDIO_CLKOUT_D_MARK, 1800 AUDIO_CLKOUT_D_MARK,
1801}; 1801};
1802/* - AVB -------------------------------------------------------------------- */
1803static const unsigned int avb_link_pins[] = {
1804 RCAR_GP_PIN(3, 11),
1805};
1806static const unsigned int avb_link_mux[] = {
1807 AVB_LINK_MARK,
1808};
1809static const unsigned int avb_magic_pins[] = {
1810 RCAR_GP_PIN(2, 14),
1811};
1812static const unsigned int avb_magic_mux[] = {
1813 AVB_MAGIC_MARK,
1814};
1815static const unsigned int avb_phy_int_pins[] = {
1816 RCAR_GP_PIN(2, 15),
1817};
1818static const unsigned int avb_phy_int_mux[] = {
1819 AVB_PHY_INT_MARK,
1820};
1821static const unsigned int avb_mdio_pins[] = {
1822 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1823};
1824static const unsigned int avb_mdio_mux[] = {
1825 AVB_MDC_MARK, AVB_MDIO_MARK,
1826};
1827static const unsigned int avb_mii_pins[] = {
1828 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1829 RCAR_GP_PIN(0, 11),
1830
1831 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1832 RCAR_GP_PIN(2, 2),
1833
1834 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1835 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
1836 RCAR_GP_PIN(3, 12),
1837};
1838static const unsigned int avb_mii_mux[] = {
1839 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1840 AVB_TXD3_MARK,
1841
1842 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1843 AVB_RXD3_MARK,
1844
1845 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1846 AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
1847 AVB_COL_MARK,
1848};
1849static const unsigned int avb_gmii_pins[] = {
1850 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1851 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1852 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1853
1854 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1855 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1856 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1857
1858 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1859 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1860 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1861 RCAR_GP_PIN(3, 12),
1862};
1863static const unsigned int avb_gmii_mux[] = {
1864 AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1865 AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1866 AVB_TXD6_MARK, AVB_TXD7_MARK,
1867
1868 AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1869 AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1870 AVB_RXD6_MARK, AVB_RXD7_MARK,
1871
1872 AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1873 AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1874 AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1875 AVB_COL_MARK,
1876};
1802/* - DU RGB ----------------------------------------------------------------- */ 1877/* - DU RGB ----------------------------------------------------------------- */
1803static const unsigned int du_rgb666_pins[] = { 1878static const unsigned int du_rgb666_pins[] = {
1804 /* R[7:2], G[7:2], B[7:2] */ 1879 /* R[7:2], G[7:2], B[7:2] */
@@ -3823,6 +3898,12 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3823 SH_PFC_PIN_GROUP(audio_clkout_b), 3898 SH_PFC_PIN_GROUP(audio_clkout_b),
3824 SH_PFC_PIN_GROUP(audio_clkout_c), 3899 SH_PFC_PIN_GROUP(audio_clkout_c),
3825 SH_PFC_PIN_GROUP(audio_clkout_d), 3900 SH_PFC_PIN_GROUP(audio_clkout_d),
3901 SH_PFC_PIN_GROUP(avb_link),
3902 SH_PFC_PIN_GROUP(avb_magic),
3903 SH_PFC_PIN_GROUP(avb_phy_int),
3904 SH_PFC_PIN_GROUP(avb_mdio),
3905 SH_PFC_PIN_GROUP(avb_mii),
3906 SH_PFC_PIN_GROUP(avb_gmii),
3826 SH_PFC_PIN_GROUP(du_rgb666), 3907 SH_PFC_PIN_GROUP(du_rgb666),
3827 SH_PFC_PIN_GROUP(du_rgb888), 3908 SH_PFC_PIN_GROUP(du_rgb888),
3828 SH_PFC_PIN_GROUP(du_clk_out_0), 3909 SH_PFC_PIN_GROUP(du_clk_out_0),
@@ -4101,6 +4182,15 @@ static const char * const audio_clk_groups[] = {
4101 "audio_clkout_d", 4182 "audio_clkout_d",
4102}; 4183};
4103 4184
4185static const char * const avb_groups[] = {
4186 "avb_link",
4187 "avb_magic",
4188 "avb_phy_int",
4189 "avb_mdio",
4190 "avb_mii",
4191 "avb_gmii",
4192};
4193
4104static const char * const du_groups[] = { 4194static const char * const du_groups[] = {
4105 "du_rgb666", 4195 "du_rgb666",
4106 "du_rgb888", 4196 "du_rgb888",
@@ -4507,6 +4597,7 @@ static const char * const vin3_groups[] = {
4507 4597
4508static const struct sh_pfc_function pinmux_functions[] = { 4598static const struct sh_pfc_function pinmux_functions[] = {
4509 SH_PFC_FUNCTION(audio_clk), 4599 SH_PFC_FUNCTION(audio_clk),
4600 SH_PFC_FUNCTION(avb),
4510 SH_PFC_FUNCTION(du), 4601 SH_PFC_FUNCTION(du),
4511 SH_PFC_FUNCTION(du0), 4602 SH_PFC_FUNCTION(du0),
4512 SH_PFC_FUNCTION(du1), 4603 SH_PFC_FUNCTION(du1),
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index c83728626906..c7508d5f6886 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -69,9 +69,10 @@ struct pinmux_func {
69}; 69};
70 70
71struct pinmux_cfg_reg { 71struct pinmux_cfg_reg {
72 unsigned long reg, reg_width, field_width; 72 u32 reg;
73 u8 reg_width, field_width;
73 const u16 *enum_ids; 74 const u16 *enum_ids;
74 const unsigned long *var_field_width; 75 const u8 *var_field_width;
75}; 76};
76 77
77#define PINMUX_CFG_REG(name, r, r_width, f_width) \ 78#define PINMUX_CFG_REG(name, r, r_width, f_width) \
@@ -80,12 +81,13 @@ struct pinmux_cfg_reg {
80 81
81#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ 82#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
82 .reg = r, .reg_width = r_width, \ 83 .reg = r, .reg_width = r_width, \
83 .var_field_width = (const unsigned long [r_width]) \ 84 .var_field_width = (const u8 [r_width]) \
84 { var_fw0, var_fwn, 0 }, \ 85 { var_fw0, var_fwn, 0 }, \
85 .enum_ids = (const u16 []) 86 .enum_ids = (const u16 [])
86 87
87struct pinmux_data_reg { 88struct pinmux_data_reg {
88 unsigned long reg, reg_width; 89 u32 reg;
90 u8 reg_width;
89 const u16 *enum_ids; 91 const u16 *enum_ids;
90}; 92};
91 93
@@ -148,7 +150,7 @@ struct sh_pfc_soc_info {
148 const struct pinmux_irq *gpio_irq; 150 const struct pinmux_irq *gpio_irq;
149 unsigned int gpio_irq_size; 151 unsigned int gpio_irq_size;
150 152
151 unsigned long unlock_reg; 153 u32 unlock_reg;
152}; 154};
153 155
154/* ----------------------------------------------------------------------------- 156/* -----------------------------------------------------------------------------
@@ -302,20 +304,21 @@ struct sh_pfc_soc_info {
302/* 304/*
303 * PORTnCR macro 305 * PORTnCR macro
304 */ 306 */
305#define _PCRH(in, in_pd, in_pu, out) \
306 0, (out), (in), 0, \
307 0, 0, 0, 0, \
308 0, 0, (in_pd), 0, \
309 0, 0, (in_pu), 0
310
311#define PORTCR(nr, reg) \ 307#define PORTCR(nr, reg) \
312 { \ 308 { \
313 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ 309 PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
314 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \ 310 /* PULMD[1:0], handled by .set_bias() */ \
315 PORT##nr##_FN0, PORT##nr##_FN1, \ 311 0, 0, 0, 0, \
316 PORT##nr##_FN2, PORT##nr##_FN3, \ 312 /* IE and OE */ \
317 PORT##nr##_FN4, PORT##nr##_FN5, \ 313 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
318 PORT##nr##_FN6, PORT##nr##_FN7 } \ 314 /* SEC, not supported */ \
315 0, 0, \
316 /* PTMD[2:0] */ \
317 PORT##nr##_FN0, PORT##nr##_FN1, \
318 PORT##nr##_FN2, PORT##nr##_FN3, \
319 PORT##nr##_FN4, PORT##nr##_FN5, \
320 PORT##nr##_FN6, PORT##nr##_FN7 \
321 } \
319 } 322 }
320 323
321#endif /* __SH_PFC_H */ 324#endif /* __SH_PFC_H */
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 2a1f07249b2f..e2efbbae4061 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -39,10 +39,9 @@ struct sirfsoc_gpio_bank {
39struct sirfsoc_gpio_chip { 39struct sirfsoc_gpio_chip {
40 struct of_mm_gpio_chip chip; 40 struct of_mm_gpio_chip chip;
41 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS]; 41 struct sirfsoc_gpio_bank sgpio_bank[SIRFSOC_GPIO_NO_OF_BANKS];
42 spinlock_t lock;
42}; 43};
43 44
44static DEFINE_SPINLOCK(sgpio_lock);
45
46static struct sirfsoc_pin_group *sirfsoc_pin_groups; 45static struct sirfsoc_pin_group *sirfsoc_pin_groups;
47static int sirfsoc_pingrp_cnt; 46static int sirfsoc_pingrp_cnt;
48 47
@@ -427,13 +426,13 @@ static void sirfsoc_gpio_irq_ack(struct irq_data *d)
427 426
428 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 427 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
429 428
430 spin_lock_irqsave(&sgpio_lock, flags); 429 spin_lock_irqsave(&sgpio->lock, flags);
431 430
432 val = readl(sgpio->chip.regs + offset); 431 val = readl(sgpio->chip.regs + offset);
433 432
434 writel(val, sgpio->chip.regs + offset); 433 writel(val, sgpio->chip.regs + offset);
435 434
436 spin_unlock_irqrestore(&sgpio_lock, flags); 435 spin_unlock_irqrestore(&sgpio->lock, flags);
437} 436}
438 437
439static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio, 438static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
@@ -445,14 +444,14 @@ static void __sirfsoc_gpio_irq_mask(struct sirfsoc_gpio_chip *sgpio,
445 444
446 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 445 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
447 446
448 spin_lock_irqsave(&sgpio_lock, flags); 447 spin_lock_irqsave(&sgpio->lock, flags);
449 448
450 val = readl(sgpio->chip.regs + offset); 449 val = readl(sgpio->chip.regs + offset);
451 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK; 450 val &= ~SIRFSOC_GPIO_CTL_INTR_EN_MASK;
452 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; 451 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
453 writel(val, sgpio->chip.regs + offset); 452 writel(val, sgpio->chip.regs + offset);
454 453
455 spin_unlock_irqrestore(&sgpio_lock, flags); 454 spin_unlock_irqrestore(&sgpio->lock, flags);
456} 455}
457 456
458static void sirfsoc_gpio_irq_mask(struct irq_data *d) 457static void sirfsoc_gpio_irq_mask(struct irq_data *d)
@@ -475,14 +474,14 @@ static void sirfsoc_gpio_irq_unmask(struct irq_data *d)
475 474
476 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 475 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
477 476
478 spin_lock_irqsave(&sgpio_lock, flags); 477 spin_lock_irqsave(&sgpio->lock, flags);
479 478
480 val = readl(sgpio->chip.regs + offset); 479 val = readl(sgpio->chip.regs + offset);
481 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; 480 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK;
482 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK; 481 val |= SIRFSOC_GPIO_CTL_INTR_EN_MASK;
483 writel(val, sgpio->chip.regs + offset); 482 writel(val, sgpio->chip.regs + offset);
484 483
485 spin_unlock_irqrestore(&sgpio_lock, flags); 484 spin_unlock_irqrestore(&sgpio->lock, flags);
486} 485}
487 486
488static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type) 487static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
@@ -496,7 +495,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
496 495
497 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 496 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
498 497
499 spin_lock_irqsave(&sgpio_lock, flags); 498 spin_lock_irqsave(&sgpio->lock, flags);
500 499
501 val = readl(sgpio->chip.regs + offset); 500 val = readl(sgpio->chip.regs + offset);
502 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK); 501 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
@@ -533,7 +532,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
533 532
534 writel(val, sgpio->chip.regs + offset); 533 writel(val, sgpio->chip.regs + offset);
535 534
536 spin_unlock_irqrestore(&sgpio_lock, flags); 535 spin_unlock_irqrestore(&sgpio->lock, flags);
537 536
538 return 0; 537 return 0;
539} 538}
@@ -568,7 +567,7 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
568 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id)); 567 status = readl(sgpio->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
569 if (!status) { 568 if (!status) {
570 printk(KERN_WARNING 569 printk(KERN_WARNING
571 "%s: gpio id %d status %#x no interrupt is flaged\n", 570 "%s: gpio id %d status %#x no interrupt is flagged\n",
572 __func__, bank->id, status); 571 __func__, bank->id, status);
573 handle_bad_irq(irq, desc); 572 handle_bad_irq(irq, desc);
574 return; 573 return;
@@ -697,11 +696,11 @@ static int sirfsoc_gpio_direction_output(struct gpio_chip *chip,
697 696
698 offset = SIRFSOC_GPIO_CTRL(bank->id, idx); 697 offset = SIRFSOC_GPIO_CTRL(bank->id, idx);
699 698
700 spin_lock_irqsave(&sgpio_lock, flags); 699 spin_lock_irqsave(&sgpio->lock, flags);
701 700
702 sirfsoc_gpio_set_output(sgpio, bank, offset, value); 701 sirfsoc_gpio_set_output(sgpio, bank, offset, value);
703 702
704 spin_unlock_irqrestore(&sgpio_lock, flags); 703 spin_unlock_irqrestore(&sgpio->lock, flags);
705 704
706 return 0; 705 return 0;
707} 706}
@@ -793,6 +792,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
793 sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL); 792 sgpio = devm_kzalloc(&pdev->dev, sizeof(*sgpio), GFP_KERNEL);
794 if (!sgpio) 793 if (!sgpio)
795 return -ENOMEM; 794 return -ENOMEM;
795 spin_lock_init(&sgpio->lock);
796 796
797 regs = of_iomap(np, 0); 797 regs = of_iomap(np, 0);
798 if (!regs) 798 if (!regs)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 3c68a8e5e0dd..7376a97b5e65 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
@@ -1020,7 +1020,7 @@ static int sun4i_a10_pinctrl_probe(struct platform_device *pdev)
1020 &sun4i_a10_pinctrl_data); 1020 &sun4i_a10_pinctrl_data);
1021} 1021}
1022 1022
1023static struct of_device_id sun4i_a10_pinctrl_match[] = { 1023static const struct of_device_id sun4i_a10_pinctrl_match[] = {
1024 { .compatible = "allwinner,sun4i-a10-pinctrl", }, 1024 { .compatible = "allwinner,sun4i-a10-pinctrl", },
1025 {} 1025 {}
1026}; 1026};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
index 45a351affa59..63676617bc59 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a10s.c
@@ -670,7 +670,7 @@ static int sun5i_a10s_pinctrl_probe(struct platform_device *pdev)
670 &sun5i_a10s_pinctrl_data); 670 &sun5i_a10s_pinctrl_data);
671} 671}
672 672
673static struct of_device_id sun5i_a10s_pinctrl_match[] = { 673static const struct of_device_id sun5i_a10s_pinctrl_match[] = {
674 { .compatible = "allwinner,sun5i-a10s-pinctrl", }, 674 { .compatible = "allwinner,sun5i-a10s-pinctrl", },
675 {} 675 {}
676}; 676};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
index 4bd23471412c..2bb07b38834f 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun5i-a13.c
@@ -388,7 +388,7 @@ static int sun5i_a13_pinctrl_probe(struct platform_device *pdev)
388 &sun5i_a13_pinctrl_data); 388 &sun5i_a13_pinctrl_data);
389} 389}
390 390
391static struct of_device_id sun5i_a13_pinctrl_match[] = { 391static const struct of_device_id sun5i_a13_pinctrl_match[] = {
392 { .compatible = "allwinner,sun5i-a13-pinctrl", }, 392 { .compatible = "allwinner,sun5i-a13-pinctrl", },
393 {} 393 {}
394}; 394};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
index 02174fa57997..9596b0a3df6b 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
@@ -120,7 +120,7 @@ static int sun6i_a31_r_pinctrl_probe(struct platform_device *pdev)
120 return ret; 120 return ret;
121} 121}
122 122
123static struct of_device_id sun6i_a31_r_pinctrl_match[] = { 123static const struct of_device_id sun6i_a31_r_pinctrl_match[] = {
124 { .compatible = "allwinner,sun6i-a31-r-pinctrl", }, 124 { .compatible = "allwinner,sun6i-a31-r-pinctrl", },
125 {} 125 {}
126}; 126};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
index 18038f0d6b52..022863ab0c58 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31.c
@@ -922,7 +922,7 @@ static int sun6i_a31_pinctrl_probe(struct platform_device *pdev)
922 &sun6i_a31_pinctrl_data); 922 &sun6i_a31_pinctrl_data);
923} 923}
924 924
925static struct of_device_id sun6i_a31_pinctrl_match[] = { 925static const struct of_device_id sun6i_a31_pinctrl_match[] = {
926 { .compatible = "allwinner,sun6i-a31-pinctrl", }, 926 { .compatible = "allwinner,sun6i-a31-pinctrl", },
927 {} 927 {}
928}; 928};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
index 9b5a91f610c7..d3725dcd6979 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun6i-a31s.c
@@ -794,7 +794,7 @@ static int sun6i_a31s_pinctrl_probe(struct platform_device *pdev)
794 &sun6i_a31s_pinctrl_data); 794 &sun6i_a31s_pinctrl_data);
795} 795}
796 796
797static struct of_device_id sun6i_a31s_pinctrl_match[] = { 797static const struct of_device_id sun6i_a31s_pinctrl_match[] = {
798 { .compatible = "allwinner,sun6i-a31s-pinctrl", }, 798 { .compatible = "allwinner,sun6i-a31s-pinctrl", },
799 {} 799 {}
800}; 800};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
index 6af6cc8547b0..cf1ce0c02600 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -1045,7 +1045,7 @@ static int sun7i_a20_pinctrl_probe(struct platform_device *pdev)
1045 &sun7i_a20_pinctrl_data); 1045 &sun7i_a20_pinctrl_data);
1046} 1046}
1047 1047
1048static struct of_device_id sun7i_a20_pinctrl_match[] = { 1048static const struct of_device_id sun7i_a20_pinctrl_match[] = {
1049 { .compatible = "allwinner,sun7i-a20-pinctrl", }, 1049 { .compatible = "allwinner,sun7i-a20-pinctrl", },
1050 {} 1050 {}
1051}; 1051};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
index 327e03ff7c4d..056287635873 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c
@@ -119,7 +119,7 @@ static int sun8i_a23_r_pinctrl_probe(struct platform_device *pdev)
119 return ret; 119 return ret;
120} 120}
121 121
122static struct of_device_id sun8i_a23_r_pinctrl_match[] = { 122static const struct of_device_id sun8i_a23_r_pinctrl_match[] = {
123 { .compatible = "allwinner,sun8i-a23-r-pinctrl", }, 123 { .compatible = "allwinner,sun8i-a23-r-pinctrl", },
124 {} 124 {}
125}; 125};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
index 62695c9a92c2..55083d278bb1 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-a23.c
@@ -571,7 +571,7 @@ static int sun8i_a23_pinctrl_probe(struct platform_device *pdev)
571 &sun8i_a23_pinctrl_data); 571 &sun8i_a23_pinctrl_data);
572} 572}
573 573
574static struct of_device_id sun8i_a23_pinctrl_match[] = { 574static const struct of_device_id sun8i_a23_pinctrl_match[] = {
575 { .compatible = "allwinner,sun8i-a23-pinctrl", }, 575 { .compatible = "allwinner,sun8i-a23-pinctrl", },
576 {} 576 {}
577}; 577};
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
index adb29422efc9..1b580ba76453 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
+++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c
@@ -729,7 +729,7 @@ static int sun9i_a80_pinctrl_probe(struct platform_device *pdev)
729 &sun9i_a80_pinctrl_data); 729 &sun9i_a80_pinctrl_data);
730} 730}
731 731
732static struct of_device_id sun9i_a80_pinctrl_match[] = { 732static const struct of_device_id sun9i_a80_pinctrl_match[] = {
733 { .compatible = "allwinner,sun9i-a80-pinctrl", }, 733 { .compatible = "allwinner,sun9i-a80-pinctrl", },
734 {} 734 {}
735}; 735};
diff --git a/drivers/pinctrl/vt8500/pinctrl-vt8500.c b/drivers/pinctrl/vt8500/pinctrl-vt8500.c
index cf8bbc946ff7..ca946b3dbdb4 100644
--- a/drivers/pinctrl/vt8500/pinctrl-vt8500.c
+++ b/drivers/pinctrl/vt8500/pinctrl-vt8500.c
@@ -478,7 +478,7 @@ static int vt8500_pinctrl_remove(struct platform_device *pdev)
478 return wmt_pinctrl_remove(pdev); 478 return wmt_pinctrl_remove(pdev);
479} 479}
480 480
481static struct of_device_id wmt_pinctrl_of_match[] = { 481static const struct of_device_id wmt_pinctrl_of_match[] = {
482 { .compatible = "via,vt8500-pinctrl" }, 482 { .compatible = "via,vt8500-pinctrl" },
483 { /* sentinel */ }, 483 { /* sentinel */ },
484}; 484};
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8505.c b/drivers/pinctrl/vt8500/pinctrl-wm8505.c
index 3f9c32dcb3d0..626fc7ec0174 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wm8505.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8505.c
@@ -509,7 +509,7 @@ static int wm8505_pinctrl_remove(struct platform_device *pdev)
509 return wmt_pinctrl_remove(pdev); 509 return wmt_pinctrl_remove(pdev);
510} 510}
511 511
512static struct of_device_id wmt_pinctrl_of_match[] = { 512static const struct of_device_id wmt_pinctrl_of_match[] = {
513 { .compatible = "wm,wm8505-pinctrl" }, 513 { .compatible = "wm,wm8505-pinctrl" },
514 { /* sentinel */ }, 514 { /* sentinel */ },
515}; 515};
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8650.c b/drivers/pinctrl/vt8500/pinctrl-wm8650.c
index 4e80f98c2ba7..8953aba8bfc2 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wm8650.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8650.c
@@ -347,7 +347,7 @@ static int wm8650_pinctrl_remove(struct platform_device *pdev)
347 return wmt_pinctrl_remove(pdev); 347 return wmt_pinctrl_remove(pdev);
348} 348}
349 349
350static struct of_device_id wmt_pinctrl_of_match[] = { 350static const struct of_device_id wmt_pinctrl_of_match[] = {
351 { .compatible = "wm,wm8650-pinctrl" }, 351 { .compatible = "wm,wm8650-pinctrl" },
352 { /* sentinel */ }, 352 { /* sentinel */ },
353}; 353};
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8750.c b/drivers/pinctrl/vt8500/pinctrl-wm8750.c
index 47b52a7cacac..c79053d430db 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wm8750.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8750.c
@@ -386,7 +386,7 @@ static int wm8750_pinctrl_remove(struct platform_device *pdev)
386 return wmt_pinctrl_remove(pdev); 386 return wmt_pinctrl_remove(pdev);
387} 387}
388 388
389static struct of_device_id wmt_pinctrl_of_match[] = { 389static const struct of_device_id wmt_pinctrl_of_match[] = {
390 { .compatible = "wm,wm8750-pinctrl" }, 390 { .compatible = "wm,wm8750-pinctrl" },
391 { /* sentinel */ }, 391 { /* sentinel */ },
392}; 392};
diff --git a/drivers/pinctrl/vt8500/pinctrl-wm8850.c b/drivers/pinctrl/vt8500/pinctrl-wm8850.c
index 8bbb38c931f6..f232b163c735 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wm8850.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wm8850.c
@@ -365,7 +365,7 @@ static int wm8850_pinctrl_remove(struct platform_device *pdev)
365 return wmt_pinctrl_remove(pdev); 365 return wmt_pinctrl_remove(pdev);
366} 366}
367 367
368static struct of_device_id wmt_pinctrl_of_match[] = { 368static const struct of_device_id wmt_pinctrl_of_match[] = {
369 { .compatible = "wm,wm8850-pinctrl" }, 369 { .compatible = "wm,wm8850-pinctrl" },
370 { /* sentinel */ }, 370 { /* sentinel */ },
371}; 371};
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 19:05:02 -0500