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authorShiraz Hashim <shiraz.hashim@st.com>2012-11-07 09:37:25 -0500
committerLinus Walleij <linus.walleij@linaro.org>2012-11-11 13:36:04 -0500
commit826d6ca8f955c7a902e775acef3bdbfc93695b04 (patch)
treeacfea21f3a3d52e0cfc706028394a4283fa6eb1b /drivers/pinctrl/spear/pinctrl-spear.h
parent6bb0700bfe124f3ee245da24b5bb35152d2e6bfc (diff)
pinctrl: SPEAr: Add SoC specific gpio configuration routines
Different SPEAr SoCs have different approach to configure pins as gpios. Some configure a group of gpios with single register bit and others have one bit per gpio pin. Only earlier one is implemented till now, this patch adds support for later one. Here we add callbacks to SoC specific code to configure gpios in gpio_request_enable(). That will do additional SoC specific configuration to enable gpio pins. We also implement this callback for SPEAr1340 in this patch. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/spear/pinctrl-spear.h')
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h
index 94f142c10c19..b06332719b2c 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.h
+++ b/drivers/pinctrl/spear/pinctrl-spear.h
@@ -13,11 +13,13 @@
13#define __PINMUX_SPEAR_H__ 13#define __PINMUX_SPEAR_H__
14 14
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16#include <linux/io.h>
16#include <linux/pinctrl/pinctrl.h> 17#include <linux/pinctrl/pinctrl.h>
17#include <linux/types.h> 18#include <linux/types.h>
18 19
19struct platform_device; 20struct platform_device;
20struct device; 21struct device;
22struct spear_pmx;
21 23
22/** 24/**
23 * struct spear_pmx_mode - SPEAr pmx mode 25 * struct spear_pmx_mode - SPEAr pmx mode
@@ -155,6 +157,8 @@ struct spear_pinctrl_machdata {
155 struct spear_pingroup **groups; 157 struct spear_pingroup **groups;
156 unsigned ngroups; 158 unsigned ngroups;
157 struct spear_gpio_pingroup *gpio_pingroups; 159 struct spear_gpio_pingroup *gpio_pingroups;
160 void (*gpio_request_endisable)(struct spear_pmx *pmx, int offset,
161 bool enable);
158 unsigned ngpio_pingroups; 162 unsigned ngpio_pingroups;
159 163
160 bool modes_supported; 164 bool modes_supported;
@@ -178,6 +182,16 @@ struct spear_pmx {
178}; 182};
179 183
180/* exported routines */ 184/* exported routines */
185static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
186{
187 return readl_relaxed(pmx->vbase + reg);
188}
189
190static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
191{
192 writel_relaxed(val, pmx->vbase + reg);
193}
194
181void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); 195void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
182void __devinit 196void __devinit
183pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup, 197pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,