diff options
author | Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com> | 2013-05-22 06:55:08 -0400 |
---|---|---|
committer | Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2013-07-29 09:52:07 -0400 |
commit | 9f2edd4113daefb5280fb5f06085fa2069ba0d2b (patch) | |
tree | 0ade8e1b79e7ed737cd59677fbeab102a75c5b26 /drivers/pinctrl/sh-pfc | |
parent | bcec7475d84c16c62d5310da96d1e34b9edc750a (diff) |
sh-pfc: r8a7790: Remove deprecated Ethernet MII/RMII pins
The pins have been removed from the datasheet, remove them here as well.
Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'drivers/pinctrl/sh-pfc')
-rw-r--r-- | drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 224 |
1 files changed, 94 insertions, 130 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 6adaa85b9036..5fdb715ee303 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c | |||
@@ -171,15 +171,15 @@ enum { | |||
171 | FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, | 171 | FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, |
172 | FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, | 172 | FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, |
173 | FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, | 173 | FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, |
174 | FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, | 174 | FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, |
175 | FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, | 175 | FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, |
176 | 176 | ||
177 | /* IPSR1 */ | 177 | /* IPSR1 */ |
178 | FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, | 178 | FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, |
179 | FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, | 179 | FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, |
180 | FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, | 180 | FN_SCIFA1_TXD_C, FN_AVB_TXD2, |
181 | FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, | 181 | FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, |
182 | FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, | 182 | FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, |
183 | FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, | 183 | FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, |
184 | FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, | 184 | FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, |
185 | FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, | 185 | FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, |
@@ -266,29 +266,29 @@ enum { | |||
266 | FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, | 266 | FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, |
267 | FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, | 267 | FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, |
268 | FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, | 268 | FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, |
269 | FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, | 269 | FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, |
270 | FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, | 270 | FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, |
271 | FN_I2C2_SCL_E, FN_ETH_RX_ER, FN_RMII_RX_ER, | 271 | FN_I2C2_SCL_E, FN_ETH_RX_ER, |
272 | FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, | 272 | FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, |
273 | FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, FN_RMII_RXD0, | 273 | FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, |
274 | FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, | 274 | FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, |
275 | FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, | 275 | FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, |
276 | FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, | 276 | FN_HRX0_E, FN_STP_ISSYNC_0_B, |
277 | FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, | 277 | FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, |
278 | FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, | 278 | FN_RX1_E, FN_ETH_LINK, FN_HTX0_E, |
279 | FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, | 279 | FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, |
280 | FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, | 280 | FN_ETH_REF_CLK, FN_HCTS0_N_E, |
281 | FN_STP_IVCXO27_1_B, FN_HRX0_F, | 281 | FN_STP_IVCXO27_1_B, FN_HRX0_F, |
282 | 282 | ||
283 | /* IPSR7 */ | 283 | /* IPSR7 */ |
284 | FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, | 284 | FN_ETH_MDIO, FN_HRTS0_N_E, |
285 | FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, | 285 | FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, |
286 | FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, | 286 | FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, |
287 | FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, | 287 | FN_ETH_TX_EN, FN_SIM0_CLK_C, |
288 | FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC, | 288 | FN_HRTS0_N_F, FN_ETH_MAGIC, |
289 | FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0, | 289 | FN_SIM0_RST_C, FN_ETH_TXD0, |
290 | FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, | 290 | FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, |
291 | FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, | 291 | FN_ETH_MDC, FN_STP_ISD_1_B, |
292 | FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, | 292 | FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, |
293 | FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, | 293 | FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, |
294 | FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, | 294 | FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, |
@@ -296,26 +296,25 @@ enum { | |||
296 | FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, | 296 | FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, |
297 | FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, | 297 | FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN, |
298 | FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, | 298 | FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, |
299 | FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, | 299 | FN_ATACS00_N, FN_AVB_RXD1, |
300 | FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, | 300 | FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, |
301 | FN_MII_RXD2, | ||
302 | 301 | ||
303 | /* IPSR8 */ | 302 | /* IPSR8 */ |
304 | FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, | 303 | FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, |
305 | FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, | 304 | FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, |
306 | FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, | 305 | FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, |
307 | FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, | 306 | FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, |
308 | FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, | 307 | FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, |
309 | FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, | 308 | FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, |
310 | FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, | 309 | FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, |
311 | FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV, | 310 | FN_VI1_CLK, FN_AVB_RX_DV, |
312 | FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, | 311 | FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, |
313 | FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1, | 312 | FN_AVB_CRS, FN_VI1_DATA1_VI1_B1, |
314 | FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, | 313 | FN_SCIFA1_RXD_D, FN_AVB_MDC, |
315 | FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, | 314 | FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, |
316 | FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, | 315 | FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, |
317 | FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, | 316 | FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, |
318 | FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5, | 317 | FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5, |
319 | FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, | 318 | FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, |
320 | FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, | 319 | FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, |
321 | FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, | 320 | FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, |
@@ -331,13 +330,13 @@ enum { | |||
331 | FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, | 330 | FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, |
332 | FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, | 331 | FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, |
333 | FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, | 332 | FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, |
334 | FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD, | 333 | FN_AVB_TX_EN, FN_SD1_CMD, |
335 | FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, | 334 | FN_AVB_TX_ER, FN_SCIFB0_SCK_B, |
336 | FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, | 335 | FN_SD1_DAT0, FN_AVB_TX_CLK, |
337 | FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, | 336 | FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, |
338 | FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2, | 337 | FN_SCIFB0_TXD_B, FN_SD1_DAT2, |
339 | FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, | 338 | FN_AVB_COL, FN_SCIFB0_CTS_N_B, |
340 | FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, | 339 | FN_SD1_DAT3, FN_AVB_RXD0, |
341 | FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, | 340 | FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, |
342 | FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, | 341 | FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, |
343 | FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, | 342 | FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, |
@@ -551,14 +550,14 @@ enum { | |||
551 | IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, | 550 | IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, |
552 | I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, | 551 | I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, |
553 | VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, | 552 | VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, |
554 | D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK, | 553 | D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, |
555 | VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, | 554 | VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, |
556 | 555 | ||
557 | D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK, | 556 | D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, |
558 | VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, | 557 | VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, |
559 | SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK, | 558 | SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, |
560 | VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, | 559 | VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, |
561 | SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK, | 560 | SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, |
562 | VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, | 561 | VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, |
563 | D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, | 562 | D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, |
564 | VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, | 563 | VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, |
@@ -641,28 +640,28 @@ enum { | |||
641 | DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, | 640 | DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, |
642 | MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, | 641 | MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, |
643 | SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, | 642 | SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, |
644 | ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK, | 643 | ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, |
645 | TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, | 644 | TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, |
646 | I2C2_SCL_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK, | 645 | I2C2_SCL_E_MARK, ETH_RX_ER_MARK, |
647 | STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, | 646 | STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, |
648 | IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK, | 647 | IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, |
649 | STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, | 648 | STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, |
650 | SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, | 649 | SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, |
651 | RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK, | 650 | HRX0_E_MARK, STP_ISSYNC_0_B_MARK, |
652 | TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, | 651 | TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, |
653 | RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK, | 652 | RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK, |
654 | STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, | 653 | STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, |
655 | ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK, | 654 | ETH_REF_CLK_MARK, HCTS0_N_E_MARK, |
656 | STP_IVCXO27_1_B_MARK, HRX0_F_MARK, | 655 | STP_IVCXO27_1_B_MARK, HRX0_F_MARK, |
657 | 656 | ||
658 | ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK, | 657 | ETH_MDIO_MARK, HRTS0_N_E_MARK, |
659 | SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, | 658 | SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, |
660 | RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, | 659 | HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK, |
661 | ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK, | 660 | ETH_TX_EN_MARK, SIM0_CLK_C_MARK, |
662 | HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK, | 661 | HRTS0_N_F_MARK, ETH_MAGIC_MARK, |
663 | SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK, | 662 | SIM0_RST_C_MARK, ETH_TXD0_MARK, |
664 | STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, | 663 | STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, |
665 | ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK, | 664 | ETH_MDC_MARK, STP_ISD_1_B_MARK, |
666 | TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, | 665 | TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, |
667 | SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, | 666 | SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, |
668 | GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, | 667 | GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, |
@@ -670,25 +669,24 @@ enum { | |||
670 | PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, | 669 | PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, |
671 | PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, | 670 | PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK, |
672 | AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, | 671 | AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, |
673 | ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK, | 672 | ATACS00_N_MARK, AVB_RXD1_MARK, |
674 | VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, | 673 | VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, |
675 | MII_RXD2_MARK, | ||
676 | 674 | ||
677 | VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, | 675 | VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, |
678 | MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, | 676 | VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, |
679 | AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, | 677 | AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, |
680 | AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, | 678 | AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, |
681 | AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, | 679 | AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, |
682 | AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, | 680 | AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, |
683 | MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, | 681 | VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, |
684 | MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK, | 682 | VI1_CLK_MARK, AVB_RX_DV_MARK, |
685 | MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, | 683 | VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, |
686 | AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK, | 684 | AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK, |
687 | SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK, | 685 | SCIFA1_RXD_D_MARK, AVB_MDC_MARK, |
688 | VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, | 686 | VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, |
689 | MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, | 687 | VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, |
690 | AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, | 688 | AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, |
691 | AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, | 689 | AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, |
692 | AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, | 690 | AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, |
693 | SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, | 691 | SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, |
694 | SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, | 692 | SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, |
@@ -703,13 +701,13 @@ enum { | |||
703 | MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, | 701 | MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, |
704 | GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, | 702 | GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, |
705 | I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, | 703 | I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, |
706 | AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK, | 704 | AVB_TX_EN_MARK, SD1_CMD_MARK, |
707 | AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK, | 705 | AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK, |
708 | SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK, | 706 | SD1_DAT0_MARK, AVB_TX_CLK_MARK, |
709 | SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, | 707 | SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, |
710 | MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, | 708 | SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, |
711 | AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK, | 709 | AVB_COL_MARK, SCIFB0_CTS_N_B_MARK, |
712 | SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK, | 710 | SD1_DAT3_MARK, AVB_RXD0_MARK, |
713 | SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, | 711 | SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, |
714 | TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, | 712 | TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, |
715 | IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, | 713 | IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, |
@@ -907,7 +905,6 @@ static const pinmux_enum_t pinmux_data[] = { | |||
907 | PINMUX_IPSR_DATA(IP0_30_27, D8), | 905 | PINMUX_IPSR_DATA(IP0_30_27, D8), |
908 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), | 906 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), |
909 | PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), | 907 | PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0), |
910 | PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0), | ||
911 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), | 908 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0), |
912 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), | 909 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1), |
913 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), | 910 | PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), |
@@ -915,21 +912,18 @@ static const pinmux_enum_t pinmux_data[] = { | |||
915 | PINMUX_IPSR_DATA(IP1_3_0, D9), | 912 | PINMUX_IPSR_DATA(IP1_3_0, D9), |
916 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), | 913 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), |
917 | PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), | 914 | PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1), |
918 | PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1), | ||
919 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), | 915 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0), |
920 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), | 916 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1), |
921 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), | 917 | PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), |
922 | PINMUX_IPSR_DATA(IP1_7_4, D10), | 918 | PINMUX_IPSR_DATA(IP1_7_4, D10), |
923 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), | 919 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), |
924 | PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), | 920 | PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2), |
925 | PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2), | ||
926 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), | 921 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0), |
927 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), | 922 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1), |
928 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), | 923 | PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), |
929 | PINMUX_IPSR_DATA(IP1_11_8, D11), | 924 | PINMUX_IPSR_DATA(IP1_11_8, D11), |
930 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), | 925 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), |
931 | PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), | 926 | PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3), |
932 | PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3), | ||
933 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), | 927 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0), |
934 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), | 928 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1), |
935 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), | 929 | PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), |
@@ -1205,28 +1199,24 @@ static const pinmux_enum_t pinmux_data[] = { | |||
1205 | PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), | 1199 | PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), |
1206 | PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), | 1200 | PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), |
1207 | PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), | 1201 | PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV), |
1208 | PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV), | ||
1209 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), | 1202 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), |
1210 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), | 1203 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), |
1211 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), | 1204 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2), |
1212 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), | 1205 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), |
1213 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), | 1206 | PINMUX_IPSR_MODSEL_DATA(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), |
1214 | PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), | 1207 | PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER), |
1215 | PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER), | ||
1216 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), | 1208 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), |
1217 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), | 1209 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), |
1218 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), | 1210 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2), |
1219 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), | 1211 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), |
1220 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), | 1212 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), |
1221 | PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), | 1213 | PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0), |
1222 | PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0), | ||
1223 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), | 1214 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), |
1224 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), | 1215 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), |
1225 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), | 1216 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2), |
1226 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), | 1217 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), |
1227 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), | 1218 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4), |
1228 | PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), | 1219 | PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1), |
1229 | PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1), | ||
1230 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), | 1220 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4), |
1231 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), | 1221 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), |
1232 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), | 1222 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), |
@@ -1234,41 +1224,33 @@ static const pinmux_enum_t pinmux_data[] = { | |||
1234 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), | 1224 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), |
1235 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), | 1225 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4), |
1236 | PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), | 1226 | PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK), |
1237 | PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK), | ||
1238 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), | 1227 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4), |
1239 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), | 1228 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), |
1240 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), | 1229 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), |
1241 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), | 1230 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4), |
1242 | PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), | 1231 | PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK), |
1243 | PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK), | ||
1244 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), | 1232 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), |
1245 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), | 1233 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), |
1246 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), | 1234 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5), |
1247 | 1235 | ||
1248 | PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), | 1236 | PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO), |
1249 | PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO), | ||
1250 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), | 1237 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), |
1251 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), | 1238 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2), |
1252 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), | 1239 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), |
1253 | PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), | 1240 | PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1), |
1254 | PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1), | ||
1255 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), | 1241 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4), |
1256 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), | 1242 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2), |
1257 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5), | 1243 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5), |
1258 | PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), | 1244 | PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN), |
1259 | PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN), | ||
1260 | PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), | 1245 | PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), |
1261 | PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), | 1246 | PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), |
1262 | PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), | 1247 | PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC), |
1263 | PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC), | ||
1264 | PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), | 1248 | PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2), |
1265 | PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), | 1249 | PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0), |
1266 | PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0), | ||
1267 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), | 1250 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), |
1268 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), | 1251 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), |
1269 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), | 1252 | PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), |
1270 | PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), | 1253 | PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC), |
1271 | PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC), | ||
1272 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), | 1254 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), |
1273 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), | 1255 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), |
1274 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), | 1256 | PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), |
@@ -1294,16 +1276,13 @@ static const pinmux_enum_t pinmux_data[] = { | |||
1294 | PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), | 1276 | PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0), |
1295 | PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), | 1277 | PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N), |
1296 | PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), | 1278 | PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1), |
1297 | PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1), | ||
1298 | PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), | 1279 | PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), |
1299 | PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), | 1280 | PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N), |
1300 | PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), | 1281 | PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2), |
1301 | PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2), | ||
1302 | 1282 | ||
1303 | PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), | 1283 | PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), |
1304 | PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), | 1284 | PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N), |
1305 | PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), | 1285 | PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3), |
1306 | PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3), | ||
1307 | PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), | 1286 | PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), |
1308 | PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), | 1287 | PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N), |
1309 | PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), | 1288 | PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4), |
@@ -1318,32 +1297,25 @@ static const pinmux_enum_t pinmux_data[] = { | |||
1318 | PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), | 1297 | PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7), |
1319 | PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), | 1298 | PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), |
1320 | PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), | 1299 | PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER), |
1321 | PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER), | ||
1322 | PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), | 1300 | PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), |
1323 | PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), | 1301 | PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK), |
1324 | PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK), | ||
1325 | PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), | 1302 | PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0), |
1326 | PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), | 1303 | PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV), |
1327 | PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV), | ||
1328 | PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), | 1304 | PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), |
1329 | PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), | 1305 | PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), |
1330 | PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), | 1306 | PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS), |
1331 | PINMUX_IPSR_DATA(IP8_17_16, MII_CRS), | ||
1332 | PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), | 1307 | PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), |
1333 | PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), | 1308 | PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), |
1334 | PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), | 1309 | PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC), |
1335 | PINMUX_IPSR_DATA(IP8_19_18, MII_MDC), | ||
1336 | PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), | 1310 | PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), |
1337 | PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), | 1311 | PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), |
1338 | PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), | 1312 | PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO), |
1339 | PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO), | ||
1340 | PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), | 1313 | PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), |
1341 | PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), | 1314 | PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), |
1342 | PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), | 1315 | PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK), |
1343 | PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), | 1316 | PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), |
1344 | PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), | 1317 | PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), |
1345 | PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), | 1318 | PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC), |
1346 | PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC), | ||
1347 | PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), | 1319 | PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), |
1348 | PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3), | 1320 | PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3), |
1349 | PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), | 1321 | PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), |
@@ -1386,26 +1358,20 @@ static const pinmux_enum_t pinmux_data[] = { | |||
1386 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), | 1358 | PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), |
1387 | PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), | 1359 | PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK), |
1388 | PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), | 1360 | PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN), |
1389 | PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN), | ||
1390 | PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), | 1361 | PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD), |
1391 | PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), | 1362 | PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER), |
1392 | PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER), | ||
1393 | PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), | 1363 | PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), |
1394 | PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), | 1364 | PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0), |
1395 | PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), | 1365 | PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK), |
1396 | PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK), | ||
1397 | PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), | 1366 | PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), |
1398 | PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), | 1367 | PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1), |
1399 | PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), | 1368 | PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK), |
1400 | PINMUX_IPSR_DATA(IP9_23_22, MII_LINK), | ||
1401 | PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), | 1369 | PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), |
1402 | PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), | 1370 | PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2), |
1403 | PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), | 1371 | PINMUX_IPSR_DATA(IP9_25_24, AVB_COL), |
1404 | PINMUX_IPSR_DATA(IP9_25_24, MII_COL), | ||
1405 | PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), | 1372 | PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), |
1406 | PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), | 1373 | PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3), |
1407 | PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), | 1374 | PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0), |
1408 | PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0), | ||
1409 | PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), | 1375 | PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), |
1410 | PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), | 1376 | PINMUX_IPSR_DATA(IP9_31_28, SD1_CD), |
1411 | PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), | 1377 | PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6), |
@@ -3257,7 +3223,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { | |||
3257 | /* IP0_31 [1] */ | 3223 | /* IP0_31 [1] */ |
3258 | 0, 0, | 3224 | 0, 0, |
3259 | /* IP0_30_27 [4] */ | 3225 | /* IP0_30_27 [4] */ |
3260 | FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0, | 3226 | FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0, |
3261 | FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, | 3227 | FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, |
3262 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | 3228 | 0, 0, 0, 0, 0, 0, 0, 0, 0, |
3263 | /* IP0_26_23 [4] */ | 3229 | /* IP0_26_23 [4] */ |
@@ -3313,15 +3279,15 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { | |||
3313 | FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, | 3279 | FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, |
3314 | 0, 0, | 3280 | 0, 0, |
3315 | /* IP1_11_8 [4] */ | 3281 | /* IP1_11_8 [4] */ |
3316 | FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3, | 3282 | FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0, |
3317 | FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, | 3283 | FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, |
3318 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | 3284 | 0, 0, 0, 0, 0, 0, 0, 0, 0, |
3319 | /* IP1_7_4 [4] */ | 3285 | /* IP1_7_4 [4] */ |
3320 | FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2, | 3286 | FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0, |
3321 | FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, | 3287 | FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, |
3322 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | 3288 | 0, 0, 0, 0, 0, 0, 0, 0, 0, |
3323 | /* IP1_3_0 [4] */ | 3289 | /* IP1_3_0 [4] */ |
3324 | FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1, | 3290 | FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, |
3325 | FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, | 3291 | FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, |
3326 | 0, 0, 0, 0, 0, 0, 0, 0, 0, } | 3292 | 0, 0, 0, 0, 0, 0, 0, 0, 0, } |
3327 | }, | 3293 | }, |
@@ -3461,22 +3427,22 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { | |||
3461 | { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, | 3427 | { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, |
3462 | 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { | 3428 | 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { |
3463 | /* IP6_31_29 [3] */ | 3429 | /* IP6_31_29 [3] */ |
3464 | FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E, | 3430 | FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, |
3465 | FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, | 3431 | FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, |
3466 | /* IP6_28_26 [3] */ | 3432 | /* IP6_28_26 [3] */ |
3467 | FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E, | 3433 | FN_ETH_LINK, 0, FN_HTX0_E, |
3468 | FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, | 3434 | FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, |
3469 | /* IP6_25_23 [3] */ | 3435 | /* IP6_25_23 [3] */ |
3470 | FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B, | 3436 | FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B, |
3471 | FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, | 3437 | FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, |
3472 | /* IP6_22_20 [3] */ | 3438 | /* IP6_22_20 [3] */ |
3473 | FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, | 3439 | FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, |
3474 | FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, | 3440 | FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, |
3475 | /* IP6_19_17 [3] */ | 3441 | /* IP6_19_17 [3] */ |
3476 | FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B, | 3442 | FN_ETH_RX_ER, 0, FN_STP_ISD_0_B, |
3477 | FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, | 3443 | FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, |
3478 | /* IP6_16_14 [3] */ | 3444 | /* IP6_16_14 [3] */ |
3479 | FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B, | 3445 | FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B, |
3480 | FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, | 3446 | FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, |
3481 | FN_I2C2_SCL_E, 0, | 3447 | FN_I2C2_SCL_E, 0, |
3482 | /* IP6_13_11 [3] */ | 3448 | /* IP6_13_11 [3] */ |
@@ -3499,10 +3465,9 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { | |||
3499 | /* IP7_31 [1] */ | 3465 | /* IP7_31 [1] */ |
3500 | 0, 0, | 3466 | 0, 0, |
3501 | /* IP7_30_29 [2] */ | 3467 | /* IP7_30_29 [2] */ |
3502 | FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, | 3468 | FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0, |
3503 | FN_MII_RXD2, | ||
3504 | /* IP7_28_27 [2] */ | 3469 | /* IP7_28_27 [2] */ |
3505 | FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1, | 3470 | FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0, |
3506 | /* IP7_26_25 [2] */ | 3471 | /* IP7_26_25 [2] */ |
3507 | FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, | 3472 | FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, |
3508 | /* IP7_24_22 [3] */ | 3473 | /* IP7_24_22 [3] */ |
@@ -3515,20 +3480,20 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { | |||
3515 | FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, | 3480 | FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, |
3516 | FN_GLO_SS_C, 0, 0, 0, | 3481 | FN_GLO_SS_C, 0, 0, 0, |
3517 | /* IP7_15_13 [3] */ | 3482 | /* IP7_15_13 [3] */ |
3518 | FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B, | 3483 | FN_ETH_MDC, 0, FN_STP_ISD_1_B, |
3519 | FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, | 3484 | FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, |
3520 | /* IP7_12_10 [3] */ | 3485 | /* IP7_12_10 [3] */ |
3521 | FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, | 3486 | FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, |
3522 | FN_GLO_SCLK_C, 0, 0, 0, | 3487 | FN_GLO_SCLK_C, 0, 0, 0, |
3523 | /* IP7_9_8 [2] */ | 3488 | /* IP7_9_8 [2] */ |
3524 | FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0, | 3489 | FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0, |
3525 | /* IP7_7_6 [2] */ | 3490 | /* IP7_7_6 [2] */ |
3526 | FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F, | 3491 | FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F, |
3527 | /* IP7_5_3 [3] */ | 3492 | /* IP7_5_3 [3] */ |
3528 | FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, | 3493 | FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F, |
3529 | 0, 0, 0, | 3494 | 0, 0, 0, |
3530 | /* IP7_2_0 [3] */ | 3495 | /* IP7_2_0 [3] */ |
3531 | FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E, | 3496 | FN_ETH_MDIO, 0, FN_HRTS0_N_E, |
3532 | FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } | 3497 | FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } |
3533 | }, | 3498 | }, |
3534 | { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, | 3499 | { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, |
@@ -3546,22 +3511,21 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { | |||
3546 | FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, | 3511 | FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, |
3547 | /* IP8_25_24 [2] */ | 3512 | /* IP8_25_24 [2] */ |
3548 | FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, | 3513 | FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, |
3549 | FN_AVB_MAGIC, FN_MII_MAGIC, | 3514 | FN_AVB_MAGIC, 0, |
3550 | /* IP8_23_22 [2] */ | 3515 | /* IP8_23_22 [2] */ |
3551 | FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, | 3516 | FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, |
3552 | /* IP8_21_20 [2] */ | 3517 | /* IP8_21_20 [2] */ |
3553 | FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, | 3518 | FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0, |
3554 | FN_MII_MDIO, | ||
3555 | /* IP8_19_18 [2] */ | 3519 | /* IP8_19_18 [2] */ |
3556 | FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC, | 3520 | FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0, |
3557 | /* IP8_17_16 [2] */ | 3521 | /* IP8_17_16 [2] */ |
3558 | FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS, | 3522 | FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0, |
3559 | /* IP8_15_14 [2] */ | 3523 | /* IP8_15_14 [2] */ |
3560 | FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0, | 3524 | FN_VI1_CLK, FN_AVB_RX_DV, 0, 0, |
3561 | /* IP8_13_12 [2] */ | 3525 | /* IP8_13_12 [2] */ |
3562 | FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0, | 3526 | FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0, |
3563 | /* IP8_11_10 [2] */ | 3527 | /* IP8_11_10 [2] */ |
3564 | FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0, | 3528 | FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0, |
3565 | /* IP8_9_8 [2] */ | 3529 | /* IP8_9_8 [2] */ |
3566 | FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, | 3530 | FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, |
3567 | /* IP8_7_6 [2] */ | 3531 | /* IP8_7_6 [2] */ |
@@ -3571,7 +3535,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { | |||
3571 | /* IP8_3_2 [2] */ | 3535 | /* IP8_3_2 [2] */ |
3572 | FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, | 3536 | FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, |
3573 | /* IP8_1_0 [2] */ | 3537 | /* IP8_1_0 [2] */ |
3574 | FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, } | 3538 | FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } |
3575 | }, | 3539 | }, |
3576 | { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, | 3540 | { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, |
3577 | 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { | 3541 | 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { |
@@ -3580,17 +3544,17 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = { | |||
3580 | FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, | 3544 | FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, |
3581 | FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, | 3545 | FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, |
3582 | /* IP9_27_26 [2] */ | 3546 | /* IP9_27_26 [2] */ |
3583 | FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B, | 3547 | FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B, |
3584 | /* IP9_25_24 [2] */ | 3548 | /* IP9_25_24 [2] */ |
3585 | FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B, | 3549 | FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B, |
3586 | /* IP9_23_22 [2] */ | 3550 | /* IP9_23_22 [2] */ |
3587 | FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B, | 3551 | FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B, |
3588 | /* IP9_21_20 [2] */ | 3552 | /* IP9_21_20 [2] */ |
3589 | FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B, | 3553 | FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B, |
3590 | /* IP9_19_18 [2] */ | 3554 | /* IP9_19_18 [2] */ |
3591 | FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B, | 3555 | FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B, |
3592 | /* IP9_17_16 [2] */ | 3556 | /* IP9_17_16 [2] */ |
3593 | FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0, | 3557 | FN_SD1_CLK, FN_AVB_TX_EN, 0, 0, |
3594 | /* IP9_15_12 [4] */ | 3558 | /* IP9_15_12 [4] */ |
3595 | FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, | 3559 | FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, |
3596 | FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, | 3560 | FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, |