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authorLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2013-01-03 07:07:05 -0500
committerLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>2013-03-15 08:34:05 -0400
commit64d87acb278fe90dbe5c69d7b1242eaf670ccc46 (patch)
treeb00c072705703a5b0a24c399a2ae99dbc7d7a27f /drivers/pinctrl/sh-pfc
parentdf68a28d1765d9409262136b1fb098f44aa32642 (diff)
sh-pfc: sh73a0: Add SCIFA and SCIFB pin groups and functions
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/sh-pfc')
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c351
1 files changed, 351 insertions, 0 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index c8b2604eb8f6..4b0a34958fdb 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -2040,6 +2040,253 @@ static const unsigned int lcd2_sys_1_mux[] = {
2040 PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK, 2040 PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2041 LCD2RD__MARK, PORT217_LCD2RS_MARK, 2041 LCD2RD__MARK, PORT217_LCD2RS_MARK,
2042}; 2042};
2043/* - SCIFA0 ----------------------------------------------------------------- */
2044static const unsigned int scifa0_data_pins[] = {
2045 /* RXD, TXD */
2046 43, 17,
2047};
2048static const unsigned int scifa0_data_mux[] = {
2049 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2050};
2051static const unsigned int scifa0_clk_pins[] = {
2052 /* SCK */
2053 16,
2054};
2055static const unsigned int scifa0_clk_mux[] = {
2056 SCIFA0_SCK_MARK,
2057};
2058static const unsigned int scifa0_ctrl_pins[] = {
2059 /* RTS, CTS */
2060 42, 44,
2061};
2062static const unsigned int scifa0_ctrl_mux[] = {
2063 SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
2064};
2065/* - SCIFA1 ----------------------------------------------------------------- */
2066static const unsigned int scifa1_data_pins[] = {
2067 /* RXD, TXD */
2068 228, 225,
2069};
2070static const unsigned int scifa1_data_mux[] = {
2071 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2072};
2073static const unsigned int scifa1_clk_pins[] = {
2074 /* SCK */
2075 226,
2076};
2077static const unsigned int scifa1_clk_mux[] = {
2078 SCIFA1_SCK_MARK,
2079};
2080static const unsigned int scifa1_ctrl_pins[] = {
2081 /* RTS, CTS */
2082 227, 229,
2083};
2084static const unsigned int scifa1_ctrl_mux[] = {
2085 SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2086};
2087/* - SCIFA2 ----------------------------------------------------------------- */
2088static const unsigned int scifa2_data_0_pins[] = {
2089 /* RXD, TXD */
2090 155, 154,
2091};
2092static const unsigned int scifa2_data_0_mux[] = {
2093 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2094};
2095static const unsigned int scifa2_clk_0_pins[] = {
2096 /* SCK */
2097 158,
2098};
2099static const unsigned int scifa2_clk_0_mux[] = {
2100 SCIFA2_SCK1_MARK,
2101};
2102static const unsigned int scifa2_ctrl_0_pins[] = {
2103 /* RTS, CTS */
2104 156, 157,
2105};
2106static const unsigned int scifa2_ctrl_0_mux[] = {
2107 SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2108};
2109static const unsigned int scifa2_data_1_pins[] = {
2110 /* RXD, TXD */
2111 233, 230,
2112};
2113static const unsigned int scifa2_data_1_mux[] = {
2114 SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2115};
2116static const unsigned int scifa2_clk_1_pins[] = {
2117 /* SCK */
2118 232,
2119};
2120static const unsigned int scifa2_clk_1_mux[] = {
2121 SCIFA2_SCK2_MARK,
2122};
2123static const unsigned int scifa2_ctrl_1_pins[] = {
2124 /* RTS, CTS */
2125 234, 231,
2126};
2127static const unsigned int scifa2_ctrl_1_mux[] = {
2128 SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2129};
2130/* - SCIFA3 ----------------------------------------------------------------- */
2131static const unsigned int scifa3_data_pins[] = {
2132 /* RXD, TXD */
2133 108, 110,
2134};
2135static const unsigned int scifa3_data_mux[] = {
2136 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2137};
2138static const unsigned int scifa3_ctrl_pins[] = {
2139 /* RTS, CTS */
2140 109, 107,
2141};
2142static const unsigned int scifa3_ctrl_mux[] = {
2143 SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2144};
2145/* - SCIFA4 ----------------------------------------------------------------- */
2146static const unsigned int scifa4_data_pins[] = {
2147 /* RXD, TXD */
2148 33, 32,
2149};
2150static const unsigned int scifa4_data_mux[] = {
2151 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2152};
2153static const unsigned int scifa4_ctrl_pins[] = {
2154 /* RTS, CTS */
2155 34, 35,
2156};
2157static const unsigned int scifa4_ctrl_mux[] = {
2158 SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2159};
2160/* - SCIFA5 ----------------------------------------------------------------- */
2161static const unsigned int scifa5_data_0_pins[] = {
2162 /* RXD, TXD */
2163 246, 247,
2164};
2165static const unsigned int scifa5_data_0_mux[] = {
2166 PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2167};
2168static const unsigned int scifa5_clk_0_pins[] = {
2169 /* SCK */
2170 248,
2171};
2172static const unsigned int scifa5_clk_0_mux[] = {
2173 PORT248_SCIFA5_SCK_MARK,
2174};
2175static const unsigned int scifa5_ctrl_0_pins[] = {
2176 /* RTS, CTS */
2177 245, 244,
2178};
2179static const unsigned int scifa5_ctrl_0_mux[] = {
2180 PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2181};
2182static const unsigned int scifa5_data_1_pins[] = {
2183 /* RXD, TXD */
2184 195, 196,
2185};
2186static const unsigned int scifa5_data_1_mux[] = {
2187 PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2188};
2189static const unsigned int scifa5_clk_1_pins[] = {
2190 /* SCK */
2191 197,
2192};
2193static const unsigned int scifa5_clk_1_mux[] = {
2194 PORT197_SCIFA5_SCK_MARK,
2195};
2196static const unsigned int scifa5_ctrl_1_pins[] = {
2197 /* RTS, CTS */
2198 194, 193,
2199};
2200static const unsigned int scifa5_ctrl_1_mux[] = {
2201 PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2202};
2203static const unsigned int scifa5_data_2_pins[] = {
2204 /* RXD, TXD */
2205 162, 160,
2206};
2207static const unsigned int scifa5_data_2_mux[] = {
2208 PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2209};
2210static const unsigned int scifa5_clk_2_pins[] = {
2211 /* SCK */
2212 159,
2213};
2214static const unsigned int scifa5_clk_2_mux[] = {
2215 PORT159_SCIFA5_SCK_MARK,
2216};
2217static const unsigned int scifa5_ctrl_2_pins[] = {
2218 /* RTS, CTS */
2219 163, 161,
2220};
2221static const unsigned int scifa5_ctrl_2_mux[] = {
2222 PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2223};
2224/* - SCIFA6 ----------------------------------------------------------------- */
2225static const unsigned int scifa6_pins[] = {
2226 /* TXD */
2227 240,
2228};
2229static const unsigned int scifa6_mux[] = {
2230 SCIFA6_TXD_MARK,
2231};
2232/* - SCIFA7 ----------------------------------------------------------------- */
2233static const unsigned int scifa7_data_pins[] = {
2234 /* RXD, TXD */
2235 12, 18,
2236};
2237static const unsigned int scifa7_data_mux[] = {
2238 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2239};
2240static const unsigned int scifa7_ctrl_pins[] = {
2241 /* RTS, CTS */
2242 19, 13,
2243};
2244static const unsigned int scifa7_ctrl_mux[] = {
2245 SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2246};
2247/* - SCIFB ------------------------------------------------------------------ */
2248static const unsigned int scifb_data_0_pins[] = {
2249 /* RXD, TXD */
2250 162, 160,
2251};
2252static const unsigned int scifb_data_0_mux[] = {
2253 PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2254};
2255static const unsigned int scifb_clk_0_pins[] = {
2256 /* SCK */
2257 159,
2258};
2259static const unsigned int scifb_clk_0_mux[] = {
2260 PORT159_SCIFB_SCK_MARK,
2261};
2262static const unsigned int scifb_ctrl_0_pins[] = {
2263 /* RTS, CTS */
2264 163, 161,
2265};
2266static const unsigned int scifb_ctrl_0_mux[] = {
2267 PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2268};
2269static const unsigned int scifb_data_1_pins[] = {
2270 /* RXD, TXD */
2271 246, 247,
2272};
2273static const unsigned int scifb_data_1_mux[] = {
2274 PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2275};
2276static const unsigned int scifb_clk_1_pins[] = {
2277 /* SCK */
2278 248,
2279};
2280static const unsigned int scifb_clk_1_mux[] = {
2281 PORT248_SCIFB_SCK_MARK,
2282};
2283static const unsigned int scifb_ctrl_1_pins[] = {
2284 /* RTS, CTS */
2285 245, 244,
2286};
2287static const unsigned int scifb_ctrl_1_mux[] = {
2288 PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2289};
2043 2290
2044static const struct sh_pfc_pin_group pinmux_groups[] = { 2291static const struct sh_pfc_pin_group pinmux_groups[] = {
2045 SH_PFC_PIN_GROUP(lcd_data8), 2292 SH_PFC_PIN_GROUP(lcd_data8),
@@ -2062,6 +2309,40 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2062 SH_PFC_PIN_GROUP(lcd2_sync_1), 2309 SH_PFC_PIN_GROUP(lcd2_sync_1),
2063 SH_PFC_PIN_GROUP(lcd2_sys_0), 2310 SH_PFC_PIN_GROUP(lcd2_sys_0),
2064 SH_PFC_PIN_GROUP(lcd2_sys_1), 2311 SH_PFC_PIN_GROUP(lcd2_sys_1),
2312 SH_PFC_PIN_GROUP(scifa0_data),
2313 SH_PFC_PIN_GROUP(scifa0_clk),
2314 SH_PFC_PIN_GROUP(scifa0_ctrl),
2315 SH_PFC_PIN_GROUP(scifa1_data),
2316 SH_PFC_PIN_GROUP(scifa1_clk),
2317 SH_PFC_PIN_GROUP(scifa1_ctrl),
2318 SH_PFC_PIN_GROUP(scifa2_data_0),
2319 SH_PFC_PIN_GROUP(scifa2_clk_0),
2320 SH_PFC_PIN_GROUP(scifa2_ctrl_0),
2321 SH_PFC_PIN_GROUP(scifa2_data_1),
2322 SH_PFC_PIN_GROUP(scifa2_clk_1),
2323 SH_PFC_PIN_GROUP(scifa2_ctrl_1),
2324 SH_PFC_PIN_GROUP(scifa3_data),
2325 SH_PFC_PIN_GROUP(scifa3_ctrl),
2326 SH_PFC_PIN_GROUP(scifa4_data),
2327 SH_PFC_PIN_GROUP(scifa4_ctrl),
2328 SH_PFC_PIN_GROUP(scifa5_data_0),
2329 SH_PFC_PIN_GROUP(scifa5_clk_0),
2330 SH_PFC_PIN_GROUP(scifa5_ctrl_0),
2331 SH_PFC_PIN_GROUP(scifa5_data_1),
2332 SH_PFC_PIN_GROUP(scifa5_clk_1),
2333 SH_PFC_PIN_GROUP(scifa5_ctrl_1),
2334 SH_PFC_PIN_GROUP(scifa5_data_2),
2335 SH_PFC_PIN_GROUP(scifa5_clk_2),
2336 SH_PFC_PIN_GROUP(scifa5_ctrl_2),
2337 SH_PFC_PIN_GROUP(scifa6),
2338 SH_PFC_PIN_GROUP(scifa7_data),
2339 SH_PFC_PIN_GROUP(scifa7_ctrl),
2340 SH_PFC_PIN_GROUP(scifb_data_0),
2341 SH_PFC_PIN_GROUP(scifb_clk_0),
2342 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2343 SH_PFC_PIN_GROUP(scifb_data_1),
2344 SH_PFC_PIN_GROUP(scifb_clk_1),
2345 SH_PFC_PIN_GROUP(scifb_ctrl_1),
2065}; 2346};
2066 2347
2067static const char * const lcd_groups[] = { 2348static const char * const lcd_groups[] = {
@@ -2090,9 +2371,79 @@ static const char * const lcd2_groups[] = {
2090 "lcd2_sys_1", 2371 "lcd2_sys_1",
2091}; 2372};
2092 2373
2374static const char * const scifa0_groups[] = {
2375 "scifa0_data",
2376 "scifa0_clk",
2377 "scifa0_ctrl",
2378};
2379
2380static const char * const scifa1_groups[] = {
2381 "scifa1_data",
2382 "scifa1_clk",
2383 "scifa1_ctrl",
2384};
2385
2386static const char * const scifa2_groups[] = {
2387 "scifa2_data_0",
2388 "scifa2_clk_0",
2389 "scifa2_ctrl_0",
2390 "scifa2_data_1",
2391 "scifa2_clk_1",
2392 "scifa2_ctrl_1",
2393};
2394
2395static const char * const scifa3_groups[] = {
2396 "scifa3_data",
2397 "scifa3_ctrl",
2398};
2399
2400static const char * const scifa4_groups[] = {
2401 "scifa4_data",
2402 "scifa4_ctrl",
2403};
2404
2405static const char * const scifa5_groups[] = {
2406 "scifa5_data_0",
2407 "scifa5_clk_0",
2408 "scifa5_ctrl_0",
2409 "scifa5_data_1",
2410 "scifa5_clk_1",
2411 "scifa5_ctrl_1",
2412 "scifa5_data_2",
2413 "scifa5_clk_2",
2414 "scifa5_ctrl_2",
2415};
2416
2417static const char * const scifa6_groups[] = {
2418 "scifa6",
2419};
2420
2421static const char * const scifa7_groups[] = {
2422 "scifa7_data",
2423 "scifa7_ctrl",
2424};
2425
2426static const char * const scifb_groups[] = {
2427 "scifb_data_0",
2428 "scifb_clk_0",
2429 "scifb_ctrl_0",
2430 "scifb_data_1",
2431 "scifb_clk_1",
2432 "scifb_ctrl_1",
2433};
2434
2093static const struct sh_pfc_function pinmux_functions[] = { 2435static const struct sh_pfc_function pinmux_functions[] = {
2094 SH_PFC_FUNCTION(lcd), 2436 SH_PFC_FUNCTION(lcd),
2095 SH_PFC_FUNCTION(lcd2), 2437 SH_PFC_FUNCTION(lcd2),
2438 SH_PFC_FUNCTION(scifa0),
2439 SH_PFC_FUNCTION(scifa1),
2440 SH_PFC_FUNCTION(scifa2),
2441 SH_PFC_FUNCTION(scifa3),
2442 SH_PFC_FUNCTION(scifa4),
2443 SH_PFC_FUNCTION(scifa5),
2444 SH_PFC_FUNCTION(scifa6),
2445 SH_PFC_FUNCTION(scifa7),
2446 SH_PFC_FUNCTION(scifb),
2096}; 2447};
2097 2448
2098#define PINMUX_FN_BASE GPIO_FN_VBUS_0 2449#define PINMUX_FN_BASE GPIO_FN_VBUS_0
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 07:35:47 -0500