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authorTomasz Figa <tomasz.figa@gmail.com>2013-03-18 17:31:52 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-04-09 03:41:09 -0400
commit499147c9dbceee27c63bf8e6b604aca1737e9e0c (patch)
tree54305db6aac8a73a8e495f98b1f0f82886e3af53 /drivers/pinctrl/pinctrl-exynos.c
parentd5517bec272ce4732f7e86a72a1bb815834c912c (diff)
pinctrl: samsung: Split pin bank description into two structures
This patch splits pin bank description into two structures, one describing bank type (currently only bitfield widths), which can be shared across multiple banks and second containing bank-specific parameters including a pointer to a bank type struct. It is a prerequisite for further patch removing the statically hardcoded register offsets, making it impossible to support SoCs with different set and order of pin control registers. Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/pinctrl/pinctrl-exynos.c')
-rw-r--r--drivers/pinctrl/pinctrl-exynos.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index cf7700ed57b8..b5dbb87800fd 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -34,6 +34,15 @@
34#include "pinctrl-samsung.h" 34#include "pinctrl-samsung.h"
35#include "pinctrl-exynos.h" 35#include "pinctrl-exynos.h"
36 36
37
38static struct samsung_pin_bank_type bank_type_off = {
39 .fld_width = { 4, 1, 2, 2, 2, 2, },
40};
41
42static struct samsung_pin_bank_type bank_type_alive = {
43 .fld_width = { 4, 1, 2, 2, },
44};
45
37/* list of external wakeup controllers supported */ 46/* list of external wakeup controllers supported */
38static const struct of_device_id exynos_wkup_irq_ids[] = { 47static const struct of_device_id exynos_wkup_irq_ids[] = {
39 { .compatible = "samsung,exynos4210-wakeup-eint", }, 48 { .compatible = "samsung,exynos4210-wakeup-eint", },
@@ -76,6 +85,7 @@ static void exynos_gpio_irq_ack(struct irq_data *irqd)
76static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type) 85static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
77{ 86{
78 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 87 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
88 struct samsung_pin_bank_type *bank_type = bank->type;
79 struct samsung_pinctrl_drv_data *d = bank->drvdata; 89 struct samsung_pinctrl_drv_data *d = bank->drvdata;
80 struct samsung_pin_ctrl *ctrl = d->ctrl; 90 struct samsung_pin_ctrl *ctrl = d->ctrl;
81 unsigned int pin = irqd->hwirq; 91 unsigned int pin = irqd->hwirq;
@@ -117,8 +127,8 @@ static int exynos_gpio_irq_set_type(struct irq_data *irqd, unsigned int type)
117 writel(con, d->virt_base + reg_con); 127 writel(con, d->virt_base + reg_con);
118 128
119 reg_con = bank->pctl_offset; 129 reg_con = bank->pctl_offset;
120 shift = pin * bank->func_width; 130 shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
121 mask = (1 << bank->func_width) - 1; 131 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
122 132
123 spin_lock_irqsave(&bank->slock, flags); 133 spin_lock_irqsave(&bank->slock, flags);
124 134
@@ -259,6 +269,7 @@ static void exynos_wkup_irq_ack(struct irq_data *irqd)
259static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type) 269static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
260{ 270{
261 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); 271 struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
272 struct samsung_pin_bank_type *bank_type = bank->type;
262 struct samsung_pinctrl_drv_data *d = bank->drvdata; 273 struct samsung_pinctrl_drv_data *d = bank->drvdata;
263 unsigned int pin = irqd->hwirq; 274 unsigned int pin = irqd->hwirq;
264 unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset; 275 unsigned long reg_con = d->ctrl->weint_con + bank->eint_offset;
@@ -299,8 +310,8 @@ static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
299 writel(con, d->virt_base + reg_con); 310 writel(con, d->virt_base + reg_con);
300 311
301 reg_con = bank->pctl_offset; 312 reg_con = bank->pctl_offset;
302 shift = pin * bank->func_width; 313 shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
303 mask = (1 << bank->func_width) - 1; 314 mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
304 315
305 spin_lock_irqsave(&bank->slock, flags); 316 spin_lock_irqsave(&bank->slock, flags);
306 317