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authorPeter Griffin <peter.griffin@linaro.org>2015-01-07 10:04:07 -0500
committerKishon Vijay Abraham I <kishon@ti.com>2015-01-30 07:42:05 -0500
commitbbd3ce86c768928d5db334881e20116c6da4d0c7 (patch)
tree5dd6904a13570a36e851008c37c9f45d7f76cd43 /drivers/phy
parente4b3d38088df6f3acd40259c8ec32c9bd3bfe3da (diff)
phy: miphy365x: Pass sysconfig register offsets via syscfg dt property.
Based on Arnds review comments here https://lkml.org/lkml/2014/11/13/161, update the miphy365 phy driver to access sysconfig register offsets via syscfg dt property. This is because the reg property should not be mixing address spaces like it does currently for miphy365. This change then also aligns us to how other platforms such as keystone and bcm7445 pass there syscon offsets via DT. This patch breaks DT compatibility, but this platform is considered WIP, and is only used by a few developers who are upstreaming support for it. This change has been done as a single atomic commit to ensure it is bisectable. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Tested-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'drivers/phy')
-rw-r--r--drivers/phy/phy-miphy365x.c29
1 files changed, 10 insertions, 19 deletions
diff --git a/drivers/phy/phy-miphy365x.c b/drivers/phy/phy-miphy365x.c
index 6ab43a814ad2..6c80154e8bff 100644
--- a/drivers/phy/phy-miphy365x.c
+++ b/drivers/phy/phy-miphy365x.c
@@ -141,7 +141,7 @@ struct miphy365x_phy {
141 bool pcie_tx_pol_inv; 141 bool pcie_tx_pol_inv;
142 bool sata_tx_pol_inv; 142 bool sata_tx_pol_inv;
143 u32 sata_gen; 143 u32 sata_gen;
144 u64 ctrlreg; 144 u32 ctrlreg;
145 u8 type; 145 u8 type;
146}; 146};
147 147
@@ -179,7 +179,7 @@ static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
179 bool sata = (miphy_phy->type == MIPHY_TYPE_SATA); 179 bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
180 180
181 return regmap_update_bits(miphy_dev->regmap, 181 return regmap_update_bits(miphy_dev->regmap,
182 (unsigned int)miphy_phy->ctrlreg, 182 miphy_phy->ctrlreg,
183 SYSCFG_SELECT_SATA_MASK, 183 SYSCFG_SELECT_SATA_MASK,
184 sata << SYSCFG_SELECT_SATA_POS); 184 sata << SYSCFG_SELECT_SATA_POS);
185} 185}
@@ -445,7 +445,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
445{ 445{
446 struct device_node *phynode = miphy_phy->phy->dev.of_node; 446 struct device_node *phynode = miphy_phy->phy->dev.of_node;
447 const char *name; 447 const char *name;
448 const __be32 *taddr;
449 int type = miphy_phy->type; 448 int type = miphy_phy->type;
450 int ret; 449 int ret;
451 450
@@ -455,22 +454,6 @@ int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
455 return ret; 454 return ret;
456 } 455 }
457 456
458 if (!strncmp(name, "syscfg", 6)) {
459 taddr = of_get_address(phynode, index, NULL, NULL);
460 if (!taddr) {
461 dev_err(dev, "failed to fetch syscfg address\n");
462 return -EINVAL;
463 }
464
465 miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
466 if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
467 dev_err(dev, "failed to translate syscfg address\n");
468 return -EINVAL;
469 }
470
471 return 0;
472 }
473
474 if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) || 457 if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
475 (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE))) 458 (!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
476 return 0; 459 return 0;
@@ -606,7 +589,15 @@ static int miphy365x_probe(struct platform_device *pdev)
606 return ret; 589 return ret;
607 590
608 phy_set_drvdata(phy, miphy_dev->phys[port]); 591 phy_set_drvdata(phy, miphy_dev->phys[port]);
592
609 port++; 593 port++;
594 /* sysconfig offsets are indexed from 1 */
595 ret = of_property_read_u32_index(np, "st,syscfg", port,
596 &miphy_phy->ctrlreg);
597 if (ret) {
598 dev_err(&pdev->dev, "No sysconfig offset found\n");
599 return ret;
600 }
610 } 601 }
611 602
612 provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate); 603 provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);