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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/pcmcia/m32r_cfc.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/pcmcia/m32r_cfc.h')
-rw-r--r--drivers/pcmcia/m32r_cfc.h83
1 files changed, 83 insertions, 0 deletions
diff --git a/drivers/pcmcia/m32r_cfc.h b/drivers/pcmcia/m32r_cfc.h
new file mode 100644
index 000000000000..17c1db7ae155
--- /dev/null
+++ b/drivers/pcmcia/m32r_cfc.h
@@ -0,0 +1,83 @@
1/*
2 * Copyright (C) 2001 by Hiroyuki Kondo
3 */
4
5#if !defined(CONFIG_M32R_CFC_NUM)
6#define M32R_MAX_PCC 2
7#else
8#define M32R_MAX_PCC CONFIG_M32R_CFC_NUM
9#endif
10
11/*
12 * M32R PC Card Controler
13 */
14#define M32R_PCC0_BASE 0x00ef7000
15#define M32R_PCC1_BASE 0x00ef7020
16
17/*
18 * Register offsets
19 */
20#define PCCR 0x00
21#define PCADR 0x04
22#define PCMOD 0x08
23#define PCIRC 0x0c
24#define PCCSIGCR 0x10
25#define PCATCR 0x14
26
27/*
28 * PCCR
29 */
30#define PCCR_PCEN (1UL<<(31-31))
31
32/*
33 * PCIRC
34 */
35#define PCIRC_BWERR (1UL<<(31-7))
36#define PCIRC_CDIN1 (1UL<<(31-14))
37#define PCIRC_CDIN2 (1UL<<(31-15))
38#define PCIRC_BEIEN (1UL<<(31-23))
39#define PCIRC_CIIEN (1UL<<(31-30))
40#define PCIRC_COIEN (1UL<<(31-31))
41
42/*
43 * PCCSIGCR
44 */
45#define PCCSIGCR_SEN (1UL<<(31-3))
46#define PCCSIGCR_VEN (1UL<<(31-7))
47#define PCCSIGCR_CRST (1UL<<(31-15))
48#define PCCSIGCR_COCR (1UL<<(31-31))
49
50/*
51 *
52 */
53#define PCMOD_AS_ATTRIB (1UL<<(31-19))
54#define PCMOD_AS_IO (1UL<<(31-18))
55
56#define PCMOD_CBSZ (1UL<<(31-23)) /* set for 8bit */
57
58#define PCMOD_DBEX (1UL<<(31-31)) /* set for excahnge */
59
60/*
61 * M32R PCC Map addr
62 */
63
64#define M32R_PCC0_MAPBASE 0x14000000
65#define M32R_PCC1_MAPBASE 0x16000000
66
67#define M32R_PCC_MAPMAX 0x02000000
68
69#define M32R_PCC_MAPSIZE 0x00001000 /* XXX */
70#define M32R_PCC_MAPMASK (~(M32R_PCC_MAPMAX-1))
71
72#define CFC_IOPORT_BASE 0x1000
73
74#if !defined(CONFIG_PLAT_USRV)
75#define CFC_ATTR_MAPBASE 0x0c014000
76#define CFC_IO_MAPBASE_BYTE 0xac012000
77#define CFC_IO_MAPBASE_WORD 0xac002000
78#else /* CONFIG_PLAT_USRV */
79#define CFC_ATTR_MAPBASE 0x04014000
80#define CFC_IO_MAPBASE_BYTE 0xa4012000
81#define CFC_IO_MAPBASE_WORD 0xa4002000
82#endif /* CONFIG_PLAT_USRV */
83