Merge commit 'v2.6.27-rc3' into x86/prototypes

Conflicts:

	include/asm-x86/dma-mapping.h

Signed-off-by: Ingo Molnar <mingo@elte.hu>

10 files changed, 280 insertions, 171 deletions

diff --git a/drivers/pci/dmar.c b/drivers/pci/dmar.c
index f941f609dbf3..8bf86ae2333f 100644
--- a/drivers/pci/dmar.c
+++ b/drivers/pci/dmar.c
@@ -317,10 +317,8 @@ int __init dmar_table_init(void)
                 return -ENODEV;
         }
 
-        if (list_empty(&dmar_rmrr_units)) {
+        if (list_empty(&dmar_rmrr_units))
                 printk(KERN_INFO PREFIX "No RMRR found\n");
-                return -ENODEV;
-        }
 
         return 0;
 }
diff --git a/drivers/pci/hotplug/acpiphp.h b/drivers/pci/hotplug/acpiphp.h
index eecf7cbf4139..5a58b075dd8d 100644
--- a/drivers/pci/hotplug/acpiphp.h
+++ b/drivers/pci/hotplug/acpiphp.h
@@ -36,7 +36,7 @@
 #define _ACPIPHP_H
 
 #include <linux/acpi.h>
-#include <linux/kobject.h>      /* for KOBJ_NAME_LEN */
+#include <linux/kobject.h>
 #include <linux/mutex.h>
 #include <linux/pci_hotplug.h>
 
@@ -51,7 +51,7 @@
 #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
 
 /* name size which is used for entries in pcihpfs */
-#define SLOT_NAME_SIZE  KOBJ_NAME_LEN           /* {_SUN} */
+#define SLOT_NAME_SIZE  20              /* {_SUN} */
 
 struct acpiphp_bridge;
 struct acpiphp_slot;
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 1323a43285d7..ad27e9e225a6 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -1103,7 +1103,7 @@ static inline void dbg_ctrl(struct controller *ctrl)
         dbg("  Power Indicator      : %3s\n", PWR_LED(ctrl)    ? "yes" : "no");
         dbg("  Hot-Plug Surprise    : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no");
         dbg("  EMI Present          : %3s\n", EMI(ctrl)        ? "yes" : "no");
-        dbg("  Comamnd Completed    : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes");
+        dbg("  Command Completed    : %3s\n", NO_CMD_CMPL(ctrl)? "no" : "yes");
         pciehp_readw(ctrl, SLOTSTATUS, &reg16);
         dbg("Slot Status            : 0x%04x\n", reg16);
         pciehp_readw(ctrl, SLOTCTRL, &reg16);
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 15af618d36e2..4a10b5624f72 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -126,7 +126,16 @@ static void msix_flush_writes(unsigned int irq)
         }
 }
 
-static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
+/*
+ * PCI 2.3 does not specify mask bits for each MSI interrupt.  Attempting to
+ * mask all MSI interrupts by clearing the MSI enable bit does not work
+ * reliably as devices without an INTx disable bit will then generate a
+ * level IRQ which will never be cleared.
+ *
+ * Returns 1 if it succeeded in masking the interrupt and 0 if the device
+ * doesn't support MSI masking.
+ */
+static int msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
 {
         struct msi_desc *entry;
 
@@ -144,8 +153,7 @@ static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
                         mask_bits |= flag & mask;
                         pci_write_config_dword(entry->dev, pos, mask_bits);
                 } else {
-                        __msi_set_enable(entry->dev, entry->msi_attrib.pos,
-                                         !flag);
+                        return 0;
                 }
                 break;
         case PCI_CAP_ID_MSIX:
@@ -161,6 +169,7 @@ static void msi_set_mask_bits(unsigned int irq, u32 mask, u32 flag)
                 break;
         }
         entry->msi_attrib.masked = !!flag;
+        return 1;
 }
 
 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
@@ -299,9 +308,8 @@ static void __pci_restore_msi_state(struct pci_dev *dev)
                                   entry->msi_attrib.masked);
 
         pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
-        control &= ~(PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE);
-        if (entry->msi_attrib.maskbit || !entry->msi_attrib.masked)
-                control |= PCI_MSI_FLAGS_ENABLE;
+        control &= ~PCI_MSI_FLAGS_QSIZE;
+        control |= PCI_MSI_FLAGS_ENABLE;
         pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
 }
 
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 7764768b6a0e..89a2f0fa10f9 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -11,6 +11,7 @@
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/module.h>
+#include <linux/pci-aspm.h>
 #include <acpi/acpi.h>
 #include <acpi/acnamesp.h>
 #include <acpi/acresrc.h>
@@ -372,6 +373,12 @@ static int __init acpi_pci_init(void)
                 printk(KERN_INFO"ACPI FADT declares the system doesn't support MSI, so disable it\n");
                 pci_no_msi();
         }
+
+        if (acpi_gbl_FADT.boot_flags & BAF_PCIE_ASPM_CONTROL) {
+                printk(KERN_INFO"ACPI FADT declares the system doesn't support PCIe ASPM, so disable it\n");
+                pcie_no_aspm();
+        }
+
         ret = register_acpi_bus_type(&acpi_pci_bus);
         if (ret)
                 return 0;
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index d00f0e0d8453..c9884bba22de 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -572,6 +572,10 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
                 if (!ret)
                         pci_update_current_state(dev);
         }
+        /* This device is quirked not to be put into D3, so
+           don't put it in D3 */
+        if (state == PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
+                return 0;
 
         error = pci_raw_set_power_state(dev, state);
 
@@ -1040,7 +1044,7 @@ int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
  * @dev: PCI device to handle.
  * @state: PCI state from which device will issue PME#.
  */
-static bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
+bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
 {
         if (!dev->pm_cap)
                 return false;
@@ -1056,7 +1060,7 @@ static bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
  * The caller must verify that the device is capable of generating PME# before
  * calling this function with @enable equal to 'true'.
  */
-static void pci_pme_active(struct pci_dev *dev, bool enable)
+void pci_pme_active(struct pci_dev *dev, bool enable)
 {
         u16 pmcsr;
 
@@ -1123,17 +1127,16 @@ int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
 }
 
 /**
- * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
- * @dev: Device to handle.
+ * pci_target_state - find an appropriate low power state for a given PCI dev
+ * @dev: PCI device
  *
- * Choose the power state appropriate for the device depending on whether
- * it can wake up the system and/or is power manageable by the platform
- * (PCI_D3hot is the default) and put the device into that state.
+ * Use underlying platform code to find a supported low power state for @dev.
+ * If the platform can't manage @dev, return the deepest state from which it
+ * can generate wake events, based on any available PME info.
  */
-int pci_prepare_to_sleep(struct pci_dev *dev)
+pci_power_t pci_target_state(struct pci_dev *dev)
 {
         pci_power_t target_state = PCI_D3hot;
-        int error;
 
         if (platform_pci_power_manageable(dev)) {
                 /*
@@ -1160,7 +1163,7 @@ int pci_prepare_to_sleep(struct pci_dev *dev)
                  * to generate PME#.
                  */
                 if (!dev->pm_cap)
-                        return -EIO;
+                        return PCI_POWER_ERROR;
 
                 if (dev->pme_support) {
                         while (target_state
@@ -1169,6 +1172,25 @@ int pci_prepare_to_sleep(struct pci_dev *dev)
                 }
         }
 
+        return target_state;
+}
+
+/**
+ * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
+ * @dev: Device to handle.
+ *
+ * Choose the power state appropriate for the device depending on whether
+ * it can wake up the system and/or is power manageable by the platform
+ * (PCI_D3hot is the default) and put the device into that state.
+ */
+int pci_prepare_to_sleep(struct pci_dev *dev)
+{
+        pci_power_t target_state = pci_target_state(dev);
+        int error;
+
+        if (target_state == PCI_POWER_ERROR)
+                return -EIO;
+
         pci_enable_wake(dev, target_state, true);
 
         error = pci_set_power_state(dev, target_state);
@@ -1918,7 +1940,10 @@ EXPORT_SYMBOL(pci_select_bars);
 EXPORT_SYMBOL(pci_set_power_state);
 EXPORT_SYMBOL(pci_save_state);
 EXPORT_SYMBOL(pci_restore_state);
+EXPORT_SYMBOL(pci_pme_capable);
+EXPORT_SYMBOL(pci_pme_active);
 EXPORT_SYMBOL(pci_enable_wake);
+EXPORT_SYMBOL(pci_target_state);
 EXPORT_SYMBOL(pci_prepare_to_sleep);
 EXPORT_SYMBOL(pci_back_from_sleep);
 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index f82495583e63..9a7c9e1408a4 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -55,7 +55,7 @@ struct pcie_link_state {
         struct endpoint_state endpoints[8];
 };
 
-static int aspm_disabled;
+static int aspm_disabled, aspm_force;
 static DEFINE_MUTEX(aspm_lock);
 static LIST_HEAD(link_list);
 
@@ -510,6 +510,7 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
 {
         struct pci_dev *child_dev;
         int child_pos;
+        u32 reg32;
 
         /*
          * Some functions in a slot might not all be PCIE functions, very
@@ -519,6 +520,19 @@ static int pcie_aspm_sanity_check(struct pci_dev *pdev)
                 child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
                 if (!child_pos)
                         return -EINVAL;
+
+                /*
+                 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
+                 * RBER bit to determine if a function is 1.1 version device
+                 */
+                pci_read_config_dword(child_dev, child_pos + PCI_EXP_DEVCAP,
+                        &reg32);
+                if (!(reg32 & PCI_EXP_DEVCAP_RBER && !aspm_force)) {
+                        printk("Pre-1.1 PCIe device detected, "
+                                "disable ASPM for %s. It can be enabled forcedly"
+                                " with 'pcie_aspm=force'\n", pci_name(pdev));
+                        return -EINVAL;
+                }
         }
         return 0;
 }
@@ -802,11 +816,23 @@ void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
 
 static int __init pcie_aspm_disable(char *str)
 {
-        aspm_disabled = 1;
+        if (!strcmp(str, "off")) {
+                aspm_disabled = 1;
+                printk(KERN_INFO "PCIe ASPM is disabled\n");
+        } else if (!strcmp(str, "force")) {
+                aspm_force = 1;
+                printk(KERN_INFO "PCIe ASPM is forcedly enabled\n");
+        }
         return 1;
 }
 
-__setup("pcie_noaspm", pcie_aspm_disable);
+__setup("pcie_aspm=", pcie_aspm_disable);
+
+void pcie_no_aspm(void)
+{
+        if (!aspm_force)
+                aspm_disabled = 1;
+}
 
 #ifdef CONFIG_ACPI
 #include <acpi/acpi_bus.h>
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index b1724cf31b66..a04498d390c8 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -52,27 +52,49 @@ EXPORT_SYMBOL(no_pci_devices);
  * Some platforms allow access to legacy I/O port and ISA memory space on
  * a per-bus basis.  This routine creates the files and ties them into
  * their associated read, write and mmap files from pci-sysfs.c
+ *
+ * On error unwind, but don't propogate the error to the caller
+ * as it is ok to set up the PCI bus without these files.
  */
 static void pci_create_legacy_files(struct pci_bus *b)
 {
+        int error;
+
         b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
                                GFP_ATOMIC);
-        if (b->legacy_io) {
-                b->legacy_io->attr.name = "legacy_io";
-                b->legacy_io->size = 0xffff;
-                b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
-                b->legacy_io->read = pci_read_legacy_io;
-                b->legacy_io->write = pci_write_legacy_io;
-                device_create_bin_file(&b->dev, b->legacy_io);
-
-                /* Allocated above after the legacy_io struct */
-                b->legacy_mem = b->legacy_io + 1;
-                b->legacy_mem->attr.name = "legacy_mem";
-                b->legacy_mem->size = 1024*1024;
-                b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
-                b->legacy_mem->mmap = pci_mmap_legacy_mem;
-                device_create_bin_file(&b->dev, b->legacy_mem);
-        }
+        if (!b->legacy_io)
+                goto kzalloc_err;
+
+        b->legacy_io->attr.name = "legacy_io";
+        b->legacy_io->size = 0xffff;
+        b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
+        b->legacy_io->read = pci_read_legacy_io;
+        b->legacy_io->write = pci_write_legacy_io;
+        error = device_create_bin_file(&b->dev, b->legacy_io);
+        if (error)
+                goto legacy_io_err;
+
+        /* Allocated above after the legacy_io struct */
+        b->legacy_mem = b->legacy_io + 1;
+        b->legacy_mem->attr.name = "legacy_mem";
+        b->legacy_mem->size = 1024*1024;
+        b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
+        b->legacy_mem->mmap = pci_mmap_legacy_mem;
+        error = device_create_bin_file(&b->dev, b->legacy_mem);
+        if (error)
+                goto legacy_mem_err;
+
+        return;
+
+legacy_mem_err:
+        device_remove_bin_file(&b->dev, b->legacy_io);
+legacy_io_err:
+        kfree(b->legacy_io);
+        b->legacy_io = NULL;
+kzalloc_err:
+        printk(KERN_WARNING "pci: warning: could not create legacy I/O port "
+               "and ISA memory resources to sysfs\n");
+        return;
 }
 
 void pci_remove_legacy_files(struct pci_bus *b)
@@ -163,12 +185,9 @@ static inline unsigned int pci_calc_resource_flags(unsigned int flags)
         return IORESOURCE_MEM;
 }
 
-/*
- * Find the extent of a PCI decode..
- */
-static u32 pci_size(u32 base, u32 maxbase, u32 mask)
+static u64 pci_size(u64 base, u64 maxbase, u64 mask)
 {
-        u32 size = mask & maxbase;      /* Find the significant bits */
+        u64 size = mask & maxbase;      /* Find the significant bits */
         if (!size)
                 return 0;
 
@@ -184,135 +203,142 @@ static u32 pci_size(u32 base, u32 maxbase, u32 mask)
         return size;
 }
 
-static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
+enum pci_bar_type {
+        pci_bar_unknown,        /* Standard PCI BAR probe */
+        pci_bar_io,             /* An io port BAR */
+        pci_bar_mem32,          /* A 32-bit memory BAR */
+        pci_bar_mem64,          /* A 64-bit memory BAR */
+};
+
+static inline enum pci_bar_type decode_bar(struct resource *res, u32 bar)
 {
-        u64 size = mask & maxbase;      /* Find the significant bits */
-        if (!size)
-                return 0;
+        if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
+                res->flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
+                return pci_bar_io;
+        }
 
-        /* Get the lowest of them to find the decode size, and
-           from that the extent.  */
-        size = (size & ~(size-1)) - 1;
+        res->flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
 
-        /* base == maxbase can be valid only if the BAR has
-           already been programmed with all 1s.  */
-        if (base == maxbase && ((base | size) & mask) != mask)
-                return 0;
-
-        return size;
+        if (res->flags == PCI_BASE_ADDRESS_MEM_TYPE_64)
+                return pci_bar_mem64;
+        return pci_bar_mem32;
 }
 
-static inline int is_64bit_memory(u32 mask)
+/*
+ * If the type is not unknown, we assume that the lowest bit is 'enable'.
+ * Returns 1 if the BAR was 64-bit and 0 if it was 32-bit.
+ */
+static int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
+                        struct resource *res, unsigned int pos)
 {
-        if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
-            (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
-                return 1;
-        return 0;
-}
+        u32 l, sz, mask;
 
-static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
-{
-        unsigned int pos, reg, next;
-        u32 l, sz;
-        struct resource *res;
+        mask = type ? ~PCI_ROM_ADDRESS_ENABLE : ~0;
 
-        for(pos=0; pos<howmany; pos = next) {
-                u64 l64;
-                u64 sz64;
-                u32 raw_sz;
+        res->name = pci_name(dev);
 
-                next = pos+1;
-                res = &dev->resource[pos];
-                res->name = pci_name(dev);
-                reg = PCI_BASE_ADDRESS_0 + (pos << 2);
-                pci_read_config_dword(dev, reg, &l);
-                pci_write_config_dword(dev, reg, ~0);
-                pci_read_config_dword(dev, reg, &sz);
-                pci_write_config_dword(dev, reg, l);
-                if (!sz || sz == 0xffffffff)
-                        continue;
-                if (l == 0xffffffff)
-                        l = 0;
-                raw_sz = sz;
-                if ((l & PCI_BASE_ADDRESS_SPACE) ==
-                                PCI_BASE_ADDRESS_SPACE_MEMORY) {
-                        sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
-                        /*
-                         * For 64bit prefetchable memory sz could be 0, if the
-                         * real size is bigger than 4G, so we need to check
-                         * szhi for that.
-                         */
-                        if (!is_64bit_memory(l) && !sz)
-                                continue;
-                        res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
-                        res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
+        pci_read_config_dword(dev, pos, &l);
+        pci_write_config_dword(dev, pos, mask);
+        pci_read_config_dword(dev, pos, &sz);
+        pci_write_config_dword(dev, pos, l);
+
+        /*
+         * All bits set in sz means the device isn't working properly.
+         * If the BAR isn't implemented, all bits must be 0.  If it's a
+         * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
+         * 1 must be clear.
+         */
+        if (!sz || sz == 0xffffffff)
+                goto fail;
+
+        /*
+         * I don't know how l can have all bits set.  Copied from old code.
+         * Maybe it fixes a bug on some ancient platform.
+         */
+        if (l == 0xffffffff)
+                l = 0;
+
+        if (type == pci_bar_unknown) {
+                type = decode_bar(res, l);
+                res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
+                if (type == pci_bar_io) {
+                        l &= PCI_BASE_ADDRESS_IO_MASK;
+                        mask = PCI_BASE_ADDRESS_IO_MASK & 0xffff;
                 } else {
-                        sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
-                        if (!sz)
-                                continue;
-                        res->start = l & PCI_BASE_ADDRESS_IO_MASK;
-                        res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
+                        l &= PCI_BASE_ADDRESS_MEM_MASK;
+                        mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
                 }
-                res->end = res->start + (unsigned long) sz;
-                res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
-                if (is_64bit_memory(l)) {
-                        u32 szhi, lhi;
-
-                        pci_read_config_dword(dev, reg+4, &lhi);
-                        pci_write_config_dword(dev, reg+4, ~0);
-                        pci_read_config_dword(dev, reg+4, &szhi);
-                        pci_write_config_dword(dev, reg+4, lhi);
-                        sz64 = ((u64)szhi << 32) | raw_sz;
-                        l64 = ((u64)lhi << 32) | l;
-                        sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
-                        next++;
-#if BITS_PER_LONG == 64
-                        if (!sz64) {
-                                res->start = 0;
-                                res->end = 0;
-                                res->flags = 0;
-                                continue;
-                        }
-                        res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
-                        res->end = res->start + sz64;
-#else
-                        if (sz64 > 0x100000000ULL) {
-                                dev_err(&dev->dev, "BAR %d: can't handle 64-bit"
-                                        " BAR\n", pos);
-                                res->start = 0;
-                                res->flags = 0;
-                        } else if (lhi) {
-                                /* 64-bit wide address, treat as disabled */
-                                pci_write_config_dword(dev, reg,
-                                        l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
-                                pci_write_config_dword(dev, reg+4, 0);
-                                res->start = 0;
-                                res->end = sz;
-                        }
-#endif
+        } else {
+                res->flags |= (l & IORESOURCE_ROM_ENABLE);
+                l &= PCI_ROM_ADDRESS_MASK;
+                mask = (u32)PCI_ROM_ADDRESS_MASK;
+        }
+
+        if (type == pci_bar_mem64) {
+                u64 l64 = l;
+                u64 sz64 = sz;
+                u64 mask64 = mask | (u64)~0 << 32;
+
+                pci_read_config_dword(dev, pos + 4, &l);
+                pci_write_config_dword(dev, pos + 4, ~0);
+                pci_read_config_dword(dev, pos + 4, &sz);
+                pci_write_config_dword(dev, pos + 4, l);
+
+                l64 |= ((u64)l << 32);
+                sz64 |= ((u64)sz << 32);
+
+                sz64 = pci_size(l64, sz64, mask64);
+
+                if (!sz64)
+                        goto fail;
+
+                if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
+                        dev_err(&dev->dev, "can't handle 64-bit BAR\n");
+                        goto fail;
+                } else if ((sizeof(resource_size_t) < 8) && l) {
+                        /* Address above 32-bit boundary; disable the BAR */
+                        pci_write_config_dword(dev, pos, 0);
+                        pci_write_config_dword(dev, pos + 4, 0);
+                        res->start = 0;
+                        res->end = sz64;
+                } else {
+                        res->start = l64;
+                        res->end = l64 + sz64;
                 }
+        } else {
+                sz = pci_size(l, sz, mask);
+
+                if (!sz)
+                        goto fail;
+
+                res->start = l;
+                res->end = l + sz;
         }
+
+ out:
+        return (type == pci_bar_mem64) ? 1 : 0;
+ fail:
+        res->flags = 0;
+        goto out;
+}
+
+static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
+{
+        unsigned int pos, reg;
+
+        for (pos = 0; pos < howmany; pos++) {
+                struct resource *res = &dev->resource[pos];
+                reg = PCI_BASE_ADDRESS_0 + (pos << 2);
+                pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
+        }
+
         if (rom) {
+                struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
                 dev->rom_base_reg = rom;
-                res = &dev->resource[PCI_ROM_RESOURCE];
-                res->name = pci_name(dev);
-                pci_read_config_dword(dev, rom, &l);
-                pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
-                pci_read_config_dword(dev, rom, &sz);
-                pci_write_config_dword(dev, rom, l);
-                if (l == 0xffffffff)
-                        l = 0;
-                if (sz && sz != 0xffffffff) {
-                        sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
-                        if (sz) {
-                                res->flags = (l & IORESOURCE_ROM_ENABLE) |
-                                  IORESOURCE_MEM | IORESOURCE_PREFETCH |
-                                  IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
-                                  IORESOURCE_SIZEALIGN;
-                                res->start = l & PCI_ROM_ADDRESS_MASK;
-                                res->end = res->start + (unsigned long) sz;
-                        }
-                }
+                res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
+                                IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
+                                IORESOURCE_SIZEALIGN;
+                __pci_read_base(dev, pci_bar_mem32, res, rom);
         }
 }
 
@@ -1053,7 +1079,8 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
                 }
         }
 
-        if (bus->self)
+        /* only one slot has pcie device */
+        if (bus->self && nr)
                 pcie_aspm_init_link_state(bus->self);
 
         return nr;
diff --git a/drivers/pci/proc.c b/drivers/pci/proc.c
index 4400dffbd93a..e1098c302c45 100644
--- a/drivers/pci/proc.c
+++ b/drivers/pci/proc.c
@@ -88,7 +88,7 @@ proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *pp
         if ((pos & 3) && cnt > 2) {
                 unsigned short val;
                 pci_user_read_config_word(dev, pos, &val);
-                __put_user(cpu_to_le16(val), (unsigned short __user *) buf);
+                __put_user(cpu_to_le16(val), (__le16 __user *) buf);
                 buf += 2;
                 pos += 2;
                 cnt -= 2;
@@ -97,7 +97,7 @@ proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *pp
         while (cnt >= 4) {
                 unsigned int val;
                 pci_user_read_config_dword(dev, pos, &val);
-                __put_user(cpu_to_le32(val), (unsigned int __user *) buf);
+                __put_user(cpu_to_le32(val), (__le32 __user *) buf);
                 buf += 4;
                 pos += 4;
                 cnt -= 4;
@@ -106,7 +106,7 @@ proc_bus_pci_read(struct file *file, char __user *buf, size_t nbytes, loff_t *pp
         if (cnt >= 2) {
                 unsigned short val;
                 pci_user_read_config_word(dev, pos, &val);
-                __put_user(cpu_to_le16(val), (unsigned short __user *) buf);
+                __put_user(cpu_to_le16(val), (__le16 __user *) buf);
                 buf += 2;
                 pos += 2;
                 cnt -= 2;
@@ -156,8 +156,8 @@ proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, lof
         }
 
         if ((pos & 3) && cnt > 2) {
-                unsigned short val;
-                __get_user(val, (unsigned short __user *) buf);
+                __le16 val;
+                __get_user(val, (__le16 __user *) buf);
                 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
                 buf += 2;
                 pos += 2;
@@ -165,8 +165,8 @@ proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, lof
         }
 
         while (cnt >= 4) {
-                unsigned int val;
-                __get_user(val, (unsigned int __user *) buf);
+                __le32 val;
+                __get_user(val, (__le32 __user *) buf);
                 pci_user_write_config_dword(dev, pos, le32_to_cpu(val));
                 buf += 4;
                 pos += 4;
@@ -174,8 +174,8 @@ proc_bus_pci_write(struct file *file, const char __user *buf, size_t nbytes, lof
         }
 
         if (cnt >= 2) {
-                unsigned short val;
-                __get_user(val, (unsigned short __user *) buf);
+                __le16 val;
+                __get_user(val, (__le16 __user *) buf);
                 pci_user_write_config_word(dev, pos, le16_to_cpu(val));
                 buf += 2;
                 pos += 2;
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 12d489395fad..9236e7f869c8 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -923,6 +923,19 @@ static void __init quirk_ide_samemode(struct pci_dev *pdev)
 }
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
 
+/*
+ * Some ATA devices break if put into D3
+ */
+
+static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
+{
+        /* Quirk the legacy ATA devices only. The AHCI ones are ok */
+        if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
+                pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
+
 /* This was originally an Alpha specific thing, but it really fits here.
  * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
  */
@@ -1743,9 +1756,14 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_c
  */
 static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
 {
-        /*  Only disable the VPD capability for 5706, 5708, and 5709 rev. A */
+        /*
+         * Only disable the VPD capability for 5706, 5706S, 5708,
+         * 5708S and 5709 rev. A
+         */
         if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
+            (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
             (dev->device == PCI_DEVICE_ID_NX2_5708) ||
+            (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
             ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
              (dev->revision & 0xf0) == 0x0)) {
                 if (dev->vpd)