PCI: MSI: Restore read_msi_msg_desc(); add get_cached_msi_msg_desc()

commit 2ca1af9aa3285c6a5f103ed31ad09f7399fc65d7 "PCI: MSI: Remove
unsafe and unnecessary hardware access" changed read_msi_msg_desc() to
return the last MSI message written instead of reading it from the
device, since it may be called while the device is in a reduced
power state.

However, the pSeries platform code really does need to read messages
from the device, since they are initially written by firmware.
Therefore:
- Restore the previous behaviour of read_msi_msg_desc()
- Add new functions get_cached_msi_msg{,_desc}() which return the
  last MSI message written
- Use the new functions where appropriate

Acked-by: Michael Ellerman <michael@ellerman.id.au>
Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

1 files changed, 42 insertions, 5 deletions

diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 4c14f31f2b4d..69b7be33b3a2 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -197,9 +197,46 @@ void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
 {
         struct msi_desc *entry = get_irq_desc_msi(desc);
 
-        /* We do not touch the hardware (which may not even be
-         * accessible at the moment) but return the last message
-         * written.  Assert that this is valid, assuming that
+        BUG_ON(entry->dev->current_state != PCI_D0);
+
+        if (entry->msi_attrib.is_msix) {
+                void __iomem *base = entry->mask_base +
+                        entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
+
+                msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
+                msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
+                msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
+        } else {
+                struct pci_dev *dev = entry->dev;
+                int pos = entry->msi_attrib.pos;
+                u16 data;
+
+                pci_read_config_dword(dev, msi_lower_address_reg(pos),
+                                        &msg->address_lo);
+                if (entry->msi_attrib.is_64) {
+                        pci_read_config_dword(dev, msi_upper_address_reg(pos),
+                                                &msg->address_hi);
+                        pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
+                } else {
+                        msg->address_hi = 0;
+                        pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
+                }
+                msg->data = data;
+        }
+}
+
+void read_msi_msg(unsigned int irq, struct msi_msg *msg)
+{
+        struct irq_desc *desc = irq_to_desc(irq);
+
+        read_msi_msg_desc(desc, msg);
+}
+
+void get_cached_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
+{
+        struct msi_desc *entry = get_irq_desc_msi(desc);
+
+        /* Assert that the cache is valid, assuming that
          * valid messages are not all-zeroes. */
         BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
                  entry->msg.data));
@@ -207,11 +244,11 @@ void read_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)
         *msg = entry->msg;
 }
 
-void read_msi_msg(unsigned int irq, struct msi_msg *msg)
+void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
 {
         struct irq_desc *desc = irq_to_desc(irq);
 
-        read_msi_msg_desc(desc, msg);
+        get_cached_msi_msg_desc(desc, msg);
 }
 
 void write_msi_msg_desc(struct irq_desc *desc, struct msi_msg *msg)