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authorLinus Torvalds <torvalds@linux-foundation.org>2008-02-01 22:29:33 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2008-02-01 22:29:33 -0500
commit215e871aaa3d94540121a3809d80d0c5e5686e4f (patch)
tree0ed6469c5ad04db8cfa0edb58c676d5155df20cd /drivers/pci
parentb6cf160c4b788a31f6a4017a469b956ca77febf4 (diff)
parentfd7d1ced29e5beb88c9068801da7a362606d8273 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6: (64 commits) PCI: make pci_bus a struct device PCI: fix codingstyle issues in include/linux/pci.h PCI: fix codingstyle issues in drivers/pci/pci.h PCI: PCIE ASPM support PCI: Fix fakephp deadlock PCI: modify SB700 SATA MSI quirk PCI: Run ACPI _OSC method on root bridges only PCI ACPI: AER driver should only register PCIe devices with _OSC PCI ACPI: Added a function to register _OSC with only PCIe devices. PCI: constify function pointer tables PCI: Convert drivers/pci/proc.c to use unlocked_ioctl pciehp: block new requests from the device before power off pciehp: workaround against Bad DLLP during power off pciehp: wait for 1000ms before LED operation after power off PCI: Remove pci_enable_device_bars() from documentation PCI: Remove pci_enable_device_bars() PCI: Remove users of pci_enable_device_bars() PCI: Add pci_enable_device_{io,mem} intefaces PCI: avoid save the same type of cap multiple times PCI: correctly initialize a structure for pcie_save_pcix_state() ...
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/bus.c18
-rw-r--r--drivers/pci/dmar.c20
-rw-r--r--drivers/pci/hotplug/Kconfig4
-rw-r--r--drivers/pci/hotplug/Makefile4
-rw-r--r--drivers/pci/hotplug/acpiphp.h1
-rw-r--r--drivers/pci/hotplug/acpiphp_glue.c5
-rw-r--r--drivers/pci/hotplug/fakephp.c39
-rw-r--r--drivers/pci/hotplug/ibmphp_core.c11
-rw-r--r--drivers/pci/hotplug/pci_hotplug_core.c4
-rw-r--r--drivers/pci/hotplug/pciehp.h9
-rw-r--r--drivers/pci/hotplug/pciehp_core.c33
-rw-r--r--drivers/pci/hotplug/pciehp_ctrl.c27
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c314
-rw-r--r--drivers/pci/hotplug/pciehp_pci.c43
-rw-r--r--drivers/pci/hotplug/rpaphp.h1
-rw-r--r--drivers/pci/hotplug/rpaphp_pci.c14
-rw-r--r--drivers/pci/hotplug/rpaphp_slot.c47
-rw-r--r--drivers/pci/hotplug/shpchp_hpc.c2
-rw-r--r--drivers/pci/intel-iommu.c2
-rw-r--r--drivers/pci/msi.c94
-rw-r--r--drivers/pci/pci-acpi.c7
-rw-r--r--drivers/pci/pci-driver.c4
-rw-r--r--drivers/pci/pci-sysfs.c11
-rw-r--r--drivers/pci/pci.c93
-rw-r--r--drivers/pci/pci.h16
-rw-r--r--drivers/pci/pcie/Kconfig20
-rw-r--r--drivers/pci/pcie/Makefile3
-rw-r--r--drivers/pci/pcie/aer/aerdrv_acpi.c24
-rw-r--r--drivers/pci/pcie/aspm.c802
-rw-r--r--drivers/pci/pcie/portdrv_core.c5
-rw-r--r--drivers/pci/probe.c80
-rw-r--r--drivers/pci/proc.c17
-rw-r--r--drivers/pci/quirks.c483
-rw-r--r--drivers/pci/remove.c10
-rw-r--r--drivers/pci/rom.c6
-rw-r--r--drivers/pci/setup-bus.c64
-rw-r--r--drivers/pci/setup-res.c7
-rw-r--r--drivers/pci/syscall.c5
38 files changed, 1714 insertions, 635 deletions
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index 9e5ea074ad20..ef5a6a245f5f 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -108,6 +108,7 @@ int pci_bus_add_device(struct pci_dev *dev)
108void pci_bus_add_devices(struct pci_bus *bus) 108void pci_bus_add_devices(struct pci_bus *bus)
109{ 109{
110 struct pci_dev *dev; 110 struct pci_dev *dev;
111 struct pci_bus *child_bus;
111 int retval; 112 int retval;
112 113
113 list_for_each_entry(dev, &bus->devices, bus_list) { 114 list_for_each_entry(dev, &bus->devices, bus_list) {
@@ -138,11 +139,19 @@ void pci_bus_add_devices(struct pci_bus *bus)
138 up_write(&pci_bus_sem); 139 up_write(&pci_bus_sem);
139 } 140 }
140 pci_bus_add_devices(dev->subordinate); 141 pci_bus_add_devices(dev->subordinate);
141 retval = sysfs_create_link(&dev->subordinate->class_dev.kobj, 142
142 &dev->dev.kobj, "bridge"); 143 /* register the bus with sysfs as the parent is now
144 * properly registered. */
145 child_bus = dev->subordinate;
146 child_bus->dev.parent = child_bus->bridge;
147 retval = device_register(&child_bus->dev);
148 if (!retval)
149 retval = device_create_file(&child_bus->dev,
150 &dev_attr_cpuaffinity);
143 if (retval) 151 if (retval)
144 dev_err(&dev->dev, "Error creating sysfs " 152 dev_err(&dev->dev, "Error registering pci_bus"
145 "bridge symlink, continuing...\n"); 153 " device bridge symlink,"
154 " continuing...\n");
146 } 155 }
147 } 156 }
148} 157}
@@ -204,7 +213,6 @@ void pci_walk_bus(struct pci_bus *top, void (*cb)(struct pci_dev *, void *),
204 } 213 }
205 up_read(&pci_bus_sem); 214 up_read(&pci_bus_sem);
206} 215}
207EXPORT_SYMBOL_GPL(pci_walk_bus);
208 216
209EXPORT_SYMBOL(pci_bus_alloc_resource); 217EXPORT_SYMBOL(pci_bus_alloc_resource);
210EXPORT_SYMBOL_GPL(pci_bus_add_device); 218EXPORT_SYMBOL_GPL(pci_bus_add_device);
diff --git a/drivers/pci/dmar.c b/drivers/pci/dmar.c
index 5dfdfdac92e1..91b2dc956be5 100644
--- a/drivers/pci/dmar.c
+++ b/drivers/pci/dmar.c
@@ -25,6 +25,7 @@
25 25
26#include <linux/pci.h> 26#include <linux/pci.h>
27#include <linux/dmar.h> 27#include <linux/dmar.h>
28#include "iova.h"
28 29
29#undef PREFIX 30#undef PREFIX
30#define PREFIX "DMAR:" 31#define PREFIX "DMAR:"
@@ -263,8 +264,8 @@ parse_dmar_table(void)
263 if (!dmar) 264 if (!dmar)
264 return -ENODEV; 265 return -ENODEV;
265 266
266 if (!dmar->width) { 267 if (dmar->width < PAGE_SHIFT_4K - 1) {
267 printk (KERN_WARNING PREFIX "Zero: Invalid DMAR haw\n"); 268 printk(KERN_WARNING PREFIX "Invalid DMAR haw\n");
268 return -EINVAL; 269 return -EINVAL;
269 } 270 }
270 271
@@ -301,11 +302,24 @@ parse_dmar_table(void)
301int __init dmar_table_init(void) 302int __init dmar_table_init(void)
302{ 303{
303 304
304 parse_dmar_table(); 305 int ret;
306
307 ret = parse_dmar_table();
308 if (ret) {
309 printk(KERN_INFO PREFIX "parse DMAR table failure.\n");
310 return ret;
311 }
312
305 if (list_empty(&dmar_drhd_units)) { 313 if (list_empty(&dmar_drhd_units)) {
306 printk(KERN_INFO PREFIX "No DMAR devices found\n"); 314 printk(KERN_INFO PREFIX "No DMAR devices found\n");
307 return -ENODEV; 315 return -ENODEV;
308 } 316 }
317
318 if (list_empty(&dmar_rmrr_units)) {
319 printk(KERN_INFO PREFIX "No RMRR found\n");
320 return -ENODEV;
321 }
322
309 return 0; 323 return 0;
310} 324}
311 325
diff --git a/drivers/pci/hotplug/Kconfig b/drivers/pci/hotplug/Kconfig
index a64449d489d6..2cdd8326f136 100644
--- a/drivers/pci/hotplug/Kconfig
+++ b/drivers/pci/hotplug/Kconfig
@@ -3,8 +3,8 @@
3# 3#
4 4
5menuconfig HOTPLUG_PCI 5menuconfig HOTPLUG_PCI
6 tristate "Support for PCI Hotplug (EXPERIMENTAL)" 6 tristate "Support for PCI Hotplug"
7 depends on PCI && EXPERIMENTAL && HOTPLUG 7 depends on PCI && HOTPLUG
8 ---help--- 8 ---help---
9 Say Y here if you have a motherboard with a PCI Hotplug controller. 9 Say Y here if you have a motherboard with a PCI Hotplug controller.
10 This allows you to add and remove PCI cards while the machine is 10 This allows you to add and remove PCI cards while the machine is
diff --git a/drivers/pci/hotplug/Makefile b/drivers/pci/hotplug/Makefile
index 34a1891191fd..9bdbe1a6688f 100644
--- a/drivers/pci/hotplug/Makefile
+++ b/drivers/pci/hotplug/Makefile
@@ -3,7 +3,6 @@
3# 3#
4 4
5obj-$(CONFIG_HOTPLUG_PCI) += pci_hotplug.o 5obj-$(CONFIG_HOTPLUG_PCI) += pci_hotplug.o
6obj-$(CONFIG_HOTPLUG_PCI_FAKE) += fakephp.o
7obj-$(CONFIG_HOTPLUG_PCI_COMPAQ) += cpqphp.o 6obj-$(CONFIG_HOTPLUG_PCI_COMPAQ) += cpqphp.o
8obj-$(CONFIG_HOTPLUG_PCI_IBM) += ibmphp.o 7obj-$(CONFIG_HOTPLUG_PCI_IBM) += ibmphp.o
9obj-$(CONFIG_HOTPLUG_PCI_ACPI) += acpiphp.o 8obj-$(CONFIG_HOTPLUG_PCI_ACPI) += acpiphp.o
@@ -16,6 +15,9 @@ obj-$(CONFIG_HOTPLUG_PCI_RPA) += rpaphp.o
16obj-$(CONFIG_HOTPLUG_PCI_RPA_DLPAR) += rpadlpar_io.o 15obj-$(CONFIG_HOTPLUG_PCI_RPA_DLPAR) += rpadlpar_io.o
17obj-$(CONFIG_HOTPLUG_PCI_SGI) += sgi_hotplug.o 16obj-$(CONFIG_HOTPLUG_PCI_SGI) += sgi_hotplug.o
18 17
18# Link this last so it doesn't claim devices that have a real hotplug driver
19obj-$(CONFIG_HOTPLUG_PCI_FAKE) += fakephp.o
20
19pci_hotplug-objs := pci_hotplug_core.o 21pci_hotplug-objs := pci_hotplug_core.o
20 22
21ifdef CONFIG_HOTPLUG_PCI_CPCI 23ifdef CONFIG_HOTPLUG_PCI_CPCI
diff --git a/drivers/pci/hotplug/acpiphp.h b/drivers/pci/hotplug/acpiphp.h
index 1ef417cca2db..7a29164d4b32 100644
--- a/drivers/pci/hotplug/acpiphp.h
+++ b/drivers/pci/hotplug/acpiphp.h
@@ -113,7 +113,6 @@ struct acpiphp_slot {
113 u8 device; /* pci device# */ 113 u8 device; /* pci device# */
114 114
115 u32 sun; /* ACPI _SUN (slot unique number) */ 115 u32 sun; /* ACPI _SUN (slot unique number) */
116 u32 slotno; /* slot number relative to bridge */
117 u32 flags; /* see below */ 116 u32 flags; /* see below */
118}; 117};
119 118
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index ff1b1c71291a..cf22f9e01e00 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -102,7 +102,7 @@ static int is_ejectable(acpi_handle handle)
102} 102}
103 103
104 104
105/* callback routine to check the existence of ejectable slots */ 105/* callback routine to check for the existence of ejectable slots */
106static acpi_status 106static acpi_status
107is_ejectable_slot(acpi_handle handle, u32 lvl, void *context, void **rv) 107is_ejectable_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
108{ 108{
@@ -117,7 +117,7 @@ is_ejectable_slot(acpi_handle handle, u32 lvl, void *context, void **rv)
117 } 117 }
118} 118}
119 119
120/* callback routine to check for the existance of a pci dock device */ 120/* callback routine to check for the existence of a pci dock device */
121static acpi_status 121static acpi_status
122is_pci_dock_device(acpi_handle handle, u32 lvl, void *context, void **rv) 122is_pci_dock_device(acpi_handle handle, u32 lvl, void *context, void **rv)
123{ 123{
@@ -1528,7 +1528,6 @@ check_sub_bridges(acpi_handle handle, u32 lvl, void *context, void **rv)
1528 acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer); 1528 acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
1529 dbg("%s: re-enumerating slots under %s\n", 1529 dbg("%s: re-enumerating slots under %s\n",
1530 __FUNCTION__, objname); 1530 __FUNCTION__, objname);
1531 acpi_get_name(handle, ACPI_FULL_PATHNAME, &buffer);
1532 acpiphp_check_bridge(bridge); 1531 acpiphp_check_bridge(bridge);
1533 } 1532 }
1534 return AE_OK ; 1533 return AE_OK ;
diff --git a/drivers/pci/hotplug/fakephp.c b/drivers/pci/hotplug/fakephp.c
index d7a293e3faf5..94b640146d44 100644
--- a/drivers/pci/hotplug/fakephp.c
+++ b/drivers/pci/hotplug/fakephp.c
@@ -39,6 +39,7 @@
39#include <linux/init.h> 39#include <linux/init.h>
40#include <linux/string.h> 40#include <linux/string.h>
41#include <linux/slab.h> 41#include <linux/slab.h>
42#include <linux/workqueue.h>
42#include "../pci.h" 43#include "../pci.h"
43 44
44#if !defined(MODULE) 45#if !defined(MODULE)
@@ -63,10 +64,16 @@ struct dummy_slot {
63 struct list_head node; 64 struct list_head node;
64 struct hotplug_slot *slot; 65 struct hotplug_slot *slot;
65 struct pci_dev *dev; 66 struct pci_dev *dev;
67 struct work_struct remove_work;
68 unsigned long removed;
66}; 69};
67 70
68static int debug; 71static int debug;
69static LIST_HEAD(slot_list); 72static LIST_HEAD(slot_list);
73static struct workqueue_struct *dummyphp_wq;
74
75static void pci_rescan_worker(struct work_struct *work);
76static DECLARE_WORK(pci_rescan_work, pci_rescan_worker);
70 77
71static int enable_slot (struct hotplug_slot *slot); 78static int enable_slot (struct hotplug_slot *slot);
72static int disable_slot (struct hotplug_slot *slot); 79static int disable_slot (struct hotplug_slot *slot);
@@ -109,7 +116,7 @@ static int add_slot(struct pci_dev *dev)
109 slot->name = &dev->dev.bus_id[0]; 116 slot->name = &dev->dev.bus_id[0];
110 dbg("slot->name = %s\n", slot->name); 117 dbg("slot->name = %s\n", slot->name);
111 118
112 dslot = kmalloc(sizeof(struct dummy_slot), GFP_KERNEL); 119 dslot = kzalloc(sizeof(struct dummy_slot), GFP_KERNEL);
113 if (!dslot) 120 if (!dslot)
114 goto error_info; 121 goto error_info;
115 122
@@ -164,6 +171,14 @@ static void remove_slot(struct dummy_slot *dslot)
164 err("Problem unregistering a slot %s\n", dslot->slot->name); 171 err("Problem unregistering a slot %s\n", dslot->slot->name);
165} 172}
166 173
174/* called from the single-threaded workqueue handler to remove a slot */
175static void remove_slot_worker(struct work_struct *work)
176{
177 struct dummy_slot *dslot =
178 container_of(work, struct dummy_slot, remove_work);
179 remove_slot(dslot);
180}
181
167/** 182/**
168 * pci_rescan_slot - Rescan slot 183 * pci_rescan_slot - Rescan slot
169 * @temp: Device template. Should be set: bus and devfn. 184 * @temp: Device template. Should be set: bus and devfn.
@@ -267,11 +282,17 @@ static inline void pci_rescan(void) {
267 pci_rescan_buses(&pci_root_buses); 282 pci_rescan_buses(&pci_root_buses);
268} 283}
269 284
285/* called from the single-threaded workqueue handler to rescan all pci buses */
286static void pci_rescan_worker(struct work_struct *work)
287{
288 pci_rescan();
289}
270 290
271static int enable_slot(struct hotplug_slot *hotplug_slot) 291static int enable_slot(struct hotplug_slot *hotplug_slot)
272{ 292{
273 /* mis-use enable_slot for rescanning of the pci bus */ 293 /* mis-use enable_slot for rescanning of the pci bus */
274 pci_rescan(); 294 cancel_work_sync(&pci_rescan_work);
295 queue_work(dummyphp_wq, &pci_rescan_work);
275 return -ENODEV; 296 return -ENODEV;
276} 297}
277 298
@@ -306,6 +327,10 @@ static int disable_slot(struct hotplug_slot *slot)
306 err("Can't remove PCI devices with other PCI devices behind it yet.\n"); 327 err("Can't remove PCI devices with other PCI devices behind it yet.\n");
307 return -ENODEV; 328 return -ENODEV;
308 } 329 }
330 if (test_and_set_bit(0, &dslot->removed)) {
331 dbg("Slot already scheduled for removal\n");
332 return -ENODEV;
333 }
309 /* search for subfunctions and disable them first */ 334 /* search for subfunctions and disable them first */
310 if (!(dslot->dev->devfn & 7)) { 335 if (!(dslot->dev->devfn & 7)) {
311 for (func = 1; func < 8; func++) { 336 for (func = 1; func < 8; func++) {
@@ -328,8 +353,9 @@ static int disable_slot(struct hotplug_slot *slot)
328 /* remove the device from the pci core */ 353 /* remove the device from the pci core */
329 pci_remove_bus_device(dslot->dev); 354 pci_remove_bus_device(dslot->dev);
330 355
331 /* blow away this sysfs entry and other parts. */ 356 /* queue work item to blow away this sysfs entry and other parts. */
332 remove_slot(dslot); 357 INIT_WORK(&dslot->remove_work, remove_slot_worker);
358 queue_work(dummyphp_wq, &dslot->remove_work);
333 359
334 return 0; 360 return 0;
335} 361}
@@ -340,6 +366,7 @@ static void cleanup_slots (void)
340 struct list_head *next; 366 struct list_head *next;
341 struct dummy_slot *dslot; 367 struct dummy_slot *dslot;
342 368
369 destroy_workqueue(dummyphp_wq);
343 list_for_each_safe (tmp, next, &slot_list) { 370 list_for_each_safe (tmp, next, &slot_list) {
344 dslot = list_entry (tmp, struct dummy_slot, node); 371 dslot = list_entry (tmp, struct dummy_slot, node);
345 remove_slot(dslot); 372 remove_slot(dslot);
@@ -351,6 +378,10 @@ static int __init dummyphp_init(void)
351{ 378{
352 info(DRIVER_DESC "\n"); 379 info(DRIVER_DESC "\n");
353 380
381 dummyphp_wq = create_singlethread_workqueue(MY_NAME);
382 if (!dummyphp_wq)
383 return -ENOMEM;
384
354 return pci_scan_buses(); 385 return pci_scan_buses();
355} 386}
356 387
diff --git a/drivers/pci/hotplug/ibmphp_core.c b/drivers/pci/hotplug/ibmphp_core.c
index a90c28d0c69d..87b6b8b280e6 100644
--- a/drivers/pci/hotplug/ibmphp_core.c
+++ b/drivers/pci/hotplug/ibmphp_core.c
@@ -761,10 +761,13 @@ static void ibm_unconfigure_device(struct pci_func *func)
761 debug("func->device << 3 | 0x0 = %x\n", func->device << 3 | 0x0); 761 debug("func->device << 3 | 0x0 = %x\n", func->device << 3 | 0x0);
762 762
763 for (j = 0; j < 0x08; j++) { 763 for (j = 0; j < 0x08; j++) {
764 temp = pci_find_slot(func->busno, (func->device << 3) | j); 764 temp = pci_get_bus_and_slot(func->busno, (func->device << 3) | j);
765 if (temp) 765 if (temp) {
766 pci_remove_bus_device(temp); 766 pci_remove_bus_device(temp);
767 pci_dev_put(temp);
768 }
767 } 769 }
770 pci_dev_put(func->dev);
768} 771}
769 772
770/* 773/*
@@ -823,7 +826,7 @@ static int ibm_configure_device(struct pci_func *func)
823 if (!(bus_structure_fixup(func->busno))) 826 if (!(bus_structure_fixup(func->busno)))
824 flag = 1; 827 flag = 1;
825 if (func->dev == NULL) 828 if (func->dev == NULL)
826 func->dev = pci_find_slot(func->busno, 829 func->dev = pci_get_bus_and_slot(func->busno,
827 PCI_DEVFN(func->device, func->function)); 830 PCI_DEVFN(func->device, func->function));
828 831
829 if (func->dev == NULL) { 832 if (func->dev == NULL) {
@@ -836,7 +839,7 @@ static int ibm_configure_device(struct pci_func *func)
836 if (num) 839 if (num)
837 pci_bus_add_devices(bus); 840 pci_bus_add_devices(bus);
838 841
839 func->dev = pci_find_slot(func->busno, 842 func->dev = pci_get_bus_and_slot(func->busno,
840 PCI_DEVFN(func->device, func->function)); 843 PCI_DEVFN(func->device, func->function));
841 if (func->dev == NULL) { 844 if (func->dev == NULL) {
842 err("ERROR... : pci_dev still NULL\n"); 845 err("ERROR... : pci_dev still NULL\n");
diff --git a/drivers/pci/hotplug/pci_hotplug_core.c b/drivers/pci/hotplug/pci_hotplug_core.c
index 47bb0e1ff3fa..dd59a050260f 100644
--- a/drivers/pci/hotplug/pci_hotplug_core.c
+++ b/drivers/pci/hotplug/pci_hotplug_core.c
@@ -137,7 +137,7 @@ static int get_##name (struct hotplug_slot *slot, type *value) \
137 int retval = 0; \ 137 int retval = 0; \
138 if (try_module_get(ops->owner)) { \ 138 if (try_module_get(ops->owner)) { \
139 if (ops->get_##name) \ 139 if (ops->get_##name) \
140 retval = ops->get_##name (slot, value); \ 140 retval = ops->get_##name(slot, value); \
141 else \ 141 else \
142 *value = slot->info->name; \ 142 *value = slot->info->name; \
143 module_put(ops->owner); \ 143 module_put(ops->owner); \
@@ -625,7 +625,7 @@ int pci_hp_register (struct hotplug_slot *slot)
625 if ((slot->info == NULL) || (slot->ops == NULL)) 625 if ((slot->info == NULL) || (slot->ops == NULL))
626 return -EINVAL; 626 return -EINVAL;
627 if (slot->release == NULL) { 627 if (slot->release == NULL) {
628 dbg("Why are you trying to register a hotplug slot" 628 dbg("Why are you trying to register a hotplug slot "
629 "without a proper release function?\n"); 629 "without a proper release function?\n");
630 return -EINVAL; 630 return -EINVAL;
631 } 631 }
diff --git a/drivers/pci/hotplug/pciehp.h b/drivers/pci/hotplug/pciehp.h
index 7959c222dc24..ca656b27a500 100644
--- a/drivers/pci/hotplug/pciehp.h
+++ b/drivers/pci/hotplug/pciehp.h
@@ -82,24 +82,18 @@ struct event_info {
82}; 82};
83 83
84struct controller { 84struct controller {
85 struct controller *next;
86 struct mutex crit_sect; /* critical section mutex */ 85 struct mutex crit_sect; /* critical section mutex */
87 struct mutex ctrl_lock; /* controller lock */ 86 struct mutex ctrl_lock; /* controller lock */
88 int num_slots; /* Number of slots on ctlr */ 87 int num_slots; /* Number of slots on ctlr */
89 int slot_num_inc; /* 1 or -1 */ 88 int slot_num_inc; /* 1 or -1 */
90 struct pci_dev *pci_dev; 89 struct pci_dev *pci_dev;
91 struct list_head slot_list; 90 struct list_head slot_list;
92 struct slot *slot;
93 struct hpc_ops *hpc_ops; 91 struct hpc_ops *hpc_ops;
94 wait_queue_head_t queue; /* sleep & wake process */ 92 wait_queue_head_t queue; /* sleep & wake process */
95 u8 bus;
96 u8 device;
97 u8 function;
98 u8 slot_device_offset; 93 u8 slot_device_offset;
99 u32 first_slot; /* First physical slot number */ /* PCIE only has 1 slot */ 94 u32 first_slot; /* First physical slot number */ /* PCIE only has 1 slot */
100 u8 slot_bus; /* Bus where the slots handled by this controller sit */ 95 u8 slot_bus; /* Bus where the slots handled by this controller sit */
101 u8 ctrlcap; 96 u8 ctrlcap;
102 u16 vendor_id;
103 u8 cap_base; 97 u8 cap_base;
104 struct timer_list poll_timer; 98 struct timer_list poll_timer;
105 volatile int cmd_busy; 99 volatile int cmd_busy;
@@ -161,6 +155,9 @@ extern int pciehp_configure_device(struct slot *p_slot);
161extern int pciehp_unconfigure_device(struct slot *p_slot); 155extern int pciehp_unconfigure_device(struct slot *p_slot);
162extern void pciehp_queue_pushbutton_work(struct work_struct *work); 156extern void pciehp_queue_pushbutton_work(struct work_struct *work);
163int pcie_init(struct controller *ctrl, struct pcie_device *dev); 157int pcie_init(struct controller *ctrl, struct pcie_device *dev);
158int pciehp_enable_slot(struct slot *p_slot);
159int pciehp_disable_slot(struct slot *p_slot);
160int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev);
164 161
165static inline struct slot *pciehp_find_slot(struct controller *ctrl, u8 device) 162static inline struct slot *pciehp_find_slot(struct controller *ctrl, u8 device)
166{ 163{
diff --git a/drivers/pci/hotplug/pciehp_core.c b/drivers/pci/hotplug/pciehp_core.c
index 6462ac3b405f..7f4836b8e71e 100644
--- a/drivers/pci/hotplug/pciehp_core.c
+++ b/drivers/pci/hotplug/pciehp_core.c
@@ -453,13 +453,9 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_
453 453
454 pci_set_drvdata(pdev, ctrl); 454 pci_set_drvdata(pdev, ctrl);
455 455
456 ctrl->bus = pdev->bus->number; /* ctrl bus */ 456 dbg("%s: ctrl bus=0x%x, device=%x, function=%x, irq=%x\n",
457 ctrl->slot_bus = pdev->subordinate->number; /* bus controlled by this HPC */ 457 __FUNCTION__, pdev->bus->number, PCI_SLOT(pdev->devfn),
458 458 PCI_FUNC(pdev->devfn), pdev->irq);
459 ctrl->device = PCI_SLOT(pdev->devfn);
460 ctrl->function = PCI_FUNC(pdev->devfn);
461 dbg("%s: ctrl bus=0x%x, device=%x, function=%x, irq=%x\n", __FUNCTION__,
462 ctrl->bus, ctrl->device, ctrl->function, pdev->irq);
463 459
464 /* Setup the slot information structures */ 460 /* Setup the slot information structures */
465 rc = init_slots(ctrl); 461 rc = init_slots(ctrl);
@@ -471,6 +467,11 @@ static int pciehp_probe(struct pcie_device *dev, const struct pcie_port_service_
471 t_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset); 467 t_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
472 468
473 t_slot->hpc_ops->get_adapter_status(t_slot, &value); /* Check if slot is occupied */ 469 t_slot->hpc_ops->get_adapter_status(t_slot, &value); /* Check if slot is occupied */
470 if (value) {
471 rc = pciehp_enable_slot(t_slot);
472 if (rc) /* -ENODEV: shouldn't happen, but deal with it */
473 value = 0;
474 }
474 if ((POWER_CTRL(ctrl->ctrlcap)) && !value) { 475 if ((POWER_CTRL(ctrl->ctrlcap)) && !value) {
475 rc = t_slot->hpc_ops->power_off_slot(t_slot); /* Power off slot if not occupied*/ 476 rc = t_slot->hpc_ops->power_off_slot(t_slot); /* Power off slot if not occupied*/
476 if (rc) 477 if (rc)
@@ -509,6 +510,24 @@ static int pciehp_suspend (struct pcie_device *dev, pm_message_t state)
509static int pciehp_resume (struct pcie_device *dev) 510static int pciehp_resume (struct pcie_device *dev)
510{ 511{
511 printk("%s ENTRY\n", __FUNCTION__); 512 printk("%s ENTRY\n", __FUNCTION__);
513 if (pciehp_force) {
514 struct pci_dev *pdev = dev->port;
515 struct controller *ctrl = pci_get_drvdata(pdev);
516 struct slot *t_slot;
517 u8 status;
518
519 /* reinitialize the chipset's event detection logic */
520 pcie_init_hardware_part2(ctrl, dev);
521
522 t_slot = pciehp_find_slot(ctrl, ctrl->slot_device_offset);
523
524 /* Check if slot is occupied */
525 t_slot->hpc_ops->get_adapter_status(t_slot, &status);
526 if (status)
527 pciehp_enable_slot(t_slot);
528 else
529 pciehp_disable_slot(t_slot);
530 }
512 return 0; 531 return 0;
513} 532}
514#endif 533#endif
diff --git a/drivers/pci/hotplug/pciehp_ctrl.c b/drivers/pci/hotplug/pciehp_ctrl.c
index f1e0966cee95..b23061c56115 100644
--- a/drivers/pci/hotplug/pciehp_ctrl.c
+++ b/drivers/pci/hotplug/pciehp_ctrl.c
@@ -37,8 +37,6 @@
37#include "pciehp.h" 37#include "pciehp.h"
38 38
39static void interrupt_event_handler(struct work_struct *work); 39static void interrupt_event_handler(struct work_struct *work);
40static int pciehp_enable_slot(struct slot *p_slot);
41static int pciehp_disable_slot(struct slot *p_slot);
42 40
43static int queue_interrupt_event(struct slot *p_slot, u32 event_type) 41static int queue_interrupt_event(struct slot *p_slot, u32 event_type)
44{ 42{
@@ -197,12 +195,6 @@ static void set_slot_off(struct controller *ctrl, struct slot * pslot)
197 __FUNCTION__); 195 __FUNCTION__);
198 return; 196 return;
199 } 197 }
200 /*
201 * After turning power off, we must wait for at least
202 * 1 second before taking any action that relies on
203 * power having been removed from the slot/adapter.
204 */
205 msleep(1000);
206 } 198 }
207} 199}
208 200
@@ -215,15 +207,12 @@ static void set_slot_off(struct controller *ctrl, struct slot * pslot)
215 */ 207 */
216static int board_added(struct slot *p_slot) 208static int board_added(struct slot *p_slot)
217{ 209{
218 u8 hp_slot;
219 int retval = 0; 210 int retval = 0;
220 struct controller *ctrl = p_slot->ctrl; 211 struct controller *ctrl = p_slot->ctrl;
221 212
222 hp_slot = p_slot->device - ctrl->slot_device_offset;
223
224 dbg("%s: slot device, slot offset, hp slot = %d, %d ,%d\n", 213 dbg("%s: slot device, slot offset, hp slot = %d, %d ,%d\n",
225 __FUNCTION__, p_slot->device, 214 __FUNCTION__, p_slot->device,
226 ctrl->slot_device_offset, hp_slot); 215 ctrl->slot_device_offset, p_slot->hp_slot);
227 216
228 if (POWER_CTRL(ctrl->ctrlcap)) { 217 if (POWER_CTRL(ctrl->ctrlcap)) {
229 /* Power on slot */ 218 /* Power on slot */
@@ -281,8 +270,6 @@ err_exit:
281 */ 270 */
282static int remove_board(struct slot *p_slot) 271static int remove_board(struct slot *p_slot)
283{ 272{
284 u8 device;
285 u8 hp_slot;
286 int retval = 0; 273 int retval = 0;
287 struct controller *ctrl = p_slot->ctrl; 274 struct controller *ctrl = p_slot->ctrl;
288 275
@@ -290,11 +277,7 @@ static int remove_board(struct slot *p_slot)
290 if (retval) 277 if (retval)
291 return retval; 278 return retval;
292 279
293 device = p_slot->device; 280 dbg("In %s, hp_slot = %d\n", __FUNCTION__, p_slot->hp_slot);
294 hp_slot = p_slot->device - ctrl->slot_device_offset;
295 p_slot = pciehp_find_slot(ctrl, hp_slot + ctrl->slot_device_offset);
296
297 dbg("In %s, hp_slot = %d\n", __FUNCTION__, hp_slot);
298 281
299 if (POWER_CTRL(ctrl->ctrlcap)) { 282 if (POWER_CTRL(ctrl->ctrlcap)) {
300 /* power off slot */ 283 /* power off slot */
@@ -621,12 +604,6 @@ int pciehp_disable_slot(struct slot *p_slot)
621 mutex_unlock(&p_slot->ctrl->crit_sect); 604 mutex_unlock(&p_slot->ctrl->crit_sect);
622 return -EINVAL; 605 return -EINVAL;
623 } 606 }
624 /*
625 * After turning power off, we must wait for at least
626 * 1 second before taking any action that relies on
627 * power having been removed from the slot/adapter.
628 */
629 msleep(1000);
630 } 607 }
631 608
632 ret = remove_board(p_slot); 609 ret = remove_board(p_slot);
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 06d025b8b13f..6eba9b2cfb90 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -636,15 +636,57 @@ static int hpc_power_on_slot(struct slot * slot)
636 return retval; 636 return retval;
637} 637}
638 638
639static inline int pcie_mask_bad_dllp(struct controller *ctrl)
640{
641 struct pci_dev *dev = ctrl->pci_dev;
642 int pos;
643 u32 reg;
644
645 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
646 if (!pos)
647 return 0;
648 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
649 if (reg & PCI_ERR_COR_BAD_DLLP)
650 return 0;
651 reg |= PCI_ERR_COR_BAD_DLLP;
652 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
653 return 1;
654}
655
656static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
657{
658 struct pci_dev *dev = ctrl->pci_dev;
659 u32 reg;
660 int pos;
661
662 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
663 if (!pos)
664 return;
665 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg);
666 if (!(reg & PCI_ERR_COR_BAD_DLLP))
667 return;
668 reg &= ~PCI_ERR_COR_BAD_DLLP;
669 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
670}
671
639static int hpc_power_off_slot(struct slot * slot) 672static int hpc_power_off_slot(struct slot * slot)
640{ 673{
641 struct controller *ctrl = slot->ctrl; 674 struct controller *ctrl = slot->ctrl;
642 u16 slot_cmd; 675 u16 slot_cmd;
643 u16 cmd_mask; 676 u16 cmd_mask;
644 int retval = 0; 677 int retval = 0;
678 int changed;
645 679
646 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot); 680 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
647 681
682 /*
683 * Set Bad DLLP Mask bit in Correctable Error Mask
684 * Register. This is the workaround against Bad DLLP error
685 * that sometimes happens during turning power off the slot
686 * which conforms to PCI Express 1.0a spec.
687 */
688 changed = pcie_mask_bad_dllp(ctrl);
689
648 slot_cmd = POWER_OFF; 690 slot_cmd = POWER_OFF;
649 cmd_mask = PWR_CTRL; 691 cmd_mask = PWR_CTRL;
650 /* 692 /*
@@ -674,6 +716,16 @@ static int hpc_power_off_slot(struct slot * slot)
674 dbg("%s: SLOTCTRL %x write cmd %x\n", 716 dbg("%s: SLOTCTRL %x write cmd %x\n",
675 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd); 717 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
676 718
719 /*
720 * After turning power off, we must wait for at least 1 second
721 * before taking any action that relies on power having been
722 * removed from the slot/adapter.
723 */
724 msleep(1000);
725
726 if (changed)
727 pcie_unmask_bad_dllp(ctrl);
728
677 return retval; 729 return retval;
678} 730}
679 731
@@ -1067,13 +1119,143 @@ int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1067} 1119}
1068#endif 1120#endif
1069 1121
1070int pcie_init(struct controller * ctrl, struct pcie_device *dev) 1122static int pcie_init_hardware_part1(struct controller *ctrl,
1123 struct pcie_device *dev)
1124{
1125 int rc;
1126 u16 temp_word;
1127 u32 slot_cap;
1128 u16 slot_status;
1129
1130 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1131 if (rc) {
1132 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1133 return -1;
1134 }
1135
1136 /* Mask Hot-plug Interrupt Enable */
1137 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1138 if (rc) {
1139 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1140 return -1;
1141 }
1142
1143 dbg("%s: SLOTCTRL %x value read %x\n",
1144 __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word);
1145 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) |
1146 0x00;
1147
1148 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1149 if (rc) {
1150 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1151 return -1;
1152 }
1153
1154 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1155 if (rc) {
1156 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1157 return -1;
1158 }
1159
1160 temp_word = 0x1F; /* Clear all events */
1161 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1162 if (rc) {
1163 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1164 return -1;
1165 }
1166 return 0;
1167}
1168
1169int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
1071{ 1170{
1072 int rc; 1171 int rc;
1073 u16 temp_word; 1172 u16 temp_word;
1074 u16 cap_reg;
1075 u16 intr_enable = 0; 1173 u16 intr_enable = 0;
1076 u32 slot_cap; 1174 u32 slot_cap;
1175 u16 slot_status;
1176
1177 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1178 if (rc) {
1179 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1180 goto abort;
1181 }
1182
1183 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1184
1185 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1186 if (rc) {
1187 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1188 goto abort;
1189 }
1190
1191 if (ATTN_BUTTN(slot_cap))
1192 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1193
1194 if (POWER_CTRL(slot_cap))
1195 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1196
1197 if (MRL_SENS(slot_cap))
1198 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1199
1200 temp_word = (temp_word & ~intr_enable) | intr_enable;
1201
1202 if (pciehp_poll_mode) {
1203 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1204 } else {
1205 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1206 }
1207
1208 /*
1209 * Unmask Hot-plug Interrupt Enable for the interrupt
1210 * notification mechanism case.
1211 */
1212 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1213 if (rc) {
1214 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1215 goto abort;
1216 }
1217 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1218 if (rc) {
1219 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1220 goto abort_disable_intr;
1221 }
1222
1223 temp_word = 0x1F; /* Clear all events */
1224 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1225 if (rc) {
1226 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1227 goto abort_disable_intr;
1228 }
1229
1230 if (pciehp_force) {
1231 dbg("Bypassing BIOS check for pciehp use on %s\n",
1232 pci_name(ctrl->pci_dev));
1233 } else {
1234 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1235 if (rc)
1236 goto abort_disable_intr;
1237 }
1238
1239 return 0;
1240
1241 /* We end up here for the many possible ways to fail this API. */
1242abort_disable_intr:
1243 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1244 if (!rc) {
1245 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1246 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1247 }
1248 if (rc)
1249 err("%s : disabling interrupts failed\n", __FUNCTION__);
1250abort:
1251 return -1;
1252}
1253
1254int pcie_init(struct controller *ctrl, struct pcie_device *dev)
1255{
1256 int rc;
1257 u16 cap_reg;
1258 u32 slot_cap;
1077 int cap_base; 1259 int cap_base;
1078 u16 slot_status, slot_ctrl; 1260 u16 slot_status, slot_ctrl;
1079 struct pci_dev *pdev; 1261 struct pci_dev *pdev;
@@ -1084,9 +1266,10 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1084 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n", 1266 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1085 __FUNCTION__, pdev->vendor, pdev->device); 1267 __FUNCTION__, pdev->vendor, pdev->device);
1086 1268
1087 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) { 1269 cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1270 if (cap_base == 0) {
1088 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__); 1271 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1089 goto abort_free_ctlr; 1272 goto abort;
1090 } 1273 }
1091 1274
1092 ctrl->cap_base = cap_base; 1275 ctrl->cap_base = cap_base;
@@ -1096,7 +1279,7 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1096 rc = pciehp_readw(ctrl, CAPREG, &cap_reg); 1279 rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1097 if (rc) { 1280 if (rc) {
1098 err("%s: Cannot read CAPREG register\n", __FUNCTION__); 1281 err("%s: Cannot read CAPREG register\n", __FUNCTION__);
1099 goto abort_free_ctlr; 1282 goto abort;
1100 } 1283 }
1101 dbg("%s: CAPREG offset %x cap_reg %x\n", 1284 dbg("%s: CAPREG offset %x cap_reg %x\n",
1102 __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg); 1285 __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
@@ -1106,26 +1289,26 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1106 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) { 1289 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1107 dbg("%s : This is not a root port or the port is not " 1290 dbg("%s : This is not a root port or the port is not "
1108 "connected to a slot\n", __FUNCTION__); 1291 "connected to a slot\n", __FUNCTION__);
1109 goto abort_free_ctlr; 1292 goto abort;
1110 } 1293 }
1111 1294
1112 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap); 1295 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1113 if (rc) { 1296 if (rc) {
1114 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__); 1297 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1115 goto abort_free_ctlr; 1298 goto abort;
1116 } 1299 }
1117 dbg("%s: SLOTCAP offset %x slot_cap %x\n", 1300 dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1118 __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap); 1301 __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
1119 1302
1120 if (!(slot_cap & HP_CAP)) { 1303 if (!(slot_cap & HP_CAP)) {
1121 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__); 1304 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1122 goto abort_free_ctlr; 1305 goto abort;
1123 } 1306 }
1124 /* For debugging purpose */ 1307 /* For debugging purpose */
1125 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status); 1308 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1126 if (rc) { 1309 if (rc) {
1127 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__); 1310 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1128 goto abort_free_ctlr; 1311 goto abort;
1129 } 1312 }
1130 dbg("%s: SLOTSTATUS offset %x slot_status %x\n", 1313 dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1131 __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status); 1314 __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
@@ -1133,7 +1316,7 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1133 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl); 1316 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1134 if (rc) { 1317 if (rc) {
1135 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 1318 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1136 goto abort_free_ctlr; 1319 goto abort;
1137 } 1320 }
1138 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n", 1321 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1139 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl); 1322 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
@@ -1161,36 +1344,9 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1161 ctrl->first_slot = slot_cap >> 19; 1344 ctrl->first_slot = slot_cap >> 19;
1162 ctrl->ctrlcap = slot_cap & 0x0000007f; 1345 ctrl->ctrlcap = slot_cap & 0x0000007f;
1163 1346
1164 /* Mask Hot-plug Interrupt Enable */ 1347 rc = pcie_init_hardware_part1(ctrl, dev);
1165 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); 1348 if (rc)
1166 if (rc) { 1349 goto abort;
1167 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1168 goto abort_free_ctlr;
1169 }
1170
1171 dbg("%s: SLOTCTRL %x value read %x\n",
1172 __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word);
1173 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) |
1174 0x00;
1175
1176 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1177 if (rc) {
1178 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1179 goto abort_free_ctlr;
1180 }
1181
1182 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1183 if (rc) {
1184 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1185 goto abort_free_ctlr;
1186 }
1187
1188 temp_word = 0x1F; /* Clear all events */
1189 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1190 if (rc) {
1191 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1192 goto abort_free_ctlr;
1193 }
1194 1350
1195 if (pciehp_poll_mode) { 1351 if (pciehp_poll_mode) {
1196 /* Install interrupt polling timer. Start with 10 sec delay */ 1352 /* Install interrupt polling timer. Start with 10 sec delay */
@@ -1206,7 +1362,7 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1206 if (rc) { 1362 if (rc) {
1207 err("Can't get irq %d for the hotplug controller\n", 1363 err("Can't get irq %d for the hotplug controller\n",
1208 ctrl->pci_dev->irq); 1364 ctrl->pci_dev->irq);
1209 goto abort_free_ctlr; 1365 goto abort;
1210 } 1366 }
1211 } 1367 }
1212 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number, 1368 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
@@ -1224,82 +1380,16 @@ int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1224 } 1380 }
1225 } 1381 }
1226 1382
1227 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word); 1383 rc = pcie_init_hardware_part2(ctrl, dev);
1228 if (rc) { 1384 if (rc == 0) {
1229 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__); 1385 ctrl->hpc_ops = &pciehp_hpc_ops;
1230 goto abort_free_irq; 1386 return 0;
1231 } 1387 }
1232
1233 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1234
1235 if (ATTN_BUTTN(slot_cap))
1236 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1237
1238 if (POWER_CTRL(slot_cap))
1239 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1240
1241 if (MRL_SENS(slot_cap))
1242 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1243
1244 temp_word = (temp_word & ~intr_enable) | intr_enable;
1245
1246 if (pciehp_poll_mode) {
1247 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1248 } else {
1249 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1250 }
1251
1252 /*
1253 * Unmask Hot-plug Interrupt Enable for the interrupt
1254 * notification mechanism case.
1255 */
1256 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1257 if (rc) {
1258 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1259 goto abort_free_irq;
1260 }
1261 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1262 if (rc) {
1263 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1264 goto abort_disable_intr;
1265 }
1266
1267 temp_word = 0x1F; /* Clear all events */
1268 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1269 if (rc) {
1270 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1271 goto abort_disable_intr;
1272 }
1273
1274 if (pciehp_force) {
1275 dbg("Bypassing BIOS check for pciehp use on %s\n",
1276 pci_name(ctrl->pci_dev));
1277 } else {
1278 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1279 if (rc)
1280 goto abort_disable_intr;
1281 }
1282
1283 ctrl->hpc_ops = &pciehp_hpc_ops;
1284
1285 return 0;
1286
1287 /* We end up here for the many possible ways to fail this API. */
1288abort_disable_intr:
1289 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1290 if (!rc) {
1291 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1292 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1293 }
1294 if (rc)
1295 err("%s : disabling interrupts failed\n", __FUNCTION__);
1296
1297abort_free_irq: 1388abort_free_irq:
1298 if (pciehp_poll_mode) 1389 if (pciehp_poll_mode)
1299 del_timer_sync(&ctrl->poll_timer); 1390 del_timer_sync(&ctrl->poll_timer);
1300 else 1391 else
1301 free_irq(ctrl->pci_dev->irq, ctrl); 1392 free_irq(ctrl->pci_dev->irq, ctrl);
1302 1393abort:
1303abort_free_ctlr:
1304 return -1; 1394 return -1;
1305} 1395}
diff --git a/drivers/pci/hotplug/pciehp_pci.c b/drivers/pci/hotplug/pciehp_pci.c
index c424aded13fb..dd50713966d1 100644
--- a/drivers/pci/hotplug/pciehp_pci.c
+++ b/drivers/pci/hotplug/pciehp_pci.c
@@ -105,12 +105,7 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
105 } 105 }
106 106
107 /* Find Advanced Error Reporting Enhanced Capability */ 107 /* Find Advanced Error Reporting Enhanced Capability */
108 pos = 256; 108 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
109 do {
110 pci_read_config_dword(dev, pos, &reg32);
111 if (PCI_EXT_CAP_ID(reg32) == PCI_EXT_CAP_ID_ERR)
112 break;
113 } while ((pos = PCI_EXT_CAP_NEXT(reg32)));
114 if (!pos) 109 if (!pos)
115 return; 110 return;
116 111
@@ -248,11 +243,15 @@ int pciehp_unconfigure_device(struct slot *p_slot)
248 u8 bctl = 0; 243 u8 bctl = 0;
249 u8 presence = 0; 244 u8 presence = 0;
250 struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate; 245 struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate;
246 u16 command;
251 247
252 dbg("%s: bus/dev = %x/%x\n", __FUNCTION__, p_slot->bus, 248 dbg("%s: bus/dev = %x/%x\n", __FUNCTION__, p_slot->bus,
253 p_slot->device); 249 p_slot->device);
250 ret = p_slot->hpc_ops->get_adapter_status(p_slot, &presence);
251 if (ret)
252 presence = 0;
254 253
255 for (j=0; j<8 ; j++) { 254 for (j = 0; j < 8; j++) {
256 struct pci_dev* temp = pci_get_slot(parent, 255 struct pci_dev* temp = pci_get_slot(parent,
257 (p_slot->device << 3) | j); 256 (p_slot->device << 3) | j);
258 if (!temp) 257 if (!temp)
@@ -263,21 +262,26 @@ int pciehp_unconfigure_device(struct slot *p_slot)
263 pci_dev_put(temp); 262 pci_dev_put(temp);
264 continue; 263 continue;
265 } 264 }
266 if (temp->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 265 if (temp->hdr_type == PCI_HEADER_TYPE_BRIDGE && presence) {
267 ret = p_slot->hpc_ops->get_adapter_status(p_slot, 266 pci_read_config_byte(temp, PCI_BRIDGE_CONTROL, &bctl);
268 &presence); 267 if (bctl & PCI_BRIDGE_CTL_VGA) {
269 if (!ret && presence) { 268 err("Cannot remove display device %s\n",
270 pci_read_config_byte(temp, PCI_BRIDGE_CONTROL, 269 pci_name(temp));
271 &bctl); 270 pci_dev_put(temp);
272 if (bctl & PCI_BRIDGE_CTL_VGA) { 271 continue;
273 err("Cannot remove display device %s\n",
274 pci_name(temp));
275 pci_dev_put(temp);
276 continue;
277 }
278 } 272 }
279 } 273 }
280 pci_remove_bus_device(temp); 274 pci_remove_bus_device(temp);
275 /*
276 * Ensure that no new Requests will be generated from
277 * the device.
278 */
279 if (presence) {
280 pci_read_config_word(temp, PCI_COMMAND, &command);
281 command &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
282 command |= PCI_COMMAND_INTX_DISABLE;
283 pci_write_config_word(temp, PCI_COMMAND, command);
284 }
281 pci_dev_put(temp); 285 pci_dev_put(temp);
282 } 286 }
283 /* 287 /*
@@ -288,4 +292,3 @@ int pciehp_unconfigure_device(struct slot *p_slot)
288 292
289 return rc; 293 return rc;
290} 294}
291
diff --git a/drivers/pci/hotplug/rpaphp.h b/drivers/pci/hotplug/rpaphp.h
index c822a779653f..7d5921b1ee78 100644
--- a/drivers/pci/hotplug/rpaphp.h
+++ b/drivers/pci/hotplug/rpaphp.h
@@ -74,7 +74,6 @@ struct slot {
74 u32 type; 74 u32 type;
75 u32 power_domain; 75 u32 power_domain;
76 char *name; 76 char *name;
77 char *location;
78 struct device_node *dn; 77 struct device_node *dn;
79 struct pci_bus *bus; 78 struct pci_bus *bus;
80 struct list_head *pci_devs; 79 struct list_head *pci_devs;
diff --git a/drivers/pci/hotplug/rpaphp_pci.c b/drivers/pci/hotplug/rpaphp_pci.c
index 0de84533cd80..6571e9b4c2ec 100644
--- a/drivers/pci/hotplug/rpaphp_pci.c
+++ b/drivers/pci/hotplug/rpaphp_pci.c
@@ -64,19 +64,6 @@ int rpaphp_get_sensor_state(struct slot *slot, int *state)
64 return rc; 64 return rc;
65} 65}
66 66
67static void set_slot_name(struct slot *slot)
68{
69 struct pci_bus *bus = slot->bus;
70 struct pci_dev *bridge;
71
72 bridge = bus->self;
73 if (bridge)
74 strcpy(slot->name, pci_name(bridge));
75 else
76 sprintf(slot->name, "%04x:%02x:00.0", pci_domain_nr(bus),
77 bus->number);
78}
79
80/** 67/**
81 * rpaphp_enable_slot - record slot state, config pci device 68 * rpaphp_enable_slot - record slot state, config pci device
82 * @slot: target &slot 69 * @slot: target &slot
@@ -115,7 +102,6 @@ int rpaphp_enable_slot(struct slot *slot)
115 info->adapter_status = EMPTY; 102 info->adapter_status = EMPTY;
116 slot->bus = bus; 103 slot->bus = bus;
117 slot->pci_devs = &bus->devices; 104 slot->pci_devs = &bus->devices;
118 set_slot_name(slot);
119 105
120 /* if there's an adapter in the slot, go add the pci devices */ 106 /* if there's an adapter in the slot, go add the pci devices */
121 if (state == PRESENT) { 107 if (state == PRESENT) {
diff --git a/drivers/pci/hotplug/rpaphp_slot.c b/drivers/pci/hotplug/rpaphp_slot.c
index d4ee8723fcb3..8ad3debb3794 100644
--- a/drivers/pci/hotplug/rpaphp_slot.c
+++ b/drivers/pci/hotplug/rpaphp_slot.c
@@ -33,23 +33,31 @@
33#include <asm/rtas.h> 33#include <asm/rtas.h>
34#include "rpaphp.h" 34#include "rpaphp.h"
35 35
36static ssize_t location_read_file (struct hotplug_slot *php_slot, char *buf) 36static ssize_t address_read_file (struct hotplug_slot *php_slot, char *buf)
37{ 37{
38 char *value; 38 int retval;
39 int retval = -ENOENT;
40 struct slot *slot = (struct slot *)php_slot->private; 39 struct slot *slot = (struct slot *)php_slot->private;
40 struct pci_bus *bus;
41 41
42 if (!slot) 42 if (!slot)
43 return retval; 43 return -ENOENT;
44
45 bus = slot->bus;
46 if (!bus)
47 return -ENOENT;
48
49 if (bus->self)
50 retval = sprintf(buf, pci_name(bus->self));
51 else
52 retval = sprintf(buf, "%04x:%02x:00.0",
53 pci_domain_nr(bus), bus->number);
44 54
45 value = slot->location;
46 retval = sprintf (buf, "%s\n", value);
47 return retval; 55 return retval;
48} 56}
49 57
50static struct hotplug_slot_attribute php_attr_location = { 58static struct hotplug_slot_attribute php_attr_address = {
51 .attr = {.name = "phy_location", .mode = S_IFREG | S_IRUGO}, 59 .attr = {.name = "address", .mode = S_IFREG | S_IRUGO},
52 .show = location_read_file, 60 .show = address_read_file,
53}; 61};
54 62
55/* free up the memory used by a slot */ 63/* free up the memory used by a slot */
@@ -64,7 +72,6 @@ void dealloc_slot_struct(struct slot *slot)
64 kfree(slot->hotplug_slot->info); 72 kfree(slot->hotplug_slot->info);
65 kfree(slot->hotplug_slot->name); 73 kfree(slot->hotplug_slot->name);
66 kfree(slot->hotplug_slot); 74 kfree(slot->hotplug_slot);
67 kfree(slot->location);
68 kfree(slot); 75 kfree(slot);
69} 76}
70 77
@@ -83,16 +90,13 @@ struct slot *alloc_slot_struct(struct device_node *dn,
83 GFP_KERNEL); 90 GFP_KERNEL);
84 if (!slot->hotplug_slot->info) 91 if (!slot->hotplug_slot->info)
85 goto error_hpslot; 92 goto error_hpslot;
86 slot->hotplug_slot->name = kmalloc(BUS_ID_SIZE + 1, GFP_KERNEL); 93 slot->hotplug_slot->name = kmalloc(strlen(drc_name) + 1, GFP_KERNEL);
87 if (!slot->hotplug_slot->name) 94 if (!slot->hotplug_slot->name)
88 goto error_info; 95 goto error_info;
89 slot->location = kmalloc(strlen(drc_name) + 1, GFP_KERNEL);
90 if (!slot->location)
91 goto error_name;
92 slot->name = slot->hotplug_slot->name; 96 slot->name = slot->hotplug_slot->name;
97 strcpy(slot->name, drc_name);
93 slot->dn = dn; 98 slot->dn = dn;
94 slot->index = drc_index; 99 slot->index = drc_index;
95 strcpy(slot->location, drc_name);
96 slot->power_domain = power_domain; 100 slot->power_domain = power_domain;
97 slot->hotplug_slot->private = slot; 101 slot->hotplug_slot->private = slot;
98 slot->hotplug_slot->ops = &rpaphp_hotplug_slot_ops; 102 slot->hotplug_slot->ops = &rpaphp_hotplug_slot_ops;
@@ -100,8 +104,6 @@ struct slot *alloc_slot_struct(struct device_node *dn,
100 104
101 return (slot); 105 return (slot);
102 106
103error_name:
104 kfree(slot->hotplug_slot->name);
105error_info: 107error_info:
106 kfree(slot->hotplug_slot->info); 108 kfree(slot->hotplug_slot->info);
107error_hpslot: 109error_hpslot:
@@ -133,8 +135,8 @@ int rpaphp_deregister_slot(struct slot *slot)
133 135
134 list_del(&slot->rpaphp_slot_list); 136 list_del(&slot->rpaphp_slot_list);
135 137
136 /* remove "phy_location" file */ 138 /* remove "address" file */
137 sysfs_remove_file(&php_slot->kobj, &php_attr_location.attr); 139 sysfs_remove_file(&php_slot->kobj, &php_attr_address.attr);
138 140
139 retval = pci_hp_deregister(php_slot); 141 retval = pci_hp_deregister(php_slot);
140 if (retval) 142 if (retval)
@@ -166,8 +168,8 @@ int rpaphp_register_slot(struct slot *slot)
166 return retval; 168 return retval;
167 } 169 }
168 170
169 /* create "phy_location" file */ 171 /* create "address" file */
170 retval = sysfs_create_file(&php_slot->kobj, &php_attr_location.attr); 172 retval = sysfs_create_file(&php_slot->kobj, &php_attr_address.attr);
171 if (retval) { 173 if (retval) {
172 err("sysfs_create_file failed with error %d\n", retval); 174 err("sysfs_create_file failed with error %d\n", retval);
173 goto sysfs_fail; 175 goto sysfs_fail;
@@ -175,8 +177,7 @@ int rpaphp_register_slot(struct slot *slot)
175 177
176 /* add slot to our internal list */ 178 /* add slot to our internal list */
177 list_add(&slot->rpaphp_slot_list, &rpaphp_slot_head); 179 list_add(&slot->rpaphp_slot_list, &rpaphp_slot_head);
178 info("Slot [%s](PCI location=%s) registered\n", slot->name, 180 info("Slot [%s] registered\n", slot->name);
179 slot->location);
180 return 0; 181 return 0;
181 182
182sysfs_fail: 183sysfs_fail:
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index 5183a45d45b5..e8aa138128ce 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -597,7 +597,7 @@ static void hpc_release_ctlr(struct controller *ctrl)
597 cleanup_slots(ctrl); 597 cleanup_slots(ctrl);
598 598
599 /* 599 /*
600 * Mask SERR and System Interrut generation 600 * Mask SERR and System Interrupt generation
601 */ 601 */
602 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE); 602 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
603 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK | 603 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c
index e079a5237c94..4e01df99681a 100644
--- a/drivers/pci/intel-iommu.c
+++ b/drivers/pci/intel-iommu.c
@@ -1781,7 +1781,7 @@ __intel_alloc_iova(struct device *dev, struct dmar_domain *domain,
1781 /* 1781 /*
1782 * First try to allocate an io virtual address in 1782 * First try to allocate an io virtual address in
1783 * DMA_32BIT_MASK and if that fails then try allocating 1783 * DMA_32BIT_MASK and if that fails then try allocating
1784 * from higer range 1784 * from higher range
1785 */ 1785 */
1786 iova = iommu_alloc_iova(domain, size, DMA_32BIT_MASK); 1786 iova = iommu_alloc_iova(domain, size, DMA_32BIT_MASK);
1787 if (!iova) 1787 if (!iova)
diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c
index 07c9f09c856d..26938da8f438 100644
--- a/drivers/pci/msi.c
+++ b/drivers/pci/msi.c
@@ -25,6 +25,51 @@
25 25
26static int pci_msi_enable = 1; 26static int pci_msi_enable = 1;
27 27
28/* Arch hooks */
29
30int __attribute__ ((weak))
31arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
32{
33 return 0;
34}
35
36int __attribute__ ((weak))
37arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *entry)
38{
39 return 0;
40}
41
42int __attribute__ ((weak))
43arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
44{
45 struct msi_desc *entry;
46 int ret;
47
48 list_for_each_entry(entry, &dev->msi_list, list) {
49 ret = arch_setup_msi_irq(dev, entry);
50 if (ret)
51 return ret;
52 }
53
54 return 0;
55}
56
57void __attribute__ ((weak)) arch_teardown_msi_irq(unsigned int irq)
58{
59 return;
60}
61
62void __attribute__ ((weak))
63arch_teardown_msi_irqs(struct pci_dev *dev)
64{
65 struct msi_desc *entry;
66
67 list_for_each_entry(entry, &dev->msi_list, list) {
68 if (entry->irq != 0)
69 arch_teardown_msi_irq(entry->irq);
70 }
71}
72
28static void msi_set_enable(struct pci_dev *dev, int enable) 73static void msi_set_enable(struct pci_dev *dev, int enable)
29{ 74{
30 int pos; 75 int pos;
@@ -230,7 +275,6 @@ static void pci_intx_for_msi(struct pci_dev *dev, int enable)
230 pci_intx(dev, enable); 275 pci_intx(dev, enable);
231} 276}
232 277
233#ifdef CONFIG_PM
234static void __pci_restore_msi_state(struct pci_dev *dev) 278static void __pci_restore_msi_state(struct pci_dev *dev)
235{ 279{
236 int pos; 280 int pos;
@@ -288,7 +332,7 @@ void pci_restore_msi_state(struct pci_dev *dev)
288 __pci_restore_msi_state(dev); 332 __pci_restore_msi_state(dev);
289 __pci_restore_msix_state(dev); 333 __pci_restore_msix_state(dev);
290} 334}
291#endif /* CONFIG_PM */ 335EXPORT_SYMBOL_GPL(pci_restore_msi_state);
292 336
293/** 337/**
294 * msi_capability_init - configure device's MSI capability structure 338 * msi_capability_init - configure device's MSI capability structure
@@ -683,49 +727,3 @@ void pci_msi_init_pci_dev(struct pci_dev *dev)
683{ 727{
684 INIT_LIST_HEAD(&dev->msi_list); 728 INIT_LIST_HEAD(&dev->msi_list);
685} 729}
686
687
688/* Arch hooks */
689
690int __attribute__ ((weak))
691arch_msi_check_device(struct pci_dev* dev, int nvec, int type)
692{
693 return 0;
694}
695
696int __attribute__ ((weak))
697arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *entry)
698{
699 return 0;
700}
701
702int __attribute__ ((weak))
703arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
704{
705 struct msi_desc *entry;
706 int ret;
707
708 list_for_each_entry(entry, &dev->msi_list, list) {
709 ret = arch_setup_msi_irq(dev, entry);
710 if (ret)
711 return ret;
712 }
713
714 return 0;
715}
716
717void __attribute__ ((weak)) arch_teardown_msi_irq(unsigned int irq)
718{
719 return;
720}
721
722void __attribute__ ((weak))
723arch_teardown_msi_irqs(struct pci_dev *dev)
724{
725 struct msi_desc *entry;
726
727 list_for_each_entry(entry, &dev->msi_list, list) {
728 if (entry->irq != 0)
729 arch_teardown_msi_irq(entry->irq);
730 }
731}
diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c
index 5c6a5d043007..e569645d59e2 100644
--- a/drivers/pci/pci-acpi.c
+++ b/drivers/pci/pci-acpi.c
@@ -156,13 +156,13 @@ run_osc_out:
156} 156}
157 157
158/** 158/**
159 * pci_osc_support_set - register OS support to Firmware 159 * __pci_osc_support_set - register OS support to Firmware
160 * @flags: OS support bits 160 * @flags: OS support bits
161 * 161 *
162 * Update OS support fields and doing a _OSC Query to obtain an update 162 * Update OS support fields and doing a _OSC Query to obtain an update
163 * from Firmware on supported control bits. 163 * from Firmware on supported control bits.
164 **/ 164 **/
165acpi_status pci_osc_support_set(u32 flags) 165acpi_status __pci_osc_support_set(u32 flags, const char *hid)
166{ 166{
167 u32 temp; 167 u32 temp;
168 acpi_status retval; 168 acpi_status retval;
@@ -176,7 +176,7 @@ acpi_status pci_osc_support_set(u32 flags)
176 temp = ctrlset_buf[OSC_CONTROL_TYPE]; 176 temp = ctrlset_buf[OSC_CONTROL_TYPE];
177 ctrlset_buf[OSC_QUERY_TYPE] = OSC_QUERY_ENABLE; 177 ctrlset_buf[OSC_QUERY_TYPE] = OSC_QUERY_ENABLE;
178 ctrlset_buf[OSC_CONTROL_TYPE] = OSC_CONTROL_MASKS; 178 ctrlset_buf[OSC_CONTROL_TYPE] = OSC_CONTROL_MASKS;
179 acpi_get_devices ( PCI_ROOT_HID_STRING, 179 acpi_get_devices(hid,
180 acpi_query_osc, 180 acpi_query_osc,
181 ctrlset_buf, 181 ctrlset_buf,
182 (void **) &retval ); 182 (void **) &retval );
@@ -188,7 +188,6 @@ acpi_status pci_osc_support_set(u32 flags)
188 } 188 }
189 return AE_OK; 189 return AE_OK;
190} 190}
191EXPORT_SYMBOL(pci_osc_support_set);
192 191
193/** 192/**
194 * pci_osc_control_set - commit requested control to Firmware 193 * pci_osc_control_set - commit requested control to Firmware
diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
index c4fa35d1dd77..e571c72e6753 100644
--- a/drivers/pci/pci-driver.c
+++ b/drivers/pci/pci-driver.c
@@ -186,13 +186,11 @@ static int pci_call_probe(struct pci_driver *drv, struct pci_dev *dev,
186 set_cpus_allowed(current, node_to_cpumask(node)); 186 set_cpus_allowed(current, node_to_cpumask(node));
187 /* And set default memory allocation policy */ 187 /* And set default memory allocation policy */
188 oldpol = current->mempolicy; 188 oldpol = current->mempolicy;
189 current->mempolicy = &default_policy; 189 current->mempolicy = NULL; /* fall back to system default policy */
190 mpol_get(current->mempolicy);
191#endif 190#endif
192 error = drv->probe(dev, id); 191 error = drv->probe(dev, id);
193#ifdef CONFIG_NUMA 192#ifdef CONFIG_NUMA
194 set_cpus_allowed(current, oldmask); 193 set_cpus_allowed(current, oldmask);
195 mpol_free(current->mempolicy);
196 current->mempolicy = oldpol; 194 current->mempolicy = oldpol;
197#endif 195#endif
198 return error; 196 return error;
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index 7d1877341aad..abf4203304e4 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -21,6 +21,7 @@
21#include <linux/topology.h> 21#include <linux/topology.h>
22#include <linux/mm.h> 22#include <linux/mm.h>
23#include <linux/capability.h> 23#include <linux/capability.h>
24#include <linux/aspm.h>
24#include "pci.h" 25#include "pci.h"
25 26
26static int sysfs_initialized; /* = 0 */ 27static int sysfs_initialized; /* = 0 */
@@ -358,7 +359,7 @@ pci_read_legacy_io(struct kobject *kobj, struct bin_attribute *bin_attr,
358 char *buf, loff_t off, size_t count) 359 char *buf, loff_t off, size_t count)
359{ 360{
360 struct pci_bus *bus = to_pci_bus(container_of(kobj, 361 struct pci_bus *bus = to_pci_bus(container_of(kobj,
361 struct class_device, 362 struct device,
362 kobj)); 363 kobj));
363 364
364 /* Only support 1, 2 or 4 byte accesses */ 365 /* Only support 1, 2 or 4 byte accesses */
@@ -383,7 +384,7 @@ pci_write_legacy_io(struct kobject *kobj, struct bin_attribute *bin_attr,
383 char *buf, loff_t off, size_t count) 384 char *buf, loff_t off, size_t count)
384{ 385{
385 struct pci_bus *bus = to_pci_bus(container_of(kobj, 386 struct pci_bus *bus = to_pci_bus(container_of(kobj,
386 struct class_device, 387 struct device,
387 kobj)); 388 kobj));
388 /* Only support 1, 2 or 4 byte accesses */ 389 /* Only support 1, 2 or 4 byte accesses */
389 if (count != 1 && count != 2 && count != 4) 390 if (count != 1 && count != 2 && count != 4)
@@ -407,7 +408,7 @@ pci_mmap_legacy_mem(struct kobject *kobj, struct bin_attribute *attr,
407 struct vm_area_struct *vma) 408 struct vm_area_struct *vma)
408{ 409{
409 struct pci_bus *bus = to_pci_bus(container_of(kobj, 410 struct pci_bus *bus = to_pci_bus(container_of(kobj,
410 struct class_device, 411 struct device,
411 kobj)); 412 kobj));
412 413
413 return pci_mmap_legacy_page_range(bus, vma); 414 return pci_mmap_legacy_page_range(bus, vma);
@@ -650,6 +651,8 @@ int __must_check pci_create_sysfs_dev_files (struct pci_dev *pdev)
650 if (pcibios_add_platform_entries(pdev)) 651 if (pcibios_add_platform_entries(pdev))
651 goto err_rom_file; 652 goto err_rom_file;
652 653
654 pcie_aspm_create_sysfs_dev_files(pdev);
655
653 return 0; 656 return 0;
654 657
655err_rom_file: 658err_rom_file:
@@ -679,6 +682,8 @@ void pci_remove_sysfs_dev_files(struct pci_dev *pdev)
679 if (!sysfs_initialized) 682 if (!sysfs_initialized)
680 return; 683 return;
681 684
685 pcie_aspm_remove_sysfs_dev_files(pdev);
686
682 if (pdev->cfg_size < 4096) 687 if (pdev->cfg_size < 4096)
683 sysfs_remove_bin_file(&pdev->dev.kobj, &pci_config_attr); 688 sysfs_remove_bin_file(&pdev->dev.kobj, &pci_config_attr);
684 else 689 else
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 7d4ce906d207..b3e9294e4a0e 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -18,6 +18,7 @@
18#include <linux/spinlock.h> 18#include <linux/spinlock.h>
19#include <linux/string.h> 19#include <linux/string.h>
20#include <linux/log2.h> 20#include <linux/log2.h>
21#include <linux/aspm.h>
21#include <asm/dma.h> /* isa_dma_bridge_buggy */ 22#include <asm/dma.h> /* isa_dma_bridge_buggy */
22#include "pci.h" 23#include "pci.h"
23 24
@@ -314,6 +315,24 @@ int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
314} 315}
315EXPORT_SYMBOL_GPL(pci_find_ht_capability); 316EXPORT_SYMBOL_GPL(pci_find_ht_capability);
316 317
318void pcie_wait_pending_transaction(struct pci_dev *dev)
319{
320 int pos;
321 u16 reg16;
322
323 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
324 if (!pos)
325 return;
326 while (1) {
327 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &reg16);
328 if (!(reg16 & PCI_EXP_DEVSTA_TRPND))
329 break;
330 cpu_relax();
331 }
332
333}
334EXPORT_SYMBOL_GPL(pcie_wait_pending_transaction);
335
317/** 336/**
318 * pci_find_parent_resource - return resource region of parent bus of given region 337 * pci_find_parent_resource - return resource region of parent bus of given region
319 * @dev: PCI device structure contains resources to be searched 338 * @dev: PCI device structure contains resources to be searched
@@ -353,7 +372,7 @@ pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
353 * Restore the BAR values for a given device, so as to make it 372 * Restore the BAR values for a given device, so as to make it
354 * accessible by its driver. 373 * accessible by its driver.
355 */ 374 */
356void 375static void
357pci_restore_bars(struct pci_dev *dev) 376pci_restore_bars(struct pci_dev *dev)
358{ 377{
359 int i, numres; 378 int i, numres;
@@ -501,6 +520,9 @@ pci_set_power_state(struct pci_dev *dev, pci_power_t state)
501 if (need_restore) 520 if (need_restore)
502 pci_restore_bars(dev); 521 pci_restore_bars(dev);
503 522
523 if (dev->bus->self)
524 pcie_aspm_pm_state_change(dev->bus->self);
525
504 return 0; 526 return 0;
505} 527}
506 528
@@ -551,6 +573,7 @@ static int pci_save_pcie_state(struct pci_dev *dev)
551 int pos, i = 0; 573 int pos, i = 0;
552 struct pci_cap_saved_state *save_state; 574 struct pci_cap_saved_state *save_state;
553 u16 *cap; 575 u16 *cap;
576 int found = 0;
554 577
555 pos = pci_find_capability(dev, PCI_CAP_ID_EXP); 578 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
556 if (pos <= 0) 579 if (pos <= 0)
@@ -559,6 +582,8 @@ static int pci_save_pcie_state(struct pci_dev *dev)
559 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 582 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
560 if (!save_state) 583 if (!save_state)
561 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL); 584 save_state = kzalloc(sizeof(*save_state) + sizeof(u16) * 4, GFP_KERNEL);
585 else
586 found = 1;
562 if (!save_state) { 587 if (!save_state) {
563 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); 588 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
564 return -ENOMEM; 589 return -ENOMEM;
@@ -569,7 +594,9 @@ static int pci_save_pcie_state(struct pci_dev *dev)
569 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]); 594 pci_read_config_word(dev, pos + PCI_EXP_LNKCTL, &cap[i++]);
570 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]); 595 pci_read_config_word(dev, pos + PCI_EXP_SLTCTL, &cap[i++]);
571 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]); 596 pci_read_config_word(dev, pos + PCI_EXP_RTCTL, &cap[i++]);
572 pci_add_saved_cap(dev, save_state); 597 save_state->cap_nr = PCI_CAP_ID_EXP;
598 if (!found)
599 pci_add_saved_cap(dev, save_state);
573 return 0; 600 return 0;
574} 601}
575 602
@@ -597,14 +624,17 @@ static int pci_save_pcix_state(struct pci_dev *dev)
597 int pos, i = 0; 624 int pos, i = 0;
598 struct pci_cap_saved_state *save_state; 625 struct pci_cap_saved_state *save_state;
599 u16 *cap; 626 u16 *cap;
627 int found = 0;
600 628
601 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 629 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
602 if (pos <= 0) 630 if (pos <= 0)
603 return 0; 631 return 0;
604 632
605 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP); 633 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
606 if (!save_state) 634 if (!save_state)
607 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL); 635 save_state = kzalloc(sizeof(*save_state) + sizeof(u16), GFP_KERNEL);
636 else
637 found = 1;
608 if (!save_state) { 638 if (!save_state) {
609 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n"); 639 dev_err(&dev->dev, "Out of memory in pci_save_pcie_state\n");
610 return -ENOMEM; 640 return -ENOMEM;
@@ -612,7 +642,9 @@ static int pci_save_pcix_state(struct pci_dev *dev)
612 cap = (u16 *)&save_state->data[0]; 642 cap = (u16 *)&save_state->data[0];
613 643
614 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]); 644 pci_read_config_word(dev, pos + PCI_X_CMD, &cap[i++]);
615 pci_add_saved_cap(dev, save_state); 645 save_state->cap_nr = PCI_CAP_ID_PCIX;
646 if (!found)
647 pci_add_saved_cap(dev, save_state);
616 return 0; 648 return 0;
617} 649}
618 650
@@ -713,23 +745,19 @@ int pci_reenable_device(struct pci_dev *dev)
713 return 0; 745 return 0;
714} 746}
715 747
716/** 748static int __pci_enable_device_flags(struct pci_dev *dev,
717 * pci_enable_device_bars - Initialize some of a device for use 749 resource_size_t flags)
718 * @dev: PCI device to be initialized
719 * @bars: bitmask of BAR's that must be configured
720 *
721 * Initialize device before it's used by a driver. Ask low-level code
722 * to enable selected I/O and memory resources. Wake up the device if it
723 * was suspended. Beware, this function can fail.
724 */
725int
726pci_enable_device_bars(struct pci_dev *dev, int bars)
727{ 750{
728 int err; 751 int err;
752 int i, bars = 0;
729 753
730 if (atomic_add_return(1, &dev->enable_cnt) > 1) 754 if (atomic_add_return(1, &dev->enable_cnt) > 1)
731 return 0; /* already enabled */ 755 return 0; /* already enabled */
732 756
757 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
758 if (dev->resource[i].flags & flags)
759 bars |= (1 << i);
760
733 err = do_pci_enable_device(dev, bars); 761 err = do_pci_enable_device(dev, bars);
734 if (err < 0) 762 if (err < 0)
735 atomic_dec(&dev->enable_cnt); 763 atomic_dec(&dev->enable_cnt);
@@ -737,6 +765,32 @@ pci_enable_device_bars(struct pci_dev *dev, int bars)
737} 765}
738 766
739/** 767/**
768 * pci_enable_device_io - Initialize a device for use with IO space
769 * @dev: PCI device to be initialized
770 *
771 * Initialize device before it's used by a driver. Ask low-level code
772 * to enable I/O resources. Wake up the device if it was suspended.
773 * Beware, this function can fail.
774 */
775int pci_enable_device_io(struct pci_dev *dev)
776{
777 return __pci_enable_device_flags(dev, IORESOURCE_IO);
778}
779
780/**
781 * pci_enable_device_mem - Initialize a device for use with Memory space
782 * @dev: PCI device to be initialized
783 *
784 * Initialize device before it's used by a driver. Ask low-level code
785 * to enable Memory resources. Wake up the device if it was suspended.
786 * Beware, this function can fail.
787 */
788int pci_enable_device_mem(struct pci_dev *dev)
789{
790 return __pci_enable_device_flags(dev, IORESOURCE_MEM);
791}
792
793/**
740 * pci_enable_device - Initialize device before it's used by a driver. 794 * pci_enable_device - Initialize device before it's used by a driver.
741 * @dev: PCI device to be initialized 795 * @dev: PCI device to be initialized
742 * 796 *
@@ -749,7 +803,7 @@ pci_enable_device_bars(struct pci_dev *dev, int bars)
749 */ 803 */
750int pci_enable_device(struct pci_dev *dev) 804int pci_enable_device(struct pci_dev *dev)
751{ 805{
752 return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1); 806 return __pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
753} 807}
754 808
755/* 809/*
@@ -885,6 +939,9 @@ pci_disable_device(struct pci_dev *dev)
885 if (atomic_sub_return(1, &dev->enable_cnt) != 0) 939 if (atomic_sub_return(1, &dev->enable_cnt) != 0)
886 return; 940 return;
887 941
942 /* Wait for all transactions are finished before disabling the device */
943 pcie_wait_pending_transaction(dev);
944
888 pci_read_config_word(dev, PCI_COMMAND, &pci_command); 945 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
889 if (pci_command & PCI_COMMAND_MASTER) { 946 if (pci_command & PCI_COMMAND_MASTER) {
890 pci_command &= ~PCI_COMMAND_MASTER; 947 pci_command &= ~PCI_COMMAND_MASTER;
@@ -1619,9 +1676,9 @@ early_param("pci", pci_setup);
1619 1676
1620device_initcall(pci_init); 1677device_initcall(pci_init);
1621 1678
1622EXPORT_SYMBOL_GPL(pci_restore_bars);
1623EXPORT_SYMBOL(pci_reenable_device); 1679EXPORT_SYMBOL(pci_reenable_device);
1624EXPORT_SYMBOL(pci_enable_device_bars); 1680EXPORT_SYMBOL(pci_enable_device_io);
1681EXPORT_SYMBOL(pci_enable_device_mem);
1625EXPORT_SYMBOL(pci_enable_device); 1682EXPORT_SYMBOL(pci_enable_device);
1626EXPORT_SYMBOL(pcim_enable_device); 1683EXPORT_SYMBOL(pcim_enable_device);
1627EXPORT_SYMBOL(pcim_pin_device); 1684EXPORT_SYMBOL(pcim_pin_device);
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index fc87e14b50de..eabeb1f2ec99 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -6,8 +6,10 @@ extern void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
6extern void pci_cleanup_rom(struct pci_dev *dev); 6extern void pci_cleanup_rom(struct pci_dev *dev);
7 7
8/* Firmware callbacks */ 8/* Firmware callbacks */
9extern pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state); 9extern pci_power_t (*platform_pci_choose_state)(struct pci_dev *dev,
10extern int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t state); 10 pm_message_t state);
11extern int (*platform_pci_set_power_state)(struct pci_dev *dev,
12 pci_power_t state);
11 13
12extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val); 14extern int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
13extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val); 15extern int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
@@ -45,12 +47,6 @@ static inline void pci_no_msi(void) { }
45static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { } 47static inline void pci_msi_init_pci_dev(struct pci_dev *dev) { }
46#endif 48#endif
47 49
48#if defined(CONFIG_PCI_MSI) && defined(CONFIG_PM)
49void pci_restore_msi_state(struct pci_dev *dev);
50#else
51static inline void pci_restore_msi_state(struct pci_dev *dev) {}
52#endif
53
54#ifdef CONFIG_PCIEAER 50#ifdef CONFIG_PCIEAER
55void pci_no_aer(void); 51void pci_no_aer(void);
56#else 52#else
@@ -68,14 +64,14 @@ static inline int pci_no_d1d2(struct pci_dev *dev)
68} 64}
69extern int pcie_mch_quirk; 65extern int pcie_mch_quirk;
70extern struct device_attribute pci_dev_attrs[]; 66extern struct device_attribute pci_dev_attrs[];
71extern struct class_device_attribute class_device_attr_cpuaffinity; 67extern struct device_attribute dev_attr_cpuaffinity;
72 68
73/** 69/**
74 * pci_match_one_device - Tell if a PCI device structure has a matching 70 * pci_match_one_device - Tell if a PCI device structure has a matching
75 * PCI device id structure 71 * PCI device id structure
76 * @id: single PCI device id structure to match 72 * @id: single PCI device id structure to match
77 * @dev: the PCI device structure to match against 73 * @dev: the PCI device structure to match against
78 * 74 *
79 * Returns the matching pci_device_id structure or %NULL if there is no match. 75 * Returns the matching pci_device_id structure or %NULL if there is no match.
80 */ 76 */
81static inline const struct pci_device_id * 77static inline const struct pci_device_id *
diff --git a/drivers/pci/pcie/Kconfig b/drivers/pci/pcie/Kconfig
index 287a9311716c..60104cf98796 100644
--- a/drivers/pci/pcie/Kconfig
+++ b/drivers/pci/pcie/Kconfig
@@ -26,3 +26,23 @@ config HOTPLUG_PCI_PCIE
26 When in doubt, say N. 26 When in doubt, say N.
27 27
28source "drivers/pci/pcie/aer/Kconfig" 28source "drivers/pci/pcie/aer/Kconfig"
29
30#
31# PCI Express ASPM
32#
33config PCIEASPM
34 bool "PCI Express ASPM support(Experimental)"
35 depends on PCI && EXPERIMENTAL
36 default y
37 help
38 This enables PCI Express ASPM (Active State Power Management) and
39 Clock Power Management. ASPM supports state L0/L0s/L1.
40
41 When in doubt, say N.
42config PCIEASPM_DEBUG
43 bool "Debug PCI Express ASPM"
44 depends on PCIEASPM
45 default n
46 help
47 This enables PCI Express ASPM debug support. It will add per-device
48 interface to control ASPM.
diff --git a/drivers/pci/pcie/Makefile b/drivers/pci/pcie/Makefile
index e00fb99acf44..11f6bb1eae24 100644
--- a/drivers/pci/pcie/Makefile
+++ b/drivers/pci/pcie/Makefile
@@ -2,6 +2,9 @@
2# Makefile for PCI-Express PORT Driver 2# Makefile for PCI-Express PORT Driver
3# 3#
4 4
5# Build PCI Express ASPM if needed
6obj-$(CONFIG_PCIEASPM) += aspm.o
7
5pcieportdrv-y := portdrv_core.o portdrv_pci.o portdrv_bus.o 8pcieportdrv-y := portdrv_core.o portdrv_pci.o portdrv_bus.o
6 9
7obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o 10obj-$(CONFIG_PCIEPORTBUS) += pcieportdrv.o
diff --git a/drivers/pci/pcie/aer/aerdrv_acpi.c b/drivers/pci/pcie/aer/aerdrv_acpi.c
index 1a1eb45a779e..8c199ae84f6d 100644
--- a/drivers/pci/pcie/aer/aerdrv_acpi.c
+++ b/drivers/pci/pcie/aer/aerdrv_acpi.c
@@ -31,26 +31,16 @@ int aer_osc_setup(struct pcie_device *pciedev)
31{ 31{
32 acpi_status status = AE_NOT_FOUND; 32 acpi_status status = AE_NOT_FOUND;
33 struct pci_dev *pdev = pciedev->port; 33 struct pci_dev *pdev = pciedev->port;
34 acpi_handle handle = DEVICE_ACPI_HANDLE(&pdev->dev); 34 acpi_handle handle = 0;
35 struct pci_bus *parent;
36 35
37 while (!handle) { 36 /* Find root host bridge */
38 if (!pdev || !pdev->bus->parent) 37 while (pdev->bus && pdev->bus->self)
39 break; 38 pdev = pdev->bus->self;
40 parent = pdev->bus->parent; 39 handle = acpi_get_pci_rootbridge_handle(
41 if (!parent->self) 40 pci_domain_nr(pdev->bus), pdev->bus->number);
42 /* Parent must be a host bridge */
43 handle = acpi_get_pci_rootbridge_handle(
44 pci_domain_nr(parent),
45 parent->number);
46 else
47 handle = DEVICE_ACPI_HANDLE(
48 &(parent->self->dev));
49 pdev = parent->self;
50 }
51 41
52 if (handle) { 42 if (handle) {
53 pci_osc_support_set(OSC_EXT_PCI_CONFIG_SUPPORT); 43 pcie_osc_support_set(OSC_EXT_PCI_CONFIG_SUPPORT);
54 status = pci_osc_control_set(handle, 44 status = pci_osc_control_set(handle,
55 OSC_PCI_EXPRESS_AER_CONTROL | 45 OSC_PCI_EXPRESS_AER_CONTROL |
56 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL); 46 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL);
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
new file mode 100644
index 000000000000..1a5adeb10c95
--- /dev/null
+++ b/drivers/pci/pcie/aspm.c
@@ -0,0 +1,802 @@
1/*
2 * File: drivers/pci/pcie/aspm.c
3 * Enabling PCIE link L0s/L1 state and Clock Power Management
4 *
5 * Copyright (C) 2007 Intel
6 * Copyright (C) Zhang Yanmin (yanmin.zhang@intel.com)
7 * Copyright (C) Shaohua Li (shaohua.li@intel.com)
8 */
9
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/pci_regs.h>
15#include <linux/errno.h>
16#include <linux/pm.h>
17#include <linux/init.h>
18#include <linux/slab.h>
19#include <linux/aspm.h>
20#include <acpi/acpi_bus.h>
21#include <linux/pci-acpi.h>
22#include "../pci.h"
23
24#ifdef MODULE_PARAM_PREFIX
25#undef MODULE_PARAM_PREFIX
26#endif
27#define MODULE_PARAM_PREFIX "pcie_aspm."
28
29struct endpoint_state {
30 unsigned int l0s_acceptable_latency;
31 unsigned int l1_acceptable_latency;
32};
33
34struct pcie_link_state {
35 struct list_head sibiling;
36 struct pci_dev *pdev;
37
38 /* ASPM state */
39 unsigned int support_state;
40 unsigned int enabled_state;
41 unsigned int bios_aspm_state;
42 /* upstream component */
43 unsigned int l0s_upper_latency;
44 unsigned int l1_upper_latency;
45 /* downstream component */
46 unsigned int l0s_down_latency;
47 unsigned int l1_down_latency;
48 /* Clock PM state*/
49 unsigned int clk_pm_capable;
50 unsigned int clk_pm_enabled;
51 unsigned int bios_clk_state;
52
53 /*
54 * A pcie downstream port only has one slot under it, so at most there
55 * are 8 functions
56 */
57 struct endpoint_state endpoints[8];
58};
59
60static int aspm_disabled;
61static DEFINE_MUTEX(aspm_lock);
62static LIST_HEAD(link_list);
63
64#define POLICY_DEFAULT 0 /* BIOS default setting */
65#define POLICY_PERFORMANCE 1 /* high performance */
66#define POLICY_POWERSAVE 2 /* high power saving */
67static int aspm_policy;
68static const char *policy_str[] = {
69 [POLICY_DEFAULT] = "default",
70 [POLICY_PERFORMANCE] = "performance",
71 [POLICY_POWERSAVE] = "powersave"
72};
73
74static int policy_to_aspm_state(struct pci_dev *pdev)
75{
76 struct pcie_link_state *link_state = pdev->link_state;
77
78 switch (aspm_policy) {
79 case POLICY_PERFORMANCE:
80 /* Disable ASPM and Clock PM */
81 return 0;
82 case POLICY_POWERSAVE:
83 /* Enable ASPM L0s/L1 */
84 return PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1;
85 case POLICY_DEFAULT:
86 return link_state->bios_aspm_state;
87 }
88 return 0;
89}
90
91static int policy_to_clkpm_state(struct pci_dev *pdev)
92{
93 struct pcie_link_state *link_state = pdev->link_state;
94
95 switch (aspm_policy) {
96 case POLICY_PERFORMANCE:
97 /* Disable ASPM and Clock PM */
98 return 0;
99 case POLICY_POWERSAVE:
100 /* Disable Clock PM */
101 return 1;
102 case POLICY_DEFAULT:
103 return link_state->bios_clk_state;
104 }
105 return 0;
106}
107
108static void pcie_set_clock_pm(struct pci_dev *pdev, int enable)
109{
110 struct pci_dev *child_dev;
111 int pos;
112 u16 reg16;
113 struct pcie_link_state *link_state = pdev->link_state;
114
115 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
116 pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
117 if (!pos)
118 return;
119 pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, &reg16);
120 if (enable)
121 reg16 |= PCI_EXP_LNKCTL_CLKREQ_EN;
122 else
123 reg16 &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
124 pci_write_config_word(child_dev, pos + PCI_EXP_LNKCTL, reg16);
125 }
126 link_state->clk_pm_enabled = !!enable;
127}
128
129static void pcie_check_clock_pm(struct pci_dev *pdev)
130{
131 int pos;
132 u32 reg32;
133 u16 reg16;
134 int capable = 1, enabled = 1;
135 struct pci_dev *child_dev;
136 struct pcie_link_state *link_state = pdev->link_state;
137
138 /* All functions should have the same cap and state, take the worst */
139 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
140 pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
141 if (!pos)
142 return;
143 pci_read_config_dword(child_dev, pos + PCI_EXP_LNKCAP, &reg32);
144 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
145 capable = 0;
146 enabled = 0;
147 break;
148 }
149 pci_read_config_word(child_dev, pos + PCI_EXP_LNKCTL, &reg16);
150 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
151 enabled = 0;
152 }
153 link_state->clk_pm_capable = capable;
154 link_state->clk_pm_enabled = enabled;
155 link_state->bios_clk_state = enabled;
156 pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev));
157}
158
159/*
160 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
161 * could use common clock. If they are, configure them to use the
162 * common clock. That will reduce the ASPM state exit latency.
163 */
164static void pcie_aspm_configure_common_clock(struct pci_dev *pdev)
165{
166 int pos, child_pos;
167 u16 reg16 = 0;
168 struct pci_dev *child_dev;
169 int same_clock = 1;
170
171 /*
172 * all functions of a slot should have the same Slot Clock
173 * Configuration, so just check one function
174 * */
175 child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev,
176 bus_list);
177 BUG_ON(!child_dev->is_pcie);
178
179 /* Check downstream component if bit Slot Clock Configuration is 1 */
180 child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
181 pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKSTA, &reg16);
182 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
183 same_clock = 0;
184
185 /* Check upstream component if bit Slot Clock Configuration is 1 */
186 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
187 pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, &reg16);
188 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
189 same_clock = 0;
190
191 /* Configure downstream component, all functions */
192 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
193 child_pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
194 pci_read_config_word(child_dev, child_pos + PCI_EXP_LNKCTL,
195 &reg16);
196 if (same_clock)
197 reg16 |= PCI_EXP_LNKCTL_CCC;
198 else
199 reg16 &= ~PCI_EXP_LNKCTL_CCC;
200 pci_write_config_word(child_dev, child_pos + PCI_EXP_LNKCTL,
201 reg16);
202 }
203
204 /* Configure upstream component */
205 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
206 if (same_clock)
207 reg16 |= PCI_EXP_LNKCTL_CCC;
208 else
209 reg16 &= ~PCI_EXP_LNKCTL_CCC;
210 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
211
212 /* retrain link */
213 reg16 |= PCI_EXP_LNKCTL_RL;
214 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
215
216 /* Wait for link training end */
217 while (1) {
218 pci_read_config_word(pdev, pos + PCI_EXP_LNKSTA, &reg16);
219 if (!(reg16 & PCI_EXP_LNKSTA_LT))
220 break;
221 cpu_relax();
222 }
223}
224
225/*
226 * calc_L0S_latency: Convert L0s latency encoding to ns
227 */
228static unsigned int calc_L0S_latency(unsigned int latency_encoding, int ac)
229{
230 unsigned int ns = 64;
231
232 if (latency_encoding == 0x7) {
233 if (ac)
234 ns = -1U;
235 else
236 ns = 5*1000; /* > 4us */
237 } else
238 ns *= (1 << latency_encoding);
239 return ns;
240}
241
242/*
243 * calc_L1_latency: Convert L1 latency encoding to ns
244 */
245static unsigned int calc_L1_latency(unsigned int latency_encoding, int ac)
246{
247 unsigned int ns = 1000;
248
249 if (latency_encoding == 0x7) {
250 if (ac)
251 ns = -1U;
252 else
253 ns = 65*1000; /* > 64us */
254 } else
255 ns *= (1 << latency_encoding);
256 return ns;
257}
258
259static void pcie_aspm_get_cap_device(struct pci_dev *pdev, u32 *state,
260 unsigned int *l0s, unsigned int *l1, unsigned int *enabled)
261{
262 int pos;
263 u16 reg16;
264 u32 reg32;
265 unsigned int latency;
266
267 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
268 pci_read_config_dword(pdev, pos + PCI_EXP_LNKCAP, &reg32);
269 *state = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10;
270 if (*state != PCIE_LINK_STATE_L0S &&
271 *state != (PCIE_LINK_STATE_L1|PCIE_LINK_STATE_L0S))
272 * state = 0;
273 if (*state == 0)
274 return;
275
276 latency = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12;
277 *l0s = calc_L0S_latency(latency, 0);
278 if (*state & PCIE_LINK_STATE_L1) {
279 latency = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15;
280 *l1 = calc_L1_latency(latency, 0);
281 }
282 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
283 *enabled = reg16 & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1);
284}
285
286static void pcie_aspm_cap_init(struct pci_dev *pdev)
287{
288 struct pci_dev *child_dev;
289 u32 state, tmp;
290 struct pcie_link_state *link_state = pdev->link_state;
291
292 /* upstream component states */
293 pcie_aspm_get_cap_device(pdev, &link_state->support_state,
294 &link_state->l0s_upper_latency,
295 &link_state->l1_upper_latency,
296 &link_state->enabled_state);
297 /* downstream component states, all functions have the same setting */
298 child_dev = list_entry(pdev->subordinate->devices.next, struct pci_dev,
299 bus_list);
300 pcie_aspm_get_cap_device(child_dev, &state,
301 &link_state->l0s_down_latency,
302 &link_state->l1_down_latency,
303 &tmp);
304 link_state->support_state &= state;
305 if (!link_state->support_state)
306 return;
307 link_state->enabled_state &= link_state->support_state;
308 link_state->bios_aspm_state = link_state->enabled_state;
309
310 /* ENDPOINT states*/
311 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
312 int pos;
313 u32 reg32;
314 unsigned int latency;
315 struct endpoint_state *ep_state =
316 &link_state->endpoints[PCI_FUNC(child_dev->devfn)];
317
318 if (child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
319 child_dev->pcie_type != PCI_EXP_TYPE_LEG_END)
320 continue;
321
322 pos = pci_find_capability(child_dev, PCI_CAP_ID_EXP);
323 pci_read_config_dword(child_dev, pos + PCI_EXP_DEVCAP, &reg32);
324 latency = (reg32 & PCI_EXP_DEVCAP_L0S) >> 6;
325 latency = calc_L0S_latency(latency, 1);
326 ep_state->l0s_acceptable_latency = latency;
327 if (link_state->support_state & PCIE_LINK_STATE_L1) {
328 latency = (reg32 & PCI_EXP_DEVCAP_L1) >> 9;
329 latency = calc_L1_latency(latency, 1);
330 ep_state->l1_acceptable_latency = latency;
331 }
332 }
333}
334
335static unsigned int __pcie_aspm_check_state_one(struct pci_dev *pdev,
336 unsigned int state)
337{
338 struct pci_dev *parent_dev, *tmp_dev;
339 unsigned int latency, l1_latency = 0;
340 struct pcie_link_state *link_state;
341 struct endpoint_state *ep_state;
342
343 parent_dev = pdev->bus->self;
344 link_state = parent_dev->link_state;
345 state &= link_state->support_state;
346 if (state == 0)
347 return 0;
348 ep_state = &link_state->endpoints[PCI_FUNC(pdev->devfn)];
349
350 /*
351 * Check latency for endpoint device.
352 * TBD: The latency from the endpoint to root complex vary per
353 * switch's upstream link state above the device. Here we just do a
354 * simple check which assumes all links above the device can be in L1
355 * state, that is we just consider the worst case. If switch's upstream
356 * link can't be put into L0S/L1, then our check is too strictly.
357 */
358 tmp_dev = pdev;
359 while (state & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {
360 parent_dev = tmp_dev->bus->self;
361 link_state = parent_dev->link_state;
362 if (state & PCIE_LINK_STATE_L0S) {
363 latency = max_t(unsigned int,
364 link_state->l0s_upper_latency,
365 link_state->l0s_down_latency);
366 if (latency > ep_state->l0s_acceptable_latency)
367 state &= ~PCIE_LINK_STATE_L0S;
368 }
369 if (state & PCIE_LINK_STATE_L1) {
370 latency = max_t(unsigned int,
371 link_state->l1_upper_latency,
372 link_state->l1_down_latency);
373 if (latency + l1_latency >
374 ep_state->l1_acceptable_latency)
375 state &= ~PCIE_LINK_STATE_L1;
376 }
377 if (!parent_dev->bus->self) /* parent_dev is a root port */
378 break;
379 else {
380 /*
381 * parent_dev is the downstream port of a switch, make
382 * tmp_dev the upstream port of the switch
383 */
384 tmp_dev = parent_dev->bus->self;
385 /*
386 * every switch on the path to root complex need 1 more
387 * microsecond for L1. Spec doesn't mention L0S.
388 */
389 if (state & PCIE_LINK_STATE_L1)
390 l1_latency += 1000;
391 }
392 }
393 return state;
394}
395
396static unsigned int pcie_aspm_check_state(struct pci_dev *pdev,
397 unsigned int state)
398{
399 struct pci_dev *child_dev;
400
401 /* If no child, disable the link */
402 if (list_empty(&pdev->subordinate->devices))
403 return 0;
404 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
405 if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
406 /*
407 * If downstream component of a link is pci bridge, we
408 * disable ASPM for now for the link
409 * */
410 state = 0;
411 break;
412 }
413 if ((child_dev->pcie_type != PCI_EXP_TYPE_ENDPOINT &&
414 child_dev->pcie_type != PCI_EXP_TYPE_LEG_END))
415 continue;
416 /* Device not in D0 doesn't need check latency */
417 if (child_dev->current_state == PCI_D1 ||
418 child_dev->current_state == PCI_D2 ||
419 child_dev->current_state == PCI_D3hot ||
420 child_dev->current_state == PCI_D3cold)
421 continue;
422 state = __pcie_aspm_check_state_one(child_dev, state);
423 }
424 return state;
425}
426
427static void __pcie_aspm_config_one_dev(struct pci_dev *pdev, unsigned int state)
428{
429 u16 reg16;
430 int pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
431
432 pci_read_config_word(pdev, pos + PCI_EXP_LNKCTL, &reg16);
433 reg16 &= ~0x3;
434 reg16 |= state;
435 pci_write_config_word(pdev, pos + PCI_EXP_LNKCTL, reg16);
436}
437
438static void __pcie_aspm_config_link(struct pci_dev *pdev, unsigned int state)
439{
440 struct pci_dev *child_dev;
441 int valid = 1;
442 struct pcie_link_state *link_state = pdev->link_state;
443
444 /*
445 * if the downstream component has pci bridge function, don't do ASPM
446 * now
447 */
448 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list) {
449 if (child_dev->pcie_type == PCI_EXP_TYPE_PCI_BRIDGE) {
450 valid = 0;
451 break;
452 }
453 }
454 if (!valid)
455 return;
456
457 /*
458 * spec 2.0 suggests all functions should be configured the same
459 * setting for ASPM. Enabling ASPM L1 should be done in upstream
460 * component first and then downstream, and vice versa for disabling
461 * ASPM L1. Spec doesn't mention L0S.
462 */
463 if (state & PCIE_LINK_STATE_L1)
464 __pcie_aspm_config_one_dev(pdev, state);
465
466 list_for_each_entry(child_dev, &pdev->subordinate->devices, bus_list)
467 __pcie_aspm_config_one_dev(child_dev, state);
468
469 if (!(state & PCIE_LINK_STATE_L1))
470 __pcie_aspm_config_one_dev(pdev, state);
471
472 link_state->enabled_state = state;
473}
474
475static void __pcie_aspm_configure_link_state(struct pci_dev *pdev,
476 unsigned int state)
477{
478 struct pcie_link_state *link_state = pdev->link_state;
479
480 if (link_state->support_state == 0)
481 return;
482 state &= PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1;
483
484 /* state 0 means disabling aspm */
485 state = pcie_aspm_check_state(pdev, state);
486 if (link_state->enabled_state == state)
487 return;
488 __pcie_aspm_config_link(pdev, state);
489}
490
491/*
492 * pcie_aspm_configure_link_state: enable/disable PCI express link state
493 * @pdev: the root port or switch downstream port
494 */
495static void pcie_aspm_configure_link_state(struct pci_dev *pdev,
496 unsigned int state)
497{
498 down_read(&pci_bus_sem);
499 mutex_lock(&aspm_lock);
500 __pcie_aspm_configure_link_state(pdev, state);
501 mutex_unlock(&aspm_lock);
502 up_read(&pci_bus_sem);
503}
504
505static void free_link_state(struct pci_dev *pdev)
506{
507 kfree(pdev->link_state);
508 pdev->link_state = NULL;
509}
510
511/*
512 * pcie_aspm_init_link_state: Initiate PCI express link state.
513 * It is called after the pcie and its children devices are scaned.
514 * @pdev: the root port or switch downstream port
515 */
516void pcie_aspm_init_link_state(struct pci_dev *pdev)
517{
518 unsigned int state;
519 struct pcie_link_state *link_state;
520 int error = 0;
521
522 if (aspm_disabled || !pdev->is_pcie || pdev->link_state)
523 return;
524 if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
525 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
526 return;
527 down_read(&pci_bus_sem);
528 if (list_empty(&pdev->subordinate->devices))
529 goto out;
530
531 mutex_lock(&aspm_lock);
532
533 link_state = kzalloc(sizeof(*link_state), GFP_KERNEL);
534 if (!link_state)
535 goto unlock_out;
536 pdev->link_state = link_state;
537
538 pcie_aspm_configure_common_clock(pdev);
539
540 pcie_aspm_cap_init(pdev);
541
542 /* config link state to avoid BIOS error */
543 state = pcie_aspm_check_state(pdev, policy_to_aspm_state(pdev));
544 __pcie_aspm_config_link(pdev, state);
545
546 pcie_check_clock_pm(pdev);
547
548 link_state->pdev = pdev;
549 list_add(&link_state->sibiling, &link_list);
550
551unlock_out:
552 if (error)
553 free_link_state(pdev);
554 mutex_unlock(&aspm_lock);
555out:
556 up_read(&pci_bus_sem);
557}
558
559/* @pdev: the endpoint device */
560void pcie_aspm_exit_link_state(struct pci_dev *pdev)
561{
562 struct pci_dev *parent = pdev->bus->self;
563 struct pcie_link_state *link_state = parent->link_state;
564
565 if (aspm_disabled || !pdev->is_pcie || !parent || !link_state)
566 return;
567 if (parent->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
568 parent->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
569 return;
570 down_read(&pci_bus_sem);
571 mutex_lock(&aspm_lock);
572
573 /*
574 * All PCIe functions are in one slot, remove one function will remove
575 * the the whole slot, so just wait
576 */
577 if (!list_empty(&parent->subordinate->devices))
578 goto out;
579
580 /* All functions are removed, so just disable ASPM for the link */
581 __pcie_aspm_config_one_dev(parent, 0);
582 list_del(&link_state->sibiling);
583 /* Clock PM is for endpoint device */
584
585 free_link_state(parent);
586out:
587 mutex_unlock(&aspm_lock);
588 up_read(&pci_bus_sem);
589}
590
591/* @pdev: the root port or switch downstream port */
592void pcie_aspm_pm_state_change(struct pci_dev *pdev)
593{
594 struct pcie_link_state *link_state = pdev->link_state;
595
596 if (aspm_disabled || !pdev->is_pcie || !pdev->link_state)
597 return;
598 if (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
599 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM)
600 return;
601 /*
602 * devices changed PM state, we should recheck if latency meets all
603 * functions' requirement
604 */
605 pcie_aspm_configure_link_state(pdev, link_state->enabled_state);
606}
607
608/*
609 * pci_disable_link_state - disable pci device's link state, so the link will
610 * never enter specific states
611 */
612void pci_disable_link_state(struct pci_dev *pdev, int state)
613{
614 struct pci_dev *parent = pdev->bus->self;
615 struct pcie_link_state *link_state;
616
617 if (aspm_disabled || !pdev->is_pcie)
618 return;
619 if (pdev->pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
620 pdev->pcie_type == PCI_EXP_TYPE_DOWNSTREAM)
621 parent = pdev;
622 if (!parent)
623 return;
624
625 down_read(&pci_bus_sem);
626 mutex_lock(&aspm_lock);
627 link_state = parent->link_state;
628 link_state->support_state &=
629 ~(state & (PCIE_LINK_STATE_L0S|PCIE_LINK_STATE_L1));
630 if (state & PCIE_LINK_STATE_CLKPM)
631 link_state->clk_pm_capable = 0;
632
633 __pcie_aspm_configure_link_state(parent, link_state->enabled_state);
634 if (!link_state->clk_pm_capable && link_state->clk_pm_enabled)
635 pcie_set_clock_pm(parent, 0);
636 mutex_unlock(&aspm_lock);
637 up_read(&pci_bus_sem);
638}
639EXPORT_SYMBOL(pci_disable_link_state);
640
641static int pcie_aspm_set_policy(const char *val, struct kernel_param *kp)
642{
643 int i;
644 struct pci_dev *pdev;
645 struct pcie_link_state *link_state;
646
647 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
648 if (!strncmp(val, policy_str[i], strlen(policy_str[i])))
649 break;
650 if (i >= ARRAY_SIZE(policy_str))
651 return -EINVAL;
652 if (i == aspm_policy)
653 return 0;
654
655 down_read(&pci_bus_sem);
656 mutex_lock(&aspm_lock);
657 aspm_policy = i;
658 list_for_each_entry(link_state, &link_list, sibiling) {
659 pdev = link_state->pdev;
660 __pcie_aspm_configure_link_state(pdev,
661 policy_to_aspm_state(pdev));
662 if (link_state->clk_pm_capable &&
663 link_state->clk_pm_enabled != policy_to_clkpm_state(pdev))
664 pcie_set_clock_pm(pdev, policy_to_clkpm_state(pdev));
665
666 }
667 mutex_unlock(&aspm_lock);
668 up_read(&pci_bus_sem);
669 return 0;
670}
671
672static int pcie_aspm_get_policy(char *buffer, struct kernel_param *kp)
673{
674 int i, cnt = 0;
675 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
676 if (i == aspm_policy)
677 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
678 else
679 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
680 return cnt;
681}
682
683module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
684 NULL, 0644);
685
686#ifdef CONFIG_PCIEASPM_DEBUG
687static ssize_t link_state_show(struct device *dev,
688 struct device_attribute *attr,
689 char *buf)
690{
691 struct pci_dev *pci_device = to_pci_dev(dev);
692 struct pcie_link_state *link_state = pci_device->link_state;
693
694 return sprintf(buf, "%d\n", link_state->enabled_state);
695}
696
697static ssize_t link_state_store(struct device *dev,
698 struct device_attribute *attr,
699 const char *buf,
700 size_t n)
701{
702 struct pci_dev *pci_device = to_pci_dev(dev);
703 int state;
704
705 if (n < 1)
706 return -EINVAL;
707 state = buf[0]-'0';
708 if (state >= 0 && state <= 3) {
709 /* setup link aspm state */
710 pcie_aspm_configure_link_state(pci_device, state);
711 return n;
712 }
713
714 return -EINVAL;
715}
716
717static ssize_t clk_ctl_show(struct device *dev,
718 struct device_attribute *attr,
719 char *buf)
720{
721 struct pci_dev *pci_device = to_pci_dev(dev);
722 struct pcie_link_state *link_state = pci_device->link_state;
723
724 return sprintf(buf, "%d\n", link_state->clk_pm_enabled);
725}
726
727static ssize_t clk_ctl_store(struct device *dev,
728 struct device_attribute *attr,
729 const char *buf,
730 size_t n)
731{
732 struct pci_dev *pci_device = to_pci_dev(dev);
733 int state;
734
735 if (n < 1)
736 return -EINVAL;
737 state = buf[0]-'0';
738
739 down_read(&pci_bus_sem);
740 mutex_lock(&aspm_lock);
741 pcie_set_clock_pm(pci_device, !!state);
742 mutex_unlock(&aspm_lock);
743 up_read(&pci_bus_sem);
744
745 return n;
746}
747
748static DEVICE_ATTR(link_state, 0644, link_state_show, link_state_store);
749static DEVICE_ATTR(clk_ctl, 0644, clk_ctl_show, clk_ctl_store);
750
751static char power_group[] = "power";
752void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev)
753{
754 struct pcie_link_state *link_state = pdev->link_state;
755
756 if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
757 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
758 return;
759
760 if (link_state->support_state)
761 sysfs_add_file_to_group(&pdev->dev.kobj,
762 &dev_attr_link_state.attr, power_group);
763 if (link_state->clk_pm_capable)
764 sysfs_add_file_to_group(&pdev->dev.kobj,
765 &dev_attr_clk_ctl.attr, power_group);
766}
767
768void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev)
769{
770 struct pcie_link_state *link_state = pdev->link_state;
771
772 if (!pdev->is_pcie || (pdev->pcie_type != PCI_EXP_TYPE_ROOT_PORT &&
773 pdev->pcie_type != PCI_EXP_TYPE_DOWNSTREAM))
774 return;
775
776 if (link_state->support_state)
777 sysfs_remove_file_from_group(&pdev->dev.kobj,
778 &dev_attr_link_state.attr, power_group);
779 if (link_state->clk_pm_capable)
780 sysfs_remove_file_from_group(&pdev->dev.kobj,
781 &dev_attr_clk_ctl.attr, power_group);
782}
783#endif
784
785static int __init pcie_aspm_disable(char *str)
786{
787 aspm_disabled = 1;
788 return 1;
789}
790
791__setup("pcie_noaspm", pcie_aspm_disable);
792
793static int __init pcie_aspm_init(void)
794{
795 if (aspm_disabled)
796 return 0;
797 pci_osc_support_set(OSC_ACTIVE_STATE_PWR_SUPPORT|
798 OSC_CLOCK_PWR_CAPABILITY_SUPPORT);
799 return 0;
800}
801
802fs_initcall(pcie_aspm_init);
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index b20a9b81dae2..23d9eb073296 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -192,9 +192,8 @@ static int get_port_device_capability(struct pci_dev *dev)
192 if (reg32 & SLOT_HP_CAPABLE_MASK) 192 if (reg32 & SLOT_HP_CAPABLE_MASK)
193 services |= PCIE_PORT_SERVICE_HP; 193 services |= PCIE_PORT_SERVICE_HP;
194 } 194 }
195 /* PME Capable */ 195 /* PME Capable - root port capability */
196 pos = pci_find_capability(dev, PCI_CAP_ID_PME); 196 if (((reg16 >> 4) & PORT_TYPE_MASK) == PCIE_RC_PORT)
197 if (pos)
198 services |= PCIE_PORT_SERVICE_PME; 197 services |= PCIE_PORT_SERVICE_PME;
199 198
200 pos = PCI_CFG_SPACE_SIZE; 199 pos = PCI_CFG_SPACE_SIZE;
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 5fd585293e79..8b505bd925aa 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -9,6 +9,7 @@
9#include <linux/slab.h> 9#include <linux/slab.h>
10#include <linux/module.h> 10#include <linux/module.h>
11#include <linux/cpumask.h> 11#include <linux/cpumask.h>
12#include <linux/aspm.h>
12#include "pci.h" 13#include "pci.h"
13 14
14#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 15#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
@@ -53,7 +54,7 @@ static void pci_create_legacy_files(struct pci_bus *b)
53 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR; 54 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
54 b->legacy_io->read = pci_read_legacy_io; 55 b->legacy_io->read = pci_read_legacy_io;
55 b->legacy_io->write = pci_write_legacy_io; 56 b->legacy_io->write = pci_write_legacy_io;
56 class_device_create_bin_file(&b->class_dev, b->legacy_io); 57 device_create_bin_file(&b->dev, b->legacy_io);
57 58
58 /* Allocated above after the legacy_io struct */ 59 /* Allocated above after the legacy_io struct */
59 b->legacy_mem = b->legacy_io + 1; 60 b->legacy_mem = b->legacy_io + 1;
@@ -61,15 +62,15 @@ static void pci_create_legacy_files(struct pci_bus *b)
61 b->legacy_mem->size = 1024*1024; 62 b->legacy_mem->size = 1024*1024;
62 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR; 63 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
63 b->legacy_mem->mmap = pci_mmap_legacy_mem; 64 b->legacy_mem->mmap = pci_mmap_legacy_mem;
64 class_device_create_bin_file(&b->class_dev, b->legacy_mem); 65 device_create_bin_file(&b->dev, b->legacy_mem);
65 } 66 }
66} 67}
67 68
68void pci_remove_legacy_files(struct pci_bus *b) 69void pci_remove_legacy_files(struct pci_bus *b)
69{ 70{
70 if (b->legacy_io) { 71 if (b->legacy_io) {
71 class_device_remove_bin_file(&b->class_dev, b->legacy_io); 72 device_remove_bin_file(&b->dev, b->legacy_io);
72 class_device_remove_bin_file(&b->class_dev, b->legacy_mem); 73 device_remove_bin_file(&b->dev, b->legacy_mem);
73 kfree(b->legacy_io); /* both are allocated here */ 74 kfree(b->legacy_io); /* both are allocated here */
74 } 75 }
75} 76}
@@ -81,26 +82,27 @@ void pci_remove_legacy_files(struct pci_bus *bus) { return; }
81/* 82/*
82 * PCI Bus Class Devices 83 * PCI Bus Class Devices
83 */ 84 */
84static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev, 85static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
86 struct device_attribute *attr,
85 char *buf) 87 char *buf)
86{ 88{
87 int ret; 89 int ret;
88 cpumask_t cpumask; 90 cpumask_t cpumask;
89 91
90 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev)); 92 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
91 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask); 93 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
92 if (ret < PAGE_SIZE) 94 if (ret < PAGE_SIZE)
93 buf[ret++] = '\n'; 95 buf[ret++] = '\n';
94 return ret; 96 return ret;
95} 97}
96CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL); 98DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
97 99
98/* 100/*
99 * PCI Bus Class 101 * PCI Bus Class
100 */ 102 */
101static void release_pcibus_dev(struct class_device *class_dev) 103static void release_pcibus_dev(struct device *dev)
102{ 104{
103 struct pci_bus *pci_bus = to_pci_bus(class_dev); 105 struct pci_bus *pci_bus = to_pci_bus(dev);
104 106
105 if (pci_bus->bridge) 107 if (pci_bus->bridge)
106 put_device(pci_bus->bridge); 108 put_device(pci_bus->bridge);
@@ -109,7 +111,7 @@ static void release_pcibus_dev(struct class_device *class_dev)
109 111
110static struct class pcibus_class = { 112static struct class pcibus_class = {
111 .name = "pci_bus", 113 .name = "pci_bus",
112 .release = &release_pcibus_dev, 114 .dev_release = &release_pcibus_dev,
113}; 115};
114 116
115static int __init pcibus_class_init(void) 117static int __init pcibus_class_init(void)
@@ -392,7 +394,6 @@ pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
392{ 394{
393 struct pci_bus *child; 395 struct pci_bus *child;
394 int i; 396 int i;
395 int retval;
396 397
397 /* 398 /*
398 * Allocate a new bus, and inherit stuff from the parent.. 399 * Allocate a new bus, and inherit stuff from the parent..
@@ -408,15 +409,12 @@ pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
408 child->bus_flags = parent->bus_flags; 409 child->bus_flags = parent->bus_flags;
409 child->bridge = get_device(&bridge->dev); 410 child->bridge = get_device(&bridge->dev);
410 411
411 child->class_dev.class = &pcibus_class; 412 /* initialize some portions of the bus device, but don't register it
412 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr); 413 * now as the parent is not properly set up yet. This device will get
413 retval = class_device_register(&child->class_dev); 414 * registered later in pci_bus_add_devices()
414 if (retval) 415 */
415 goto error_register; 416 child->dev.class = &pcibus_class;
416 retval = class_device_create_file(&child->class_dev, 417 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
417 &class_device_attr_cpuaffinity);
418 if (retval)
419 goto error_file_create;
420 418
421 /* 419 /*
422 * Set up the primary, secondary and subordinate 420 * Set up the primary, secondary and subordinate
@@ -434,12 +432,6 @@ pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
434 bridge->subordinate = child; 432 bridge->subordinate = child;
435 433
436 return child; 434 return child;
437
438error_file_create:
439 class_device_unregister(&child->class_dev);
440error_register:
441 kfree(child);
442 return NULL;
443} 435}
444 436
445struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) 437struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
@@ -471,8 +463,6 @@ static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
471 } 463 }
472} 464}
473 465
474unsigned int pci_scan_child_bus(struct pci_bus *bus);
475
476/* 466/*
477 * If it's a bridge, configure it and scan the bus behind it. 467 * If it's a bridge, configure it and scan the bus behind it.
478 * For CardBus bridges, we don't scan behind as the devices will 468 * For CardBus bridges, we don't scan behind as the devices will
@@ -641,13 +631,13 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass
641 (child->number > bus->subordinate) || 631 (child->number > bus->subordinate) ||
642 (child->number < bus->number) || 632 (child->number < bus->number) ||
643 (child->subordinate < bus->number)) { 633 (child->subordinate < bus->number)) {
644 pr_debug("PCI: Bus #%02x (-#%02x) is %s" 634 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
645 "hidden behind%s bridge #%02x (-#%02x)\n", 635 "hidden behind%s bridge #%02x (-#%02x)\n",
646 child->number, child->subordinate, 636 child->number, child->subordinate,
647 (bus->number > child->subordinate && 637 (bus->number > child->subordinate &&
648 bus->subordinate < child->number) ? 638 bus->subordinate < child->number) ?
649 "wholly " : " partially", 639 "wholly" : "partially",
650 bus->self->transparent ? " transparent" : " ", 640 bus->self->transparent ? " transparent" : "",
651 bus->number, bus->subordinate); 641 bus->number, bus->subordinate);
652 } 642 }
653 bus = bus->parent; 643 bus = bus->parent;
@@ -971,6 +961,7 @@ struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
971 961
972 return dev; 962 return dev;
973} 963}
964EXPORT_SYMBOL(pci_scan_single_device);
974 965
975/** 966/**
976 * pci_scan_slot - scan a PCI slot on a bus for devices. 967 * pci_scan_slot - scan a PCI slot on a bus for devices.
@@ -1011,6 +1002,10 @@ int pci_scan_slot(struct pci_bus *bus, int devfn)
1011 break; 1002 break;
1012 } 1003 }
1013 } 1004 }
1005
1006 if (bus->self)
1007 pcie_aspm_init_link_state(bus->self);
1008
1014 return nr; 1009 return nr;
1015} 1010}
1016 1011
@@ -1103,32 +1098,27 @@ struct pci_bus * pci_create_bus(struct device *parent,
1103 goto dev_reg_err; 1098 goto dev_reg_err;
1104 b->bridge = get_device(dev); 1099 b->bridge = get_device(dev);
1105 1100
1106 b->class_dev.class = &pcibus_class; 1101 b->dev.class = &pcibus_class;
1107 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus); 1102 b->dev.parent = b->bridge;
1108 error = class_device_register(&b->class_dev); 1103 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1104 error = device_register(&b->dev);
1109 if (error) 1105 if (error)
1110 goto class_dev_reg_err; 1106 goto class_dev_reg_err;
1111 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity); 1107 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1112 if (error) 1108 if (error)
1113 goto class_dev_create_file_err; 1109 goto dev_create_file_err;
1114 1110
1115 /* Create legacy_io and legacy_mem files for this bus */ 1111 /* Create legacy_io and legacy_mem files for this bus */
1116 pci_create_legacy_files(b); 1112 pci_create_legacy_files(b);
1117 1113
1118 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1119 if (error)
1120 goto sys_create_link_err;
1121
1122 b->number = b->secondary = bus; 1114 b->number = b->secondary = bus;
1123 b->resource[0] = &ioport_resource; 1115 b->resource[0] = &ioport_resource;
1124 b->resource[1] = &iomem_resource; 1116 b->resource[1] = &iomem_resource;
1125 1117
1126 return b; 1118 return b;
1127 1119
1128sys_create_link_err: 1120dev_create_file_err:
1129 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity); 1121 device_unregister(&b->dev);
1130class_dev_create_file_err:
1131 class_device_unregister(&b->class_dev);
1132class_dev_reg_err: 1122class_dev_reg_err:
1133 device_unregister(dev); 1123 device_unregister(dev);
1134dev_reg_err: 1124dev_reg_err:
@@ -1140,7 +1130,6 @@ err_out:
1140 kfree(b); 1130 kfree(b);
1141 return NULL; 1131 return NULL;
1142} 1132}
1143EXPORT_SYMBOL_GPL(pci_create_bus);
1144 1133
1145struct pci_bus *pci_scan_bus_parented(struct device *parent, 1134struct pci_bus *pci_scan_bus_parented(struct device *parent,
1146 int bus, struct pci_ops *ops, void *sysdata) 1135 int bus, struct pci_ops *ops, void *sysdata)
@@ -1159,7 +1148,6 @@ EXPORT_SYMBOL(pci_add_new_bus);
1159EXPORT_SYMBOL(pci_do_scan_bus); 1148EXPORT_SYMBOL(pci_do_scan_bus);
1160EXPORT_SYMBOL(pci_scan_slot); 1149EXPORT_SYMBOL(pci_scan_slot);
1161EXPORT_SYMBOL(pci_scan_bridge); 1150EXPORT_SYMBOL(pci_scan_bridge);
1162EXPORT_SYMBOL(pci_scan_single_device);
1163EXPORT_SYMBOL_GPL(pci_scan_child_bus); 1151EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1164#endif 1152#endif
1165 1153
diff --git a/drivers/pci/proc.c b/drivers/pci/proc.c
index 716439e25dd2..68aeeb7206de 100644
--- a/drivers/pci/proc.c
+++ b/drivers/pci/proc.c
@@ -11,6 +11,7 @@
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/proc_fs.h> 12#include <linux/proc_fs.h>
13#include <linux/seq_file.h> 13#include <linux/seq_file.h>
14#include <linux/smp_lock.h>
14#include <linux/capability.h> 15#include <linux/capability.h>
15#include <asm/uaccess.h> 16#include <asm/uaccess.h>
16#include <asm/byteorder.h> 17#include <asm/byteorder.h>
@@ -202,15 +203,18 @@ struct pci_filp_private {
202 int write_combine; 203 int write_combine;
203}; 204};
204 205
205static int proc_bus_pci_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg) 206static long proc_bus_pci_ioctl(struct file *file, unsigned int cmd,
207 unsigned long arg)
206{ 208{
207 const struct proc_dir_entry *dp = PDE(inode); 209 const struct proc_dir_entry *dp = PDE(file->f_dentry->d_inode);
208 struct pci_dev *dev = dp->data; 210 struct pci_dev *dev = dp->data;
209#ifdef HAVE_PCI_MMAP 211#ifdef HAVE_PCI_MMAP
210 struct pci_filp_private *fpriv = file->private_data; 212 struct pci_filp_private *fpriv = file->private_data;
211#endif /* HAVE_PCI_MMAP */ 213#endif /* HAVE_PCI_MMAP */
212 int ret = 0; 214 int ret = 0;
213 215
216 lock_kernel();
217
214 switch (cmd) { 218 switch (cmd) {
215 case PCIIOC_CONTROLLER: 219 case PCIIOC_CONTROLLER:
216 ret = pci_domain_nr(dev->bus); 220 ret = pci_domain_nr(dev->bus);
@@ -239,6 +243,7 @@ static int proc_bus_pci_ioctl(struct inode *inode, struct file *file, unsigned i
239 break; 243 break;
240 }; 244 };
241 245
246 unlock_kernel();
242 return ret; 247 return ret;
243} 248}
244 249
@@ -291,7 +296,7 @@ static const struct file_operations proc_bus_pci_operations = {
291 .llseek = proc_bus_pci_lseek, 296 .llseek = proc_bus_pci_lseek,
292 .read = proc_bus_pci_read, 297 .read = proc_bus_pci_read,
293 .write = proc_bus_pci_write, 298 .write = proc_bus_pci_write,
294 .ioctl = proc_bus_pci_ioctl, 299 .unlocked_ioctl = proc_bus_pci_ioctl,
295#ifdef HAVE_PCI_MMAP 300#ifdef HAVE_PCI_MMAP
296 .open = proc_bus_pci_open, 301 .open = proc_bus_pci_open,
297 .release = proc_bus_pci_release, 302 .release = proc_bus_pci_release,
@@ -370,7 +375,7 @@ static int show_device(struct seq_file *m, void *v)
370 return 0; 375 return 0;
371} 376}
372 377
373static struct seq_operations proc_bus_pci_devices_op = { 378static const struct seq_operations proc_bus_pci_devices_op = {
374 .start = pci_seq_start, 379 .start = pci_seq_start,
375 .next = pci_seq_next, 380 .next = pci_seq_next,
376 .stop = pci_seq_stop, 381 .stop = pci_seq_stop,
@@ -480,7 +485,3 @@ static int __init pci_proc_init(void)
480 485
481__initcall(pci_proc_init); 486__initcall(pci_proc_init);
482 487
483#ifdef CONFIG_HOTPLUG
484EXPORT_SYMBOL(pci_proc_detach_bus);
485#endif
486
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 72e0bd5d80ac..0a953d43b9a2 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -21,6 +21,7 @@
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/delay.h> 22#include <linux/delay.h>
23#include <linux/acpi.h> 23#include <linux/acpi.h>
24#include <linux/kallsyms.h>
24#include "pci.h" 25#include "pci.h"
25 26
26/* The Mellanox Tavor device gives false positive parity errors 27/* The Mellanox Tavor device gives false positive parity errors
@@ -46,14 +47,14 @@ static void quirk_passive_release(struct pci_dev *dev)
46 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 47 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
47 pci_read_config_byte(d, 0x82, &dlc); 48 pci_read_config_byte(d, 0x82, &dlc);
48 if (!(dlc & 1<<1)) { 49 if (!(dlc & 1<<1)) {
49 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d)); 50 dev_err(&d->dev, "PIIX3: Enabling Passive Release\n");
50 dlc |= 1<<1; 51 dlc |= 1<<1;
51 pci_write_config_byte(d, 0x82, dlc); 52 pci_write_config_byte(d, 0x82, dlc);
52 } 53 }
53 } 54 }
54} 55}
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 56DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
56DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release ); 57DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
57 58
58/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround 59/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
59 but VIA don't answer queries. If you happen to have good contacts at VIA 60 but VIA don't answer queries. If you happen to have good contacts at VIA
@@ -68,20 +69,20 @@ static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
68{ 69{
69 if (!isa_dma_bridge_buggy) { 70 if (!isa_dma_bridge_buggy) {
70 isa_dma_bridge_buggy=1; 71 isa_dma_bridge_buggy=1;
71 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n"); 72 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
72 } 73 }
73} 74}
74 /* 75 /*
75 * Its not totally clear which chipsets are the problematic ones 76 * Its not totally clear which chipsets are the problematic ones
76 * We know 82C586 and 82C596 variants are affected. 77 * We know 82C586 and 82C596 variants are affected.
77 */ 78 */
78DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs ); 79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
79DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs ); 80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
80DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs ); 81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
81DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs ); 82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
82DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs ); 83DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
83DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs ); 84DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
84DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs ); 85DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
85 86
86int pci_pci_problems; 87int pci_pci_problems;
87EXPORT_SYMBOL(pci_pci_problems); 88EXPORT_SYMBOL(pci_pci_problems);
@@ -92,12 +93,12 @@ EXPORT_SYMBOL(pci_pci_problems);
92static void __devinit quirk_nopcipci(struct pci_dev *dev) 93static void __devinit quirk_nopcipci(struct pci_dev *dev)
93{ 94{
94 if ((pci_pci_problems & PCIPCI_FAIL)==0) { 95 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
95 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n"); 96 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
96 pci_pci_problems |= PCIPCI_FAIL; 97 pci_pci_problems |= PCIPCI_FAIL;
97 } 98 }
98} 99}
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci ); 100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci ); 101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
101 102
102static void __devinit quirk_nopciamd(struct pci_dev *dev) 103static void __devinit quirk_nopciamd(struct pci_dev *dev)
103{ 104{
@@ -105,11 +106,11 @@ static void __devinit quirk_nopciamd(struct pci_dev *dev)
105 pci_read_config_byte(dev, 0x08, &rev); 106 pci_read_config_byte(dev, 0x08, &rev);
106 if (rev == 0x13) { 107 if (rev == 0x13) {
107 /* Erratum 24 */ 108 /* Erratum 24 */
108 printk(KERN_INFO "Chipset erratum: Disabling direct PCI/AGP transfers.\n"); 109 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
109 pci_pci_problems |= PCIAGP_FAIL; 110 pci_pci_problems |= PCIAGP_FAIL;
110 } 111 }
111} 112}
112DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd ); 113DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
113 114
114/* 115/*
115 * Triton requires workarounds to be used by the drivers 116 * Triton requires workarounds to be used by the drivers
@@ -117,14 +118,14 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopci
117static void __devinit quirk_triton(struct pci_dev *dev) 118static void __devinit quirk_triton(struct pci_dev *dev)
118{ 119{
119 if ((pci_pci_problems&PCIPCI_TRITON)==0) { 120 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
120 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 121 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
121 pci_pci_problems |= PCIPCI_TRITON; 122 pci_pci_problems |= PCIPCI_TRITON;
122 } 123 }
123} 124}
124DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton ); 125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
125DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton ); 126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton ); 127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton ); 128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
128 129
129/* 130/*
130 * VIA Apollo KT133 needs PCI latency patch 131 * VIA Apollo KT133 needs PCI latency patch
@@ -139,25 +140,22 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quir
139static void quirk_vialatency(struct pci_dev *dev) 140static void quirk_vialatency(struct pci_dev *dev)
140{ 141{
141 struct pci_dev *p; 142 struct pci_dev *p;
142 u8 rev;
143 u8 busarb; 143 u8 busarb;
144 /* Ok we have a potential problem chipset here. Now see if we have 144 /* Ok we have a potential problem chipset here. Now see if we have
145 a buggy southbridge */ 145 a buggy southbridge */
146 146
147 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 147 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
148 if (p!=NULL) { 148 if (p!=NULL) {
149 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
150 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */ 149 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
151 /* Check for buggy part revisions */ 150 /* Check for buggy part revisions */
152 if (rev < 0x40 || rev > 0x42) 151 if (p->revision < 0x40 || p->revision > 0x42)
153 goto exit; 152 goto exit;
154 } else { 153 } else {
155 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 154 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
156 if (p==NULL) /* No problem parts */ 155 if (p==NULL) /* No problem parts */
157 goto exit; 156 goto exit;
158 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
159 /* Check for buggy part revisions */ 157 /* Check for buggy part revisions */
160 if (rev < 0x10 || rev > 0x12) 158 if (p->revision < 0x10 || p->revision > 0x12)
161 goto exit; 159 goto exit;
162 } 160 }
163 161
@@ -180,17 +178,17 @@ static void quirk_vialatency(struct pci_dev *dev)
180 busarb &= ~(1<<5); 178 busarb &= ~(1<<5);
181 busarb |= (1<<4); 179 busarb |= (1<<4);
182 pci_write_config_byte(dev, 0x76, busarb); 180 pci_write_config_byte(dev, 0x76, busarb);
183 printk(KERN_INFO "Applying VIA southbridge workaround.\n"); 181 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
184exit: 182exit:
185 pci_dev_put(p); 183 pci_dev_put(p);
186} 184}
187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 185DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
188DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 186DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
189DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 187DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
190/* Must restore this on a resume from RAM */ 188/* Must restore this on a resume from RAM */
191DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency ); 189DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
192DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency ); 190DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
193DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency ); 191DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
194 192
195/* 193/*
196 * VIA Apollo VP3 needs ETBF on BT848/878 194 * VIA Apollo VP3 needs ETBF on BT848/878
@@ -198,20 +196,20 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_viala
198static void __devinit quirk_viaetbf(struct pci_dev *dev) 196static void __devinit quirk_viaetbf(struct pci_dev *dev)
199{ 197{
200 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) { 198 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
201 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 199 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
202 pci_pci_problems |= PCIPCI_VIAETBF; 200 pci_pci_problems |= PCIPCI_VIAETBF;
203 } 201 }
204} 202}
205DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf ); 203DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
206 204
207static void __devinit quirk_vsfx(struct pci_dev *dev) 205static void __devinit quirk_vsfx(struct pci_dev *dev)
208{ 206{
209 if ((pci_pci_problems&PCIPCI_VSFX)==0) { 207 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
210 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 208 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
211 pci_pci_problems |= PCIPCI_VSFX; 209 pci_pci_problems |= PCIPCI_VSFX;
212 } 210 }
213} 211}
214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx ); 212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
215 213
216/* 214/*
217 * Ali Magik requires workarounds to be used by the drivers 215 * Ali Magik requires workarounds to be used by the drivers
@@ -222,12 +220,12 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx
222static void __init quirk_alimagik(struct pci_dev *dev) 220static void __init quirk_alimagik(struct pci_dev *dev)
223{ 221{
224 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) { 222 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
225 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 223 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
226 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 224 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
227 } 225 }
228} 226}
229DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik ); 227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
230DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik ); 228DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
231 229
232/* 230/*
233 * Natoma has some interesting boundary conditions with Zoran stuff 231 * Natoma has some interesting boundary conditions with Zoran stuff
@@ -236,16 +234,16 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimag
236static void __devinit quirk_natoma(struct pci_dev *dev) 234static void __devinit quirk_natoma(struct pci_dev *dev)
237{ 235{
238 if ((pci_pci_problems&PCIPCI_NATOMA)==0) { 236 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
239 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n"); 237 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
240 pci_pci_problems |= PCIPCI_NATOMA; 238 pci_pci_problems |= PCIPCI_NATOMA;
241 } 239 }
242} 240}
243DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma ); 241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma ); 242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma ); 243DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma ); 244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
247DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma ); 245DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma ); 246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
249 247
250/* 248/*
251 * This chip can cause PCI parity errors if config register 0xA0 is read 249 * This chip can cause PCI parity errors if config register 0xA0 is read
@@ -255,7 +253,7 @@ static void __devinit quirk_citrine(struct pci_dev *dev)
255{ 253{
256 dev->cfg_size = 0xA0; 254 dev->cfg_size = 0xA0;
257} 255}
258DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine ); 256DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
259 257
260/* 258/*
261 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 259 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
@@ -270,8 +268,8 @@ static void __devinit quirk_s3_64M(struct pci_dev *dev)
270 r->end = 0x3ffffff; 268 r->end = 0x3ffffff;
271 } 269 }
272} 270}
273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M ); 271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
274DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M ); 272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
275 273
276static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, 274static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
277 unsigned size, int nr, const char *name) 275 unsigned size, int nr, const char *name)
@@ -292,7 +290,7 @@ static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
292 pcibios_bus_to_resource(dev, res, &bus_region); 290 pcibios_bus_to_resource(dev, res, &bus_region);
293 291
294 pci_claim_resource(dev, nr); 292 pci_claim_resource(dev, nr);
295 printk("PCI quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name); 293 dev_info(&dev->dev, "quirk: region %04x-%04x claimed by %s\n", region, region + size - 1, name);
296 } 294 }
297} 295}
298 296
@@ -302,12 +300,12 @@ static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
302 */ 300 */
303static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev) 301static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
304{ 302{
305 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n"); 303 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
306 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 304 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
307 request_region(0x3b0, 0x0C, "RadeonIGP"); 305 request_region(0x3b0, 0x0C, "RadeonIGP");
308 request_region(0x3d3, 0x01, "RadeonIGP"); 306 request_region(0x3d3, 0x01, "RadeonIGP");
309} 307}
310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce ); 308DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
311 309
312/* 310/*
313 * Let's make the southbridge information explicit instead 311 * Let's make the southbridge information explicit instead
@@ -329,7 +327,7 @@ static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
329 pci_read_config_word(dev, 0xE2, &region); 327 pci_read_config_word(dev, 0xE2, &region);
330 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 328 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
331} 329}
332DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi ); 330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
333 331
334static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 332static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
335{ 333{
@@ -354,7 +352,7 @@ static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int p
354 * let's get enough confirmation reports first. 352 * let's get enough confirmation reports first.
355 */ 353 */
356 base &= -size; 354 base &= -size;
357 printk("%s PIO at %04x-%04x\n", name, base, base + size - 1); 355 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
358} 356}
359 357
360static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 358static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
@@ -379,7 +377,7 @@ static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int
379 * reserve it, but let's get enough confirmation reports first. 377 * reserve it, but let's get enough confirmation reports first.
380 */ 378 */
381 base &= -size; 379 base &= -size;
382 printk("%s MMIO at %04x-%04x\n", name, base, base + size - 1); 380 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
383} 381}
384 382
385/* 383/*
@@ -418,8 +416,8 @@ static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
418 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 416 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
419 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 417 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
420} 418}
421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi ); 419DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
422DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi ); 420DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
423 421
424/* 422/*
425 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 423 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
@@ -436,16 +434,16 @@ static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
436 pci_read_config_dword(dev, 0x58, &region); 434 pci_read_config_dword(dev, 0x58, &region);
437 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO"); 435 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH4 GPIO");
438} 436}
439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi ); 437DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi ); 438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi ); 439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi ); 440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi ); 441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi ); 442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi ); 443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi ); 444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi ); 445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
448DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi ); 446DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
449 447
450static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev) 448static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
451{ 449{
@@ -457,20 +455,20 @@ static void __devinit quirk_ich6_lpc_acpi(struct pci_dev *dev)
457 pci_read_config_dword(dev, 0x48, &region); 455 pci_read_config_dword(dev, 0x48, &region);
458 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO"); 456 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1, "ICH6 GPIO");
459} 457}
460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi ); 458DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc_acpi);
461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi ); 459DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc_acpi);
462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi ); 460DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich6_lpc_acpi);
463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi ); 461DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich6_lpc_acpi);
464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi ); 462DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich6_lpc_acpi);
465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi ); 463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich6_lpc_acpi);
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi ); 464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich6_lpc_acpi);
467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi ); 465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich6_lpc_acpi);
468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi ); 466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich6_lpc_acpi);
469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi ); 467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich6_lpc_acpi);
470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi ); 468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich6_lpc_acpi);
471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi ); 469DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich6_lpc_acpi);
472DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi ); 470DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich6_lpc_acpi);
473DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi ); 471DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich6_lpc_acpi);
474 472
475/* 473/*
476 * VIA ACPI: One IO region pointed to by longword at 474 * VIA ACPI: One IO region pointed to by longword at
@@ -486,7 +484,7 @@ static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
486 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI"); 484 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
487 } 485 }
488} 486}
489DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi ); 487DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
490 488
491/* 489/*
492 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 490 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
@@ -509,7 +507,7 @@ static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
509 smb &= PCI_BASE_ADDRESS_IO_MASK; 507 smb &= PCI_BASE_ADDRESS_IO_MASK;
510 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB"); 508 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
511} 509}
512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi ); 510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
513 511
514/* 512/*
515 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 513 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
@@ -551,14 +549,14 @@ static void quirk_via_ioapic(struct pci_dev *dev)
551 else 549 else
552 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 550 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
553 551
554 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n", 552 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
555 tmp == 0 ? "Disa" : "Ena"); 553 tmp == 0 ? "Disa" : "Ena");
556 554
557 /* Offset 0x58: External APIC IRQ output control */ 555 /* Offset 0x58: External APIC IRQ output control */
558 pci_write_config_byte (dev, 0x58, tmp); 556 pci_write_config_byte (dev, 0x58, tmp);
559} 557}
560DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 558DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
561DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic ); 559DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
562 560
563/* 561/*
564 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit. 562 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
@@ -573,7 +571,7 @@ static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
573 571
574 pci_read_config_byte(dev, 0x5B, &misc_control2); 572 pci_read_config_byte(dev, 0x5B, &misc_control2);
575 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 573 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
576 printk(KERN_INFO "PCI: Bypassing VIA 8237 APIC De-Assert Message\n"); 574 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
577 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 575 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
578 } 576 }
579} 577}
@@ -592,18 +590,18 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_v
592static void __devinit quirk_amd_ioapic(struct pci_dev *dev) 590static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
593{ 591{
594 if (dev->revision >= 0x02) { 592 if (dev->revision >= 0x02) {
595 printk(KERN_WARNING "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 593 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
596 printk(KERN_WARNING " : booting with the \"noapic\" option.\n"); 594 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
597 } 595 }
598} 596}
599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic ); 597DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
600 598
601static void __init quirk_ioapic_rmw(struct pci_dev *dev) 599static void __init quirk_ioapic_rmw(struct pci_dev *dev)
602{ 600{
603 if (dev->devfn == 0 && dev->bus->number == 0) 601 if (dev->devfn == 0 && dev->bus->number == 0)
604 sis_apic_bug = 1; 602 sis_apic_bug = 1;
605} 603}
606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw ); 604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
607 605
608#define AMD8131_revA0 0x01 606#define AMD8131_revA0 0x01
609#define AMD8131_revB0 0x11 607#define AMD8131_revB0 0x11
@@ -617,7 +615,7 @@ static void quirk_amd_8131_ioapic(struct pci_dev *dev)
617 return; 615 return;
618 616
619 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) { 617 if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {
620 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n"); 618 dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n");
621 pci_read_config_byte( dev, AMD8131_MISC, &tmp); 619 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
622 tmp &= ~(1 << AMD8131_NIOAMODE_BIT); 620 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
623 pci_write_config_byte( dev, AMD8131_MISC, tmp); 621 pci_write_config_byte( dev, AMD8131_MISC, tmp);
@@ -634,8 +632,8 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk
634static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev) 632static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
635{ 633{
636 if (dev->subordinate && dev->revision <= 0x12) { 634 if (dev->subordinate && dev->revision <= 0x12) {
637 printk(KERN_INFO "AMD8131 rev %x detected, disabling PCI-X " 635 dev_info(&dev->dev, "AMD8131 rev %x detected; "
638 "MMRBC\n", dev->revision); 636 "disabling PCI-X MMRBC\n", dev->revision);
639 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 637 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
640 } 638 }
641} 639}
@@ -660,8 +658,8 @@ static void __devinit quirk_via_acpi(struct pci_dev *d)
660 if (irq && (irq != 2)) 658 if (irq && (irq != 2))
661 d->irq = irq; 659 d->irq = irq;
662} 660}
663DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi ); 661DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
664DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi ); 662DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
665 663
666 664
667/* 665/*
@@ -742,8 +740,8 @@ static void quirk_via_vlink(struct pci_dev *dev)
742 740
743 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 741 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
744 if (new_irq != irq) { 742 if (new_irq != irq) {
745 printk(KERN_INFO "PCI: VIA VLink IRQ fixup for %s, from %d to %d\n", 743 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
746 pci_name(dev), irq, new_irq); 744 irq, new_irq);
747 udelay(15); /* unknown if delay really needed */ 745 udelay(15); /* unknown if delay really needed */
748 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 746 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
749 } 747 }
@@ -761,7 +759,7 @@ static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
761 pci_write_config_byte(dev, 0xfc, 0); 759 pci_write_config_byte(dev, 0xfc, 0);
762 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 760 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
763} 761}
764DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id ); 762DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
765 763
766/* 764/*
767 * CardBus controllers have a legacy base address that enables them 765 * CardBus controllers have a legacy base address that enables them
@@ -791,15 +789,15 @@ static void quirk_amd_ordering(struct pci_dev *dev)
791 pci_read_config_dword(dev, 0x4C, &pcic); 789 pci_read_config_dword(dev, 0x4C, &pcic);
792 if ((pcic&6)!=6) { 790 if ((pcic&6)!=6) {
793 pcic |= 6; 791 pcic |= 6;
794 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n"); 792 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
795 pci_write_config_dword(dev, 0x4C, pcic); 793 pci_write_config_dword(dev, 0x4C, pcic);
796 pci_read_config_dword(dev, 0x84, &pcic); 794 pci_read_config_dword(dev, 0x84, &pcic);
797 pcic |= (1<<23); /* Required in this mode */ 795 pcic |= (1<<23); /* Required in this mode */
798 pci_write_config_dword(dev, 0x84, pcic); 796 pci_write_config_dword(dev, 0x84, pcic);
799 } 797 }
800} 798}
801DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 799DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
802DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering ); 800DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
803 801
804/* 802/*
805 * DreamWorks provided workaround for Dunord I-3000 problem 803 * DreamWorks provided workaround for Dunord I-3000 problem
@@ -814,7 +812,7 @@ static void __devinit quirk_dunord ( struct pci_dev * dev )
814 r->start = 0; 812 r->start = 0;
815 r->end = 0xffffff; 813 r->end = 0xffffff;
816} 814}
817DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord ); 815DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
818 816
819/* 817/*
820 * i82380FB mobile docking controller: its PCI-to-PCI bridge 818 * i82380FB mobile docking controller: its PCI-to-PCI bridge
@@ -826,8 +824,8 @@ static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
826{ 824{
827 dev->transparent = 1; 825 dev->transparent = 1;
828} 826}
829DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge ); 827DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
830DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge ); 828DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
831 829
832/* 830/*
833 * Common misconfiguration of the MediaGX/Geode PCI master that will 831 * Common misconfiguration of the MediaGX/Geode PCI master that will
@@ -841,12 +839,12 @@ static void quirk_mediagx_master(struct pci_dev *dev)
841 pci_read_config_byte(dev, 0x41, &reg); 839 pci_read_config_byte(dev, 0x41, &reg);
842 if (reg & 2) { 840 if (reg & 2) {
843 reg &= ~2; 841 reg &= ~2;
844 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg); 842 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
845 pci_write_config_byte(dev, 0x41, reg); 843 pci_write_config_byte(dev, 0x41, reg);
846 } 844 }
847} 845}
848DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 846DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
849DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master ); 847DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
850 848
851/* 849/*
852 * Ensure C0 rev restreaming is off. This is normally done by 850 * Ensure C0 rev restreaming is off. This is normally done by
@@ -863,11 +861,11 @@ static void quirk_disable_pxb(struct pci_dev *pdev)
863 if (config & (1<<6)) { 861 if (config & (1<<6)) {
864 config &= ~(1<<6); 862 config &= ~(1<<6);
865 pci_write_config_word(pdev, 0x40, config); 863 pci_write_config_word(pdev, 0x40, config);
866 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n"); 864 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
867 } 865 }
868} 866}
869DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 867DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
870DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb ); 868DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
871 869
872 870
873static void __devinit quirk_sb600_sata(struct pci_dev *pdev) 871static void __devinit quirk_sb600_sata(struct pci_dev *pdev)
@@ -902,7 +900,7 @@ static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
902 /* PCI layer will sort out resources */ 900 /* PCI layer will sort out resources */
903 } 901 }
904} 902}
905DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide ); 903DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
906 904
907/* 905/*
908 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same 906 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
@@ -914,7 +912,7 @@ static void __init quirk_ide_samemode(struct pci_dev *pdev)
914 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 912 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
915 913
916 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 914 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
917 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n"); 915 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
918 prog &= ~5; 916 prog &= ~5;
919 pdev->class &= ~5; 917 pdev->class &= ~5;
920 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 918 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
@@ -929,7 +927,7 @@ static void __init quirk_eisa_bridge(struct pci_dev *dev)
929{ 927{
930 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 928 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
931} 929}
932DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge ); 930DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
933 931
934 932
935/* 933/*
@@ -1022,6 +1020,11 @@ static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1022 case 0x12bd: /* HP D530 */ 1020 case 0x12bd: /* HP D530 */
1023 asus_hides_smbus = 1; 1021 asus_hides_smbus = 1;
1024 } 1022 }
1023 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1024 switch (dev->subsystem_device) {
1025 case 0x12bf: /* HP xw4100 */
1026 asus_hides_smbus = 1;
1027 }
1025 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1028 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1026 switch (dev->subsystem_device) { 1029 switch (dev->subsystem_device) {
1027 case 0x099c: /* HP Compaq nx6110 */ 1030 case 0x099c: /* HP Compaq nx6110 */
@@ -1049,17 +1052,18 @@ static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1049 } 1052 }
1050 } 1053 }
1051} 1054}
1052DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge ); 1055DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1053DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge ); 1056DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1054DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge ); 1057DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1055DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge ); 1058DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1056DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge ); 1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1057DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge ); 1060DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1058DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge ); 1061DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1059DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge ); 1062DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1060DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge ); 1063DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1064DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1061 1065
1062DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge ); 1066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1063 1067
1064static void asus_hides_smbus_lpc(struct pci_dev *dev) 1068static void asus_hides_smbus_lpc(struct pci_dev *dev)
1065{ 1069{
@@ -1073,25 +1077,25 @@ static void asus_hides_smbus_lpc(struct pci_dev *dev)
1073 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1077 pci_write_config_word(dev, 0xF2, val & (~0x8));
1074 pci_read_config_word(dev, 0xF2, &val); 1078 pci_read_config_word(dev, 0xF2, &val);
1075 if (val & 0x8) 1079 if (val & 0x8)
1076 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val); 1080 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
1077 else 1081 else
1078 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n"); 1082 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
1079 } 1083 }
1080} 1084}
1081DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc ); 1085DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1082DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 1086DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1083DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 1087DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1084DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); 1088DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1085DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 1089DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1086DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 1090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1087DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 1091DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1088DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc ); 1092DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1089DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc ); 1093DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1090DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc ); 1094DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1091DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc ); 1095DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1092DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc ); 1096DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1093DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc ); 1097DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1094DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc ); 1098DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1095 1099
1096static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1100static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1097{ 1101{
@@ -1106,10 +1110,10 @@ static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1106 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */ 1110 val=readl(base + 0x3418); /* read the Function Disable register, dword mode only */
1107 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */ 1111 writel(val & 0xFFFFFFF7, base + 0x3418); /* enable the SMBus device */
1108 iounmap(base); 1112 iounmap(base);
1109 printk(KERN_INFO "PCI: Enabled ICH6/i801 SMBus device\n"); 1113 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
1110} 1114}
1111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); 1115DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1112DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6 ); 1116DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1113 1117
1114/* 1118/*
1115 * SiS 96x south bridge: BIOS typically hides SMBus device... 1119 * SiS 96x south bridge: BIOS typically hides SMBus device...
@@ -1119,18 +1123,18 @@ static void quirk_sis_96x_smbus(struct pci_dev *dev)
1119 u8 val = 0; 1123 u8 val = 0;
1120 pci_read_config_byte(dev, 0x77, &val); 1124 pci_read_config_byte(dev, 0x77, &val);
1121 if (val & 0x10) { 1125 if (val & 0x10) {
1122 printk(KERN_INFO "Enabling SiS 96x SMBus.\n"); 1126 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
1123 pci_write_config_byte(dev, 0x77, val & ~0x10); 1127 pci_write_config_byte(dev, 0x77, val & ~0x10);
1124 } 1128 }
1125} 1129}
1126DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1130DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1127DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1131DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1128DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1132DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1129DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1133DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1130DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus ); 1134DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1131DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus ); 1135DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1132DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus ); 1136DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1133DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus ); 1137DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1134 1138
1135/* 1139/*
1136 * ... This is further complicated by the fact that some SiS96x south 1140 * ... This is further complicated by the fact that some SiS96x south
@@ -1163,8 +1167,8 @@ static void quirk_sis_503(struct pci_dev *dev)
1163 dev->device = devid; 1167 dev->device = devid;
1164 quirk_sis_96x_smbus(dev); 1168 quirk_sis_96x_smbus(dev);
1165} 1169}
1166DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1170DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1167DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 ); 1171DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1168 1172
1169 1173
1170/* 1174/*
@@ -1191,13 +1195,13 @@ static void asus_hides_ac97_lpc(struct pci_dev *dev)
1191 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1195 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1192 pci_read_config_byte(dev, 0x50, &val); 1196 pci_read_config_byte(dev, 0x50, &val);
1193 if (val & 0xc0) 1197 if (val & 0xc0)
1194 printk(KERN_INFO "PCI: onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val); 1198 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
1195 else 1199 else
1196 printk(KERN_INFO "PCI: enabled onboard AC97/MC97 devices\n"); 1200 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
1197 } 1201 }
1198} 1202}
1199DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); 1203DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1200DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc ); 1204DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1201 1205
1202#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1206#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1203 1207
@@ -1292,7 +1296,7 @@ static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1292 } 1296 }
1293 1297
1294} 1298}
1295DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic ); 1299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1296#endif 1300#endif
1297 1301
1298int pcie_mch_quirk; 1302int pcie_mch_quirk;
@@ -1302,9 +1306,9 @@ static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1302{ 1306{
1303 pcie_mch_quirk = 1; 1307 pcie_mch_quirk = 1;
1304} 1308}
1305DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch ); 1309DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1306DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch ); 1310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1307DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch ); 1311DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1308 1312
1309 1313
1310/* 1314/*
@@ -1314,11 +1318,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quir
1314static void __devinit quirk_pcie_pxh(struct pci_dev *dev) 1318static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1315{ 1319{
1316 pci_msi_off(dev); 1320 pci_msi_off(dev);
1317
1318 dev->no_msi = 1; 1321 dev->no_msi = 1;
1319 1322 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
1320 printk(KERN_WARNING "PCI: PXH quirk detected, "
1321 "disabling MSI for SHPC device\n");
1322} 1323}
1323DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 1324DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1324DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 1325DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
@@ -1399,7 +1400,7 @@ static void __devinit quirk_netmos(struct pci_dev *dev)
1399 case PCI_DEVICE_ID_NETMOS_9855: 1400 case PCI_DEVICE_ID_NETMOS_9855:
1400 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL && 1401 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1401 num_parallel) { 1402 num_parallel) {
1402 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, " 1403 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
1403 "%u serial); changing class SERIAL to OTHER " 1404 "%u serial); changing class SERIAL to OTHER "
1404 "(use parport_serial)\n", 1405 "(use parport_serial)\n",
1405 dev->device, num_parallel, num_serial); 1406 dev->device, num_parallel, num_serial);
@@ -1412,9 +1413,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1412 1413
1413static void __devinit quirk_e100_interrupt(struct pci_dev *dev) 1414static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1414{ 1415{
1415 u16 command; 1416 u16 command, pmcsr;
1416 u8 __iomem *csr; 1417 u8 __iomem *csr;
1417 u8 cmd_hi; 1418 u8 cmd_hi;
1419 int pm;
1418 1420
1419 switch (dev->device) { 1421 switch (dev->device) {
1420 /* PCI IDs taken from drivers/net/e100.c */ 1422 /* PCI IDs taken from drivers/net/e100.c */
@@ -1448,18 +1450,28 @@ static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1448 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 1450 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
1449 return; 1451 return;
1450 1452
1453 /*
1454 * Check that the device is in the D0 power state. If it's not,
1455 * there is no point to look any further.
1456 */
1457 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1458 if (pm) {
1459 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1460 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1461 return;
1462 }
1463
1451 /* Convert from PCI bus to resource space. */ 1464 /* Convert from PCI bus to resource space. */
1452 csr = ioremap(pci_resource_start(dev, 0), 8); 1465 csr = ioremap(pci_resource_start(dev, 0), 8);
1453 if (!csr) { 1466 if (!csr) {
1454 printk(KERN_WARNING "PCI: Can't map %s e100 registers\n", 1467 dev_warn(&dev->dev, "Can't map e100 registers\n");
1455 pci_name(dev));
1456 return; 1468 return;
1457 } 1469 }
1458 1470
1459 cmd_hi = readb(csr + 3); 1471 cmd_hi = readb(csr + 3);
1460 if (cmd_hi == 0) { 1472 if (cmd_hi == 0) {
1461 printk(KERN_WARNING "PCI: Firmware left %s e100 interrupts " 1473 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1462 "enabled, disabling\n", pci_name(dev)); 1474 "disabling\n");
1463 writeb(1, csr + 3); 1475 writeb(1, csr + 3);
1464 } 1476 }
1465 1477
@@ -1474,7 +1486,7 @@ static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1474 */ 1486 */
1475 1487
1476 if (dev->class == PCI_CLASS_NOT_DEFINED) { 1488 if (dev->class == PCI_CLASS_NOT_DEFINED) {
1477 printk(KERN_INFO "NCR 53c810 rev 1 detected, setting PCI class.\n"); 1489 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
1478 dev->class = PCI_CLASS_STORAGE_SCSI; 1490 dev->class = PCI_CLASS_STORAGE_SCSI;
1479 } 1491 }
1480} 1492}
@@ -1485,7 +1497,11 @@ static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_f
1485 while (f < end) { 1497 while (f < end) {
1486 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) && 1498 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1487 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) { 1499 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1488 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev)); 1500#ifdef DEBUG
1501 dev_dbg(&dev->dev, "calling quirk 0x%p", f->hook);
1502 print_fn_descriptor_symbol(": %s()\n",
1503 (unsigned long) f->hook);
1504#endif
1489 f->hook(dev); 1505 f->hook(dev);
1490 } 1506 }
1491 f++; 1507 f++;
@@ -1553,7 +1569,7 @@ static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1553 pci_read_config_word(dev, 0x40, &en1k); 1569 pci_read_config_word(dev, 0x40, &en1k);
1554 1570
1555 if (en1k & 0x200) { 1571 if (en1k & 0x200) {
1556 printk(KERN_INFO "PCI: Enable I/O Space to 1 KB Granularity\n"); 1572 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
1557 1573
1558 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 1574 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
1559 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 1575 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
@@ -1585,7 +1601,7 @@ static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
1585 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00); 1601 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
1586 1602
1587 if (iobl_adr != iobl_adr_1k) { 1603 if (iobl_adr != iobl_adr_1k) {
1588 printk(KERN_INFO "PCI: Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1 KB Granularity\n", 1604 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
1589 iobl_adr,iobl_adr_1k); 1605 iobl_adr,iobl_adr_1k);
1590 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k); 1606 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
1591 } 1607 }
@@ -1603,9 +1619,8 @@ static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
1603 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 1619 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
1604 if (!(b & 0x20)) { 1620 if (!(b & 0x20)) {
1605 pci_write_config_byte(dev, 0xf41, b | 0x20); 1621 pci_write_config_byte(dev, 0xf41, b | 0x20);
1606 printk(KERN_INFO 1622 dev_info(&dev->dev,
1607 "PCI: Linking AER extended capability on %s\n", 1623 "Linking AER extended capability\n");
1608 pci_name(dev));
1609 } 1624 }
1610 } 1625 }
1611} 1626}
@@ -1614,6 +1629,34 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1614DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 1629DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1615 quirk_nvidia_ck804_pcie_aer_ext_cap); 1630 quirk_nvidia_ck804_pcie_aer_ext_cap);
1616 1631
1632static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
1633{
1634 /*
1635 * Disable PCI Bus Parking and PCI Master read caching on CX700
1636 * which causes unspecified timing errors with a VT6212L on the PCI
1637 * bus leading to USB2.0 packet loss. The defaults are that these
1638 * features are turned off but some BIOSes turn them on.
1639 */
1640
1641 uint8_t b;
1642 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
1643 if (b & 0x40) {
1644 /* Turn off PCI Bus Parking */
1645 pci_write_config_byte(dev, 0x76, b ^ 0x40);
1646
1647 /* Turn off PCI Master read caching */
1648 pci_write_config_byte(dev, 0x72, 0x0);
1649 pci_write_config_byte(dev, 0x75, 0x1);
1650 pci_write_config_byte(dev, 0x77, 0x0);
1651
1652 printk(KERN_INFO
1653 "PCI: VIA CX700 PCI parking/caching fixup on %s\n",
1654 pci_name(dev));
1655 }
1656 }
1657}
1658DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
1659
1617#ifdef CONFIG_PCI_MSI 1660#ifdef CONFIG_PCI_MSI
1618/* Some chipsets do not support MSI. We cannot easily rely on setting 1661/* Some chipsets do not support MSI. We cannot easily rely on setting
1619 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually 1662 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
@@ -1624,7 +1667,7 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
1624static void __init quirk_disable_all_msi(struct pci_dev *dev) 1667static void __init quirk_disable_all_msi(struct pci_dev *dev)
1625{ 1668{
1626 pci_no_msi(); 1669 pci_no_msi();
1627 printk(KERN_WARNING "PCI: MSI quirk detected. MSI deactivated.\n"); 1670 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
1628} 1671}
1629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
1630DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
@@ -1635,9 +1678,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disab
1635static void __devinit quirk_disable_msi(struct pci_dev *dev) 1678static void __devinit quirk_disable_msi(struct pci_dev *dev)
1636{ 1679{
1637 if (dev->subordinate) { 1680 if (dev->subordinate) {
1638 printk(KERN_WARNING "PCI: MSI quirk detected. " 1681 dev_warn(&dev->dev, "MSI quirk detected; "
1639 "PCI_BUS_FLAGS_NO_MSI set for %s subordinate bus.\n", 1682 "subordinate MSI disabled\n");
1640 pci_name(dev));
1641 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1683 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1642 } 1684 }
1643} 1685}
@@ -1656,9 +1698,9 @@ static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1656 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 1698 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
1657 &flags) == 0) 1699 &flags) == 0)
1658 { 1700 {
1659 printk(KERN_INFO "PCI: Found %s HT MSI Mapping on %s\n", 1701 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
1660 flags & HT_MSI_FLAGS_ENABLE ? 1702 flags & HT_MSI_FLAGS_ENABLE ?
1661 "enabled" : "disabled", pci_name(dev)); 1703 "enabled" : "disabled");
1662 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 1704 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
1663 } 1705 }
1664 1706
@@ -1672,17 +1714,40 @@ static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
1672static void __devinit quirk_msi_ht_cap(struct pci_dev *dev) 1714static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
1673{ 1715{
1674 if (dev->subordinate && !msi_ht_cap_enabled(dev)) { 1716 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
1675 printk(KERN_WARNING "PCI: MSI quirk detected. " 1717 dev_warn(&dev->dev, "MSI quirk detected; "
1676 "MSI disabled on chipset %s.\n", 1718 "subordinate MSI disabled\n");
1677 pci_name(dev));
1678 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1719 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1679 } 1720 }
1680} 1721}
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 1722DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
1682 quirk_msi_ht_cap); 1723 quirk_msi_ht_cap);
1683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, 1724
1684 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 1725
1685 quirk_msi_ht_cap); 1726/*
1727 * Force enable MSI mapping capability on HT bridges
1728 */
1729static void __devinit quirk_msi_ht_cap_enable(struct pci_dev *dev)
1730{
1731 int pos, ttl = 48;
1732
1733 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
1734 while (pos && ttl--) {
1735 u8 flags;
1736
1737 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, &flags) == 0) {
1738 printk(KERN_INFO "PCI: Enabling HT MSI Mapping on %s\n",
1739 pci_name(dev));
1740
1741 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
1742 flags | HT_MSI_FLAGS_ENABLE);
1743 }
1744 pos = pci_find_next_ht_capability(dev, pos,
1745 HT_CAPTYPE_MSI_MAPPING);
1746 }
1747}
1748DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
1749 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
1750 quirk_msi_ht_cap_enable);
1686 1751
1687/* The nVidia CK804 chipset may have 2 HT MSI mappings. 1752/* The nVidia CK804 chipset may have 2 HT MSI mappings.
1688 * MSI are supported if the MSI capability set in any of these mappings. 1753 * MSI are supported if the MSI capability set in any of these mappings.
@@ -1701,9 +1766,8 @@ static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
1701 if (!pdev) 1766 if (!pdev)
1702 return; 1767 return;
1703 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) { 1768 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
1704 printk(KERN_WARNING "PCI: MSI quirk detected. " 1769 dev_warn(&dev->dev, "MSI quirk detected; "
1705 "MSI disabled on chipset %s.\n", 1770 "subordinate MSI disabled\n");
1706 pci_name(dev));
1707 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1771 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
1708 } 1772 }
1709 pci_dev_put(pdev); 1773 pci_dev_put(pdev);
@@ -1715,6 +1779,23 @@ static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
1715{ 1779{
1716 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 1780 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1717} 1781}
1782static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
1783{
1784 struct pci_dev *p;
1785
1786 /* SB700 MSI issue will be fixed at HW level from revision A21,
1787 * we need check PCI REVISION ID of SMBus controller to get SB700
1788 * revision.
1789 */
1790 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
1791 NULL);
1792 if (!p)
1793 return;
1794
1795 if ((p->revision < 0x3B) && (p->revision >= 0x30))
1796 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
1797 pci_dev_put(p);
1798}
1718DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 1799DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1719 PCI_DEVICE_ID_TIGON3_5780, 1800 PCI_DEVICE_ID_TIGON3_5780,
1720 quirk_msi_intx_disable_bug); 1801 quirk_msi_intx_disable_bug);
@@ -1735,17 +1816,15 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
1735 quirk_msi_intx_disable_bug); 1816 quirk_msi_intx_disable_bug);
1736 1817
1737DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 1818DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
1738 quirk_msi_intx_disable_bug); 1819 quirk_msi_intx_disable_ati_bug);
1739DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 1820DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
1740 quirk_msi_intx_disable_bug); 1821 quirk_msi_intx_disable_ati_bug);
1741DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 1822DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
1742 quirk_msi_intx_disable_bug); 1823 quirk_msi_intx_disable_ati_bug);
1743DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 1824DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
1744 quirk_msi_intx_disable_bug); 1825 quirk_msi_intx_disable_ati_bug);
1745DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 1826DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
1746 quirk_msi_intx_disable_bug); 1827 quirk_msi_intx_disable_ati_bug);
1747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4395,
1748 quirk_msi_intx_disable_bug);
1749 1828
1750DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 1829DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
1751 quirk_msi_intx_disable_bug); 1830 quirk_msi_intx_disable_bug);
diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c
index 430281b2e921..ec4a82ba29a8 100644
--- a/drivers/pci/remove.c
+++ b/drivers/pci/remove.c
@@ -1,5 +1,6 @@
1#include <linux/pci.h> 1#include <linux/pci.h>
2#include <linux/module.h> 2#include <linux/module.h>
3#include <linux/aspm.h>
3#include "pci.h" 4#include "pci.h"
4 5
5static void pci_free_resources(struct pci_dev *dev) 6static void pci_free_resources(struct pci_dev *dev)
@@ -30,6 +31,9 @@ static void pci_stop_dev(struct pci_dev *dev)
30 dev->global_list.next = dev->global_list.prev = NULL; 31 dev->global_list.next = dev->global_list.prev = NULL;
31 up_write(&pci_bus_sem); 32 up_write(&pci_bus_sem);
32 } 33 }
34
35 if (dev->bus->self)
36 pcie_aspm_exit_link_state(dev);
33} 37}
34 38
35static void pci_destroy_dev(struct pci_dev *dev) 39static void pci_destroy_dev(struct pci_dev *dev)
@@ -74,10 +78,8 @@ void pci_remove_bus(struct pci_bus *pci_bus)
74 list_del(&pci_bus->node); 78 list_del(&pci_bus->node);
75 up_write(&pci_bus_sem); 79 up_write(&pci_bus_sem);
76 pci_remove_legacy_files(pci_bus); 80 pci_remove_legacy_files(pci_bus);
77 class_device_remove_file(&pci_bus->class_dev, 81 device_remove_file(&pci_bus->dev, &dev_attr_cpuaffinity);
78 &class_device_attr_cpuaffinity); 82 device_unregister(&pci_bus->dev);
79 sysfs_remove_link(&pci_bus->class_dev.kobj, "bridge");
80 class_device_unregister(&pci_bus->class_dev);
81} 83}
82EXPORT_SYMBOL(pci_remove_bus); 84EXPORT_SYMBOL(pci_remove_bus);
83 85
diff --git a/drivers/pci/rom.c b/drivers/pci/rom.c
index dbbcc04abd1a..a98b2470b9ea 100644
--- a/drivers/pci/rom.c
+++ b/drivers/pci/rom.c
@@ -162,6 +162,7 @@ void __iomem *pci_map_rom(struct pci_dev *pdev, size_t *size)
162 return rom; 162 return rom;
163} 163}
164 164
165#if 0
165/** 166/**
166 * pci_map_rom_copy - map a PCI ROM to kernel space, create a copy 167 * pci_map_rom_copy - map a PCI ROM to kernel space, create a copy
167 * @pdev: pointer to pci device struct 168 * @pdev: pointer to pci device struct
@@ -196,6 +197,7 @@ void __iomem *pci_map_rom_copy(struct pci_dev *pdev, size_t *size)
196 197
197 return (void __iomem *)(unsigned long)res->start; 198 return (void __iomem *)(unsigned long)res->start;
198} 199}
200#endif /* 0 */
199 201
200/** 202/**
201 * pci_unmap_rom - unmap the ROM from kernel space 203 * pci_unmap_rom - unmap the ROM from kernel space
@@ -218,6 +220,7 @@ void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
218 pci_disable_rom(pdev); 220 pci_disable_rom(pdev);
219} 221}
220 222
223#if 0
221/** 224/**
222 * pci_remove_rom - disable the ROM and remove its sysfs attribute 225 * pci_remove_rom - disable the ROM and remove its sysfs attribute
223 * @pdev: pointer to pci device struct 226 * @pdev: pointer to pci device struct
@@ -236,6 +239,7 @@ void pci_remove_rom(struct pci_dev *pdev)
236 IORESOURCE_ROM_COPY))) 239 IORESOURCE_ROM_COPY)))
237 pci_disable_rom(pdev); 240 pci_disable_rom(pdev);
238} 241}
242#endif /* 0 */
239 243
240/** 244/**
241 * pci_cleanup_rom - internal routine for freeing the ROM copy created 245 * pci_cleanup_rom - internal routine for freeing the ROM copy created
@@ -256,6 +260,4 @@ void pci_cleanup_rom(struct pci_dev *pdev)
256} 260}
257 261
258EXPORT_SYMBOL(pci_map_rom); 262EXPORT_SYMBOL(pci_map_rom);
259EXPORT_SYMBOL(pci_map_rom_copy);
260EXPORT_SYMBOL(pci_unmap_rom); 263EXPORT_SYMBOL(pci_unmap_rom);
261EXPORT_SYMBOL(pci_remove_rom);
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index 401e03c920bd..8a7232feb553 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -89,8 +89,9 @@ void pci_setup_cardbus(struct pci_bus *bus)
89 * The IO resource is allocated a range twice as large as it 89 * The IO resource is allocated a range twice as large as it
90 * would normally need. This allows us to set both IO regs. 90 * would normally need. This allows us to set both IO regs.
91 */ 91 */
92 printk(" IO window: %08lx-%08lx\n", 92 printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n",
93 region.start, region.end); 93 (unsigned long)region.start,
94 (unsigned long)region.end);
94 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, 95 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
95 region.start); 96 region.start);
96 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, 97 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
@@ -99,8 +100,9 @@ void pci_setup_cardbus(struct pci_bus *bus)
99 100
100 pcibios_resource_to_bus(bridge, &region, bus->resource[1]); 101 pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
101 if (bus->resource[1]->flags & IORESOURCE_IO) { 102 if (bus->resource[1]->flags & IORESOURCE_IO) {
102 printk(" IO window: %08lx-%08lx\n", 103 printk(KERN_INFO " IO window: 0x%08lx-0x%08lx\n",
103 region.start, region.end); 104 (unsigned long)region.start,
105 (unsigned long)region.end);
104 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, 106 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
105 region.start); 107 region.start);
106 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, 108 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
@@ -109,8 +111,9 @@ void pci_setup_cardbus(struct pci_bus *bus)
109 111
110 pcibios_resource_to_bus(bridge, &region, bus->resource[2]); 112 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
111 if (bus->resource[2]->flags & IORESOURCE_MEM) { 113 if (bus->resource[2]->flags & IORESOURCE_MEM) {
112 printk(" PREFETCH window: %08lx-%08lx\n", 114 printk(KERN_INFO " PREFETCH window: 0x%08lx-0x%08lx\n",
113 region.start, region.end); 115 (unsigned long)region.start,
116 (unsigned long)region.end);
114 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, 117 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
115 region.start); 118 region.start);
116 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, 119 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
@@ -119,8 +122,9 @@ void pci_setup_cardbus(struct pci_bus *bus)
119 122
120 pcibios_resource_to_bus(bridge, &region, bus->resource[3]); 123 pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
121 if (bus->resource[3]->flags & IORESOURCE_MEM) { 124 if (bus->resource[3]->flags & IORESOURCE_MEM) {
122 printk(" MEM window: %08lx-%08lx\n", 125 printk(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n",
123 region.start, region.end); 126 (unsigned long)region.start,
127 (unsigned long)region.end);
124 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, 128 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
125 region.start); 129 region.start);
126 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, 130 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
@@ -145,7 +149,7 @@ pci_setup_bridge(struct pci_bus *bus)
145{ 149{
146 struct pci_dev *bridge = bus->self; 150 struct pci_dev *bridge = bus->self;
147 struct pci_bus_region region; 151 struct pci_bus_region region;
148 u32 l, io_upper16; 152 u32 l, bu, lu, io_upper16;
149 153
150 DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge)); 154 DBG(KERN_INFO "PCI: Bridge: %s\n", pci_name(bridge));
151 155
@@ -159,7 +163,8 @@ pci_setup_bridge(struct pci_bus *bus)
159 /* Set up upper 16 bits of I/O base/limit. */ 163 /* Set up upper 16 bits of I/O base/limit. */
160 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); 164 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
161 DBG(KERN_INFO " IO window: %04lx-%04lx\n", 165 DBG(KERN_INFO " IO window: %04lx-%04lx\n",
162 region.start, region.end); 166 (unsigned long)region.start,
167 (unsigned long)region.end);
163 } 168 }
164 else { 169 else {
165 /* Clear upper 16 bits of I/O base/limit. */ 170 /* Clear upper 16 bits of I/O base/limit. */
@@ -180,8 +185,9 @@ pci_setup_bridge(struct pci_bus *bus)
180 if (bus->resource[1]->flags & IORESOURCE_MEM) { 185 if (bus->resource[1]->flags & IORESOURCE_MEM) {
181 l = (region.start >> 16) & 0xfff0; 186 l = (region.start >> 16) & 0xfff0;
182 l |= region.end & 0xfff00000; 187 l |= region.end & 0xfff00000;
183 DBG(KERN_INFO " MEM window: %08lx-%08lx\n", 188 DBG(KERN_INFO " MEM window: 0x%08lx-0x%08lx\n",
184 region.start, region.end); 189 (unsigned long)region.start,
190 (unsigned long)region.end);
185 } 191 }
186 else { 192 else {
187 l = 0x0000fff0; 193 l = 0x0000fff0;
@@ -195,12 +201,18 @@ pci_setup_bridge(struct pci_bus *bus)
195 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); 201 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
196 202
197 /* Set up PREF base/limit. */ 203 /* Set up PREF base/limit. */
204 bu = lu = 0;
198 pcibios_resource_to_bus(bridge, &region, bus->resource[2]); 205 pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
199 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { 206 if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
200 l = (region.start >> 16) & 0xfff0; 207 l = (region.start >> 16) & 0xfff0;
201 l |= region.end & 0xfff00000; 208 l |= region.end & 0xfff00000;
202 DBG(KERN_INFO " PREFETCH window: %08lx-%08lx\n", 209#ifdef CONFIG_RESOURCES_64BIT
203 region.start, region.end); 210 bu = region.start >> 32;
211 lu = region.end >> 32;
212#endif
213 DBG(KERN_INFO " PREFETCH window: 0x%016llx-0x%016llx\n",
214 (unsigned long long)region.start,
215 (unsigned long long)region.end);
204 } 216 }
205 else { 217 else {
206 l = 0x0000fff0; 218 l = 0x0000fff0;
@@ -208,8 +220,9 @@ pci_setup_bridge(struct pci_bus *bus)
208 } 220 }
209 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); 221 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
210 222
211 /* Clear out the upper 32 bits of PREF base. */ 223 /* Set the upper 32 bits of PREF base & limit. */
212 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0); 224 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
225 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
213 226
214 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl); 227 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
215} 228}
@@ -323,8 +336,8 @@ static void pbus_size_io(struct pci_bus *bus)
323static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type) 336static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
324{ 337{
325 struct pci_dev *dev; 338 struct pci_dev *dev;
326 unsigned long min_align, align, size; 339 resource_size_t min_align, align, size;
327 unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */ 340 resource_size_t aligns[12]; /* Alignments from 1Mb to 2Gb */
328 int order, max_order; 341 int order, max_order;
329 struct resource *b_res = find_free_bus_resource(bus, type); 342 struct resource *b_res = find_free_bus_resource(bus, type);
330 343
@@ -340,7 +353,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long
340 353
341 for (i = 0; i < PCI_NUM_RESOURCES; i++) { 354 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
342 struct resource *r = &dev->resource[i]; 355 struct resource *r = &dev->resource[i];
343 unsigned long r_size; 356 resource_size_t r_size;
344 357
345 if (r->parent || (r->flags & mask) != type) 358 if (r->parent || (r->flags & mask) != type)
346 continue; 359 continue;
@@ -350,10 +363,10 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long
350 order = __ffs(align) - 20; 363 order = __ffs(align) - 20;
351 if (order > 11) { 364 if (order > 11) {
352 printk(KERN_WARNING "PCI: region %s/%d " 365 printk(KERN_WARNING "PCI: region %s/%d "
353 "too large: %llx-%llx\n", 366 "too large: 0x%016llx-0x%016llx\n",
354 pci_name(dev), i, 367 pci_name(dev), i,
355 (unsigned long long)r->start, 368 (unsigned long long)r->start,
356 (unsigned long long)r->end); 369 (unsigned long long)r->end);
357 r->flags = 0; 370 r->flags = 0;
358 continue; 371 continue;
359 } 372 }
@@ -372,8 +385,11 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long
372 align = 0; 385 align = 0;
373 min_align = 0; 386 min_align = 0;
374 for (order = 0; order <= max_order; order++) { 387 for (order = 0; order <= max_order; order++) {
375 unsigned long align1 = 1UL << (order + 20); 388#ifdef CONFIG_RESOURCES_64BIT
376 389 resource_size_t align1 = 1ULL << (order + 20);
390#else
391 resource_size_t align1 = 1U << (order + 20);
392#endif
377 if (!align) 393 if (!align)
378 min_align = align1; 394 min_align = align1;
379 else if (ALIGN(align + min_align, min_align) < align1) 395 else if (ALIGN(align + min_align, min_align) < align1)
diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c
index 6dfd86167e39..4be7ccf7e3ae 100644
--- a/drivers/pci/setup-res.c
+++ b/drivers/pci/setup-res.c
@@ -51,10 +51,12 @@ pci_update_resource(struct pci_dev *dev, struct resource *res, int resno)
51 51
52 pcibios_resource_to_bus(dev, &region, res); 52 pcibios_resource_to_bus(dev, &region, res);
53 53
54 pr_debug(" got res [%llx:%llx] bus [%lx:%lx] flags %lx for " 54 pr_debug(" got res [%llx:%llx] bus [%llx:%llx] flags %lx for "
55 "BAR %d of %s\n", (unsigned long long)res->start, 55 "BAR %d of %s\n", (unsigned long long)res->start,
56 (unsigned long long)res->end, 56 (unsigned long long)res->end,
57 region.start, region.end, res->flags, resno, pci_name(dev)); 57 (unsigned long long)region.start,
58 (unsigned long long)region.end,
59 (unsigned long)res->flags, resno, pci_name(dev));
58 60
59 new = region.start | (res->flags & PCI_REGION_FLAG_MASK); 61 new = region.start | (res->flags & PCI_REGION_FLAG_MASK);
60 if (res->flags & IORESOURCE_IO) 62 if (res->flags & IORESOURCE_IO)
@@ -125,7 +127,6 @@ int pci_claim_resource(struct pci_dev *dev, int resource)
125 127
126 return err; 128 return err;
127} 129}
128EXPORT_SYMBOL_GPL(pci_claim_resource);
129 130
130int pci_assign_resource(struct pci_dev *dev, int resno) 131int pci_assign_resource(struct pci_dev *dev, int resno)
131{ 132{
diff --git a/drivers/pci/syscall.c b/drivers/pci/syscall.c
index 2ac050d7f8cf..645d7a60e412 100644
--- a/drivers/pci/syscall.c
+++ b/drivers/pci/syscall.c
@@ -34,7 +34,6 @@ sys_pciconfig_read(unsigned long bus, unsigned long dfn,
34 if (!dev) 34 if (!dev)
35 goto error; 35 goto error;
36 36
37 lock_kernel();
38 switch (len) { 37 switch (len) {
39 case 1: 38 case 1:
40 cfg_ret = pci_user_read_config_byte(dev, off, &byte); 39 cfg_ret = pci_user_read_config_byte(dev, off, &byte);
@@ -47,10 +46,8 @@ sys_pciconfig_read(unsigned long bus, unsigned long dfn,
47 break; 46 break;
48 default: 47 default:
49 err = -EINVAL; 48 err = -EINVAL;
50 unlock_kernel();
51 goto error; 49 goto error;
52 }; 50 };
53 unlock_kernel();
54 51
55 err = -EIO; 52 err = -EIO;
56 if (cfg_ret != PCIBIOS_SUCCESSFUL) 53 if (cfg_ret != PCIBIOS_SUCCESSFUL)
@@ -107,7 +104,6 @@ sys_pciconfig_write(unsigned long bus, unsigned long dfn,
107 if (!dev) 104 if (!dev)
108 return -ENODEV; 105 return -ENODEV;
109 106
110 lock_kernel();
111 switch(len) { 107 switch(len) {
112 case 1: 108 case 1:
113 err = get_user(byte, (u8 __user *)buf); 109 err = get_user(byte, (u8 __user *)buf);
@@ -140,7 +136,6 @@ sys_pciconfig_write(unsigned long bus, unsigned long dfn,
140 err = -EINVAL; 136 err = -EINVAL;
141 break; 137 break;
142 } 138 }
143 unlock_kernel();
144 pci_dev_put(dev); 139 pci_dev_put(dev);
145 return err; 140 return err;
146} 141}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 03:00:43 -0500