PCI: Add generic config accessors

Many PCI controllers' configuration space accesses are memory-mapped and
vary only in address calculation and access checks.  There are 2 main
access methods: a decoded address space such as ECAM or a single address
and data register similar to x86.  This implementation can support both
cases as well as be used in cases that need additional pre- or post-access
handling.

Add a new pci_ops member, map_bus, which can do access checks and any
necessary setup.  It returns the address to use for the configuration space
access.  The access types supported are 32-bit only accesses or correct
byte, word, or dword sized accesses.

Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>

1 files changed, 87 insertions, 0 deletions

diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 49dd766852ba..d9b64a175990 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -67,6 +67,93 @@ EXPORT_SYMBOL(pci_bus_write_config_byte);
 EXPORT_SYMBOL(pci_bus_write_config_word);
 EXPORT_SYMBOL(pci_bus_write_config_dword);
 
+int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
+                            int where, int size, u32 *val)
+{
+        void __iomem *addr;
+
+        addr = bus->ops->map_bus(bus, devfn, where);
+        if (!addr) {
+                *val = ~0;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        if (size == 1)
+                *val = readb(addr);
+        else if (size == 2)
+                *val = readw(addr);
+        else
+                *val = readl(addr);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+EXPORT_SYMBOL_GPL(pci_generic_config_read);
+
+int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
+                             int where, int size, u32 val)
+{
+        void __iomem *addr;
+
+        addr = bus->ops->map_bus(bus, devfn, where);
+        if (!addr)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        if (size == 1)
+                writeb(val, addr);
+        else if (size == 2)
+                writew(val, addr);
+        else
+                writel(val, addr);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+EXPORT_SYMBOL_GPL(pci_generic_config_write);
+
+int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
+                              int where, int size, u32 *val)
+{
+        void __iomem *addr;
+
+        addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
+        if (!addr) {
+                *val = ~0;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        *val = readl(addr);
+
+        if (size <= 2)
+                *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+EXPORT_SYMBOL_GPL(pci_generic_config_read32);
+
+int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
+                               int where, int size, u32 val)
+{
+        void __iomem *addr;
+        u32 mask, tmp;
+
+        addr = bus->ops->map_bus(bus, devfn, where & ~0x3);
+        if (!addr)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        if (size == 4) {
+                writel(val, addr);
+                return PCIBIOS_SUCCESSFUL;
+        } else {
+                mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
+        }
+
+        tmp = readl(addr) & mask;
+        tmp |= val << ((where & 0x3) * 8);
+        writel(tmp, addr);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+EXPORT_SYMBOL_GPL(pci_generic_config_write32);
+
 /**
  * pci_bus_set_ops - Set raw operations of pci bus
  * @bus:        pci bus struct