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authorJesse Barnes <jbarnes@virtuousgeek.org>2008-10-18 20:33:19 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2008-10-20 14:01:51 -0400
commit0927678f55c9a50c296f7e6dae85e87b8236e155 (patch)
tree480bec05ca6b31329eac8533243e1295749d3e46 /drivers/pci
parent1543c90c39360df333a21bfbbdfe812ae23b8167 (diff)
PCI: use pci_find_ext_capability everywhere
Remove some open coded (and buggy) versions of pci_find_ext_capability in favor of the real routine in the PCI core. Tested-by: Tomasz Czernecki <czernecki@gmail.com> Acked-by: Andrew Vasquez <andrew.vasquez@qlogic.com> Reviewed-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pcie/aer/aerdrv.c6
-rw-r--r--drivers/pci/pcie/aer/aerdrv_core.c47
-rw-r--r--drivers/pci/pcie/portdrv_core.c23
3 files changed, 18 insertions, 58 deletions
diff --git a/drivers/pci/pcie/aer/aerdrv.c b/drivers/pci/pcie/aer/aerdrv.c
index 77036f46acfe..e390707661dd 100644
--- a/drivers/pci/pcie/aer/aerdrv.c
+++ b/drivers/pci/pcie/aer/aerdrv.c
@@ -105,7 +105,7 @@ static irqreturn_t aer_irq(int irq, void *context)
105 unsigned long flags; 105 unsigned long flags;
106 int pos; 106 int pos;
107 107
108 pos = pci_find_aer_capability(pdev->port); 108 pos = pci_find_ext_capability(pdev->port, PCI_EXT_CAP_ID_ERR);
109 /* 109 /*
110 * Must lock access to Root Error Status Reg, Root Error ID Reg, 110 * Must lock access to Root Error Status Reg, Root Error ID Reg,
111 * and Root error producer/consumer index 111 * and Root error producer/consumer index
@@ -252,7 +252,7 @@ static pci_ers_result_t aer_root_reset(struct pci_dev *dev)
252 u32 status; 252 u32 status;
253 int pos; 253 int pos;
254 254
255 pos = pci_find_aer_capability(dev); 255 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
256 256
257 /* Disable Root's interrupt in response to error messages */ 257 /* Disable Root's interrupt in response to error messages */
258 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, 0); 258 pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND, 0);
@@ -316,7 +316,7 @@ static void aer_error_resume(struct pci_dev *dev)
316 pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, reg16); 316 pci_write_config_word(dev, pos + PCI_EXP_DEVSTA, reg16);
317 317
318 /* Clean AER Root Error Status */ 318 /* Clean AER Root Error Status */
319 pos = pci_find_aer_capability(dev); 319 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
320 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status); 320 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS, &status);
321 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask); 321 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &mask);
322 if (dev->error_state == pci_channel_io_normal) 322 if (dev->error_state == pci_channel_io_normal)
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index ee5e7b5176d0..1ff21f6045d6 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -28,36 +28,6 @@
28static int forceload; 28static int forceload;
29module_param(forceload, bool, 0); 29module_param(forceload, bool, 0);
30 30
31#define PCI_CFG_SPACE_SIZE (0x100)
32int pci_find_aer_capability(struct pci_dev *dev)
33{
34 int pos;
35 u32 reg32 = 0;
36
37 /* Check if it's a pci-express device */
38 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
39 if (!pos)
40 return 0;
41
42 /* Check if it supports pci-express AER */
43 pos = PCI_CFG_SPACE_SIZE;
44 while (pos) {
45 if (pci_read_config_dword(dev, pos, &reg32))
46 return 0;
47
48 /* some broken boards return ~0 */
49 if (reg32 == 0xffffffff)
50 return 0;
51
52 if (PCI_EXT_CAP_ID(reg32) == PCI_EXT_CAP_ID_ERR)
53 break;
54
55 pos = reg32 >> 20;
56 }
57
58 return pos;
59}
60
61int pci_enable_pcie_error_reporting(struct pci_dev *dev) 31int pci_enable_pcie_error_reporting(struct pci_dev *dev)
62{ 32{
63 u16 reg16 = 0; 33 u16 reg16 = 0;
@@ -67,6 +37,10 @@ int pci_enable_pcie_error_reporting(struct pci_dev *dev)
67 if (!pos) 37 if (!pos)
68 return -EIO; 38 return -EIO;
69 39
40 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
41 if (!pos)
42 return -EIO;
43
70 pci_read_config_word(dev, pos+PCI_EXP_DEVCTL, &reg16); 44 pci_read_config_word(dev, pos+PCI_EXP_DEVCTL, &reg16);
71 reg16 = reg16 | 45 reg16 = reg16 |
72 PCI_EXP_DEVCTL_CERE | 46 PCI_EXP_DEVCTL_CERE |
@@ -102,7 +76,7 @@ int pci_cleanup_aer_uncorrect_error_status(struct pci_dev *dev)
102 int pos; 76 int pos;
103 u32 status, mask; 77 u32 status, mask;
104 78
105 pos = pci_find_aer_capability(dev); 79 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
106 if (!pos) 80 if (!pos)
107 return -EIO; 81 return -EIO;
108 82
@@ -123,7 +97,7 @@ int pci_cleanup_aer_correct_error_status(struct pci_dev *dev)
123 int pos; 97 int pos;
124 u32 status; 98 u32 status;
125 99
126 pos = pci_find_aer_capability(dev); 100 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
127 if (!pos) 101 if (!pos)
128 return -EIO; 102 return -EIO;
129 103
@@ -502,7 +476,7 @@ static void handle_error_source(struct pcie_device * aerdev,
502 * Correctable error does not need software intevention. 476 * Correctable error does not need software intevention.
503 * No need to go through error recovery process. 477 * No need to go through error recovery process.
504 */ 478 */
505 pos = pci_find_aer_capability(dev); 479 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
506 if (pos) 480 if (pos)
507 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, 481 pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS,
508 info.status); 482 info.status);
@@ -542,7 +516,7 @@ void aer_enable_rootport(struct aer_rpc *rpc)
542 reg16 &= ~(SYSTEM_ERROR_INTR_ON_MESG_MASK); 516 reg16 &= ~(SYSTEM_ERROR_INTR_ON_MESG_MASK);
543 pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, reg16); 517 pci_write_config_word(pdev, pos + PCI_EXP_RTCTL, reg16);
544 518
545 aer_pos = pci_find_aer_capability(pdev); 519 aer_pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
546 /* Clear error status */ 520 /* Clear error status */
547 pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, &reg32); 521 pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, &reg32);
548 pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, reg32); 522 pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, reg32);
@@ -579,7 +553,7 @@ static void disable_root_aer(struct aer_rpc *rpc)
579 u32 reg32; 553 u32 reg32;
580 int pos; 554 int pos;
581 555
582 pos = pci_find_aer_capability(pdev); 556 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
583 /* Disable Root's interrupt in response to error messages */ 557 /* Disable Root's interrupt in response to error messages */
584 pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, 0); 558 pci_write_config_dword(pdev, pos + PCI_ERR_ROOT_COMMAND, 0);
585 559
@@ -618,7 +592,7 @@ static int get_device_error_info(struct pci_dev *dev, struct aer_err_info *info)
618{ 592{
619 int pos; 593 int pos;
620 594
621 pos = pci_find_aer_capability(dev); 595 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
622 596
623 /* The device might not support AER */ 597 /* The device might not support AER */
624 if (!pos) 598 if (!pos)
@@ -755,7 +729,6 @@ int aer_init(struct pcie_device *dev)
755 return AER_SUCCESS; 729 return AER_SUCCESS;
756} 730}
757 731
758EXPORT_SYMBOL_GPL(pci_find_aer_capability);
759EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting); 732EXPORT_SYMBOL_GPL(pci_enable_pcie_error_reporting);
760EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting); 733EXPORT_SYMBOL_GPL(pci_disable_pcie_error_reporting);
761EXPORT_SYMBOL_GPL(pci_cleanup_aer_uncorrect_error_status); 734EXPORT_SYMBOL_GPL(pci_cleanup_aer_uncorrect_error_status);
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 890f0d2b370a..2e091e014829 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -195,24 +195,11 @@ static int get_port_device_capability(struct pci_dev *dev)
195 /* PME Capable - root port capability */ 195 /* PME Capable - root port capability */
196 if (((reg16 >> 4) & PORT_TYPE_MASK) == PCIE_RC_PORT) 196 if (((reg16 >> 4) & PORT_TYPE_MASK) == PCIE_RC_PORT)
197 services |= PCIE_PORT_SERVICE_PME; 197 services |= PCIE_PORT_SERVICE_PME;
198 198
199 pos = PCI_CFG_SPACE_SIZE; 199 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR))
200 while (pos) { 200 services |= PCIE_PORT_SERVICE_AER;
201 pci_read_config_dword(dev, pos, &reg32); 201 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_VC))
202 switch (reg32 & 0xffff) { 202 services |= PCIE_PORT_SERVICE_VC;
203 case PCI_EXT_CAP_ID_ERR:
204 services |= PCIE_PORT_SERVICE_AER;
205 pos = reg32 >> 20;
206 break;
207 case PCI_EXT_CAP_ID_VC:
208 services |= PCIE_PORT_SERVICE_VC;
209 pos = reg32 >> 20;
210 break;
211 default:
212 pos = 0;
213 break;
214 }
215 }
216 203
217 return services; 204 return services;
218} 205}