diff options
author | Seungwon Jeon <tgih.jun@samsung.com> | 2013-08-29 08:35:56 -0400 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2013-08-29 15:47:20 -0400 |
commit | 058dd016a1ed43d0d8e0c6c10a472d560a3299b4 (patch) | |
tree | e2d3227074ed233fd2736d800777017d955d070f /drivers/pci | |
parent | f7b7868ced6dd5c8e9362c813b1fbb554f7a5812 (diff) |
PCI: exynos: Add I/O access wrappers
This patch adds wrappers for MMIO access to ELBI, PHY, and other
registers. No functional change.
[bhelgaas: changelog]
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Diffstat (limited to 'drivers/pci')
-rw-r--r-- | drivers/pci/host/pci-exynos.c | 160 |
1 files changed, 91 insertions, 69 deletions
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c index 012ca8aec71a..94e096bb2d0a 100644 --- a/drivers/pci/host/pci-exynos.c +++ b/drivers/pci/host/pci-exynos.c | |||
@@ -91,19 +91,49 @@ struct exynos_pcie { | |||
91 | #define PCIE_PHY_TRSV3_RXCDR 0x2ec | 91 | #define PCIE_PHY_TRSV3_RXCDR 0x2ec |
92 | #define PCIE_PHY_TRSV3_LVCC 0x31c | 92 | #define PCIE_PHY_TRSV3_LVCC 0x31c |
93 | 93 | ||
94 | static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg) | ||
95 | { | ||
96 | writel(val, pcie->elbi_base + reg); | ||
97 | } | ||
98 | |||
99 | static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg) | ||
100 | { | ||
101 | return readl(pcie->elbi_base + reg); | ||
102 | } | ||
103 | |||
104 | static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg) | ||
105 | { | ||
106 | writel(val, pcie->phy_base + reg); | ||
107 | } | ||
108 | |||
109 | static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg) | ||
110 | { | ||
111 | return readl(pcie->phy_base + reg); | ||
112 | } | ||
113 | |||
114 | static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg) | ||
115 | { | ||
116 | writel(val, pcie->block_base + reg); | ||
117 | } | ||
118 | |||
119 | static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg) | ||
120 | { | ||
121 | return readl(pcie->block_base + reg); | ||
122 | } | ||
123 | |||
94 | static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on) | 124 | static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on) |
95 | { | 125 | { |
96 | u32 val; | 126 | u32 val; |
97 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | 127 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
98 | 128 | ||
99 | if (on) { | 129 | if (on) { |
100 | val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC); | 130 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC); |
101 | val |= PCIE_ELBI_SLV_DBI_ENABLE; | 131 | val |= PCIE_ELBI_SLV_DBI_ENABLE; |
102 | writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC); | 132 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC); |
103 | } else { | 133 | } else { |
104 | val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC); | 134 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC); |
105 | val &= ~PCIE_ELBI_SLV_DBI_ENABLE; | 135 | val &= ~PCIE_ELBI_SLV_DBI_ENABLE; |
106 | writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_AWMISC); | 136 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC); |
107 | } | 137 | } |
108 | } | 138 | } |
109 | 139 | ||
@@ -113,13 +143,13 @@ static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on) | |||
113 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | 143 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
114 | 144 | ||
115 | if (on) { | 145 | if (on) { |
116 | val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC); | 146 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC); |
117 | val |= PCIE_ELBI_SLV_DBI_ENABLE; | 147 | val |= PCIE_ELBI_SLV_DBI_ENABLE; |
118 | writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC); | 148 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC); |
119 | } else { | 149 | } else { |
120 | val = readl(exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC); | 150 | val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC); |
121 | val &= ~PCIE_ELBI_SLV_DBI_ENABLE; | 151 | val &= ~PCIE_ELBI_SLV_DBI_ENABLE; |
122 | writel(val, exynos_pcie->elbi_base + PCIE_ELBI_SLV_ARMISC); | 152 | exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC); |
123 | } | 153 | } |
124 | } | 154 | } |
125 | 155 | ||
@@ -127,95 +157,89 @@ static void exynos_pcie_assert_core_reset(struct pcie_port *pp) | |||
127 | { | 157 | { |
128 | u32 val; | 158 | u32 val; |
129 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | 159 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
130 | void __iomem *elbi_base = exynos_pcie->elbi_base; | ||
131 | 160 | ||
132 | val = readl(elbi_base + PCIE_CORE_RESET); | 161 | val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET); |
133 | val &= ~PCIE_CORE_RESET_ENABLE; | 162 | val &= ~PCIE_CORE_RESET_ENABLE; |
134 | writel(val, elbi_base + PCIE_CORE_RESET); | 163 | exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET); |
135 | writel(0, elbi_base + PCIE_PWR_RESET); | 164 | exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET); |
136 | writel(0, elbi_base + PCIE_STICKY_RESET); | 165 | exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET); |
137 | writel(0, elbi_base + PCIE_NONSTICKY_RESET); | 166 | exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET); |
138 | } | 167 | } |
139 | 168 | ||
140 | static void exynos_pcie_deassert_core_reset(struct pcie_port *pp) | 169 | static void exynos_pcie_deassert_core_reset(struct pcie_port *pp) |
141 | { | 170 | { |
142 | u32 val; | 171 | u32 val; |
143 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | 172 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
144 | void __iomem *elbi_base = exynos_pcie->elbi_base; | ||
145 | void __iomem *block_base = exynos_pcie->block_base; | ||
146 | 173 | ||
147 | val = readl(elbi_base + PCIE_CORE_RESET); | 174 | val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET); |
148 | val |= PCIE_CORE_RESET_ENABLE; | 175 | val |= PCIE_CORE_RESET_ENABLE; |
149 | writel(val, elbi_base + PCIE_CORE_RESET); | 176 | |
150 | writel(1, elbi_base + PCIE_STICKY_RESET); | 177 | exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET); |
151 | writel(1, elbi_base + PCIE_NONSTICKY_RESET); | 178 | exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET); |
152 | writel(1, elbi_base + PCIE_APP_INIT_RESET); | 179 | exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET); |
153 | writel(0, elbi_base + PCIE_APP_INIT_RESET); | 180 | exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET); |
154 | writel(1, block_base + PCIE_PHY_MAC_RESET); | 181 | exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET); |
182 | exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET); | ||
155 | } | 183 | } |
156 | 184 | ||
157 | static void exynos_pcie_assert_phy_reset(struct pcie_port *pp) | 185 | static void exynos_pcie_assert_phy_reset(struct pcie_port *pp) |
158 | { | 186 | { |
159 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | 187 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
160 | void __iomem *block_base = exynos_pcie->block_base; | ||
161 | 188 | ||
162 | writel(0, block_base + PCIE_PHY_MAC_RESET); | 189 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET); |
163 | writel(1, block_base + PCIE_PHY_GLOBAL_RESET); | 190 | exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET); |
164 | } | 191 | } |
165 | 192 | ||
166 | static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp) | 193 | static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp) |
167 | { | 194 | { |
168 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | 195 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
169 | void __iomem *elbi_base = exynos_pcie->elbi_base; | 196 | |
170 | void __iomem *block_base = exynos_pcie->block_base; | 197 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET); |
171 | 198 | exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET); | |
172 | writel(0, block_base + PCIE_PHY_GLOBAL_RESET); | 199 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET); |
173 | writel(1, elbi_base + PCIE_PWR_RESET); | 200 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG); |
174 | writel(0, block_base + PCIE_PHY_COMMON_RESET); | 201 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET); |
175 | writel(0, block_base + PCIE_PHY_CMN_REG); | 202 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET); |
176 | writel(0, block_base + PCIE_PHY_TRSVREG_RESET); | ||
177 | writel(0, block_base + PCIE_PHY_TRSV_RESET); | ||
178 | } | 203 | } |
179 | 204 | ||
180 | static void exynos_pcie_init_phy(struct pcie_port *pp) | 205 | static void exynos_pcie_init_phy(struct pcie_port *pp) |
181 | { | 206 | { |
182 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | 207 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
183 | void __iomem *phy_base = exynos_pcie->phy_base; | ||
184 | 208 | ||
185 | /* DCC feedback control off */ | 209 | /* DCC feedback control off */ |
186 | writel(0x29, phy_base + PCIE_PHY_DCC_FEEDBACK); | 210 | exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK); |
187 | 211 | ||
188 | /* set TX/RX impedance */ | 212 | /* set TX/RX impedance */ |
189 | writel(0xd5, phy_base + PCIE_PHY_IMPEDANCE); | 213 | exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE); |
190 | 214 | ||
191 | /* set 50Mhz PHY clock */ | 215 | /* set 50Mhz PHY clock */ |
192 | writel(0x14, phy_base + PCIE_PHY_PLL_DIV_0); | 216 | exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0); |
193 | writel(0x12, phy_base + PCIE_PHY_PLL_DIV_1); | 217 | exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1); |
194 | 218 | ||
195 | /* set TX Differential output for lane 0 */ | 219 | /* set TX Differential output for lane 0 */ |
196 | writel(0x7f, phy_base + PCIE_PHY_TRSV0_DRV_LVL); | 220 | exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL); |
197 | 221 | ||
198 | /* set TX Pre-emphasis Level Control for lane 0 to minimum */ | 222 | /* set TX Pre-emphasis Level Control for lane 0 to minimum */ |
199 | writel(0x0, phy_base + PCIE_PHY_TRSV0_EMP_LVL); | 223 | exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL); |
200 | 224 | ||
201 | /* set RX clock and data recovery bandwidth */ | 225 | /* set RX clock and data recovery bandwidth */ |
202 | writel(0xe7, phy_base + PCIE_PHY_PLL_BIAS); | 226 | exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS); |
203 | writel(0x82, phy_base + PCIE_PHY_TRSV0_RXCDR); | 227 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR); |
204 | writel(0x82, phy_base + PCIE_PHY_TRSV1_RXCDR); | 228 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR); |
205 | writel(0x82, phy_base + PCIE_PHY_TRSV2_RXCDR); | 229 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR); |
206 | writel(0x82, phy_base + PCIE_PHY_TRSV3_RXCDR); | 230 | exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR); |
207 | 231 | ||
208 | /* change TX Pre-emphasis Level Control for lanes */ | 232 | /* change TX Pre-emphasis Level Control for lanes */ |
209 | writel(0x39, phy_base + PCIE_PHY_TRSV0_EMP_LVL); | 233 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL); |
210 | writel(0x39, phy_base + PCIE_PHY_TRSV1_EMP_LVL); | 234 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL); |
211 | writel(0x39, phy_base + PCIE_PHY_TRSV2_EMP_LVL); | 235 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL); |
212 | writel(0x39, phy_base + PCIE_PHY_TRSV3_EMP_LVL); | 236 | exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL); |
213 | 237 | ||
214 | /* set LVCC */ | 238 | /* set LVCC */ |
215 | writel(0x20, phy_base + PCIE_PHY_TRSV0_LVCC); | 239 | exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC); |
216 | writel(0xa0, phy_base + PCIE_PHY_TRSV1_LVCC); | 240 | exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC); |
217 | writel(0xa0, phy_base + PCIE_PHY_TRSV2_LVCC); | 241 | exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC); |
218 | writel(0xa0, phy_base + PCIE_PHY_TRSV3_LVCC); | 242 | exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC); |
219 | } | 243 | } |
220 | 244 | ||
221 | static void exynos_pcie_assert_reset(struct pcie_port *pp) | 245 | static void exynos_pcie_assert_reset(struct pcie_port *pp) |
@@ -233,9 +257,6 @@ static int exynos_pcie_establish_link(struct pcie_port *pp) | |||
233 | u32 val; | 257 | u32 val; |
234 | int count = 0; | 258 | int count = 0; |
235 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | 259 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
236 | void __iomem *elbi_base = exynos_pcie->elbi_base; | ||
237 | void __iomem *block_base = exynos_pcie->block_base; | ||
238 | void __iomem *phy_base = exynos_pcie->phy_base; | ||
239 | 260 | ||
240 | if (dw_pcie_link_up(pp)) { | 261 | if (dw_pcie_link_up(pp)) { |
241 | dev_err(pp->dev, "Link already up\n"); | 262 | dev_err(pp->dev, "Link already up\n"); |
@@ -253,9 +274,9 @@ static int exynos_pcie_establish_link(struct pcie_port *pp) | |||
253 | exynos_pcie_init_phy(pp); | 274 | exynos_pcie_init_phy(pp); |
254 | 275 | ||
255 | /* pulse for common reset */ | 276 | /* pulse for common reset */ |
256 | writel(1, block_base + PCIE_PHY_COMMON_RESET); | 277 | exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET); |
257 | udelay(500); | 278 | udelay(500); |
258 | writel(0, block_base + PCIE_PHY_COMMON_RESET); | 279 | exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET); |
259 | 280 | ||
260 | /* de-assert core reset */ | 281 | /* de-assert core reset */ |
261 | exynos_pcie_deassert_core_reset(pp); | 282 | exynos_pcie_deassert_core_reset(pp); |
@@ -267,15 +288,18 @@ static int exynos_pcie_establish_link(struct pcie_port *pp) | |||
267 | exynos_pcie_assert_reset(pp); | 288 | exynos_pcie_assert_reset(pp); |
268 | 289 | ||
269 | /* assert LTSSM enable */ | 290 | /* assert LTSSM enable */ |
270 | writel(PCIE_ELBI_LTSSM_ENABLE, elbi_base + PCIE_APP_LTSSM_ENABLE); | 291 | exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE, |
292 | PCIE_APP_LTSSM_ENABLE); | ||
271 | 293 | ||
272 | /* check if the link is up or not */ | 294 | /* check if the link is up or not */ |
273 | while (!dw_pcie_link_up(pp)) { | 295 | while (!dw_pcie_link_up(pp)) { |
274 | mdelay(100); | 296 | mdelay(100); |
275 | count++; | 297 | count++; |
276 | if (count == 10) { | 298 | if (count == 10) { |
277 | while (readl(phy_base + PCIE_PHY_PLL_LOCKED) == 0) { | 299 | while (exynos_phy_readl(exynos_pcie, |
278 | val = readl(block_base + PCIE_PHY_PLL_LOCKED); | 300 | PCIE_PHY_PLL_LOCKED) == 0) { |
301 | val = exynos_blk_readl(exynos_pcie, | ||
302 | PCIE_PHY_PLL_LOCKED); | ||
279 | dev_info(pp->dev, "PLL Locked: 0x%x\n", val); | 303 | dev_info(pp->dev, "PLL Locked: 0x%x\n", val); |
280 | } | 304 | } |
281 | dev_err(pp->dev, "PCIe Link Fail\n"); | 305 | dev_err(pp->dev, "PCIe Link Fail\n"); |
@@ -292,10 +316,9 @@ static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp) | |||
292 | { | 316 | { |
293 | u32 val; | 317 | u32 val; |
294 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | 318 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
295 | void __iomem *elbi_base = exynos_pcie->elbi_base; | ||
296 | 319 | ||
297 | val = readl(elbi_base + PCIE_IRQ_PULSE); | 320 | val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE); |
298 | writel(val, elbi_base + PCIE_IRQ_PULSE); | 321 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE); |
299 | return; | 322 | return; |
300 | } | 323 | } |
301 | 324 | ||
@@ -303,12 +326,11 @@ static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp) | |||
303 | { | 326 | { |
304 | u32 val; | 327 | u32 val; |
305 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | 328 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
306 | void __iomem *elbi_base = exynos_pcie->elbi_base; | ||
307 | 329 | ||
308 | /* enable INTX interrupt */ | 330 | /* enable INTX interrupt */ |
309 | val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | | 331 | val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | |
310 | IRQ_INTC_ASSERT | IRQ_INTD_ASSERT, | 332 | IRQ_INTC_ASSERT | IRQ_INTD_ASSERT, |
311 | writel(val, elbi_base + PCIE_IRQ_EN_PULSE); | 333 | exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE); |
312 | return; | 334 | return; |
313 | } | 335 | } |
314 | 336 | ||
@@ -369,7 +391,7 @@ static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, | |||
369 | static int exynos_pcie_link_up(struct pcie_port *pp) | 391 | static int exynos_pcie_link_up(struct pcie_port *pp) |
370 | { | 392 | { |
371 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); | 393 | struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
372 | u32 val = readl(exynos_pcie->elbi_base + PCIE_ELBI_RDLH_LINKUP); | 394 | u32 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP); |
373 | 395 | ||
374 | if (val == PCIE_ELBI_LTSSM_ENABLE) | 396 | if (val == PCIE_ELBI_LTSSM_ENABLE) |
375 | return 1; | 397 | return 1; |