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authorZhang, Yanmin <yanmin.zhang@intel.com>2006-07-31 03:21:33 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2006-09-26 20:43:53 -0400
commit6c2b374d74857e892080ee726184ec1d15e7d4e4 (patch)
treec107532c288bcede80e45ebc3e46292bfaf0cea2 /drivers/pci/pcie/aer/aerdrv_acpi.c
parent48408157ebf5b2c6dc1e04ba5d258012f6a7f356 (diff)
PCI-Express AER implemetation: AER core and aerdriver
Patch 3 implements the core part of PCI-Express AER and aerdrv port service driver. When a root port service device is probed, the aerdrv will call request_irq to register irq handler for AER error interrupt. When a device sends an PCI-Express error message to the root port, the root port will trigger an interrupt, by either MSI or IO-APIC, then kernel would run the irq handler. The handler collects root error status register and schedules a work. The work will call the core part to process the error based on its type (Correctable/non-fatal/fatal). As for Correctable errors, the patch chooses to just clear the correctable error status register of the device. As for the non-fatal error, the patch follows generic PCI error handler rules to call the error callback functions of the endpoint's driver. If the device is a bridge, the patch chooses to broadcast the error to downstream devices. As for the fatal error, the patch resets the pci-express link and follows generic PCI error handler rules to call the error callback functions of the endpoint's driver. If the device is a bridge, the patch chooses to broadcast the error to downstream devices. Signed-off-by: Zhang Yanmin <yanmin.zhang@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci/pcie/aer/aerdrv_acpi.c')
-rw-r--r--drivers/pci/pcie/aer/aerdrv_acpi.c68
1 files changed, 68 insertions, 0 deletions
diff --git a/drivers/pci/pcie/aer/aerdrv_acpi.c b/drivers/pci/pcie/aer/aerdrv_acpi.c
new file mode 100644
index 000000000000..fa68e89ebec9
--- /dev/null
+++ b/drivers/pci/pcie/aer/aerdrv_acpi.c
@@ -0,0 +1,68 @@
1/*
2 * Access ACPI _OSC method
3 *
4 * Copyright (C) 2006 Intel Corp.
5 * Tom Long Nguyen (tom.l.nguyen@intel.com)
6 * Zhang Yanmin (yanmin.zhang@intel.com)
7 *
8 */
9
10#include <linux/module.h>
11#include <linux/pci.h>
12#include <linux/kernel.h>
13#include <linux/errno.h>
14#include <linux/pm.h>
15#include <linux/suspend.h>
16#include <linux/acpi.h>
17#include <linux/pci-acpi.h>
18#include <linux/delay.h>
19#include "aerdrv.h"
20
21/**
22 * aer_osc_setup - run ACPI _OSC method
23 *
24 * Return:
25 * Zero if success. Nonzero for otherwise.
26 *
27 * Invoked when PCIE bus loads AER service driver. To avoid conflict with
28 * BIOS AER support requires BIOS to yield AER control to OS native driver.
29 **/
30int aer_osc_setup(struct pci_dev *dev)
31{
32 int retval = OSC_METHOD_RUN_SUCCESS;
33 acpi_status status;
34 acpi_handle handle = DEVICE_ACPI_HANDLE(&dev->dev);
35 struct pci_dev *pdev = dev;
36 struct pci_bus *parent;
37
38 while (!handle) {
39 if (!pdev || !pdev->bus->parent)
40 break;
41 parent = pdev->bus->parent;
42 if (!parent->self)
43 /* Parent must be a host bridge */
44 handle = acpi_get_pci_rootbridge_handle(
45 pci_domain_nr(parent),
46 parent->number);
47 else
48 handle = DEVICE_ACPI_HANDLE(
49 &(parent->self->dev));
50 pdev = parent->self;
51 }
52
53 if (!handle)
54 return OSC_METHOD_NOT_SUPPORTED;
55
56 pci_osc_support_set(OSC_EXT_PCI_CONFIG_SUPPORT);
57 status = pci_osc_control_set(handle, OSC_PCI_EXPRESS_AER_CONTROL |
58 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL);
59 if (ACPI_FAILURE(status)) {
60 if (status == AE_SUPPORT)
61 retval = OSC_METHOD_NOT_SUPPORTED;
62 else
63 retval = OSC_METHOD_RUN_FAILURE;
64 }
65
66 return retval;
67}
68