diff options
author | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 20:55:21 -0400 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2009-09-08 20:55:21 -0400 |
commit | bbb20089a3275a19e475dbc21320c3742e3ca423 (patch) | |
tree | 216fdc1cbef450ca688135c5b8969169482d9a48 /drivers/pci/msi.h | |
parent | 3e48e656903e9fd8bc805c6a2c4264d7808d315b (diff) | |
parent | 657a77fa7284d8ae28dfa48f1dc5d919bf5b2843 (diff) |
Merge branch 'dmaengine' into async-tx-next
Conflicts:
crypto/async_tx/async_xor.c
drivers/dma/ioat/dma_v2.h
drivers/dma/ioat/pci.c
drivers/md/raid5.c
Diffstat (limited to 'drivers/pci/msi.h')
-rw-r--r-- | drivers/pci/msi.h | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/drivers/pci/msi.h b/drivers/pci/msi.h index 71f4df2ef654..a0662842550b 100644 --- a/drivers/pci/msi.h +++ b/drivers/pci/msi.h | |||
@@ -16,21 +16,15 @@ | |||
16 | #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO) | 16 | #define msi_lower_address_reg(base) (base + PCI_MSI_ADDRESS_LO) |
17 | #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI) | 17 | #define msi_upper_address_reg(base) (base + PCI_MSI_ADDRESS_HI) |
18 | #define msi_data_reg(base, is64bit) \ | 18 | #define msi_data_reg(base, is64bit) \ |
19 | ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 ) | 19 | (base + ((is64bit == 1) ? PCI_MSI_DATA_64 : PCI_MSI_DATA_32)) |
20 | #define msi_mask_bits_reg(base, is64bit) \ | 20 | #define msi_mask_reg(base, is64bit) \ |
21 | ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4) | 21 | (base + ((is64bit == 1) ? PCI_MSI_MASK_64 : PCI_MSI_MASK_32)) |
22 | #define msi_disable(control) control &= ~PCI_MSI_FLAGS_ENABLE | ||
23 | #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT)) | 22 | #define is_64bit_address(control) (!!(control & PCI_MSI_FLAGS_64BIT)) |
24 | #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT)) | 23 | #define is_mask_bit_support(control) (!!(control & PCI_MSI_FLAGS_MASKBIT)) |
25 | 24 | ||
26 | #define msix_table_offset_reg(base) (base + 0x04) | 25 | #define msix_table_offset_reg(base) (base + 0x04) |
27 | #define msix_pba_offset_reg(base) (base + 0x08) | 26 | #define msix_pba_offset_reg(base) (base + 0x08) |
28 | #define msix_enable(control) control |= PCI_MSIX_FLAGS_ENABLE | ||
29 | #define msix_disable(control) control &= ~PCI_MSIX_FLAGS_ENABLE | ||
30 | #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1) | 27 | #define msix_table_size(control) ((control & PCI_MSIX_FLAGS_QSIZE)+1) |
31 | #define multi_msix_capable msix_table_size | 28 | #define multi_msix_capable(control) msix_table_size((control)) |
32 | #define msix_unmask(address) (address & ~PCI_MSIX_FLAGS_BITMASK) | ||
33 | #define msix_mask(address) (address | PCI_MSIX_FLAGS_BITMASK) | ||
34 | #define msix_is_pending(address) (address & PCI_MSIX_FLAGS_PENDMASK) | ||
35 | 29 | ||
36 | #endif /* MSI_H */ | 30 | #endif /* MSI_H */ |