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authorLinus Torvalds <torvalds@linux-foundation.org>2011-11-23 17:58:46 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2011-11-23 17:58:46 -0500
commit09521577ca7718b6c83f095ca4f0d474b01a8378 (patch)
tree56bbc5f0ac255f36a0935d3ba4e0a4702203dc66 /drivers/pci/hotplug
parentde7badf1adc7cc95269ac4b435da23c169018a3e (diff)
parent4cac2eb158c6da0c761689345c6cc5df788a6292 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci: PCI hotplug: shpchp: don't blindly claim non-AMD 0x7450 device IDs PCI: pciehp: wait 100 ms after Link Training check PCI: pciehp: wait 1000 ms before Link Training check PCI: pciehp: Retrieve link speed after link is trained PCI: Let PCI_PRI depend on PCI PCI: Fix compile errors with PCI_ATS and !PCI_IOV PCI / ACPI: Make acpiphp ignore root bridges using PCIe native hotplug
Diffstat (limited to 'drivers/pci/hotplug')
-rw-r--r--drivers/pci/hotplug/acpiphp_glue.c29
-rw-r--r--drivers/pci/hotplug/pciehp_ctrl.c3
-rw-r--r--drivers/pci/hotplug/pciehp_hpc.c27
-rw-r--r--drivers/pci/hotplug/shpchp_core.c4
-rw-r--r--drivers/pci/hotplug/shpchp_hpc.c4
5 files changed, 46 insertions, 21 deletions
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 596172b4ae95..fce1c54a0c8d 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -459,8 +459,17 @@ static int add_bridge(acpi_handle handle)
459{ 459{
460 acpi_status status; 460 acpi_status status;
461 unsigned long long tmp; 461 unsigned long long tmp;
462 struct acpi_pci_root *root;
462 acpi_handle dummy_handle; 463 acpi_handle dummy_handle;
463 464
465 /*
466 * We shouldn't use this bridge if PCIe native hotplug control has been
467 * granted by the BIOS for it.
468 */
469 root = acpi_pci_find_root(handle);
470 if (root && (root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
471 return -ENODEV;
472
464 /* if the bridge doesn't have _STA, we assume it is always there */ 473 /* if the bridge doesn't have _STA, we assume it is always there */
465 status = acpi_get_handle(handle, "_STA", &dummy_handle); 474 status = acpi_get_handle(handle, "_STA", &dummy_handle);
466 if (ACPI_SUCCESS(status)) { 475 if (ACPI_SUCCESS(status)) {
@@ -1376,13 +1385,23 @@ static void handle_hotplug_event_func(acpi_handle handle, u32 type,
1376static acpi_status 1385static acpi_status
1377find_root_bridges(acpi_handle handle, u32 lvl, void *context, void **rv) 1386find_root_bridges(acpi_handle handle, u32 lvl, void *context, void **rv)
1378{ 1387{
1388 struct acpi_pci_root *root;
1379 int *count = (int *)context; 1389 int *count = (int *)context;
1380 1390
1381 if (acpi_is_root_bridge(handle)) { 1391 if (!acpi_is_root_bridge(handle))
1382 acpi_install_notify_handler(handle, ACPI_SYSTEM_NOTIFY, 1392 return AE_OK;
1383 handle_hotplug_event_bridge, NULL); 1393
1384 (*count)++; 1394 root = acpi_pci_find_root(handle);
1385 } 1395 if (!root)
1396 return AE_OK;
1397
1398 if (root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL)
1399 return AE_OK;
1400
1401 (*count)++;
1402 acpi_install_notify_handler(handle, ACPI_SYSTEM_NOTIFY,
1403 handle_hotplug_event_bridge, NULL);
1404
1386 return AE_OK ; 1405 return AE_OK ;
1387} 1406}
1388 1407
diff --git a/drivers/pci/hotplug/pciehp_ctrl.c b/drivers/pci/hotplug/pciehp_ctrl.c
index 1e9c9aacc3a6..085dbb5fc168 100644
--- a/drivers/pci/hotplug/pciehp_ctrl.c
+++ b/drivers/pci/hotplug/pciehp_ctrl.c
@@ -213,9 +213,6 @@ static int board_added(struct slot *p_slot)
213 goto err_exit; 213 goto err_exit;
214 } 214 }
215 215
216 /* Wait for 1 second after checking link training status */
217 msleep(1000);
218
219 /* Check for a power fault */ 216 /* Check for a power fault */
220 if (ctrl->power_fault_detected || pciehp_query_power_fault(p_slot)) { 217 if (ctrl->power_fault_detected || pciehp_query_power_fault(p_slot)) {
221 ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot)); 218 ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot));
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c
index 96dc4734e4af..7b1414810ae3 100644
--- a/drivers/pci/hotplug/pciehp_hpc.c
+++ b/drivers/pci/hotplug/pciehp_hpc.c
@@ -280,6 +280,14 @@ int pciehp_check_link_status(struct controller *ctrl)
280 else 280 else
281 msleep(1000); 281 msleep(1000);
282 282
283 /*
284 * Need to wait for 1000 ms after Data Link Layer Link Active
285 * (DLLLA) bit reads 1b before sending configuration request.
286 * We need it before checking Link Training (LT) bit becuase
287 * LT is still set even after DLLLA bit is set on some platform.
288 */
289 msleep(1000);
290
283 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); 291 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
284 if (retval) { 292 if (retval) {
285 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); 293 ctrl_err(ctrl, "Cannot read LNKSTATUS register\n");
@@ -294,6 +302,16 @@ int pciehp_check_link_status(struct controller *ctrl)
294 return retval; 302 return retval;
295 } 303 }
296 304
305 /*
306 * If the port supports Link speeds greater than 5.0 GT/s, we
307 * must wait for 100 ms after Link training completes before
308 * sending configuration request.
309 */
310 if (ctrl->pcie->port->subordinate->max_bus_speed > PCIE_SPEED_5_0GT)
311 msleep(100);
312
313 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
314
297 return retval; 315 return retval;
298} 316}
299 317
@@ -484,7 +502,6 @@ int pciehp_power_on_slot(struct slot * slot)
484 u16 slot_cmd; 502 u16 slot_cmd;
485 u16 cmd_mask; 503 u16 cmd_mask;
486 u16 slot_status; 504 u16 slot_status;
487 u16 lnk_status;
488 int retval = 0; 505 int retval = 0;
489 506
490 /* Clear sticky power-fault bit from previous power failures */ 507 /* Clear sticky power-fault bit from previous power failures */
@@ -516,14 +533,6 @@ int pciehp_power_on_slot(struct slot * slot)
516 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__, 533 ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
517 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd); 534 pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
518 535
519 retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
520 if (retval) {
521 ctrl_err(ctrl, "%s: Cannot read LNKSTA register\n",
522 __func__);
523 return retval;
524 }
525 pcie_update_link_speed(ctrl->pcie->port->subordinate, lnk_status);
526
527 return retval; 536 return retval;
528} 537}
529 538
diff --git a/drivers/pci/hotplug/shpchp_core.c b/drivers/pci/hotplug/shpchp_core.c
index aca972bbfb4c..dd7e0c51a33e 100644
--- a/drivers/pci/hotplug/shpchp_core.c
+++ b/drivers/pci/hotplug/shpchp_core.c
@@ -278,8 +278,8 @@ static int get_adapter_status (struct hotplug_slot *hotplug_slot, u8 *value)
278 278
279static int is_shpc_capable(struct pci_dev *dev) 279static int is_shpc_capable(struct pci_dev *dev)
280{ 280{
281 if ((dev->vendor == PCI_VENDOR_ID_AMD) || (dev->device == 281 if (dev->vendor == PCI_VENDOR_ID_AMD &&
282 PCI_DEVICE_ID_AMD_GOLAM_7450)) 282 dev->device == PCI_DEVICE_ID_AMD_GOLAM_7450)
283 return 1; 283 return 1;
284 if (!pci_find_capability(dev, PCI_CAP_ID_SHPC)) 284 if (!pci_find_capability(dev, PCI_CAP_ID_SHPC))
285 return 0; 285 return 0;
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index 36547f0ce305..75ba2311b54f 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -944,8 +944,8 @@ int shpc_init(struct controller *ctrl, struct pci_dev *pdev)
944 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */ 944 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
945 ctrl_dbg(ctrl, "Hotplug Controller:\n"); 945 ctrl_dbg(ctrl, "Hotplug Controller:\n");
946 946
947 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device == 947 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
948 PCI_DEVICE_ID_AMD_GOLAM_7450)) { 948 pdev->device == PCI_DEVICE_ID_AMD_GOLAM_7450) {
949 /* amd shpc driver doesn't use Base Offset; assume 0 */ 949 /* amd shpc driver doesn't use Base Offset; assume 0 */
950 ctrl->mmio_base = pci_resource_start(pdev, 0); 950 ctrl->mmio_base = pci_resource_start(pdev, 0);
951 ctrl->mmio_size = pci_resource_len(pdev, 0); 951 ctrl->mmio_size = pci_resource_len(pdev, 0);