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authorKenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>2006-03-01 00:55:11 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2006-03-23 17:35:16 -0500
commit0afabe906539b4e8b9e895f19ea31aabdf12f30b (patch)
treeaecea8cc15db5255018217f7247f5a521ed2a208 /drivers/pci/hotplug/shpchp_hpc.c
parent3c990e9219ea0b0aee588473ce6c8a66cdee3ff5 (diff)
[PATCH] shpchp: cleanup bus speed handling
The code related to handling bus speed in SHPCHP driver is unnecessarily complex. This patch cleans up and simplify that. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers/pci/hotplug/shpchp_hpc.c')
-rw-r--r--drivers/pci/hotplug/shpchp_hpc.c466
1 files changed, 153 insertions, 313 deletions
diff --git a/drivers/pci/hotplug/shpchp_hpc.c b/drivers/pci/hotplug/shpchp_hpc.c
index b392606a905a..66123cf4deaa 100644
--- a/drivers/pci/hotplug/shpchp_hpc.c
+++ b/drivers/pci/hotplug/shpchp_hpc.c
@@ -82,31 +82,6 @@
82#define SLOT_100MHZ_PCIX_533 0x0f000000 82#define SLOT_100MHZ_PCIX_533 0x0f000000
83#define SLOT_133MHZ_PCIX_533 0xf0000000 83#define SLOT_133MHZ_PCIX_533 0xf0000000
84 84
85
86/* Secondary Bus Configuration Register */
87/* For PI = 1, Bits 0 to 2 have been encoded as follows to show current bus speed/mode */
88#define PCI_33MHZ 0x0
89#define PCI_66MHZ 0x1
90#define PCIX_66MHZ 0x2
91#define PCIX_100MHZ 0x3
92#define PCIX_133MHZ 0x4
93
94/* For PI = 2, Bits 0 to 3 have been encoded as follows to show current bus speed/mode */
95#define PCI_33MHZ 0x0
96#define PCI_66MHZ 0x1
97#define PCIX_66MHZ 0x2
98#define PCIX_100MHZ 0x3
99#define PCIX_133MHZ 0x4
100#define PCIX_66MHZ_ECC 0x5
101#define PCIX_100MHZ_ECC 0x6
102#define PCIX_133MHZ_ECC 0x7
103#define PCIX_66MHZ_266 0x9
104#define PCIX_100MHZ_266 0xa
105#define PCIX_133MHZ_266 0xb
106#define PCIX_66MHZ_533 0x11
107#define PCIX_100MHZ_533 0x12
108#define PCIX_133MHZ_533 0x13
109
110/* Slot Configuration */ 85/* Slot Configuration */
111#define SLOT_NUM 0x0000001F 86#define SLOT_NUM 0x0000001F
112#define FIRST_DEV_NUM 0x00001F00 87#define FIRST_DEV_NUM 0x00001F00
@@ -548,81 +523,41 @@ static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
548 523
549static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value) 524static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
550{ 525{
551 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
552 u32 slot_reg;
553 u16 slot_status, sec_bus_status;
554 u8 m66_cap, pcix_cap, pi;
555 int retval = 0; 526 int retval = 0;
527 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
528 u32 slot_reg = readl(php_ctlr->creg + SLOT1 + 4 * slot->hp_slot);
529 u8 pcix_cap = (slot_reg >> 12) & 7;
530 u8 m66_cap = (slot_reg >> 9) & 1;
556 531
557 DBG_ENTER_ROUTINE 532 DBG_ENTER_ROUTINE
558 533
559 if (!slot->ctrl->hpc_ctlr_handle) { 534 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
560 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 535 __FUNCTION__, slot_reg, pcix_cap, m66_cap);
561 return -1;
562 }
563
564 if (slot->hp_slot >= php_ctlr->num_slots) {
565 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
566 return -1;
567 }
568
569 pi = readb(php_ctlr->creg + PROG_INTERFACE);
570 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
571 dbg("%s: pi = %d, slot_reg = %x\n", __FUNCTION__, pi, slot_reg);
572 slot_status = (u16) slot_reg;
573 dbg("%s: slot_status = %x\n", __FUNCTION__, slot_status);
574 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
575
576 pcix_cap = (u8) ((slot_status & 0x3000) >> 12);
577 dbg("%s: pcix_cap = %x\n", __FUNCTION__, pcix_cap);
578 m66_cap = (u8) ((slot_status & 0x0200) >> 9);
579 dbg("%s: m66_cap = %x\n", __FUNCTION__, m66_cap);
580 536
581 537 switch (pcix_cap) {
582 if (pi == 2) { 538 case 0x0:
583 switch (pcix_cap) { 539 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
584 case 0: 540 break;
585 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz; 541 case 0x1:
586 break; 542 *value = PCI_SPEED_66MHz_PCIX;
587 case 1: 543 break;
588 *value = PCI_SPEED_66MHz_PCIX; 544 case 0x3:
589 break; 545 *value = PCI_SPEED_133MHz_PCIX;
590 case 3: 546 break;
591 *value = PCI_SPEED_133MHz_PCIX; 547 case 0x4:
592 break; 548 *value = PCI_SPEED_133MHz_PCIX_266;
593 case 4: 549 break;
594 *value = PCI_SPEED_133MHz_PCIX_266; 550 case 0x5:
595 break; 551 *value = PCI_SPEED_133MHz_PCIX_533;
596 case 5: 552 break;
597 *value = PCI_SPEED_133MHz_PCIX_533; 553 case 0x2:
598 break; 554 default:
599 case 2: /* Reserved */ 555 *value = PCI_SPEED_UNKNOWN;
600 default: 556 retval = -ENODEV;
601 *value = PCI_SPEED_UNKNOWN; 557 break;
602 retval = -ENODEV;
603 break;
604 }
605 } else {
606 switch (pcix_cap) {
607 case 0:
608 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
609 break;
610 case 1:
611 *value = PCI_SPEED_66MHz_PCIX;
612 break;
613 case 3:
614 *value = PCI_SPEED_133MHz_PCIX;
615 break;
616 case 2: /* Reserved */
617 default:
618 *value = PCI_SPEED_UNKNOWN;
619 retval = -ENODEV;
620 break;
621 }
622 } 558 }
623 559
624 dbg("Adapter speed = %d\n", *value); 560 dbg("Adapter speed = %d\n", *value);
625
626 DBG_LEAVE_ROUTINE 561 DBG_LEAVE_ROUTINE
627 return retval; 562 return retval;
628} 563}
@@ -965,98 +900,66 @@ static int hpc_slot_disable(struct slot * slot)
965 900
966static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value) 901static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
967{ 902{
968 u8 slot_cmd; 903 int retval;
969 u8 pi;
970 int retval = 0;
971 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 904 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
905 u8 pi, cmd;
972 906
973 DBG_ENTER_ROUTINE 907 DBG_ENTER_ROUTINE
974
975 if (!slot->ctrl->hpc_ctlr_handle) {
976 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
977 return -1;
978 }
979 908
980 pi = readb(php_ctlr->creg + PROG_INTERFACE); 909 pi = readb(php_ctlr->creg + PROG_INTERFACE);
981 910 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
982 if (pi == 1) { 911 return -EINVAL;
983 switch (value) {
984 case 0:
985 slot_cmd = SETA_PCI_33MHZ;
986 break;
987 case 1:
988 slot_cmd = SETA_PCI_66MHZ;
989 break;
990 case 2:
991 slot_cmd = SETA_PCIX_66MHZ;
992 break;
993 case 3:
994 slot_cmd = SETA_PCIX_100MHZ;
995 break;
996 case 4:
997 slot_cmd = SETA_PCIX_133MHZ;
998 break;
999 default:
1000 slot_cmd = PCI_SPEED_UNKNOWN;
1001 retval = -ENODEV;
1002 return retval;
1003 }
1004 } else {
1005 switch (value) {
1006 case 0:
1007 slot_cmd = SETB_PCI_33MHZ;
1008 break;
1009 case 1:
1010 slot_cmd = SETB_PCI_66MHZ;
1011 break;
1012 case 2:
1013 slot_cmd = SETB_PCIX_66MHZ_PM;
1014 break;
1015 case 3:
1016 slot_cmd = SETB_PCIX_100MHZ_PM;
1017 break;
1018 case 4:
1019 slot_cmd = SETB_PCIX_133MHZ_PM;
1020 break;
1021 case 5:
1022 slot_cmd = SETB_PCIX_66MHZ_EM;
1023 break;
1024 case 6:
1025 slot_cmd = SETB_PCIX_100MHZ_EM;
1026 break;
1027 case 7:
1028 slot_cmd = SETB_PCIX_133MHZ_EM;
1029 break;
1030 case 8:
1031 slot_cmd = SETB_PCIX_66MHZ_266;
1032 break;
1033 case 0x9:
1034 slot_cmd = SETB_PCIX_100MHZ_266;
1035 break;
1036 case 0xa:
1037 slot_cmd = SETB_PCIX_133MHZ_266;
1038 break;
1039 case 0xb:
1040 slot_cmd = SETB_PCIX_66MHZ_533;
1041 break;
1042 case 0xc:
1043 slot_cmd = SETB_PCIX_100MHZ_533;
1044 break;
1045 case 0xd:
1046 slot_cmd = SETB_PCIX_133MHZ_533;
1047 break;
1048 default:
1049 slot_cmd = PCI_SPEED_UNKNOWN;
1050 retval = -ENODEV;
1051 return retval;
1052 }
1053 912
913 switch (value) {
914 case PCI_SPEED_33MHz:
915 cmd = SETA_PCI_33MHZ;
916 break;
917 case PCI_SPEED_66MHz:
918 cmd = SETA_PCI_66MHZ;
919 break;
920 case PCI_SPEED_66MHz_PCIX:
921 cmd = SETA_PCIX_66MHZ;
922 break;
923 case PCI_SPEED_100MHz_PCIX:
924 cmd = SETA_PCIX_100MHZ;
925 break;
926 case PCI_SPEED_133MHz_PCIX:
927 cmd = SETA_PCIX_133MHZ;
928 break;
929 case PCI_SPEED_66MHz_PCIX_ECC:
930 cmd = SETB_PCIX_66MHZ_EM;
931 break;
932 case PCI_SPEED_100MHz_PCIX_ECC:
933 cmd = SETB_PCIX_100MHZ_EM;
934 break;
935 case PCI_SPEED_133MHz_PCIX_ECC:
936 cmd = SETB_PCIX_133MHZ_EM;
937 break;
938 case PCI_SPEED_66MHz_PCIX_266:
939 cmd = SETB_PCIX_66MHZ_266;
940 break;
941 case PCI_SPEED_100MHz_PCIX_266:
942 cmd = SETB_PCIX_100MHZ_266;
943 break;
944 case PCI_SPEED_133MHz_PCIX_266:
945 cmd = SETB_PCIX_133MHZ_266;
946 break;
947 case PCI_SPEED_66MHz_PCIX_533:
948 cmd = SETB_PCIX_66MHZ_533;
949 break;
950 case PCI_SPEED_100MHz_PCIX_533:
951 cmd = SETB_PCIX_100MHZ_533;
952 break;
953 case PCI_SPEED_133MHz_PCIX_533:
954 cmd = SETB_PCIX_133MHZ_533;
955 break;
956 default:
957 return -EINVAL;
1054 } 958 }
1055 retval = shpc_write_cmd(slot, 0, slot_cmd); 959
1056 if (retval) { 960 retval = shpc_write_cmd(slot, 0, cmd);
961 if (retval)
1057 err("%s: Write command failed!\n", __FUNCTION__); 962 err("%s: Write command failed!\n", __FUNCTION__);
1058 return -1;
1059 }
1060 963
1061 DBG_LEAVE_ROUTINE 964 DBG_LEAVE_ROUTINE
1062 return retval; 965 return retval;
@@ -1163,64 +1066,43 @@ static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1163 1066
1164static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value) 1067static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1165{ 1068{
1069 int retval = 0;
1166 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 1070 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1167 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 1071 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1168 int retval = 0; 1072 u8 pi = readb(php_ctlr->creg + PROG_INTERFACE);
1169 u8 pi; 1073 u32 slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1);
1170 u32 slot_avail1, slot_avail2; 1074 u32 slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);
1171 1075
1172 DBG_ENTER_ROUTINE 1076 DBG_ENTER_ROUTINE
1173 1077
1174 if (!slot->ctrl->hpc_ctlr_handle) {
1175 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1176 return -1;
1177 }
1178
1179 if (slot->hp_slot >= php_ctlr->num_slots) {
1180 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1181 return -1;
1182 }
1183
1184 pi = readb(php_ctlr->creg + PROG_INTERFACE);
1185 slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1);
1186 slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);
1187
1188 if (pi == 2) { 1078 if (pi == 2) {
1189 if (slot_avail2 & SLOT_133MHZ_PCIX_533) 1079 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
1190 bus_speed = PCIX_133MHZ_533; 1080 bus_speed = PCI_SPEED_133MHz_PCIX_533;
1191 else if (slot_avail2 & SLOT_100MHZ_PCIX_533) 1081 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
1192 bus_speed = PCIX_100MHZ_533; 1082 bus_speed = PCI_SPEED_100MHz_PCIX_533;
1193 else if (slot_avail2 & SLOT_66MHZ_PCIX_533) 1083 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
1194 bus_speed = PCIX_66MHZ_533; 1084 bus_speed = PCI_SPEED_66MHz_PCIX_533;
1195 else if (slot_avail2 & SLOT_133MHZ_PCIX_266) 1085 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
1196 bus_speed = PCIX_133MHZ_266; 1086 bus_speed = PCI_SPEED_133MHz_PCIX_266;
1197 else if (slot_avail2 & SLOT_100MHZ_PCIX_266) 1087 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
1198 bus_speed = PCIX_100MHZ_266; 1088 bus_speed = PCI_SPEED_100MHz_PCIX_266;
1199 else if (slot_avail2 & SLOT_66MHZ_PCIX_266) 1089 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
1200 bus_speed = PCIX_66MHZ_266; 1090 bus_speed = PCI_SPEED_66MHz_PCIX_266;
1201 else if (slot_avail1 & SLOT_133MHZ_PCIX) 1091 }
1202 bus_speed = PCIX_133MHZ; 1092
1203 else if (slot_avail1 & SLOT_100MHZ_PCIX) 1093 if (bus_speed == PCI_SPEED_UNKNOWN) {
1204 bus_speed = PCIX_100MHZ;
1205 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1206 bus_speed = PCIX_66MHZ;
1207 else if (slot_avail2 & SLOT_66MHZ)
1208 bus_speed = PCI_66MHZ;
1209 else if (slot_avail1 & SLOT_33MHZ)
1210 bus_speed = PCI_33MHZ;
1211 else bus_speed = PCI_SPEED_UNKNOWN;
1212 } else {
1213 if (slot_avail1 & SLOT_133MHZ_PCIX) 1094 if (slot_avail1 & SLOT_133MHZ_PCIX)
1214 bus_speed = PCIX_133MHZ; 1095 bus_speed = PCI_SPEED_133MHz_PCIX;
1215 else if (slot_avail1 & SLOT_100MHZ_PCIX) 1096 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1216 bus_speed = PCIX_100MHZ; 1097 bus_speed = PCI_SPEED_100MHz_PCIX;
1217 else if (slot_avail1 & SLOT_66MHZ_PCIX) 1098 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1218 bus_speed = PCIX_66MHZ; 1099 bus_speed = PCI_SPEED_66MHz_PCIX;
1219 else if (slot_avail2 & SLOT_66MHZ) 1100 else if (slot_avail2 & SLOT_66MHZ)
1220 bus_speed = PCI_66MHZ; 1101 bus_speed = PCI_SPEED_66MHz;
1221 else if (slot_avail1 & SLOT_33MHZ) 1102 else if (slot_avail1 & SLOT_33MHZ)
1222 bus_speed = PCI_33MHZ; 1103 bus_speed = PCI_SPEED_33MHz;
1223 else bus_speed = PCI_SPEED_UNKNOWN; 1104 else
1105 retval = -ENODEV;
1224 } 1106 }
1225 1107
1226 *value = bus_speed; 1108 *value = bus_speed;
@@ -1231,111 +1113,69 @@ static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1231 1113
1232static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value) 1114static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1233{ 1115{
1116 int retval = 0;
1234 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle; 1117 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
1235 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN; 1118 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1236 u16 sec_bus_status; 1119 u16 sec_bus_reg = readw(php_ctlr->creg + SEC_BUS_CONFIG);
1237 int retval = 0; 1120 u8 pi = readb(php_ctlr->creg + PROG_INTERFACE);
1238 u8 pi; 1121 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
1239 1122
1240 DBG_ENTER_ROUTINE 1123 DBG_ENTER_ROUTINE
1241 1124
1242 if (!slot->ctrl->hpc_ctlr_handle) { 1125 if ((pi == 1) && (speed_mode > 4)) {
1243 err("%s: Invalid HPC controller handle!\n", __FUNCTION__); 1126 *value = PCI_SPEED_UNKNOWN;
1244 return -1; 1127 return -ENODEV;
1245 }
1246
1247 if (slot->hp_slot >= php_ctlr->num_slots) {
1248 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1249 return -1;
1250 } 1128 }
1251 1129
1252 pi = readb(php_ctlr->creg + PROG_INTERFACE); 1130 switch (speed_mode) {
1253 sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG); 1131 case 0x0:
1254 1132 *value = PCI_SPEED_33MHz;
1255 if (pi == 2) { 1133 break;
1256 switch (sec_bus_status & 0x000f) { 1134 case 0x1:
1257 case 0: 1135 *value = PCI_SPEED_66MHz;
1258 bus_speed = PCI_SPEED_33MHz; 1136 break;
1259 break; 1137 case 0x2:
1260 case 1: 1138 *value = PCI_SPEED_66MHz_PCIX;
1261 bus_speed = PCI_SPEED_66MHz; 1139 break;
1262 break; 1140 case 0x3:
1263 case 2: 1141 *value = PCI_SPEED_100MHz_PCIX;
1264 bus_speed = PCI_SPEED_66MHz_PCIX; 1142 break;
1265 break; 1143 case 0x4:
1266 case 3: 1144 *value = PCI_SPEED_133MHz_PCIX;
1267 bus_speed = PCI_SPEED_100MHz_PCIX; 1145 break;
1268 break; 1146 case 0x5:
1269 case 4: 1147 *value = PCI_SPEED_66MHz_PCIX_ECC;
1270 bus_speed = PCI_SPEED_133MHz_PCIX; 1148 break;
1271 break; 1149 case 0x6:
1272 case 5: 1150 *value = PCI_SPEED_100MHz_PCIX_ECC;
1273 bus_speed = PCI_SPEED_66MHz_PCIX_ECC; 1151 break;
1274 break; 1152 case 0x7:
1275 case 6: 1153 *value = PCI_SPEED_133MHz_PCIX_ECC;
1276 bus_speed = PCI_SPEED_100MHz_PCIX_ECC; 1154 break;
1277 break; 1155 case 0x8:
1278 case 7: 1156 *value = PCI_SPEED_66MHz_PCIX_266;
1279 bus_speed = PCI_SPEED_133MHz_PCIX_ECC; 1157 break;
1280 break; 1158 case 0x9:
1281 case 8: 1159 *value = PCI_SPEED_100MHz_PCIX_266;
1282 bus_speed = PCI_SPEED_66MHz_PCIX_266; 1160 break;
1283 break; 1161 case 0xa:
1284 case 9: 1162 *value = PCI_SPEED_133MHz_PCIX_266;
1285 bus_speed = PCI_SPEED_100MHz_PCIX_266; 1163 break;
1286 break; 1164 case 0xb:
1287 case 0xa: 1165 *value = PCI_SPEED_66MHz_PCIX_533;
1288 bus_speed = PCI_SPEED_133MHz_PCIX_266; 1166 break;
1289 break; 1167 case 0xc:
1290 case 0xb: 1168 *value = PCI_SPEED_100MHz_PCIX_533;
1291 bus_speed = PCI_SPEED_66MHz_PCIX_533; 1169 break;
1292 break; 1170 case 0xd:
1293 case 0xc: 1171 *value = PCI_SPEED_133MHz_PCIX_533;
1294 bus_speed = PCI_SPEED_100MHz_PCIX_533; 1172 break;
1295 break; 1173 default:
1296 case 0xd: 1174 *value = PCI_SPEED_UNKNOWN;
1297 bus_speed = PCI_SPEED_133MHz_PCIX_533; 1175 retval = -ENODEV;
1298 break; 1176 break;
1299 case 0xe:
1300 case 0xf:
1301 default:
1302 bus_speed = PCI_SPEED_UNKNOWN;
1303 break;
1304 }
1305 } else {
1306 /* In the case where pi is undefined, default it to 1 */
1307 switch (sec_bus_status & 0x0007) {
1308 case 0:
1309 bus_speed = PCI_SPEED_33MHz;
1310 break;
1311 case 1:
1312 bus_speed = PCI_SPEED_66MHz;
1313 break;
1314 case 2:
1315 bus_speed = PCI_SPEED_66MHz_PCIX;
1316 break;
1317 case 3:
1318 bus_speed = PCI_SPEED_100MHz_PCIX;
1319 break;
1320 case 4:
1321 bus_speed = PCI_SPEED_133MHz_PCIX;
1322 break;
1323 case 5:
1324 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1325 break;
1326 case 6:
1327 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1328 break;
1329 case 7:
1330 bus_speed = PCI_SPEED_UNKNOWN; /* Reserved */
1331 break;
1332 default:
1333 bus_speed = PCI_SPEED_UNKNOWN;
1334 break;
1335 }
1336 } 1177 }
1337 1178
1338 *value = bus_speed;
1339 dbg("Current bus speed = %d\n", bus_speed); 1179 dbg("Current bus speed = %d\n", bus_speed);
1340 DBG_LEAVE_ROUTINE 1180 DBG_LEAVE_ROUTINE
1341 return retval; 1181 return retval;
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-28 23:40:55 -0400