diff options
author | Bjorn Helgaas <bhelgaas@google.com> | 2013-05-09 13:26:16 -0400 |
---|---|---|
committer | Bjorn Helgaas <bhelgaas@google.com> | 2013-12-14 15:05:58 -0500 |
commit | cd84d34074f56595fbae7a70f8a85b7d089249d1 (patch) | |
tree | f0d6049eadd63ac018cf6973fa9314baf4c2c1b7 /drivers/pci/hotplug/pciehp_hpc.c | |
parent | 6ce4eac1f600b34f2f7f58f9cd8f0503d79e42ae (diff) |
PCI: pciehp: Drop pciehp_readw()/pciehp_writew() wrappers
The pciehp_readw() and pciehp_writew() wrappers only look up the pci_dev
and call the PCIe Capability accessors, so we can make things a little
more straightforward by just using the PCIe Capability accessors directly.
No functional change.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'drivers/pci/hotplug/pciehp_hpc.c')
-rw-r--r-- | drivers/pci/hotplug/pciehp_hpc.c | 95 |
1 files changed, 48 insertions, 47 deletions
diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 3eea3fdd4b0b..53bb5501d199 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c | |||
@@ -41,28 +41,9 @@ | |||
41 | #include "../pci.h" | 41 | #include "../pci.h" |
42 | #include "pciehp.h" | 42 | #include "pciehp.h" |
43 | 43 | ||
44 | static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value) | 44 | static inline struct pci_dev *ctrl_dev(struct controller *ctrl) |
45 | { | 45 | { |
46 | struct pci_dev *dev = ctrl->pcie->port; | 46 | return ctrl->pcie->port; |
47 | return pcie_capability_read_word(dev, reg, value); | ||
48 | } | ||
49 | |||
50 | static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value) | ||
51 | { | ||
52 | struct pci_dev *dev = ctrl->pcie->port; | ||
53 | return pcie_capability_read_dword(dev, reg, value); | ||
54 | } | ||
55 | |||
56 | static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value) | ||
57 | { | ||
58 | struct pci_dev *dev = ctrl->pcie->port; | ||
59 | return pcie_capability_write_word(dev, reg, value); | ||
60 | } | ||
61 | |||
62 | static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value) | ||
63 | { | ||
64 | struct pci_dev *dev = ctrl->pcie->port; | ||
65 | return pcie_capability_write_dword(dev, reg, value); | ||
66 | } | 47 | } |
67 | 48 | ||
68 | /* Power Control Command */ | 49 | /* Power Control Command */ |
@@ -129,20 +110,24 @@ static inline void pciehp_free_irq(struct controller *ctrl) | |||
129 | 110 | ||
130 | static int pcie_poll_cmd(struct controller *ctrl) | 111 | static int pcie_poll_cmd(struct controller *ctrl) |
131 | { | 112 | { |
113 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
132 | u16 slot_status; | 114 | u16 slot_status; |
133 | int err, timeout = 1000; | 115 | int err, timeout = 1000; |
134 | 116 | ||
135 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); | 117 | err = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
136 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | 118 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { |
137 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | 119 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
120 | PCI_EXP_SLTSTA_CC); | ||
138 | return 1; | 121 | return 1; |
139 | } | 122 | } |
140 | while (timeout > 0) { | 123 | while (timeout > 0) { |
141 | msleep(10); | 124 | msleep(10); |
142 | timeout -= 10; | 125 | timeout -= 10; |
143 | err = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); | 126 | err = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, |
127 | &slot_status); | ||
144 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { | 128 | if (!err && (slot_status & PCI_EXP_SLTSTA_CC)) { |
145 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_CC); | 129 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
130 | PCI_EXP_SLTSTA_CC); | ||
146 | return 1; | 131 | return 1; |
147 | } | 132 | } |
148 | } | 133 | } |
@@ -171,13 +156,14 @@ static void pcie_wait_cmd(struct controller *ctrl, int poll) | |||
171 | */ | 156 | */ |
172 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) | 157 | static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) |
173 | { | 158 | { |
159 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
174 | int retval = 0; | 160 | int retval = 0; |
175 | u16 slot_status; | 161 | u16 slot_status; |
176 | u16 slot_ctrl; | 162 | u16 slot_ctrl; |
177 | 163 | ||
178 | mutex_lock(&ctrl->ctrl_lock); | 164 | mutex_lock(&ctrl->ctrl_lock); |
179 | 165 | ||
180 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); | 166 | retval = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
181 | if (retval) { | 167 | if (retval) { |
182 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", | 168 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
183 | __func__); | 169 | __func__); |
@@ -207,7 +193,7 @@ static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) | |||
207 | } | 193 | } |
208 | } | 194 | } |
209 | 195 | ||
210 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); | 196 | retval = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
211 | if (retval) { | 197 | if (retval) { |
212 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); | 198 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
213 | goto out; | 199 | goto out; |
@@ -217,7 +203,7 @@ static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) | |||
217 | slot_ctrl |= (cmd & mask); | 203 | slot_ctrl |= (cmd & mask); |
218 | ctrl->cmd_busy = 1; | 204 | ctrl->cmd_busy = 1; |
219 | smp_mb(); | 205 | smp_mb(); |
220 | retval = pciehp_writew(ctrl, PCI_EXP_SLTCTL, slot_ctrl); | 206 | retval = pcie_capability_write_word(pdev, PCI_EXP_SLTCTL, slot_ctrl); |
221 | if (retval) | 207 | if (retval) |
222 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); | 208 | ctrl_err(ctrl, "Cannot write to SLOTCTRL register\n"); |
223 | 209 | ||
@@ -243,10 +229,11 @@ static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask) | |||
243 | 229 | ||
244 | static bool check_link_active(struct controller *ctrl) | 230 | static bool check_link_active(struct controller *ctrl) |
245 | { | 231 | { |
232 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
246 | bool ret = false; | 233 | bool ret = false; |
247 | u16 lnk_status; | 234 | u16 lnk_status; |
248 | 235 | ||
249 | if (pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status)) | 236 | if (pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status)) |
250 | return ret; | 237 | return ret; |
251 | 238 | ||
252 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); | 239 | ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA); |
@@ -311,6 +298,7 @@ static bool pci_bus_check_dev(struct pci_bus *bus, int devfn) | |||
311 | 298 | ||
312 | int pciehp_check_link_status(struct controller *ctrl) | 299 | int pciehp_check_link_status(struct controller *ctrl) |
313 | { | 300 | { |
301 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
314 | u16 lnk_status; | 302 | u16 lnk_status; |
315 | int retval = 0; | 303 | int retval = 0; |
316 | bool found = false; | 304 | bool found = false; |
@@ -330,7 +318,7 @@ int pciehp_check_link_status(struct controller *ctrl) | |||
330 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, | 318 | found = pci_bus_check_dev(ctrl->pcie->port->subordinate, |
331 | PCI_DEVFN(0, 0)); | 319 | PCI_DEVFN(0, 0)); |
332 | 320 | ||
333 | retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status); | 321 | retval = pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status); |
334 | if (retval) { | 322 | if (retval) { |
335 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); | 323 | ctrl_err(ctrl, "Cannot read LNKSTATUS register\n"); |
336 | return retval; | 324 | return retval; |
@@ -354,10 +342,11 @@ int pciehp_check_link_status(struct controller *ctrl) | |||
354 | 342 | ||
355 | static int __pciehp_link_set(struct controller *ctrl, bool enable) | 343 | static int __pciehp_link_set(struct controller *ctrl, bool enable) |
356 | { | 344 | { |
345 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
357 | u16 lnk_ctrl; | 346 | u16 lnk_ctrl; |
358 | int retval = 0; | 347 | int retval = 0; |
359 | 348 | ||
360 | retval = pciehp_readw(ctrl, PCI_EXP_LNKCTL, &lnk_ctrl); | 349 | retval = pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); |
361 | if (retval) { | 350 | if (retval) { |
362 | ctrl_err(ctrl, "Cannot read LNKCTRL register\n"); | 351 | ctrl_err(ctrl, "Cannot read LNKCTRL register\n"); |
363 | return retval; | 352 | return retval; |
@@ -368,7 +357,7 @@ static int __pciehp_link_set(struct controller *ctrl, bool enable) | |||
368 | else | 357 | else |
369 | lnk_ctrl |= PCI_EXP_LNKCTL_LD; | 358 | lnk_ctrl |= PCI_EXP_LNKCTL_LD; |
370 | 359 | ||
371 | retval = pciehp_writew(ctrl, PCI_EXP_LNKCTL, lnk_ctrl); | 360 | retval = pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); |
372 | if (retval) { | 361 | if (retval) { |
373 | ctrl_err(ctrl, "Cannot write LNKCTRL register\n"); | 362 | ctrl_err(ctrl, "Cannot write LNKCTRL register\n"); |
374 | return retval; | 363 | return retval; |
@@ -391,11 +380,12 @@ static int pciehp_link_disable(struct controller *ctrl) | |||
391 | int pciehp_get_attention_status(struct slot *slot, u8 *status) | 380 | int pciehp_get_attention_status(struct slot *slot, u8 *status) |
392 | { | 381 | { |
393 | struct controller *ctrl = slot->ctrl; | 382 | struct controller *ctrl = slot->ctrl; |
383 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
394 | u16 slot_ctrl; | 384 | u16 slot_ctrl; |
395 | u8 atten_led_state; | 385 | u8 atten_led_state; |
396 | int retval = 0; | 386 | int retval = 0; |
397 | 387 | ||
398 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); | 388 | retval = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
399 | if (retval) { | 389 | if (retval) { |
400 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); | 390 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
401 | return retval; | 391 | return retval; |
@@ -430,11 +420,12 @@ int pciehp_get_attention_status(struct slot *slot, u8 *status) | |||
430 | int pciehp_get_power_status(struct slot *slot, u8 *status) | 420 | int pciehp_get_power_status(struct slot *slot, u8 *status) |
431 | { | 421 | { |
432 | struct controller *ctrl = slot->ctrl; | 422 | struct controller *ctrl = slot->ctrl; |
423 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
433 | u16 slot_ctrl; | 424 | u16 slot_ctrl; |
434 | u8 pwr_state; | 425 | u8 pwr_state; |
435 | int retval = 0; | 426 | int retval = 0; |
436 | 427 | ||
437 | retval = pciehp_readw(ctrl, PCI_EXP_SLTCTL, &slot_ctrl); | 428 | retval = pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl); |
438 | if (retval) { | 429 | if (retval) { |
439 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); | 430 | ctrl_err(ctrl, "%s: Cannot read SLOTCTRL register\n", __func__); |
440 | return retval; | 431 | return retval; |
@@ -462,10 +453,11 @@ int pciehp_get_power_status(struct slot *slot, u8 *status) | |||
462 | int pciehp_get_latch_status(struct slot *slot, u8 *status) | 453 | int pciehp_get_latch_status(struct slot *slot, u8 *status) |
463 | { | 454 | { |
464 | struct controller *ctrl = slot->ctrl; | 455 | struct controller *ctrl = slot->ctrl; |
456 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
465 | u16 slot_status; | 457 | u16 slot_status; |
466 | int retval; | 458 | int retval; |
467 | 459 | ||
468 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); | 460 | retval = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
469 | if (retval) { | 461 | if (retval) { |
470 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", | 462 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
471 | __func__); | 463 | __func__); |
@@ -478,10 +470,11 @@ int pciehp_get_latch_status(struct slot *slot, u8 *status) | |||
478 | int pciehp_get_adapter_status(struct slot *slot, u8 *status) | 470 | int pciehp_get_adapter_status(struct slot *slot, u8 *status) |
479 | { | 471 | { |
480 | struct controller *ctrl = slot->ctrl; | 472 | struct controller *ctrl = slot->ctrl; |
473 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
481 | u16 slot_status; | 474 | u16 slot_status; |
482 | int retval; | 475 | int retval; |
483 | 476 | ||
484 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); | 477 | retval = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
485 | if (retval) { | 478 | if (retval) { |
486 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", | 479 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
487 | __func__); | 480 | __func__); |
@@ -494,10 +487,11 @@ int pciehp_get_adapter_status(struct slot *slot, u8 *status) | |||
494 | int pciehp_query_power_fault(struct slot *slot) | 487 | int pciehp_query_power_fault(struct slot *slot) |
495 | { | 488 | { |
496 | struct controller *ctrl = slot->ctrl; | 489 | struct controller *ctrl = slot->ctrl; |
490 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
497 | u16 slot_status; | 491 | u16 slot_status; |
498 | int retval; | 492 | int retval; |
499 | 493 | ||
500 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); | 494 | retval = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
501 | if (retval) { | 495 | if (retval) { |
502 | ctrl_err(ctrl, "Cannot check for power fault\n"); | 496 | ctrl_err(ctrl, "Cannot check for power fault\n"); |
503 | return retval; | 497 | return retval; |
@@ -572,13 +566,14 @@ void pciehp_green_led_blink(struct slot *slot) | |||
572 | int pciehp_power_on_slot(struct slot * slot) | 566 | int pciehp_power_on_slot(struct slot * slot) |
573 | { | 567 | { |
574 | struct controller *ctrl = slot->ctrl; | 568 | struct controller *ctrl = slot->ctrl; |
569 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
575 | u16 slot_cmd; | 570 | u16 slot_cmd; |
576 | u16 cmd_mask; | 571 | u16 cmd_mask; |
577 | u16 slot_status; | 572 | u16 slot_status; |
578 | int retval = 0; | 573 | int retval = 0; |
579 | 574 | ||
580 | /* Clear sticky power-fault bit from previous power failures */ | 575 | /* Clear sticky power-fault bit from previous power failures */ |
581 | retval = pciehp_readw(ctrl, PCI_EXP_SLTSTA, &slot_status); | 576 | retval = pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); |
582 | if (retval) { | 577 | if (retval) { |
583 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", | 578 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS register\n", |
584 | __func__); | 579 | __func__); |
@@ -586,7 +581,7 @@ int pciehp_power_on_slot(struct slot * slot) | |||
586 | } | 581 | } |
587 | slot_status &= PCI_EXP_SLTSTA_PFD; | 582 | slot_status &= PCI_EXP_SLTSTA_PFD; |
588 | if (slot_status) { | 583 | if (slot_status) { |
589 | retval = pciehp_writew(ctrl, PCI_EXP_SLTSTA, slot_status); | 584 | retval = pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, slot_status); |
590 | if (retval) { | 585 | if (retval) { |
591 | ctrl_err(ctrl, | 586 | ctrl_err(ctrl, |
592 | "%s: Cannot write to SLOTSTATUS register\n", | 587 | "%s: Cannot write to SLOTSTATUS register\n", |
@@ -643,6 +638,7 @@ int pciehp_power_off_slot(struct slot * slot) | |||
643 | static irqreturn_t pcie_isr(int irq, void *dev_id) | 638 | static irqreturn_t pcie_isr(int irq, void *dev_id) |
644 | { | 639 | { |
645 | struct controller *ctrl = (struct controller *)dev_id; | 640 | struct controller *ctrl = (struct controller *)dev_id; |
641 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
646 | struct slot *slot = ctrl->slot; | 642 | struct slot *slot = ctrl->slot; |
647 | u16 detected, intr_loc; | 643 | u16 detected, intr_loc; |
648 | 644 | ||
@@ -653,7 +649,8 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) | |||
653 | */ | 649 | */ |
654 | intr_loc = 0; | 650 | intr_loc = 0; |
655 | do { | 651 | do { |
656 | if (pciehp_readw(ctrl, PCI_EXP_SLTSTA, &detected)) { | 652 | if (pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, |
653 | &detected)) { | ||
657 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", | 654 | ctrl_err(ctrl, "%s: Cannot read SLOTSTATUS\n", |
658 | __func__); | 655 | __func__); |
659 | return IRQ_NONE; | 656 | return IRQ_NONE; |
@@ -666,7 +663,9 @@ static irqreturn_t pcie_isr(int irq, void *dev_id) | |||
666 | intr_loc |= detected; | 663 | intr_loc |= detected; |
667 | if (!intr_loc) | 664 | if (!intr_loc) |
668 | return IRQ_NONE; | 665 | return IRQ_NONE; |
669 | if (detected && pciehp_writew(ctrl, PCI_EXP_SLTSTA, intr_loc)) { | 666 | if (detected && |
667 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, | ||
668 | intr_loc)) { | ||
670 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", | 669 | ctrl_err(ctrl, "%s: Cannot write to SLOTSTATUS\n", |
671 | __func__); | 670 | __func__); |
672 | return IRQ_NONE; | 671 | return IRQ_NONE; |
@@ -758,6 +757,7 @@ static void pcie_disable_notification(struct controller *ctrl) | |||
758 | int pciehp_reset_slot(struct slot *slot, int probe) | 757 | int pciehp_reset_slot(struct slot *slot, int probe) |
759 | { | 758 | { |
760 | struct controller *ctrl = slot->ctrl; | 759 | struct controller *ctrl = slot->ctrl; |
760 | struct pci_dev *pdev = ctrl_dev(ctrl); | ||
761 | 761 | ||
762 | if (probe) | 762 | if (probe) |
763 | return 0; | 763 | return 0; |
@@ -771,7 +771,8 @@ int pciehp_reset_slot(struct slot *slot, int probe) | |||
771 | pci_reset_bridge_secondary_bus(ctrl->pcie->port); | 771 | pci_reset_bridge_secondary_bus(ctrl->pcie->port); |
772 | 772 | ||
773 | if (HP_SUPR_RM(ctrl)) { | 773 | if (HP_SUPR_RM(ctrl)) { |
774 | pciehp_writew(ctrl, PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_PDC); | 774 | pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, |
775 | PCI_EXP_SLTSTA_PDC); | ||
775 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE); | 776 | pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PDCE, PCI_EXP_SLTCTL_PDCE); |
776 | if (pciehp_poll_mode) | 777 | if (pciehp_poll_mode) |
777 | int_poll_timeout(ctrl->poll_timer.data); | 778 | int_poll_timeout(ctrl->poll_timer.data); |
@@ -875,9 +876,9 @@ static inline void dbg_ctrl(struct controller *ctrl) | |||
875 | EMI(ctrl) ? "yes" : "no"); | 876 | EMI(ctrl) ? "yes" : "no"); |
876 | ctrl_info(ctrl, " Command Completed : %3s\n", | 877 | ctrl_info(ctrl, " Command Completed : %3s\n", |
877 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); | 878 | NO_CMD_CMPL(ctrl) ? "no" : "yes"); |
878 | pciehp_readw(ctrl, PCI_EXP_SLTSTA, ®16); | 879 | pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, ®16); |
879 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); | 880 | ctrl_info(ctrl, "Slot Status : 0x%04x\n", reg16); |
880 | pciehp_readw(ctrl, PCI_EXP_SLTCTL, ®16); | 881 | pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, ®16); |
881 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); | 882 | ctrl_info(ctrl, "Slot Control : 0x%04x\n", reg16); |
882 | } | 883 | } |
883 | 884 | ||
@@ -893,7 +894,7 @@ struct controller *pcie_init(struct pcie_device *dev) | |||
893 | goto abort; | 894 | goto abort; |
894 | } | 895 | } |
895 | ctrl->pcie = dev; | 896 | ctrl->pcie = dev; |
896 | if (pciehp_readl(ctrl, PCI_EXP_SLTCAP, &slot_cap)) { | 897 | if (pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &slot_cap)) { |
897 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); | 898 | ctrl_err(ctrl, "Cannot read SLOTCAP register\n"); |
898 | goto abort_ctrl; | 899 | goto abort_ctrl; |
899 | } | 900 | } |
@@ -913,7 +914,7 @@ struct controller *pcie_init(struct pcie_device *dev) | |||
913 | ctrl->no_cmd_complete = 1; | 914 | ctrl->no_cmd_complete = 1; |
914 | 915 | ||
915 | /* Check if Data Link Layer Link Active Reporting is implemented */ | 916 | /* Check if Data Link Layer Link Active Reporting is implemented */ |
916 | if (pciehp_readl(ctrl, PCI_EXP_LNKCAP, &link_cap)) { | 917 | if (pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap)) { |
917 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); | 918 | ctrl_err(ctrl, "%s: Cannot read LNKCAP register\n", __func__); |
918 | goto abort_ctrl; | 919 | goto abort_ctrl; |
919 | } | 920 | } |
@@ -923,7 +924,7 @@ struct controller *pcie_init(struct pcie_device *dev) | |||
923 | } | 924 | } |
924 | 925 | ||
925 | /* Clear all remaining event bits in Slot Status register */ | 926 | /* Clear all remaining event bits in Slot Status register */ |
926 | if (pciehp_writew(ctrl, PCI_EXP_SLTSTA, 0x1f)) | 927 | if (pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, 0x1f)) |
927 | goto abort_ctrl; | 928 | goto abort_ctrl; |
928 | 929 | ||
929 | /* Disable software notification */ | 930 | /* Disable software notification */ |