NTB: Xeon Errata Workaround

There is a Xeon hardware errata related to writes to SDOORBELL or
B2BDOORBELL in conjunction with inbound access to NTB MMIO Space, which
may hang the system.  To workaround this issue, use one of the memory
windows to access the interrupt and scratch pad registers on the remote
system.  This bypasses the issue, but removes one of the memory windows
from use by the transport.  This reduction of MWs necessitates adding
some logic to determine the number of available MWs.

Since some NTB usage methodologies may have unidirectional traffic, the
ability to disable the workaround via modparm has been added.

See BF113 in
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-c5500-c3500-spec-update.pdf
See BT119 in
http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-family-spec-update.pdf

Signed-off-by: Jon Mason <jon.mason@intel.com>

1 files changed, 15 insertions, 10 deletions

diff --git a/drivers/ntb/ntb_regs.h b/drivers/ntb/ntb_regs.h
index 96209b4abc22..4ddc590d03a6 100644
--- a/drivers/ntb/ntb_regs.h
+++ b/drivers/ntb/ntb_regs.h
@@ -58,6 +58,8 @@
 /* Reserve the uppermost bit for link interrupt */
 #define SNB_MAX_DB_BITS         15
 #define SNB_DB_BITS_PER_VEC     5
+#define SNB_MAX_MW              2
+#define SNB_ERRATA_MAX_MW       1
 
 #define SNB_DB_HW_LINK          0x8000
 
@@ -74,6 +76,9 @@
 #define SNB_SBAR2XLAT_OFFSET    0x0030
 #define SNB_SBAR4XLAT_OFFSET    0x0038
 #define SNB_SBAR0BASE_OFFSET    0x0040
+#define SNB_SBAR0BASE_OFFSET    0x0040
+#define SNB_SBAR2BASE_OFFSET    0x0048
+#define SNB_SBAR4BASE_OFFSET    0x0050
 #define SNB_SBAR2BASE_OFFSET    0x0048
 #define SNB_SBAR4BASE_OFFSET    0x0050
 #define SNB_NTBCNTL_OFFSET      0x0058
@@ -88,13 +93,22 @@
 #define SNB_WCCNTRL_OFFSET      0x00e0
 #define SNB_B2B_SPAD_OFFSET     0x0100
 #define SNB_B2B_DOORBELL_OFFSET 0x0140
-#define SNB_B2B_XLAT_OFFSET     0x0144
+#define SNB_B2B_XLAT_OFFSETL    0x0144
+#define SNB_B2B_XLAT_OFFSETU    0x0148
+
+#define SNB_MBAR01_USD_ADDR     0x000000210000000CULL
+#define SNB_MBAR23_USD_ADDR     0x000000410000000CULL
+#define SNB_MBAR45_USD_ADDR     0x000000810000000CULL
+#define SNB_MBAR01_DSD_ADDR     0x000000200000000CULL
+#define SNB_MBAR23_DSD_ADDR     0x000000400000000CULL
+#define SNB_MBAR45_DSD_ADDR     0x000000800000000CULL
 
 #define BWD_MSIX_CNT            34
 #define BWD_MAX_SPADS           16
 #define BWD_MAX_COMPAT_SPADS    16
 #define BWD_MAX_DB_BITS         34
 #define BWD_DB_BITS_PER_VEC     1
+#define BWD_MAX_MW              2
 
 #define BWD_PCICMD_OFFSET       0xb004
 #define BWD_MBAR23_OFFSET       0xb018
@@ -128,12 +142,3 @@
 #define BWD_PPD_INIT_LINK       0x0008
 #define BWD_PPD_CONN_TYPE       0x0300
 #define BWD_PPD_DEV_TYPE        0x1000
-
-#define BWD_PBAR2XLAT_USD_ADDR  0x0000004000000000
-#define BWD_PBAR4XLAT_USD_ADDR  0x0000008000000000
-#define BWD_MBAR23_USD_ADDR     0x000000410000000C
-#define BWD_MBAR45_USD_ADDR     0x000000810000000C
-#define BWD_PBAR2XLAT_DSD_ADDR  0x0000004100000000
-#define BWD_PBAR4XLAT_DSD_ADDR  0x0000008100000000
-#define BWD_MBAR23_DSD_ADDR     0x000000400000000C
-#define BWD_MBAR45_DSD_ADDR     0x000000800000000C