diff options
| author | Rajkumar Manoharan <rmanohar@qca.qualcomm.com> | 2011-10-21 03:23:51 -0400 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2011-11-02 15:23:11 -0400 |
| commit | fd26981cf53ee91951a92fae53416e4ce639164c (patch) | |
| tree | c30d9fbcb6d59cffbfd57c08dbbd6db10fb5aa01 /drivers/net | |
| parent | 6911bf0453e0d6ea8eb694a4ce67a68d071c538e (diff) | |
ath9k_hw: Fix regression of register offset of AR9330/AR9340
The commit ce407afc10 introduced regression for AR9330/AR9340
register offsets. Some of the register offsets are common
for AR9330/AR9340/AR9485 except AR9380. Fix that.
Cc: stable@kernel.org [3.1.0+]
Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com>
Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_phy.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h index 70e01031714f..4114fe752c6b 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h | |||
| @@ -651,7 +651,7 @@ | |||
| 651 | #define AR_SWITCH_TABLE_ALL_S (0) | 651 | #define AR_SWITCH_TABLE_ALL_S (0) |
| 652 | 652 | ||
| 653 | #define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 :\ | 653 | #define AR_PHY_65NM_CH0_THERM (AR_SREV_9300(ah) ? 0x16290 :\ |
| 654 | (AR_SREV_9485(ah) ? 0x1628c : 0x16294)) | 654 | (AR_SREV_9462(ah) ? 0x16294 : 0x1628c)) |
| 655 | 655 | ||
| 656 | #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 | 656 | #define AR_PHY_65NM_CH0_THERM_LOCAL 0x80000000 |
| 657 | #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 | 657 | #define AR_PHY_65NM_CH0_THERM_LOCAL_S 31 |
| @@ -668,12 +668,12 @@ | |||
| 668 | #define AR_PHY_65NM_CH2_RXTX2 0x16904 | 668 | #define AR_PHY_65NM_CH2_RXTX2 0x16904 |
| 669 | 669 | ||
| 670 | #define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : \ | 670 | #define AR_CH0_TOP2 (AR_SREV_9300(ah) ? 0x1628c : \ |
| 671 | (AR_SREV_9485(ah) ? 0x16284 : 0x16290)) | 671 | (AR_SREV_9462(ah) ? 0x16290 : 0x16284)) |
| 672 | #define AR_CH0_TOP2_XPABIASLVL 0xf000 | 672 | #define AR_CH0_TOP2_XPABIASLVL 0xf000 |
| 673 | #define AR_CH0_TOP2_XPABIASLVL_S 12 | 673 | #define AR_CH0_TOP2_XPABIASLVL_S 12 |
| 674 | 674 | ||
| 675 | #define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \ | 675 | #define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \ |
| 676 | (AR_SREV_9485(ah) ? 0x16290 : 0x16298)) | 676 | (AR_SREV_9462(ah) ? 0x16298 : 0x16290)) |
| 677 | #define AR_CH0_XTAL_CAPINDAC 0x7f000000 | 677 | #define AR_CH0_XTAL_CAPINDAC 0x7f000000 |
| 678 | #define AR_CH0_XTAL_CAPINDAC_S 24 | 678 | #define AR_CH0_XTAL_CAPINDAC_S 24 |
| 679 | #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 | 679 | #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 |
| @@ -908,8 +908,8 @@ | |||
| 908 | #define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208) | 908 | #define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208) |
| 909 | #define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c) | 909 | #define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c) |
| 910 | #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220) | 910 | #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220) |
| 911 | #define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + (AR_SREV_AR9300(ah) ? \ | 911 | #define AR_PHY_PDADC_TAB_1 (AR_SM1_BASE + (AR_SREV_AR9462(ah) ? \ |
| 912 | 0x240 : 0x280)) | 912 | 0x280 : 0x240)) |
| 913 | #define AR_PHY_TPC_19_B1 (AR_SM1_BASE + 0x240) | 913 | #define AR_PHY_TPC_19_B1 (AR_SM1_BASE + 0x240) |
| 914 | #define AR_PHY_TPC_19_B1_ALPHA_THERM 0xff | 914 | #define AR_PHY_TPC_19_B1_ALPHA_THERM 0xff |
| 915 | #define AR_PHY_TPC_19_B1_ALPHA_THERM_S 0 | 915 | #define AR_PHY_TPC_19_B1_ALPHA_THERM_S 0 |