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authorBrice Goglin <brice@myri.com>2006-08-14 17:52:54 -0400
committerJeff Garzik <jeff@garzik.org>2006-08-19 17:45:17 -0400
commite700f9f4a208bf6c5d2b4dd67816555930524476 (patch)
tree58fb624280c4295b8975d18055ac323959cd2e9f /drivers/net
parent846050dd49719b1f68248807bba5c27bfc86f81a (diff)
[PATCH] myri10ge: define some previously hardwired firmware constants
Define some previously hardwired firmware constants. Signed-off-by: Brice Goglin <brice@myri.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/myri10ge/myri10ge.c17
-rw-r--r--drivers/net/myri10ge/myri10ge_mcp.h14
2 files changed, 23 insertions, 8 deletions
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index 9bdd43ab3573..f463a2f2bdde 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -271,7 +271,7 @@ myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
271 struct mcp_cmd *buf; 271 struct mcp_cmd *buf;
272 char buf_bytes[sizeof(*buf) + 8]; 272 char buf_bytes[sizeof(*buf) + 8];
273 struct mcp_cmd_response *response = mgp->cmd; 273 struct mcp_cmd_response *response = mgp->cmd;
274 char __iomem *cmd_addr = mgp->sram + MXGEFW_CMD_OFFSET; 274 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
275 u32 dma_low, dma_high, result, value; 275 u32 dma_low, dma_high, result, value;
276 int sleep_total = 0; 276 int sleep_total = 0;
277 277
@@ -404,7 +404,7 @@ static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
404 buf[4] = htonl(dma_low); /* dummy addr LSW */ 404 buf[4] = htonl(dma_low); /* dummy addr LSW */
405 buf[5] = htonl(enable); /* enable? */ 405 buf[5] = htonl(enable); /* enable? */
406 406
407 submit = mgp->sram + 0xfc01c0; 407 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
408 408
409 myri10ge_pio_copy(submit, &buf, sizeof(buf)); 409 myri10ge_pio_copy(submit, &buf, sizeof(buf));
410 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++) 410 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
@@ -600,7 +600,7 @@ static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
600 buf[5] = htonl(8); /* where to copy to */ 600 buf[5] = htonl(8); /* where to copy to */
601 buf[6] = htonl(0); /* where to jump to */ 601 buf[6] = htonl(0); /* where to jump to */
602 602
603 submit = mgp->sram + 0xfc0000; 603 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
604 604
605 myri10ge_pio_copy(submit, &buf, sizeof(buf)); 605 myri10ge_pio_copy(submit, &buf, sizeof(buf));
606 mb(); 606 mb();
@@ -1648,9 +1648,11 @@ static int myri10ge_open(struct net_device *dev)
1648 } 1648 }
1649 1649
1650 if (mgp->mtrr >= 0) { 1650 if (mgp->mtrr >= 0) {
1651 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + 0x200000; 1651 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1652 mgp->rx_small.wc_fifo = (u8 __iomem *) mgp->sram + 0x300000; 1652 mgp->rx_small.wc_fifo =
1653 mgp->rx_big.wc_fifo = (u8 __iomem *) mgp->sram + 0x340000; 1653 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1654 mgp->rx_big.wc_fifo =
1655 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1654 } else { 1656 } else {
1655 mgp->tx.wc_fifo = NULL; 1657 mgp->tx.wc_fifo = NULL;
1656 mgp->rx_small.wc_fifo = NULL; 1658 mgp->rx_small.wc_fifo = NULL;
@@ -1841,7 +1843,8 @@ myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1841 if (cnt > 0) { 1843 if (cnt > 0) {
1842 /* pad it to 64 bytes. The src is 64 bytes bigger than it 1844 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1843 * needs to be so that we don't overrun it */ 1845 * needs to be so that we don't overrun it */
1844 myri10ge_pio_copy(tx->wc_fifo + (cnt << 18), src, 64); 1846 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1847 src, 64);
1845 mb(); 1848 mb();
1846 } 1849 }
1847} 1850}
diff --git a/drivers/net/myri10ge/myri10ge_mcp.h b/drivers/net/myri10ge/myri10ge_mcp.h
index 0a6cae6cb186..d7dfaa5f64a2 100644
--- a/drivers/net/myri10ge/myri10ge_mcp.h
+++ b/drivers/net/myri10ge/myri10ge_mcp.h
@@ -91,7 +91,19 @@ struct mcp_kreq_ether_recv {
91 91
92/* Commands */ 92/* Commands */
93 93
94#define MXGEFW_CMD_OFFSET 0xf80000 94#define MXGEFW_BOOT_HANDOFF 0xfc0000
95#define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0
96
97#define MXGEFW_ETH_CMD 0xf80000
98#define MXGEFW_ETH_SEND_4 0x200000
99#define MXGEFW_ETH_SEND_1 0x240000
100#define MXGEFW_ETH_SEND_2 0x280000
101#define MXGEFW_ETH_SEND_3 0x2c0000
102#define MXGEFW_ETH_RECV_SMALL 0x300000
103#define MXGEFW_ETH_RECV_BIG 0x340000
104
105#define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000))
106#define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4)
95 107
96enum myri10ge_mcp_cmd_type { 108enum myri10ge_mcp_cmd_type {
97 MXGEFW_CMD_NONE = 0, 109 MXGEFW_CMD_NONE = 0,