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authorFrancesco Virlinzi <francesco.virlinzi@st.com>2011-11-16 16:57:58 -0500
committerDavid S. Miller <davem@davemloft.net>2011-11-17 03:13:41 -0500
commitbbc1754639f771cd2b515fed39b977549b373034 (patch)
tree7f5cd57925266ec2484d5f6f2e0fc2d434a2b82a /drivers/net
parentd9fa7c86f1fca60693beea187c963cfda4a54a06 (diff)
stmmac: use mdelay on timeout of sw reset
This patch uses an mdelay to manage the timeout on sw reset to be independant of cpu_clk. Signed-off-by: Francesco Virlinzi <francesco.virlinzi@st.com> Reviewed-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c3
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c3
2 files changed, 4 insertions, 2 deletions
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
index da66ac511c4c..4d5402a1d262 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c
@@ -39,10 +39,11 @@ static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,
39 /* DMA SW reset */ 39 /* DMA SW reset */
40 value |= DMA_BUS_MODE_SFT_RESET; 40 value |= DMA_BUS_MODE_SFT_RESET;
41 writel(value, ioaddr + DMA_BUS_MODE); 41 writel(value, ioaddr + DMA_BUS_MODE);
42 limit = 15000; 42 limit = 10;
43 while (limit--) { 43 while (limit--) {
44 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) 44 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
45 break; 45 break;
46 mdelay(10);
46 } 47 }
47 if (limit < 0) 48 if (limit < 0)
48 return -EBUSY; 49 return -EBUSY;
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
index 627f656b0f3c..bc17fd08b55d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c
@@ -41,10 +41,11 @@ static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx,
41 /* DMA SW reset */ 41 /* DMA SW reset */
42 value |= DMA_BUS_MODE_SFT_RESET; 42 value |= DMA_BUS_MODE_SFT_RESET;
43 writel(value, ioaddr + DMA_BUS_MODE); 43 writel(value, ioaddr + DMA_BUS_MODE);
44 limit = 15000; 44 limit = 10;
45 while (limit--) { 45 while (limit--) {
46 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET)) 46 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
47 break; 47 break;
48 mdelay(10);
48 } 49 }
49 if (limit < 0) 50 if (limit < 0)
50 return -EBUSY; 51 return -EBUSY;