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authorAyaz Abdulla <aabdulla@nvidia.com>2006-07-06 16:45:58 -0400
committerJeff Garzik <jeff@garzik.org>2006-07-12 17:38:20 -0400
commit9744e218aad2ef4569b0de960ff193fb50f5d6e0 (patch)
treeebc30de9c7b427bd620fc94967b17a701f5a42a1 /drivers/net
parent7c3dec0679c66ce177726802adbe2f403942fc27 (diff)
[PATCH] forcedeth: deferral fixup
This patch adds the definition for the deferral registers and fixes up the use of these registers. Signed-Off-By: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/forcedeth.c26
1 files changed, 19 insertions, 7 deletions
diff --git a/drivers/net/forcedeth.c b/drivers/net/forcedeth.c
index ad81ec68f887..1a315d09d95e 100644
--- a/drivers/net/forcedeth.c
+++ b/drivers/net/forcedeth.c
@@ -240,10 +240,12 @@ enum {
240#define NVREG_RNDSEED_FORCE2 0x2d00 240#define NVREG_RNDSEED_FORCE2 0x2d00
241#define NVREG_RNDSEED_FORCE3 0x7400 241#define NVREG_RNDSEED_FORCE3 0x7400
242 242
243 NvRegUnknownSetupReg1 = 0xA0, 243 NvRegTxDeferral = 0xA0,
244#define NVREG_UNKSETUP1_VAL 0x16070f 244#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
245 NvRegUnknownSetupReg2 = 0xA4, 245#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
246#define NVREG_UNKSETUP2_VAL 0x16 246#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
247 NvRegRxDeferral = 0xA4,
248#define NVREG_RX_DEFERRAL_DEFAULT 0x16
247 NvRegMacAddrA = 0xA8, 249 NvRegMacAddrA = 0xA8,
248 NvRegMacAddrB = 0xAC, 250 NvRegMacAddrB = 0xAC,
249 NvRegMulticastAddrA = 0xB0, 251 NvRegMulticastAddrA = 0xB0,
@@ -2127,7 +2129,7 @@ static int nv_update_linkspeed(struct net_device *dev)
2127 int newdup = np->duplex; 2129 int newdup = np->duplex;
2128 int mii_status; 2130 int mii_status;
2129 int retval = 0; 2131 int retval = 0;
2130 u32 control_1000, status_1000, phyreg, pause_flags; 2132 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
2131 2133
2132 /* BMSR_LSTATUS is latched, read it twice: 2134 /* BMSR_LSTATUS is latched, read it twice:
2133 * we want the current value. 2135 * we want the current value.
@@ -2245,6 +2247,16 @@ set_speed:
2245 phyreg |= PHY_1000; 2247 phyreg |= PHY_1000;
2246 writel(phyreg, base + NvRegPhyInterface); 2248 writel(phyreg, base + NvRegPhyInterface);
2247 2249
2250 if (phyreg & PHY_RGMII) {
2251 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
2252 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
2253 else
2254 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
2255 } else {
2256 txreg = NVREG_TX_DEFERRAL_DEFAULT;
2257 }
2258 writel(txreg, base + NvRegTxDeferral);
2259
2248 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), 2260 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
2249 base + NvRegMisc1); 2261 base + NvRegMisc1);
2250 pci_push(base); 2262 pci_push(base);
@@ -3932,8 +3944,8 @@ static int nv_open(struct net_device *dev)
3932 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus); 3944 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
3933 get_random_bytes(&i, sizeof(i)); 3945 get_random_bytes(&i, sizeof(i));
3934 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); 3946 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
3935 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1); 3947 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
3936 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2); 3948 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
3937 if (poll_interval == -1) { 3949 if (poll_interval == -1) {
3938 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT) 3950 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
3939 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); 3951 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);