diff options
| author | Alexander Aring <alex.aring@gmail.com> | 2015-04-30 11:44:58 -0400 |
|---|---|---|
| committer | Marcel Holtmann <marcel@holtmann.org> | 2015-04-30 12:48:10 -0400 |
| commit | 5e8e01e262be1eeaae598be44b8e43b29aab842a (patch) | |
| tree | 1db26bf521cb69f9e2e29e3ecf7d27f06a338bcd /drivers/net | |
| parent | 5b4a10390460cccf17a9fac739e153d68cf25ef5 (diff) | |
at86rf230: remove tabs after define
This patch cleanups the at86rf230 driver to use a space instead a tab
after define.
Signed-off-by: Alexander Aring <alex.aring@gmail.com>
Reviewed-by: Varka Bhadram <varkabhadram@gmail.com>
Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/ieee802154/at86rf230.c | 304 |
1 files changed, 152 insertions, 152 deletions
diff --git a/drivers/net/ieee802154/at86rf230.c b/drivers/net/ieee802154/at86rf230.c index 684488acc65d..9a41deb1966c 100644 --- a/drivers/net/ieee802154/at86rf230.c +++ b/drivers/net/ieee802154/at86rf230.c | |||
| @@ -100,158 +100,158 @@ struct at86rf230_local { | |||
| 100 | struct at86rf230_state_change tx; | 100 | struct at86rf230_state_change tx; |
| 101 | }; | 101 | }; |
| 102 | 102 | ||
| 103 | #define RG_TRX_STATUS (0x01) | 103 | #define RG_TRX_STATUS (0x01) |
| 104 | #define SR_TRX_STATUS 0x01, 0x1f, 0 | 104 | #define SR_TRX_STATUS 0x01, 0x1f, 0 |
| 105 | #define SR_RESERVED_01_3 0x01, 0x20, 5 | 105 | #define SR_RESERVED_01_3 0x01, 0x20, 5 |
| 106 | #define SR_CCA_STATUS 0x01, 0x40, 6 | 106 | #define SR_CCA_STATUS 0x01, 0x40, 6 |
| 107 | #define SR_CCA_DONE 0x01, 0x80, 7 | 107 | #define SR_CCA_DONE 0x01, 0x80, 7 |
| 108 | #define RG_TRX_STATE (0x02) | 108 | #define RG_TRX_STATE (0x02) |
| 109 | #define SR_TRX_CMD 0x02, 0x1f, 0 | 109 | #define SR_TRX_CMD 0x02, 0x1f, 0 |
| 110 | #define SR_TRAC_STATUS 0x02, 0xe0, 5 | 110 | #define SR_TRAC_STATUS 0x02, 0xe0, 5 |
| 111 | #define RG_TRX_CTRL_0 (0x03) | 111 | #define RG_TRX_CTRL_0 (0x03) |
| 112 | #define SR_CLKM_CTRL 0x03, 0x07, 0 | 112 | #define SR_CLKM_CTRL 0x03, 0x07, 0 |
| 113 | #define SR_CLKM_SHA_SEL 0x03, 0x08, 3 | 113 | #define SR_CLKM_SHA_SEL 0x03, 0x08, 3 |
| 114 | #define SR_PAD_IO_CLKM 0x03, 0x30, 4 | 114 | #define SR_PAD_IO_CLKM 0x03, 0x30, 4 |
| 115 | #define SR_PAD_IO 0x03, 0xc0, 6 | 115 | #define SR_PAD_IO 0x03, 0xc0, 6 |
| 116 | #define RG_TRX_CTRL_1 (0x04) | 116 | #define RG_TRX_CTRL_1 (0x04) |
| 117 | #define SR_IRQ_POLARITY 0x04, 0x01, 0 | 117 | #define SR_IRQ_POLARITY 0x04, 0x01, 0 |
| 118 | #define SR_IRQ_MASK_MODE 0x04, 0x02, 1 | 118 | #define SR_IRQ_MASK_MODE 0x04, 0x02, 1 |
| 119 | #define SR_SPI_CMD_MODE 0x04, 0x0c, 2 | 119 | #define SR_SPI_CMD_MODE 0x04, 0x0c, 2 |
| 120 | #define SR_RX_BL_CTRL 0x04, 0x10, 4 | 120 | #define SR_RX_BL_CTRL 0x04, 0x10, 4 |
| 121 | #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5 | 121 | #define SR_TX_AUTO_CRC_ON 0x04, 0x20, 5 |
| 122 | #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6 | 122 | #define SR_IRQ_2_EXT_EN 0x04, 0x40, 6 |
| 123 | #define SR_PA_EXT_EN 0x04, 0x80, 7 | 123 | #define SR_PA_EXT_EN 0x04, 0x80, 7 |
| 124 | #define RG_PHY_TX_PWR (0x05) | 124 | #define RG_PHY_TX_PWR (0x05) |
| 125 | #define SR_TX_PWR 0x05, 0x0f, 0 | 125 | #define SR_TX_PWR 0x05, 0x0f, 0 |
| 126 | #define SR_PA_LT 0x05, 0x30, 4 | 126 | #define SR_PA_LT 0x05, 0x30, 4 |
| 127 | #define SR_PA_BUF_LT 0x05, 0xc0, 6 | 127 | #define SR_PA_BUF_LT 0x05, 0xc0, 6 |
| 128 | #define RG_PHY_RSSI (0x06) | 128 | #define RG_PHY_RSSI (0x06) |
| 129 | #define SR_RSSI 0x06, 0x1f, 0 | 129 | #define SR_RSSI 0x06, 0x1f, 0 |
| 130 | #define SR_RND_VALUE 0x06, 0x60, 5 | 130 | #define SR_RND_VALUE 0x06, 0x60, 5 |
| 131 | #define SR_RX_CRC_VALID 0x06, 0x80, 7 | 131 | #define SR_RX_CRC_VALID 0x06, 0x80, 7 |
| 132 | #define RG_PHY_ED_LEVEL (0x07) | 132 | #define RG_PHY_ED_LEVEL (0x07) |
| 133 | #define SR_ED_LEVEL 0x07, 0xff, 0 | 133 | #define SR_ED_LEVEL 0x07, 0xff, 0 |
| 134 | #define RG_PHY_CC_CCA (0x08) | 134 | #define RG_PHY_CC_CCA (0x08) |
| 135 | #define SR_CHANNEL 0x08, 0x1f, 0 | 135 | #define SR_CHANNEL 0x08, 0x1f, 0 |
| 136 | #define SR_CCA_MODE 0x08, 0x60, 5 | 136 | #define SR_CCA_MODE 0x08, 0x60, 5 |
| 137 | #define SR_CCA_REQUEST 0x08, 0x80, 7 | 137 | #define SR_CCA_REQUEST 0x08, 0x80, 7 |
| 138 | #define RG_CCA_THRES (0x09) | 138 | #define RG_CCA_THRES (0x09) |
| 139 | #define SR_CCA_ED_THRES 0x09, 0x0f, 0 | 139 | #define SR_CCA_ED_THRES 0x09, 0x0f, 0 |
| 140 | #define SR_RESERVED_09_1 0x09, 0xf0, 4 | 140 | #define SR_RESERVED_09_1 0x09, 0xf0, 4 |
| 141 | #define RG_RX_CTRL (0x0a) | 141 | #define RG_RX_CTRL (0x0a) |
| 142 | #define SR_PDT_THRES 0x0a, 0x0f, 0 | 142 | #define SR_PDT_THRES 0x0a, 0x0f, 0 |
| 143 | #define SR_RESERVED_0a_1 0x0a, 0xf0, 4 | 143 | #define SR_RESERVED_0a_1 0x0a, 0xf0, 4 |
| 144 | #define RG_SFD_VALUE (0x0b) | 144 | #define RG_SFD_VALUE (0x0b) |
| 145 | #define SR_SFD_VALUE 0x0b, 0xff, 0 | 145 | #define SR_SFD_VALUE 0x0b, 0xff, 0 |
| 146 | #define RG_TRX_CTRL_2 (0x0c) | 146 | #define RG_TRX_CTRL_2 (0x0c) |
| 147 | #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0 | 147 | #define SR_OQPSK_DATA_RATE 0x0c, 0x03, 0 |
| 148 | #define SR_SUB_MODE 0x0c, 0x04, 2 | 148 | #define SR_SUB_MODE 0x0c, 0x04, 2 |
| 149 | #define SR_BPSK_QPSK 0x0c, 0x08, 3 | 149 | #define SR_BPSK_QPSK 0x0c, 0x08, 3 |
| 150 | #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4 | 150 | #define SR_OQPSK_SUB1_RC_EN 0x0c, 0x10, 4 |
| 151 | #define SR_RESERVED_0c_5 0x0c, 0x60, 5 | 151 | #define SR_RESERVED_0c_5 0x0c, 0x60, 5 |
| 152 | #define SR_RX_SAFE_MODE 0x0c, 0x80, 7 | 152 | #define SR_RX_SAFE_MODE 0x0c, 0x80, 7 |
| 153 | #define RG_ANT_DIV (0x0d) | 153 | #define RG_ANT_DIV (0x0d) |
| 154 | #define SR_ANT_CTRL 0x0d, 0x03, 0 | 154 | #define SR_ANT_CTRL 0x0d, 0x03, 0 |
| 155 | #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2 | 155 | #define SR_ANT_EXT_SW_EN 0x0d, 0x04, 2 |
| 156 | #define SR_ANT_DIV_EN 0x0d, 0x08, 3 | 156 | #define SR_ANT_DIV_EN 0x0d, 0x08, 3 |
| 157 | #define SR_RESERVED_0d_2 0x0d, 0x70, 4 | 157 | #define SR_RESERVED_0d_2 0x0d, 0x70, 4 |
| 158 | #define SR_ANT_SEL 0x0d, 0x80, 7 | 158 | #define SR_ANT_SEL 0x0d, 0x80, 7 |
| 159 | #define RG_IRQ_MASK (0x0e) | 159 | #define RG_IRQ_MASK (0x0e) |
| 160 | #define SR_IRQ_MASK 0x0e, 0xff, 0 | 160 | #define SR_IRQ_MASK 0x0e, 0xff, 0 |
| 161 | #define RG_IRQ_STATUS (0x0f) | 161 | #define RG_IRQ_STATUS (0x0f) |
| 162 | #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0 | 162 | #define SR_IRQ_0_PLL_LOCK 0x0f, 0x01, 0 |
| 163 | #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1 | 163 | #define SR_IRQ_1_PLL_UNLOCK 0x0f, 0x02, 1 |
| 164 | #define SR_IRQ_2_RX_START 0x0f, 0x04, 2 | 164 | #define SR_IRQ_2_RX_START 0x0f, 0x04, 2 |
| 165 | #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3 | 165 | #define SR_IRQ_3_TRX_END 0x0f, 0x08, 3 |
| 166 | #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4 | 166 | #define SR_IRQ_4_CCA_ED_DONE 0x0f, 0x10, 4 |
| 167 | #define SR_IRQ_5_AMI 0x0f, 0x20, 5 | 167 | #define SR_IRQ_5_AMI 0x0f, 0x20, 5 |
| 168 | #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6 | 168 | #define SR_IRQ_6_TRX_UR 0x0f, 0x40, 6 |
| 169 | #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7 | 169 | #define SR_IRQ_7_BAT_LOW 0x0f, 0x80, 7 |
| 170 | #define RG_VREG_CTRL (0x10) | 170 | #define RG_VREG_CTRL (0x10) |
| 171 | #define SR_RESERVED_10_6 0x10, 0x03, 0 | 171 | #define SR_RESERVED_10_6 0x10, 0x03, 0 |
| 172 | #define SR_DVDD_OK 0x10, 0x04, 2 | 172 | #define SR_DVDD_OK 0x10, 0x04, 2 |
| 173 | #define SR_DVREG_EXT 0x10, 0x08, 3 | 173 | #define SR_DVREG_EXT 0x10, 0x08, 3 |
| 174 | #define SR_RESERVED_10_3 0x10, 0x30, 4 | 174 | #define SR_RESERVED_10_3 0x10, 0x30, 4 |
| 175 | #define SR_AVDD_OK 0x10, 0x40, 6 | 175 | #define SR_AVDD_OK 0x10, 0x40, 6 |
| 176 | #define SR_AVREG_EXT 0x10, 0x80, 7 | 176 | #define SR_AVREG_EXT 0x10, 0x80, 7 |
| 177 | #define RG_BATMON (0x11) | 177 | #define RG_BATMON (0x11) |
| 178 | #define SR_BATMON_VTH 0x11, 0x0f, 0 | 178 | #define SR_BATMON_VTH 0x11, 0x0f, 0 |
| 179 | #define SR_BATMON_HR 0x11, 0x10, 4 | 179 | #define SR_BATMON_HR 0x11, 0x10, 4 |
| 180 | #define SR_BATMON_OK 0x11, 0x20, 5 | 180 | #define SR_BATMON_OK 0x11, 0x20, 5 |
| 181 | #define SR_RESERVED_11_1 0x11, 0xc0, 6 | 181 | #define SR_RESERVED_11_1 0x11, 0xc0, 6 |
| 182 | #define RG_XOSC_CTRL (0x12) | 182 | #define RG_XOSC_CTRL (0x12) |
| 183 | #define SR_XTAL_TRIM 0x12, 0x0f, 0 | 183 | #define SR_XTAL_TRIM 0x12, 0x0f, 0 |
| 184 | #define SR_XTAL_MODE 0x12, 0xf0, 4 | 184 | #define SR_XTAL_MODE 0x12, 0xf0, 4 |
| 185 | #define RG_RX_SYN (0x15) | 185 | #define RG_RX_SYN (0x15) |
| 186 | #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0 | 186 | #define SR_RX_PDT_LEVEL 0x15, 0x0f, 0 |
| 187 | #define SR_RESERVED_15_2 0x15, 0x70, 4 | 187 | #define SR_RESERVED_15_2 0x15, 0x70, 4 |
| 188 | #define SR_RX_PDT_DIS 0x15, 0x80, 7 | 188 | #define SR_RX_PDT_DIS 0x15, 0x80, 7 |
| 189 | #define RG_XAH_CTRL_1 (0x17) | 189 | #define RG_XAH_CTRL_1 (0x17) |
| 190 | #define SR_RESERVED_17_8 0x17, 0x01, 0 | 190 | #define SR_RESERVED_17_8 0x17, 0x01, 0 |
| 191 | #define SR_AACK_PROM_MODE 0x17, 0x02, 1 | 191 | #define SR_AACK_PROM_MODE 0x17, 0x02, 1 |
| 192 | #define SR_AACK_ACK_TIME 0x17, 0x04, 2 | 192 | #define SR_AACK_ACK_TIME 0x17, 0x04, 2 |
| 193 | #define SR_RESERVED_17_5 0x17, 0x08, 3 | 193 | #define SR_RESERVED_17_5 0x17, 0x08, 3 |
| 194 | #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4 | 194 | #define SR_AACK_UPLD_RES_FT 0x17, 0x10, 4 |
| 195 | #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5 | 195 | #define SR_AACK_FLTR_RES_FT 0x17, 0x20, 5 |
| 196 | #define SR_CSMA_LBT_MODE 0x17, 0x40, 6 | 196 | #define SR_CSMA_LBT_MODE 0x17, 0x40, 6 |
| 197 | #define SR_RESERVED_17_1 0x17, 0x80, 7 | 197 | #define SR_RESERVED_17_1 0x17, 0x80, 7 |
| 198 | #define RG_FTN_CTRL (0x18) | 198 | #define RG_FTN_CTRL (0x18) |
| 199 | #define SR_RESERVED_18_2 0x18, 0x7f, 0 | 199 | #define SR_RESERVED_18_2 0x18, 0x7f, 0 |
| 200 | #define SR_FTN_START 0x18, 0x80, 7 | 200 | #define SR_FTN_START 0x18, 0x80, 7 |
| 201 | #define RG_PLL_CF (0x1a) | 201 | #define RG_PLL_CF (0x1a) |
| 202 | #define SR_RESERVED_1a_2 0x1a, 0x7f, 0 | 202 | #define SR_RESERVED_1a_2 0x1a, 0x7f, 0 |
| 203 | #define SR_PLL_CF_START 0x1a, 0x80, 7 | 203 | #define SR_PLL_CF_START 0x1a, 0x80, 7 |
| 204 | #define RG_PLL_DCU (0x1b) | 204 | #define RG_PLL_DCU (0x1b) |
| 205 | #define SR_RESERVED_1b_3 0x1b, 0x3f, 0 | 205 | #define SR_RESERVED_1b_3 0x1b, 0x3f, 0 |
| 206 | #define SR_RESERVED_1b_2 0x1b, 0x40, 6 | 206 | #define SR_RESERVED_1b_2 0x1b, 0x40, 6 |
| 207 | #define SR_PLL_DCU_START 0x1b, 0x80, 7 | 207 | #define SR_PLL_DCU_START 0x1b, 0x80, 7 |
| 208 | #define RG_PART_NUM (0x1c) | 208 | #define RG_PART_NUM (0x1c) |
| 209 | #define SR_PART_NUM 0x1c, 0xff, 0 | 209 | #define SR_PART_NUM 0x1c, 0xff, 0 |
| 210 | #define RG_VERSION_NUM (0x1d) | 210 | #define RG_VERSION_NUM (0x1d) |
| 211 | #define SR_VERSION_NUM 0x1d, 0xff, 0 | 211 | #define SR_VERSION_NUM 0x1d, 0xff, 0 |
| 212 | #define RG_MAN_ID_0 (0x1e) | 212 | #define RG_MAN_ID_0 (0x1e) |
| 213 | #define SR_MAN_ID_0 0x1e, 0xff, 0 | 213 | #define SR_MAN_ID_0 0x1e, 0xff, 0 |
| 214 | #define RG_MAN_ID_1 (0x1f) | 214 | #define RG_MAN_ID_1 (0x1f) |
| 215 | #define SR_MAN_ID_1 0x1f, 0xff, 0 | 215 | #define SR_MAN_ID_1 0x1f, 0xff, 0 |
| 216 | #define RG_SHORT_ADDR_0 (0x20) | 216 | #define RG_SHORT_ADDR_0 (0x20) |
| 217 | #define SR_SHORT_ADDR_0 0x20, 0xff, 0 | 217 | #define SR_SHORT_ADDR_0 0x20, 0xff, 0 |
| 218 | #define RG_SHORT_ADDR_1 (0x21) | 218 | #define RG_SHORT_ADDR_1 (0x21) |
| 219 | #define SR_SHORT_ADDR_1 0x21, 0xff, 0 | 219 | #define SR_SHORT_ADDR_1 0x21, 0xff, 0 |
| 220 | #define RG_PAN_ID_0 (0x22) | 220 | #define RG_PAN_ID_0 (0x22) |
| 221 | #define SR_PAN_ID_0 0x22, 0xff, 0 | 221 | #define SR_PAN_ID_0 0x22, 0xff, 0 |
| 222 | #define RG_PAN_ID_1 (0x23) | 222 | #define RG_PAN_ID_1 (0x23) |
| 223 | #define SR_PAN_ID_1 0x23, 0xff, 0 | 223 | #define SR_PAN_ID_1 0x23, 0xff, 0 |
| 224 | #define RG_IEEE_ADDR_0 (0x24) | 224 | #define RG_IEEE_ADDR_0 (0x24) |
| 225 | #define SR_IEEE_ADDR_0 0x24, 0xff, 0 | 225 | #define SR_IEEE_ADDR_0 0x24, 0xff, 0 |
| 226 | #define RG_IEEE_ADDR_1 (0x25) | 226 | #define RG_IEEE_ADDR_1 (0x25) |
| 227 | #define SR_IEEE_ADDR_1 0x25, 0xff, 0 | 227 | #define SR_IEEE_ADDR_1 0x25, 0xff, 0 |
| 228 | #define RG_IEEE_ADDR_2 (0x26) | 228 | #define RG_IEEE_ADDR_2 (0x26) |
| 229 | #define SR_IEEE_ADDR_2 0x26, 0xff, 0 | 229 | #define SR_IEEE_ADDR_2 0x26, 0xff, 0 |
| 230 | #define RG_IEEE_ADDR_3 (0x27) | 230 | #define RG_IEEE_ADDR_3 (0x27) |
| 231 | #define SR_IEEE_ADDR_3 0x27, 0xff, 0 | 231 | #define SR_IEEE_ADDR_3 0x27, 0xff, 0 |
| 232 | #define RG_IEEE_ADDR_4 (0x28) | 232 | #define RG_IEEE_ADDR_4 (0x28) |
| 233 | #define SR_IEEE_ADDR_4 0x28, 0xff, 0 | 233 | #define SR_IEEE_ADDR_4 0x28, 0xff, 0 |
| 234 | #define RG_IEEE_ADDR_5 (0x29) | 234 | #define RG_IEEE_ADDR_5 (0x29) |
| 235 | #define SR_IEEE_ADDR_5 0x29, 0xff, 0 | 235 | #define SR_IEEE_ADDR_5 0x29, 0xff, 0 |
| 236 | #define RG_IEEE_ADDR_6 (0x2a) | 236 | #define RG_IEEE_ADDR_6 (0x2a) |
| 237 | #define SR_IEEE_ADDR_6 0x2a, 0xff, 0 | 237 | #define SR_IEEE_ADDR_6 0x2a, 0xff, 0 |
| 238 | #define RG_IEEE_ADDR_7 (0x2b) | 238 | #define RG_IEEE_ADDR_7 (0x2b) |
| 239 | #define SR_IEEE_ADDR_7 0x2b, 0xff, 0 | 239 | #define SR_IEEE_ADDR_7 0x2b, 0xff, 0 |
| 240 | #define RG_XAH_CTRL_0 (0x2c) | 240 | #define RG_XAH_CTRL_0 (0x2c) |
| 241 | #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0 | 241 | #define SR_SLOTTED_OPERATION 0x2c, 0x01, 0 |
| 242 | #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 | 242 | #define SR_MAX_CSMA_RETRIES 0x2c, 0x0e, 1 |
| 243 | #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4 | 243 | #define SR_MAX_FRAME_RETRIES 0x2c, 0xf0, 4 |
| 244 | #define RG_CSMA_SEED_0 (0x2d) | 244 | #define RG_CSMA_SEED_0 (0x2d) |
| 245 | #define SR_CSMA_SEED_0 0x2d, 0xff, 0 | 245 | #define SR_CSMA_SEED_0 0x2d, 0xff, 0 |
| 246 | #define RG_CSMA_SEED_1 (0x2e) | 246 | #define RG_CSMA_SEED_1 (0x2e) |
| 247 | #define SR_CSMA_SEED_1 0x2e, 0x07, 0 | 247 | #define SR_CSMA_SEED_1 0x2e, 0x07, 0 |
| 248 | #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3 | 248 | #define SR_AACK_I_AM_COORD 0x2e, 0x08, 3 |
| 249 | #define SR_AACK_DIS_ACK 0x2e, 0x10, 4 | 249 | #define SR_AACK_DIS_ACK 0x2e, 0x10, 4 |
| 250 | #define SR_AACK_SET_PD 0x2e, 0x20, 5 | 250 | #define SR_AACK_SET_PD 0x2e, 0x20, 5 |
| 251 | #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6 | 251 | #define SR_AACK_FVN_MODE 0x2e, 0xc0, 6 |
| 252 | #define RG_CSMA_BE (0x2f) | 252 | #define RG_CSMA_BE (0x2f) |
| 253 | #define SR_MIN_BE 0x2f, 0x0f, 0 | 253 | #define SR_MIN_BE 0x2f, 0x0f, 0 |
| 254 | #define SR_MAX_BE 0x2f, 0xf0, 4 | 254 | #define SR_MAX_BE 0x2f, 0xf0, 4 |
| 255 | 255 | ||
| 256 | #define CMD_REG 0x80 | 256 | #define CMD_REG 0x80 |
| 257 | #define CMD_REG_MASK 0x3f | 257 | #define CMD_REG_MASK 0x3f |