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authorJesse Brandeburg <jesse.brandeburg@intel.com>2013-09-11 04:40:12 -0400
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>2013-09-11 05:12:25 -0400
commit56a62fc8689509fb86bcb20768d575b81d9c311e (patch)
tree730bd7cdea03abbf5a8dfbc276d28d4063534ea4 /drivers/net
parent5c3c48ac6bf56367c4e89f6453cd2d61e50375bd (diff)
i40e: init code and hardware support
This patch implements the hardware specific init and management. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Shannon Nelson <shannon.nelson@intel.com> CC: PJ Waskiewicz <peter.p.waskiewicz.jr@intel.com> CC: e1000-devel@lists.sourceforge.net Tested-by: Kavindya Deegala <kavindya.s.deegala@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_adminq.c983
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_adminq.h112
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h2076
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_alloc.h59
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_common.c2041
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_diag.c131
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_diag.h52
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_hmc.c366
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_hmc.h245
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c1006
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_lan_hmc.h169
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_nvm.c391
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_prototype.h239
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_register.h4688
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_status.h101
-rw-r--r--drivers/net/ethernet/intel/i40e/i40e_type.h1154
16 files changed, 13813 insertions, 0 deletions
diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.c b/drivers/net/ethernet/intel/i40e/i40e_adminq.c
new file mode 100644
index 000000000000..0c524fa9f811
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq.c
@@ -0,0 +1,983 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e_status.h"
29#include "i40e_type.h"
30#include "i40e_register.h"
31#include "i40e_adminq.h"
32#include "i40e_prototype.h"
33
34/**
35 * i40e_adminq_init_regs - Initialize AdminQ registers
36 * @hw: pointer to the hardware structure
37 *
38 * This assumes the alloc_asq and alloc_arq functions have already been called
39 **/
40static void i40e_adminq_init_regs(struct i40e_hw *hw)
41{
42 /* set head and tail registers in our local struct */
43 if (hw->mac.type == I40E_MAC_VF) {
44 hw->aq.asq.tail = I40E_VF_ATQT1;
45 hw->aq.asq.head = I40E_VF_ATQH1;
46 hw->aq.arq.tail = I40E_VF_ARQT1;
47 hw->aq.arq.head = I40E_VF_ARQH1;
48 } else {
49 hw->aq.asq.tail = I40E_PF_ATQT;
50 hw->aq.asq.head = I40E_PF_ATQH;
51 hw->aq.arq.tail = I40E_PF_ARQT;
52 hw->aq.arq.head = I40E_PF_ARQH;
53 }
54}
55
56/**
57 * i40e_alloc_adminq_asq_ring - Allocate Admin Queue send rings
58 * @hw: pointer to the hardware structure
59 **/
60static i40e_status i40e_alloc_adminq_asq_ring(struct i40e_hw *hw)
61{
62 i40e_status ret_code;
63 struct i40e_virt_mem mem;
64
65 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.asq_mem,
66 i40e_mem_atq_ring,
67 (hw->aq.num_asq_entries *
68 sizeof(struct i40e_aq_desc)),
69 I40E_ADMINQ_DESC_ALIGNMENT);
70 if (ret_code)
71 return ret_code;
72
73 hw->aq.asq.desc = hw->aq.asq_mem.va;
74 hw->aq.asq.dma_addr = hw->aq.asq_mem.pa;
75
76 ret_code = i40e_allocate_virt_mem(hw, &mem,
77 (hw->aq.num_asq_entries *
78 sizeof(struct i40e_asq_cmd_details)));
79 if (ret_code) {
80 i40e_free_dma_mem(hw, &hw->aq.asq_mem);
81 hw->aq.asq_mem.va = NULL;
82 hw->aq.asq_mem.pa = 0;
83 return ret_code;
84 }
85
86 hw->aq.asq.details = mem.va;
87
88 return ret_code;
89}
90
91/**
92 * i40e_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
93 * @hw: pointer to the hardware structure
94 **/
95static i40e_status i40e_alloc_adminq_arq_ring(struct i40e_hw *hw)
96{
97 i40e_status ret_code;
98
99 ret_code = i40e_allocate_dma_mem(hw, &hw->aq.arq_mem,
100 i40e_mem_arq_ring,
101 (hw->aq.num_arq_entries *
102 sizeof(struct i40e_aq_desc)),
103 I40E_ADMINQ_DESC_ALIGNMENT);
104 if (ret_code)
105 return ret_code;
106
107 hw->aq.arq.desc = hw->aq.arq_mem.va;
108 hw->aq.arq.dma_addr = hw->aq.arq_mem.pa;
109
110 return ret_code;
111}
112
113/**
114 * i40e_free_adminq_asq - Free Admin Queue send rings
115 * @hw: pointer to the hardware structure
116 *
117 * This assumes the posted send buffers have already been cleaned
118 * and de-allocated
119 **/
120static void i40e_free_adminq_asq(struct i40e_hw *hw)
121{
122 struct i40e_virt_mem mem;
123
124 i40e_free_dma_mem(hw, &hw->aq.asq_mem);
125 hw->aq.asq_mem.va = NULL;
126 hw->aq.asq_mem.pa = 0;
127 mem.va = hw->aq.asq.details;
128 i40e_free_virt_mem(hw, &mem);
129 hw->aq.asq.details = NULL;
130}
131
132/**
133 * i40e_free_adminq_arq - Free Admin Queue receive rings
134 * @hw: pointer to the hardware structure
135 *
136 * This assumes the posted receive buffers have already been cleaned
137 * and de-allocated
138 **/
139static void i40e_free_adminq_arq(struct i40e_hw *hw)
140{
141 i40e_free_dma_mem(hw, &hw->aq.arq_mem);
142 hw->aq.arq_mem.va = NULL;
143 hw->aq.arq_mem.pa = 0;
144}
145
146/**
147 * i40e_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
148 * @hw: pointer to the hardware structure
149 **/
150static i40e_status i40e_alloc_arq_bufs(struct i40e_hw *hw)
151{
152 i40e_status ret_code;
153 struct i40e_aq_desc *desc;
154 struct i40e_virt_mem mem;
155 struct i40e_dma_mem *bi;
156 int i;
157
158 /* We'll be allocating the buffer info memory first, then we can
159 * allocate the mapped buffers for the event processing
160 */
161
162 /* buffer_info structures do not need alignment */
163 ret_code = i40e_allocate_virt_mem(hw, &mem, (hw->aq.num_arq_entries *
164 sizeof(struct i40e_dma_mem)));
165 if (ret_code)
166 goto alloc_arq_bufs;
167 hw->aq.arq.r.arq_bi = (struct i40e_dma_mem *)mem.va;
168
169 /* allocate the mapped buffers */
170 for (i = 0; i < hw->aq.num_arq_entries; i++) {
171 bi = &hw->aq.arq.r.arq_bi[i];
172 ret_code = i40e_allocate_dma_mem(hw, bi,
173 i40e_mem_arq_buf,
174 hw->aq.arq_buf_size,
175 I40E_ADMINQ_DESC_ALIGNMENT);
176 if (ret_code)
177 goto unwind_alloc_arq_bufs;
178
179 /* now configure the descriptors for use */
180 desc = I40E_ADMINQ_DESC(hw->aq.arq, i);
181
182 desc->flags = cpu_to_le16(I40E_AQ_FLAG_BUF);
183 if (hw->aq.arq_buf_size > I40E_AQ_LARGE_BUF)
184 desc->flags |= cpu_to_le16(I40E_AQ_FLAG_LB);
185 desc->opcode = 0;
186 /* This is in accordance with Admin queue design, there is no
187 * register for buffer size configuration
188 */
189 desc->datalen = cpu_to_le16((u16)bi->size);
190 desc->retval = 0;
191 desc->cookie_high = 0;
192 desc->cookie_low = 0;
193 desc->params.external.addr_high =
194 cpu_to_le32(upper_32_bits(bi->pa));
195 desc->params.external.addr_low =
196 cpu_to_le32(lower_32_bits(bi->pa));
197 desc->params.external.param0 = 0;
198 desc->params.external.param1 = 0;
199 }
200
201alloc_arq_bufs:
202 return ret_code;
203
204unwind_alloc_arq_bufs:
205 /* don't try to free the one that failed... */
206 i--;
207 for (; i >= 0; i--)
208 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
209 mem.va = hw->aq.arq.r.arq_bi;
210 i40e_free_virt_mem(hw, &mem);
211
212 return ret_code;
213}
214
215/**
216 * i40e_alloc_asq_bufs - Allocate empty buffer structs for the send queue
217 * @hw: pointer to the hardware structure
218 **/
219static i40e_status i40e_alloc_asq_bufs(struct i40e_hw *hw)
220{
221 i40e_status ret_code;
222 struct i40e_virt_mem mem;
223 struct i40e_dma_mem *bi;
224 int i;
225
226 /* No mapped memory needed yet, just the buffer info structures */
227 ret_code = i40e_allocate_virt_mem(hw, &mem, (hw->aq.num_asq_entries *
228 sizeof(struct i40e_dma_mem)));
229 if (ret_code)
230 goto alloc_asq_bufs;
231 hw->aq.asq.r.asq_bi = (struct i40e_dma_mem *)mem.va;
232
233 /* allocate the mapped buffers */
234 for (i = 0; i < hw->aq.num_asq_entries; i++) {
235 bi = &hw->aq.asq.r.asq_bi[i];
236 ret_code = i40e_allocate_dma_mem(hw, bi,
237 i40e_mem_asq_buf,
238 hw->aq.asq_buf_size,
239 I40E_ADMINQ_DESC_ALIGNMENT);
240 if (ret_code)
241 goto unwind_alloc_asq_bufs;
242 }
243alloc_asq_bufs:
244 return ret_code;
245
246unwind_alloc_asq_bufs:
247 /* don't try to free the one that failed... */
248 i--;
249 for (; i >= 0; i--)
250 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
251 mem.va = hw->aq.asq.r.asq_bi;
252 i40e_free_virt_mem(hw, &mem);
253
254 return ret_code;
255}
256
257/**
258 * i40e_free_arq_bufs - Free receive queue buffer info elements
259 * @hw: pointer to the hardware structure
260 **/
261static void i40e_free_arq_bufs(struct i40e_hw *hw)
262{
263 struct i40e_virt_mem mem;
264 int i;
265
266 for (i = 0; i < hw->aq.num_arq_entries; i++)
267 i40e_free_dma_mem(hw, &hw->aq.arq.r.arq_bi[i]);
268
269 mem.va = hw->aq.arq.r.arq_bi;
270 i40e_free_virt_mem(hw, &mem);
271}
272
273/**
274 * i40e_free_asq_bufs - Free send queue buffer info elements
275 * @hw: pointer to the hardware structure
276 **/
277static void i40e_free_asq_bufs(struct i40e_hw *hw)
278{
279 struct i40e_virt_mem mem;
280 int i;
281
282 /* only unmap if the address is non-NULL */
283 for (i = 0; i < hw->aq.num_asq_entries; i++)
284 if (hw->aq.asq.r.asq_bi[i].pa)
285 i40e_free_dma_mem(hw, &hw->aq.asq.r.asq_bi[i]);
286
287 /* now free the buffer info list */
288 mem.va = hw->aq.asq.r.asq_bi;
289 i40e_free_virt_mem(hw, &mem);
290}
291
292/**
293 * i40e_config_asq_regs - configure ASQ registers
294 * @hw: pointer to the hardware structure
295 *
296 * Configure base address and length registers for the transmit queue
297 **/
298static void i40e_config_asq_regs(struct i40e_hw *hw)
299{
300 if (hw->mac.type == I40E_MAC_VF) {
301 /* configure the transmit queue */
302 wr32(hw, I40E_VF_ATQBAH1, upper_32_bits(hw->aq.asq.dma_addr));
303 wr32(hw, I40E_VF_ATQBAL1, lower_32_bits(hw->aq.asq.dma_addr));
304 wr32(hw, I40E_VF_ATQLEN1, (hw->aq.num_asq_entries |
305 I40E_VF_ATQLEN1_ATQENABLE_MASK));
306 } else {
307 /* configure the transmit queue */
308 wr32(hw, I40E_PF_ATQBAH, upper_32_bits(hw->aq.asq.dma_addr));
309 wr32(hw, I40E_PF_ATQBAL, lower_32_bits(hw->aq.asq.dma_addr));
310 wr32(hw, I40E_PF_ATQLEN, (hw->aq.num_asq_entries |
311 I40E_PF_ATQLEN_ATQENABLE_MASK));
312 }
313}
314
315/**
316 * i40e_config_arq_regs - ARQ register configuration
317 * @hw: pointer to the hardware structure
318 *
319 * Configure base address and length registers for the receive (event queue)
320 **/
321static void i40e_config_arq_regs(struct i40e_hw *hw)
322{
323 if (hw->mac.type == I40E_MAC_VF) {
324 /* configure the receive queue */
325 wr32(hw, I40E_VF_ARQBAH1, upper_32_bits(hw->aq.arq.dma_addr));
326 wr32(hw, I40E_VF_ARQBAL1, lower_32_bits(hw->aq.arq.dma_addr));
327 wr32(hw, I40E_VF_ARQLEN1, (hw->aq.num_arq_entries |
328 I40E_VF_ARQLEN1_ARQENABLE_MASK));
329 } else {
330 /* configure the receive queue */
331 wr32(hw, I40E_PF_ARQBAH, upper_32_bits(hw->aq.arq.dma_addr));
332 wr32(hw, I40E_PF_ARQBAL, lower_32_bits(hw->aq.arq.dma_addr));
333 wr32(hw, I40E_PF_ARQLEN, (hw->aq.num_arq_entries |
334 I40E_PF_ARQLEN_ARQENABLE_MASK));
335 }
336
337 /* Update tail in the HW to post pre-allocated buffers */
338 wr32(hw, hw->aq.arq.tail, hw->aq.num_arq_entries - 1);
339}
340
341/**
342 * i40e_init_asq - main initialization routine for ASQ
343 * @hw: pointer to the hardware structure
344 *
345 * This is the main initialization routine for the Admin Send Queue
346 * Prior to calling this function, drivers *MUST* set the following fields
347 * in the hw->aq structure:
348 * - hw->aq.num_asq_entries
349 * - hw->aq.arq_buf_size
350 *
351 * Do *NOT* hold the lock when calling this as the memory allocation routines
352 * called are not going to be atomic context safe
353 **/
354static i40e_status i40e_init_asq(struct i40e_hw *hw)
355{
356 i40e_status ret_code = 0;
357
358 if (hw->aq.asq.count > 0) {
359 /* queue already initialized */
360 ret_code = I40E_ERR_NOT_READY;
361 goto init_adminq_exit;
362 }
363
364 /* verify input for valid configuration */
365 if ((hw->aq.num_asq_entries == 0) ||
366 (hw->aq.asq_buf_size == 0)) {
367 ret_code = I40E_ERR_CONFIG;
368 goto init_adminq_exit;
369 }
370
371 hw->aq.asq.next_to_use = 0;
372 hw->aq.asq.next_to_clean = 0;
373 hw->aq.asq.count = hw->aq.num_asq_entries;
374
375 /* allocate the ring memory */
376 ret_code = i40e_alloc_adminq_asq_ring(hw);
377 if (ret_code)
378 goto init_adminq_exit;
379
380 /* allocate buffers in the rings */
381 ret_code = i40e_alloc_asq_bufs(hw);
382 if (ret_code)
383 goto init_adminq_free_rings;
384
385 /* initialize base registers */
386 i40e_config_asq_regs(hw);
387
388 /* success! */
389 goto init_adminq_exit;
390
391init_adminq_free_rings:
392 i40e_free_adminq_asq(hw);
393
394init_adminq_exit:
395 return ret_code;
396}
397
398/**
399 * i40e_init_arq - initialize ARQ
400 * @hw: pointer to the hardware structure
401 *
402 * The main initialization routine for the Admin Receive (Event) Queue.
403 * Prior to calling this function, drivers *MUST* set the following fields
404 * in the hw->aq structure:
405 * - hw->aq.num_asq_entries
406 * - hw->aq.arq_buf_size
407 *
408 * Do *NOT* hold the lock when calling this as the memory allocation routines
409 * called are not going to be atomic context safe
410 **/
411static i40e_status i40e_init_arq(struct i40e_hw *hw)
412{
413 i40e_status ret_code = 0;
414
415 if (hw->aq.arq.count > 0) {
416 /* queue already initialized */
417 ret_code = I40E_ERR_NOT_READY;
418 goto init_adminq_exit;
419 }
420
421 /* verify input for valid configuration */
422 if ((hw->aq.num_arq_entries == 0) ||
423 (hw->aq.arq_buf_size == 0)) {
424 ret_code = I40E_ERR_CONFIG;
425 goto init_adminq_exit;
426 }
427
428 hw->aq.arq.next_to_use = 0;
429 hw->aq.arq.next_to_clean = 0;
430 hw->aq.arq.count = hw->aq.num_arq_entries;
431
432 /* allocate the ring memory */
433 ret_code = i40e_alloc_adminq_arq_ring(hw);
434 if (ret_code)
435 goto init_adminq_exit;
436
437 /* allocate buffers in the rings */
438 ret_code = i40e_alloc_arq_bufs(hw);
439 if (ret_code)
440 goto init_adminq_free_rings;
441
442 /* initialize base registers */
443 i40e_config_arq_regs(hw);
444
445 /* success! */
446 goto init_adminq_exit;
447
448init_adminq_free_rings:
449 i40e_free_adminq_arq(hw);
450
451init_adminq_exit:
452 return ret_code;
453}
454
455/**
456 * i40e_shutdown_asq - shutdown the ASQ
457 * @hw: pointer to the hardware structure
458 *
459 * The main shutdown routine for the Admin Send Queue
460 **/
461static i40e_status i40e_shutdown_asq(struct i40e_hw *hw)
462{
463 i40e_status ret_code = 0;
464
465 if (hw->aq.asq.count == 0)
466 return I40E_ERR_NOT_READY;
467
468 /* Stop firmware AdminQ processing */
469 if (hw->mac.type == I40E_MAC_VF)
470 wr32(hw, I40E_VF_ATQLEN1, 0);
471 else
472 wr32(hw, I40E_PF_ATQLEN, 0);
473
474 /* make sure lock is available */
475 mutex_lock(&hw->aq.asq_mutex);
476
477 hw->aq.asq.count = 0; /* to indicate uninitialized queue */
478
479 /* free ring buffers */
480 i40e_free_asq_bufs(hw);
481 /* free the ring descriptors */
482 i40e_free_adminq_asq(hw);
483
484 mutex_unlock(&hw->aq.asq_mutex);
485
486 return ret_code;
487}
488
489/**
490 * i40e_shutdown_arq - shutdown ARQ
491 * @hw: pointer to the hardware structure
492 *
493 * The main shutdown routine for the Admin Receive Queue
494 **/
495static i40e_status i40e_shutdown_arq(struct i40e_hw *hw)
496{
497 i40e_status ret_code = 0;
498
499 if (hw->aq.arq.count == 0)
500 return I40E_ERR_NOT_READY;
501
502 /* Stop firmware AdminQ processing */
503 if (hw->mac.type == I40E_MAC_VF)
504 wr32(hw, I40E_VF_ARQLEN1, 0);
505 else
506 wr32(hw, I40E_PF_ARQLEN, 0);
507
508 /* make sure lock is available */
509 mutex_lock(&hw->aq.arq_mutex);
510
511 hw->aq.arq.count = 0; /* to indicate uninitialized queue */
512
513 /* free ring buffers */
514 i40e_free_arq_bufs(hw);
515 /* free the ring descriptors */
516 i40e_free_adminq_arq(hw);
517
518 mutex_unlock(&hw->aq.arq_mutex);
519
520 return ret_code;
521}
522
523/**
524 * i40e_init_adminq - main initialization routine for Admin Queue
525 * @hw: pointer to the hardware structure
526 *
527 * Prior to calling this function, drivers *MUST* set the following fields
528 * in the hw->aq structure:
529 * - hw->aq.num_asq_entries
530 * - hw->aq.num_arq_entries
531 * - hw->aq.arq_buf_size
532 * - hw->aq.asq_buf_size
533 **/
534i40e_status i40e_init_adminq(struct i40e_hw *hw)
535{
536 u16 eetrack_lo, eetrack_hi;
537 i40e_status ret_code;
538
539 /* verify input for valid configuration */
540 if ((hw->aq.num_arq_entries == 0) ||
541 (hw->aq.num_asq_entries == 0) ||
542 (hw->aq.arq_buf_size == 0) ||
543 (hw->aq.asq_buf_size == 0)) {
544 ret_code = I40E_ERR_CONFIG;
545 goto init_adminq_exit;
546 }
547
548 /* initialize locks */
549 mutex_init(&hw->aq.asq_mutex);
550 mutex_init(&hw->aq.arq_mutex);
551
552 /* Set up register offsets */
553 i40e_adminq_init_regs(hw);
554
555 /* allocate the ASQ */
556 ret_code = i40e_init_asq(hw);
557 if (ret_code)
558 goto init_adminq_destroy_locks;
559
560 /* allocate the ARQ */
561 ret_code = i40e_init_arq(hw);
562 if (ret_code)
563 goto init_adminq_free_asq;
564
565 ret_code = i40e_aq_get_firmware_version(hw,
566 &hw->aq.fw_maj_ver, &hw->aq.fw_min_ver,
567 &hw->aq.api_maj_ver, &hw->aq.api_min_ver,
568 NULL);
569 if (ret_code)
570 goto init_adminq_free_arq;
571
572 if (hw->aq.api_maj_ver != I40E_FW_API_VERSION_MAJOR ||
573 hw->aq.api_min_ver != I40E_FW_API_VERSION_MINOR) {
574 ret_code = I40E_ERR_FIRMWARE_API_VERSION;
575 goto init_adminq_free_arq;
576 }
577 i40e_read_nvm_word(hw, I40E_SR_NVM_IMAGE_VERSION, &hw->nvm.version);
578 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_LO, &eetrack_lo);
579 i40e_read_nvm_word(hw, I40E_SR_NVM_EETRACK_HI, &eetrack_hi);
580 hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
581
582 ret_code = i40e_aq_set_hmc_resource_profile(hw,
583 I40E_HMC_PROFILE_DEFAULT,
584 0,
585 NULL);
586 ret_code = 0;
587
588 /* success! */
589 goto init_adminq_exit;
590
591init_adminq_free_arq:
592 i40e_shutdown_arq(hw);
593init_adminq_free_asq:
594 i40e_shutdown_asq(hw);
595init_adminq_destroy_locks:
596
597init_adminq_exit:
598 return ret_code;
599}
600
601/**
602 * i40e_shutdown_adminq - shutdown routine for the Admin Queue
603 * @hw: pointer to the hardware structure
604 **/
605i40e_status i40e_shutdown_adminq(struct i40e_hw *hw)
606{
607 i40e_status ret_code = 0;
608
609 i40e_shutdown_asq(hw);
610 i40e_shutdown_arq(hw);
611
612 /* destroy the locks */
613
614 return ret_code;
615}
616
617/**
618 * i40e_clean_asq - cleans Admin send queue
619 * @asq: pointer to the adminq send ring
620 *
621 * returns the number of free desc
622 **/
623static u16 i40e_clean_asq(struct i40e_hw *hw)
624{
625 struct i40e_adminq_ring *asq = &(hw->aq.asq);
626 struct i40e_asq_cmd_details *details;
627 u16 ntc = asq->next_to_clean;
628 struct i40e_aq_desc desc_cb;
629 struct i40e_aq_desc *desc;
630
631 desc = I40E_ADMINQ_DESC(*asq, ntc);
632 details = I40E_ADMINQ_DETAILS(*asq, ntc);
633 while (rd32(hw, hw->aq.asq.head) != ntc) {
634 if (details->callback) {
635 I40E_ADMINQ_CALLBACK cb_func =
636 (I40E_ADMINQ_CALLBACK)details->callback;
637 desc_cb = *desc;
638 cb_func(hw, &desc_cb);
639 }
640 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
641 memset((void *)details, 0,
642 sizeof(struct i40e_asq_cmd_details));
643 ntc++;
644 if (ntc == asq->count)
645 ntc = 0;
646 desc = I40E_ADMINQ_DESC(*asq, ntc);
647 details = I40E_ADMINQ_DETAILS(*asq, ntc);
648 }
649
650 asq->next_to_clean = ntc;
651
652 return I40E_DESC_UNUSED(asq);
653}
654
655/**
656 * i40e_asq_done - check if FW has processed the Admin Send Queue
657 * @hw: pointer to the hw struct
658 *
659 * Returns true if the firmware has processed all descriptors on the
660 * admin send queue. Returns false if there are still requests pending.
661 **/
662bool i40e_asq_done(struct i40e_hw *hw)
663{
664 /* AQ designers suggest use of head for better
665 * timing reliability than DD bit
666 */
667 return (rd32(hw, hw->aq.asq.head) == hw->aq.asq.next_to_use);
668
669}
670
671/**
672 * i40e_asq_send_command - send command to Admin Queue
673 * @hw: pointer to the hw struct
674 * @desc: prefilled descriptor describing the command (non DMA mem)
675 * @buff: buffer to use for indirect commands
676 * @buff_size: size of buffer for indirect commands
677 * @opaque: pointer to info to be used in async cleanup
678 *
679 * This is the main send command driver routine for the Admin Queue send
680 * queue. It runs the queue, cleans the queue, etc
681 **/
682i40e_status i40e_asq_send_command(struct i40e_hw *hw,
683 struct i40e_aq_desc *desc,
684 void *buff, /* can be NULL */
685 u16 buff_size,
686 struct i40e_asq_cmd_details *cmd_details)
687{
688 i40e_status status = 0;
689 struct i40e_dma_mem *dma_buff = NULL;
690 struct i40e_asq_cmd_details *details;
691 struct i40e_aq_desc *desc_on_ring;
692 bool cmd_completed = false;
693 u16 retval = 0;
694
695 if (hw->aq.asq.count == 0) {
696 i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
697 "AQTX: Admin queue not initialized.\n");
698 status = I40E_ERR_QUEUE_EMPTY;
699 goto asq_send_command_exit;
700 }
701
702 details = I40E_ADMINQ_DETAILS(hw->aq.asq, hw->aq.asq.next_to_use);
703 if (cmd_details) {
704 memcpy(details, cmd_details,
705 sizeof(struct i40e_asq_cmd_details));
706
707 /* If the cmd_details are defined copy the cookie. The
708 * cpu_to_le32 is not needed here because the data is ignored
709 * by the FW, only used by the driver
710 */
711 if (details->cookie) {
712 desc->cookie_high =
713 cpu_to_le32(upper_32_bits(details->cookie));
714 desc->cookie_low =
715 cpu_to_le32(lower_32_bits(details->cookie));
716 }
717 } else {
718 memset(details, 0, sizeof(struct i40e_asq_cmd_details));
719 }
720
721 /* clear requested flags and then set additional flags if defined */
722 desc->flags &= ~cpu_to_le16(details->flags_dis);
723 desc->flags |= cpu_to_le16(details->flags_ena);
724
725 mutex_lock(&hw->aq.asq_mutex);
726
727 if (buff_size > hw->aq.asq_buf_size) {
728 i40e_debug(hw,
729 I40E_DEBUG_AQ_MESSAGE,
730 "AQTX: Invalid buffer size: %d.\n",
731 buff_size);
732 status = I40E_ERR_INVALID_SIZE;
733 goto asq_send_command_error;
734 }
735
736 if (details->postpone && !details->async) {
737 i40e_debug(hw,
738 I40E_DEBUG_AQ_MESSAGE,
739 "AQTX: Async flag not set along with postpone flag");
740 status = I40E_ERR_PARAM;
741 goto asq_send_command_error;
742 }
743
744 /* call clean and check queue available function to reclaim the
745 * descriptors that were processed by FW, the function returns the
746 * number of desc available
747 */
748 /* the clean function called here could be called in a separate thread
749 * in case of asynchronous completions
750 */
751 if (i40e_clean_asq(hw) == 0) {
752 i40e_debug(hw,
753 I40E_DEBUG_AQ_MESSAGE,
754 "AQTX: Error queue is full.\n");
755 status = I40E_ERR_ADMIN_QUEUE_FULL;
756 goto asq_send_command_error;
757 }
758
759 /* initialize the temp desc pointer with the right desc */
760 desc_on_ring = I40E_ADMINQ_DESC(hw->aq.asq, hw->aq.asq.next_to_use);
761
762 /* if the desc is available copy the temp desc to the right place */
763 memcpy(desc_on_ring, desc, sizeof(struct i40e_aq_desc));
764
765 /* if buff is not NULL assume indirect command */
766 if (buff != NULL) {
767 dma_buff = &(hw->aq.asq.r.asq_bi[hw->aq.asq.next_to_use]);
768 /* copy the user buff into the respective DMA buff */
769 memcpy(dma_buff->va, buff, buff_size);
770 desc_on_ring->datalen = cpu_to_le16(buff_size);
771
772 /* Update the address values in the desc with the pa value
773 * for respective buffer
774 */
775 desc_on_ring->params.external.addr_high =
776 cpu_to_le32(upper_32_bits(dma_buff->pa));
777 desc_on_ring->params.external.addr_low =
778 cpu_to_le32(lower_32_bits(dma_buff->pa));
779 }
780
781 /* bump the tail */
782 i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
783 (hw->aq.asq.next_to_use)++;
784 if (hw->aq.asq.next_to_use == hw->aq.asq.count)
785 hw->aq.asq.next_to_use = 0;
786 if (!details->postpone)
787 wr32(hw, hw->aq.asq.tail, hw->aq.asq.next_to_use);
788
789 /* if cmd_details are not defined or async flag is not set,
790 * we need to wait for desc write back
791 */
792 if (!details->async && !details->postpone) {
793 u32 total_delay = 0;
794 u32 delay_len = 10;
795
796 do {
797 /* AQ designers suggest use of head for better
798 * timing reliability than DD bit
799 */
800 if (i40e_asq_done(hw))
801 break;
802 /* ugh! delay while spin_lock */
803 udelay(delay_len);
804 total_delay += delay_len;
805 } while (total_delay < I40E_ASQ_CMD_TIMEOUT);
806 }
807
808 /* if ready, copy the desc back to temp */
809 if (i40e_asq_done(hw)) {
810 memcpy(desc, desc_on_ring, sizeof(struct i40e_aq_desc));
811 if (buff != NULL)
812 memcpy(buff, dma_buff->va, buff_size);
813 retval = le16_to_cpu(desc->retval);
814 if (retval != 0) {
815 i40e_debug(hw,
816 I40E_DEBUG_AQ_MESSAGE,
817 "AQTX: Command completed with error 0x%X.\n",
818 retval);
819 /* strip off FW internal code */
820 retval &= 0xff;
821 }
822 cmd_completed = true;
823 if ((enum i40e_admin_queue_err)retval == I40E_AQ_RC_OK)
824 status = 0;
825 else
826 status = I40E_ERR_ADMIN_QUEUE_ERROR;
827 hw->aq.asq_last_status = (enum i40e_admin_queue_err)retval;
828 }
829
830 /* update the error if time out occurred */
831 if ((!cmd_completed) &&
832 (!details->async && !details->postpone)) {
833 i40e_debug(hw,
834 I40E_DEBUG_AQ_MESSAGE,
835 "AQTX: Writeback timeout.\n");
836 status = I40E_ERR_ADMIN_QUEUE_TIMEOUT;
837 }
838
839asq_send_command_error:
840 mutex_unlock(&hw->aq.asq_mutex);
841asq_send_command_exit:
842 return status;
843}
844
845/**
846 * i40e_fill_default_direct_cmd_desc - AQ descriptor helper function
847 * @desc: pointer to the temp descriptor (non DMA mem)
848 * @opcode: the opcode can be used to decide which flags to turn off or on
849 *
850 * Fill the desc with default values
851 **/
852void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
853 u16 opcode)
854{
855 /* zero out the desc */
856 memset((void *)desc, 0, sizeof(struct i40e_aq_desc));
857 desc->opcode = cpu_to_le16(opcode);
858 desc->flags = cpu_to_le16(I40E_AQ_FLAG_EI | I40E_AQ_FLAG_SI);
859}
860
861/**
862 * i40e_clean_arq_element
863 * @hw: pointer to the hw struct
864 * @e: event info from the receive descriptor, includes any buffers
865 * @pending: number of events that could be left to process
866 *
867 * This function cleans one Admin Receive Queue element and returns
868 * the contents through e. It can also return how many events are
869 * left to process through 'pending'
870 **/
871i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
872 struct i40e_arq_event_info *e,
873 u16 *pending)
874{
875 i40e_status ret_code = 0;
876 u16 ntc = hw->aq.arq.next_to_clean;
877 struct i40e_aq_desc *desc;
878 struct i40e_dma_mem *bi;
879 u16 desc_idx;
880 u16 datalen;
881 u16 flags;
882 u16 ntu;
883
884 /* take the lock before we start messing with the ring */
885 mutex_lock(&hw->aq.arq_mutex);
886
887 /* set next_to_use to head */
888 ntu = (rd32(hw, hw->aq.arq.head) & I40E_PF_ARQH_ARQH_MASK);
889 if (ntu == ntc) {
890 /* nothing to do - shouldn't need to update ring's values */
891 i40e_debug(hw,
892 I40E_DEBUG_AQ_MESSAGE,
893 "AQRX: Queue is empty.\n");
894 ret_code = I40E_ERR_ADMIN_QUEUE_NO_WORK;
895 goto clean_arq_element_out;
896 }
897
898 /* now clean the next descriptor */
899 desc = I40E_ADMINQ_DESC(hw->aq.arq, ntc);
900 desc_idx = ntc;
901 i40e_debug_aq(hw,
902 I40E_DEBUG_AQ_COMMAND,
903 (void *)desc,
904 hw->aq.arq.r.arq_bi[desc_idx].va);
905
906 flags = le16_to_cpu(desc->flags);
907 if (flags & I40E_AQ_FLAG_ERR) {
908 ret_code = I40E_ERR_ADMIN_QUEUE_ERROR;
909 hw->aq.arq_last_status =
910 (enum i40e_admin_queue_err)le16_to_cpu(desc->retval);
911 i40e_debug(hw,
912 I40E_DEBUG_AQ_MESSAGE,
913 "AQRX: Event received with error 0x%X.\n",
914 hw->aq.arq_last_status);
915 } else {
916 memcpy(&e->desc, desc, sizeof(struct i40e_aq_desc));
917 datalen = le16_to_cpu(desc->datalen);
918 e->msg_size = min(datalen, e->msg_size);
919 if (e->msg_buf != NULL && (e->msg_size != 0))
920 memcpy(e->msg_buf, hw->aq.arq.r.arq_bi[desc_idx].va,
921 e->msg_size);
922 }
923
924 /* Restore the original datalen and buffer address in the desc,
925 * FW updates datalen to indicate the event message
926 * size
927 */
928 bi = &hw->aq.arq.r.arq_bi[ntc];
929 desc->datalen = cpu_to_le16((u16)bi->size);
930 desc->params.external.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
931 desc->params.external.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
932
933 /* set tail = the last cleaned desc index. */
934 wr32(hw, hw->aq.arq.tail, ntc);
935 /* ntc is updated to tail + 1 */
936 ntc++;
937 if (ntc == hw->aq.num_arq_entries)
938 ntc = 0;
939 hw->aq.arq.next_to_clean = ntc;
940 hw->aq.arq.next_to_use = ntu;
941
942clean_arq_element_out:
943 /* Set pending if needed, unlock and return */
944 if (pending != NULL)
945 *pending = (ntc > ntu ? hw->aq.arq.count : 0) + (ntu - ntc);
946 mutex_unlock(&hw->aq.arq_mutex);
947
948 return ret_code;
949}
950
951void i40e_resume_aq(struct i40e_hw *hw)
952{
953 u32 reg = 0;
954
955 /* Registers are reset after PF reset */
956 hw->aq.asq.next_to_use = 0;
957 hw->aq.asq.next_to_clean = 0;
958
959 i40e_config_asq_regs(hw);
960 reg = hw->aq.num_asq_entries;
961
962 if (hw->mac.type == I40E_MAC_VF) {
963 reg |= I40E_VF_ATQLEN_ATQENABLE_MASK;
964 wr32(hw, I40E_VF_ATQLEN1, reg);
965 } else {
966 reg |= I40E_PF_ATQLEN_ATQENABLE_MASK;
967 wr32(hw, I40E_PF_ATQLEN, reg);
968 }
969
970 hw->aq.arq.next_to_use = 0;
971 hw->aq.arq.next_to_clean = 0;
972
973 i40e_config_arq_regs(hw);
974 reg = hw->aq.num_arq_entries;
975
976 if (hw->mac.type == I40E_MAC_VF) {
977 reg |= I40E_VF_ATQLEN_ATQENABLE_MASK;
978 wr32(hw, I40E_VF_ARQLEN1, reg);
979 } else {
980 reg |= I40E_PF_ATQLEN_ATQENABLE_MASK;
981 wr32(hw, I40E_PF_ARQLEN, reg);
982 }
983}
diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.h b/drivers/net/ethernet/intel/i40e/i40e_adminq.h
new file mode 100644
index 000000000000..22e5ed683e47
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq.h
@@ -0,0 +1,112 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_ADMINQ_H_
29#define _I40E_ADMINQ_H_
30
31#include "i40e_osdep.h"
32#include "i40e_adminq_cmd.h"
33
34#define I40E_ADMINQ_DESC(R, i) \
35 (&(((struct i40e_aq_desc *)((R).desc))[i]))
36
37#define I40E_ADMINQ_DESC_ALIGNMENT 4096
38
39struct i40e_adminq_ring {
40 void *desc; /* Descriptor ring memory */
41 void *details; /* ASQ details */
42
43 union {
44 struct i40e_dma_mem *asq_bi;
45 struct i40e_dma_mem *arq_bi;
46 } r;
47
48 u64 dma_addr; /* Physical address of the ring */
49 u16 count; /* Number of descriptors */
50 u16 rx_buf_len; /* Admin Receive Queue buffer length */
51
52 /* used for interrupt processing */
53 u16 next_to_use;
54 u16 next_to_clean;
55
56 /* used for queue tracking */
57 u32 head;
58 u32 tail;
59};
60
61/* ASQ transaction details */
62struct i40e_asq_cmd_details {
63 void *callback; /* cast from type I40E_ADMINQ_CALLBACK */
64 u64 cookie;
65 u16 flags_ena;
66 u16 flags_dis;
67 bool async;
68 bool postpone;
69};
70
71#define I40E_ADMINQ_DETAILS(R, i) \
72 (&(((struct i40e_asq_cmd_details *)((R).details))[i]))
73
74/* ARQ event information */
75struct i40e_arq_event_info {
76 struct i40e_aq_desc desc;
77 u16 msg_size;
78 u8 *msg_buf;
79};
80
81/* Admin Queue information */
82struct i40e_adminq_info {
83 struct i40e_adminq_ring arq; /* receive queue */
84 struct i40e_adminq_ring asq; /* send queue */
85 u16 num_arq_entries; /* receive queue depth */
86 u16 num_asq_entries; /* send queue depth */
87 u16 arq_buf_size; /* receive queue buffer size */
88 u16 asq_buf_size; /* send queue buffer size */
89 u16 fw_maj_ver; /* firmware major version */
90 u16 fw_min_ver; /* firmware minor version */
91 u16 api_maj_ver; /* api major version */
92 u16 api_min_ver; /* api minor version */
93
94 struct mutex asq_mutex; /* Send queue lock */
95 struct mutex arq_mutex; /* Receive queue lock */
96
97 struct i40e_dma_mem asq_mem; /* send queue dynamic memory */
98 struct i40e_dma_mem arq_mem; /* receive queue dynamic memory */
99
100 /* last status values on send and receive queues */
101 enum i40e_admin_queue_err asq_last_status;
102 enum i40e_admin_queue_err arq_last_status;
103};
104
105/* general information */
106#define I40E_AQ_LARGE_BUF 512
107#define I40E_ASQ_CMD_TIMEOUT 100000 /* usecs */
108
109void i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc,
110 u16 opcode);
111
112#endif /* _I40E_ADMINQ_H_ */
diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
new file mode 100644
index 000000000000..e61ebdd5a5f9
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq_cmd.h
@@ -0,0 +1,2076 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_ADMINQ_CMD_H_
29#define _I40E_ADMINQ_CMD_H_
30
31/* This header file defines the i40e Admin Queue commands and is shared between
32 * i40e Firmware and Software.
33 *
34 * This file needs to comply with the Linux Kernel coding style.
35 */
36
37#define I40E_FW_API_VERSION_MAJOR 0x0001
38#define I40E_FW_API_VERSION_MINOR 0x0000
39
40struct i40e_aq_desc {
41 __le16 flags;
42 __le16 opcode;
43 __le16 datalen;
44 __le16 retval;
45 __le32 cookie_high;
46 __le32 cookie_low;
47 union {
48 struct {
49 __le32 param0;
50 __le32 param1;
51 __le32 param2;
52 __le32 param3;
53 } internal;
54 struct {
55 __le32 param0;
56 __le32 param1;
57 __le32 addr_high;
58 __le32 addr_low;
59 } external;
60 u8 raw[16];
61 } params;
62};
63
64/* Flags sub-structure
65 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
66 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
67 */
68
69/* command flags and offsets*/
70#define I40E_AQ_FLAG_DD_SHIFT 0
71#define I40E_AQ_FLAG_CMP_SHIFT 1
72#define I40E_AQ_FLAG_ERR_SHIFT 2
73#define I40E_AQ_FLAG_VFE_SHIFT 3
74#define I40E_AQ_FLAG_LB_SHIFT 9
75#define I40E_AQ_FLAG_RD_SHIFT 10
76#define I40E_AQ_FLAG_VFC_SHIFT 11
77#define I40E_AQ_FLAG_BUF_SHIFT 12
78#define I40E_AQ_FLAG_SI_SHIFT 13
79#define I40E_AQ_FLAG_EI_SHIFT 14
80#define I40E_AQ_FLAG_FE_SHIFT 15
81
82#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
83#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
84#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
85#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
86#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
87#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
88#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
89#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
90#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
91#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
92#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
93
94/* error codes */
95enum i40e_admin_queue_err {
96 I40E_AQ_RC_OK = 0, /* success */
97 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
98 I40E_AQ_RC_ENOENT = 2, /* No such element */
99 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
100 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
101 I40E_AQ_RC_EIO = 5, /* I/O error */
102 I40E_AQ_RC_ENXIO = 6, /* No such resource */
103 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
104 I40E_AQ_RC_EAGAIN = 8, /* Try again */
105 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
106 I40E_AQ_RC_EACCES = 10, /* Permission denied */
107 I40E_AQ_RC_EFAULT = 11, /* Bad address */
108 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
109 I40E_AQ_RC_EEXIST = 13, /* object already exists */
110 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
111 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
112 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
113 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
114 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
115 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed because of prev cmd error */
116 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
117 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
118 I40E_AQ_RC_EFBIG = 22, /* File too large */
119};
120
121/* Admin Queue command opcodes */
122enum i40e_admin_queue_opc {
123 /* aq commands */
124 i40e_aqc_opc_get_version = 0x0001,
125 i40e_aqc_opc_driver_version = 0x0002,
126 i40e_aqc_opc_queue_shutdown = 0x0003,
127
128 /* resource ownership */
129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
131
132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
134
135 i40e_aqc_opc_set_cppm_configuration = 0x0103,
136 i40e_aqc_opc_set_arp_proxy_entry = 0x0104,
137 i40e_aqc_opc_set_ns_proxy_entry = 0x0105,
138
139 /* LAA */
140 i40e_aqc_opc_mng_laa = 0x0106,
141 i40e_aqc_opc_mac_address_read = 0x0107,
142 i40e_aqc_opc_mac_address_write = 0x0108,
143
144 /* internal switch commands */
145 i40e_aqc_opc_get_switch_config = 0x0200,
146 i40e_aqc_opc_add_statistics = 0x0201,
147 i40e_aqc_opc_remove_statistics = 0x0202,
148 i40e_aqc_opc_set_port_parameters = 0x0203,
149 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
150
151 i40e_aqc_opc_add_vsi = 0x0210,
152 i40e_aqc_opc_update_vsi_parameters = 0x0211,
153 i40e_aqc_opc_get_vsi_parameters = 0x0212,
154
155 i40e_aqc_opc_add_pv = 0x0220,
156 i40e_aqc_opc_update_pv_parameters = 0x0221,
157 i40e_aqc_opc_get_pv_parameters = 0x0222,
158
159 i40e_aqc_opc_add_veb = 0x0230,
160 i40e_aqc_opc_update_veb_parameters = 0x0231,
161 i40e_aqc_opc_get_veb_parameters = 0x0232,
162
163 i40e_aqc_opc_delete_element = 0x0243,
164
165 i40e_aqc_opc_add_macvlan = 0x0250,
166 i40e_aqc_opc_remove_macvlan = 0x0251,
167 i40e_aqc_opc_add_vlan = 0x0252,
168 i40e_aqc_opc_remove_vlan = 0x0253,
169 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
170 i40e_aqc_opc_add_tag = 0x0255,
171 i40e_aqc_opc_remove_tag = 0x0256,
172 i40e_aqc_opc_add_multicast_etag = 0x0257,
173 i40e_aqc_opc_remove_multicast_etag = 0x0258,
174 i40e_aqc_opc_update_tag = 0x0259,
175 i40e_aqc_opc_add_control_packet_filter = 0x025A,
176 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
177 i40e_aqc_opc_add_cloud_filters = 0x025C,
178 i40e_aqc_opc_remove_cloud_filters = 0x025D,
179
180 i40e_aqc_opc_add_mirror_rule = 0x0260,
181 i40e_aqc_opc_delete_mirror_rule = 0x0261,
182
183 i40e_aqc_opc_set_storm_control_config = 0x0280,
184 i40e_aqc_opc_get_storm_control_config = 0x0281,
185
186 /* DCB commands */
187 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
188 i40e_aqc_opc_dcb_updated = 0x0302,
189
190 /* TX scheduler */
191 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
192 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
193 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
194 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
195 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
196 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
197
198 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
199 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
200 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
201 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
202 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
203 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
204 i40e_aqc_opc_query_port_ets_config = 0x0419,
205 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
206 i40e_aqc_opc_suspend_port_tx = 0x041B,
207 i40e_aqc_opc_resume_port_tx = 0x041C,
208
209 /* hmc */
210 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
211 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
212
213 /* phy commands*/
214 i40e_aqc_opc_get_phy_abilities = 0x0600,
215 i40e_aqc_opc_set_phy_config = 0x0601,
216 i40e_aqc_opc_set_mac_config = 0x0603,
217 i40e_aqc_opc_set_link_restart_an = 0x0605,
218 i40e_aqc_opc_get_link_status = 0x0607,
219 i40e_aqc_opc_set_phy_int_mask = 0x0613,
220 i40e_aqc_opc_get_local_advt_reg = 0x0614,
221 i40e_aqc_opc_set_local_advt_reg = 0x0615,
222 i40e_aqc_opc_get_partner_advt = 0x0616,
223 i40e_aqc_opc_set_lb_modes = 0x0618,
224 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
225 i40e_aqc_opc_set_phy_reset = 0x0622,
226 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
227
228 /* NVM commands */
229 i40e_aqc_opc_nvm_read = 0x0701,
230 i40e_aqc_opc_nvm_erase = 0x0702,
231 i40e_aqc_opc_nvm_update = 0x0703,
232
233 /* virtualization commands */
234 i40e_aqc_opc_send_msg_to_pf = 0x0801,
235 i40e_aqc_opc_send_msg_to_vf = 0x0802,
236 i40e_aqc_opc_send_msg_to_peer = 0x0803,
237
238 /* alternate structure */
239 i40e_aqc_opc_alternate_write = 0x0900,
240 i40e_aqc_opc_alternate_write_indirect = 0x0901,
241 i40e_aqc_opc_alternate_read = 0x0902,
242 i40e_aqc_opc_alternate_read_indirect = 0x0903,
243 i40e_aqc_opc_alternate_write_done = 0x0904,
244 i40e_aqc_opc_alternate_set_mode = 0x0905,
245 i40e_aqc_opc_alternate_clear_port = 0x0906,
246
247 /* LLDP commands */
248 i40e_aqc_opc_lldp_get_mib = 0x0A00,
249 i40e_aqc_opc_lldp_update_mib = 0x0A01,
250 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
251 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
252 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
253 i40e_aqc_opc_lldp_stop = 0x0A05,
254 i40e_aqc_opc_lldp_start = 0x0A06,
255
256 /* Tunnel commands */
257 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
258 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
259 i40e_aqc_opc_tunnel_key_structure = 0x0B10,
260
261 /* Async Events */
262 i40e_aqc_opc_event_lan_overflow = 0x1001,
263
264 /* OEM commands */
265 i40e_aqc_opc_oem_parameter_change = 0xFE00,
266 i40e_aqc_opc_oem_device_status_change = 0xFE01,
267
268 /* debug commands */
269 i40e_aqc_opc_debug_get_deviceid = 0xFF00,
270 i40e_aqc_opc_debug_set_mode = 0xFF01,
271 i40e_aqc_opc_debug_read_reg = 0xFF03,
272 i40e_aqc_opc_debug_write_reg = 0xFF04,
273 i40e_aqc_opc_debug_read_reg_sg = 0xFF05,
274 i40e_aqc_opc_debug_write_reg_sg = 0xFF06,
275 i40e_aqc_opc_debug_modify_reg = 0xFF07,
276 i40e_aqc_opc_debug_dump_internals = 0xFF08,
277 i40e_aqc_opc_debug_modify_internals = 0xFF09,
278};
279
280/* command structures and indirect data structures */
281
282/* Structure naming conventions:
283 * - no suffix for direct command descriptor structures
284 * - _data for indirect sent data
285 * - _resp for indirect return data (data which is both will use _data)
286 * - _completion for direct return data
287 * - _element_ for repeated elements (may also be _data or _resp)
288 *
289 * Command structures are expected to overlay the params.raw member of the basic
290 * descriptor, and as such cannot exceed 16 bytes in length.
291 */
292
293/* This macro is used to generate a compilation error if a structure
294 * is not exactly the correct length. It gives a divide by zero error if the
295 * structure is not of the correct size, otherwise it creates an enum that is
296 * never used.
297 */
298#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
299 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
300
301/* This macro is used extensively to ensure that command structures are 16
302 * bytes in length as they have to map to the raw array of that size.
303 */
304#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
305
306/* internal (0x00XX) commands */
307
308/* Get version (direct 0x0001) */
309struct i40e_aqc_get_version {
310 __le32 rom_ver;
311 __le32 fw_build;
312 __le16 fw_major;
313 __le16 fw_minor;
314 __le16 api_major;
315 __le16 api_minor;
316};
317
318I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
319
320/* Send driver version (direct 0x0002) */
321struct i40e_aqc_driver_version {
322 u8 driver_major_ver;
323 u8 driver_minor_ver;
324 u8 driver_build_ver;
325 u8 driver_subbuild_ver;
326 u8 reserved[12];
327};
328
329I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
330
331/* Queue Shutdown (direct 0x0003) */
332struct i40e_aqc_queue_shutdown {
333 __le32 driver_unloading;
334#define I40E_AQ_DRIVER_UNLOADING 0x1
335 u8 reserved[12];
336};
337
338I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
339
340/* Request resource ownership (direct 0x0008)
341 * Release resource ownership (direct 0x0009)
342 */
343#define I40E_AQ_RESOURCE_NVM 1
344#define I40E_AQ_RESOURCE_SDP 2
345#define I40E_AQ_RESOURCE_ACCESS_READ 1
346#define I40E_AQ_RESOURCE_ACCESS_WRITE 2
347#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
348#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
349
350struct i40e_aqc_request_resource {
351 __le16 resource_id;
352 __le16 access_type;
353 __le32 timeout;
354 __le32 resource_number;
355 u8 reserved[4];
356};
357
358I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
359
360/* Get function capabilities (indirect 0x000A)
361 * Get device capabilities (indirect 0x000B)
362 */
363struct i40e_aqc_list_capabilites {
364 u8 command_flags;
365#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
366 u8 pf_index;
367 u8 reserved[2];
368 __le32 count;
369 __le32 addr_high;
370 __le32 addr_low;
371};
372
373I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
374
375struct i40e_aqc_list_capabilities_element_resp {
376 __le16 id;
377 u8 major_rev;
378 u8 minor_rev;
379 __le32 number;
380 __le32 logical_id;
381 __le32 phys_id;
382 u8 reserved[16];
383};
384
385/* list of caps */
386
387#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
388#define I40E_AQ_CAP_ID_MNG_MODE 0x0002
389#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
390#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
391#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
392#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
393#define I40E_AQ_CAP_ID_SRIOV 0x0012
394#define I40E_AQ_CAP_ID_VF 0x0013
395#define I40E_AQ_CAP_ID_VMDQ 0x0014
396#define I40E_AQ_CAP_ID_8021QBG 0x0015
397#define I40E_AQ_CAP_ID_8021QBR 0x0016
398#define I40E_AQ_CAP_ID_VSI 0x0017
399#define I40E_AQ_CAP_ID_DCB 0x0018
400#define I40E_AQ_CAP_ID_FCOE 0x0021
401#define I40E_AQ_CAP_ID_RSS 0x0040
402#define I40E_AQ_CAP_ID_RXQ 0x0041
403#define I40E_AQ_CAP_ID_TXQ 0x0042
404#define I40E_AQ_CAP_ID_MSIX 0x0043
405#define I40E_AQ_CAP_ID_VF_MSIX 0x0044
406#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
407#define I40E_AQ_CAP_ID_1588 0x0046
408#define I40E_AQ_CAP_ID_IWARP 0x0051
409#define I40E_AQ_CAP_ID_LED 0x0061
410#define I40E_AQ_CAP_ID_SDP 0x0062
411#define I40E_AQ_CAP_ID_MDIO 0x0063
412#define I40E_AQ_CAP_ID_FLEX10 0x00F1
413#define I40E_AQ_CAP_ID_CEM 0x00F2
414
415/* Set CPPM Configuration (direct 0x0103) */
416struct i40e_aqc_cppm_configuration {
417 __le16 command_flags;
418#define I40E_AQ_CPPM_EN_LTRC 0x0800
419#define I40E_AQ_CPPM_EN_DMCTH 0x1000
420#define I40E_AQ_CPPM_EN_DMCTLX 0x2000
421#define I40E_AQ_CPPM_EN_HPTC 0x4000
422#define I40E_AQ_CPPM_EN_DMARC 0x8000
423 __le16 ttlx;
424 __le32 dmacr;
425 __le16 dmcth;
426 u8 hptc;
427 u8 reserved;
428 __le32 pfltrc;
429};
430
431I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
432
433/* Set ARP Proxy command / response (indirect 0x0104) */
434struct i40e_aqc_arp_proxy_data {
435 __le16 command_flags;
436#define I40E_AQ_ARP_INIT_IPV4 0x0008
437#define I40E_AQ_ARP_UNSUP_CTL 0x0010
438#define I40E_AQ_ARP_ENA 0x0020
439#define I40E_AQ_ARP_ADD_IPV4 0x0040
440#define I40E_AQ_ARP_DEL_IPV4 0x0080
441 __le16 table_id;
442 __le32 pfpm_proxyfc;
443 __le32 ip_addr;
444 u8 mac_addr[6];
445};
446
447/* Set NS Proxy Table Entry Command (indirect 0x0105) */
448struct i40e_aqc_ns_proxy_data {
449 __le16 table_idx_mac_addr_0;
450 __le16 table_idx_mac_addr_1;
451 __le16 table_idx_ipv6_0;
452 __le16 table_idx_ipv6_1;
453 __le16 control;
454#define I40E_AQ_NS_PROXY_ADD_0 0x0100
455#define I40E_AQ_NS_PROXY_DEL_0 0x0200
456#define I40E_AQ_NS_PROXY_ADD_1 0x0400
457#define I40E_AQ_NS_PROXY_DEL_1 0x0800
458#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
459#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
460#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
461#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
462#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
463#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
464#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
465 u8 mac_addr_0[6];
466 u8 mac_addr_1[6];
467 u8 local_mac_addr[6];
468 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
469 u8 ipv6_addr_1[16];
470};
471
472/* Manage LAA Command (0x0106) - obsolete */
473struct i40e_aqc_mng_laa {
474 __le16 command_flags;
475#define I40E_AQ_LAA_FLAG_WR 0x8000
476 u8 reserved[2];
477 __le32 sal;
478 __le16 sah;
479 u8 reserved2[6];
480};
481
482/* Manage MAC Address Read Command (0x0107) */
483struct i40e_aqc_mac_address_read {
484 __le16 command_flags;
485#define I40E_AQC_LAN_ADDR_VALID 0x10
486#define I40E_AQC_SAN_ADDR_VALID 0x20
487#define I40E_AQC_PORT_ADDR_VALID 0x40
488#define I40E_AQC_WOL_ADDR_VALID 0x80
489#define I40E_AQC_ADDR_VALID_MASK 0xf0
490 u8 reserved[6];
491 __le32 addr_high;
492 __le32 addr_low;
493};
494
495I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
496
497struct i40e_aqc_mac_address_read_data {
498 u8 pf_lan_mac[6];
499 u8 pf_san_mac[6];
500 u8 port_mac[6];
501 u8 pf_wol_mac[6];
502};
503
504I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
505
506/* Manage MAC Address Write Command (0x0108) */
507struct i40e_aqc_mac_address_write {
508 __le16 command_flags;
509#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
510#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
511#define I40E_AQC_WRITE_TYPE_PORT 0x8000
512#define I40E_AQC_WRITE_TYPE_MASK 0xc000
513 __le16 mac_sah;
514 __le32 mac_sal;
515 u8 reserved[8];
516};
517
518I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
519
520/* Switch configuration commands (0x02xx) */
521
522/* Used by many indirect commands that only pass an seid and a buffer in the
523 * command
524 */
525struct i40e_aqc_switch_seid {
526 __le16 seid;
527 u8 reserved[6];
528 __le32 addr_high;
529 __le32 addr_low;
530};
531
532I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
533
534/* Get Switch Configuration command (indirect 0x0200)
535 * uses i40e_aqc_switch_seid for the descriptor
536 */
537struct i40e_aqc_get_switch_config_header_resp {
538 __le16 num_reported;
539 __le16 num_total;
540 u8 reserved[12];
541};
542
543struct i40e_aqc_switch_config_element_resp {
544 u8 element_type;
545#define I40E_AQ_SW_ELEM_TYPE_MAC 1
546#define I40E_AQ_SW_ELEM_TYPE_PF 2
547#define I40E_AQ_SW_ELEM_TYPE_VF 3
548#define I40E_AQ_SW_ELEM_TYPE_EMP 4
549#define I40E_AQ_SW_ELEM_TYPE_BMC 5
550#define I40E_AQ_SW_ELEM_TYPE_PV 16
551#define I40E_AQ_SW_ELEM_TYPE_VEB 17
552#define I40E_AQ_SW_ELEM_TYPE_PA 18
553#define I40E_AQ_SW_ELEM_TYPE_VSI 19
554 u8 revision;
555#define I40E_AQ_SW_ELEM_REV_1 1
556 __le16 seid;
557 __le16 uplink_seid;
558 __le16 downlink_seid;
559 u8 reserved[3];
560 u8 connection_type;
561#define I40E_AQ_CONN_TYPE_REGULAR 0x1
562#define I40E_AQ_CONN_TYPE_DEFAULT 0x2
563#define I40E_AQ_CONN_TYPE_CASCADED 0x3
564 __le16 scheduler_id;
565 __le16 element_info;
566};
567
568/* Get Switch Configuration (indirect 0x0200)
569 * an array of elements are returned in the response buffer
570 * the first in the array is the header, remainder are elements
571 */
572struct i40e_aqc_get_switch_config_resp {
573 struct i40e_aqc_get_switch_config_header_resp header;
574 struct i40e_aqc_switch_config_element_resp element[1];
575};
576
577/* Add Statistics (direct 0x0201)
578 * Remove Statistics (direct 0x0202)
579 */
580struct i40e_aqc_add_remove_statistics {
581 __le16 seid;
582 __le16 vlan;
583 __le16 stat_index;
584 u8 reserved[10];
585};
586
587I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
588
589/* Set Port Parameters command (direct 0x0203) */
590struct i40e_aqc_set_port_parameters {
591 __le16 command_flags;
592#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
593#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
594#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
595 __le16 bad_frame_vsi;
596 __le16 default_seid; /* reserved for command */
597 u8 reserved[10];
598};
599
600I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
601
602/* Get Switch Resource Allocation (indirect 0x0204) */
603struct i40e_aqc_get_switch_resource_alloc {
604 u8 num_entries; /* reserved for command */
605 u8 reserved[7];
606 __le32 addr_high;
607 __le32 addr_low;
608};
609
610I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
611
612/* expect an array of these structs in the response buffer */
613struct i40e_aqc_switch_resource_alloc_element_resp {
614 u8 resource_type;
615#define I40E_AQ_RESOURCE_TYPE_VEB 0x0
616#define I40E_AQ_RESOURCE_TYPE_VSI 0x1
617#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
618#define I40E_AQ_RESOURCE_TYPE_STAG 0x3
619#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
620#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
621#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
622#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
623#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
624#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
625#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
626#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
627#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
628#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
629#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
630#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
631#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
632#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
633#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
634 u8 reserved1;
635 __le16 guaranteed;
636 __le16 total;
637 __le16 used;
638 __le16 total_unalloced;
639 u8 reserved2[6];
640};
641
642/* Add VSI (indirect 0x210)
643 * this indirect command uses struct i40e_aqc_vsi_properties_data
644 * as the indirect buffer (128 bytes)
645 *
646 * Update VSI (indirect 0x211) Get VSI (indirect 0x0212)
647 * use the generic i40e_aqc_switch_seid descriptor format
648 * use the same completion and data structure as Add VSI
649 */
650struct i40e_aqc_add_get_update_vsi {
651 __le16 uplink_seid;
652 u8 connection_type;
653#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
654#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
655#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
656 u8 reserved1;
657 u8 vf_id;
658 u8 reserved2;
659 __le16 vsi_flags;
660#define I40E_AQ_VSI_TYPE_SHIFT 0x0
661#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
662#define I40E_AQ_VSI_TYPE_VF 0x0
663#define I40E_AQ_VSI_TYPE_VMDQ2 0x1
664#define I40E_AQ_VSI_TYPE_PF 0x2
665#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
666#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
667#define I40E_AQ_VSI_FLAG_CLOUD_VSI 0x8
668 __le32 addr_high;
669 __le32 addr_low;
670};
671
672I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
673
674struct i40e_aqc_add_get_update_vsi_completion {
675 __le16 seid;
676 __le16 vsi_number;
677 __le16 vsi_used;
678 __le16 vsi_free;
679 __le32 addr_high;
680 __le32 addr_low;
681};
682
683I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
684
685struct i40e_aqc_vsi_properties_data {
686 /* first 96 byte are written by SW */
687 __le16 valid_sections;
688#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
689#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
690#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
691#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
692#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
693#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
694#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
695#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
696#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
697#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
698 /* switch section */
699 __le16 switch_id; /* 12bit id combined with flags below */
700#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
701#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
702#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
703#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
704#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
705 u8 sw_reserved[2];
706 /* security section */
707 u8 sec_flags;
708#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
709#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
710#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
711 u8 sec_reserved;
712 /* VLAN section */
713 __le16 pvid; /* VLANS include priority bits */
714 __le16 fcoe_pvid;
715 u8 port_vlan_flags;
716#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
717#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
718 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
719#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
720#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
721#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
722#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
723#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
724#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
725 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
726#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
727#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
728#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
729#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
730 u8 pvlan_reserved[3];
731 /* ingress egress up sections */
732 __le32 ingress_table; /* bitmap, 3 bits per up */
733#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
734#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
735 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
736#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
737#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
738 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
739#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
740#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
741 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
742#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
743#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
744 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
745#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
746#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
747 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
748#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
749#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
750 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
751#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
752#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
753 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
754#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
755#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
756 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
757 __le32 egress_table; /* same defines as for ingress table */
758 /* cascaded PV section */
759 __le16 cas_pv_tag;
760 u8 cas_pv_flags;
761#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
762#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
763 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
764#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
765#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
766#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
767#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
768#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
769#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
770 u8 cas_pv_reserved;
771 /* queue mapping section */
772 __le16 mapping_flags;
773#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
774#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
775 __le16 queue_mapping[16];
776#define I40E_AQ_VSI_QUEUE_SHIFT 0x0
777#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
778 __le16 tc_mapping[8];
779#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
780#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
781 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
782#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
783#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
784 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
785 /* queueing option section */
786 u8 queueing_opt_flags;
787#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
788#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
789 u8 queueing_opt_reserved[3];
790 /* scheduler section */
791 u8 up_enable_bits;
792 u8 sched_reserved;
793 /* outer up section */
794 __le32 outer_up_table; /* same structure and defines as ingress table */
795 u8 cmd_reserved[8];
796 /* last 32 bytes are written by FW */
797 __le16 qs_handle[8];
798#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
799 __le16 stat_counter_idx;
800 __le16 sched_id;
801 u8 resp_reserved[12];
802};
803
804I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
805
806/* Add Port Virtualizer (direct 0x0220)
807 * also used for update PV (direct 0x0221) but only flags are used
808 * (IS_CTRL_PORT only works on add PV)
809 */
810struct i40e_aqc_add_update_pv {
811 __le16 command_flags;
812#define I40E_AQC_PV_FLAG_PV_TYPE 0x1
813#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
814#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
815#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
816 __le16 uplink_seid;
817 __le16 connected_seid;
818 u8 reserved[10];
819};
820
821I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
822
823struct i40e_aqc_add_update_pv_completion {
824 /* reserved for update; for add also encodes error if rc == ENOSPC */
825 __le16 pv_seid;
826#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
827#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
828#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
829#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
830 u8 reserved[14];
831};
832
833I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
834
835/* Get PV Params (direct 0x0222)
836 * uses i40e_aqc_switch_seid for the descriptor
837 */
838
839struct i40e_aqc_get_pv_params_completion {
840 __le16 seid;
841 __le16 default_stag;
842 __le16 pv_flags; /* same flags as add_pv */
843#define I40E_AQC_GET_PV_PV_TYPE 0x1
844#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
845#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
846 u8 reserved[8];
847 __le16 default_port_seid;
848};
849
850I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
851
852/* Add VEB (direct 0x0230) */
853struct i40e_aqc_add_veb {
854 __le16 uplink_seid;
855 __le16 downlink_seid;
856 __le16 veb_flags;
857#define I40E_AQC_ADD_VEB_FLOATING 0x1
858#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
859#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
860 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
861#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
862#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
863#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8
864 u8 enable_tcs;
865 u8 reserved[9];
866};
867
868I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
869
870struct i40e_aqc_add_veb_completion {
871 u8 reserved[6];
872 __le16 switch_seid;
873 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
874 __le16 veb_seid;
875#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
876#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
877#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
878#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
879 __le16 statistic_index;
880 __le16 vebs_used;
881 __le16 vebs_free;
882};
883
884I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
885
886/* Get VEB Parameters (direct 0x0232)
887 * uses i40e_aqc_switch_seid for the descriptor
888 */
889struct i40e_aqc_get_veb_parameters_completion {
890 __le16 seid;
891 __le16 switch_id;
892 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
893 __le16 statistic_index;
894 __le16 vebs_used;
895 __le16 vebs_free;
896 u8 reserved[4];
897};
898
899I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
900
901/* Delete Element (direct 0x0243)
902 * uses the generic i40e_aqc_switch_seid
903 */
904
905/* Add MAC-VLAN (indirect 0x0250) */
906
907/* used for the command for most vlan commands */
908struct i40e_aqc_macvlan {
909 __le16 num_addresses;
910 __le16 seid[3];
911#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
912#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
913 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
914#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
915 __le32 addr_high;
916 __le32 addr_low;
917};
918
919I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
920
921/* indirect data for command and response */
922struct i40e_aqc_add_macvlan_element_data {
923 u8 mac_addr[6];
924 __le16 vlan_tag;
925 __le16 flags;
926#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
927#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
928#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
929#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
930 __le16 queue_number;
931#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
932#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
933 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
934 /* response section */
935 u8 match_method;
936#define I40E_AQC_MM_PERFECT_MATCH 0x01
937#define I40E_AQC_MM_HASH_MATCH 0x02
938#define I40E_AQC_MM_ERR_NO_RES 0xFF
939 u8 reserved1[3];
940};
941
942struct i40e_aqc_add_remove_macvlan_completion {
943 __le16 perfect_mac_used;
944 __le16 perfect_mac_free;
945 __le16 unicast_hash_free;
946 __le16 multicast_hash_free;
947 __le32 addr_high;
948 __le32 addr_low;
949};
950
951I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
952
953/* Remove MAC-VLAN (indirect 0x0251)
954 * uses i40e_aqc_macvlan for the descriptor
955 * data points to an array of num_addresses of elements
956 */
957
958struct i40e_aqc_remove_macvlan_element_data {
959 u8 mac_addr[6];
960 __le16 vlan_tag;
961 u8 flags;
962#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
963#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
964#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
965#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
966 u8 reserved[3];
967 /* reply section */
968 u8 error_code;
969#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
970#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
971 u8 reply_reserved[3];
972};
973
974/* Add VLAN (indirect 0x0252)
975 * Remove VLAN (indirect 0x0253)
976 * use the generic i40e_aqc_macvlan for the command
977 */
978struct i40e_aqc_add_remove_vlan_element_data {
979 __le16 vlan_tag;
980 u8 vlan_flags;
981/* flags for add VLAN */
982#define I40E_AQC_ADD_VLAN_LOCAL 0x1
983#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
984#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << \
985 I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
986#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
987#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
988#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
989#define I40E_AQC_VLAN_PTYPE_SHIFT 3
990#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
991#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
992#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
993#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
994#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
995/* flags for remove VLAN */
996#define I40E_AQC_REMOVE_VLAN_ALL 0x1
997 u8 reserved;
998 u8 result;
999/* flags for add VLAN */
1000#define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1001#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1002#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1003/* flags for remove VLAN */
1004#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1005#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1006 u8 reserved1[3];
1007};
1008
1009struct i40e_aqc_add_remove_vlan_completion {
1010 u8 reserved[4];
1011 __le16 vlans_used;
1012 __le16 vlans_free;
1013 __le32 addr_high;
1014 __le32 addr_low;
1015};
1016
1017/* Set VSI Promiscuous Modes (direct 0x0254) */
1018struct i40e_aqc_set_vsi_promiscuous_modes {
1019 __le16 promiscuous_flags;
1020 __le16 valid_flags;
1021/* flags used for both fields above */
1022#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1023#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1024#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1025#define I40E_AQC_SET_VSI_DEFAULT 0x08
1026#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1027 __le16 seid;
1028#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1029 u8 reserved[10];
1030};
1031
1032I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1033
1034/* Add S/E-tag command (direct 0x0255)
1035 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1036 */
1037struct i40e_aqc_add_tag {
1038 __le16 flags;
1039#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1040 __le16 seid;
1041#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1042#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1043 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1044 __le16 tag;
1045 __le16 queue_number;
1046 u8 reserved[8];
1047};
1048
1049I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1050
1051struct i40e_aqc_add_remove_tag_completion {
1052 u8 reserved[12];
1053 __le16 tags_used;
1054 __le16 tags_free;
1055};
1056
1057I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1058
1059/* Remove S/E-tag command (direct 0x0256)
1060 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1061 */
1062struct i40e_aqc_remove_tag {
1063 __le16 seid;
1064#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1065#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1066 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1067 __le16 tag;
1068 u8 reserved[12];
1069};
1070
1071/* Add multicast E-Tag (direct 0x0257)
1072 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1073 * and no external data
1074 */
1075struct i40e_aqc_add_remove_mcast_etag {
1076 __le16 pv_seid;
1077 __le16 etag;
1078 u8 num_unicast_etags;
1079 u8 reserved[3];
1080 __le32 addr_high; /* address of array of 2-byte s-tags */
1081 __le32 addr_low;
1082};
1083
1084I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1085
1086struct i40e_aqc_add_remove_mcast_etag_completion {
1087 u8 reserved[4];
1088 __le16 mcast_etags_used;
1089 __le16 mcast_etags_free;
1090 __le32 addr_high;
1091 __le32 addr_low;
1092
1093};
1094
1095I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1096
1097/* Update S/E-Tag (direct 0x0259) */
1098struct i40e_aqc_update_tag {
1099 __le16 seid;
1100#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1101#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1102 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1103 __le16 old_tag;
1104 __le16 new_tag;
1105 u8 reserved[10];
1106};
1107
1108I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1109
1110struct i40e_aqc_update_tag_completion {
1111 u8 reserved[12];
1112 __le16 tags_used;
1113 __le16 tags_free;
1114};
1115
1116I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1117
1118/* Add Control Packet filter (direct 0x025A)
1119 * Remove Control Packet filter (direct 0x025B)
1120 * uses the i40e_aqc_add_oveb_cloud,
1121 * and the generic direct completion structure
1122 */
1123struct i40e_aqc_add_remove_control_packet_filter {
1124 u8 mac[6];
1125 __le16 etype;
1126 __le16 flags;
1127#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1128#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1129#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1130#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1131#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1132 __le16 seid;
1133#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1134#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1135 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1136 __le16 queue;
1137 u8 reserved[2];
1138};
1139
1140I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1141
1142struct i40e_aqc_add_remove_control_packet_filter_completion {
1143 __le16 mac_etype_used;
1144 __le16 etype_used;
1145 __le16 mac_etype_free;
1146 __le16 etype_free;
1147 u8 reserved[8];
1148};
1149
1150I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1151
1152/* Add Cloud filters (indirect 0x025C)
1153 * Remove Cloud filters (indirect 0x025D)
1154 * uses the i40e_aqc_add_remove_cloud_filters,
1155 * and the generic indirect completion structure
1156 */
1157struct i40e_aqc_add_remove_cloud_filters {
1158 u8 num_filters;
1159 u8 reserved;
1160 __le16 seid;
1161#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1162#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1163 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1164 u8 reserved2[4];
1165 __le32 addr_high;
1166 __le32 addr_low;
1167};
1168
1169I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1170
1171struct i40e_aqc_add_remove_cloud_filters_element_data {
1172 u8 outer_mac[6];
1173 u8 inner_mac[6];
1174 __le16 inner_vlan;
1175 union {
1176 struct {
1177 u8 reserved[12];
1178 u8 data[4];
1179 } v4;
1180 struct {
1181 u8 data[16];
1182 } v6;
1183 } ipaddr;
1184 __le16 flags;
1185#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1186#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1187 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1188#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1189#define I40E_AQC_ADD_CLOUD_FILTER_OIP_GRE 0x0002
1190#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1191#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_GRE 0x0004
1192#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1193#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_VNL 0x0007
1194/* 0x0008 reserved */
1195#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1196#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1197#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1198#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1199#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1200#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1201#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1202 __le32 key_low;
1203 __le32 key_high;
1204 __le16 queue_number;
1205#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1206#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \
1207 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1208 u8 reserved[14];
1209 /* response section */
1210 u8 allocation_result;
1211#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1212#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1213 u8 response_reserved[7];
1214};
1215
1216struct i40e_aqc_remove_cloud_filters_completion {
1217 __le16 perfect_ovlan_used;
1218 __le16 perfect_ovlan_free;
1219 __le16 vlan_used;
1220 __le16 vlan_free;
1221 __le32 addr_high;
1222 __le32 addr_low;
1223};
1224
1225I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1226
1227/* Add Mirror Rule (indirect or direct 0x0260)
1228 * Delete Mirror Rule (indirect or direct 0x0261)
1229 * note: some rule types (4,5) do not use an external buffer.
1230 * take care to set the flags correctly.
1231 */
1232struct i40e_aqc_add_delete_mirror_rule {
1233 __le16 seid;
1234 __le16 rule_type;
1235#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1236#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1237 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1238#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1239#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1240#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1241#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1242#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1243 __le16 num_entries;
1244 __le16 destination; /* VSI for add, rule id for delete */
1245 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1246 __le32 addr_low;
1247};
1248
1249I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1250
1251struct i40e_aqc_add_delete_mirror_rule_completion {
1252 u8 reserved[2];
1253 __le16 rule_id; /* only used on add */
1254 __le16 mirror_rules_used;
1255 __le16 mirror_rules_free;
1256 __le32 addr_high;
1257 __le32 addr_low;
1258};
1259
1260I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1261
1262/* Set Storm Control Configuration (direct 0x0280)
1263 * Get Storm Control Configuration (direct 0x0281)
1264 * the command and response use the same descriptor structure
1265 */
1266struct i40e_aqc_set_get_storm_control_config {
1267 __le32 broadcast_threshold;
1268 __le32 multicast_threshold;
1269 __le32 control_flags;
1270#define I40E_AQC_STORM_CONTROL_MDIPW 0x01
1271#define I40E_AQC_STORM_CONTROL_MDICW 0x02
1272#define I40E_AQC_STORM_CONTROL_BDIPW 0x04
1273#define I40E_AQC_STORM_CONTROL_BDICW 0x08
1274#define I40E_AQC_STORM_CONTROL_BIDU 0x10
1275#define I40E_AQC_STORM_CONTROL_INTERVAL_SHIFT 8
1276#define I40E_AQC_STORM_CONTROL_INTERVAL_MASK (0x3FF << \
1277 I40E_AQC_STORM_CONTROL_INTERVAL_SHIFT)
1278 u8 reserved[4];
1279};
1280
1281I40E_CHECK_CMD_LENGTH(i40e_aqc_set_get_storm_control_config);
1282
1283/* DCB 0x03xx*/
1284
1285/* PFC Ignore (direct 0x0301)
1286 * the command and response use the same descriptor structure
1287 */
1288struct i40e_aqc_pfc_ignore {
1289 u8 tc_bitmap;
1290 u8 command_flags; /* unused on response */
1291#define I40E_AQC_PFC_IGNORE_SET 0x80
1292#define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1293 u8 reserved[14];
1294};
1295
1296I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1297
1298/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1299 * with no parameters
1300 */
1301
1302/* TX scheduler 0x04xx */
1303
1304/* Almost all the indirect commands use
1305 * this generic struct to pass the SEID in param0
1306 */
1307struct i40e_aqc_tx_sched_ind {
1308 __le16 vsi_seid;
1309 u8 reserved[6];
1310 __le32 addr_high;
1311 __le32 addr_low;
1312};
1313
1314I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1315
1316/* Several commands respond with a set of queue set handles */
1317struct i40e_aqc_qs_handles_resp {
1318 __le16 qs_handles[8];
1319};
1320
1321/* Configure VSI BW limits (direct 0x0400) */
1322struct i40e_aqc_configure_vsi_bw_limit {
1323 __le16 vsi_seid;
1324 u8 reserved[2];
1325 __le16 credit;
1326 u8 reserved1[2];
1327 u8 max_credit; /* 0-3, limit = 2^max */
1328 u8 reserved2[7];
1329};
1330
1331I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1332
1333/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1334 * responds with i40e_aqc_qs_handles_resp
1335 */
1336struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1337 u8 tc_valid_bits;
1338 u8 reserved[15];
1339 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1340
1341 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1342 __le16 tc_bw_max[2];
1343 u8 reserved1[28];
1344};
1345
1346/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1347 * responds with i40e_aqc_qs_handles_resp
1348 */
1349struct i40e_aqc_configure_vsi_tc_bw_data {
1350 u8 tc_valid_bits;
1351 u8 reserved[3];
1352 u8 tc_bw_credits[8];
1353 u8 reserved1[4];
1354 __le16 qs_handles[8];
1355};
1356
1357/* Query vsi bw configuration (indirect 0x0408) */
1358struct i40e_aqc_query_vsi_bw_config_resp {
1359 u8 tc_valid_bits;
1360 u8 tc_suspended_bits;
1361 u8 reserved[14];
1362 __le16 qs_handles[8];
1363 u8 reserved1[4];
1364 __le16 port_bw_limit;
1365 u8 reserved2[2];
1366 u8 max_bw; /* 0-3, limit = 2^max */
1367 u8 reserved3[23];
1368};
1369
1370/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1371struct i40e_aqc_query_vsi_ets_sla_config_resp {
1372 u8 tc_valid_bits;
1373 u8 reserved[3];
1374 u8 share_credits[8];
1375 __le16 credits[8];
1376
1377 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1378 __le16 tc_bw_max[2];
1379};
1380
1381/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1382struct i40e_aqc_configure_switching_comp_bw_limit {
1383 __le16 seid;
1384 u8 reserved[2];
1385 __le16 credit;
1386 u8 reserved1[2];
1387 u8 max_bw; /* 0-3, limit = 2^max */
1388 u8 reserved2[7];
1389};
1390
1391I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1392
1393/* Enable Physical Port ETS (indirect 0x0413)
1394 * Modify Physical Port ETS (indirect 0x0414)
1395 * Disable Physical Port ETS (indirect 0x0415)
1396 */
1397struct i40e_aqc_configure_switching_comp_ets_data {
1398 u8 reserved[4];
1399 u8 tc_valid_bits;
1400 u8 reserved1;
1401 u8 tc_strict_priority_flags;
1402 u8 reserved2[17];
1403 u8 tc_bw_share_credits[8];
1404 u8 reserved3[96];
1405};
1406
1407/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1408struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1409 u8 tc_valid_bits;
1410 u8 reserved[15];
1411 __le16 tc_bw_credit[8];
1412
1413 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1414 __le16 tc_bw_max[2];
1415 u8 reserved1[28];
1416};
1417
1418/* Configure Switching Component Bandwidth Allocation per Tc
1419 * (indirect 0x0417)
1420 */
1421struct i40e_aqc_configure_switching_comp_bw_config_data {
1422 u8 tc_valid_bits;
1423 u8 reserved[2];
1424 u8 absolute_credits; /* bool */
1425 u8 tc_bw_share_credits[8];
1426 u8 reserved1[20];
1427};
1428
1429/* Query Switching Component Configuration (indirect 0x0418) */
1430struct i40e_aqc_query_switching_comp_ets_config_resp {
1431 u8 tc_valid_bits;
1432 u8 reserved[35];
1433 __le16 port_bw_limit;
1434 u8 reserved1[2];
1435 u8 tc_bw_max; /* 0-3, limit = 2^max */
1436 u8 reserved2[23];
1437};
1438
1439/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1440struct i40e_aqc_query_port_ets_config_resp {
1441 u8 reserved[4];
1442 u8 tc_valid_bits;
1443 u8 reserved1;
1444 u8 tc_strict_priority_bits;
1445 u8 reserved2;
1446 u8 tc_bw_share_credits[8];
1447 __le16 tc_bw_limits[8];
1448
1449 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1450 __le16 tc_bw_max[2];
1451 u8 reserved3[32];
1452};
1453
1454/* Query Switching Component Bandwidth Allocation per Traffic Type
1455 * (indirect 0x041A)
1456 */
1457struct i40e_aqc_query_switching_comp_bw_config_resp {
1458 u8 tc_valid_bits;
1459 u8 reserved[2];
1460 u8 absolute_credits_enable; /* bool */
1461 u8 tc_bw_share_credits[8];
1462 __le16 tc_bw_limits[8];
1463
1464 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1465 __le16 tc_bw_max[2];
1466};
1467
1468/* Suspend/resume port TX traffic
1469 * (direct 0x041B and 0x041C) uses the generic SEID struct
1470 */
1471
1472/* Get and set the active HMC resource profile and status.
1473 * (direct 0x0500) and (direct 0x0501)
1474 */
1475struct i40e_aq_get_set_hmc_resource_profile {
1476 u8 pm_profile;
1477 u8 pe_vf_enabled;
1478 u8 reserved[14];
1479};
1480
1481I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1482
1483enum i40e_aq_hmc_profile {
1484 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1485 I40E_HMC_PROFILE_DEFAULT = 1,
1486 I40E_HMC_PROFILE_FAVOR_VF = 2,
1487 I40E_HMC_PROFILE_EQUAL = 3,
1488};
1489
1490#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1491#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1492
1493/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1494
1495/* set in param0 for get phy abilities to report qualified modules */
1496#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1497#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1498
1499enum i40e_aq_phy_type {
1500 I40E_PHY_TYPE_SGMII = 0x0,
1501 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1502 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1503 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1504 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1505 I40E_PHY_TYPE_XAUI = 0x5,
1506 I40E_PHY_TYPE_XFI = 0x6,
1507 I40E_PHY_TYPE_SFI = 0x7,
1508 I40E_PHY_TYPE_XLAUI = 0x8,
1509 I40E_PHY_TYPE_XLPPI = 0x9,
1510 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1511 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1512 I40E_PHY_TYPE_100BASE_TX = 0x11,
1513 I40E_PHY_TYPE_1000BASE_T = 0x12,
1514 I40E_PHY_TYPE_10GBASE_T = 0x13,
1515 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1516 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1517 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1518 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1519 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1520 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1521 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1522 I40E_PHY_TYPE_20GBASE_KR2 = 0x1B,
1523 I40E_PHY_TYPE_MAX
1524};
1525
1526#define I40E_LINK_SPEED_100MB_SHIFT 0x1
1527#define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1528#define I40E_LINK_SPEED_10GB_SHIFT 0x3
1529#define I40E_LINK_SPEED_40GB_SHIFT 0x4
1530#define I40E_LINK_SPEED_20GB_SHIFT 0x5
1531
1532enum i40e_aq_link_speed {
1533 I40E_LINK_SPEED_UNKNOWN = 0,
1534 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1535 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1536 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1537 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1538 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1539};
1540
1541struct i40e_aqc_module_desc {
1542 u8 oui[3];
1543 u8 reserved1;
1544 u8 part_number[16];
1545 u8 revision[4];
1546 u8 reserved2[8];
1547};
1548
1549struct i40e_aq_get_phy_abilities_resp {
1550 __le32 phy_type; /* bitmap using the above enum for offsets */
1551 u8 link_speed; /* bitmap using the above enum */
1552 u8 abilities;
1553#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1554#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1555#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1556#define I40E_AQ_PHY_FLAG_AN_SHIFT 3
1557#define I40E_AQ_PHY_FLAG_AN_MASK (0x3 << I40E_AQ_PHY_FLAG_AN_SHIFT)
1558#define I40E_AQ_PHY_FLAG_AN_OFF 0x00 /* link forced on */
1559#define I40E_AQ_PHY_FLAG_AN_OFF_LINK_DOWN 0x01
1560#define I40E_AQ_PHY_FLAG_AN_ON 0x02
1561#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1562 __le16 eee_capability;
1563#define I40E_AQ_EEE_100BASE_TX 0x0002
1564#define I40E_AQ_EEE_1000BASE_T 0x0004
1565#define I40E_AQ_EEE_10GBASE_T 0x0008
1566#define I40E_AQ_EEE_1000BASE_KX 0x0010
1567#define I40E_AQ_EEE_10GBASE_KX4 0x0020
1568#define I40E_AQ_EEE_10GBASE_KR 0x0040
1569 __le32 eeer_val;
1570 u8 d3_lpan;
1571#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1572 u8 reserved[3];
1573 u8 phy_id[4];
1574 u8 module_type[3];
1575 u8 qualified_module_count;
1576#define I40E_AQ_PHY_MAX_QMS 16
1577 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1578};
1579
1580/* Set PHY Config (direct 0x0601) */
1581struct i40e_aq_set_phy_config { /* same bits as above in all */
1582 __le32 phy_type;
1583 u8 link_speed;
1584 u8 abilities;
1585 __le16 eee_capability;
1586 __le32 eeer;
1587 u8 low_power_ctrl;
1588 u8 reserved[3];
1589};
1590
1591I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1592
1593/* Set MAC Config command data structure (direct 0x0603) */
1594struct i40e_aq_set_mac_config {
1595 __le16 max_frame_size;
1596 u8 params;
1597#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1598#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1599#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1600#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1601#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1602#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1603#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1604#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1605#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1606#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1607#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1608#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1609#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1610#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1611 u8 tx_timer_priority; /* bitmap */
1612 __le16 tx_timer_value;
1613 __le16 fc_refresh_threshold;
1614 u8 reserved[8];
1615};
1616
1617I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1618
1619/* Restart Auto-Negotiation (direct 0x605) */
1620struct i40e_aqc_set_link_restart_an {
1621 u8 command;
1622#define I40E_AQ_PHY_RESTART_AN 0x02
1623#define I40E_AQ_PHY_LINK_ENABLE 0x04
1624 u8 reserved[15];
1625};
1626
1627I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1628
1629/* Get Link Status cmd & response data structure (direct 0x0607) */
1630struct i40e_aqc_get_link_status {
1631 __le16 command_flags; /* only field set on command */
1632#define I40E_AQ_LSE_MASK 0x3
1633#define I40E_AQ_LSE_NOP 0x0
1634#define I40E_AQ_LSE_DISABLE 0x2
1635#define I40E_AQ_LSE_ENABLE 0x3
1636/* only response uses this flag */
1637#define I40E_AQ_LSE_IS_ENABLED 0x1
1638 u8 phy_type; /* i40e_aq_phy_type */
1639 u8 link_speed; /* i40e_aq_link_speed */
1640 u8 link_info;
1641#define I40E_AQ_LINK_UP 0x01
1642#define I40E_AQ_LINK_FAULT 0x02
1643#define I40E_AQ_LINK_FAULT_TX 0x04
1644#define I40E_AQ_LINK_FAULT_RX 0x08
1645#define I40E_AQ_LINK_FAULT_REMOTE 0x10
1646#define I40E_AQ_MEDIA_AVAILABLE 0x40
1647#define I40E_AQ_SIGNAL_DETECT 0x80
1648 u8 an_info;
1649#define I40E_AQ_AN_COMPLETED 0x01
1650#define I40E_AQ_LP_AN_ABILITY 0x02
1651#define I40E_AQ_PD_FAULT 0x04
1652#define I40E_AQ_FEC_EN 0x08
1653#define I40E_AQ_PHY_LOW_POWER 0x10
1654#define I40E_AQ_LINK_PAUSE_TX 0x20
1655#define I40E_AQ_LINK_PAUSE_RX 0x40
1656#define I40E_AQ_QUALIFIED_MODULE 0x80
1657 u8 ext_info;
1658#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1659#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1660#define I40E_AQ_LINK_TX_SHIFT 0x02
1661#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1662#define I40E_AQ_LINK_TX_ACTIVE 0x00
1663#define I40E_AQ_LINK_TX_DRAINED 0x01
1664#define I40E_AQ_LINK_TX_FLUSHED 0x03
1665 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1666 __le16 max_frame_size;
1667 u8 config;
1668#define I40E_AQ_CONFIG_CRC_ENA 0x04
1669#define I40E_AQ_CONFIG_PACING_MASK 0x78
1670 u8 reserved[5];
1671};
1672
1673I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1674
1675/* Set event mask command (direct 0x613) */
1676struct i40e_aqc_set_phy_int_mask {
1677 u8 reserved[8];
1678 __le16 event_mask;
1679#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1680#define I40E_AQ_EVENT_MEDIA_NA 0x0004
1681#define I40E_AQ_EVENT_LINK_FAULT 0x0008
1682#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1683#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1684#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1685#define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1686#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1687#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1688 u8 reserved1[6];
1689};
1690
1691I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1692
1693/* Get Local AN advt register (direct 0x0614)
1694 * Set Local AN advt register (direct 0x0615)
1695 * Get Link Partner AN advt register (direct 0x0616)
1696 */
1697struct i40e_aqc_an_advt_reg {
1698 __le32 local_an_reg0;
1699 __le16 local_an_reg1;
1700 u8 reserved[10];
1701};
1702
1703I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1704
1705/* Set Loopback mode (0x0618) */
1706struct i40e_aqc_set_lb_mode {
1707 __le16 lb_mode;
1708#define I40E_AQ_LB_PHY_LOCAL 0x01
1709#define I40E_AQ_LB_PHY_REMOTE 0x02
1710#define I40E_AQ_LB_MAC_LOCAL 0x04
1711 u8 reserved[14];
1712};
1713
1714I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1715
1716/* Set PHY Reset command (0x0622) */
1717struct i40e_aqc_set_phy_reset {
1718 u8 reset_flags;
1719#define I40E_AQ_PHY_RESET_REQUEST 0x02
1720 u8 reserved[15];
1721};
1722
1723I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_reset);
1724
1725enum i40e_aq_phy_reg_type {
1726 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1727 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1728 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1729};
1730
1731/* NVM Read command (indirect 0x0701)
1732 * NVM Erase commands (direct 0x0702)
1733 * NVM Update commands (indirect 0x0703)
1734 */
1735struct i40e_aqc_nvm_update {
1736 u8 command_flags;
1737#define I40E_AQ_NVM_LAST_CMD 0x01
1738#define I40E_AQ_NVM_FLASH_ONLY 0x80
1739 u8 module_pointer;
1740 __le16 length;
1741 __le32 offset;
1742 __le32 addr_high;
1743 __le32 addr_low;
1744};
1745
1746I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1747
1748/* Send to PF command (indirect 0x0801) id is only used by PF
1749 * Send to VF command (indirect 0x0802) id is only used by PF
1750 * Send to Peer PF command (indirect 0x0803)
1751 */
1752struct i40e_aqc_pf_vf_message {
1753 __le32 id;
1754 u8 reserved[4];
1755 __le32 addr_high;
1756 __le32 addr_low;
1757};
1758
1759I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1760
1761/* Alternate structure */
1762
1763/* Direct write (direct 0x0900)
1764 * Direct read (direct 0x0902)
1765 */
1766struct i40e_aqc_alternate_write {
1767 __le32 address0;
1768 __le32 data0;
1769 __le32 address1;
1770 __le32 data1;
1771};
1772
1773I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
1774
1775/* Indirect write (indirect 0x0901)
1776 * Indirect read (indirect 0x0903)
1777 */
1778
1779struct i40e_aqc_alternate_ind_write {
1780 __le32 address;
1781 __le32 length;
1782 __le32 addr_high;
1783 __le32 addr_low;
1784};
1785
1786I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
1787
1788/* Done alternate write (direct 0x0904)
1789 * uses i40e_aq_desc
1790 */
1791struct i40e_aqc_alternate_write_done {
1792 __le16 cmd_flags;
1793#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
1794#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
1795#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
1796#define I40E_AQ_ALTERNATE_RESET_NEEDED 2
1797 u8 reserved[14];
1798};
1799
1800I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
1801
1802/* Set OEM mode (direct 0x0905) */
1803struct i40e_aqc_alternate_set_mode {
1804 __le32 mode;
1805#define I40E_AQ_ALTERNATE_MODE_NONE 0
1806#define I40E_AQ_ALTERNATE_MODE_OEM 1
1807 u8 reserved[12];
1808};
1809
1810I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
1811
1812/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
1813
1814/* async events 0x10xx */
1815
1816/* Lan Queue Overflow Event (direct, 0x1001) */
1817struct i40e_aqc_lan_overflow {
1818 __le32 prtdcb_rupto;
1819 __le32 otx_ctl;
1820 u8 reserved[8];
1821};
1822
1823I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
1824
1825/* Get LLDP MIB (indirect 0x0A00) */
1826struct i40e_aqc_lldp_get_mib {
1827 u8 type;
1828 u8 reserved1;
1829#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
1830#define I40E_AQ_LLDP_MIB_LOCAL 0x0
1831#define I40E_AQ_LLDP_MIB_REMOTE 0x1
1832#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
1833#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
1834#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
1835#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
1836#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
1837#define I40E_AQ_LLDP_TX_SHIFT 0x4
1838#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
1839/* TX pause flags use I40E_AQ_LINK_TX_* above */
1840 __le16 local_len;
1841 __le16 remote_len;
1842 u8 reserved2[2];
1843 __le32 addr_high;
1844 __le32 addr_low;
1845};
1846
1847I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
1848
1849/* Configure LLDP MIB Change Event (direct 0x0A01)
1850 * also used for the event (with type in the command field)
1851 */
1852struct i40e_aqc_lldp_update_mib {
1853 u8 command;
1854#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
1855#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
1856 u8 reserved[7];
1857 __le32 addr_high;
1858 __le32 addr_low;
1859};
1860
1861I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
1862
1863/* Add LLDP TLV (indirect 0x0A02)
1864 * Delete LLDP TLV (indirect 0x0A04)
1865 */
1866struct i40e_aqc_lldp_add_tlv {
1867 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1868 u8 reserved1[1];
1869 __le16 len;
1870 u8 reserved2[4];
1871 __le32 addr_high;
1872 __le32 addr_low;
1873};
1874
1875I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
1876
1877/* Update LLDP TLV (indirect 0x0A03) */
1878struct i40e_aqc_lldp_update_tlv {
1879 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
1880 u8 reserved;
1881 __le16 old_len;
1882 __le16 new_offset;
1883 __le16 new_len;
1884 __le32 addr_high;
1885 __le32 addr_low;
1886};
1887
1888I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
1889
1890/* Stop LLDP (direct 0x0A05) */
1891struct i40e_aqc_lldp_stop {
1892 u8 command;
1893#define I40E_AQ_LLDP_AGENT_STOP 0x0
1894#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
1895 u8 reserved[15];
1896};
1897
1898I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
1899
1900/* Start LLDP (direct 0x0A06) */
1901
1902struct i40e_aqc_lldp_start {
1903 u8 command;
1904#define I40E_AQ_LLDP_AGENT_START 0x1
1905 u8 reserved[15];
1906};
1907
1908I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
1909
1910/* Apply MIB changes (0x0A07)
1911 * uses the generic struc as it contains no data
1912 */
1913
1914/* Add Udp Tunnel command and completion (direct 0x0B00) */
1915struct i40e_aqc_add_udp_tunnel {
1916 __le16 udp_port;
1917 u8 header_len; /* in DWords, 1 to 15 */
1918 u8 protocol_index;
1919#define I40E_AQC_TUNNEL_TYPE_MAC 0x0
1920#define I40E_AQC_TUNNEL_TYPE_UDP 0x1
1921 u8 reserved[12];
1922};
1923
1924I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
1925
1926/* remove UDP Tunnel command (0x0B01) */
1927struct i40e_aqc_remove_udp_tunnel {
1928 u8 reserved[2];
1929 u8 index; /* 0 to 15 */
1930 u8 pf_filters;
1931 u8 total_filters;
1932 u8 reserved2[11];
1933};
1934
1935I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
1936
1937struct i40e_aqc_del_udp_tunnel_completion {
1938 __le16 udp_port;
1939 u8 index; /* 0 to 15 */
1940 u8 multiple_entries;
1941 u8 tunnels_used;
1942 u8 reserved;
1943 u8 tunnels_free;
1944 u8 reserved1[9];
1945};
1946
1947I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
1948
1949/* tunnel key structure 0x0B10 */
1950struct i40e_aqc_tunnel_key_structure {
1951 __le16 key1_off;
1952 __le16 key1_len;
1953 __le16 key2_off;
1954 __le16 key2_len;
1955 __le16 flags;
1956#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
1957/* response flags */
1958#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
1959#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
1960#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
1961 u8 resreved[6];
1962};
1963
1964I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
1965
1966/* OEM mode commands (direct 0xFE0x) */
1967struct i40e_aqc_oem_param_change {
1968 __le32 param_type;
1969#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
1970#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
1971#define I40E_AQ_OEM_PARAM_MAC 2
1972 __le32 param_value1;
1973 u8 param_value2[8];
1974};
1975
1976I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
1977
1978struct i40e_aqc_oem_state_change {
1979 __le32 state;
1980#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
1981#define I40E_AQ_OEM_STATE_LINK_UP 0x1
1982 u8 reserved[12];
1983};
1984
1985I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
1986
1987/* debug commands */
1988
1989/* get device id (0xFF00) uses the generic structure */
1990
1991/* set test more (0xFF01, internal) */
1992
1993struct i40e_acq_set_test_mode {
1994 u8 mode;
1995#define I40E_AQ_TEST_PARTIAL 0
1996#define I40E_AQ_TEST_FULL 1
1997#define I40E_AQ_TEST_NVM 2
1998 u8 reserved[3];
1999 u8 command;
2000#define I40E_AQ_TEST_OPEN 0
2001#define I40E_AQ_TEST_CLOSE 1
2002#define I40E_AQ_TEST_INC 2
2003 u8 reserved2[3];
2004 __le32 address_high;
2005 __le32 address_low;
2006};
2007
2008I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2009
2010/* Debug Read Register command (0xFF03)
2011 * Debug Write Register command (0xFF04)
2012 */
2013struct i40e_aqc_debug_reg_read_write {
2014 __le32 reserved;
2015 __le32 address;
2016 __le32 value_high;
2017 __le32 value_low;
2018};
2019
2020I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2021
2022/* Scatter/gather Reg Read (indirect 0xFF05)
2023 * Scatter/gather Reg Write (indirect 0xFF06)
2024 */
2025
2026/* i40e_aq_desc is used for the command */
2027struct i40e_aqc_debug_reg_sg_element_data {
2028 __le32 address;
2029 __le32 value;
2030};
2031
2032/* Debug Modify register (direct 0xFF07) */
2033struct i40e_aqc_debug_modify_reg {
2034 __le32 address;
2035 __le32 value;
2036 __le32 clear_mask;
2037 __le32 set_mask;
2038};
2039
2040I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2041
2042/* dump internal data (0xFF08, indirect) */
2043
2044#define I40E_AQ_CLUSTER_ID_AUX 0
2045#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2046#define I40E_AQ_CLUSTER_ID_TXSCHED 2
2047#define I40E_AQ_CLUSTER_ID_HMC 3
2048#define I40E_AQ_CLUSTER_ID_MAC0 4
2049#define I40E_AQ_CLUSTER_ID_MAC1 5
2050#define I40E_AQ_CLUSTER_ID_MAC2 6
2051#define I40E_AQ_CLUSTER_ID_MAC3 7
2052#define I40E_AQ_CLUSTER_ID_DCB 8
2053#define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2054#define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2055
2056struct i40e_aqc_debug_dump_internals {
2057 u8 cluster_id;
2058 u8 table_id;
2059 __le16 data_size;
2060 __le32 idx;
2061 __le32 address_high;
2062 __le32 address_low;
2063};
2064
2065I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2066
2067struct i40e_aqc_debug_modify_internals {
2068 u8 cluster_id;
2069 u8 cluster_specific_params[7];
2070 __le32 address_high;
2071 __le32 address_low;
2072};
2073
2074I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2075
2076#endif
diff --git a/drivers/net/ethernet/intel/i40e/i40e_alloc.h b/drivers/net/ethernet/intel/i40e/i40e_alloc.h
new file mode 100644
index 000000000000..3b1cc214f9dc
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_alloc.h
@@ -0,0 +1,59 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_ALLOC_H_
29#define _I40E_ALLOC_H_
30
31struct i40e_hw;
32
33/* Memory allocation types */
34enum i40e_memory_type {
35 i40e_mem_arq_buf = 0, /* ARQ indirect command buffer */
36 i40e_mem_asq_buf = 1,
37 i40e_mem_atq_buf = 2, /* ATQ indirect command buffer */
38 i40e_mem_arq_ring = 3, /* ARQ descriptor ring */
39 i40e_mem_atq_ring = 4, /* ATQ descriptor ring */
40 i40e_mem_pd = 5, /* Page Descriptor */
41 i40e_mem_bp = 6, /* Backing Page - 4KB */
42 i40e_mem_bp_jumbo = 7, /* Backing Page - > 4KB */
43 i40e_mem_reserved
44};
45
46/* prototype for functions used for dynamic memory allocation */
47i40e_status i40e_allocate_dma_mem(struct i40e_hw *hw,
48 struct i40e_dma_mem *mem,
49 enum i40e_memory_type type,
50 u64 size, u32 alignment);
51i40e_status i40e_free_dma_mem(struct i40e_hw *hw,
52 struct i40e_dma_mem *mem);
53i40e_status i40e_allocate_virt_mem(struct i40e_hw *hw,
54 struct i40e_virt_mem *mem,
55 u32 size);
56i40e_status i40e_free_virt_mem(struct i40e_hw *hw,
57 struct i40e_virt_mem *mem);
58
59#endif /* _I40E_ALLOC_H_ */
diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c
new file mode 100644
index 000000000000..c21df7bc3b1d
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c
@@ -0,0 +1,2041 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e_type.h"
29#include "i40e_adminq.h"
30#include "i40e_prototype.h"
31#include "i40e_virtchnl.h"
32
33/**
34 * i40e_set_mac_type - Sets MAC type
35 * @hw: pointer to the HW structure
36 *
37 * This function sets the mac type of the adapter based on the
38 * vendor ID and device ID stored in the hw structure.
39 **/
40static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
41{
42 i40e_status status = 0;
43
44 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
45 switch (hw->device_id) {
46 case I40E_SFP_XL710_DEVICE_ID:
47 case I40E_SFP_X710_DEVICE_ID:
48 case I40E_QEMU_DEVICE_ID:
49 case I40E_KX_A_DEVICE_ID:
50 case I40E_KX_B_DEVICE_ID:
51 case I40E_KX_C_DEVICE_ID:
52 case I40E_KX_D_DEVICE_ID:
53 case I40E_QSFP_A_DEVICE_ID:
54 case I40E_QSFP_B_DEVICE_ID:
55 case I40E_QSFP_C_DEVICE_ID:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_VF_DEVICE_ID:
59 case I40E_VF_HV_DEVICE_ID:
60 hw->mac.type = I40E_MAC_VF;
61 break;
62 default:
63 hw->mac.type = I40E_MAC_GENERIC;
64 break;
65 }
66 } else {
67 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
68 }
69
70 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
71 hw->mac.type, status);
72 return status;
73}
74
75/**
76 * i40e_debug_aq
77 * @hw: debug mask related to admin queue
78 * @cap: pointer to adminq command descriptor
79 * @buffer: pointer to command buffer
80 *
81 * Dumps debug log about adminq command with descriptor contents.
82 **/
83void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
84 void *buffer)
85{
86 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
87 u8 *aq_buffer = (u8 *)buffer;
88 u32 data[4];
89 u32 i = 0;
90
91 if ((!(mask & hw->debug_mask)) || (desc == NULL))
92 return;
93
94 i40e_debug(hw, mask,
95 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
96 aq_desc->opcode, aq_desc->flags, aq_desc->datalen,
97 aq_desc->retval);
98 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
99 aq_desc->cookie_high, aq_desc->cookie_low);
100 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
101 aq_desc->params.internal.param0,
102 aq_desc->params.internal.param1);
103 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
104 aq_desc->params.external.addr_high,
105 aq_desc->params.external.addr_low);
106
107 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
108 memset(data, 0, sizeof(data));
109 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
110 for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
111 data[((i % 16) / 4)] |=
112 ((u32)aq_buffer[i]) << (8 * (i % 4));
113 if ((i % 16) == 15) {
114 i40e_debug(hw, mask,
115 "\t0x%04X %08X %08X %08X %08X\n",
116 i - 15, data[0], data[1], data[2],
117 data[3]);
118 memset(data, 0, sizeof(data));
119 }
120 }
121 if ((i % 16) != 0)
122 i40e_debug(hw, mask, "\t0x%04X %08X %08X %08X %08X\n",
123 i - (i % 16), data[0], data[1], data[2],
124 data[3]);
125 }
126}
127
128/**
129 * i40e_init_shared_code - Initialize the shared code
130 * @hw: pointer to hardware structure
131 *
132 * This assigns the MAC type and PHY code and inits the NVM.
133 * Does not touch the hardware. This function must be called prior to any
134 * other function in the shared code. The i40e_hw structure should be
135 * memset to 0 prior to calling this function. The following fields in
136 * hw structure should be filled in prior to calling this function:
137 * hw_addr, back, device_id, vendor_id, subsystem_device_id,
138 * subsystem_vendor_id, and revision_id
139 **/
140i40e_status i40e_init_shared_code(struct i40e_hw *hw)
141{
142 i40e_status status = 0;
143 u32 reg;
144
145 hw->phy.get_link_info = true;
146
147 /* Determine port number */
148 reg = rd32(hw, I40E_PFGEN_PORTNUM);
149 reg = ((reg & I40E_PFGEN_PORTNUM_PORT_NUM_MASK) >>
150 I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT);
151 hw->port = (u8)reg;
152
153 i40e_set_mac_type(hw);
154
155 switch (hw->mac.type) {
156 case I40E_MAC_XL710:
157 break;
158 default:
159 return I40E_ERR_DEVICE_NOT_SUPPORTED;
160 break;
161 }
162
163 status = i40e_init_nvm(hw);
164 return status;
165}
166
167/**
168 * i40e_aq_mac_address_read - Retrieve the MAC addresses
169 * @hw: pointer to the hw struct
170 * @flags: a return indicator of what addresses were added to the addr store
171 * @addrs: the requestor's mac addr store
172 * @cmd_details: pointer to command details structure or NULL
173 **/
174static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
175 u16 *flags,
176 struct i40e_aqc_mac_address_read_data *addrs,
177 struct i40e_asq_cmd_details *cmd_details)
178{
179 struct i40e_aq_desc desc;
180 struct i40e_aqc_mac_address_read *cmd_data =
181 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
182 i40e_status status;
183
184 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
185 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
186
187 status = i40e_asq_send_command(hw, &desc, addrs,
188 sizeof(*addrs), cmd_details);
189 *flags = le16_to_cpu(cmd_data->command_flags);
190
191 return status;
192}
193
194/**
195 * i40e_aq_mac_address_write - Change the MAC addresses
196 * @hw: pointer to the hw struct
197 * @flags: indicates which MAC to be written
198 * @mac_addr: address to write
199 * @cmd_details: pointer to command details structure or NULL
200 **/
201i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
202 u16 flags, u8 *mac_addr,
203 struct i40e_asq_cmd_details *cmd_details)
204{
205 struct i40e_aq_desc desc;
206 struct i40e_aqc_mac_address_write *cmd_data =
207 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
208 i40e_status status;
209
210 i40e_fill_default_direct_cmd_desc(&desc,
211 i40e_aqc_opc_mac_address_write);
212 cmd_data->command_flags = cpu_to_le16(flags);
213 memcpy(&cmd_data->mac_sal, &mac_addr[0], 4);
214 memcpy(&cmd_data->mac_sah, &mac_addr[4], 2);
215
216 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
217
218 return status;
219}
220
221/**
222 * i40e_get_mac_addr - get MAC address
223 * @hw: pointer to the HW structure
224 * @mac_addr: pointer to MAC address
225 *
226 * Reads the adapter's MAC address from register
227 **/
228i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
229{
230 struct i40e_aqc_mac_address_read_data addrs;
231 i40e_status status;
232 u16 flags = 0;
233
234 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
235
236 if (flags & I40E_AQC_LAN_ADDR_VALID)
237 memcpy(mac_addr, &addrs.pf_lan_mac, sizeof(addrs.pf_lan_mac));
238
239 return status;
240}
241
242/**
243 * i40e_validate_mac_addr - Validate MAC address
244 * @mac_addr: pointer to MAC address
245 *
246 * Tests a MAC address to ensure it is a valid Individual Address
247 **/
248i40e_status i40e_validate_mac_addr(u8 *mac_addr)
249{
250 i40e_status status = 0;
251
252 /* Make sure it is not a multicast address */
253 if (I40E_IS_MULTICAST(mac_addr)) {
254 hw_dbg(hw, "MAC address is multicast\n");
255 status = I40E_ERR_INVALID_MAC_ADDR;
256 /* Not a broadcast address */
257 } else if (I40E_IS_BROADCAST(mac_addr)) {
258 hw_dbg(hw, "MAC address is broadcast\n");
259 status = I40E_ERR_INVALID_MAC_ADDR;
260 /* Reject the zero address */
261 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
262 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
263 hw_dbg(hw, "MAC address is all zeros\n");
264 status = I40E_ERR_INVALID_MAC_ADDR;
265 }
266 return status;
267}
268
269/**
270 * i40e_pf_reset - Reset the PF
271 * @hw: pointer to the hardware structure
272 *
273 * Assuming someone else has triggered a global reset,
274 * assure the global reset is complete and then reset the PF
275 **/
276i40e_status i40e_pf_reset(struct i40e_hw *hw)
277{
278 u32 wait_cnt = 0;
279 u32 reg = 0;
280 u32 grst_del;
281
282 /* Poll for Global Reset steady state in case of recent GRST.
283 * The grst delay value is in 100ms units, and we'll wait a
284 * couple counts longer to be sure we don't just miss the end.
285 */
286 grst_del = rd32(hw, I40E_GLGEN_RSTCTL) & I40E_GLGEN_RSTCTL_GRSTDEL_MASK
287 >> I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
288 for (wait_cnt = 0; wait_cnt < grst_del + 2; wait_cnt++) {
289 reg = rd32(hw, I40E_GLGEN_RSTAT);
290 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
291 break;
292 msleep(100);
293 }
294 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
295 hw_dbg(hw, "Global reset polling failed to complete.\n");
296 return I40E_ERR_RESET_FAILED;
297 }
298
299 /* Determine the PF number based on the PCI fn */
300 hw->pf_id = (u8)hw->bus.func;
301
302 /* If there was a Global Reset in progress when we got here,
303 * we don't need to do the PF Reset
304 */
305 if (!wait_cnt) {
306 reg = rd32(hw, I40E_PFGEN_CTRL);
307 wr32(hw, I40E_PFGEN_CTRL,
308 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
309 for (wait_cnt = 0; wait_cnt < 10; wait_cnt++) {
310 reg = rd32(hw, I40E_PFGEN_CTRL);
311 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
312 break;
313 usleep_range(1000, 2000);
314 }
315 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
316 hw_dbg(hw, "PF reset polling failed to complete.\n");
317 return I40E_ERR_RESET_FAILED;
318 }
319 }
320
321 i40e_clear_pxe_mode(hw);
322 return 0;
323}
324
325/**
326 * i40e_clear_pxe_mode - clear pxe operations mode
327 * @hw: pointer to the hw struct
328 *
329 * Make sure all PXE mode settings are cleared, including things
330 * like descriptor fetch/write-back mode.
331 **/
332void i40e_clear_pxe_mode(struct i40e_hw *hw)
333{
334 u32 reg;
335
336 /* Clear single descriptor fetch/write-back mode */
337 reg = rd32(hw, I40E_GLLAN_RCTL_0);
338 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
339}
340
341/**
342 * i40e_led_get - return current on/off mode
343 * @hw: pointer to the hw struct
344 *
345 * The value returned is the 'mode' field as defined in the
346 * GPIO register definitions: 0x0 = off, 0xf = on, and other
347 * values are variations of possible behaviors relating to
348 * blink, link, and wire.
349 **/
350u32 i40e_led_get(struct i40e_hw *hw)
351{
352 u32 gpio_val = 0;
353 u32 mode = 0;
354 u32 port;
355 int i;
356
357 for (i = 0; i < I40E_HW_CAP_MAX_GPIO; i++) {
358 if (!hw->func_caps.led[i])
359 continue;
360
361 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(i));
362 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK)
363 >> I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
364
365 if (port != hw->port)
366 continue;
367
368 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
369 >> I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT;
370 break;
371 }
372
373 return mode;
374}
375
376/**
377 * i40e_led_set - set new on/off mode
378 * @hw: pointer to the hw struct
379 * @mode: 0=off, else on (see EAS for mode details)
380 **/
381void i40e_led_set(struct i40e_hw *hw, u32 mode)
382{
383 u32 gpio_val = 0;
384 u32 led_mode = 0;
385 u32 port;
386 int i;
387
388 for (i = 0; i < I40E_HW_CAP_MAX_GPIO; i++) {
389 if (!hw->func_caps.led[i])
390 continue;
391
392 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(i));
393 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK)
394 >> I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
395
396 if (port != hw->port)
397 continue;
398
399 led_mode = (mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
400 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
401 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
402 gpio_val |= led_mode;
403 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
404 }
405}
406
407/* Admin command wrappers */
408/**
409 * i40e_aq_queue_shutdown
410 * @hw: pointer to the hw struct
411 * @unloading: is the driver unloading itself
412 *
413 * Tell the Firmware that we're shutting down the AdminQ and whether
414 * or not the driver is unloading as well.
415 **/
416i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
417 bool unloading)
418{
419 struct i40e_aq_desc desc;
420 struct i40e_aqc_queue_shutdown *cmd =
421 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
422 i40e_status status;
423
424 i40e_fill_default_direct_cmd_desc(&desc,
425 i40e_aqc_opc_queue_shutdown);
426
427 if (unloading)
428 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
429 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
430
431 return status;
432}
433
434/**
435 * i40e_aq_set_link_restart_an
436 * @hw: pointer to the hw struct
437 * @cmd_details: pointer to command details structure or NULL
438 *
439 * Sets up the link and restarts the Auto-Negotiation over the link.
440 **/
441i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
442 struct i40e_asq_cmd_details *cmd_details)
443{
444 struct i40e_aq_desc desc;
445 struct i40e_aqc_set_link_restart_an *cmd =
446 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
447 i40e_status status;
448
449 i40e_fill_default_direct_cmd_desc(&desc,
450 i40e_aqc_opc_set_link_restart_an);
451
452 cmd->command = I40E_AQ_PHY_RESTART_AN;
453
454 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
455
456 return status;
457}
458
459/**
460 * i40e_aq_get_link_info
461 * @hw: pointer to the hw struct
462 * @enable_lse: enable/disable LinkStatusEvent reporting
463 * @link: pointer to link status structure - optional
464 * @cmd_details: pointer to command details structure or NULL
465 *
466 * Returns the link status of the adapter.
467 **/
468i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
469 bool enable_lse, struct i40e_link_status *link,
470 struct i40e_asq_cmd_details *cmd_details)
471{
472 struct i40e_aq_desc desc;
473 struct i40e_aqc_get_link_status *resp =
474 (struct i40e_aqc_get_link_status *)&desc.params.raw;
475 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
476 i40e_status status;
477 u16 command_flags;
478
479 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
480
481 if (enable_lse)
482 command_flags = I40E_AQ_LSE_ENABLE;
483 else
484 command_flags = I40E_AQ_LSE_DISABLE;
485 resp->command_flags = cpu_to_le16(command_flags);
486
487 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
488
489 if (status)
490 goto aq_get_link_info_exit;
491
492 /* save off old link status information */
493 memcpy(&hw->phy.link_info_old, hw_link_info,
494 sizeof(struct i40e_link_status));
495
496 /* update link status */
497 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
498 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
499 hw_link_info->link_info = resp->link_info;
500 hw_link_info->an_info = resp->an_info;
501 hw_link_info->ext_info = resp->ext_info;
502
503 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
504 hw_link_info->lse_enable = true;
505 else
506 hw_link_info->lse_enable = false;
507
508 /* save link status information */
509 if (link)
510 memcpy(link, hw_link_info, sizeof(struct i40e_link_status));
511
512 /* flag cleared so helper functions don't call AQ again */
513 hw->phy.get_link_info = false;
514
515aq_get_link_info_exit:
516 return status;
517}
518
519/**
520 * i40e_aq_add_vsi
521 * @hw: pointer to the hw struct
522 * @vsi: pointer to a vsi context struct
523 * @cmd_details: pointer to command details structure or NULL
524 *
525 * Add a VSI context to the hardware.
526**/
527i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
528 struct i40e_vsi_context *vsi_ctx,
529 struct i40e_asq_cmd_details *cmd_details)
530{
531 struct i40e_aq_desc desc;
532 struct i40e_aqc_add_get_update_vsi *cmd =
533 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
534 struct i40e_aqc_add_get_update_vsi_completion *resp =
535 (struct i40e_aqc_add_get_update_vsi_completion *)
536 &desc.params.raw;
537 i40e_status status;
538
539 i40e_fill_default_direct_cmd_desc(&desc,
540 i40e_aqc_opc_add_vsi);
541
542 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
543 cmd->connection_type = vsi_ctx->connection_type;
544 cmd->vf_id = vsi_ctx->vf_num;
545 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
546
547 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
548 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
549 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
550
551 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
552 sizeof(vsi_ctx->info), cmd_details);
553
554 if (status)
555 goto aq_add_vsi_exit;
556
557 vsi_ctx->seid = le16_to_cpu(resp->seid);
558 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
559 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
560 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
561
562aq_add_vsi_exit:
563 return status;
564}
565
566/**
567 * i40e_aq_set_vsi_unicast_promiscuous
568 * @hw: pointer to the hw struct
569 * @seid: vsi number
570 * @set: set unicast promiscuous enable/disable
571 * @cmd_details: pointer to command details structure or NULL
572 **/
573i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
574 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
575{
576 struct i40e_aq_desc desc;
577 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
578 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
579 i40e_status status;
580 u16 flags = 0;
581
582 i40e_fill_default_direct_cmd_desc(&desc,
583 i40e_aqc_opc_set_vsi_promiscuous_modes);
584
585 if (set)
586 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
587
588 cmd->promiscuous_flags = cpu_to_le16(flags);
589
590 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
591
592 cmd->seid = cpu_to_le16(seid);
593 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
594
595 return status;
596}
597
598/**
599 * i40e_aq_set_vsi_multicast_promiscuous
600 * @hw: pointer to the hw struct
601 * @seid: vsi number
602 * @set: set multicast promiscuous enable/disable
603 * @cmd_details: pointer to command details structure or NULL
604 **/
605i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
606 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
607{
608 struct i40e_aq_desc desc;
609 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
610 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
611 i40e_status status;
612 u16 flags = 0;
613
614 i40e_fill_default_direct_cmd_desc(&desc,
615 i40e_aqc_opc_set_vsi_promiscuous_modes);
616
617 if (set)
618 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
619
620 cmd->promiscuous_flags = cpu_to_le16(flags);
621
622 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
623
624 cmd->seid = cpu_to_le16(seid);
625 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
626
627 return status;
628}
629
630/**
631 * i40e_aq_set_vsi_broadcast
632 * @hw: pointer to the hw struct
633 * @seid: vsi number
634 * @set_filter: true to set filter, false to clear filter
635 * @cmd_details: pointer to command details structure or NULL
636 *
637 * Set or clear the broadcast promiscuous flag (filter) for a given VSI.
638 **/
639i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
640 u16 seid, bool set_filter,
641 struct i40e_asq_cmd_details *cmd_details)
642{
643 struct i40e_aq_desc desc;
644 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
645 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
646 i40e_status status;
647
648 i40e_fill_default_direct_cmd_desc(&desc,
649 i40e_aqc_opc_set_vsi_promiscuous_modes);
650
651 if (set_filter)
652 cmd->promiscuous_flags
653 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
654 else
655 cmd->promiscuous_flags
656 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
657
658 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
659 cmd->seid = cpu_to_le16(seid);
660 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
661
662 return status;
663}
664
665/**
666 * i40e_get_vsi_params - get VSI configuration info
667 * @hw: pointer to the hw struct
668 * @vsi: pointer to a vsi context struct
669 * @cmd_details: pointer to command details structure or NULL
670 **/
671i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
672 struct i40e_vsi_context *vsi_ctx,
673 struct i40e_asq_cmd_details *cmd_details)
674{
675 struct i40e_aq_desc desc;
676 struct i40e_aqc_switch_seid *cmd =
677 (struct i40e_aqc_switch_seid *)&desc.params.raw;
678 struct i40e_aqc_add_get_update_vsi_completion *resp =
679 (struct i40e_aqc_add_get_update_vsi_completion *)
680 &desc.params.raw;
681 i40e_status status;
682
683 i40e_fill_default_direct_cmd_desc(&desc,
684 i40e_aqc_opc_get_vsi_parameters);
685
686 cmd->seid = cpu_to_le16(vsi_ctx->seid);
687
688 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
689 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
690 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
691
692 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
693 sizeof(vsi_ctx->info), NULL);
694
695 if (status)
696 goto aq_get_vsi_params_exit;
697
698 vsi_ctx->seid = le16_to_cpu(resp->seid);
699 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
700 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
701 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
702
703aq_get_vsi_params_exit:
704 return status;
705}
706
707/**
708 * i40e_aq_update_vsi_params
709 * @hw: pointer to the hw struct
710 * @vsi: pointer to a vsi context struct
711 * @cmd_details: pointer to command details structure or NULL
712 *
713 * Update a VSI context.
714 **/
715i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
716 struct i40e_vsi_context *vsi_ctx,
717 struct i40e_asq_cmd_details *cmd_details)
718{
719 struct i40e_aq_desc desc;
720 struct i40e_aqc_switch_seid *cmd =
721 (struct i40e_aqc_switch_seid *)&desc.params.raw;
722 i40e_status status;
723
724 i40e_fill_default_direct_cmd_desc(&desc,
725 i40e_aqc_opc_update_vsi_parameters);
726 cmd->seid = cpu_to_le16(vsi_ctx->seid);
727
728 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
729 if (sizeof(vsi_ctx->info) > I40E_AQ_LARGE_BUF)
730 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
731
732 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
733 sizeof(vsi_ctx->info), cmd_details);
734
735 return status;
736}
737
738/**
739 * i40e_aq_get_switch_config
740 * @hw: pointer to the hardware structure
741 * @buf: pointer to the result buffer
742 * @buf_size: length of input buffer
743 * @start_seid: seid to start for the report, 0 == beginning
744 * @cmd_details: pointer to command details structure or NULL
745 *
746 * Fill the buf with switch configuration returned from AdminQ command
747 **/
748i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
749 struct i40e_aqc_get_switch_config_resp *buf,
750 u16 buf_size, u16 *start_seid,
751 struct i40e_asq_cmd_details *cmd_details)
752{
753 struct i40e_aq_desc desc;
754 struct i40e_aqc_switch_seid *scfg =
755 (struct i40e_aqc_switch_seid *)&desc.params.raw;
756 i40e_status status;
757
758 i40e_fill_default_direct_cmd_desc(&desc,
759 i40e_aqc_opc_get_switch_config);
760 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
761 if (buf_size > I40E_AQ_LARGE_BUF)
762 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
763 scfg->seid = cpu_to_le16(*start_seid);
764
765 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
766 *start_seid = le16_to_cpu(scfg->seid);
767
768 return status;
769}
770
771/**
772 * i40e_aq_get_firmware_version
773 * @hw: pointer to the hw struct
774 * @fw_major_version: firmware major version
775 * @fw_minor_version: firmware minor version
776 * @api_major_version: major queue version
777 * @api_minor_version: minor queue version
778 * @cmd_details: pointer to command details structure or NULL
779 *
780 * Get the firmware version from the admin queue commands
781 **/
782i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
783 u16 *fw_major_version, u16 *fw_minor_version,
784 u16 *api_major_version, u16 *api_minor_version,
785 struct i40e_asq_cmd_details *cmd_details)
786{
787 struct i40e_aq_desc desc;
788 struct i40e_aqc_get_version *resp =
789 (struct i40e_aqc_get_version *)&desc.params.raw;
790 i40e_status status;
791
792 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
793
794 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
795
796 if (!status) {
797 if (fw_major_version != NULL)
798 *fw_major_version = le16_to_cpu(resp->fw_major);
799 if (fw_minor_version != NULL)
800 *fw_minor_version = le16_to_cpu(resp->fw_minor);
801 if (api_major_version != NULL)
802 *api_major_version = le16_to_cpu(resp->api_major);
803 if (api_minor_version != NULL)
804 *api_minor_version = le16_to_cpu(resp->api_minor);
805 }
806
807 return status;
808}
809
810/**
811 * i40e_aq_send_driver_version
812 * @hw: pointer to the hw struct
813 * @event: driver event: driver ok, start or stop
814 * @dv: driver's major, minor version
815 * @cmd_details: pointer to command details structure or NULL
816 *
817 * Send the driver version to the firmware
818 **/
819i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
820 struct i40e_driver_version *dv,
821 struct i40e_asq_cmd_details *cmd_details)
822{
823 struct i40e_aq_desc desc;
824 struct i40e_aqc_driver_version *cmd =
825 (struct i40e_aqc_driver_version *)&desc.params.raw;
826 i40e_status status;
827
828 if (dv == NULL)
829 return I40E_ERR_PARAM;
830
831 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
832
833 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_SI);
834 cmd->driver_major_ver = dv->major_version;
835 cmd->driver_minor_ver = dv->minor_version;
836 cmd->driver_build_ver = dv->build_version;
837 cmd->driver_subbuild_ver = dv->subbuild_version;
838 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
839
840 return status;
841}
842
843/**
844 * i40e_get_link_status - get status of the HW network link
845 * @hw: pointer to the hw struct
846 *
847 * Returns true if link is up, false if link is down.
848 *
849 * Side effect: LinkStatusEvent reporting becomes enabled
850 **/
851bool i40e_get_link_status(struct i40e_hw *hw)
852{
853 i40e_status status = 0;
854 bool link_status = false;
855
856 if (hw->phy.get_link_info) {
857 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
858
859 if (status)
860 goto i40e_get_link_status_exit;
861 }
862
863 link_status = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
864
865i40e_get_link_status_exit:
866 return link_status;
867}
868
869/**
870 * i40e_aq_add_veb - Insert a VEB between the VSI and the MAC
871 * @hw: pointer to the hw struct
872 * @uplink_seid: the MAC or other gizmo SEID
873 * @downlink_seid: the VSI SEID
874 * @enabled_tc: bitmap of TCs to be enabled
875 * @default_port: true for default port VSI, false for control port
876 * @veb_seid: pointer to where to put the resulting VEB SEID
877 * @cmd_details: pointer to command details structure or NULL
878 *
879 * This asks the FW to add a VEB between the uplink and downlink
880 * elements. If the uplink SEID is 0, this will be a floating VEB.
881 **/
882i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
883 u16 downlink_seid, u8 enabled_tc,
884 bool default_port, u16 *veb_seid,
885 struct i40e_asq_cmd_details *cmd_details)
886{
887 struct i40e_aq_desc desc;
888 struct i40e_aqc_add_veb *cmd =
889 (struct i40e_aqc_add_veb *)&desc.params.raw;
890 struct i40e_aqc_add_veb_completion *resp =
891 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
892 i40e_status status;
893 u16 veb_flags = 0;
894
895 /* SEIDs need to either both be set or both be 0 for floating VEB */
896 if (!!uplink_seid != !!downlink_seid)
897 return I40E_ERR_PARAM;
898
899 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
900
901 cmd->uplink_seid = cpu_to_le16(uplink_seid);
902 cmd->downlink_seid = cpu_to_le16(downlink_seid);
903 cmd->enable_tcs = enabled_tc;
904 if (!uplink_seid)
905 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
906 if (default_port)
907 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
908 else
909 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
910 cmd->veb_flags = cpu_to_le16(veb_flags);
911
912 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
913
914 if (!status && veb_seid)
915 *veb_seid = le16_to_cpu(resp->veb_seid);
916
917 return status;
918}
919
920/**
921 * i40e_aq_get_veb_parameters - Retrieve VEB parameters
922 * @hw: pointer to the hw struct
923 * @veb_seid: the SEID of the VEB to query
924 * @switch_id: the uplink switch id
925 * @floating_veb: set to true if the VEB is floating
926 * @statistic_index: index of the stats counter block for this VEB
927 * @vebs_used: number of VEB's used by function
928 * @vebs_unallocated: total VEB's not reserved by any function
929 * @cmd_details: pointer to command details structure or NULL
930 *
931 * This retrieves the parameters for a particular VEB, specified by
932 * uplink_seid, and returns them to the caller.
933 **/
934i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
935 u16 veb_seid, u16 *switch_id,
936 bool *floating, u16 *statistic_index,
937 u16 *vebs_used, u16 *vebs_free,
938 struct i40e_asq_cmd_details *cmd_details)
939{
940 struct i40e_aq_desc desc;
941 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
942 (struct i40e_aqc_get_veb_parameters_completion *)
943 &desc.params.raw;
944 i40e_status status;
945
946 if (veb_seid == 0)
947 return I40E_ERR_PARAM;
948
949 i40e_fill_default_direct_cmd_desc(&desc,
950 i40e_aqc_opc_get_veb_parameters);
951 cmd_resp->seid = cpu_to_le16(veb_seid);
952
953 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
954 if (status)
955 goto get_veb_exit;
956
957 if (switch_id)
958 *switch_id = le16_to_cpu(cmd_resp->switch_id);
959 if (statistic_index)
960 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
961 if (vebs_used)
962 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
963 if (vebs_free)
964 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
965 if (floating) {
966 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
967 if (flags & I40E_AQC_ADD_VEB_FLOATING)
968 *floating = true;
969 else
970 *floating = false;
971 }
972
973get_veb_exit:
974 return status;
975}
976
977/**
978 * i40e_aq_add_macvlan
979 * @hw: pointer to the hw struct
980 * @seid: VSI for the mac address
981 * @mv_list: list of macvlans to be added
982 * @count: length of the list
983 * @cmd_details: pointer to command details structure or NULL
984 *
985 * Add MAC/VLAN addresses to the HW filtering
986 **/
987i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
988 struct i40e_aqc_add_macvlan_element_data *mv_list,
989 u16 count, struct i40e_asq_cmd_details *cmd_details)
990{
991 struct i40e_aq_desc desc;
992 struct i40e_aqc_macvlan *cmd =
993 (struct i40e_aqc_macvlan *)&desc.params.raw;
994 i40e_status status;
995 u16 buf_size;
996
997 if (count == 0 || !mv_list || !hw)
998 return I40E_ERR_PARAM;
999
1000 buf_size = count * sizeof(struct i40e_aqc_add_macvlan_element_data);
1001
1002 /* prep the rest of the request */
1003 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
1004 cmd->num_addresses = cpu_to_le16(count);
1005 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1006 cmd->seid[1] = 0;
1007 cmd->seid[2] = 0;
1008
1009 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1010 if (buf_size > I40E_AQ_LARGE_BUF)
1011 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1012
1013 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1014 cmd_details);
1015
1016 return status;
1017}
1018
1019/**
1020 * i40e_aq_remove_macvlan
1021 * @hw: pointer to the hw struct
1022 * @seid: VSI for the mac address
1023 * @mv_list: list of macvlans to be removed
1024 * @count: length of the list
1025 * @cmd_details: pointer to command details structure or NULL
1026 *
1027 * Remove MAC/VLAN addresses from the HW filtering
1028 **/
1029i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
1030 struct i40e_aqc_remove_macvlan_element_data *mv_list,
1031 u16 count, struct i40e_asq_cmd_details *cmd_details)
1032{
1033 struct i40e_aq_desc desc;
1034 struct i40e_aqc_macvlan *cmd =
1035 (struct i40e_aqc_macvlan *)&desc.params.raw;
1036 i40e_status status;
1037 u16 buf_size;
1038
1039 if (count == 0 || !mv_list || !hw)
1040 return I40E_ERR_PARAM;
1041
1042 buf_size = count * sizeof(struct i40e_aqc_remove_macvlan_element_data);
1043
1044 /* prep the rest of the request */
1045 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
1046 cmd->num_addresses = cpu_to_le16(count);
1047 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
1048 cmd->seid[1] = 0;
1049 cmd->seid[2] = 0;
1050
1051 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1052 if (buf_size > I40E_AQ_LARGE_BUF)
1053 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1054
1055 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
1056 cmd_details);
1057
1058 return status;
1059}
1060
1061/**
1062 * i40e_aq_add_vlan - Add VLAN ids to the HW filtering
1063 * @hw: pointer to the hw struct
1064 * @seid: VSI for the vlan filters
1065 * @v_list: list of vlan filters to be added
1066 * @count: length of the list
1067 * @cmd_details: pointer to command details structure or NULL
1068 **/
1069i40e_status i40e_aq_add_vlan(struct i40e_hw *hw, u16 seid,
1070 struct i40e_aqc_add_remove_vlan_element_data *v_list,
1071 u8 count, struct i40e_asq_cmd_details *cmd_details)
1072{
1073 struct i40e_aq_desc desc;
1074 struct i40e_aqc_macvlan *cmd =
1075 (struct i40e_aqc_macvlan *)&desc.params.raw;
1076 i40e_status status;
1077 u16 buf_size;
1078
1079 if (count == 0 || !v_list || !hw)
1080 return I40E_ERR_PARAM;
1081
1082 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
1083
1084 /* prep the rest of the request */
1085 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_vlan);
1086 cmd->num_addresses = cpu_to_le16(count);
1087 cmd->seid[0] = cpu_to_le16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
1088 cmd->seid[1] = 0;
1089 cmd->seid[2] = 0;
1090
1091 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1092 if (buf_size > I40E_AQ_LARGE_BUF)
1093 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1094
1095 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
1096 cmd_details);
1097
1098 return status;
1099}
1100
1101/**
1102 * i40e_aq_remove_vlan - Remove VLANs from the HW filtering
1103 * @hw: pointer to the hw struct
1104 * @seid: VSI for the vlan filters
1105 * @v_list: list of macvlans to be removed
1106 * @count: length of the list
1107 * @cmd_details: pointer to command details structure or NULL
1108 **/
1109i40e_status i40e_aq_remove_vlan(struct i40e_hw *hw, u16 seid,
1110 struct i40e_aqc_add_remove_vlan_element_data *v_list,
1111 u8 count, struct i40e_asq_cmd_details *cmd_details)
1112{
1113 struct i40e_aq_desc desc;
1114 struct i40e_aqc_macvlan *cmd =
1115 (struct i40e_aqc_macvlan *)&desc.params.raw;
1116 i40e_status status;
1117 u16 buf_size;
1118
1119 if (count == 0 || !v_list || !hw)
1120 return I40E_ERR_PARAM;
1121
1122 buf_size = count * sizeof(struct i40e_aqc_add_remove_vlan_element_data);
1123
1124 /* prep the rest of the request */
1125 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_vlan);
1126 cmd->num_addresses = cpu_to_le16(count);
1127 cmd->seid[0] = cpu_to_le16(seid | I40E_AQC_MACVLAN_CMD_SEID_VALID);
1128 cmd->seid[1] = 0;
1129 cmd->seid[2] = 0;
1130
1131 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1132 if (buf_size > I40E_AQ_LARGE_BUF)
1133 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1134
1135 status = i40e_asq_send_command(hw, &desc, v_list, buf_size,
1136 cmd_details);
1137
1138 return status;
1139}
1140
1141/**
1142 * i40e_aq_send_msg_to_vf
1143 * @hw: pointer to the hardware structure
1144 * @vfid: vf id to send msg
1145 * @msg: pointer to the msg buffer
1146 * @msglen: msg length
1147 * @cmd_details: pointer to command details
1148 *
1149 * send msg to vf
1150 **/
1151i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
1152 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
1153 struct i40e_asq_cmd_details *cmd_details)
1154{
1155 struct i40e_aq_desc desc;
1156 struct i40e_aqc_pf_vf_message *cmd =
1157 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
1158 i40e_status status;
1159
1160 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
1161 cmd->id = cpu_to_le32(vfid);
1162 desc.cookie_high = cpu_to_le32(v_opcode);
1163 desc.cookie_low = cpu_to_le32(v_retval);
1164 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
1165 if (msglen) {
1166 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
1167 I40E_AQ_FLAG_RD));
1168 if (msglen > I40E_AQ_LARGE_BUF)
1169 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1170 desc.datalen = cpu_to_le16(msglen);
1171 }
1172 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
1173
1174 return status;
1175}
1176
1177/**
1178 * i40e_aq_set_hmc_resource_profile
1179 * @hw: pointer to the hw struct
1180 * @profile: type of profile the HMC is to be set as
1181 * @pe_vf_enabled_count: the number of PE enabled VFs the system has
1182 * @cmd_details: pointer to command details structure or NULL
1183 *
1184 * set the HMC profile of the device.
1185 **/
1186i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
1187 enum i40e_aq_hmc_profile profile,
1188 u8 pe_vf_enabled_count,
1189 struct i40e_asq_cmd_details *cmd_details)
1190{
1191 struct i40e_aq_desc desc;
1192 struct i40e_aq_get_set_hmc_resource_profile *cmd =
1193 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
1194 i40e_status status;
1195
1196 i40e_fill_default_direct_cmd_desc(&desc,
1197 i40e_aqc_opc_set_hmc_resource_profile);
1198
1199 cmd->pm_profile = (u8)profile;
1200 cmd->pe_vf_enabled = pe_vf_enabled_count;
1201
1202 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1203
1204 return status;
1205}
1206
1207/**
1208 * i40e_aq_request_resource
1209 * @hw: pointer to the hw struct
1210 * @resource: resource id
1211 * @access: access type
1212 * @sdp_number: resource number
1213 * @timeout: the maximum time in ms that the driver may hold the resource
1214 * @cmd_details: pointer to command details structure or NULL
1215 *
1216 * requests common resource using the admin queue commands
1217 **/
1218i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
1219 enum i40e_aq_resources_ids resource,
1220 enum i40e_aq_resource_access_type access,
1221 u8 sdp_number, u64 *timeout,
1222 struct i40e_asq_cmd_details *cmd_details)
1223{
1224 struct i40e_aq_desc desc;
1225 struct i40e_aqc_request_resource *cmd_resp =
1226 (struct i40e_aqc_request_resource *)&desc.params.raw;
1227 i40e_status status;
1228
1229 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
1230
1231 cmd_resp->resource_id = cpu_to_le16(resource);
1232 cmd_resp->access_type = cpu_to_le16(access);
1233 cmd_resp->resource_number = cpu_to_le32(sdp_number);
1234
1235 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1236 /* The completion specifies the maximum time in ms that the driver
1237 * may hold the resource in the Timeout field.
1238 * If the resource is held by someone else, the command completes with
1239 * busy return value and the timeout field indicates the maximum time
1240 * the current owner of the resource has to free it.
1241 */
1242 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
1243 *timeout = le32_to_cpu(cmd_resp->timeout);
1244
1245 return status;
1246}
1247
1248/**
1249 * i40e_aq_release_resource
1250 * @hw: pointer to the hw struct
1251 * @resource: resource id
1252 * @sdp_number: resource number
1253 * @cmd_details: pointer to command details structure or NULL
1254 *
1255 * release common resource using the admin queue commands
1256 **/
1257i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
1258 enum i40e_aq_resources_ids resource,
1259 u8 sdp_number,
1260 struct i40e_asq_cmd_details *cmd_details)
1261{
1262 struct i40e_aq_desc desc;
1263 struct i40e_aqc_request_resource *cmd =
1264 (struct i40e_aqc_request_resource *)&desc.params.raw;
1265 i40e_status status;
1266
1267 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
1268
1269 cmd->resource_id = cpu_to_le16(resource);
1270 cmd->resource_number = cpu_to_le32(sdp_number);
1271
1272 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1273
1274 return status;
1275}
1276
1277/**
1278 * i40e_aq_read_nvm
1279 * @hw: pointer to the hw struct
1280 * @module_pointer: module pointer location in words from the NVM beginning
1281 * @offset: byte offset from the module beginning
1282 * @length: length of the section to be read (in bytes from the offset)
1283 * @data: command buffer (size [bytes] = length)
1284 * @last_command: tells if this is the last command in a series
1285 * @cmd_details: pointer to command details structure or NULL
1286 *
1287 * Read the NVM using the admin queue commands
1288 **/
1289i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
1290 u32 offset, u16 length, void *data,
1291 bool last_command,
1292 struct i40e_asq_cmd_details *cmd_details)
1293{
1294 struct i40e_aq_desc desc;
1295 struct i40e_aqc_nvm_update *cmd =
1296 (struct i40e_aqc_nvm_update *)&desc.params.raw;
1297 i40e_status status;
1298
1299 /* In offset the highest byte must be zeroed. */
1300 if (offset & 0xFF000000) {
1301 status = I40E_ERR_PARAM;
1302 goto i40e_aq_read_nvm_exit;
1303 }
1304
1305 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
1306
1307 /* If this is the last command in a series, set the proper flag. */
1308 if (last_command)
1309 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
1310 cmd->module_pointer = module_pointer;
1311 cmd->offset = cpu_to_le32(offset);
1312 cmd->length = cpu_to_le16(length);
1313
1314 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1315 if (length > I40E_AQ_LARGE_BUF)
1316 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1317
1318 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
1319
1320i40e_aq_read_nvm_exit:
1321 return status;
1322}
1323
1324#define I40E_DEV_FUNC_CAP_SWITCH_MODE 0x01
1325#define I40E_DEV_FUNC_CAP_MGMT_MODE 0x02
1326#define I40E_DEV_FUNC_CAP_NPAR 0x03
1327#define I40E_DEV_FUNC_CAP_OS2BMC 0x04
1328#define I40E_DEV_FUNC_CAP_VALID_FUNC 0x05
1329#define I40E_DEV_FUNC_CAP_SRIOV_1_1 0x12
1330#define I40E_DEV_FUNC_CAP_VF 0x13
1331#define I40E_DEV_FUNC_CAP_VMDQ 0x14
1332#define I40E_DEV_FUNC_CAP_802_1_QBG 0x15
1333#define I40E_DEV_FUNC_CAP_802_1_QBH 0x16
1334#define I40E_DEV_FUNC_CAP_VSI 0x17
1335#define I40E_DEV_FUNC_CAP_DCB 0x18
1336#define I40E_DEV_FUNC_CAP_FCOE 0x21
1337#define I40E_DEV_FUNC_CAP_RSS 0x40
1338#define I40E_DEV_FUNC_CAP_RX_QUEUES 0x41
1339#define I40E_DEV_FUNC_CAP_TX_QUEUES 0x42
1340#define I40E_DEV_FUNC_CAP_MSIX 0x43
1341#define I40E_DEV_FUNC_CAP_MSIX_VF 0x44
1342#define I40E_DEV_FUNC_CAP_FLOW_DIRECTOR 0x45
1343#define I40E_DEV_FUNC_CAP_IEEE_1588 0x46
1344#define I40E_DEV_FUNC_CAP_MFP_MODE_1 0xF1
1345#define I40E_DEV_FUNC_CAP_CEM 0xF2
1346#define I40E_DEV_FUNC_CAP_IWARP 0x51
1347#define I40E_DEV_FUNC_CAP_LED 0x61
1348#define I40E_DEV_FUNC_CAP_SDP 0x62
1349#define I40E_DEV_FUNC_CAP_MDIO 0x63
1350
1351/**
1352 * i40e_parse_discover_capabilities
1353 * @hw: pointer to the hw struct
1354 * @buff: pointer to a buffer containing device/function capability records
1355 * @cap_count: number of capability records in the list
1356 * @list_type_opc: type of capabilities list to parse
1357 *
1358 * Parse the device/function capabilities list.
1359 **/
1360static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
1361 u32 cap_count,
1362 enum i40e_admin_queue_opc list_type_opc)
1363{
1364 struct i40e_aqc_list_capabilities_element_resp *cap;
1365 u32 number, logical_id, phys_id;
1366 struct i40e_hw_capabilities *p;
1367 u32 reg_val;
1368 u32 i = 0;
1369 u16 id;
1370
1371 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
1372
1373 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
1374 p = (struct i40e_hw_capabilities *)&hw->dev_caps;
1375 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
1376 p = (struct i40e_hw_capabilities *)&hw->func_caps;
1377 else
1378 return;
1379
1380 for (i = 0; i < cap_count; i++, cap++) {
1381 id = le16_to_cpu(cap->id);
1382 number = le32_to_cpu(cap->number);
1383 logical_id = le32_to_cpu(cap->logical_id);
1384 phys_id = le32_to_cpu(cap->phys_id);
1385
1386 switch (id) {
1387 case I40E_DEV_FUNC_CAP_SWITCH_MODE:
1388 p->switch_mode = number;
1389 break;
1390 case I40E_DEV_FUNC_CAP_MGMT_MODE:
1391 p->management_mode = number;
1392 break;
1393 case I40E_DEV_FUNC_CAP_NPAR:
1394 p->npar_enable = number;
1395 break;
1396 case I40E_DEV_FUNC_CAP_OS2BMC:
1397 p->os2bmc = number;
1398 break;
1399 case I40E_DEV_FUNC_CAP_VALID_FUNC:
1400 p->valid_functions = number;
1401 break;
1402 case I40E_DEV_FUNC_CAP_SRIOV_1_1:
1403 if (number == 1)
1404 p->sr_iov_1_1 = true;
1405 break;
1406 case I40E_DEV_FUNC_CAP_VF:
1407 p->num_vfs = number;
1408 p->vf_base_id = logical_id;
1409 break;
1410 case I40E_DEV_FUNC_CAP_VMDQ:
1411 if (number == 1)
1412 p->vmdq = true;
1413 break;
1414 case I40E_DEV_FUNC_CAP_802_1_QBG:
1415 if (number == 1)
1416 p->evb_802_1_qbg = true;
1417 break;
1418 case I40E_DEV_FUNC_CAP_802_1_QBH:
1419 if (number == 1)
1420 p->evb_802_1_qbh = true;
1421 break;
1422 case I40E_DEV_FUNC_CAP_VSI:
1423 p->num_vsis = number;
1424 break;
1425 case I40E_DEV_FUNC_CAP_DCB:
1426 if (number == 1) {
1427 p->dcb = true;
1428 p->enabled_tcmap = logical_id;
1429 p->maxtc = phys_id;
1430 }
1431 break;
1432 case I40E_DEV_FUNC_CAP_FCOE:
1433 if (number == 1)
1434 p->fcoe = true;
1435 break;
1436 case I40E_DEV_FUNC_CAP_RSS:
1437 p->rss = true;
1438 reg_val = rd32(hw, I40E_PFQF_CTL_0);
1439 if (reg_val & I40E_PFQF_CTL_0_HASHLUTSIZE_MASK)
1440 p->rss_table_size = number;
1441 else
1442 p->rss_table_size = 128;
1443 p->rss_table_entry_width = logical_id;
1444 break;
1445 case I40E_DEV_FUNC_CAP_RX_QUEUES:
1446 p->num_rx_qp = number;
1447 p->base_queue = phys_id;
1448 break;
1449 case I40E_DEV_FUNC_CAP_TX_QUEUES:
1450 p->num_tx_qp = number;
1451 p->base_queue = phys_id;
1452 break;
1453 case I40E_DEV_FUNC_CAP_MSIX:
1454 p->num_msix_vectors = number;
1455 break;
1456 case I40E_DEV_FUNC_CAP_MSIX_VF:
1457 p->num_msix_vectors_vf = number;
1458 break;
1459 case I40E_DEV_FUNC_CAP_MFP_MODE_1:
1460 if (number == 1)
1461 p->mfp_mode_1 = true;
1462 break;
1463 case I40E_DEV_FUNC_CAP_CEM:
1464 if (number == 1)
1465 p->mgmt_cem = true;
1466 break;
1467 case I40E_DEV_FUNC_CAP_IWARP:
1468 if (number == 1)
1469 p->iwarp = true;
1470 break;
1471 case I40E_DEV_FUNC_CAP_LED:
1472 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1473 p->led[phys_id] = true;
1474 break;
1475 case I40E_DEV_FUNC_CAP_SDP:
1476 if (phys_id < I40E_HW_CAP_MAX_GPIO)
1477 p->sdp[phys_id] = true;
1478 break;
1479 case I40E_DEV_FUNC_CAP_MDIO:
1480 if (number == 1) {
1481 p->mdio_port_num = phys_id;
1482 p->mdio_port_mode = logical_id;
1483 }
1484 break;
1485 case I40E_DEV_FUNC_CAP_IEEE_1588:
1486 if (number == 1)
1487 p->ieee_1588 = true;
1488 break;
1489 case I40E_DEV_FUNC_CAP_FLOW_DIRECTOR:
1490 p->fd = true;
1491 p->fd_filters_guaranteed = number;
1492 p->fd_filters_best_effort = logical_id;
1493 break;
1494 default:
1495 break;
1496 }
1497 }
1498
1499 /* additional HW specific goodies that might
1500 * someday be HW version specific
1501 */
1502 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
1503}
1504
1505/**
1506 * i40e_aq_discover_capabilities
1507 * @hw: pointer to the hw struct
1508 * @buff: a virtual buffer to hold the capabilities
1509 * @buff_size: Size of the virtual buffer
1510 * @data_size: Size of the returned data, or buff size needed if AQ err==ENOMEM
1511 * @list_type_opc: capabilities type to discover - pass in the command opcode
1512 * @cmd_details: pointer to command details structure or NULL
1513 *
1514 * Get the device capabilities descriptions from the firmware
1515 **/
1516i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
1517 void *buff, u16 buff_size, u16 *data_size,
1518 enum i40e_admin_queue_opc list_type_opc,
1519 struct i40e_asq_cmd_details *cmd_details)
1520{
1521 struct i40e_aqc_list_capabilites *cmd;
1522 i40e_status status = 0;
1523 struct i40e_aq_desc desc;
1524
1525 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
1526
1527 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
1528 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
1529 status = I40E_ERR_PARAM;
1530 goto exit;
1531 }
1532
1533 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
1534
1535 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1536 if (buff_size > I40E_AQ_LARGE_BUF)
1537 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1538
1539 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1540 *data_size = le16_to_cpu(desc.datalen);
1541
1542 if (status)
1543 goto exit;
1544
1545 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
1546 list_type_opc);
1547
1548exit:
1549 return status;
1550}
1551
1552/**
1553 * i40e_aq_get_lldp_mib
1554 * @hw: pointer to the hw struct
1555 * @bridge_type: type of bridge requested
1556 * @mib_type: Local, Remote or both Local and Remote MIBs
1557 * @buff: pointer to a user supplied buffer to store the MIB block
1558 * @buff_size: size of the buffer (in bytes)
1559 * @local_len : length of the returned Local LLDP MIB
1560 * @remote_len: length of the returned Remote LLDP MIB
1561 * @cmd_details: pointer to command details structure or NULL
1562 *
1563 * Requests the complete LLDP MIB (entire packet).
1564 **/
1565i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
1566 u8 mib_type, void *buff, u16 buff_size,
1567 u16 *local_len, u16 *remote_len,
1568 struct i40e_asq_cmd_details *cmd_details)
1569{
1570 struct i40e_aq_desc desc;
1571 struct i40e_aqc_lldp_get_mib *cmd =
1572 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1573 struct i40e_aqc_lldp_get_mib *resp =
1574 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
1575 i40e_status status;
1576
1577 if (buff_size == 0 || !buff)
1578 return I40E_ERR_PARAM;
1579
1580 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
1581 /* Indirect Command */
1582 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1583
1584 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
1585 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
1586 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
1587
1588 desc.datalen = cpu_to_le16(buff_size);
1589
1590 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1591 if (buff_size > I40E_AQ_LARGE_BUF)
1592 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1593
1594 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1595 if (!status) {
1596 if (local_len != NULL)
1597 *local_len = le16_to_cpu(resp->local_len);
1598 if (remote_len != NULL)
1599 *remote_len = le16_to_cpu(resp->remote_len);
1600 }
1601
1602 return status;
1603}
1604
1605/**
1606 * i40e_aq_cfg_lldp_mib_change_event
1607 * @hw: pointer to the hw struct
1608 * @enable_update: Enable or Disable event posting
1609 * @cmd_details: pointer to command details structure or NULL
1610 *
1611 * Enable or Disable posting of an event on ARQ when LLDP MIB
1612 * associated with the interface changes
1613 **/
1614i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
1615 bool enable_update,
1616 struct i40e_asq_cmd_details *cmd_details)
1617{
1618 struct i40e_aq_desc desc;
1619 struct i40e_aqc_lldp_update_mib *cmd =
1620 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
1621 i40e_status status;
1622
1623 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
1624
1625 if (!enable_update)
1626 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
1627
1628 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1629
1630 return status;
1631}
1632
1633/**
1634 * i40e_aq_stop_lldp
1635 * @hw: pointer to the hw struct
1636 * @shutdown_agent: True if LLDP Agent needs to be Shutdown
1637 * @cmd_details: pointer to command details structure or NULL
1638 *
1639 * Stop or Shutdown the embedded LLDP Agent
1640 **/
1641i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
1642 struct i40e_asq_cmd_details *cmd_details)
1643{
1644 struct i40e_aq_desc desc;
1645 struct i40e_aqc_lldp_stop *cmd =
1646 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
1647 i40e_status status;
1648
1649 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
1650
1651 if (shutdown_agent)
1652 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
1653
1654 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1655
1656 return status;
1657}
1658
1659/**
1660 * i40e_aq_start_lldp
1661 * @hw: pointer to the hw struct
1662 * @cmd_details: pointer to command details structure or NULL
1663 *
1664 * Start the embedded LLDP Agent on all ports.
1665 **/
1666i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
1667 struct i40e_asq_cmd_details *cmd_details)
1668{
1669 struct i40e_aq_desc desc;
1670 struct i40e_aqc_lldp_start *cmd =
1671 (struct i40e_aqc_lldp_start *)&desc.params.raw;
1672 i40e_status status;
1673
1674 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
1675
1676 cmd->command = I40E_AQ_LLDP_AGENT_START;
1677
1678 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1679
1680 return status;
1681}
1682
1683/**
1684 * i40e_aq_delete_element - Delete switch element
1685 * @hw: pointer to the hw struct
1686 * @seid: the SEID to delete from the switch
1687 * @cmd_details: pointer to command details structure or NULL
1688 *
1689 * This deletes a switch element from the switch.
1690 **/
1691i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
1692 struct i40e_asq_cmd_details *cmd_details)
1693{
1694 struct i40e_aq_desc desc;
1695 struct i40e_aqc_switch_seid *cmd =
1696 (struct i40e_aqc_switch_seid *)&desc.params.raw;
1697 i40e_status status;
1698
1699 if (seid == 0)
1700 return I40E_ERR_PARAM;
1701
1702 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
1703
1704 cmd->seid = cpu_to_le16(seid);
1705
1706 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1707
1708 return status;
1709}
1710
1711/**
1712 * i40e_aq_tx_sched_cmd - generic Tx scheduler AQ command handler
1713 * @hw: pointer to the hw struct
1714 * @seid: seid for the physical port/switching component/vsi
1715 * @buff: Indirect buffer to hold data parameters and response
1716 * @buff_size: Indirect buffer size
1717 * @opcode: Tx scheduler AQ command opcode
1718 * @cmd_details: pointer to command details structure or NULL
1719 *
1720 * Generic command handler for Tx scheduler AQ commands
1721 **/
1722static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
1723 void *buff, u16 buff_size,
1724 enum i40e_admin_queue_opc opcode,
1725 struct i40e_asq_cmd_details *cmd_details)
1726{
1727 struct i40e_aq_desc desc;
1728 struct i40e_aqc_tx_sched_ind *cmd =
1729 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
1730 i40e_status status;
1731 bool cmd_param_flag = false;
1732
1733 switch (opcode) {
1734 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
1735 case i40e_aqc_opc_configure_vsi_tc_bw:
1736 case i40e_aqc_opc_enable_switching_comp_ets:
1737 case i40e_aqc_opc_modify_switching_comp_ets:
1738 case i40e_aqc_opc_disable_switching_comp_ets:
1739 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
1740 case i40e_aqc_opc_configure_switching_comp_bw_config:
1741 cmd_param_flag = true;
1742 break;
1743 case i40e_aqc_opc_query_vsi_bw_config:
1744 case i40e_aqc_opc_query_vsi_ets_sla_config:
1745 case i40e_aqc_opc_query_switching_comp_ets_config:
1746 case i40e_aqc_opc_query_port_ets_config:
1747 case i40e_aqc_opc_query_switching_comp_bw_config:
1748 cmd_param_flag = false;
1749 break;
1750 default:
1751 return I40E_ERR_PARAM;
1752 }
1753
1754 i40e_fill_default_direct_cmd_desc(&desc, opcode);
1755
1756 /* Indirect command */
1757 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1758 if (cmd_param_flag)
1759 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
1760 if (buff_size > I40E_AQ_LARGE_BUF)
1761 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1762
1763 desc.datalen = cpu_to_le16(buff_size);
1764
1765 cmd->vsi_seid = cpu_to_le16(seid);
1766
1767 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
1768
1769 return status;
1770}
1771
1772/**
1773 * i40e_aq_config_vsi_tc_bw - Config VSI BW Allocation per TC
1774 * @hw: pointer to the hw struct
1775 * @seid: VSI seid
1776 * @bw_data: Buffer holding enabled TCs, relative TC BW limit/credits
1777 * @cmd_details: pointer to command details structure or NULL
1778 **/
1779i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
1780 u16 seid,
1781 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
1782 struct i40e_asq_cmd_details *cmd_details)
1783{
1784 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1785 i40e_aqc_opc_configure_vsi_tc_bw,
1786 cmd_details);
1787}
1788
1789/**
1790 * i40e_aq_query_vsi_bw_config - Query VSI BW configuration
1791 * @hw: pointer to the hw struct
1792 * @seid: seid of the VSI
1793 * @bw_data: Buffer to hold VSI BW configuration
1794 * @cmd_details: pointer to command details structure or NULL
1795 **/
1796i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
1797 u16 seid,
1798 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
1799 struct i40e_asq_cmd_details *cmd_details)
1800{
1801 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1802 i40e_aqc_opc_query_vsi_bw_config,
1803 cmd_details);
1804}
1805
1806/**
1807 * i40e_aq_query_vsi_ets_sla_config - Query VSI BW configuration per TC
1808 * @hw: pointer to the hw struct
1809 * @seid: seid of the VSI
1810 * @bw_data: Buffer to hold VSI BW configuration per TC
1811 * @cmd_details: pointer to command details structure or NULL
1812 **/
1813i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
1814 u16 seid,
1815 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
1816 struct i40e_asq_cmd_details *cmd_details)
1817{
1818 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1819 i40e_aqc_opc_query_vsi_ets_sla_config,
1820 cmd_details);
1821}
1822
1823/**
1824 * i40e_aq_query_switch_comp_ets_config - Query Switch comp BW config per TC
1825 * @hw: pointer to the hw struct
1826 * @seid: seid of the switching component
1827 * @bw_data: Buffer to hold switching component's per TC BW config
1828 * @cmd_details: pointer to command details structure or NULL
1829 **/
1830i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
1831 u16 seid,
1832 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
1833 struct i40e_asq_cmd_details *cmd_details)
1834{
1835 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1836 i40e_aqc_opc_query_switching_comp_ets_config,
1837 cmd_details);
1838}
1839
1840/**
1841 * i40e_aq_query_port_ets_config - Query Physical Port ETS configuration
1842 * @hw: pointer to the hw struct
1843 * @seid: seid of the VSI or switching component connected to Physical Port
1844 * @bw_data: Buffer to hold current ETS configuration for the Physical Port
1845 * @cmd_details: pointer to command details structure or NULL
1846 **/
1847i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
1848 u16 seid,
1849 struct i40e_aqc_query_port_ets_config_resp *bw_data,
1850 struct i40e_asq_cmd_details *cmd_details)
1851{
1852 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1853 i40e_aqc_opc_query_port_ets_config,
1854 cmd_details);
1855}
1856
1857/**
1858 * i40e_aq_query_switch_comp_bw_config - Query Switch comp BW configuration
1859 * @hw: pointer to the hw struct
1860 * @seid: seid of the switching component
1861 * @bw_data: Buffer to hold switching component's BW configuration
1862 * @cmd_details: pointer to command details structure or NULL
1863 **/
1864i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
1865 u16 seid,
1866 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
1867 struct i40e_asq_cmd_details *cmd_details)
1868{
1869 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
1870 i40e_aqc_opc_query_switching_comp_bw_config,
1871 cmd_details);
1872}
1873
1874/**
1875 * i40e_validate_filter_settings
1876 * @hw: pointer to the hardware structure
1877 * @settings: Filter control settings
1878 *
1879 * Check and validate the filter control settings passed.
1880 * The function checks for the valid filter/context sizes being
1881 * passed for FCoE and PE.
1882 *
1883 * Returns 0 if the values passed are valid and within
1884 * range else returns an error.
1885 **/
1886static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
1887 struct i40e_filter_control_settings *settings)
1888{
1889 u32 fcoe_cntx_size, fcoe_filt_size;
1890 u32 pe_cntx_size, pe_filt_size;
1891 u32 fcoe_fmax, pe_fmax;
1892 u32 val;
1893
1894 /* Validate FCoE settings passed */
1895 switch (settings->fcoe_filt_num) {
1896 case I40E_HASH_FILTER_SIZE_1K:
1897 case I40E_HASH_FILTER_SIZE_2K:
1898 case I40E_HASH_FILTER_SIZE_4K:
1899 case I40E_HASH_FILTER_SIZE_8K:
1900 case I40E_HASH_FILTER_SIZE_16K:
1901 case I40E_HASH_FILTER_SIZE_32K:
1902 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
1903 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
1904 break;
1905 default:
1906 return I40E_ERR_PARAM;
1907 }
1908
1909 switch (settings->fcoe_cntx_num) {
1910 case I40E_DMA_CNTX_SIZE_512:
1911 case I40E_DMA_CNTX_SIZE_1K:
1912 case I40E_DMA_CNTX_SIZE_2K:
1913 case I40E_DMA_CNTX_SIZE_4K:
1914 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
1915 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
1916 break;
1917 default:
1918 return I40E_ERR_PARAM;
1919 }
1920
1921 /* Validate PE settings passed */
1922 switch (settings->pe_filt_num) {
1923 case I40E_HASH_FILTER_SIZE_1K:
1924 case I40E_HASH_FILTER_SIZE_2K:
1925 case I40E_HASH_FILTER_SIZE_4K:
1926 case I40E_HASH_FILTER_SIZE_8K:
1927 case I40E_HASH_FILTER_SIZE_16K:
1928 case I40E_HASH_FILTER_SIZE_32K:
1929 case I40E_HASH_FILTER_SIZE_64K:
1930 case I40E_HASH_FILTER_SIZE_128K:
1931 case I40E_HASH_FILTER_SIZE_256K:
1932 case I40E_HASH_FILTER_SIZE_512K:
1933 case I40E_HASH_FILTER_SIZE_1M:
1934 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
1935 pe_filt_size <<= (u32)settings->pe_filt_num;
1936 break;
1937 default:
1938 return I40E_ERR_PARAM;
1939 }
1940
1941 switch (settings->pe_cntx_num) {
1942 case I40E_DMA_CNTX_SIZE_512:
1943 case I40E_DMA_CNTX_SIZE_1K:
1944 case I40E_DMA_CNTX_SIZE_2K:
1945 case I40E_DMA_CNTX_SIZE_4K:
1946 case I40E_DMA_CNTX_SIZE_8K:
1947 case I40E_DMA_CNTX_SIZE_16K:
1948 case I40E_DMA_CNTX_SIZE_32K:
1949 case I40E_DMA_CNTX_SIZE_64K:
1950 case I40E_DMA_CNTX_SIZE_128K:
1951 case I40E_DMA_CNTX_SIZE_256K:
1952 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
1953 pe_cntx_size <<= (u32)settings->pe_cntx_num;
1954 break;
1955 default:
1956 return I40E_ERR_PARAM;
1957 }
1958
1959 /* FCHSIZE + FCDSIZE should not be greater than PMFCOEFMAX */
1960 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
1961 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
1962 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
1963 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
1964 return I40E_ERR_INVALID_SIZE;
1965
1966 /* PEHSIZE + PEDSIZE should not be greater than PMPEXFMAX */
1967 val = rd32(hw, I40E_GLHMC_PEXFMAX);
1968 pe_fmax = (val & I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK)
1969 >> I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT;
1970 if (pe_filt_size + pe_cntx_size > pe_fmax)
1971 return I40E_ERR_INVALID_SIZE;
1972
1973 return 0;
1974}
1975
1976/**
1977 * i40e_set_filter_control
1978 * @hw: pointer to the hardware structure
1979 * @settings: Filter control settings
1980 *
1981 * Set the Queue Filters for PE/FCoE and enable filters required
1982 * for a single PF. It is expected that these settings are programmed
1983 * at the driver initialization time.
1984 **/
1985i40e_status i40e_set_filter_control(struct i40e_hw *hw,
1986 struct i40e_filter_control_settings *settings)
1987{
1988 i40e_status ret = 0;
1989 u32 hash_lut_size = 0;
1990 u32 val;
1991
1992 if (!settings)
1993 return I40E_ERR_PARAM;
1994
1995 /* Validate the input settings */
1996 ret = i40e_validate_filter_settings(hw, settings);
1997 if (ret)
1998 return ret;
1999
2000 /* Read the PF Queue Filter control register */
2001 val = rd32(hw, I40E_PFQF_CTL_0);
2002
2003 /* Program required PE hash buckets for the PF */
2004 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
2005 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
2006 I40E_PFQF_CTL_0_PEHSIZE_MASK;
2007 /* Program required PE contexts for the PF */
2008 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
2009 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
2010 I40E_PFQF_CTL_0_PEDSIZE_MASK;
2011
2012 /* Program required FCoE hash buckets for the PF */
2013 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2014 val |= ((u32)settings->fcoe_filt_num <<
2015 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
2016 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
2017 /* Program required FCoE DDP contexts for the PF */
2018 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2019 val |= ((u32)settings->fcoe_cntx_num <<
2020 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
2021 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
2022
2023 /* Program Hash LUT size for the PF */
2024 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2025 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
2026 hash_lut_size = 1;
2027 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
2028 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
2029
2030 /* Enable FDIR, Ethertype and MACVLAN filters for PF and VFs */
2031 if (settings->enable_fdir)
2032 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
2033 if (settings->enable_ethtype)
2034 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
2035 if (settings->enable_macvlan)
2036 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
2037
2038 wr32(hw, I40E_PFQF_CTL_0, val);
2039
2040 return 0;
2041}
diff --git a/drivers/net/ethernet/intel/i40e/i40e_diag.c b/drivers/net/ethernet/intel/i40e/i40e_diag.c
new file mode 100644
index 000000000000..de255143bde6
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_diag.c
@@ -0,0 +1,131 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e_diag.h"
29#include "i40e_prototype.h"
30
31/**
32 * i40e_diag_reg_pattern_test
33 * @hw: pointer to the hw struct
34 * @reg: reg to be tested
35 * @mask: bits to be touched
36 **/
37static i40e_status i40e_diag_reg_pattern_test(struct i40e_hw *hw,
38 u32 reg, u32 mask)
39{
40 const u32 patterns[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
41 u32 pat, val, orig_val;
42 int i;
43
44 orig_val = rd32(hw, reg);
45 for (i = 0; i < ARRAY_SIZE(patterns); i++) {
46 pat = patterns[i];
47 wr32(hw, reg, (pat & mask));
48 val = rd32(hw, reg);
49 if ((val & mask) != (pat & mask)) {
50 i40e_debug(hw, I40E_DEBUG_DIAG,
51 "%s: reg pattern test failed - reg 0x%08x pat 0x%08x val 0x%08x\n",
52 __func__, reg, pat, val);
53 return I40E_ERR_DIAG_TEST_FAILED;
54 }
55 }
56
57 wr32(hw, reg, orig_val);
58 val = rd32(hw, reg);
59 if (val != orig_val) {
60 i40e_debug(hw, I40E_DEBUG_DIAG,
61 "%s: reg restore test failed - reg 0x%08x orig_val 0x%08x val 0x%08x\n",
62 __func__, reg, orig_val, val);
63 return I40E_ERR_DIAG_TEST_FAILED;
64 }
65
66 return 0;
67}
68
69struct i40e_diag_reg_test_info i40e_reg_list[] = {
70 /* offset mask elements stride */
71 {I40E_QTX_CTL(0), 0x0000FFBF, 64, I40E_QTX_CTL(1) - I40E_QTX_CTL(0)},
72 {I40E_PFINT_ITR0(0), 0x00000FFF, 3, I40E_PFINT_ITR0(1) - I40E_PFINT_ITR0(0)},
73 {I40E_PFINT_ITRN(0, 0), 0x00000FFF, 64, I40E_PFINT_ITRN(0, 1) - I40E_PFINT_ITRN(0, 0)},
74 {I40E_PFINT_ITRN(1, 0), 0x00000FFF, 64, I40E_PFINT_ITRN(1, 1) - I40E_PFINT_ITRN(1, 0)},
75 {I40E_PFINT_ITRN(2, 0), 0x00000FFF, 64, I40E_PFINT_ITRN(2, 1) - I40E_PFINT_ITRN(2, 0)},
76 {I40E_PFINT_STAT_CTL0, 0x0000000C, 1, 0},
77 {I40E_PFINT_LNKLST0, 0x00001FFF, 1, 0},
78 {I40E_PFINT_LNKLSTN(0), 0x000007FF, 511, I40E_PFINT_LNKLSTN(1) - I40E_PFINT_LNKLSTN(0)},
79 {I40E_QINT_TQCTL(0), 0x000000FF, I40E_QINT_TQCTL_MAX_INDEX + 1, I40E_QINT_TQCTL(1) - I40E_QINT_TQCTL(0)},
80 {I40E_QINT_RQCTL(0), 0x000000FF, I40E_QINT_RQCTL_MAX_INDEX + 1, I40E_QINT_RQCTL(1) - I40E_QINT_RQCTL(0)},
81 {I40E_PFINT_ICR0_ENA, 0xF7F20000, 1, 0},
82 { 0 }
83};
84
85/**
86 * i40e_diag_reg_test
87 * @hw: pointer to the hw struct
88 *
89 * Perform registers diagnostic test
90 **/
91i40e_status i40e_diag_reg_test(struct i40e_hw *hw)
92{
93 i40e_status ret_code = 0;
94 u32 reg, mask;
95 u32 i, j;
96
97 for (i = 0; (i40e_reg_list[i].offset != 0) && !ret_code; i++) {
98 mask = i40e_reg_list[i].mask;
99 for (j = 0; (j < i40e_reg_list[i].elements) && !ret_code; j++) {
100 reg = i40e_reg_list[i].offset +
101 (j * i40e_reg_list[i].stride);
102 ret_code = i40e_diag_reg_pattern_test(hw, reg, mask);
103 }
104 }
105
106 return ret_code;
107}
108
109/**
110 * i40e_diag_eeprom_test
111 * @hw: pointer to the hw struct
112 *
113 * Perform EEPROM diagnostic test
114 **/
115i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw)
116{
117 i40e_status ret_code;
118 u16 reg_val;
119
120 /* read NVM control word and if NVM valid, validate EEPROM checksum*/
121 ret_code = i40e_read_nvm_word(hw, I40E_SR_NVM_CONTROL_WORD, &reg_val);
122 if ((!ret_code) &&
123 ((reg_val & I40E_SR_CONTROL_WORD_1_MASK) ==
124 (0x01 << I40E_SR_CONTROL_WORD_1_SHIFT))) {
125 ret_code = i40e_validate_nvm_checksum(hw, NULL);
126 } else {
127 ret_code = I40E_ERR_DIAG_TEST_FAILED;
128 }
129
130 return ret_code;
131}
diff --git a/drivers/net/ethernet/intel/i40e/i40e_diag.h b/drivers/net/ethernet/intel/i40e/i40e_diag.h
new file mode 100644
index 000000000000..3d98277f4526
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_diag.h
@@ -0,0 +1,52 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_DIAG_H_
29#define _I40E_DIAG_H_
30
31#include "i40e_type.h"
32
33enum i40e_lb_mode {
34 I40E_LB_MODE_NONE = 0,
35 I40E_LB_MODE_PHY_LOCAL,
36 I40E_LB_MODE_PHY_REMOTE,
37 I40E_LB_MODE_MAC_LOCAL,
38};
39
40struct i40e_diag_reg_test_info {
41 u32 offset; /* the base register */
42 u32 mask; /* bits that can be tested */
43 u32 elements; /* number of elements if array */
44 u32 stride; /* bytes between each element */
45};
46
47extern struct i40e_diag_reg_test_info i40e_reg_list[];
48
49i40e_status i40e_diag_reg_test(struct i40e_hw *hw);
50i40e_status i40e_diag_eeprom_test(struct i40e_hw *hw);
51
52#endif /* _I40E_DIAG_H_ */
diff --git a/drivers/net/ethernet/intel/i40e/i40e_hmc.c b/drivers/net/ethernet/intel/i40e/i40e_hmc.c
new file mode 100644
index 000000000000..901804af8b0e
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_hmc.c
@@ -0,0 +1,366 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e_osdep.h"
29#include "i40e_register.h"
30#include "i40e_status.h"
31#include "i40e_alloc.h"
32#include "i40e_hmc.h"
33#include "i40e_type.h"
34
35/**
36 * i40e_add_sd_table_entry - Adds a segment descriptor to the table
37 * @hw: pointer to our hw struct
38 * @hmc_info: pointer to the HMC configuration information struct
39 * @sd_index: segment descriptor index to manipulate
40 * @type: what type of segment descriptor we're manipulating
41 * @direct_mode_sz: size to alloc in direct mode
42 **/
43i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw,
44 struct i40e_hmc_info *hmc_info,
45 u32 sd_index,
46 enum i40e_sd_entry_type type,
47 u64 direct_mode_sz)
48{
49 enum i40e_memory_type mem_type __attribute__((unused));
50 i40e_status ret_code = 0;
51 struct i40e_hmc_sd_entry *sd_entry;
52 bool dma_mem_alloc_done = false;
53 struct i40e_dma_mem mem;
54 u64 alloc_len;
55
56 if (NULL == hmc_info->sd_table.sd_entry) {
57 ret_code = I40E_ERR_BAD_PTR;
58 hw_dbg(hw, "i40e_add_sd_table_entry: bad sd_entry\n");
59 goto exit;
60 }
61
62 if (sd_index >= hmc_info->sd_table.sd_cnt) {
63 ret_code = I40E_ERR_INVALID_SD_INDEX;
64 hw_dbg(hw, "i40e_add_sd_table_entry: bad sd_index\n");
65 goto exit;
66 }
67
68 sd_entry = &hmc_info->sd_table.sd_entry[sd_index];
69 if (!sd_entry->valid) {
70 if (I40E_SD_TYPE_PAGED == type) {
71 mem_type = i40e_mem_pd;
72 alloc_len = I40E_HMC_PAGED_BP_SIZE;
73 } else {
74 mem_type = i40e_mem_bp_jumbo;
75 alloc_len = direct_mode_sz;
76 }
77
78 /* allocate a 4K pd page or 2M backing page */
79 ret_code = i40e_allocate_dma_mem(hw, &mem, mem_type, alloc_len,
80 I40E_HMC_PD_BP_BUF_ALIGNMENT);
81 if (ret_code)
82 goto exit;
83 dma_mem_alloc_done = true;
84 if (I40E_SD_TYPE_PAGED == type) {
85 ret_code = i40e_allocate_virt_mem(hw,
86 &sd_entry->u.pd_table.pd_entry_virt_mem,
87 sizeof(struct i40e_hmc_pd_entry) * 512);
88 if (ret_code)
89 goto exit;
90 sd_entry->u.pd_table.pd_entry =
91 (struct i40e_hmc_pd_entry *)
92 sd_entry->u.pd_table.pd_entry_virt_mem.va;
93 memcpy(&sd_entry->u.pd_table.pd_page_addr, &mem,
94 sizeof(struct i40e_dma_mem));
95 } else {
96 memcpy(&sd_entry->u.bp.addr, &mem,
97 sizeof(struct i40e_dma_mem));
98 sd_entry->u.bp.sd_pd_index = sd_index;
99 }
100 /* initialize the sd entry */
101 hmc_info->sd_table.sd_entry[sd_index].entry_type = type;
102
103 /* increment the ref count */
104 I40E_INC_SD_REFCNT(&hmc_info->sd_table);
105 }
106 /* Increment backing page reference count */
107 if (I40E_SD_TYPE_DIRECT == sd_entry->entry_type)
108 I40E_INC_BP_REFCNT(&sd_entry->u.bp);
109exit:
110 if (ret_code)
111 if (dma_mem_alloc_done)
112 i40e_free_dma_mem(hw, &mem);
113
114 return ret_code;
115}
116
117/**
118 * i40e_add_pd_table_entry - Adds page descriptor to the specified table
119 * @hw: pointer to our HW structure
120 * @hmc_info: pointer to the HMC configuration information structure
121 * @pd_index: which page descriptor index to manipulate
122 *
123 * This function:
124 * 1. Initializes the pd entry
125 * 2. Adds pd_entry in the pd_table
126 * 3. Mark the entry valid in i40e_hmc_pd_entry structure
127 * 4. Initializes the pd_entry's ref count to 1
128 * assumptions:
129 * 1. The memory for pd should be pinned down, physically contiguous and
130 * aligned on 4K boundary and zeroed memory.
131 * 2. It should be 4K in size.
132 **/
133i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,
134 struct i40e_hmc_info *hmc_info,
135 u32 pd_index)
136{
137 i40e_status ret_code = 0;
138 struct i40e_hmc_pd_table *pd_table;
139 struct i40e_hmc_pd_entry *pd_entry;
140 struct i40e_dma_mem mem;
141 u32 sd_idx, rel_pd_idx;
142 u64 *pd_addr;
143 u64 page_desc;
144
145 if (pd_index / I40E_HMC_PD_CNT_IN_SD >= hmc_info->sd_table.sd_cnt) {
146 ret_code = I40E_ERR_INVALID_PAGE_DESC_INDEX;
147 hw_dbg(hw, "i40e_add_pd_table_entry: bad pd_index\n");
148 goto exit;
149 }
150
151 /* find corresponding sd */
152 sd_idx = (pd_index / I40E_HMC_PD_CNT_IN_SD);
153 if (I40E_SD_TYPE_PAGED !=
154 hmc_info->sd_table.sd_entry[sd_idx].entry_type)
155 goto exit;
156
157 rel_pd_idx = (pd_index % I40E_HMC_PD_CNT_IN_SD);
158 pd_table = &hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;
159 pd_entry = &pd_table->pd_entry[rel_pd_idx];
160 if (!pd_entry->valid) {
161 /* allocate a 4K backing page */
162 ret_code = i40e_allocate_dma_mem(hw, &mem, i40e_mem_bp,
163 I40E_HMC_PAGED_BP_SIZE,
164 I40E_HMC_PD_BP_BUF_ALIGNMENT);
165 if (ret_code)
166 goto exit;
167
168 memcpy(&pd_entry->bp.addr, &mem, sizeof(struct i40e_dma_mem));
169 pd_entry->bp.sd_pd_index = pd_index;
170 pd_entry->bp.entry_type = I40E_SD_TYPE_PAGED;
171 /* Set page address and valid bit */
172 page_desc = mem.pa | 0x1;
173
174 pd_addr = (u64 *)pd_table->pd_page_addr.va;
175 pd_addr += rel_pd_idx;
176
177 /* Add the backing page physical address in the pd entry */
178 memcpy(pd_addr, &page_desc, sizeof(u64));
179
180 pd_entry->sd_index = sd_idx;
181 pd_entry->valid = true;
182 I40E_INC_PD_REFCNT(pd_table);
183 }
184 I40E_INC_BP_REFCNT(&pd_entry->bp);
185exit:
186 return ret_code;
187}
188
189/**
190 * i40e_remove_pd_bp - remove a backing page from a page descriptor
191 * @hw: pointer to our HW structure
192 * @hmc_info: pointer to the HMC configuration information structure
193 * @idx: the page index
194 * @is_pf: distinguishes a VF from a PF
195 *
196 * This function:
197 * 1. Marks the entry in pd tabe (for paged address mode) or in sd table
198 * (for direct address mode) invalid.
199 * 2. Write to register PMPDINV to invalidate the backing page in FV cache
200 * 3. Decrement the ref count for the pd _entry
201 * assumptions:
202 * 1. Caller can deallocate the memory used by backing storage after this
203 * function returns.
204 **/
205i40e_status i40e_remove_pd_bp(struct i40e_hw *hw,
206 struct i40e_hmc_info *hmc_info,
207 u32 idx, bool is_pf)
208{
209 i40e_status ret_code = 0;
210 struct i40e_hmc_pd_entry *pd_entry;
211 struct i40e_hmc_pd_table *pd_table;
212 struct i40e_hmc_sd_entry *sd_entry;
213 u32 sd_idx, rel_pd_idx;
214 u64 *pd_addr;
215
216 /* calculate index */
217 sd_idx = idx / I40E_HMC_PD_CNT_IN_SD;
218 rel_pd_idx = idx % I40E_HMC_PD_CNT_IN_SD;
219 if (sd_idx >= hmc_info->sd_table.sd_cnt) {
220 ret_code = I40E_ERR_INVALID_PAGE_DESC_INDEX;
221 hw_dbg(hw, "i40e_remove_pd_bp: bad idx\n");
222 goto exit;
223 }
224 sd_entry = &hmc_info->sd_table.sd_entry[sd_idx];
225 if (I40E_SD_TYPE_PAGED != sd_entry->entry_type) {
226 ret_code = I40E_ERR_INVALID_SD_TYPE;
227 hw_dbg(hw, "i40e_remove_pd_bp: wrong sd_entry type\n");
228 goto exit;
229 }
230 /* get the entry and decrease its ref counter */
231 pd_table = &hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;
232 pd_entry = &pd_table->pd_entry[rel_pd_idx];
233 I40E_DEC_BP_REFCNT(&pd_entry->bp);
234 if (pd_entry->bp.ref_cnt)
235 goto exit;
236
237 /* mark the entry invalid */
238 pd_entry->valid = false;
239 I40E_DEC_PD_REFCNT(pd_table);
240 pd_addr = (u64 *)pd_table->pd_page_addr.va;
241 pd_addr += rel_pd_idx;
242 memset(pd_addr, 0, sizeof(u64));
243 if (is_pf)
244 I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, idx);
245 else
246 I40E_INVALIDATE_VF_HMC_PD(hw, sd_idx, idx, hmc_info->hmc_fn_id);
247
248 /* free memory here */
249 ret_code = i40e_free_dma_mem(hw, &(pd_entry->bp.addr));
250 if (ret_code)
251 goto exit;
252 if (!pd_table->ref_cnt)
253 i40e_free_virt_mem(hw, &pd_table->pd_entry_virt_mem);
254exit:
255 return ret_code;
256}
257
258/**
259 * i40e_prep_remove_sd_bp - Prepares to remove a backing page from a sd entry
260 * @hmc_info: pointer to the HMC configuration information structure
261 * @idx: the page index
262 **/
263i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
264 u32 idx)
265{
266 i40e_status ret_code = 0;
267 struct i40e_hmc_sd_entry *sd_entry;
268
269 /* get the entry and decrease its ref counter */
270 sd_entry = &hmc_info->sd_table.sd_entry[idx];
271 I40E_DEC_BP_REFCNT(&sd_entry->u.bp);
272 if (sd_entry->u.bp.ref_cnt) {
273 ret_code = I40E_ERR_NOT_READY;
274 goto exit;
275 }
276 I40E_DEC_SD_REFCNT(&hmc_info->sd_table);
277
278 /* mark the entry invalid */
279 sd_entry->valid = false;
280exit:
281 return ret_code;
282}
283
284/**
285 * i40e_remove_sd_bp_new - Removes a backing page from a segment descriptor
286 * @hw: pointer to our hw struct
287 * @hmc_info: pointer to the HMC configuration information structure
288 * @idx: the page index
289 * @is_pf: used to distinguish between VF and PF
290 **/
291i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw,
292 struct i40e_hmc_info *hmc_info,
293 u32 idx, bool is_pf)
294{
295 struct i40e_hmc_sd_entry *sd_entry;
296 i40e_status ret_code = 0;
297
298 /* get the entry and decrease its ref counter */
299 sd_entry = &hmc_info->sd_table.sd_entry[idx];
300 if (is_pf) {
301 I40E_CLEAR_PF_SD_ENTRY(hw, idx, I40E_SD_TYPE_DIRECT);
302 } else {
303 ret_code = I40E_NOT_SUPPORTED;
304 goto exit;
305 }
306 ret_code = i40e_free_dma_mem(hw, &(sd_entry->u.bp.addr));
307 if (ret_code)
308 goto exit;
309exit:
310 return ret_code;
311}
312
313/**
314 * i40e_prep_remove_pd_page - Prepares to remove a PD page from sd entry.
315 * @hmc_info: pointer to the HMC configuration information structure
316 * @idx: segment descriptor index to find the relevant page descriptor
317 **/
318i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
319 u32 idx)
320{
321 i40e_status ret_code = 0;
322 struct i40e_hmc_sd_entry *sd_entry;
323
324 sd_entry = &hmc_info->sd_table.sd_entry[idx];
325
326 if (sd_entry->u.pd_table.ref_cnt) {
327 ret_code = I40E_ERR_NOT_READY;
328 goto exit;
329 }
330
331 /* mark the entry invalid */
332 sd_entry->valid = false;
333
334 I40E_DEC_SD_REFCNT(&hmc_info->sd_table);
335exit:
336 return ret_code;
337}
338
339/**
340 * i40e_remove_pd_page_new - Removes a PD page from sd entry.
341 * @hw: pointer to our hw struct
342 * @hmc_info: pointer to the HMC configuration information structure
343 * @idx: segment descriptor index to find the relevant page descriptor
344 * @is_pf: used to distinguish between VF and PF
345 **/
346i40e_status i40e_remove_pd_page_new(struct i40e_hw *hw,
347 struct i40e_hmc_info *hmc_info,
348 u32 idx, bool is_pf)
349{
350 i40e_status ret_code = 0;
351 struct i40e_hmc_sd_entry *sd_entry;
352
353 sd_entry = &hmc_info->sd_table.sd_entry[idx];
354 if (is_pf) {
355 I40E_CLEAR_PF_SD_ENTRY(hw, idx, I40E_SD_TYPE_PAGED);
356 } else {
357 ret_code = I40E_NOT_SUPPORTED;
358 goto exit;
359 }
360 /* free memory here */
361 ret_code = i40e_free_dma_mem(hw, &(sd_entry->u.pd_table.pd_page_addr));
362 if (ret_code)
363 goto exit;
364exit:
365 return ret_code;
366}
diff --git a/drivers/net/ethernet/intel/i40e/i40e_hmc.h b/drivers/net/ethernet/intel/i40e/i40e_hmc.h
new file mode 100644
index 000000000000..aacd42a261e9
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_hmc.h
@@ -0,0 +1,245 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_HMC_H_
29#define _I40E_HMC_H_
30
31#define I40E_HMC_MAX_BP_COUNT 512
32
33/* forward-declare the HW struct for the compiler */
34struct i40e_hw;
35
36#define I40E_HMC_INFO_SIGNATURE 0x484D5347 /* HMSG */
37#define I40E_HMC_PD_CNT_IN_SD 512
38#define I40E_HMC_DIRECT_BP_SIZE 0x200000 /* 2M */
39#define I40E_HMC_PAGED_BP_SIZE 4096
40#define I40E_HMC_PD_BP_BUF_ALIGNMENT 4096
41#define I40E_FIRST_VF_FPM_ID 16
42
43struct i40e_hmc_obj_info {
44 u64 base; /* base addr in FPM */
45 u32 max_cnt; /* max count available for this hmc func */
46 u32 cnt; /* count of objects driver actually wants to create */
47 u64 size; /* size in bytes of one object */
48};
49
50enum i40e_sd_entry_type {
51 I40E_SD_TYPE_INVALID = 0,
52 I40E_SD_TYPE_PAGED = 1,
53 I40E_SD_TYPE_DIRECT = 2
54};
55
56struct i40e_hmc_bp {
57 enum i40e_sd_entry_type entry_type;
58 struct i40e_dma_mem addr; /* populate to be used by hw */
59 u32 sd_pd_index;
60 u32 ref_cnt;
61};
62
63struct i40e_hmc_pd_entry {
64 struct i40e_hmc_bp bp;
65 u32 sd_index;
66 bool valid;
67};
68
69struct i40e_hmc_pd_table {
70 struct i40e_dma_mem pd_page_addr; /* populate to be used by hw */
71 struct i40e_hmc_pd_entry *pd_entry; /* [512] for sw book keeping */
72 struct i40e_virt_mem pd_entry_virt_mem; /* virt mem for pd_entry */
73
74 u32 ref_cnt;
75 u32 sd_index;
76};
77
78struct i40e_hmc_sd_entry {
79 enum i40e_sd_entry_type entry_type;
80 bool valid;
81
82 union {
83 struct i40e_hmc_pd_table pd_table;
84 struct i40e_hmc_bp bp;
85 } u;
86};
87
88struct i40e_hmc_sd_table {
89 struct i40e_virt_mem addr; /* used to track sd_entry allocations */
90 u32 sd_cnt;
91 u32 ref_cnt;
92 struct i40e_hmc_sd_entry *sd_entry; /* (sd_cnt*512) entries max */
93};
94
95struct i40e_hmc_info {
96 u32 signature;
97 /* equals to pci func num for PF and dynamically allocated for VFs */
98 u8 hmc_fn_id;
99 u16 first_sd_index; /* index of the first available SD */
100
101 /* hmc objects */
102 struct i40e_hmc_obj_info *hmc_obj;
103 struct i40e_virt_mem hmc_obj_virt_mem;
104 struct i40e_hmc_sd_table sd_table;
105};
106
107#define I40E_INC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt++)
108#define I40E_INC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt++)
109#define I40E_INC_BP_REFCNT(bp) ((bp)->ref_cnt++)
110
111#define I40E_DEC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt--)
112#define I40E_DEC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt--)
113#define I40E_DEC_BP_REFCNT(bp) ((bp)->ref_cnt--)
114
115/**
116 * I40E_SET_PF_SD_ENTRY - marks the sd entry as valid in the hardware
117 * @hw: pointer to our hw struct
118 * @pa: pointer to physical address
119 * @sd_index: segment descriptor index
120 * @hmc_fn_id: hmc function id
121 * @type: if sd entry is direct or paged
122 **/
123#define I40E_SET_PF_SD_ENTRY(hw, pa, sd_index, type) \
124{ \
125 u32 val1, val2, val3; \
126 val1 = (u32)(upper_32_bits(pa)); \
127 val2 = (u32)(pa) | (I40E_HMC_MAX_BP_COUNT << \
128 I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
129 ((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
130 I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) | \
131 (1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \
132 val3 = (sd_index) | (1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
133 wr32((hw), I40E_PFHMC_SDDATAHIGH, val1); \
134 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
135 wr32((hw), I40E_PFHMC_SDCMD, val3); \
136}
137
138/**
139 * I40E_CLEAR_PF_SD_ENTRY - marks the sd entry as invalid in the hardware
140 * @hw: pointer to our hw struct
141 * @sd_index: segment descriptor index
142 * @hmc_fn_id: hmc function id
143 * @type: if sd entry is direct or paged
144 **/
145#define I40E_CLEAR_PF_SD_ENTRY(hw, sd_index, type) \
146{ \
147 u32 val2, val3; \
148 val2 = (I40E_HMC_MAX_BP_COUNT << \
149 I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
150 ((((type) == I40E_SD_TYPE_PAGED) ? 0 : 1) << \
151 I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT); \
152 val3 = (sd_index) | (1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
153 wr32((hw), I40E_PFHMC_SDDATAHIGH, 0); \
154 wr32((hw), I40E_PFHMC_SDDATALOW, val2); \
155 wr32((hw), I40E_PFHMC_SDCMD, val3); \
156}
157
158/**
159 * I40E_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware
160 * @hw: pointer to our hw struct
161 * @sd_idx: segment descriptor index
162 * @pd_idx: page descriptor index
163 * @hmc_fn_id: hmc function id
164 **/
165#define I40E_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx) \
166 wr32((hw), I40E_PFHMC_PDINV, \
167 (((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \
168 ((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))
169
170#define I40E_INVALIDATE_VF_HMC_PD(hw, sd_idx, pd_idx, hmc_fn_id) \
171 wr32((hw), I40E_GLHMC_VFPDINV((hmc_fn_id) - I40E_FIRST_VF_FPM_ID), \
172 (((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \
173 ((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)))
174
175/**
176 * I40E_FIND_SD_INDEX_LIMIT - finds segment descriptor index limit
177 * @hmc_info: pointer to the HMC configuration information structure
178 * @type: type of HMC resources we're searching
179 * @index: starting index for the object
180 * @cnt: number of objects we're trying to create
181 * @sd_idx: pointer to return index of the segment descriptor in question
182 * @sd_limit: pointer to return the maximum number of segment descriptors
183 *
184 * This function calculates the segment descriptor index and index limit
185 * for the resource defined by i40e_hmc_rsrc_type.
186 **/
187#define I40E_FIND_SD_INDEX_LIMIT(hmc_info, type, index, cnt, sd_idx, sd_limit)\
188{ \
189 u64 fpm_addr, fpm_limit; \
190 fpm_addr = (hmc_info)->hmc_obj[(type)].base + \
191 (hmc_info)->hmc_obj[(type)].size * (index); \
192 fpm_limit = fpm_addr + (hmc_info)->hmc_obj[(type)].size * (cnt);\
193 *(sd_idx) = (u32)(fpm_addr / I40E_HMC_DIRECT_BP_SIZE); \
194 *(sd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_DIRECT_BP_SIZE); \
195 /* add one more to the limit to correct our range */ \
196 *(sd_limit) += 1; \
197}
198
199/**
200 * I40E_FIND_PD_INDEX_LIMIT - finds page descriptor index limit
201 * @hmc_info: pointer to the HMC configuration information struct
202 * @type: HMC resource type we're examining
203 * @idx: starting index for the object
204 * @cnt: number of objects we're trying to create
205 * @pd_index: pointer to return page descriptor index
206 * @pd_limit: pointer to return page descriptor index limit
207 *
208 * Calculates the page descriptor index and index limit for the resource
209 * defined by i40e_hmc_rsrc_type.
210 **/
211#define I40E_FIND_PD_INDEX_LIMIT(hmc_info, type, idx, cnt, pd_index, pd_limit)\
212{ \
213 u64 fpm_adr, fpm_limit; \
214 fpm_adr = (hmc_info)->hmc_obj[(type)].base + \
215 (hmc_info)->hmc_obj[(type)].size * (idx); \
216 fpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt); \
217 *(pd_index) = (u32)(fpm_adr / I40E_HMC_PAGED_BP_SIZE); \
218 *(pd_limit) = (u32)((fpm_limit - 1) / I40E_HMC_PAGED_BP_SIZE); \
219 /* add one more to the limit to correct our range */ \
220 *(pd_limit) += 1; \
221}
222i40e_status i40e_add_sd_table_entry(struct i40e_hw *hw,
223 struct i40e_hmc_info *hmc_info,
224 u32 sd_index,
225 enum i40e_sd_entry_type type,
226 u64 direct_mode_sz);
227
228i40e_status i40e_add_pd_table_entry(struct i40e_hw *hw,
229 struct i40e_hmc_info *hmc_info,
230 u32 pd_index);
231i40e_status i40e_remove_pd_bp(struct i40e_hw *hw,
232 struct i40e_hmc_info *hmc_info,
233 u32 idx, bool is_pf);
234i40e_status i40e_prep_remove_sd_bp(struct i40e_hmc_info *hmc_info,
235 u32 idx);
236i40e_status i40e_remove_sd_bp_new(struct i40e_hw *hw,
237 struct i40e_hmc_info *hmc_info,
238 u32 idx, bool is_pf);
239i40e_status i40e_prep_remove_pd_page(struct i40e_hmc_info *hmc_info,
240 u32 idx);
241i40e_status i40e_remove_pd_page_new(struct i40e_hw *hw,
242 struct i40e_hmc_info *hmc_info,
243 u32 idx, bool is_pf);
244
245#endif /* _I40E_HMC_H_ */
diff --git a/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c b/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c
new file mode 100644
index 000000000000..a695b91c9c79
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.c
@@ -0,0 +1,1006 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e_osdep.h"
29#include "i40e_register.h"
30#include "i40e_type.h"
31#include "i40e_hmc.h"
32#include "i40e_lan_hmc.h"
33#include "i40e_prototype.h"
34
35/* lan specific interface functions */
36
37/**
38 * i40e_align_l2obj_base - aligns base object pointer to 512 bytes
39 * @offset: base address offset needing alignment
40 *
41 * Aligns the layer 2 function private memory so it's 512-byte aligned.
42 **/
43static u64 i40e_align_l2obj_base(u64 offset)
44{
45 u64 aligned_offset = offset;
46
47 if ((offset % I40E_HMC_L2OBJ_BASE_ALIGNMENT) > 0)
48 aligned_offset += (I40E_HMC_L2OBJ_BASE_ALIGNMENT -
49 (offset % I40E_HMC_L2OBJ_BASE_ALIGNMENT));
50
51 return aligned_offset;
52}
53
54/**
55 * i40e_calculate_l2fpm_size - calculates layer 2 FPM memory size
56 * @txq_num: number of Tx queues needing backing context
57 * @rxq_num: number of Rx queues needing backing context
58 * @fcoe_cntx_num: amount of FCoE statefull contexts needing backing context
59 * @fcoe_filt_num: number of FCoE filters needing backing context
60 *
61 * Calculates the maximum amount of memory for the function required, based
62 * on the number of resources it must provide context for.
63 **/
64static u64 i40e_calculate_l2fpm_size(u32 txq_num, u32 rxq_num,
65 u32 fcoe_cntx_num, u32 fcoe_filt_num)
66{
67 u64 fpm_size = 0;
68
69 fpm_size = txq_num * I40E_HMC_OBJ_SIZE_TXQ;
70 fpm_size = i40e_align_l2obj_base(fpm_size);
71
72 fpm_size += (rxq_num * I40E_HMC_OBJ_SIZE_RXQ);
73 fpm_size = i40e_align_l2obj_base(fpm_size);
74
75 fpm_size += (fcoe_cntx_num * I40E_HMC_OBJ_SIZE_FCOE_CNTX);
76 fpm_size = i40e_align_l2obj_base(fpm_size);
77
78 fpm_size += (fcoe_filt_num * I40E_HMC_OBJ_SIZE_FCOE_FILT);
79 fpm_size = i40e_align_l2obj_base(fpm_size);
80
81 return fpm_size;
82}
83
84/**
85 * i40e_init_lan_hmc - initialize i40e_hmc_info struct
86 * @hw: pointer to the HW structure
87 * @txq_num: number of Tx queues needing backing context
88 * @rxq_num: number of Rx queues needing backing context
89 * @fcoe_cntx_num: amount of FCoE statefull contexts needing backing context
90 * @fcoe_filt_num: number of FCoE filters needing backing context
91 *
92 * This function will be called once per physical function initialization.
93 * It will fill out the i40e_hmc_obj_info structure for LAN objects based on
94 * the driver's provided input, as well as information from the HMC itself
95 * loaded from NVRAM.
96 *
97 * Assumptions:
98 * - HMC Resource Profile has been selected before calling this function.
99 **/
100i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
101 u32 rxq_num, u32 fcoe_cntx_num,
102 u32 fcoe_filt_num)
103{
104 struct i40e_hmc_obj_info *obj, *full_obj;
105 i40e_status ret_code = 0;
106 u64 l2fpm_size;
107 u32 size_exp;
108
109 hw->hmc.signature = I40E_HMC_INFO_SIGNATURE;
110 hw->hmc.hmc_fn_id = hw->pf_id;
111
112 /* allocate memory for hmc_obj */
113 ret_code = i40e_allocate_virt_mem(hw, &hw->hmc.hmc_obj_virt_mem,
114 sizeof(struct i40e_hmc_obj_info) * I40E_HMC_LAN_MAX);
115 if (ret_code)
116 goto init_lan_hmc_out;
117 hw->hmc.hmc_obj = (struct i40e_hmc_obj_info *)
118 hw->hmc.hmc_obj_virt_mem.va;
119
120 /* The full object will be used to create the LAN HMC SD */
121 full_obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_FULL];
122 full_obj->max_cnt = 0;
123 full_obj->cnt = 0;
124 full_obj->base = 0;
125 full_obj->size = 0;
126
127 /* Tx queue context information */
128 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_TX];
129 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);
130 obj->cnt = txq_num;
131 obj->base = 0;
132 size_exp = rd32(hw, I40E_GLHMC_LANTXOBJSZ);
133 obj->size = (u64)1 << size_exp;
134
135 /* validate values requested by driver don't exceed HMC capacity */
136 if (txq_num > obj->max_cnt) {
137 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
138 hw_dbg(hw, "i40e_init_lan_hmc: Tx context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
139 txq_num, obj->max_cnt, ret_code);
140 goto init_lan_hmc_out;
141 }
142
143 /* aggregate values into the full LAN object for later */
144 full_obj->max_cnt += obj->max_cnt;
145 full_obj->cnt += obj->cnt;
146
147 /* Rx queue context information */
148 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_RX];
149 obj->max_cnt = rd32(hw, I40E_GLHMC_LANQMAX);
150 obj->cnt = rxq_num;
151 obj->base = hw->hmc.hmc_obj[I40E_HMC_LAN_TX].base +
152 (hw->hmc.hmc_obj[I40E_HMC_LAN_TX].cnt *
153 hw->hmc.hmc_obj[I40E_HMC_LAN_TX].size);
154 obj->base = i40e_align_l2obj_base(obj->base);
155 size_exp = rd32(hw, I40E_GLHMC_LANRXOBJSZ);
156 obj->size = (u64)1 << size_exp;
157
158 /* validate values requested by driver don't exceed HMC capacity */
159 if (rxq_num > obj->max_cnt) {
160 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
161 hw_dbg(hw, "i40e_init_lan_hmc: Rx context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
162 rxq_num, obj->max_cnt, ret_code);
163 goto init_lan_hmc_out;
164 }
165
166 /* aggregate values into the full LAN object for later */
167 full_obj->max_cnt += obj->max_cnt;
168 full_obj->cnt += obj->cnt;
169
170 /* FCoE context information */
171 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX];
172 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEMAX);
173 obj->cnt = fcoe_cntx_num;
174 obj->base = hw->hmc.hmc_obj[I40E_HMC_LAN_RX].base +
175 (hw->hmc.hmc_obj[I40E_HMC_LAN_RX].cnt *
176 hw->hmc.hmc_obj[I40E_HMC_LAN_RX].size);
177 obj->base = i40e_align_l2obj_base(obj->base);
178 size_exp = rd32(hw, I40E_GLHMC_FCOEDDPOBJSZ);
179 obj->size = (u64)1 << size_exp;
180
181 /* validate values requested by driver don't exceed HMC capacity */
182 if (fcoe_cntx_num > obj->max_cnt) {
183 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
184 hw_dbg(hw, "i40e_init_lan_hmc: FCoE context: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
185 fcoe_cntx_num, obj->max_cnt, ret_code);
186 goto init_lan_hmc_out;
187 }
188
189 /* aggregate values into the full LAN object for later */
190 full_obj->max_cnt += obj->max_cnt;
191 full_obj->cnt += obj->cnt;
192
193 /* FCoE filter information */
194 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_FILT];
195 obj->max_cnt = rd32(hw, I40E_GLHMC_FCOEFMAX);
196 obj->cnt = fcoe_filt_num;
197 obj->base = hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].base +
198 (hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].cnt *
199 hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX].size);
200 obj->base = i40e_align_l2obj_base(obj->base);
201 size_exp = rd32(hw, I40E_GLHMC_FCOEFOBJSZ);
202 obj->size = (u64)1 << size_exp;
203
204 /* validate values requested by driver don't exceed HMC capacity */
205 if (fcoe_filt_num > obj->max_cnt) {
206 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
207 hw_dbg(hw, "i40e_init_lan_hmc: FCoE filter: asks for 0x%x but max allowed is 0x%x, returns error %d\n",
208 fcoe_filt_num, obj->max_cnt, ret_code);
209 goto init_lan_hmc_out;
210 }
211
212 /* aggregate values into the full LAN object for later */
213 full_obj->max_cnt += obj->max_cnt;
214 full_obj->cnt += obj->cnt;
215
216 hw->hmc.first_sd_index = 0;
217 hw->hmc.sd_table.ref_cnt = 0;
218 l2fpm_size = i40e_calculate_l2fpm_size(txq_num, rxq_num, fcoe_cntx_num,
219 fcoe_filt_num);
220 if (NULL == hw->hmc.sd_table.sd_entry) {
221 hw->hmc.sd_table.sd_cnt = (u32)
222 (l2fpm_size + I40E_HMC_DIRECT_BP_SIZE - 1) /
223 I40E_HMC_DIRECT_BP_SIZE;
224
225 /* allocate the sd_entry members in the sd_table */
226 ret_code = i40e_allocate_virt_mem(hw, &hw->hmc.sd_table.addr,
227 (sizeof(struct i40e_hmc_sd_entry) *
228 hw->hmc.sd_table.sd_cnt));
229 if (ret_code)
230 goto init_lan_hmc_out;
231 hw->hmc.sd_table.sd_entry =
232 (struct i40e_hmc_sd_entry *)hw->hmc.sd_table.addr.va;
233 }
234 /* store in the LAN full object for later */
235 full_obj->size = l2fpm_size;
236
237init_lan_hmc_out:
238 return ret_code;
239}
240
241/**
242 * i40e_remove_pd_page - Remove a page from the page descriptor table
243 * @hw: pointer to the HW structure
244 * @hmc_info: pointer to the HMC configuration information structure
245 * @idx: segment descriptor index to find the relevant page descriptor
246 *
247 * This function:
248 * 1. Marks the entry in pd table (for paged address mode) invalid
249 * 2. write to register PMPDINV to invalidate the backing page in FV cache
250 * 3. Decrement the ref count for pd_entry
251 * assumptions:
252 * 1. caller can deallocate the memory used by pd after this function
253 * returns.
254 **/
255static i40e_status i40e_remove_pd_page(struct i40e_hw *hw,
256 struct i40e_hmc_info *hmc_info,
257 u32 idx)
258{
259 i40e_status ret_code = 0;
260
261 if (!i40e_prep_remove_pd_page(hmc_info, idx))
262 ret_code = i40e_remove_pd_page_new(hw, hmc_info, idx, true);
263
264 return ret_code;
265}
266
267/**
268 * i40e_remove_sd_bp - remove a backing page from a segment descriptor
269 * @hw: pointer to our HW structure
270 * @hmc_info: pointer to the HMC configuration information structure
271 * @idx: the page index
272 *
273 * This function:
274 * 1. Marks the entry in sd table (for direct address mode) invalid
275 * 2. write to register PMSDCMD, PMSDDATALOW(PMSDDATALOW.PMSDVALID set
276 * to 0) and PMSDDATAHIGH to invalidate the sd page
277 * 3. Decrement the ref count for the sd_entry
278 * assumptions:
279 * 1. caller can deallocate the memory used by backing storage after this
280 * function returns.
281 **/
282static i40e_status i40e_remove_sd_bp(struct i40e_hw *hw,
283 struct i40e_hmc_info *hmc_info,
284 u32 idx)
285{
286 i40e_status ret_code = 0;
287
288 if (!i40e_prep_remove_sd_bp(hmc_info, idx))
289 ret_code = i40e_remove_sd_bp_new(hw, hmc_info, idx, true);
290
291 return ret_code;
292}
293
294/**
295 * i40e_create_lan_hmc_object - allocate backing store for hmc objects
296 * @hw: pointer to the HW structure
297 * @info: pointer to i40e_hmc_create_obj_info struct
298 *
299 * This will allocate memory for PDs and backing pages and populate
300 * the sd and pd entries.
301 **/
302static i40e_status i40e_create_lan_hmc_object(struct i40e_hw *hw,
303 struct i40e_hmc_lan_create_obj_info *info)
304{
305 i40e_status ret_code = 0;
306 struct i40e_hmc_sd_entry *sd_entry;
307 u32 pd_idx1 = 0, pd_lmt1 = 0;
308 u32 pd_idx = 0, pd_lmt = 0;
309 bool pd_error = false;
310 u32 sd_idx, sd_lmt;
311 u64 sd_size;
312 u32 i, j;
313
314 if (NULL == info) {
315 ret_code = I40E_ERR_BAD_PTR;
316 hw_dbg(hw, "i40e_create_lan_hmc_object: bad info ptr\n");
317 goto exit;
318 }
319 if (NULL == info->hmc_info) {
320 ret_code = I40E_ERR_BAD_PTR;
321 hw_dbg(hw, "i40e_create_lan_hmc_object: bad hmc_info ptr\n");
322 goto exit;
323 }
324 if (I40E_HMC_INFO_SIGNATURE != info->hmc_info->signature) {
325 ret_code = I40E_ERR_BAD_PTR;
326 hw_dbg(hw, "i40e_create_lan_hmc_object: bad signature\n");
327 goto exit;
328 }
329
330 if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
331 ret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;
332 hw_dbg(hw, "i40e_create_lan_hmc_object: returns error %d\n",
333 ret_code);
334 goto exit;
335 }
336 if ((info->start_idx + info->count) >
337 info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
338 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
339 hw_dbg(hw, "i40e_create_lan_hmc_object: returns error %d\n",
340 ret_code);
341 goto exit;
342 }
343
344 /* find sd index and limit */
345 I40E_FIND_SD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
346 info->start_idx, info->count,
347 &sd_idx, &sd_lmt);
348 if (sd_idx >= info->hmc_info->sd_table.sd_cnt ||
349 sd_lmt > info->hmc_info->sd_table.sd_cnt) {
350 ret_code = I40E_ERR_INVALID_SD_INDEX;
351 goto exit;
352 }
353 /* find pd index */
354 I40E_FIND_PD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
355 info->start_idx, info->count, &pd_idx,
356 &pd_lmt);
357
358 /* This is to cover for cases where you may not want to have an SD with
359 * the full 2M memory but something smaller. By not filling out any
360 * size, the function will default the SD size to be 2M.
361 */
362 if (info->direct_mode_sz == 0)
363 sd_size = I40E_HMC_DIRECT_BP_SIZE;
364 else
365 sd_size = info->direct_mode_sz;
366
367 /* check if all the sds are valid. If not, allocate a page and
368 * initialize it.
369 */
370 for (j = sd_idx; j < sd_lmt; j++) {
371 /* update the sd table entry */
372 ret_code = i40e_add_sd_table_entry(hw, info->hmc_info, j,
373 info->entry_type,
374 sd_size);
375 if (ret_code)
376 goto exit_sd_error;
377 sd_entry = &info->hmc_info->sd_table.sd_entry[j];
378 if (I40E_SD_TYPE_PAGED == sd_entry->entry_type) {
379 /* check if all the pds in this sd are valid. If not,
380 * allocate a page and initialize it.
381 */
382
383 /* find pd_idx and pd_lmt in this sd */
384 pd_idx1 = max(pd_idx, (j * I40E_HMC_MAX_BP_COUNT));
385 pd_lmt1 = min(pd_lmt,
386 ((j + 1) * I40E_HMC_MAX_BP_COUNT));
387 for (i = pd_idx1; i < pd_lmt1; i++) {
388 /* update the pd table entry */
389 ret_code = i40e_add_pd_table_entry(hw,
390 info->hmc_info,
391 i);
392 if (ret_code) {
393 pd_error = true;
394 break;
395 }
396 }
397 if (pd_error) {
398 /* remove the backing pages from pd_idx1 to i */
399 while (i && (i > pd_idx1)) {
400 i40e_remove_pd_bp(hw, info->hmc_info,
401 (i - 1), true);
402 i--;
403 }
404 }
405 }
406 if (!sd_entry->valid) {
407 sd_entry->valid = true;
408 switch (sd_entry->entry_type) {
409 case I40E_SD_TYPE_PAGED:
410 I40E_SET_PF_SD_ENTRY(hw,
411 sd_entry->u.pd_table.pd_page_addr.pa,
412 j, sd_entry->entry_type);
413 break;
414 case I40E_SD_TYPE_DIRECT:
415 I40E_SET_PF_SD_ENTRY(hw, sd_entry->u.bp.addr.pa,
416 j, sd_entry->entry_type);
417 break;
418 default:
419 ret_code = I40E_ERR_INVALID_SD_TYPE;
420 goto exit;
421 break;
422 }
423 }
424 }
425 goto exit;
426
427exit_sd_error:
428 /* cleanup for sd entries from j to sd_idx */
429 while (j && (j > sd_idx)) {
430 sd_entry = &info->hmc_info->sd_table.sd_entry[j - 1];
431 switch (sd_entry->entry_type) {
432 case I40E_SD_TYPE_PAGED:
433 pd_idx1 = max(pd_idx,
434 ((j - 1) * I40E_HMC_MAX_BP_COUNT));
435 pd_lmt1 = min(pd_lmt, (j * I40E_HMC_MAX_BP_COUNT));
436 for (i = pd_idx1; i < pd_lmt1; i++) {
437 i40e_remove_pd_bp(
438 hw,
439 info->hmc_info,
440 i,
441 true);
442 }
443 i40e_remove_pd_page(hw, info->hmc_info, (j - 1));
444 break;
445 case I40E_SD_TYPE_DIRECT:
446 i40e_remove_sd_bp(hw, info->hmc_info, (j - 1));
447 break;
448 default:
449 ret_code = I40E_ERR_INVALID_SD_TYPE;
450 break;
451 }
452 j--;
453 }
454exit:
455 return ret_code;
456}
457
458/**
459 * i40e_configure_lan_hmc - prepare the HMC backing store
460 * @hw: pointer to the hw structure
461 * @model: the model for the layout of the SD/PD tables
462 *
463 * - This function will be called once per physical function initialization.
464 * - This function will be called after i40e_init_lan_hmc() and before
465 * any LAN/FCoE HMC objects can be created.
466 **/
467i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
468 enum i40e_hmc_model model)
469{
470 struct i40e_hmc_lan_create_obj_info info;
471 i40e_status ret_code = 0;
472 u8 hmc_fn_id = hw->hmc.hmc_fn_id;
473 struct i40e_hmc_obj_info *obj;
474
475 /* Initialize part of the create object info struct */
476 info.hmc_info = &hw->hmc;
477 info.rsrc_type = I40E_HMC_LAN_FULL;
478 info.start_idx = 0;
479 info.direct_mode_sz = hw->hmc.hmc_obj[I40E_HMC_LAN_FULL].size;
480
481 /* Build the SD entry for the LAN objects */
482 switch (model) {
483 case I40E_HMC_MODEL_DIRECT_PREFERRED:
484 case I40E_HMC_MODEL_DIRECT_ONLY:
485 info.entry_type = I40E_SD_TYPE_DIRECT;
486 /* Make one big object, a single SD */
487 info.count = 1;
488 ret_code = i40e_create_lan_hmc_object(hw, &info);
489 if ((ret_code) &&
490 (model == I40E_HMC_MODEL_DIRECT_PREFERRED))
491 goto try_type_paged;
492 else if (ret_code)
493 goto configure_lan_hmc_out;
494 /* else clause falls through the break */
495 break;
496 case I40E_HMC_MODEL_PAGED_ONLY:
497try_type_paged:
498 info.entry_type = I40E_SD_TYPE_PAGED;
499 /* Make one big object in the PD table */
500 info.count = 1;
501 ret_code = i40e_create_lan_hmc_object(hw, &info);
502 if (ret_code)
503 goto configure_lan_hmc_out;
504 break;
505 default:
506 /* unsupported type */
507 ret_code = I40E_ERR_INVALID_SD_TYPE;
508 hw_dbg(hw, "i40e_configure_lan_hmc: Unknown SD type: %d\n",
509 ret_code);
510 goto configure_lan_hmc_out;
511 break;
512 }
513
514 /* Configure and program the FPM registers so objects can be created */
515
516 /* Tx contexts */
517 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_TX];
518 wr32(hw, I40E_GLHMC_LANTXBASE(hmc_fn_id),
519 (u32)((obj->base & I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK) / 512));
520 wr32(hw, I40E_GLHMC_LANTXCNT(hmc_fn_id), obj->cnt);
521
522 /* Rx contexts */
523 obj = &hw->hmc.hmc_obj[I40E_HMC_LAN_RX];
524 wr32(hw, I40E_GLHMC_LANRXBASE(hmc_fn_id),
525 (u32)((obj->base & I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK) / 512));
526 wr32(hw, I40E_GLHMC_LANRXCNT(hmc_fn_id), obj->cnt);
527
528 /* FCoE contexts */
529 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_CTX];
530 wr32(hw, I40E_GLHMC_FCOEDDPBASE(hmc_fn_id),
531 (u32)((obj->base & I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK) / 512));
532 wr32(hw, I40E_GLHMC_FCOEDDPCNT(hmc_fn_id), obj->cnt);
533
534 /* FCoE filters */
535 obj = &hw->hmc.hmc_obj[I40E_HMC_FCOE_FILT];
536 wr32(hw, I40E_GLHMC_FCOEFBASE(hmc_fn_id),
537 (u32)((obj->base & I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK) / 512));
538 wr32(hw, I40E_GLHMC_FCOEFCNT(hmc_fn_id), obj->cnt);
539
540configure_lan_hmc_out:
541 return ret_code;
542}
543
544/**
545 * i40e_delete_hmc_object - remove hmc objects
546 * @hw: pointer to the HW structure
547 * @info: pointer to i40e_hmc_delete_obj_info struct
548 *
549 * This will de-populate the SDs and PDs. It frees
550 * the memory for PDS and backing storage. After this function is returned,
551 * caller should deallocate memory allocated previously for
552 * book-keeping information about PDs and backing storage.
553 **/
554static i40e_status i40e_delete_lan_hmc_object(struct i40e_hw *hw,
555 struct i40e_hmc_lan_delete_obj_info *info)
556{
557 i40e_status ret_code = 0;
558 struct i40e_hmc_pd_table *pd_table;
559 u32 pd_idx, pd_lmt, rel_pd_idx;
560 u32 sd_idx, sd_lmt;
561 u32 i, j;
562
563 if (NULL == info) {
564 ret_code = I40E_ERR_BAD_PTR;
565 hw_dbg(hw, "i40e_delete_hmc_object: bad info ptr\n");
566 goto exit;
567 }
568 if (NULL == info->hmc_info) {
569 ret_code = I40E_ERR_BAD_PTR;
570 hw_dbg(hw, "i40e_delete_hmc_object: bad info->hmc_info ptr\n");
571 goto exit;
572 }
573 if (I40E_HMC_INFO_SIGNATURE != info->hmc_info->signature) {
574 ret_code = I40E_ERR_BAD_PTR;
575 hw_dbg(hw, "i40e_delete_hmc_object: bad hmc_info->signature\n");
576 goto exit;
577 }
578
579 if (NULL == info->hmc_info->sd_table.sd_entry) {
580 ret_code = I40E_ERR_BAD_PTR;
581 hw_dbg(hw, "i40e_delete_hmc_object: bad sd_entry\n");
582 goto exit;
583 }
584
585 if (NULL == info->hmc_info->hmc_obj) {
586 ret_code = I40E_ERR_BAD_PTR;
587 hw_dbg(hw, "i40e_delete_hmc_object: bad hmc_info->hmc_obj\n");
588 goto exit;
589 }
590 if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
591 ret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;
592 hw_dbg(hw, "i40e_delete_hmc_object: returns error %d\n",
593 ret_code);
594 goto exit;
595 }
596
597 if ((info->start_idx + info->count) >
598 info->hmc_info->hmc_obj[info->rsrc_type].cnt) {
599 ret_code = I40E_ERR_INVALID_HMC_OBJ_COUNT;
600 hw_dbg(hw, "i40e_delete_hmc_object: returns error %d\n",
601 ret_code);
602 goto exit;
603 }
604
605 I40E_FIND_PD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
606 info->start_idx, info->count, &pd_idx,
607 &pd_lmt);
608
609 for (j = pd_idx; j < pd_lmt; j++) {
610 sd_idx = j / I40E_HMC_PD_CNT_IN_SD;
611
612 if (I40E_SD_TYPE_PAGED !=
613 info->hmc_info->sd_table.sd_entry[sd_idx].entry_type)
614 continue;
615
616 rel_pd_idx = j % I40E_HMC_PD_CNT_IN_SD;
617
618 pd_table =
619 &info->hmc_info->sd_table.sd_entry[sd_idx].u.pd_table;
620 if (pd_table->pd_entry[rel_pd_idx].valid) {
621 ret_code = i40e_remove_pd_bp(hw, info->hmc_info,
622 j, true);
623 if (ret_code)
624 goto exit;
625 }
626 }
627
628 /* find sd index and limit */
629 I40E_FIND_SD_INDEX_LIMIT(info->hmc_info, info->rsrc_type,
630 info->start_idx, info->count,
631 &sd_idx, &sd_lmt);
632 if (sd_idx >= info->hmc_info->sd_table.sd_cnt ||
633 sd_lmt > info->hmc_info->sd_table.sd_cnt) {
634 ret_code = I40E_ERR_INVALID_SD_INDEX;
635 goto exit;
636 }
637
638 for (i = sd_idx; i < sd_lmt; i++) {
639 if (!info->hmc_info->sd_table.sd_entry[i].valid)
640 continue;
641 switch (info->hmc_info->sd_table.sd_entry[i].entry_type) {
642 case I40E_SD_TYPE_DIRECT:
643 ret_code = i40e_remove_sd_bp(hw, info->hmc_info, i);
644 if (ret_code)
645 goto exit;
646 break;
647 case I40E_SD_TYPE_PAGED:
648 ret_code = i40e_remove_pd_page(hw, info->hmc_info, i);
649 if (ret_code)
650 goto exit;
651 break;
652 default:
653 break;
654 }
655 }
656exit:
657 return ret_code;
658}
659
660/**
661 * i40e_shutdown_lan_hmc - Remove HMC backing store, free allocated memory
662 * @hw: pointer to the hw structure
663 *
664 * This must be called by drivers as they are shutting down and being
665 * removed from the OS.
666 **/
667i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw)
668{
669 struct i40e_hmc_lan_delete_obj_info info;
670 i40e_status ret_code;
671
672 info.hmc_info = &hw->hmc;
673 info.rsrc_type = I40E_HMC_LAN_FULL;
674 info.start_idx = 0;
675 info.count = 1;
676
677 /* delete the object */
678 ret_code = i40e_delete_lan_hmc_object(hw, &info);
679
680 /* free the SD table entry for LAN */
681 i40e_free_virt_mem(hw, &hw->hmc.sd_table.addr);
682 hw->hmc.sd_table.sd_cnt = 0;
683 hw->hmc.sd_table.sd_entry = NULL;
684
685 /* free memory used for hmc_obj */
686 i40e_free_virt_mem(hw, &hw->hmc.hmc_obj_virt_mem);
687 hw->hmc.hmc_obj = NULL;
688
689 return ret_code;
690}
691
692#define I40E_HMC_STORE(_struct, _ele) \
693 offsetof(struct _struct, _ele), \
694 FIELD_SIZEOF(struct _struct, _ele)
695
696struct i40e_context_ele {
697 u16 offset;
698 u16 size_of;
699 u16 width;
700 u16 lsb;
701};
702
703/* LAN Tx Queue Context */
704static struct i40e_context_ele i40e_hmc_txq_ce_info[] = {
705 /* Field Width LSB */
706 {I40E_HMC_STORE(i40e_hmc_obj_txq, head), 13, 0 },
707 {I40E_HMC_STORE(i40e_hmc_obj_txq, new_context), 1, 30 },
708 {I40E_HMC_STORE(i40e_hmc_obj_txq, base), 57, 32 },
709 {I40E_HMC_STORE(i40e_hmc_obj_txq, fc_ena), 1, 89 },
710 {I40E_HMC_STORE(i40e_hmc_obj_txq, timesync_ena), 1, 90 },
711 {I40E_HMC_STORE(i40e_hmc_obj_txq, fd_ena), 1, 91 },
712 {I40E_HMC_STORE(i40e_hmc_obj_txq, alt_vlan_ena), 1, 92 },
713 {I40E_HMC_STORE(i40e_hmc_obj_txq, cpuid), 8, 96 },
714/* line 1 */
715 {I40E_HMC_STORE(i40e_hmc_obj_txq, thead_wb), 13, 0 + 128 },
716 {I40E_HMC_STORE(i40e_hmc_obj_txq, head_wb_ena), 1, 32 + 128 },
717 {I40E_HMC_STORE(i40e_hmc_obj_txq, qlen), 13, 33 + 128 },
718 {I40E_HMC_STORE(i40e_hmc_obj_txq, tphrdesc_ena), 1, 46 + 128 },
719 {I40E_HMC_STORE(i40e_hmc_obj_txq, tphrpacket_ena), 1, 47 + 128 },
720 {I40E_HMC_STORE(i40e_hmc_obj_txq, tphwdesc_ena), 1, 48 + 128 },
721 {I40E_HMC_STORE(i40e_hmc_obj_txq, head_wb_addr), 64, 64 + 128 },
722/* line 7 */
723 {I40E_HMC_STORE(i40e_hmc_obj_txq, crc), 32, 0 + (7 * 128) },
724 {I40E_HMC_STORE(i40e_hmc_obj_txq, rdylist), 10, 84 + (7 * 128) },
725 {I40E_HMC_STORE(i40e_hmc_obj_txq, rdylist_act), 1, 94 + (7 * 128) },
726 { 0 }
727};
728
729/* LAN Rx Queue Context */
730static struct i40e_context_ele i40e_hmc_rxq_ce_info[] = {
731 /* Field Width LSB */
732 { I40E_HMC_STORE(i40e_hmc_obj_rxq, head), 13, 0 },
733 { I40E_HMC_STORE(i40e_hmc_obj_rxq, cpuid), 8, 13 },
734 { I40E_HMC_STORE(i40e_hmc_obj_rxq, base), 57, 32 },
735 { I40E_HMC_STORE(i40e_hmc_obj_rxq, qlen), 13, 89 },
736 { I40E_HMC_STORE(i40e_hmc_obj_rxq, dbuff), 7, 102 },
737 { I40E_HMC_STORE(i40e_hmc_obj_rxq, hbuff), 5, 109 },
738 { I40E_HMC_STORE(i40e_hmc_obj_rxq, dtype), 2, 114 },
739 { I40E_HMC_STORE(i40e_hmc_obj_rxq, dsize), 1, 116 },
740 { I40E_HMC_STORE(i40e_hmc_obj_rxq, crcstrip), 1, 117 },
741 { I40E_HMC_STORE(i40e_hmc_obj_rxq, fc_ena), 1, 118 },
742 { I40E_HMC_STORE(i40e_hmc_obj_rxq, l2tsel), 1, 119 },
743 { I40E_HMC_STORE(i40e_hmc_obj_rxq, hsplit_0), 4, 120 },
744 { I40E_HMC_STORE(i40e_hmc_obj_rxq, hsplit_1), 2, 124 },
745 { I40E_HMC_STORE(i40e_hmc_obj_rxq, showiv), 1, 127 },
746 { I40E_HMC_STORE(i40e_hmc_obj_rxq, rxmax), 14, 174 },
747 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphrdesc_ena), 1, 193 },
748 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphwdesc_ena), 1, 194 },
749 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphdata_ena), 1, 195 },
750 { I40E_HMC_STORE(i40e_hmc_obj_rxq, tphhead_ena), 1, 196 },
751 { I40E_HMC_STORE(i40e_hmc_obj_rxq, lrxqthresh), 3, 198 },
752 { 0 }
753};
754
755/**
756 * i40e_clear_hmc_context - zero out the HMC context bits
757 * @hw: the hardware struct
758 * @context_bytes: pointer to the context bit array (DMA memory)
759 * @hmc_type: the type of HMC resource
760 **/
761static i40e_status i40e_clear_hmc_context(struct i40e_hw *hw,
762 u8 *context_bytes,
763 enum i40e_hmc_lan_rsrc_type hmc_type)
764{
765 /* clean the bit array */
766 memset(context_bytes, 0, (u32)hw->hmc.hmc_obj[hmc_type].size);
767
768 return 0;
769}
770
771/**
772 * i40e_set_hmc_context - replace HMC context bits
773 * @context_bytes: pointer to the context bit array
774 * @ce_info: a description of the struct to be filled
775 * @dest: the struct to be filled
776 **/
777static i40e_status i40e_set_hmc_context(u8 *context_bytes,
778 struct i40e_context_ele *ce_info,
779 u8 *dest)
780{
781 u16 shift_width;
782 u64 bitfield;
783 u8 hi_byte;
784 u8 hi_mask;
785 u64 t_bits;
786 u64 mask;
787 u8 *p;
788 int f;
789
790 for (f = 0; ce_info[f].width != 0; f++) {
791 /* clear out the field */
792 bitfield = 0;
793
794 /* copy from the next struct field */
795 p = dest + ce_info[f].offset;
796 switch (ce_info[f].size_of) {
797 case 1:
798 bitfield = *p;
799 break;
800 case 2:
801 bitfield = cpu_to_le16(*(u16 *)p);
802 break;
803 case 4:
804 bitfield = cpu_to_le32(*(u32 *)p);
805 break;
806 case 8:
807 bitfield = cpu_to_le64(*(u64 *)p);
808 break;
809 }
810
811 /* prepare the bits and mask */
812 shift_width = ce_info[f].lsb % 8;
813 mask = ((u64)1 << ce_info[f].width) - 1;
814
815 /* save upper bytes for special case */
816 hi_mask = (u8)((mask >> 56) & 0xff);
817 hi_byte = (u8)((bitfield >> 56) & 0xff);
818
819 /* shift to correct alignment */
820 mask <<= shift_width;
821 bitfield <<= shift_width;
822
823 /* get the current bits from the target bit string */
824 p = context_bytes + (ce_info[f].lsb / 8);
825 memcpy(&t_bits, p, sizeof(u64));
826
827 t_bits &= ~mask; /* get the bits not changing */
828 t_bits |= bitfield; /* add in the new bits */
829
830 /* put it all back */
831 memcpy(p, &t_bits, sizeof(u64));
832
833 /* deal with the special case if needed
834 * example: 62 bit field that starts in bit 5 of first byte
835 * will overlap 3 bits into byte 9
836 */
837 if ((shift_width + ce_info[f].width) > 64) {
838 u8 byte;
839
840 hi_mask >>= (8 - shift_width);
841 hi_byte >>= (8 - shift_width);
842 byte = p[8] & ~hi_mask; /* get the bits not changing */
843 byte |= hi_byte; /* add in the new bits */
844 p[8] = byte; /* put it back */
845 }
846 }
847
848 return 0;
849}
850
851/**
852 * i40e_hmc_get_object_va - retrieves an object's virtual address
853 * @hmc_info: pointer to i40e_hmc_info struct
854 * @object_base: pointer to u64 to get the va
855 * @rsrc_type: the hmc resource type
856 * @obj_idx: hmc object index
857 *
858 * This function retrieves the object's virtual address from the object
859 * base pointer. This function is used for LAN Queue contexts.
860 **/
861static
862i40e_status i40e_hmc_get_object_va(struct i40e_hmc_info *hmc_info,
863 u8 **object_base,
864 enum i40e_hmc_lan_rsrc_type rsrc_type,
865 u32 obj_idx)
866{
867 u32 obj_offset_in_sd, obj_offset_in_pd;
868 i40e_status ret_code = 0;
869 struct i40e_hmc_sd_entry *sd_entry;
870 struct i40e_hmc_pd_entry *pd_entry;
871 u32 pd_idx, pd_lmt, rel_pd_idx;
872 u64 obj_offset_in_fpm;
873 u32 sd_idx, sd_lmt;
874
875 if (NULL == hmc_info) {
876 ret_code = I40E_ERR_BAD_PTR;
877 hw_dbg(hw, "i40e_hmc_get_object_va: bad hmc_info ptr\n");
878 goto exit;
879 }
880 if (NULL == hmc_info->hmc_obj) {
881 ret_code = I40E_ERR_BAD_PTR;
882 hw_dbg(hw, "i40e_hmc_get_object_va: bad hmc_info->hmc_obj ptr\n");
883 goto exit;
884 }
885 if (NULL == object_base) {
886 ret_code = I40E_ERR_BAD_PTR;
887 hw_dbg(hw, "i40e_hmc_get_object_va: bad object_base ptr\n");
888 goto exit;
889 }
890 if (I40E_HMC_INFO_SIGNATURE != hmc_info->signature) {
891 ret_code = I40E_ERR_BAD_PTR;
892 hw_dbg(hw, "i40e_hmc_get_object_va: bad hmc_info->signature\n");
893 goto exit;
894 }
895 if (obj_idx >= hmc_info->hmc_obj[rsrc_type].cnt) {
896 hw_dbg(hw, "i40e_hmc_get_object_va: returns error %d\n",
897 ret_code);
898 ret_code = I40E_ERR_INVALID_HMC_OBJ_INDEX;
899 goto exit;
900 }
901 /* find sd index and limit */
902 I40E_FIND_SD_INDEX_LIMIT(hmc_info, rsrc_type, obj_idx, 1,
903 &sd_idx, &sd_lmt);
904
905 sd_entry = &hmc_info->sd_table.sd_entry[sd_idx];
906 obj_offset_in_fpm = hmc_info->hmc_obj[rsrc_type].base +
907 hmc_info->hmc_obj[rsrc_type].size * obj_idx;
908
909 if (I40E_SD_TYPE_PAGED == sd_entry->entry_type) {
910 I40E_FIND_PD_INDEX_LIMIT(hmc_info, rsrc_type, obj_idx, 1,
911 &pd_idx, &pd_lmt);
912 rel_pd_idx = pd_idx % I40E_HMC_PD_CNT_IN_SD;
913 pd_entry = &sd_entry->u.pd_table.pd_entry[rel_pd_idx];
914 obj_offset_in_pd = (u32)(obj_offset_in_fpm %
915 I40E_HMC_PAGED_BP_SIZE);
916 *object_base = (u8 *)pd_entry->bp.addr.va + obj_offset_in_pd;
917 } else {
918 obj_offset_in_sd = (u32)(obj_offset_in_fpm %
919 I40E_HMC_DIRECT_BP_SIZE);
920 *object_base = (u8 *)sd_entry->u.bp.addr.va + obj_offset_in_sd;
921 }
922exit:
923 return ret_code;
924}
925
926/**
927 * i40e_clear_lan_tx_queue_context - clear the HMC context for the queue
928 * @hw: the hardware struct
929 * @queue: the queue we care about
930 **/
931i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
932 u16 queue)
933{
934 i40e_status err;
935 u8 *context_bytes;
936
937 err = i40e_hmc_get_object_va(&hw->hmc, &context_bytes,
938 I40E_HMC_LAN_TX, queue);
939 if (err < 0)
940 return err;
941
942 return i40e_clear_hmc_context(hw, context_bytes, I40E_HMC_LAN_TX);
943}
944
945/**
946 * i40e_set_lan_tx_queue_context - set the HMC context for the queue
947 * @hw: the hardware struct
948 * @queue: the queue we care about
949 * @s: the struct to be filled
950 **/
951i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
952 u16 queue,
953 struct i40e_hmc_obj_txq *s)
954{
955 i40e_status err;
956 u8 *context_bytes;
957
958 err = i40e_hmc_get_object_va(&hw->hmc, &context_bytes,
959 I40E_HMC_LAN_TX, queue);
960 if (err < 0)
961 return err;
962
963 return i40e_set_hmc_context(context_bytes,
964 i40e_hmc_txq_ce_info, (u8 *)s);
965}
966
967/**
968 * i40e_clear_lan_rx_queue_context - clear the HMC context for the queue
969 * @hw: the hardware struct
970 * @queue: the queue we care about
971 **/
972i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
973 u16 queue)
974{
975 i40e_status err;
976 u8 *context_bytes;
977
978 err = i40e_hmc_get_object_va(&hw->hmc, &context_bytes,
979 I40E_HMC_LAN_RX, queue);
980 if (err < 0)
981 return err;
982
983 return i40e_clear_hmc_context(hw, context_bytes, I40E_HMC_LAN_RX);
984}
985
986/**
987 * i40e_set_lan_rx_queue_context - set the HMC context for the queue
988 * @hw: the hardware struct
989 * @queue: the queue we care about
990 * @s: the struct to be filled
991 **/
992i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
993 u16 queue,
994 struct i40e_hmc_obj_rxq *s)
995{
996 i40e_status err;
997 u8 *context_bytes;
998
999 err = i40e_hmc_get_object_va(&hw->hmc, &context_bytes,
1000 I40E_HMC_LAN_RX, queue);
1001 if (err < 0)
1002 return err;
1003
1004 return i40e_set_hmc_context(context_bytes,
1005 i40e_hmc_rxq_ce_info, (u8 *)s);
1006}
diff --git a/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.h b/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.h
new file mode 100644
index 000000000000..00ff35006077
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_lan_hmc.h
@@ -0,0 +1,169 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_LAN_HMC_H_
29#define _I40E_LAN_HMC_H_
30
31/* forward-declare the HW struct for the compiler */
32struct i40e_hw;
33
34/* HMC element context information */
35
36/* Rx queue context data */
37struct i40e_hmc_obj_rxq {
38 u16 head;
39 u8 cpuid;
40 u64 base;
41 u16 qlen;
42#define I40E_RXQ_CTX_DBUFF_SHIFT 7
43 u8 dbuff;
44#define I40E_RXQ_CTX_HBUFF_SHIFT 6
45 u8 hbuff;
46 u8 dtype;
47 u8 dsize;
48 u8 crcstrip;
49 u8 fc_ena;
50 u8 l2tsel;
51 u8 hsplit_0;
52 u8 hsplit_1;
53 u8 showiv;
54 u16 rxmax;
55 u8 tphrdesc_ena;
56 u8 tphwdesc_ena;
57 u8 tphdata_ena;
58 u8 tphhead_ena;
59 u8 lrxqthresh;
60};
61
62/* Tx queue context data */
63struct i40e_hmc_obj_txq {
64 u16 head;
65 u8 new_context;
66 u64 base;
67 u8 fc_ena;
68 u8 timesync_ena;
69 u8 fd_ena;
70 u8 alt_vlan_ena;
71 u16 thead_wb;
72 u16 cpuid;
73 u8 head_wb_ena;
74 u16 qlen;
75 u8 tphrdesc_ena;
76 u8 tphrpacket_ena;
77 u8 tphwdesc_ena;
78 u64 head_wb_addr;
79 u32 crc;
80 u16 rdylist;
81 u8 rdylist_act;
82};
83
84/* for hsplit_0 field of Rx HMC context */
85enum i40e_hmc_obj_rx_hsplit_0 {
86 I40E_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0,
87 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1,
88 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2,
89 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
90 I40E_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8,
91};
92
93/* fcoe_cntx and fcoe_filt are for debugging purpose only */
94struct i40e_hmc_obj_fcoe_cntx {
95 u32 rsv[32];
96};
97
98struct i40e_hmc_obj_fcoe_filt {
99 u32 rsv[8];
100};
101
102/* Context sizes for LAN objects */
103enum i40e_hmc_lan_object_size {
104 I40E_HMC_LAN_OBJ_SZ_8 = 0x3,
105 I40E_HMC_LAN_OBJ_SZ_16 = 0x4,
106 I40E_HMC_LAN_OBJ_SZ_32 = 0x5,
107 I40E_HMC_LAN_OBJ_SZ_64 = 0x6,
108 I40E_HMC_LAN_OBJ_SZ_128 = 0x7,
109 I40E_HMC_LAN_OBJ_SZ_256 = 0x8,
110 I40E_HMC_LAN_OBJ_SZ_512 = 0x9,
111};
112
113#define I40E_HMC_L2OBJ_BASE_ALIGNMENT 512
114#define I40E_HMC_OBJ_SIZE_TXQ 128
115#define I40E_HMC_OBJ_SIZE_RXQ 32
116#define I40E_HMC_OBJ_SIZE_FCOE_CNTX 128
117#define I40E_HMC_OBJ_SIZE_FCOE_FILT 32
118
119enum i40e_hmc_lan_rsrc_type {
120 I40E_HMC_LAN_FULL = 0,
121 I40E_HMC_LAN_TX = 1,
122 I40E_HMC_LAN_RX = 2,
123 I40E_HMC_FCOE_CTX = 3,
124 I40E_HMC_FCOE_FILT = 4,
125 I40E_HMC_LAN_MAX = 5
126};
127
128enum i40e_hmc_model {
129 I40E_HMC_MODEL_DIRECT_PREFERRED = 0,
130 I40E_HMC_MODEL_DIRECT_ONLY = 1,
131 I40E_HMC_MODEL_PAGED_ONLY = 2,
132 I40E_HMC_MODEL_UNKNOWN,
133};
134
135struct i40e_hmc_lan_create_obj_info {
136 struct i40e_hmc_info *hmc_info;
137 u32 rsrc_type;
138 u32 start_idx;
139 u32 count;
140 enum i40e_sd_entry_type entry_type;
141 u64 direct_mode_sz;
142};
143
144struct i40e_hmc_lan_delete_obj_info {
145 struct i40e_hmc_info *hmc_info;
146 u32 rsrc_type;
147 u32 start_idx;
148 u32 count;
149};
150
151i40e_status i40e_init_lan_hmc(struct i40e_hw *hw, u32 txq_num,
152 u32 rxq_num, u32 fcoe_cntx_num,
153 u32 fcoe_filt_num);
154i40e_status i40e_configure_lan_hmc(struct i40e_hw *hw,
155 enum i40e_hmc_model model);
156i40e_status i40e_shutdown_lan_hmc(struct i40e_hw *hw);
157
158i40e_status i40e_clear_lan_tx_queue_context(struct i40e_hw *hw,
159 u16 queue);
160i40e_status i40e_set_lan_tx_queue_context(struct i40e_hw *hw,
161 u16 queue,
162 struct i40e_hmc_obj_txq *s);
163i40e_status i40e_clear_lan_rx_queue_context(struct i40e_hw *hw,
164 u16 queue);
165i40e_status i40e_set_lan_rx_queue_context(struct i40e_hw *hw,
166 u16 queue,
167 struct i40e_hmc_obj_rxq *s);
168
169#endif /* _I40E_LAN_HMC_H_ */
diff --git a/drivers/net/ethernet/intel/i40e/i40e_nvm.c b/drivers/net/ethernet/intel/i40e/i40e_nvm.c
new file mode 100644
index 000000000000..97e1bb30ef8a
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_nvm.c
@@ -0,0 +1,391 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#include "i40e_prototype.h"
29
30/**
31 * i40e_init_nvm_ops - Initialize NVM function pointers.
32 * @hw: pointer to the HW structure.
33 *
34 * Setups the function pointers and the NVM info structure. Should be called
35 * once per NVM initialization, e.g. inside the i40e_init_shared_code().
36 * Please notice that the NVM term is used here (& in all methods covered
37 * in this file) as an equivalent of the FLASH part mapped into the SR.
38 * We are accessing FLASH always thru the Shadow RAM.
39 **/
40i40e_status i40e_init_nvm(struct i40e_hw *hw)
41{
42 struct i40e_nvm_info *nvm = &hw->nvm;
43 i40e_status ret_code = 0;
44 u32 fla, gens;
45 u8 sr_size;
46
47 /* The SR size is stored regardless of the nvm programming mode
48 * as the blank mode may be used in the factory line.
49 */
50 gens = rd32(hw, I40E_GLNVM_GENS);
51 sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
52 I40E_GLNVM_GENS_SR_SIZE_SHIFT);
53 /* Switching to words (sr_size contains power of 2KB). */
54 nvm->sr_size = (1 << sr_size) * I40E_SR_WORDS_IN_1KB;
55
56 /* Check if we are in the normal or blank NVM programming mode. */
57 fla = rd32(hw, I40E_GLNVM_FLA);
58 if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode. */
59 /* Max NVM timeout. */
60 nvm->timeout = I40E_MAX_NVM_TIMEOUT;
61 nvm->blank_nvm_mode = false;
62 } else { /* Blank programming mode. */
63 nvm->blank_nvm_mode = true;
64 ret_code = I40E_ERR_NVM_BLANK_MODE;
65 hw_dbg(hw, "NVM init error: unsupported blank mode.\n");
66 }
67
68 return ret_code;
69}
70
71/**
72 * i40e_acquire_nvm - Generic request for acquiring the NVM ownership.
73 * @hw: pointer to the HW structure.
74 * @access: NVM access type (read or write).
75 *
76 * This function will request NVM ownership for reading
77 * via the proper Admin Command.
78 **/
79i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
80 enum i40e_aq_resource_access_type access)
81{
82 i40e_status ret_code = 0;
83 u64 gtime, timeout;
84 u64 time = 0;
85
86 if (hw->nvm.blank_nvm_mode)
87 goto i40e_i40e_acquire_nvm_exit;
88
89 ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
90 0, &time, NULL);
91 /* Reading the Global Device Timer. */
92 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
93
94 /* Store the timeout. */
95 hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time) + gtime;
96
97 if (ret_code) {
98 /* Set the polling timeout. */
99 if (time > I40E_MAX_NVM_TIMEOUT)
100 timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT)
101 + gtime;
102 else
103 timeout = hw->nvm.hw_semaphore_timeout;
104 /* Poll until the current NVM owner timeouts. */
105 while (gtime < timeout) {
106 usleep_range(10000, 20000);
107 ret_code = i40e_aq_request_resource(hw,
108 I40E_NVM_RESOURCE_ID,
109 access, 0, &time,
110 NULL);
111 if (!ret_code) {
112 hw->nvm.hw_semaphore_timeout =
113 I40E_MS_TO_GTIME(time) + gtime;
114 break;
115 }
116 gtime = rd32(hw, I40E_GLVFGEN_TIMER);
117 }
118 if (ret_code) {
119 hw->nvm.hw_semaphore_timeout = 0;
120 hw->nvm.hw_semaphore_wait =
121 I40E_MS_TO_GTIME(time) + gtime;
122 hw_dbg(hw, "NVM acquire timed out, wait %llu ms before trying again.\n",
123 time);
124 }
125 }
126
127i40e_i40e_acquire_nvm_exit:
128 return ret_code;
129}
130
131/**
132 * i40e_release_nvm - Generic request for releasing the NVM ownership.
133 * @hw: pointer to the HW structure.
134 *
135 * This function will release NVM resource via the proper Admin Command.
136 **/
137void i40e_release_nvm(struct i40e_hw *hw)
138{
139 if (!hw->nvm.blank_nvm_mode)
140 i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
141}
142
143/**
144 * i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit.
145 * @hw: pointer to the HW structure.
146 *
147 * Polls the SRCTL Shadow RAM register done bit.
148 **/
149static i40e_status i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
150{
151 i40e_status ret_code = I40E_ERR_TIMEOUT;
152 u32 srctl, wait_cnt;
153
154 /* Poll the I40E_GLNVM_SRCTL until the done bit is set. */
155 for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
156 srctl = rd32(hw, I40E_GLNVM_SRCTL);
157 if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
158 ret_code = 0;
159 break;
160 }
161 udelay(5);
162 }
163 if (ret_code == I40E_ERR_TIMEOUT)
164 hw_dbg(hw, "Done bit in GLNVM_SRCTL not set");
165 return ret_code;
166}
167
168/**
169 * i40e_read_nvm_srctl - Reads Shadow RAM.
170 * @hw: pointer to the HW structure.
171 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
172 * @data: word read from the Shadow RAM.
173 *
174 * Reads 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
175 **/
176static i40e_status i40e_read_nvm_srctl(struct i40e_hw *hw, u16 offset,
177 u16 *data)
178{
179 i40e_status ret_code = I40E_ERR_TIMEOUT;
180 u32 sr_reg;
181
182 if (offset >= hw->nvm.sr_size) {
183 hw_dbg(hw, "NVM read error: Offset beyond Shadow RAM limit.\n");
184 ret_code = I40E_ERR_PARAM;
185 goto read_nvm_exit;
186 }
187
188 /* Poll the done bit first. */
189 ret_code = i40e_poll_sr_srctl_done_bit(hw);
190 if (!ret_code) {
191 /* Write the address and start reading. */
192 sr_reg = (u32)(offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
193 (1 << I40E_GLNVM_SRCTL_START_SHIFT);
194 wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
195
196 /* Poll I40E_GLNVM_SRCTL until the done bit is set. */
197 ret_code = i40e_poll_sr_srctl_done_bit(hw);
198 if (!ret_code) {
199 sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
200 *data = (u16)((sr_reg &
201 I40E_GLNVM_SRDATA_RDDATA_MASK)
202 >> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
203 }
204 }
205 if (ret_code)
206 hw_dbg(hw, "NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
207 offset);
208
209read_nvm_exit:
210 return ret_code;
211}
212
213/**
214 * i40e_read_nvm_word - Reads Shadow RAM word.
215 * @hw: pointer to the HW structure.
216 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
217 * @data: word read from the Shadow RAM.
218 *
219 * Reads 16 bit word from the Shadow RAM. Each read is preceded
220 * with the NVM ownership taking and followed by the release.
221 **/
222i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
223 u16 *data)
224{
225 i40e_status ret_code = 0;
226
227 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
228 if (!ret_code) {
229 ret_code = i40e_read_nvm_srctl(hw, offset, data);
230 i40e_release_nvm(hw);
231 }
232
233 return ret_code;
234}
235
236/**
237 * i40e_read_nvm_buffer - Reads Shadow RAM buffer.
238 * @hw: pointer to the HW structure.
239 * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
240 * @words: number of words to read (in) &
241 * number of words read before the NVM ownership timeout (out).
242 * @data: words read from the Shadow RAM.
243 *
244 * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
245 * method. The buffer read is preceded by the NVM ownership take
246 * and followed by the release.
247 **/
248i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
249 u16 *words, u16 *data)
250{
251 i40e_status ret_code = 0;
252 u16 index, word;
253 u32 time;
254
255 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
256 if (!ret_code) {
257 /* Loop thru the selected region. */
258 for (word = 0; word < *words; word++) {
259 index = offset + word;
260 ret_code = i40e_read_nvm_srctl(hw, index, &data[word]);
261 if (ret_code)
262 break;
263 /* Check if we didn't exceeded the semaphore timeout. */
264 time = rd32(hw, I40E_GLVFGEN_TIMER);
265 if (time >= hw->nvm.hw_semaphore_timeout) {
266 ret_code = I40E_ERR_TIMEOUT;
267 hw_dbg(hw, "NVM read error: timeout.\n");
268 break;
269 }
270 }
271 /* Update the number of words read from the Shadow RAM. */
272 *words = word;
273 /* Release the NVM ownership. */
274 i40e_release_nvm(hw);
275 }
276
277 return ret_code;
278}
279
280/**
281 * i40e_calc_nvm_checksum - Calculates and returns the checksum
282 * @hw: pointer to hardware structure
283 *
284 * This function calculate SW Checksum that covers the whole 64kB shadow RAM
285 * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
286 * is customer specific and unknown. Therefore, this function skips all maximum
287 * possible size of VPD (1kB).
288 **/
289static i40e_status i40e_calc_nvm_checksum(struct i40e_hw *hw,
290 u16 *checksum)
291{
292 i40e_status ret_code = 0;
293 u16 pcie_alt_module = 0;
294 u16 checksum_local = 0;
295 u16 vpd_module = 0;
296 u16 word = 0;
297 u32 i = 0;
298
299 /* read pointer to VPD area */
300 ret_code = i40e_read_nvm_srctl(hw, I40E_SR_VPD_PTR, &vpd_module);
301 if (ret_code) {
302 ret_code = I40E_ERR_NVM_CHECKSUM;
303 goto i40e_calc_nvm_checksum_exit;
304 }
305
306 /* read pointer to PCIe Alt Auto-load module */
307 ret_code = i40e_read_nvm_srctl(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
308 &pcie_alt_module);
309 if (ret_code) {
310 ret_code = I40E_ERR_NVM_CHECKSUM;
311 goto i40e_calc_nvm_checksum_exit;
312 }
313
314 /* Calculate SW checksum that covers the whole 64kB shadow RAM
315 * except the VPD and PCIe ALT Auto-load modules
316 */
317 for (i = 0; i < hw->nvm.sr_size; i++) {
318 /* Skip Checksum word */
319 if (i == I40E_SR_SW_CHECKSUM_WORD)
320 i++;
321 /* Skip VPD module (convert byte size to word count) */
322 if (i == (u32)vpd_module) {
323 i += (I40E_SR_VPD_MODULE_MAX_SIZE / 2);
324 if (i >= hw->nvm.sr_size)
325 break;
326 }
327 /* Skip PCIe ALT module (convert byte size to word count) */
328 if (i == (u32)pcie_alt_module) {
329 i += (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2);
330 if (i >= hw->nvm.sr_size)
331 break;
332 }
333
334 ret_code = i40e_read_nvm_srctl(hw, (u16)i, &word);
335 if (ret_code) {
336 ret_code = I40E_ERR_NVM_CHECKSUM;
337 goto i40e_calc_nvm_checksum_exit;
338 }
339 checksum_local += word;
340 }
341
342 *checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
343
344i40e_calc_nvm_checksum_exit:
345 return ret_code;
346}
347
348/**
349 * i40e_validate_nvm_checksum - Validate EEPROM checksum
350 * @hw: pointer to hardware structure
351 * @checksum: calculated checksum
352 *
353 * Performs checksum calculation and validates the NVM SW checksum. If the
354 * caller does not need checksum, the value can be NULL.
355 **/
356i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
357 u16 *checksum)
358{
359 i40e_status ret_code = 0;
360 u16 checksum_sr = 0;
361 u16 checksum_local;
362
363 ret_code = i40e_acquire_nvm(hw, I40E_RESOURCE_READ);
364 if (ret_code)
365 goto i40e_validate_nvm_checksum_exit;
366
367 ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
368 if (ret_code)
369 goto i40e_validate_nvm_checksum_free;
370
371 /* Do not use i40e_read_nvm_word() because we do not want to take
372 * the synchronization semaphores twice here.
373 */
374 i40e_read_nvm_srctl(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
375
376 /* Verify read checksum from EEPROM is the same as
377 * calculated checksum
378 */
379 if (checksum_local != checksum_sr)
380 ret_code = I40E_ERR_NVM_CHECKSUM;
381
382 /* If the user cares, return the calculated checksum */
383 if (checksum)
384 *checksum = checksum_local;
385
386i40e_validate_nvm_checksum_free:
387 i40e_release_nvm(hw);
388
389i40e_validate_nvm_checksum_exit:
390 return ret_code;
391}
diff --git a/drivers/net/ethernet/intel/i40e/i40e_prototype.h b/drivers/net/ethernet/intel/i40e/i40e_prototype.h
new file mode 100644
index 000000000000..f75bb9ccc900
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_prototype.h
@@ -0,0 +1,239 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_PROTOTYPE_H_
29#define _I40E_PROTOTYPE_H_
30
31#include "i40e_type.h"
32#include "i40e_alloc.h"
33#include "i40e_virtchnl.h"
34
35/* Prototypes for shared code functions that are not in
36 * the standard function pointer structures. These are
37 * mostly because they are needed even before the init
38 * has happened and will assist in the early SW and FW
39 * setup.
40 */
41
42/* adminq functions */
43i40e_status i40e_init_adminq(struct i40e_hw *hw);
44i40e_status i40e_shutdown_adminq(struct i40e_hw *hw);
45void i40e_adminq_init_ring_data(struct i40e_hw *hw);
46i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
47 struct i40e_arq_event_info *e,
48 u16 *events_pending);
49i40e_status i40e_asq_send_command(struct i40e_hw *hw,
50 struct i40e_aq_desc *desc,
51 void *buff, /* can be NULL */
52 u16 buff_size,
53 struct i40e_asq_cmd_details *cmd_details);
54bool i40e_asq_done(struct i40e_hw *hw);
55
56/* debug function for adminq */
57void i40e_debug_aq(struct i40e_hw *hw,
58 enum i40e_debug_mask mask,
59 void *desc,
60 void *buffer);
61
62void i40e_idle_aq(struct i40e_hw *hw);
63void i40e_resume_aq(struct i40e_hw *hw);
64
65u32 i40e_led_get(struct i40e_hw *hw);
66void i40e_led_set(struct i40e_hw *hw, u32 mode);
67
68/* admin send queue commands */
69
70i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
71 u16 *fw_major_version, u16 *fw_minor_version,
72 u16 *api_major_version, u16 *api_minor_version,
73 struct i40e_asq_cmd_details *cmd_details);
74i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
75 bool unloading);
76i40e_status i40e_aq_set_phy_reset(struct i40e_hw *hw,
77 struct i40e_asq_cmd_details *cmd_details);
78i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,
79 struct i40e_asq_cmd_details *cmd_details);
80i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
81 struct i40e_asq_cmd_details *cmd_details);
82i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
83 bool enable_lse, struct i40e_link_status *link,
84 struct i40e_asq_cmd_details *cmd_details);
85i40e_status i40e_aq_set_local_advt_reg(struct i40e_hw *hw,
86 u64 advt_reg,
87 struct i40e_asq_cmd_details *cmd_details);
88i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
89 struct i40e_driver_version *dv,
90 struct i40e_asq_cmd_details *cmd_details);
91i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
92 struct i40e_vsi_context *vsi_ctx,
93 struct i40e_asq_cmd_details *cmd_details);
94i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
95 u16 vsi_id, bool set_filter,
96 struct i40e_asq_cmd_details *cmd_details);
97i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
98 u16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details);
99i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
100 u16 vsi_id, bool set, struct i40e_asq_cmd_details *cmd_details);
101i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
102 struct i40e_vsi_context *vsi_ctx,
103 struct i40e_asq_cmd_details *cmd_details);
104i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
105 struct i40e_vsi_context *vsi_ctx,
106 struct i40e_asq_cmd_details *cmd_details);
107i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
108 u16 downlink_seid, u8 enabled_tc,
109 bool default_port, u16 *pveb_seid,
110 struct i40e_asq_cmd_details *cmd_details);
111i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
112 u16 veb_seid, u16 *switch_id, bool *floating,
113 u16 *statistic_index, u16 *vebs_used,
114 u16 *vebs_free,
115 struct i40e_asq_cmd_details *cmd_details);
116i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 vsi_id,
117 struct i40e_aqc_add_macvlan_element_data *mv_list,
118 u16 count, struct i40e_asq_cmd_details *cmd_details);
119i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 vsi_id,
120 struct i40e_aqc_remove_macvlan_element_data *mv_list,
121 u16 count, struct i40e_asq_cmd_details *cmd_details);
122i40e_status i40e_aq_add_vlan(struct i40e_hw *hw, u16 vsi_id,
123 struct i40e_aqc_add_remove_vlan_element_data *v_list,
124 u8 count, struct i40e_asq_cmd_details *cmd_details);
125i40e_status i40e_aq_remove_vlan(struct i40e_hw *hw, u16 vsi_id,
126 struct i40e_aqc_add_remove_vlan_element_data *v_list,
127 u8 count, struct i40e_asq_cmd_details *cmd_details);
128i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
129 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
130 struct i40e_asq_cmd_details *cmd_details);
131i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
132 struct i40e_aqc_get_switch_config_resp *buf,
133 u16 buf_size, u16 *start_seid,
134 struct i40e_asq_cmd_details *cmd_details);
135i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
136 enum i40e_aq_resources_ids resource,
137 enum i40e_aq_resource_access_type access,
138 u8 sdp_number, u64 *timeout,
139 struct i40e_asq_cmd_details *cmd_details);
140i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
141 enum i40e_aq_resources_ids resource,
142 u8 sdp_number,
143 struct i40e_asq_cmd_details *cmd_details);
144i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
145 u32 offset, u16 length, void *data,
146 bool last_command,
147 struct i40e_asq_cmd_details *cmd_details);
148i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
149 void *buff, u16 buff_size, u16 *data_size,
150 enum i40e_admin_queue_opc list_type_opc,
151 struct i40e_asq_cmd_details *cmd_details);
152i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
153 u32 offset, u16 length, void *data,
154 bool last_command,
155 struct i40e_asq_cmd_details *cmd_details);
156i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
157 u8 mib_type, void *buff, u16 buff_size,
158 u16 *local_len, u16 *remote_len,
159 struct i40e_asq_cmd_details *cmd_details);
160i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
161 bool enable_update,
162 struct i40e_asq_cmd_details *cmd_details);
163i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
164 struct i40e_asq_cmd_details *cmd_details);
165i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
166 struct i40e_asq_cmd_details *cmd_details);
167i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
168 struct i40e_asq_cmd_details *cmd_details);
169i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
170 u16 flags, u8 *mac_addr,
171 struct i40e_asq_cmd_details *cmd_details);
172i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
173 enum i40e_aq_hmc_profile profile,
174 u8 pe_vf_enabled_count,
175 struct i40e_asq_cmd_details *cmd_details);
176i40e_status i40e_aq_config_switch_comp_bw_limit(struct i40e_hw *hw,
177 u16 seid, u16 credit, u8 max_bw,
178 struct i40e_asq_cmd_details *cmd_details);
179i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw, u16 seid,
180 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
181 struct i40e_asq_cmd_details *cmd_details);
182i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
183 u16 seid,
184 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
185 struct i40e_asq_cmd_details *cmd_details);
186i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
187 u16 seid,
188 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
189 struct i40e_asq_cmd_details *cmd_details);
190i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
191 u16 seid,
192 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
193 struct i40e_asq_cmd_details *cmd_details);
194i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
195 u16 seid,
196 struct i40e_aqc_query_port_ets_config_resp *bw_data,
197 struct i40e_asq_cmd_details *cmd_details);
198i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
199 u16 seid,
200 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
201 struct i40e_asq_cmd_details *cmd_details);
202/* i40e_common */
203i40e_status i40e_init_shared_code(struct i40e_hw *hw);
204i40e_status i40e_pf_reset(struct i40e_hw *hw);
205void i40e_clear_pxe_mode(struct i40e_hw *hw);
206bool i40e_get_link_status(struct i40e_hw *hw);
207i40e_status i40e_get_mac_addr(struct i40e_hw *hw,
208 u8 *mac_addr);
209i40e_status i40e_validate_mac_addr(u8 *mac_addr);
210i40e_status i40e_read_lldp_cfg(struct i40e_hw *hw,
211 struct i40e_lldp_variables *lldp_cfg);
212/* prototype for functions used for NVM access */
213i40e_status i40e_init_nvm(struct i40e_hw *hw);
214i40e_status i40e_acquire_nvm(struct i40e_hw *hw,
215 enum i40e_aq_resource_access_type access);
216void i40e_release_nvm(struct i40e_hw *hw);
217i40e_status i40e_read_nvm_srrd(struct i40e_hw *hw, u16 offset,
218 u16 *data);
219i40e_status i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
220 u16 *data);
221i40e_status i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
222 u16 *words, u16 *data);
223i40e_status i40e_validate_nvm_checksum(struct i40e_hw *hw,
224 u16 *checksum);
225
226/* prototype for functions used for SW locks */
227
228/* i40e_common for VF drivers*/
229void i40e_vf_parse_hw_config(struct i40e_hw *hw,
230 struct i40e_virtchnl_vf_resource *msg);
231i40e_status i40e_vf_reset(struct i40e_hw *hw);
232i40e_status i40e_aq_send_msg_to_pf(struct i40e_hw *hw,
233 enum i40e_virtchnl_ops v_opcode,
234 i40e_status v_retval,
235 u8 *msg, u16 msglen,
236 struct i40e_asq_cmd_details *cmd_details);
237i40e_status i40e_set_filter_control(struct i40e_hw *hw,
238 struct i40e_filter_control_settings *settings);
239#endif /* _I40E_PROTOTYPE_H_ */
diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h
new file mode 100644
index 000000000000..6bd333cde28b
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_register.h
@@ -0,0 +1,4688 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_REGISTER_H_
29#define _I40E_REGISTER_H_
30
31#define I40E_GLPCI_PM_MUX_NPQ 0x0009C4F4
32#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT 0
33#define I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_MASK (0x7 << I40E_GLPCI_PM_MUX_NPQ_NPQ_NUM_PORT_SEL_SHIFT)
34#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT 16
35#define I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_MASK (0x1F << I40E_GLPCI_PM_MUX_NPQ_INNER_NPQ_SEL_SHIFT)
36#define I40E_GLPCI_PM_MUX_PFB 0x0009C4F0
37#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT 0
38#define I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_MASK (0x1F << I40E_GLPCI_PM_MUX_PFB_PFB_PORT_SEL_SHIFT)
39#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT 16
40#define I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_MASK (0x7 << I40E_GLPCI_PM_MUX_PFB_INNER_PORT_SEL_SHIFT)
41#define I40E_GLPCI_SPARE_BITS_0 0x0009C4F8
42#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT 0
43#define I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_MASK (0xFFFFFFFF << I40E_GLPCI_SPARE_BITS_0_SPARE_BITS_SHIFT)
44#define I40E_GLPCI_SPARE_BITS_1 0x0009C4FC
45#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT 0
46#define I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_MASK (0xFFFFFFFF << I40E_GLPCI_SPARE_BITS_1_SPARE_BITS_SHIFT)
47#define I40E_PFPCI_PF_FLUSH_DONE 0x0009C800
48#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
49#define I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_PF_FLUSH_DONE_FLUSH_DONE_SHIFT)
50#define I40E_PFPCI_VF_FLUSH_DONE 0x0009C600
51#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT 0
52#define I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VF_FLUSH_DONE_FLUSH_DONE_SHIFT)
53#define I40E_PFPCI_VM_FLUSH_DONE 0x0009C880
54#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT 0
55#define I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_MASK (0x1 << I40E_PFPCI_VM_FLUSH_DONE_FLUSH_DONE_SHIFT)
56#define I40E_PF_ARQBAH 0x00080180
57#define I40E_PF_ARQBAH_ARQBAH_SHIFT 0
58#define I40E_PF_ARQBAH_ARQBAH_MASK (0xFFFFFFFF << I40E_PF_ARQBAH_ARQBAH_SHIFT)
59#define I40E_PF_ARQBAL 0x00080080
60#define I40E_PF_ARQBAL_ARQBAL_SHIFT 0
61#define I40E_PF_ARQBAL_ARQBAL_MASK (0xFFFFFFFF << I40E_PF_ARQBAL_ARQBAL_SHIFT)
62#define I40E_PF_ARQH 0x00080380
63#define I40E_PF_ARQH_ARQH_SHIFT 0
64#define I40E_PF_ARQH_ARQH_MASK (0x3FF << I40E_PF_ARQH_ARQH_SHIFT)
65#define I40E_PF_ARQLEN 0x00080280
66#define I40E_PF_ARQLEN_ARQLEN_SHIFT 0
67#define I40E_PF_ARQLEN_ARQLEN_MASK (0x3FF << I40E_PF_ARQLEN_ARQLEN_SHIFT)
68#define I40E_PF_ARQLEN_ARQVFE_SHIFT 28
69#define I40E_PF_ARQLEN_ARQVFE_MASK (0x1 << I40E_PF_ARQLEN_ARQVFE_SHIFT)
70#define I40E_PF_ARQLEN_ARQOVFL_SHIFT 29
71#define I40E_PF_ARQLEN_ARQOVFL_MASK (0x1 << I40E_PF_ARQLEN_ARQOVFL_SHIFT)
72#define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30
73#define I40E_PF_ARQLEN_ARQCRIT_MASK (0x1 << I40E_PF_ARQLEN_ARQCRIT_SHIFT)
74#define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31
75#define I40E_PF_ARQLEN_ARQENABLE_MASK (0x1 << I40E_PF_ARQLEN_ARQENABLE_SHIFT)
76#define I40E_PF_ARQT 0x00080480
77#define I40E_PF_ARQT_ARQT_SHIFT 0
78#define I40E_PF_ARQT_ARQT_MASK (0x3FF << I40E_PF_ARQT_ARQT_SHIFT)
79#define I40E_PF_ATQBAH 0x00080100
80#define I40E_PF_ATQBAH_ATQBAH_SHIFT 0
81#define I40E_PF_ATQBAH_ATQBAH_MASK (0xFFFFFFFF << I40E_PF_ATQBAH_ATQBAH_SHIFT)
82#define I40E_PF_ATQBAL 0x00080000
83#define I40E_PF_ATQBAL_ATQBAL_SHIFT 0
84#define I40E_PF_ATQBAL_ATQBAL_MASK (0xFFFFFFFF << I40E_PF_ATQBAL_ATQBAL_SHIFT)
85#define I40E_PF_ATQH 0x00080300
86#define I40E_PF_ATQH_ATQH_SHIFT 0
87#define I40E_PF_ATQH_ATQH_MASK (0x3FF << I40E_PF_ATQH_ATQH_SHIFT)
88#define I40E_PF_ATQLEN 0x00080200
89#define I40E_PF_ATQLEN_ATQLEN_SHIFT 0
90#define I40E_PF_ATQLEN_ATQLEN_MASK (0x3FF << I40E_PF_ATQLEN_ATQLEN_SHIFT)
91#define I40E_PF_ATQLEN_ATQVFE_SHIFT 28
92#define I40E_PF_ATQLEN_ATQVFE_MASK (0x1 << I40E_PF_ATQLEN_ATQVFE_SHIFT)
93#define I40E_PF_ATQLEN_ATQOVFL_SHIFT 29
94#define I40E_PF_ATQLEN_ATQOVFL_MASK (0x1 << I40E_PF_ATQLEN_ATQOVFL_SHIFT)
95#define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30
96#define I40E_PF_ATQLEN_ATQCRIT_MASK (0x1 << I40E_PF_ATQLEN_ATQCRIT_SHIFT)
97#define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31
98#define I40E_PF_ATQLEN_ATQENABLE_MASK (0x1 << I40E_PF_ATQLEN_ATQENABLE_SHIFT)
99#define I40E_PF_ATQT 0x00080400
100#define I40E_PF_ATQT_ATQT_SHIFT 0
101#define I40E_PF_ATQT_ATQT_MASK (0x3FF << I40E_PF_ATQT_ATQT_SHIFT)
102#define I40E_VF_ARQBAH(_VF) (0x00081400 + ((_VF) * 4)) /* _i=0...127 */
103#define I40E_VF_ARQBAH_MAX_INDEX 127
104#define I40E_VF_ARQBAH_ARQBAH_SHIFT 0
105#define I40E_VF_ARQBAH_ARQBAH_MASK (0xFFFFFFFF << I40E_VF_ARQBAH_ARQBAH_SHIFT)
106#define I40E_VF_ARQBAL(_VF) (0x00080C00 + ((_VF) * 4)) /* _i=0...127 */
107#define I40E_VF_ARQBAL_MAX_INDEX 127
108#define I40E_VF_ARQBAL_ARQBAL_SHIFT 0
109#define I40E_VF_ARQBAL_ARQBAL_MASK (0xFFFFFFFF << I40E_VF_ARQBAL_ARQBAL_SHIFT)
110#define I40E_VF_ARQH(_VF) (0x00082400 + ((_VF) * 4)) /* _i=0...127 */
111#define I40E_VF_ARQH_MAX_INDEX 127
112#define I40E_VF_ARQH_ARQH_SHIFT 0
113#define I40E_VF_ARQH_ARQH_MASK (0x3FF << I40E_VF_ARQH_ARQH_SHIFT)
114#define I40E_VF_ARQLEN(_VF) (0x00081C00 + ((_VF) * 4)) /* _i=0...127 */
115#define I40E_VF_ARQLEN_MAX_INDEX 127
116#define I40E_VF_ARQLEN_ARQLEN_SHIFT 0
117#define I40E_VF_ARQLEN_ARQLEN_MASK (0x3FF << I40E_VF_ARQLEN_ARQLEN_SHIFT)
118#define I40E_VF_ARQLEN_ARQVFE_SHIFT 28
119#define I40E_VF_ARQLEN_ARQVFE_MASK (0x1 << I40E_VF_ARQLEN_ARQVFE_SHIFT)
120#define I40E_VF_ARQLEN_ARQOVFL_SHIFT 29
121#define I40E_VF_ARQLEN_ARQOVFL_MASK (0x1 << I40E_VF_ARQLEN_ARQOVFL_SHIFT)
122#define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30
123#define I40E_VF_ARQLEN_ARQCRIT_MASK (0x1 << I40E_VF_ARQLEN_ARQCRIT_SHIFT)
124#define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31
125#define I40E_VF_ARQLEN_ARQENABLE_MASK (0x1 << I40E_VF_ARQLEN_ARQENABLE_SHIFT)
126#define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */
127#define I40E_VF_ARQT_MAX_INDEX 127
128#define I40E_VF_ARQT_ARQT_SHIFT 0
129#define I40E_VF_ARQT_ARQT_MASK (0x3FF << I40E_VF_ARQT_ARQT_SHIFT)
130#define I40E_VF_ATQBAH(_VF) (0x00081000 + ((_VF) * 4)) /* _i=0...127 */
131#define I40E_VF_ATQBAH_MAX_INDEX 127
132#define I40E_VF_ATQBAH_ATQBAH_SHIFT 0
133#define I40E_VF_ATQBAH_ATQBAH_MASK (0xFFFFFFFF << I40E_VF_ATQBAH_ATQBAH_SHIFT)
134#define I40E_VF_ATQBAL(_VF) (0x00080800 + ((_VF) * 4)) /* _i=0...127 */
135#define I40E_VF_ATQBAL_MAX_INDEX 127
136#define I40E_VF_ATQBAL_ATQBAL_SHIFT 0
137#define I40E_VF_ATQBAL_ATQBAL_MASK (0xFFFFFFFF << I40E_VF_ATQBAL_ATQBAL_SHIFT)
138#define I40E_VF_ATQH(_VF) (0x00082000 + ((_VF) * 4)) /* _i=0...127 */
139#define I40E_VF_ATQH_MAX_INDEX 127
140#define I40E_VF_ATQH_ATQH_SHIFT 0
141#define I40E_VF_ATQH_ATQH_MASK (0x3FF << I40E_VF_ATQH_ATQH_SHIFT)
142#define I40E_VF_ATQLEN(_VF) (0x00081800 + ((_VF) * 4)) /* _i=0...127 */
143#define I40E_VF_ATQLEN_MAX_INDEX 127
144#define I40E_VF_ATQLEN_ATQLEN_SHIFT 0
145#define I40E_VF_ATQLEN_ATQLEN_MASK (0x3FF << I40E_VF_ATQLEN_ATQLEN_SHIFT)
146#define I40E_VF_ATQLEN_ATQVFE_SHIFT 28
147#define I40E_VF_ATQLEN_ATQVFE_MASK (0x1 << I40E_VF_ATQLEN_ATQVFE_SHIFT)
148#define I40E_VF_ATQLEN_ATQOVFL_SHIFT 29
149#define I40E_VF_ATQLEN_ATQOVFL_MASK (0x1 << I40E_VF_ATQLEN_ATQOVFL_SHIFT)
150#define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30
151#define I40E_VF_ATQLEN_ATQCRIT_MASK (0x1 << I40E_VF_ATQLEN_ATQCRIT_SHIFT)
152#define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31
153#define I40E_VF_ATQLEN_ATQENABLE_MASK (0x1 << I40E_VF_ATQLEN_ATQENABLE_SHIFT)
154#define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */
155#define I40E_VF_ATQT_MAX_INDEX 127
156#define I40E_VF_ATQT_ATQT_SHIFT 0
157#define I40E_VF_ATQT_ATQT_MASK (0x3FF << I40E_VF_ATQT_ATQT_SHIFT)
158#define I40E_PRT_L2TAGSEN 0x001C0B20
159#define I40E_PRT_L2TAGSEN_ENABLE_SHIFT 0
160#define I40E_PRT_L2TAGSEN_ENABLE_MASK (0xFF << I40E_PRT_L2TAGSEN_ENABLE_SHIFT)
161#define I40E_PFCM_LAN_ERRDATA 0x0010C080
162#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT 0
163#define I40E_PFCM_LAN_ERRDATA_ERROR_CODE_MASK (0xF << I40E_PFCM_LAN_ERRDATA_ERROR_CODE_SHIFT)
164#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT 4
165#define I40E_PFCM_LAN_ERRDATA_Q_TYPE_MASK (0x7 << I40E_PFCM_LAN_ERRDATA_Q_TYPE_SHIFT)
166#define I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT 8
167#define I40E_PFCM_LAN_ERRDATA_Q_NUM_MASK (0xFFF << I40E_PFCM_LAN_ERRDATA_Q_NUM_SHIFT)
168#define I40E_PFCM_LAN_ERRINFO 0x0010C000
169#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT 0
170#define I40E_PFCM_LAN_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_PFCM_LAN_ERRINFO_ERROR_VALID_SHIFT)
171#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT 4
172#define I40E_PFCM_LAN_ERRINFO_ERROR_INST_MASK (0x7 << I40E_PFCM_LAN_ERRINFO_ERROR_INST_SHIFT)
173#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT 8
174#define I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_DBL_ERROR_CNT_SHIFT)
175#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT 16
176#define I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLU_ERROR_CNT_SHIFT)
177#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT 24
178#define I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_PFCM_LAN_ERRINFO_RLS_ERROR_CNT_SHIFT)
179#define I40E_PFCM_LANCTXCTL 0x0010C300
180#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT 0
181#define I40E_PFCM_LANCTXCTL_QUEUE_NUM_MASK (0xFFF << I40E_PFCM_LANCTXCTL_QUEUE_NUM_SHIFT)
182#define I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT 12
183#define I40E_PFCM_LANCTXCTL_SUB_LINE_MASK (0x7 << I40E_PFCM_LANCTXCTL_SUB_LINE_SHIFT)
184#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT 15
185#define I40E_PFCM_LANCTXCTL_QUEUE_TYPE_MASK (0x3 << I40E_PFCM_LANCTXCTL_QUEUE_TYPE_SHIFT)
186#define I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT 17
187#define I40E_PFCM_LANCTXCTL_OP_CODE_MASK (0x3 << I40E_PFCM_LANCTXCTL_OP_CODE_SHIFT)
188#define I40E_PFCM_LANCTXDATA(_i) (0x0010C100 + ((_i) * 128)) /* _i=0...3 */
189#define I40E_PFCM_LANCTXDATA_MAX_INDEX 3
190#define I40E_PFCM_LANCTXDATA_DATA_SHIFT 0
191#define I40E_PFCM_LANCTXDATA_DATA_MASK (0xFFFFFFFF << I40E_PFCM_LANCTXDATA_DATA_SHIFT)
192#define I40E_PFCM_LANCTXSTAT 0x0010C380
193#define I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT 0
194#define I40E_PFCM_LANCTXSTAT_CTX_DONE_MASK (0x1 << I40E_PFCM_LANCTXSTAT_CTX_DONE_SHIFT)
195#define I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT 1
196#define I40E_PFCM_LANCTXSTAT_CTX_MISS_MASK (0x1 << I40E_PFCM_LANCTXSTAT_CTX_MISS_SHIFT)
197#define I40E_PFCM_PE_ERRDATA 0x00138D00
198#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
199#define I40E_PFCM_PE_ERRDATA_ERROR_CODE_MASK (0xF << I40E_PFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
200#define I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
201#define I40E_PFCM_PE_ERRDATA_Q_TYPE_MASK (0x7 << I40E_PFCM_PE_ERRDATA_Q_TYPE_SHIFT)
202#define I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT 8
203#define I40E_PFCM_PE_ERRDATA_Q_NUM_MASK (0x3FFFF << I40E_PFCM_PE_ERRDATA_Q_NUM_SHIFT)
204#define I40E_PFCM_PE_ERRINFO 0x00138C80
205#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
206#define I40E_PFCM_PE_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_PFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
207#define I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
208#define I40E_PFCM_PE_ERRINFO_ERROR_INST_MASK (0x7 << I40E_PFCM_PE_ERRINFO_ERROR_INST_SHIFT)
209#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
210#define I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
211#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
212#define I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
213#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
214#define I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_PFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
215#define I40E_VFCM_PE_ERRDATA1(_VF) (0x00138800 + ((_VF) * 4)) /* _i=0...127 */
216#define I40E_VFCM_PE_ERRDATA1_MAX_INDEX 127
217#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT 0
218#define I40E_VFCM_PE_ERRDATA1_ERROR_CODE_MASK (0xF << I40E_VFCM_PE_ERRDATA1_ERROR_CODE_SHIFT)
219#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT 4
220#define I40E_VFCM_PE_ERRDATA1_Q_TYPE_MASK (0x7 << I40E_VFCM_PE_ERRDATA1_Q_TYPE_SHIFT)
221#define I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT 8
222#define I40E_VFCM_PE_ERRDATA1_Q_NUM_MASK (0x3FFFF << I40E_VFCM_PE_ERRDATA1_Q_NUM_SHIFT)
223#define I40E_VFCM_PE_ERRINFO1(_VF) (0x00138400 + ((_VF) * 4)) /* _i=0...127 */
224#define I40E_VFCM_PE_ERRINFO1_MAX_INDEX 127
225#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT 0
226#define I40E_VFCM_PE_ERRINFO1_ERROR_VALID_MASK (0x1 << I40E_VFCM_PE_ERRINFO1_ERROR_VALID_SHIFT)
227#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT 4
228#define I40E_VFCM_PE_ERRINFO1_ERROR_INST_MASK (0x7 << I40E_VFCM_PE_ERRINFO1_ERROR_INST_SHIFT)
229#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT 8
230#define I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_DBL_ERROR_CNT_SHIFT)
231#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT 16
232#define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT)
233#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24
234#define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT)
235#define I40E_GLDCB_GENC 0x00083044
236#define I40E_GLDCB_GENC_PCIRTT_SHIFT 0
237#define I40E_GLDCB_GENC_PCIRTT_MASK (0xFFFF << I40E_GLDCB_GENC_PCIRTT_SHIFT)
238#define I40E_GLDCB_RUPTI 0x00122618
239#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT 0
240#define I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_MASK (0xFFFFFFFF << I40E_GLDCB_RUPTI_PFCTIMEOUT_UP_SHIFT)
241#define I40E_PRTDCB_FCCFG 0x001E4640
242#define I40E_PRTDCB_FCCFG_TFCE_SHIFT 3
243#define I40E_PRTDCB_FCCFG_TFCE_MASK (0x3 << I40E_PRTDCB_FCCFG_TFCE_SHIFT)
244#define I40E_PRTDCB_FCRTV 0x001E4600
245#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT 0
246#define I40E_PRTDCB_FCRTV_FC_REFRESH_TH_MASK (0xFFFF << I40E_PRTDCB_FCRTV_FC_REFRESH_TH_SHIFT)
247#define I40E_PRTDCB_FCTTVN(_i) (0x001E4580 + ((_i) * 32)) /* _i=0...3 */
248#define I40E_PRTDCB_FCTTVN_MAX_INDEX 3
249#define I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT 0
250#define I40E_PRTDCB_FCTTVN_TTV_2N_MASK (0xFFFF << I40E_PRTDCB_FCTTVN_TTV_2N_SHIFT)
251#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT 16
252#define I40E_PRTDCB_FCTTVN_TTV_2N_P1_MASK (0xFFFF << I40E_PRTDCB_FCTTVN_TTV_2N_P1_SHIFT)
253#define I40E_PRTDCB_GENC 0x00083000
254#define I40E_PRTDCB_GENC_RESERVED_1_SHIFT 0
255#define I40E_PRTDCB_GENC_RESERVED_1_MASK (0x3 << I40E_PRTDCB_GENC_RESERVED_1_SHIFT)
256#define I40E_PRTDCB_GENC_NUMTC_SHIFT 2
257#define I40E_PRTDCB_GENC_NUMTC_MASK (0xF << I40E_PRTDCB_GENC_NUMTC_SHIFT)
258#define I40E_PRTDCB_GENC_FCOEUP_SHIFT 6
259#define I40E_PRTDCB_GENC_FCOEUP_MASK (0x7 << I40E_PRTDCB_GENC_FCOEUP_SHIFT)
260#define I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT 9
261#define I40E_PRTDCB_GENC_FCOEUP_VALID_MASK (0x1 << I40E_PRTDCB_GENC_FCOEUP_VALID_SHIFT)
262#define I40E_PRTDCB_GENC_PFCLDA_SHIFT 16
263#define I40E_PRTDCB_GENC_PFCLDA_MASK (0xFFFF << I40E_PRTDCB_GENC_PFCLDA_SHIFT)
264#define I40E_PRTDCB_GENS 0x00083020
265#define I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT 0
266#define I40E_PRTDCB_GENS_DCBX_STATUS_MASK (0x7 << I40E_PRTDCB_GENS_DCBX_STATUS_SHIFT)
267#define I40E_PRTDCB_MFLCN 0x001E2400
268#define I40E_PRTDCB_MFLCN_PMCF_SHIFT 0
269#define I40E_PRTDCB_MFLCN_PMCF_MASK (0x1 << I40E_PRTDCB_MFLCN_PMCF_SHIFT)
270#define I40E_PRTDCB_MFLCN_DPF_SHIFT 1
271#define I40E_PRTDCB_MFLCN_DPF_MASK (0x1 << I40E_PRTDCB_MFLCN_DPF_SHIFT)
272#define I40E_PRTDCB_MFLCN_RPFCM_SHIFT 2
273#define I40E_PRTDCB_MFLCN_RPFCM_MASK (0x1 << I40E_PRTDCB_MFLCN_RPFCM_SHIFT)
274#define I40E_PRTDCB_MFLCN_RFCE_SHIFT 3
275#define I40E_PRTDCB_MFLCN_RFCE_MASK (0x1 << I40E_PRTDCB_MFLCN_RFCE_SHIFT)
276#define I40E_PRTDCB_MFLCN_RPFCE_SHIFT 4
277#define I40E_PRTDCB_MFLCN_RPFCE_MASK (0xFF << I40E_PRTDCB_MFLCN_RPFCE_SHIFT)
278#define I40E_PRTDCB_RETSC 0x001223E0
279#define I40E_PRTDCB_RETSC_ETS_MODE_SHIFT 0
280#define I40E_PRTDCB_RETSC_ETS_MODE_MASK (0x1 << I40E_PRTDCB_RETSC_ETS_MODE_SHIFT)
281#define I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT 1
282#define I40E_PRTDCB_RETSC_NON_ETS_MODE_MASK (0x1 << I40E_PRTDCB_RETSC_NON_ETS_MODE_SHIFT)
283#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT 2
284#define I40E_PRTDCB_RETSC_ETS_MAX_EXP_MASK (0xF << I40E_PRTDCB_RETSC_ETS_MAX_EXP_SHIFT)
285#define I40E_PRTDCB_RETSC_LLTC_SHIFT 8
286#define I40E_PRTDCB_RETSC_LLTC_MASK (0xFF << I40E_PRTDCB_RETSC_LLTC_SHIFT)
287#define I40E_PRTDCB_RETSTCC(_i) (0x00122180 + ((_i) * 32)) /* _i=0...7 */
288#define I40E_PRTDCB_RETSTCC_MAX_INDEX 7
289#define I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT 0
290#define I40E_PRTDCB_RETSTCC_BWSHARE_MASK (0x7F << I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT)
291#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30
292#define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK (0x1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)
293#define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31
294#define I40E_PRTDCB_RETSTCC_ETSTC_MASK (0x1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)
295#define I40E_PRTDCB_RPPMC 0x001223A0
296#define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0
297#define I40E_PRTDCB_RPPMC_LANRPPM_MASK (0xFF << I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)
298#define I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT 8
299#define I40E_PRTDCB_RPPMC_RDMARPPM_MASK (0xFF << I40E_PRTDCB_RPPMC_RDMARPPM_SHIFT)
300#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT 16
301#define I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_MASK (0xFF << I40E_PRTDCB_RPPMC_RX_FIFO_SIZE_SHIFT)
302#define I40E_PRTDCB_RUP 0x001C0B00
303#define I40E_PRTDCB_RUP_NOVLANUP_SHIFT 0
304#define I40E_PRTDCB_RUP_NOVLANUP_MASK (0x7 << I40E_PRTDCB_RUP_NOVLANUP_SHIFT)
305#define I40E_PRTDCB_RUP2TC 0x001C09A0
306#define I40E_PRTDCB_RUP2TC_UP0TC_SHIFT 0
307#define I40E_PRTDCB_RUP2TC_UP0TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP0TC_SHIFT)
308#define I40E_PRTDCB_RUP2TC_UP1TC_SHIFT 3
309#define I40E_PRTDCB_RUP2TC_UP1TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP1TC_SHIFT)
310#define I40E_PRTDCB_RUP2TC_UP2TC_SHIFT 6
311#define I40E_PRTDCB_RUP2TC_UP2TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP2TC_SHIFT)
312#define I40E_PRTDCB_RUP2TC_UP3TC_SHIFT 9
313#define I40E_PRTDCB_RUP2TC_UP3TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP3TC_SHIFT)
314#define I40E_PRTDCB_RUP2TC_UP4TC_SHIFT 12
315#define I40E_PRTDCB_RUP2TC_UP4TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP4TC_SHIFT)
316#define I40E_PRTDCB_RUP2TC_UP5TC_SHIFT 15
317#define I40E_PRTDCB_RUP2TC_UP5TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP5TC_SHIFT)
318#define I40E_PRTDCB_RUP2TC_UP6TC_SHIFT 18
319#define I40E_PRTDCB_RUP2TC_UP6TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP6TC_SHIFT)
320#define I40E_PRTDCB_RUP2TC_UP7TC_SHIFT 21
321#define I40E_PRTDCB_RUP2TC_UP7TC_MASK (0x7 << I40E_PRTDCB_RUP2TC_UP7TC_SHIFT)
322#define I40E_PRTDCB_TC2PFC 0x001C0980
323#define I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT 0
324#define I40E_PRTDCB_TC2PFC_TC2PFC_MASK (0xFF << I40E_PRTDCB_TC2PFC_TC2PFC_SHIFT)
325#define I40E_PRTDCB_TCPMC 0x000A21A0
326#define I40E_PRTDCB_TCPMC_CPM_SHIFT 0
327#define I40E_PRTDCB_TCPMC_CPM_MASK (0x1FFF << I40E_PRTDCB_TCPMC_CPM_SHIFT)
328#define I40E_PRTDCB_TCPMC_LLTC_SHIFT 13
329#define I40E_PRTDCB_TCPMC_LLTC_MASK (0xFF << I40E_PRTDCB_TCPMC_LLTC_SHIFT)
330#define I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT 30
331#define I40E_PRTDCB_TCPMC_TCPM_MODE_MASK (0x1 << I40E_PRTDCB_TCPMC_TCPM_MODE_SHIFT)
332#define I40E_PRTDCB_TCWSTC(_i) (0x000A2040 + ((_i) * 32)) /* _i=0...7 */
333#define I40E_PRTDCB_TCWSTC_MAX_INDEX 7
334#define I40E_PRTDCB_TCWSTC_MSTC_SHIFT 0
335#define I40E_PRTDCB_TCWSTC_MSTC_MASK (0xFFFFF << I40E_PRTDCB_TCWSTC_MSTC_SHIFT)
336#define I40E_PRTDCB_TDPMC 0x000A0180
337#define I40E_PRTDCB_TDPMC_DPM_SHIFT 0
338#define I40E_PRTDCB_TDPMC_DPM_MASK (0xFF << I40E_PRTDCB_TDPMC_DPM_SHIFT)
339#define I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT 30
340#define I40E_PRTDCB_TDPMC_TCPM_MODE_MASK (0x1 << I40E_PRTDCB_TDPMC_TCPM_MODE_SHIFT)
341#define I40E_PRTDCB_TDPUC 0x00044100
342#define I40E_PRTDCB_TDPUC_MAX_TXFRAME_SHIFT 0
343#define I40E_PRTDCB_TDPUC_MAX_TXFRAME_MASK (0xFFFF << I40E_PRTDCB_TDPUC_MAX_TXFRAME_SHIFT)
344#define I40E_PRTDCB_TETSC_TCB 0x000AE060
345#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT 0
346#define I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_MASK (0x1 << I40E_PRTDCB_TETSC_TCB_EN_LL_STRICT_PRIORITY_SHIFT)
347#define I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT 8
348#define I40E_PRTDCB_TETSC_TCB_LLTC_MASK (0xFF << I40E_PRTDCB_TETSC_TCB_LLTC_SHIFT)
349#define I40E_PRTDCB_TETSC_TPB 0x00098060
350#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT 0
351#define I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_MASK (0x1 << I40E_PRTDCB_TETSC_TPB_EN_LL_STRICT_PRIORITY_SHIFT)
352#define I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT 8
353#define I40E_PRTDCB_TETSC_TPB_LLTC_MASK (0xFF << I40E_PRTDCB_TETSC_TPB_LLTC_SHIFT)
354#define I40E_PRTDCB_TFCS 0x001E4560
355#define I40E_PRTDCB_TFCS_TXOFF_SHIFT 0
356#define I40E_PRTDCB_TFCS_TXOFF_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF_SHIFT)
357#define I40E_PRTDCB_TFCS_TXOFF0_SHIFT 8
358#define I40E_PRTDCB_TFCS_TXOFF0_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF0_SHIFT)
359#define I40E_PRTDCB_TFCS_TXOFF1_SHIFT 9
360#define I40E_PRTDCB_TFCS_TXOFF1_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF1_SHIFT)
361#define I40E_PRTDCB_TFCS_TXOFF2_SHIFT 10
362#define I40E_PRTDCB_TFCS_TXOFF2_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF2_SHIFT)
363#define I40E_PRTDCB_TFCS_TXOFF3_SHIFT 11
364#define I40E_PRTDCB_TFCS_TXOFF3_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF3_SHIFT)
365#define I40E_PRTDCB_TFCS_TXOFF4_SHIFT 12
366#define I40E_PRTDCB_TFCS_TXOFF4_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF4_SHIFT)
367#define I40E_PRTDCB_TFCS_TXOFF5_SHIFT 13
368#define I40E_PRTDCB_TFCS_TXOFF5_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF5_SHIFT)
369#define I40E_PRTDCB_TFCS_TXOFF6_SHIFT 14
370#define I40E_PRTDCB_TFCS_TXOFF6_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF6_SHIFT)
371#define I40E_PRTDCB_TFCS_TXOFF7_SHIFT 15
372#define I40E_PRTDCB_TFCS_TXOFF7_MASK (0x1 << I40E_PRTDCB_TFCS_TXOFF7_SHIFT)
373#define I40E_PRTDCB_TFWSTC(_i) (0x000A0040 + ((_i) * 32)) /* _i=0...7 */
374#define I40E_PRTDCB_TFWSTC_MAX_INDEX 7
375#define I40E_PRTDCB_TFWSTC_MSTC_SHIFT 0
376#define I40E_PRTDCB_TFWSTC_MSTC_MASK (0xFFFFF << I40E_PRTDCB_TFWSTC_MSTC_SHIFT)
377#define I40E_PRTDCB_TPFCTS(_i) (0x001E4660 + ((_i) * 32)) /* _i=0...7 */
378#define I40E_PRTDCB_TPFCTS_MAX_INDEX 7
379#define I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT 0
380#define I40E_PRTDCB_TPFCTS_PFCTIMER_MASK (0x3FFF << I40E_PRTDCB_TPFCTS_PFCTIMER_SHIFT)
381#define I40E_GLFCOE_RCTL 0x00269B94
382#define I40E_GLFCOE_RCTL_FCOEVER_SHIFT 0
383#define I40E_GLFCOE_RCTL_FCOEVER_MASK (0xF << I40E_GLFCOE_RCTL_FCOEVER_SHIFT)
384#define I40E_GLFCOE_RCTL_SAVBAD_SHIFT 4
385#define I40E_GLFCOE_RCTL_SAVBAD_MASK (0x1 << I40E_GLFCOE_RCTL_SAVBAD_SHIFT)
386#define I40E_GLFCOE_RCTL_ICRC_SHIFT 5
387#define I40E_GLFCOE_RCTL_ICRC_MASK (0x1 << I40E_GLFCOE_RCTL_ICRC_SHIFT)
388#define I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT 16
389#define I40E_GLFCOE_RCTL_MAX_SIZE_MASK (0x3FFF << I40E_GLFCOE_RCTL_MAX_SIZE_SHIFT)
390#define I40E_GL_FWSTS 0x00083048
391#define I40E_GL_FWSTS_FWS0B_SHIFT 0
392#define I40E_GL_FWSTS_FWS0B_MASK (0xFF << I40E_GL_FWSTS_FWS0B_SHIFT)
393#define I40E_GL_FWSTS_FWRI_SHIFT 9
394#define I40E_GL_FWSTS_FWRI_MASK (0x1 << I40E_GL_FWSTS_FWRI_SHIFT)
395#define I40E_GL_FWSTS_FWS1B_SHIFT 16
396#define I40E_GL_FWSTS_FWS1B_MASK (0xFF << I40E_GL_FWSTS_FWS1B_SHIFT)
397#define I40E_GLGEN_CLKSTAT 0x000B8184
398#define I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT 0
399#define I40E_GLGEN_CLKSTAT_CLKMODE_MASK (0x1 << I40E_GLGEN_CLKSTAT_CLKMODE_SHIFT)
400#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT 4
401#define I40E_GLGEN_CLKSTAT_U_CLK_SPEED_MASK (0x3 << I40E_GLGEN_CLKSTAT_U_CLK_SPEED_SHIFT)
402#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT 8
403#define I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P0_CLK_SPEED_SHIFT)
404#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT 12
405#define I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P1_CLK_SPEED_SHIFT)
406#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT 16
407#define I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P2_CLK_SPEED_SHIFT)
408#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT 20
409#define I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_MASK (0x7 << I40E_GLGEN_CLKSTAT_P3_CLK_SPEED_SHIFT)
410#define I40E_GLGEN_GPIO_CTL(_i) (0x00088100 + ((_i) * 4)) /* _i=0...29 */
411#define I40E_GLGEN_GPIO_CTL_MAX_INDEX 29
412#define I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT 0
413#define I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK (0x3 << I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT)
414#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT 3
415#define I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK (0x1 << I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_SHIFT)
416#define I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT 4
417#define I40E_GLGEN_GPIO_CTL_PIN_DIR_MASK (0x1 << I40E_GLGEN_GPIO_CTL_PIN_DIR_SHIFT)
418#define I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT 5
419#define I40E_GLGEN_GPIO_CTL_TRI_CTL_MASK (0x1 << I40E_GLGEN_GPIO_CTL_TRI_CTL_SHIFT)
420#define I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT 6
421#define I40E_GLGEN_GPIO_CTL_OUT_CTL_MASK (0x1 << I40E_GLGEN_GPIO_CTL_OUT_CTL_SHIFT)
422#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT 7
423#define I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK (0x7 << I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT)
424#define I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT 10
425#define I40E_GLGEN_GPIO_CTL_LED_INVRT_MASK (0x1 << I40E_GLGEN_GPIO_CTL_LED_INVRT_SHIFT)
426#define I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT 11
427#define I40E_GLGEN_GPIO_CTL_LED_BLINK_MASK (0x1 << I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT)
428#define I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT 12
429#define I40E_GLGEN_GPIO_CTL_LED_MODE_MASK (0xF << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
430#define I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT 17
431#define I40E_GLGEN_GPIO_CTL_INT_MODE_MASK (0x3 << I40E_GLGEN_GPIO_CTL_INT_MODE_SHIFT)
432#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT 19
433#define I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_MASK (0x1 << I40E_GLGEN_GPIO_CTL_OUT_DEFAULT_SHIFT)
434#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT 20
435#define I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_MASK (0x3F << I40E_GLGEN_GPIO_CTL_PHY_PIN_NAME_SHIFT)
436#define I40E_GLGEN_GPIO_SET 0x00088184
437#define I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT 0
438#define I40E_GLGEN_GPIO_SET_GPIO_INDX_MASK (0x1F << I40E_GLGEN_GPIO_SET_GPIO_INDX_SHIFT)
439#define I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT 5
440#define I40E_GLGEN_GPIO_SET_SDP_DATA_MASK (0x1 << I40E_GLGEN_GPIO_SET_SDP_DATA_SHIFT)
441#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT 6
442#define I40E_GLGEN_GPIO_SET_DRIVE_SDP_MASK (0x1 << I40E_GLGEN_GPIO_SET_DRIVE_SDP_SHIFT)
443#define I40E_GLGEN_GPIO_STAT 0x0008817C
444#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT 0
445#define I40E_GLGEN_GPIO_STAT_GPIO_VALUE_MASK (0x3FFFFFFF << I40E_GLGEN_GPIO_STAT_GPIO_VALUE_SHIFT)
446#define I40E_GLGEN_GPIO_TRANSIT 0x00088180
447#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT 0
448#define I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_MASK (0x3FFFFFFF << I40E_GLGEN_GPIO_TRANSIT_GPIO_TRANSITION_SHIFT)
449#define I40E_GLGEN_I2CCMD(_i) (0x000881E0 + ((_i) * 4)) /* _i=0...3 */
450#define I40E_GLGEN_I2CCMD_MAX_INDEX 3
451#define I40E_GLGEN_I2CCMD_DATA_SHIFT 0
452#define I40E_GLGEN_I2CCMD_DATA_MASK (0xFFFF << I40E_GLGEN_I2CCMD_DATA_SHIFT)
453#define I40E_GLGEN_I2CCMD_REGADD_SHIFT 16
454#define I40E_GLGEN_I2CCMD_REGADD_MASK (0xFF << I40E_GLGEN_I2CCMD_REGADD_SHIFT)
455#define I40E_GLGEN_I2CCMD_PHYADD_SHIFT 24
456#define I40E_GLGEN_I2CCMD_PHYADD_MASK (0x7 << I40E_GLGEN_I2CCMD_PHYADD_SHIFT)
457#define I40E_GLGEN_I2CCMD_OP_SHIFT 27
458#define I40E_GLGEN_I2CCMD_OP_MASK (0x1 << I40E_GLGEN_I2CCMD_OP_SHIFT)
459#define I40E_GLGEN_I2CCMD_RESET_SHIFT 28
460#define I40E_GLGEN_I2CCMD_RESET_MASK (0x1 << I40E_GLGEN_I2CCMD_RESET_SHIFT)
461#define I40E_GLGEN_I2CCMD_R_SHIFT 29
462#define I40E_GLGEN_I2CCMD_R_MASK (0x1 << I40E_GLGEN_I2CCMD_R_SHIFT)
463#define I40E_GLGEN_I2CCMD_E_SHIFT 31
464#define I40E_GLGEN_I2CCMD_E_MASK (0x1 << I40E_GLGEN_I2CCMD_E_SHIFT)
465#define I40E_GLGEN_I2CPARAMS(_i) (0x000881AC + ((_i) * 4)) /* _i=0...3 */
466#define I40E_GLGEN_I2CPARAMS_MAX_INDEX 3
467#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT 0
468#define I40E_GLGEN_I2CPARAMS_WRITE_TIME_MASK (0x1F << I40E_GLGEN_I2CPARAMS_WRITE_TIME_SHIFT)
469#define I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT 5
470#define I40E_GLGEN_I2CPARAMS_READ_TIME_MASK (0x7 << I40E_GLGEN_I2CPARAMS_READ_TIME_SHIFT)
471#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT 8
472#define I40E_GLGEN_I2CPARAMS_I2CBB_EN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_I2CBB_EN_SHIFT)
473#define I40E_GLGEN_I2CPARAMS_CLK_SHIFT 9
474#define I40E_GLGEN_I2CPARAMS_CLK_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_SHIFT)
475#define I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT 10
476#define I40E_GLGEN_I2CPARAMS_DATA_OUT_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_OUT_SHIFT)
477#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT 11
478#define I40E_GLGEN_I2CPARAMS_DATA_OE_N_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_OE_N_SHIFT)
479#define I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT 12
480#define I40E_GLGEN_I2CPARAMS_DATA_IN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_DATA_IN_SHIFT)
481#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT 13
482#define I40E_GLGEN_I2CPARAMS_CLK_OE_N_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_OE_N_SHIFT)
483#define I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT 14
484#define I40E_GLGEN_I2CPARAMS_CLK_IN_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_IN_SHIFT)
485#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT 15
486#define I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_MASK (0x1 << I40E_GLGEN_I2CPARAMS_CLK_STRETCH_DIS_SHIFT)
487#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT 31
488#define I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_MASK (0x1 << I40E_GLGEN_I2CPARAMS_I2C_DATA_ORDER_SHIFT)
489#define I40E_GLGEN_LED_CTL 0x00088178
490#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT 0
491#define I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_MASK (0x1 << I40E_GLGEN_LED_CTL_GLOBAL_BLINK_MODE_SHIFT)
492#define I40E_GLGEN_MDIO_CTRL(_i) (0x000881D0 + ((_i) * 4)) /* _i=0...3 */
493#define I40E_GLGEN_MDIO_CTRL_MAX_INDEX 3
494#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT 0
495#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_MASK (0x1FFFF << I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD2_SHIFT)
496#define I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT 17
497#define I40E_GLGEN_MDIO_CTRL_CONTMDC_MASK (0x1 << I40E_GLGEN_MDIO_CTRL_CONTMDC_SHIFT)
498#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT 18
499#define I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_MASK (0x3FFF << I40E_GLGEN_MDIO_CTRL_LEGACY_RSVD1_SHIFT)
500#define I40E_GLGEN_MDIO_I2C_SEL(_i) (0x000881C0 + ((_i) * 4)) /* _i=0...3 */
501#define I40E_GLGEN_MDIO_I2C_SEL_MAX_INDEX 3
502#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT 0
503#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_MASK (0x1 << I40E_GLGEN_MDIO_I2C_SEL_MDIO_I2C_SEL_SHIFT)
504#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT 1
505#define I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_MASK (0xF << I40E_GLGEN_MDIO_I2C_SEL_PHY_PORT_NUM_SHIFT)
506#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT 5
507#define I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY0_ADDRESS_SHIFT)
508#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT 10
509#define I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY1_ADDRESS_SHIFT)
510#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT 15
511#define I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY2_ADDRESS_SHIFT)
512#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT 20
513#define I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_MASK (0x1F << I40E_GLGEN_MDIO_I2C_SEL_PHY3_ADDRESS_SHIFT)
514#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT 25
515#define I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_MASK (0xF << I40E_GLGEN_MDIO_I2C_SEL_MDIO_IF_MODE_SHIFT)
516#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT 31
517#define I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_MASK (0x1 << I40E_GLGEN_MDIO_I2C_SEL_EN_FAST_MODE_SHIFT)
518#define I40E_GLGEN_MSCA(_i) (0x0008818C + ((_i) * 4)) /* _i=0...3 */
519#define I40E_GLGEN_MSCA_MAX_INDEX 3
520#define I40E_GLGEN_MSCA_MDIADD_SHIFT 0
521#define I40E_GLGEN_MSCA_MDIADD_MASK (0xFFFF << I40E_GLGEN_MSCA_MDIADD_SHIFT)
522#define I40E_GLGEN_MSCA_DEVADD_SHIFT 16
523#define I40E_GLGEN_MSCA_DEVADD_MASK (0x1F << I40E_GLGEN_MSCA_DEVADD_SHIFT)
524#define I40E_GLGEN_MSCA_PHYADD_SHIFT 21
525#define I40E_GLGEN_MSCA_PHYADD_MASK (0x1F << I40E_GLGEN_MSCA_PHYADD_SHIFT)
526#define I40E_GLGEN_MSCA_OPCODE_SHIFT 26
527#define I40E_GLGEN_MSCA_OPCODE_MASK (0x3 << I40E_GLGEN_MSCA_OPCODE_SHIFT)
528#define I40E_GLGEN_MSCA_STCODE_SHIFT 28
529#define I40E_GLGEN_MSCA_STCODE_MASK (0x3 << I40E_GLGEN_MSCA_STCODE_SHIFT)
530#define I40E_GLGEN_MSCA_MDICMD_SHIFT 30
531#define I40E_GLGEN_MSCA_MDICMD_MASK (0x1 << I40E_GLGEN_MSCA_MDICMD_SHIFT)
532#define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31
533#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK (0x1 << I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)
534#define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */
535#define I40E_GLGEN_MSRWD_MAX_INDEX 3
536#define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0
537#define I40E_GLGEN_MSRWD_MDIWRDATA_MASK (0xFFFF << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT)
538#define I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT 16
539#define I40E_GLGEN_MSRWD_MDIRDDATA_MASK (0xFFFF << I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT)
540#define I40E_GLGEN_PCIFCNCNT 0x001C0AB4
541#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT 0
542#define I40E_GLGEN_PCIFCNCNT_PCIPFCNT_MASK (0x1F << I40E_GLGEN_PCIFCNCNT_PCIPFCNT_SHIFT)
543#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT 16
544#define I40E_GLGEN_PCIFCNCNT_PCIVFCNT_MASK (0xFF << I40E_GLGEN_PCIFCNCNT_PCIVFCNT_SHIFT)
545#define I40E_GLGEN_PE_ENA 0x000B81A0
546#define I40E_GLGEN_PE_ENA_PE_ENA_SHIFT 0
547#define I40E_GLGEN_PE_ENA_PE_ENA_MASK (0x1 << I40E_GLGEN_PE_ENA_PE_ENA_SHIFT)
548#define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT 1
549#define I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_MASK (0x3 << I40E_GLGEN_PE_ENA_PE_CLK_SRC_SEL_SHIFT)
550#define I40E_GLGEN_RSTAT 0x000B8188
551#define I40E_GLGEN_RSTAT_DEVSTATE_SHIFT 0
552#define I40E_GLGEN_RSTAT_DEVSTATE_MASK (0x3 << I40E_GLGEN_RSTAT_DEVSTATE_SHIFT)
553#define I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT 2
554#define I40E_GLGEN_RSTAT_RESET_TYPE_MASK (0x3 << I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT)
555#define I40E_GLGEN_RSTAT_CORERCNT_SHIFT 4
556#define I40E_GLGEN_RSTAT_CORERCNT_MASK (0x3 << I40E_GLGEN_RSTAT_CORERCNT_SHIFT)
557#define I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT 6
558#define I40E_GLGEN_RSTAT_GLOBRCNT_MASK (0x3 << I40E_GLGEN_RSTAT_GLOBRCNT_SHIFT)
559#define I40E_GLGEN_RSTAT_EMPRCNT_SHIFT 8
560#define I40E_GLGEN_RSTAT_EMPRCNT_MASK (0x3 << I40E_GLGEN_RSTAT_EMPRCNT_SHIFT)
561#define I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT 10
562#define I40E_GLGEN_RSTAT_TIME_TO_RST_MASK (0x3F << I40E_GLGEN_RSTAT_TIME_TO_RST_SHIFT)
563#define I40E_GLGEN_RSTCTL 0x000B8180
564#define I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT 0
565#define I40E_GLGEN_RSTCTL_GRSTDEL_MASK (0x3F << I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT)
566#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT 8
567#define I40E_GLGEN_RSTCTL_ECC_RST_ENA_MASK (0x1 << I40E_GLGEN_RSTCTL_ECC_RST_ENA_SHIFT)
568#define I40E_GLGEN_RSTENA_EMP 0x000B818C
569#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT 0
570#define I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_MASK (0x1 << I40E_GLGEN_RSTENA_EMP_EMP_RST_ENA_SHIFT)
571#define I40E_GLGEN_RTRIG 0x000B8190
572#define I40E_GLGEN_RTRIG_CORER_SHIFT 0
573#define I40E_GLGEN_RTRIG_CORER_MASK (0x1 << I40E_GLGEN_RTRIG_CORER_SHIFT)
574#define I40E_GLGEN_RTRIG_GLOBR_SHIFT 1
575#define I40E_GLGEN_RTRIG_GLOBR_MASK (0x1 << I40E_GLGEN_RTRIG_GLOBR_SHIFT)
576#define I40E_GLGEN_RTRIG_EMPFWR_SHIFT 2
577#define I40E_GLGEN_RTRIG_EMPFWR_MASK (0x1 << I40E_GLGEN_RTRIG_EMPFWR_SHIFT)
578#define I40E_GLGEN_STAT 0x000B612C
579#define I40E_GLGEN_STAT_HWRSVD0_SHIFT 0
580#define I40E_GLGEN_STAT_HWRSVD0_MASK (0x3 << I40E_GLGEN_STAT_HWRSVD0_SHIFT)
581#define I40E_GLGEN_STAT_DCBEN_SHIFT 2
582#define I40E_GLGEN_STAT_DCBEN_MASK (0x1 << I40E_GLGEN_STAT_DCBEN_SHIFT)
583#define I40E_GLGEN_STAT_VTEN_SHIFT 3
584#define I40E_GLGEN_STAT_VTEN_MASK (0x1 << I40E_GLGEN_STAT_VTEN_SHIFT)
585#define I40E_GLGEN_STAT_FCOEN_SHIFT 4
586#define I40E_GLGEN_STAT_FCOEN_MASK (0x1 << I40E_GLGEN_STAT_FCOEN_SHIFT)
587#define I40E_GLGEN_STAT_EVBEN_SHIFT 5
588#define I40E_GLGEN_STAT_EVBEN_MASK (0x1 << I40E_GLGEN_STAT_EVBEN_SHIFT)
589#define I40E_GLGEN_STAT_HWRSVD1_SHIFT 6
590#define I40E_GLGEN_STAT_HWRSVD1_MASK (0x3 << I40E_GLGEN_STAT_HWRSVD1_SHIFT)
591#define I40E_GLGEN_VFLRSTAT(_i) (0x00092600 + ((_i) * 4)) /* _i=0...3 */
592#define I40E_GLGEN_VFLRSTAT_MAX_INDEX 3
593#define I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT 0
594#define I40E_GLGEN_VFLRSTAT_VFLRE_MASK (0xFFFFFFFF << I40E_GLGEN_VFLRSTAT_VFLRE_SHIFT)
595#define I40E_GLVFGEN_TIMER 0x000881BC
596#define I40E_GLVFGEN_TIMER_GTIME_SHIFT 0
597#define I40E_GLVFGEN_TIMER_GTIME_MASK (0xFFFFFFFF << I40E_GLVFGEN_TIMER_GTIME_SHIFT)
598#define I40E_PFGEN_CTRL 0x00092400
599#define I40E_PFGEN_CTRL_PFSWR_SHIFT 0
600#define I40E_PFGEN_CTRL_PFSWR_MASK (0x1 << I40E_PFGEN_CTRL_PFSWR_SHIFT)
601#define I40E_PFGEN_DRUN 0x00092500
602#define I40E_PFGEN_DRUN_DRVUNLD_SHIFT 0
603#define I40E_PFGEN_DRUN_DRVUNLD_MASK (0x1 << I40E_PFGEN_DRUN_DRVUNLD_SHIFT)
604#define I40E_PFGEN_PORTNUM 0x001C0480
605#define I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT 0
606#define I40E_PFGEN_PORTNUM_PORT_NUM_MASK (0x3 << I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT)
607#define I40E_PFGEN_STATE 0x00088000
608#define I40E_PFGEN_STATE_PFPEEN_SHIFT 0
609#define I40E_PFGEN_STATE_PFPEEN_MASK (0x1 << I40E_PFGEN_STATE_PFPEEN_SHIFT)
610#define I40E_PFGEN_STATE_PFFCEN_SHIFT 1
611#define I40E_PFGEN_STATE_PFFCEN_MASK (0x1 << I40E_PFGEN_STATE_PFFCEN_SHIFT)
612#define I40E_PFGEN_STATE_PFLINKEN_SHIFT 2
613#define I40E_PFGEN_STATE_PFLINKEN_MASK (0x1 << I40E_PFGEN_STATE_PFLINKEN_SHIFT)
614#define I40E_PFGEN_STATE_PFSCEN_SHIFT 3
615#define I40E_PFGEN_STATE_PFSCEN_MASK (0x1 << I40E_PFGEN_STATE_PFSCEN_SHIFT)
616#define I40E_PRTGEN_CNF 0x000B8120
617#define I40E_PRTGEN_CNF_PORT_DIS_SHIFT 0
618#define I40E_PRTGEN_CNF_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_PORT_DIS_SHIFT)
619#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT 1
620#define I40E_PRTGEN_CNF_ALLOW_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_ALLOW_PORT_DIS_SHIFT)
621#define I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT 2
622#define I40E_PRTGEN_CNF_EMP_PORT_DIS_MASK (0x1 << I40E_PRTGEN_CNF_EMP_PORT_DIS_SHIFT)
623#define I40E_PRTGEN_CNF2 0x000B8160
624#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT 0
625#define I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_MASK (0x1 << I40E_PRTGEN_CNF2_ACTIVATE_PORT_LINK_SHIFT)
626#define I40E_PRTGEN_STATUS 0x000B8100
627#define I40E_PRTGEN_STATUS_PORT_VALID_SHIFT 0
628#define I40E_PRTGEN_STATUS_PORT_VALID_MASK (0x1 << I40E_PRTGEN_STATUS_PORT_VALID_SHIFT)
629#define I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT 1
630#define I40E_PRTGEN_STATUS_PORT_ACTIVE_MASK (0x1 << I40E_PRTGEN_STATUS_PORT_ACTIVE_SHIFT)
631#define I40E_VFGEN_RSTAT1(_VF) (0x00074400 + ((_VF) * 4)) /* _i=0...127 */
632#define I40E_VFGEN_RSTAT1_MAX_INDEX 127
633#define I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT 0
634#define I40E_VFGEN_RSTAT1_VFR_STATE_MASK (0x3 << I40E_VFGEN_RSTAT1_VFR_STATE_SHIFT)
635#define I40E_VPGEN_VFRSTAT(_VF) (0x00091C00 + ((_VF) * 4)) /* _i=0...127 */
636#define I40E_VPGEN_VFRSTAT_MAX_INDEX 127
637#define I40E_VPGEN_VFRSTAT_VFRD_SHIFT 0
638#define I40E_VPGEN_VFRSTAT_VFRD_MASK (0x1 << I40E_VPGEN_VFRSTAT_VFRD_SHIFT)
639#define I40E_VPGEN_VFRTRIG(_VF) (0x00091800 + ((_VF) * 4)) /* _i=0...127 */
640#define I40E_VPGEN_VFRTRIG_MAX_INDEX 127
641#define I40E_VPGEN_VFRTRIG_VFSWR_SHIFT 0
642#define I40E_VPGEN_VFRTRIG_VFSWR_MASK (0x1 << I40E_VPGEN_VFRTRIG_VFSWR_SHIFT)
643#define I40E_VSIGEN_RSTAT(_VSI) (0x00090800 + ((_VSI) * 4)) /* _i=0...383 */
644#define I40E_VSIGEN_RSTAT_MAX_INDEX 383
645#define I40E_VSIGEN_RSTAT_VMRD_SHIFT 0
646#define I40E_VSIGEN_RSTAT_VMRD_MASK (0x1 << I40E_VSIGEN_RSTAT_VMRD_SHIFT)
647#define I40E_VSIGEN_RTRIG(_VSI) (0x00090000 + ((_VSI) * 4)) /* _i=0...383 */
648#define I40E_VSIGEN_RTRIG_MAX_INDEX 383
649#define I40E_VSIGEN_RTRIG_VMSWR_SHIFT 0
650#define I40E_VSIGEN_RTRIG_VMSWR_MASK (0x1 << I40E_VSIGEN_RTRIG_VMSWR_SHIFT)
651#define I40E_GLHMC_APBVTINUSEBASE(_i) (0x000C4a00 + ((_i) * 4))
652#define I40E_GLHMC_APBVTINUSEBASE_MAX_INDEX 15
653#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
654#define I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_MASK (0xFFFFFF << I40E_GLHMC_APBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
655#define I40E_GLHMC_CEQPART(_i) (0x001312C0 + ((_i) * 4)) /* _i=0...15 */
656#define I40E_GLHMC_CEQPART_MAX_INDEX 15
657#define I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT 0
658#define I40E_GLHMC_CEQPART_PMCEQBASE_MASK (0xFF << I40E_GLHMC_CEQPART_PMCEQBASE_SHIFT)
659#define I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT 16
660#define I40E_GLHMC_CEQPART_PMCEQSIZE_MASK (0x1FF << I40E_GLHMC_CEQPART_PMCEQSIZE_SHIFT)
661#define I40E_GLHMC_DBCQPART(_i) (0x00131240 + ((_i) * 4)) /* _i=0...15 */
662#define I40E_GLHMC_DBCQPART_MAX_INDEX 15
663#define I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT 0
664#define I40E_GLHMC_DBCQPART_PMDBCQBASE_MASK (0x3FFF << I40E_GLHMC_DBCQPART_PMDBCQBASE_SHIFT)
665#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT 16
666#define I40E_GLHMC_DBCQPART_PMDBCQSIZE_MASK (0x7FFF << I40E_GLHMC_DBCQPART_PMDBCQSIZE_SHIFT)
667#define I40E_GLHMC_DBQPPART(_i) (0x00138D80 + ((_i) * 4)) /* _i=0...15 */
668#define I40E_GLHMC_DBQPPART_MAX_INDEX 15
669#define I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT 0
670#define I40E_GLHMC_DBQPPART_PMDBQPBASE_MASK (0x3FFF << I40E_GLHMC_DBQPPART_PMDBQPBASE_SHIFT)
671#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT 16
672#define I40E_GLHMC_DBQPPART_PMDBQPSIZE_MASK (0x7FFF << I40E_GLHMC_DBQPPART_PMDBQPSIZE_SHIFT)
673#define I40E_GLHMC_FCOEDDPBASE(_i) (0x000C6600 + ((_i) * 4)) /* _i=0...15 */
674#define I40E_GLHMC_FCOEDDPBASE_MAX_INDEX 15
675#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT 0
676#define I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_MASK (0xFFFFFF << I40E_GLHMC_FCOEDDPBASE_FPMFCOEDDPBASE_SHIFT)
677#define I40E_GLHMC_FCOEDDPCNT(_i) (0x000C6700 + ((_i) * 4)) /* _i=0...15 */
678#define I40E_GLHMC_FCOEDDPCNT_MAX_INDEX 15
679#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT 0
680#define I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_MASK (0xFFFFF << I40E_GLHMC_FCOEDDPCNT_FPMFCOEDDPCNT_SHIFT)
681#define I40E_GLHMC_FCOEDDPOBJSZ 0x000C2010
682#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT 0
683#define I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_MASK (0xF << I40E_GLHMC_FCOEDDPOBJSZ_PMFCOEDDPOBJSZ_SHIFT)
684#define I40E_GLHMC_FCOEFBASE(_i) (0x000C6800 + ((_i) * 4)) /* _i=0...15 */
685#define I40E_GLHMC_FCOEFBASE_MAX_INDEX 15
686#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT 0
687#define I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_MASK (0xFFFFFF << I40E_GLHMC_FCOEFBASE_FPMFCOEFBASE_SHIFT)
688#define I40E_GLHMC_FCOEFCNT(_i) (0x000C6900 + ((_i) * 4)) /* _i=0...15 */
689#define I40E_GLHMC_FCOEFCNT_MAX_INDEX 15
690#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT 0
691#define I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_MASK (0x7FFFFF << I40E_GLHMC_FCOEFCNT_FPMFCOEFCNT_SHIFT)
692#define I40E_GLHMC_FCOEFMAX 0x000C20D0
693#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT 0
694#define I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK (0xFFFF << I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT)
695#define I40E_GLHMC_FCOEFOBJSZ 0x000C2018
696#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT 0
697#define I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_MASK (0xF << I40E_GLHMC_FCOEFOBJSZ_PMFCOEFOBJSZ_SHIFT)
698#define I40E_GLHMC_FCOEMAX 0x000C2014
699#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT 0
700#define I40E_GLHMC_FCOEMAX_PMFCOEMAX_MASK (0x1FFF << I40E_GLHMC_FCOEMAX_PMFCOEMAX_SHIFT)
701#define I40E_GLHMC_FSIAVBASE(_i) (0x000C5600 + ((_i) * 4)) /* _i=0...15 */
702#define I40E_GLHMC_FSIAVBASE_MAX_INDEX 15
703#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT 0
704#define I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_MASK (0xFFFFFF << I40E_GLHMC_FSIAVBASE_FPMFSIAVBASE_SHIFT)
705#define I40E_GLHMC_FSIAVCNT(_i) (0x000C5700 + ((_i) * 4)) /* _i=0...15 */
706#define I40E_GLHMC_FSIAVCNT_MAX_INDEX 15
707#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT 0
708#define I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_MASK (0x1FFFFFFF << I40E_GLHMC_FSIAVCNT_FPMFSIAVCNT_SHIFT)
709#define I40E_GLHMC_FSIAVCNT_RSVD_SHIFT 29
710#define I40E_GLHMC_FSIAVCNT_RSVD_MASK (0x7 << I40E_GLHMC_FSIAVCNT_RSVD_SHIFT)
711#define I40E_GLHMC_FSIAVMAX 0x000C2068
712#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT 0
713#define I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_MASK (0x1FFFF << I40E_GLHMC_FSIAVMAX_PMFSIAVMAX_SHIFT)
714#define I40E_GLHMC_FSIAVOBJSZ 0x000C2064
715#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT 0
716#define I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_MASK (0xF << I40E_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_SHIFT)
717#define I40E_GLHMC_FSIMCBASE(_i) (0x000C6000 + ((_i) * 4)) /* _i=0...15 */
718#define I40E_GLHMC_FSIMCBASE_MAX_INDEX 15
719#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT 0
720#define I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_MASK (0xFFFFFF << I40E_GLHMC_FSIMCBASE_FPMFSIMCBASE_SHIFT)
721#define I40E_GLHMC_FSIMCCNT(_i) (0x000C6100 + ((_i) * 4)) /* _i=0...15 */
722#define I40E_GLHMC_FSIMCCNT_MAX_INDEX 15
723#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT 0
724#define I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_MASK (0x1FFFFFFF << I40E_GLHMC_FSIMCCNT_FPMFSIMCSZ_SHIFT)
725#define I40E_GLHMC_FSIMCMAX 0x000C2060
726#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT 0
727#define I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_MASK (0x3FFF << I40E_GLHMC_FSIMCMAX_PMFSIMCMAX_SHIFT)
728#define I40E_GLHMC_FSIMCOBJSZ 0x000C205c
729#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT 0
730#define I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_MASK (0xF << I40E_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_SHIFT)
731#define I40E_GLHMC_LANQMAX 0x000C2008
732#define I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT 0
733#define I40E_GLHMC_LANQMAX_PMLANQMAX_MASK (0x7FF << I40E_GLHMC_LANQMAX_PMLANQMAX_SHIFT)
734#define I40E_GLHMC_LANRXBASE(_i) (0x000C6400 + ((_i) * 4)) /* _i=0...15 */
735#define I40E_GLHMC_LANRXBASE_MAX_INDEX 15
736#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT 0
737#define I40E_GLHMC_LANRXBASE_FPMLANRXBASE_MASK (0xFFFFFF << I40E_GLHMC_LANRXBASE_FPMLANRXBASE_SHIFT)
738#define I40E_GLHMC_LANRXCNT(_i) (0x000C6500 + ((_i) * 4)) /* _i=0...15 */
739#define I40E_GLHMC_LANRXCNT_MAX_INDEX 15
740#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT 0
741#define I40E_GLHMC_LANRXCNT_FPMLANRXCNT_MASK (0x7FF << I40E_GLHMC_LANRXCNT_FPMLANRXCNT_SHIFT)
742#define I40E_GLHMC_LANRXOBJSZ 0x000C200c
743#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT 0
744#define I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_MASK (0xF << I40E_GLHMC_LANRXOBJSZ_PMLANRXOBJSZ_SHIFT)
745#define I40E_GLHMC_LANTXBASE(_i) (0x000C6200 + ((_i) * 4)) /* _i=0...15 */
746#define I40E_GLHMC_LANTXBASE_MAX_INDEX 15
747#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT 0
748#define I40E_GLHMC_LANTXBASE_FPMLANTXBASE_MASK (0xFFFFFF << I40E_GLHMC_LANTXBASE_FPMLANTXBASE_SHIFT)
749#define I40E_GLHMC_LANTXBASE_RSVD_SHIFT 24
750#define I40E_GLHMC_LANTXBASE_RSVD_MASK (0xFF << I40E_GLHMC_LANTXBASE_RSVD_SHIFT)
751#define I40E_GLHMC_LANTXCNT(_i) (0x000C6300 + ((_i) * 4)) /* _i=0...15 */
752#define I40E_GLHMC_LANTXCNT_MAX_INDEX 15
753#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT 0
754#define I40E_GLHMC_LANTXCNT_FPMLANTXCNT_MASK (0x7FF << I40E_GLHMC_LANTXCNT_FPMLANTXCNT_SHIFT)
755#define I40E_GLHMC_LANTXOBJSZ 0x000C2004
756#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT 0
757#define I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_MASK (0xF << I40E_GLHMC_LANTXOBJSZ_PMLANTXOBJSZ_SHIFT)
758#define I40E_GLHMC_PEARPBASE(_i) (0x000C4800 + ((_i) * 4)) /* _i=0...15 */
759#define I40E_GLHMC_PEARPBASE_MAX_INDEX 15
760#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT 0
761#define I40E_GLHMC_PEARPBASE_FPMPEARPBASE_MASK (0xFFFFFF << I40E_GLHMC_PEARPBASE_FPMPEARPBASE_SHIFT)
762#define I40E_GLHMC_PEARPCNT(_i) (0x000C4900 + ((_i) * 4)) /* _i=0...15 */
763#define I40E_GLHMC_PEARPCNT_MAX_INDEX 15
764#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT 0
765#define I40E_GLHMC_PEARPCNT_FPMPEARPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEARPCNT_FPMPEARPCNT_SHIFT)
766#define I40E_GLHMC_PEARPMAX 0x000C2038
767#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT 0
768#define I40E_GLHMC_PEARPMAX_PMPEARPMAX_MASK (0x1FFFF << I40E_GLHMC_PEARPMAX_PMPEARPMAX_SHIFT)
769#define I40E_GLHMC_PEARPOBJSZ 0x000C2034
770#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT 0
771#define I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_MASK (0x7 << I40E_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_SHIFT)
772#define I40E_GLHMC_PECQBASE(_i) (0x000C4200 + ((_i) * 4)) /* _i=0...15 */
773#define I40E_GLHMC_PECQBASE_MAX_INDEX 15
774#define I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT 0
775#define I40E_GLHMC_PECQBASE_FPMPECQBASE_MASK (0xFFFFFF << I40E_GLHMC_PECQBASE_FPMPECQBASE_SHIFT)
776#define I40E_GLHMC_PECQCNT(_i) (0x000C4300 + ((_i) * 4)) /* _i=0...15 */
777#define I40E_GLHMC_PECQCNT_MAX_INDEX 15
778#define I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT 0
779#define I40E_GLHMC_PECQCNT_FPMPECQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PECQCNT_FPMPECQCNT_SHIFT)
780#define I40E_GLHMC_PECQOBJSZ 0x000C2020
781#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT 0
782#define I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_MASK (0xF << I40E_GLHMC_PECQOBJSZ_PMPECQOBJSZ_SHIFT)
783#define I40E_GLHMC_PEHTCNT(_i) (0x000C4700 + ((_i) * 4)) /* _i=0...15 */
784#define I40E_GLHMC_PEHTCNT_MAX_INDEX 15
785#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT 0
786#define I40E_GLHMC_PEHTCNT_FPMPEHTCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEHTCNT_FPMPEHTCNT_SHIFT)
787#define I40E_GLHMC_PEHTEBASE(_i) (0x000C4600 + ((_i) * 4)) /* _i=0...15 */
788#define I40E_GLHMC_PEHTEBASE_MAX_INDEX 15
789#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT 0
790#define I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_MASK (0xFFFFFF << I40E_GLHMC_PEHTEBASE_FPMPEHTEBASE_SHIFT)
791#define I40E_GLHMC_PEHTEOBJSZ 0x000C202c
792#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT 0
793#define I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_MASK (0xF << I40E_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_SHIFT)
794#define I40E_GLHMC_PEHTMAX 0x000C2030
795#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT 0
796#define I40E_GLHMC_PEHTMAX_PMPEHTMAX_MASK (0x1FFFFF << I40E_GLHMC_PEHTMAX_PMPEHTMAX_SHIFT)
797#define I40E_GLHMC_PEMRBASE(_i) (0x000C4c00 + ((_i) * 4)) /* _i=0...15 */
798#define I40E_GLHMC_PEMRBASE_MAX_INDEX 15
799#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT 0
800#define I40E_GLHMC_PEMRBASE_FPMPEMRBASE_MASK (0xFFFFFF << I40E_GLHMC_PEMRBASE_FPMPEMRBASE_SHIFT)
801#define I40E_GLHMC_PEMRCNT(_i) (0x000C4d00 + ((_i) * 4)) /* _i=0...15 */
802#define I40E_GLHMC_PEMRCNT_MAX_INDEX 15
803#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT 0
804#define I40E_GLHMC_PEMRCNT_FPMPEMRSZ_MASK (0x1FFFFFFF << I40E_GLHMC_PEMRCNT_FPMPEMRSZ_SHIFT)
805#define I40E_GLHMC_PEMRMAX 0x000C2040
806#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT 0
807#define I40E_GLHMC_PEMRMAX_PMPEMRMAX_MASK (0x7FFFFF << I40E_GLHMC_PEMRMAX_PMPEMRMAX_SHIFT)
808#define I40E_GLHMC_PEMROBJSZ 0x000C203c
809#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT 0
810#define I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_MASK (0xF << I40E_GLHMC_PEMROBJSZ_PMPEMROBJSZ_SHIFT)
811#define I40E_GLHMC_PEPBLBASE(_i) (0x000C5800 + ((_i) * 4)) /* _i=0...15 */
812#define I40E_GLHMC_PEPBLBASE_MAX_INDEX 15
813#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT 0
814#define I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEPBLBASE_FPMPEPBLBASE_SHIFT)
815#define I40E_GLHMC_PEPBLCNT(_i) (0x000C5900 + ((_i) * 4)) /* _i=0...15 */
816#define I40E_GLHMC_PEPBLCNT_MAX_INDEX 15
817#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT 0
818#define I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEPBLCNT_FPMPEPBLCNT_SHIFT)
819#define I40E_GLHMC_PEPBLMAX 0x000C206c
820#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT 0
821#define I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_MASK (0x1FFFFFFF << I40E_GLHMC_PEPBLMAX_PMPEPBLMAX_SHIFT)
822#define I40E_GLHMC_PEQ1BASE(_i) (0x000C5200 + ((_i) * 4)) /* _i=0...15 */
823#define I40E_GLHMC_PEQ1BASE_MAX_INDEX 15
824#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT 0
825#define I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_MASK (0xFFFFFF << I40E_GLHMC_PEQ1BASE_FPMPEQ1BASE_SHIFT)
826#define I40E_GLHMC_PEQ1CNT(_i) (0x000C5300 + ((_i) * 4)) /* _i=0...15 */
827#define I40E_GLHMC_PEQ1CNT_MAX_INDEX 15
828#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT 0
829#define I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQ1CNT_FPMPEQ1CNT_SHIFT)
830#define I40E_GLHMC_PEQ1FLBASE(_i) (0x000C5400 + ((_i) * 4)) /* _i=0...15 */
831#define I40E_GLHMC_PEQ1FLBASE_MAX_INDEX 15
832#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
833#define I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
834#define I40E_GLHMC_PEQ1FLCNT(_i) (0x000C5500 + ((_i) * 4)) /* _i=0...15 */
835#define I40E_GLHMC_PEQ1FLCNT_MAX_INDEX 15
836#define I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_SHIFT 0
837#define I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQ1FLCNT_FPMPEQ1FLCNT_SHIFT)
838#define I40E_GLHMC_PEQ1FLMAX 0x000C2058
839#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT 0
840#define I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_MASK (0x3FFFFF << I40E_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_SHIFT)
841#define I40E_GLHMC_PEQ1MAX 0x000C2054
842#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT 0
843#define I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_MASK (0x3FFFFFF << I40E_GLHMC_PEQ1MAX_PMPEQ1MAX_SHIFT)
844#define I40E_GLHMC_PEQ1OBJSZ 0x000C2050
845#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT 0
846#define I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_MASK (0xF << I40E_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_SHIFT)
847#define I40E_GLHMC_PEQPBASE(_i) (0x000C4000 + ((_i) * 4)) /* _i=0...15 */
848#define I40E_GLHMC_PEQPBASE_MAX_INDEX 15
849#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT 0
850#define I40E_GLHMC_PEQPBASE_FPMPEQPBASE_MASK (0xFFFFFF << I40E_GLHMC_PEQPBASE_FPMPEQPBASE_SHIFT)
851#define I40E_GLHMC_PEQPCNT(_i) (0x000C4100 + ((_i) * 4)) /* _i=0...15 */
852#define I40E_GLHMC_PEQPCNT_MAX_INDEX 15
853#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT 0
854#define I40E_GLHMC_PEQPCNT_FPMPEQPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEQPCNT_FPMPEQPCNT_SHIFT)
855#define I40E_GLHMC_PEQPOBJSZ 0x000C201c
856#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT 0
857#define I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_MASK (0xF << I40E_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_SHIFT)
858#define I40E_GLHMC_PESRQBASE(_i) (0x000C4400 + ((_i) * 4)) /* _i=0...15 */
859#define I40E_GLHMC_PESRQBASE_MAX_INDEX 15
860#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT 0
861#define I40E_GLHMC_PESRQBASE_FPMPESRQBASE_MASK (0xFFFFFF << I40E_GLHMC_PESRQBASE_FPMPESRQBASE_SHIFT)
862#define I40E_GLHMC_PESRQCNT(_i) (0x000C4500 + ((_i) * 4)) /* _i=0...15 */
863#define I40E_GLHMC_PESRQCNT_MAX_INDEX 15
864#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT 0
865#define I40E_GLHMC_PESRQCNT_FPMPESRQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PESRQCNT_FPMPESRQCNT_SHIFT)
866#define I40E_GLHMC_PESRQMAX 0x000C2028
867#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT 0
868#define I40E_GLHMC_PESRQMAX_PMPESRQMAX_MASK (0xFFFF << I40E_GLHMC_PESRQMAX_PMPESRQMAX_SHIFT)
869#define I40E_GLHMC_PESRQOBJSZ 0x000C2024
870#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT 0
871#define I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_MASK (0xF << I40E_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_SHIFT)
872#define I40E_GLHMC_PESRQOBJSZ_RSVD_SHIFT 4
873#define I40E_GLHMC_PESRQOBJSZ_RSVD_MASK (0xFFFFFFF << I40E_GLHMC_PESRQOBJSZ_RSVD_SHIFT)
874#define I40E_GLHMC_PETIMERBASE(_i) (0x000C5A00 + ((_i) * 4)) /* _i=0...15 */
875#define I40E_GLHMC_PETIMERBASE_MAX_INDEX 15
876#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT 0
877#define I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_MASK (0xFFFFFF << I40E_GLHMC_PETIMERBASE_FPMPETIMERBASE_SHIFT)
878#define I40E_GLHMC_PETIMERCNT(_i) (0x000C5B00 + ((_i) * 4)) /* _i=0...15 */
879#define I40E_GLHMC_PETIMERCNT_MAX_INDEX 15
880#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT 0
881#define I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PETIMERCNT_FPMPETIMERCNT_SHIFT)
882#define I40E_GLHMC_PETIMERMAX 0x000C2084
883#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT 0
884#define I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_MASK (0x1FFFFFFF << I40E_GLHMC_PETIMERMAX_PMPETIMERMAX_SHIFT)
885#define I40E_GLHMC_PETIMEROBJSZ 0x000C2080
886#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT 0
887#define I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_MASK (0xF << I40E_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_SHIFT)
888#define I40E_GLHMC_PEXFBASE(_i) (0x000C4e00 + ((_i) * 4)) /* _i=0...15 */
889#define I40E_GLHMC_PEXFBASE_MAX_INDEX 15
890#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT 0
891#define I40E_GLHMC_PEXFBASE_FPMPEXFBASE_MASK (0xFFFFFF << I40E_GLHMC_PEXFBASE_FPMPEXFBASE_SHIFT)
892#define I40E_GLHMC_PEXFCNT(_i) (0x000C4f00 + ((_i) * 4)) /* _i=0...15 */
893#define I40E_GLHMC_PEXFCNT_MAX_INDEX 15
894#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT 0
895#define I40E_GLHMC_PEXFCNT_FPMPEXFCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEXFCNT_FPMPEXFCNT_SHIFT)
896#define I40E_GLHMC_PEXFFLBASE(_i) (0x000C5000 + ((_i) * 4)) /* _i=0...15 */
897#define I40E_GLHMC_PEXFFLBASE_MAX_INDEX 15
898#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
899#define I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_MASK (0xFFFFFF << I40E_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_SHIFT)
900#define I40E_GLHMC_PEXFFLCNT(_i) (0x000C5100 + ((_i) * 4)) /* _i=0...15 */
901#define I40E_GLHMC_PEXFFLCNT_MAX_INDEX 15
902#define I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_SHIFT 0
903#define I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_PEXFFLCNT_FPMPEXFFLCNT_SHIFT)
904#define I40E_GLHMC_PEXFFLMAX 0x000C204c
905#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT 0
906#define I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_MASK (0x3FFFFF << I40E_GLHMC_PEXFFLMAX_PMPEXFFLMAX_SHIFT)
907#define I40E_GLHMC_PEXFMAX 0x000C2048
908#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT 0
909#define I40E_GLHMC_PEXFMAX_PMPEXFMAX_MASK (0x3FFFFFF << I40E_GLHMC_PEXFMAX_PMPEXFMAX_SHIFT)
910#define I40E_GLHMC_PEXFOBJSZ 0x000C2044
911#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT 0
912#define I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_MASK (0xF << I40E_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_SHIFT)
913#define I40E_GLHMC_PEXFOBJSZ_RSVD_SHIFT 4
914#define I40E_GLHMC_PEXFOBJSZ_RSVD_MASK (0xFFFFFFF << I40E_GLHMC_PEXFOBJSZ_RSVD_SHIFT)
915#define I40E_GLHMC_PFASSIGN(_i) (0x000C0c00 + ((_i) * 4)) /* _i=0...15 */
916#define I40E_GLHMC_PFASSIGN_MAX_INDEX 15
917#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT 0
918#define I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_MASK (0xF << I40E_GLHMC_PFASSIGN_PMFCNPFASSIGN_SHIFT)
919#define I40E_GLHMC_SDPART(_i) (0x000C0800 + ((_i) * 4)) /* _i=0...15 */
920#define I40E_GLHMC_SDPART_MAX_INDEX 15
921#define I40E_GLHMC_SDPART_PMSDBASE_SHIFT 0
922#define I40E_GLHMC_SDPART_PMSDBASE_MASK (0xFFF << I40E_GLHMC_SDPART_PMSDBASE_SHIFT)
923#define I40E_GLHMC_SDPART_PMSDSIZE_SHIFT 16
924#define I40E_GLHMC_SDPART_PMSDSIZE_MASK (0x1FFF << I40E_GLHMC_SDPART_PMSDSIZE_SHIFT)
925#define I40E_GLHMC_VFAPBVTINUSEBASE(_i) (0x000Cca00 + ((_i) * 4))
926#define I40E_GLHMC_VFAPBVTINUSEBASE_MAX_INDEX 31
927#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT 0
928#define I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_MASK (0xFFFFFF << I40E_GLHMC_VFAPBVTINUSEBASE_FPMAPBINUSEBASE_SHIFT)
929#define I40E_GLHMC_VFCEQPART(_i) (0x00132240 + ((_i) * 4)) /* _i=0...31 */
930#define I40E_GLHMC_VFCEQPART_MAX_INDEX 31
931#define I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT 0
932#define I40E_GLHMC_VFCEQPART_PMCEQBASE_MASK (0xFF << I40E_GLHMC_VFCEQPART_PMCEQBASE_SHIFT)
933#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT 16
934#define I40E_GLHMC_VFCEQPART_PMCEQSIZE_MASK (0x1FF << I40E_GLHMC_VFCEQPART_PMCEQSIZE_SHIFT)
935#define I40E_GLHMC_VFDBCQPART(_i) (0x00132140 + ((_i) * 4)) /* _i=0...31 */
936#define I40E_GLHMC_VFDBCQPART_MAX_INDEX 31
937#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT 0
938#define I40E_GLHMC_VFDBCQPART_PMDBCQBASE_MASK (0x3FFF << I40E_GLHMC_VFDBCQPART_PMDBCQBASE_SHIFT)
939#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT 16
940#define I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_MASK (0x7FFF << I40E_GLHMC_VFDBCQPART_PMDBCQSIZE_SHIFT)
941#define I40E_GLHMC_VFDBQPPART(_i) (0x00138E00 + ((_i) * 4)) /* _i=0...31 */
942#define I40E_GLHMC_VFDBQPPART_MAX_INDEX 31
943#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT 0
944#define I40E_GLHMC_VFDBQPPART_PMDBQPBASE_MASK (0x3FFF << I40E_GLHMC_VFDBQPPART_PMDBQPBASE_SHIFT)
945#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT 16
946#define I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_MASK (0x7FFF << I40E_GLHMC_VFDBQPPART_PMDBQPSIZE_SHIFT)
947#define I40E_GLHMC_VFFSIAVBASE(_i) (0x000Cd600 + ((_i) * 4)) /* _i=0...31 */
948#define I40E_GLHMC_VFFSIAVBASE_MAX_INDEX 31
949#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT 0
950#define I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_MASK (0xFFFFFF << I40E_GLHMC_VFFSIAVBASE_FPMFSIAVBASE_SHIFT)
951#define I40E_GLHMC_VFFSIAVCNT(_i) (0x000Cd700 + ((_i) * 4)) /* _i=0...31 */
952#define I40E_GLHMC_VFFSIAVCNT_MAX_INDEX 31
953#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT 0
954#define I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFFSIAVCNT_FPMFSIAVCNT_SHIFT)
955#define I40E_GLHMC_VFFSIAVCNT_RSVD_SHIFT 29
956#define I40E_GLHMC_VFFSIAVCNT_RSVD_MASK (0x7 << I40E_GLHMC_VFFSIAVCNT_RSVD_SHIFT)
957#define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */
958#define I40E_GLHMC_VFPDINV_MAX_INDEX 31
959#define I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT 0
960#define I40E_GLHMC_VFPDINV_PMSDIDX_MASK (0xFFF << I40E_GLHMC_VFPDINV_PMSDIDX_SHIFT)
961#define I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT 16
962#define I40E_GLHMC_VFPDINV_PMPDIDX_MASK (0x1FF << I40E_GLHMC_VFPDINV_PMPDIDX_SHIFT)
963#define I40E_GLHMC_VFPEARPBASE(_i) (0x000Cc800 + ((_i) * 4)) /* _i=0...31 */
964#define I40E_GLHMC_VFPEARPBASE_MAX_INDEX 31
965#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT 0
966#define I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEARPBASE_FPMPEARPBASE_SHIFT)
967#define I40E_GLHMC_VFPEARPCNT(_i) (0x000Cc900 + ((_i) * 4)) /* _i=0...31 */
968#define I40E_GLHMC_VFPEARPCNT_MAX_INDEX 31
969#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT 0
970#define I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEARPCNT_FPMPEARPCNT_SHIFT)
971#define I40E_GLHMC_VFPECQBASE(_i) (0x000Cc200 + ((_i) * 4)) /* _i=0...31 */
972#define I40E_GLHMC_VFPECQBASE_MAX_INDEX 31
973#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT 0
974#define I40E_GLHMC_VFPECQBASE_FPMPECQBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPECQBASE_FPMPECQBASE_SHIFT)
975#define I40E_GLHMC_VFPECQCNT(_i) (0x000Cc300 + ((_i) * 4)) /* _i=0...31 */
976#define I40E_GLHMC_VFPECQCNT_MAX_INDEX 31
977#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT 0
978#define I40E_GLHMC_VFPECQCNT_FPMPECQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPECQCNT_FPMPECQCNT_SHIFT)
979#define I40E_GLHMC_VFPEHTCNT(_i) (0x000Cc700 + ((_i) * 4)) /* _i=0...31 */
980#define I40E_GLHMC_VFPEHTCNT_MAX_INDEX 31
981#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT 0
982#define I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEHTCNT_FPMPEHTCNT_SHIFT)
983#define I40E_GLHMC_VFPEHTEBASE(_i) (0x000Cc600 + ((_i) * 4)) /* _i=0...31 */
984#define I40E_GLHMC_VFPEHTEBASE_MAX_INDEX 31
985#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT 0
986#define I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEHTEBASE_FPMPEHTEBASE_SHIFT)
987#define I40E_GLHMC_VFPEMRBASE(_i) (0x000Ccc00 + ((_i) * 4)) /* _i=0...31 */
988#define I40E_GLHMC_VFPEMRBASE_MAX_INDEX 31
989#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT 0
990#define I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEMRBASE_FPMPEMRBASE_SHIFT)
991#define I40E_GLHMC_VFPEMRCNT(_i) (0x000Ccd00 + ((_i) * 4)) /* _i=0...31 */
992#define I40E_GLHMC_VFPEMRCNT_MAX_INDEX 31
993#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT 0
994#define I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEMRCNT_FPMPEMRSZ_SHIFT)
995#define I40E_GLHMC_VFPEPBLBASE(_i) (0x000Cd800 + ((_i) * 4)) /* _i=0...31 */
996#define I40E_GLHMC_VFPEPBLBASE_MAX_INDEX 31
997#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT 0
998#define I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEPBLBASE_FPMPEPBLBASE_SHIFT)
999#define I40E_GLHMC_VFPEPBLCNT(_i) (0x000Cd900 + ((_i) * 4)) /* _i=0...31 */
1000#define I40E_GLHMC_VFPEPBLCNT_MAX_INDEX 31
1001#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT 0
1002#define I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEPBLCNT_FPMPEPBLCNT_SHIFT)
1003#define I40E_GLHMC_VFPEQ1BASE(_i) (0x000Cd200 + ((_i) * 4)) /* _i=0...31 */
1004#define I40E_GLHMC_VFPEQ1BASE_MAX_INDEX 31
1005#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT 0
1006#define I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQ1BASE_FPMPEQ1BASE_SHIFT)
1007#define I40E_GLHMC_VFPEQ1CNT(_i) (0x000Cd300 + ((_i) * 4)) /* _i=0...31 */
1008#define I40E_GLHMC_VFPEQ1CNT_MAX_INDEX 31
1009#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT 0
1010#define I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQ1CNT_FPMPEQ1CNT_SHIFT)
1011#define I40E_GLHMC_VFPEQ1FLBASE(_i) (0x000Cd400 + ((_i) * 4)) /* _i=0...31 */
1012#define I40E_GLHMC_VFPEQ1FLBASE_MAX_INDEX 31
1013#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT 0
1014#define I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQ1FLBASE_FPMPEQ1FLBASE_SHIFT)
1015#define I40E_GLHMC_VFPEQ1FLCNT(_i) (0x000Cd500 + ((_i) * 4)) /* _i=0...31 */
1016#define I40E_GLHMC_VFPEQ1FLCNT_MAX_INDEX 31
1017#define I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_SHIFT 0
1018#define I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQ1FLCNT_FPMPEQ1FLCNT_SHIFT)
1019#define I40E_GLHMC_VFPEQPBASE(_i) (0x000Cc000 + ((_i) * 4)) /* _i=0...31 */
1020#define I40E_GLHMC_VFPEQPBASE_MAX_INDEX 31
1021#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT 0
1022#define I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEQPBASE_FPMPEQPBASE_SHIFT)
1023#define I40E_GLHMC_VFPEQPCNT(_i) (0x000Cc100 + ((_i) * 4)) /* _i=0...31 */
1024#define I40E_GLHMC_VFPEQPCNT_MAX_INDEX 31
1025#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT 0
1026#define I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEQPCNT_FPMPEQPCNT_SHIFT)
1027#define I40E_GLHMC_VFPESRQBASE(_i) (0x000Cc400 + ((_i) * 4)) /* _i=0...31 */
1028#define I40E_GLHMC_VFPESRQBASE_MAX_INDEX 31
1029#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT 0
1030#define I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPESRQBASE_FPMPESRQBASE_SHIFT)
1031#define I40E_GLHMC_VFPESRQCNT(_i) (0x000Cc500 + ((_i) * 4)) /* _i=0...31 */
1032#define I40E_GLHMC_VFPESRQCNT_MAX_INDEX 31
1033#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT 0
1034#define I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPESRQCNT_FPMPESRQCNT_SHIFT)
1035#define I40E_GLHMC_VFPETIMERBASE(_i) (0x000CDA00 + ((_i) * 4)) /* _i=0...31 */
1036#define I40E_GLHMC_VFPETIMERBASE_MAX_INDEX 31
1037#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT 0
1038#define I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPETIMERBASE_FPMPETIMERBASE_SHIFT)
1039#define I40E_GLHMC_VFPETIMERCNT(_i) (0x000CDB00 + ((_i) * 4)) /* _i=0...31 */
1040#define I40E_GLHMC_VFPETIMERCNT_MAX_INDEX 31
1041#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT 0
1042#define I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPETIMERCNT_FPMPETIMERCNT_SHIFT)
1043#define I40E_GLHMC_VFPEXFBASE(_i) (0x000Cce00 + ((_i) * 4)) /* _i=0...31 */
1044#define I40E_GLHMC_VFPEXFBASE_MAX_INDEX 31
1045#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT 0
1046#define I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEXFBASE_FPMPEXFBASE_SHIFT)
1047#define I40E_GLHMC_VFPEXFCNT(_i) (0x000Ccf00 + ((_i) * 4)) /* _i=0...31 */
1048#define I40E_GLHMC_VFPEXFCNT_MAX_INDEX 31
1049#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT 0
1050#define I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEXFCNT_FPMPEXFCNT_SHIFT)
1051#define I40E_GLHMC_VFPEXFFLBASE(_i) (0x000Cd000 + ((_i) * 4)) /* _i=0...31 */
1052#define I40E_GLHMC_VFPEXFFLBASE_MAX_INDEX 31
1053#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT 0
1054#define I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_MASK (0xFFFFFF << I40E_GLHMC_VFPEXFFLBASE_FPMPEXFFLBASE_SHIFT)
1055#define I40E_GLHMC_VFPEXFFLCNT(_i) (0x000Cd100 + ((_i) * 4)) /* _i=0...31 */
1056#define I40E_GLHMC_VFPEXFFLCNT_MAX_INDEX 31
1057#define I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_SHIFT 0
1058#define I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_MASK (0x1FFFFFFF << I40E_GLHMC_VFPEXFFLCNT_FPMPEXFFLCNT_SHIFT)
1059#define I40E_GLHMC_VFSDPART(_i) (0x000C8800 + ((_i) * 4)) /* _i=0...31 */
1060#define I40E_GLHMC_VFSDPART_MAX_INDEX 31
1061#define I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT 0
1062#define I40E_GLHMC_VFSDPART_PMSDBASE_MASK (0xFFF << I40E_GLHMC_VFSDPART_PMSDBASE_SHIFT)
1063#define I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT 16
1064#define I40E_GLHMC_VFSDPART_PMSDSIZE_MASK (0x1FFF << I40E_GLHMC_VFSDPART_PMSDSIZE_SHIFT)
1065#define I40E_PFHMC_ERRORDATA 0x000C0500
1066#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT 0
1067#define I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_MASK (0x3FFFFFFF << I40E_PFHMC_ERRORDATA_HMC_ERROR_DATA_SHIFT)
1068#define I40E_PFHMC_ERRORINFO 0x000C0400
1069#define I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT 0
1070#define I40E_PFHMC_ERRORINFO_PMF_INDEX_MASK (0x1F << I40E_PFHMC_ERRORINFO_PMF_INDEX_SHIFT)
1071#define I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT 7
1072#define I40E_PFHMC_ERRORINFO_PMF_ISVF_MASK (0x1 << I40E_PFHMC_ERRORINFO_PMF_ISVF_SHIFT)
1073#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT 8
1074#define I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_MASK (0xF << I40E_PFHMC_ERRORINFO_HMC_ERROR_TYPE_SHIFT)
1075#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT 16
1076#define I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_MASK (0x1F << I40E_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_SHIFT)
1077#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT 31
1078#define I40E_PFHMC_ERRORINFO_ERROR_DETECTED_MASK (0x1 << I40E_PFHMC_ERRORINFO_ERROR_DETECTED_SHIFT)
1079#define I40E_PFHMC_PDINV 0x000C0300
1080#define I40E_PFHMC_PDINV_PMSDIDX_SHIFT 0
1081#define I40E_PFHMC_PDINV_PMSDIDX_MASK (0xFFF << I40E_PFHMC_PDINV_PMSDIDX_SHIFT)
1082#define I40E_PFHMC_PDINV_PMPDIDX_SHIFT 16
1083#define I40E_PFHMC_PDINV_PMPDIDX_MASK (0x1FF << I40E_PFHMC_PDINV_PMPDIDX_SHIFT)
1084#define I40E_PFHMC_SDCMD 0x000C0000
1085#define I40E_PFHMC_SDCMD_PMSDIDX_SHIFT 0
1086#define I40E_PFHMC_SDCMD_PMSDIDX_MASK (0xFFF << I40E_PFHMC_SDCMD_PMSDIDX_SHIFT)
1087#define I40E_PFHMC_SDCMD_PMSDWR_SHIFT 31
1088#define I40E_PFHMC_SDCMD_PMSDWR_MASK (0x1 << I40E_PFHMC_SDCMD_PMSDWR_SHIFT)
1089#define I40E_PFHMC_SDDATAHIGH 0x000C0200
1090#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT 0
1091#define I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_MASK (0xFFFFFFFF << I40E_PFHMC_SDDATAHIGH_PMSDDATAHIGH_SHIFT)
1092#define I40E_PFHMC_SDDATALOW 0x000C0100
1093#define I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT 0
1094#define I40E_PFHMC_SDDATALOW_PMSDVALID_MASK (0x1 << I40E_PFHMC_SDDATALOW_PMSDVALID_SHIFT)
1095#define I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT 1
1096#define I40E_PFHMC_SDDATALOW_PMSDTYPE_MASK (0x1 << I40E_PFHMC_SDDATALOW_PMSDTYPE_SHIFT)
1097#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT 2
1098#define I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_MASK (0x3FF << I40E_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT)
1099#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT 12
1100#define I40E_PFHMC_SDDATALOW_PMSDDATALOW_MASK (0xFFFFF << I40E_PFHMC_SDDATALOW_PMSDDATALOW_SHIFT)
1101#define I40E_GL_UFUSE 0x00094008
1102#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT 1
1103#define I40E_GL_UFUSE_FOUR_PORT_ENABLE_MASK (0x1 << I40E_GL_UFUSE_FOUR_PORT_ENABLE_SHIFT)
1104#define I40E_GL_UFUSE_NIC_ID_SHIFT 2
1105#define I40E_GL_UFUSE_NIC_ID_MASK (0x1 << I40E_GL_UFUSE_NIC_ID_SHIFT)
1106#define I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT 10
1107#define I40E_GL_UFUSE_ULT_LOCKOUT_MASK (0x1 << I40E_GL_UFUSE_ULT_LOCKOUT_SHIFT)
1108#define I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT 11
1109#define I40E_GL_UFUSE_CLS_LOCKOUT_MASK (0x1 << I40E_GL_UFUSE_CLS_LOCKOUT_SHIFT)
1110#define I40E_EMPINT_GPIO_ENA 0x00088188
1111#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT 0
1112#define I40E_EMPINT_GPIO_ENA_GPIO0_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO0_ENA_SHIFT)
1113#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT 1
1114#define I40E_EMPINT_GPIO_ENA_GPIO1_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO1_ENA_SHIFT)
1115#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT 2
1116#define I40E_EMPINT_GPIO_ENA_GPIO2_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO2_ENA_SHIFT)
1117#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT 3
1118#define I40E_EMPINT_GPIO_ENA_GPIO3_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO3_ENA_SHIFT)
1119#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT 4
1120#define I40E_EMPINT_GPIO_ENA_GPIO4_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO4_ENA_SHIFT)
1121#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT 5
1122#define I40E_EMPINT_GPIO_ENA_GPIO5_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO5_ENA_SHIFT)
1123#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT 6
1124#define I40E_EMPINT_GPIO_ENA_GPIO6_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO6_ENA_SHIFT)
1125#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT 7
1126#define I40E_EMPINT_GPIO_ENA_GPIO7_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO7_ENA_SHIFT)
1127#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT 8
1128#define I40E_EMPINT_GPIO_ENA_GPIO8_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO8_ENA_SHIFT)
1129#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT 9
1130#define I40E_EMPINT_GPIO_ENA_GPIO9_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO9_ENA_SHIFT)
1131#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT 10
1132#define I40E_EMPINT_GPIO_ENA_GPIO10_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO10_ENA_SHIFT)
1133#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT 11
1134#define I40E_EMPINT_GPIO_ENA_GPIO11_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO11_ENA_SHIFT)
1135#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT 12
1136#define I40E_EMPINT_GPIO_ENA_GPIO12_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO12_ENA_SHIFT)
1137#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT 13
1138#define I40E_EMPINT_GPIO_ENA_GPIO13_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO13_ENA_SHIFT)
1139#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT 14
1140#define I40E_EMPINT_GPIO_ENA_GPIO14_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO14_ENA_SHIFT)
1141#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT 15
1142#define I40E_EMPINT_GPIO_ENA_GPIO15_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO15_ENA_SHIFT)
1143#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT 16
1144#define I40E_EMPINT_GPIO_ENA_GPIO16_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO16_ENA_SHIFT)
1145#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT 17
1146#define I40E_EMPINT_GPIO_ENA_GPIO17_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO17_ENA_SHIFT)
1147#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT 18
1148#define I40E_EMPINT_GPIO_ENA_GPIO18_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO18_ENA_SHIFT)
1149#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT 19
1150#define I40E_EMPINT_GPIO_ENA_GPIO19_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO19_ENA_SHIFT)
1151#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT 20
1152#define I40E_EMPINT_GPIO_ENA_GPIO20_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO20_ENA_SHIFT)
1153#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT 21
1154#define I40E_EMPINT_GPIO_ENA_GPIO21_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO21_ENA_SHIFT)
1155#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT 22
1156#define I40E_EMPINT_GPIO_ENA_GPIO22_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO22_ENA_SHIFT)
1157#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT 23
1158#define I40E_EMPINT_GPIO_ENA_GPIO23_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO23_ENA_SHIFT)
1159#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT 24
1160#define I40E_EMPINT_GPIO_ENA_GPIO24_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO24_ENA_SHIFT)
1161#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT 25
1162#define I40E_EMPINT_GPIO_ENA_GPIO25_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO25_ENA_SHIFT)
1163#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT 26
1164#define I40E_EMPINT_GPIO_ENA_GPIO26_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO26_ENA_SHIFT)
1165#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT 27
1166#define I40E_EMPINT_GPIO_ENA_GPIO27_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO27_ENA_SHIFT)
1167#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT 28
1168#define I40E_EMPINT_GPIO_ENA_GPIO28_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO28_ENA_SHIFT)
1169#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
1170#define I40E_EMPINT_GPIO_ENA_GPIO29_ENA_MASK (0x1 << I40E_EMPINT_GPIO_ENA_GPIO29_ENA_SHIFT)
1171#define I40E_PFGEN_PORTMDIO_NUM 0x0003F100
1172#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT 0
1173#define I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_MASK (0x3 << I40E_PFGEN_PORTMDIO_NUM_PORT_NUM_SHIFT)
1174#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT 4
1175#define I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK (0x1 << I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_SHIFT)
1176#define I40E_PFINT_AEQCTL 0x00038700
1177#define I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT 0
1178#define I40E_PFINT_AEQCTL_MSIX_INDX_MASK (0xFF << I40E_PFINT_AEQCTL_MSIX_INDX_SHIFT)
1179#define I40E_PFINT_AEQCTL_ITR_INDX_SHIFT 11
1180#define I40E_PFINT_AEQCTL_ITR_INDX_MASK (0x3 << I40E_PFINT_AEQCTL_ITR_INDX_SHIFT)
1181#define I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT 13
1182#define I40E_PFINT_AEQCTL_MSIX0_INDX_MASK (0x7 << I40E_PFINT_AEQCTL_MSIX0_INDX_SHIFT)
1183#define I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT 30
1184#define I40E_PFINT_AEQCTL_CAUSE_ENA_MASK (0x1 << I40E_PFINT_AEQCTL_CAUSE_ENA_SHIFT)
1185#define I40E_PFINT_AEQCTL_INTEVENT_SHIFT 31
1186#define I40E_PFINT_AEQCTL_INTEVENT_MASK (0x1 << I40E_PFINT_AEQCTL_INTEVENT_SHIFT)
1187#define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */
1188#define I40E_PFINT_CEQCTL_MAX_INDEX 511
1189#define I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT 0
1190#define I40E_PFINT_CEQCTL_MSIX_INDX_MASK (0xFF << I40E_PFINT_CEQCTL_MSIX_INDX_SHIFT)
1191#define I40E_PFINT_CEQCTL_ITR_INDX_SHIFT 11
1192#define I40E_PFINT_CEQCTL_ITR_INDX_MASK (0x3 << I40E_PFINT_CEQCTL_ITR_INDX_SHIFT)
1193#define I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT 13
1194#define I40E_PFINT_CEQCTL_MSIX0_INDX_MASK (0x7 << I40E_PFINT_CEQCTL_MSIX0_INDX_SHIFT)
1195#define I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT 16
1196#define I40E_PFINT_CEQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_PFINT_CEQCTL_NEXTQ_INDX_SHIFT)
1197#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT 27
1198#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_PFINT_CEQCTL_NEXTQ_TYPE_SHIFT)
1199#define I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT 30
1200#define I40E_PFINT_CEQCTL_CAUSE_ENA_MASK (0x1 << I40E_PFINT_CEQCTL_CAUSE_ENA_SHIFT)
1201#define I40E_PFINT_CEQCTL_INTEVENT_SHIFT 31
1202#define I40E_PFINT_CEQCTL_INTEVENT_MASK (0x1 << I40E_PFINT_CEQCTL_INTEVENT_SHIFT)
1203#define I40E_PFINT_DYN_CTL0 0x00038480
1204#define I40E_PFINT_DYN_CTL0_INTENA_SHIFT 0
1205#define I40E_PFINT_DYN_CTL0_INTENA_MASK (0x1 << I40E_PFINT_DYN_CTL0_INTENA_SHIFT)
1206#define I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT 1
1207#define I40E_PFINT_DYN_CTL0_CLEARPBA_MASK (0x1 << I40E_PFINT_DYN_CTL0_CLEARPBA_SHIFT)
1208#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2
1209#define I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK (0x1 << I40E_PFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
1210#define I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT 3
1211#define I40E_PFINT_DYN_CTL0_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT)
1212#define I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT 5
1213#define I40E_PFINT_DYN_CTL0_INTERVAL_MASK (0xFFF << I40E_PFINT_DYN_CTL0_INTERVAL_SHIFT)
1214#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24
1215#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK (0x1 << I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
1216#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25
1217#define I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
1218#define I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT 31
1219#define I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK (0x1 << I40E_PFINT_DYN_CTL0_INTENA_MSK_SHIFT)
1220#define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */
1221#define I40E_PFINT_DYN_CTLN_MAX_INDEX 511
1222#define I40E_PFINT_DYN_CTLN_INTENA_SHIFT 0
1223#define I40E_PFINT_DYN_CTLN_INTENA_MASK (0x1 << I40E_PFINT_DYN_CTLN_INTENA_SHIFT)
1224#define I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT 1
1225#define I40E_PFINT_DYN_CTLN_CLEARPBA_MASK (0x1 << I40E_PFINT_DYN_CTLN_CLEARPBA_SHIFT)
1226#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2
1227#define I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK (0x1 << I40E_PFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
1228#define I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT 3
1229#define I40E_PFINT_DYN_CTLN_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT)
1230#define I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT 5
1231#define I40E_PFINT_DYN_CTLN_INTERVAL_MASK (0xFFF << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT)
1232#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24
1233#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK (0x1 << I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
1234#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25
1235#define I40E_PFINT_DYN_CTLN_SW_ITR_INDX_MASK (0x3 << I40E_PFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
1236#define I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT 31
1237#define I40E_PFINT_DYN_CTLN_INTENA_MSK_MASK (0x1 << I40E_PFINT_DYN_CTLN_INTENA_MSK_SHIFT)
1238#define I40E_PFINT_GPIO_ENA 0x00088080
1239#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT 0
1240#define I40E_PFINT_GPIO_ENA_GPIO0_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO0_ENA_SHIFT)
1241#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT 1
1242#define I40E_PFINT_GPIO_ENA_GPIO1_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO1_ENA_SHIFT)
1243#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT 2
1244#define I40E_PFINT_GPIO_ENA_GPIO2_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO2_ENA_SHIFT)
1245#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT 3
1246#define I40E_PFINT_GPIO_ENA_GPIO3_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO3_ENA_SHIFT)
1247#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT 4
1248#define I40E_PFINT_GPIO_ENA_GPIO4_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO4_ENA_SHIFT)
1249#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT 5
1250#define I40E_PFINT_GPIO_ENA_GPIO5_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO5_ENA_SHIFT)
1251#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT 6
1252#define I40E_PFINT_GPIO_ENA_GPIO6_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO6_ENA_SHIFT)
1253#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT 7
1254#define I40E_PFINT_GPIO_ENA_GPIO7_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO7_ENA_SHIFT)
1255#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT 8
1256#define I40E_PFINT_GPIO_ENA_GPIO8_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO8_ENA_SHIFT)
1257#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT 9
1258#define I40E_PFINT_GPIO_ENA_GPIO9_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO9_ENA_SHIFT)
1259#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT 10
1260#define I40E_PFINT_GPIO_ENA_GPIO10_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO10_ENA_SHIFT)
1261#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT 11
1262#define I40E_PFINT_GPIO_ENA_GPIO11_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO11_ENA_SHIFT)
1263#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT 12
1264#define I40E_PFINT_GPIO_ENA_GPIO12_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO12_ENA_SHIFT)
1265#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT 13
1266#define I40E_PFINT_GPIO_ENA_GPIO13_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO13_ENA_SHIFT)
1267#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT 14
1268#define I40E_PFINT_GPIO_ENA_GPIO14_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO14_ENA_SHIFT)
1269#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT 15
1270#define I40E_PFINT_GPIO_ENA_GPIO15_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO15_ENA_SHIFT)
1271#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT 16
1272#define I40E_PFINT_GPIO_ENA_GPIO16_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO16_ENA_SHIFT)
1273#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT 17
1274#define I40E_PFINT_GPIO_ENA_GPIO17_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO17_ENA_SHIFT)
1275#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT 18
1276#define I40E_PFINT_GPIO_ENA_GPIO18_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO18_ENA_SHIFT)
1277#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT 19
1278#define I40E_PFINT_GPIO_ENA_GPIO19_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO19_ENA_SHIFT)
1279#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT 20
1280#define I40E_PFINT_GPIO_ENA_GPIO20_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO20_ENA_SHIFT)
1281#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT 21
1282#define I40E_PFINT_GPIO_ENA_GPIO21_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO21_ENA_SHIFT)
1283#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT 22
1284#define I40E_PFINT_GPIO_ENA_GPIO22_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO22_ENA_SHIFT)
1285#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT 23
1286#define I40E_PFINT_GPIO_ENA_GPIO23_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO23_ENA_SHIFT)
1287#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT 24
1288#define I40E_PFINT_GPIO_ENA_GPIO24_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO24_ENA_SHIFT)
1289#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT 25
1290#define I40E_PFINT_GPIO_ENA_GPIO25_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO25_ENA_SHIFT)
1291#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT 26
1292#define I40E_PFINT_GPIO_ENA_GPIO26_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO26_ENA_SHIFT)
1293#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT 27
1294#define I40E_PFINT_GPIO_ENA_GPIO27_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO27_ENA_SHIFT)
1295#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT 28
1296#define I40E_PFINT_GPIO_ENA_GPIO28_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO28_ENA_SHIFT)
1297#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT 29
1298#define I40E_PFINT_GPIO_ENA_GPIO29_ENA_MASK (0x1 << I40E_PFINT_GPIO_ENA_GPIO29_ENA_SHIFT)
1299#define I40E_PFINT_ICR0 0x00038780
1300#define I40E_PFINT_ICR0_INTEVENT_SHIFT 0
1301#define I40E_PFINT_ICR0_INTEVENT_MASK (0x1 << I40E_PFINT_ICR0_INTEVENT_SHIFT)
1302#define I40E_PFINT_ICR0_QUEUE_0_SHIFT 1
1303#define I40E_PFINT_ICR0_QUEUE_0_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_0_SHIFT)
1304#define I40E_PFINT_ICR0_QUEUE_1_SHIFT 2
1305#define I40E_PFINT_ICR0_QUEUE_1_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_1_SHIFT)
1306#define I40E_PFINT_ICR0_QUEUE_2_SHIFT 3
1307#define I40E_PFINT_ICR0_QUEUE_2_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_2_SHIFT)
1308#define I40E_PFINT_ICR0_QUEUE_3_SHIFT 4
1309#define I40E_PFINT_ICR0_QUEUE_3_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_3_SHIFT)
1310#define I40E_PFINT_ICR0_QUEUE_4_SHIFT 5
1311#define I40E_PFINT_ICR0_QUEUE_4_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_4_SHIFT)
1312#define I40E_PFINT_ICR0_QUEUE_5_SHIFT 6
1313#define I40E_PFINT_ICR0_QUEUE_5_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_5_SHIFT)
1314#define I40E_PFINT_ICR0_QUEUE_6_SHIFT 7
1315#define I40E_PFINT_ICR0_QUEUE_6_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_6_SHIFT)
1316#define I40E_PFINT_ICR0_QUEUE_7_SHIFT 8
1317#define I40E_PFINT_ICR0_QUEUE_7_MASK (0x1 << I40E_PFINT_ICR0_QUEUE_7_SHIFT)
1318#define I40E_PFINT_ICR0_ECC_ERR_SHIFT 16
1319#define I40E_PFINT_ICR0_ECC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ECC_ERR_SHIFT)
1320#define I40E_PFINT_ICR0_MAL_DETECT_SHIFT 19
1321#define I40E_PFINT_ICR0_MAL_DETECT_MASK (0x1 << I40E_PFINT_ICR0_MAL_DETECT_SHIFT)
1322#define I40E_PFINT_ICR0_GRST_SHIFT 20
1323#define I40E_PFINT_ICR0_GRST_MASK (0x1 << I40E_PFINT_ICR0_GRST_SHIFT)
1324#define I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT 21
1325#define I40E_PFINT_ICR0_PCI_EXCEPTION_MASK (0x1 << I40E_PFINT_ICR0_PCI_EXCEPTION_SHIFT)
1326#define I40E_PFINT_ICR0_GPIO_SHIFT 22
1327#define I40E_PFINT_ICR0_GPIO_MASK (0x1 << I40E_PFINT_ICR0_GPIO_SHIFT)
1328#define I40E_PFINT_ICR0_TIMESYNC_SHIFT 23
1329#define I40E_PFINT_ICR0_TIMESYNC_MASK (0x1 << I40E_PFINT_ICR0_TIMESYNC_SHIFT)
1330#define I40E_PFINT_ICR0_STORM_DETECT_SHIFT 24
1331#define I40E_PFINT_ICR0_STORM_DETECT_MASK (0x1 << I40E_PFINT_ICR0_STORM_DETECT_SHIFT)
1332#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25
1333#define I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK (0x1 << I40E_PFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
1334#define I40E_PFINT_ICR0_HMC_ERR_SHIFT 26
1335#define I40E_PFINT_ICR0_HMC_ERR_MASK (0x1 << I40E_PFINT_ICR0_HMC_ERR_SHIFT)
1336#define I40E_PFINT_ICR0_PE_CRITERR_SHIFT 28
1337#define I40E_PFINT_ICR0_PE_CRITERR_MASK (0x1 << I40E_PFINT_ICR0_PE_CRITERR_SHIFT)
1338#define I40E_PFINT_ICR0_VFLR_SHIFT 29
1339#define I40E_PFINT_ICR0_VFLR_MASK (0x1 << I40E_PFINT_ICR0_VFLR_SHIFT)
1340#define I40E_PFINT_ICR0_ADMINQ_SHIFT 30
1341#define I40E_PFINT_ICR0_ADMINQ_MASK (0x1 << I40E_PFINT_ICR0_ADMINQ_SHIFT)
1342#define I40E_PFINT_ICR0_SWINT_SHIFT 31
1343#define I40E_PFINT_ICR0_SWINT_MASK (0x1 << I40E_PFINT_ICR0_SWINT_SHIFT)
1344#define I40E_PFINT_ICR0_ENA 0x00038800
1345#define I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT 16
1346#define I40E_PFINT_ICR0_ENA_ECC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_ECC_ERR_SHIFT)
1347#define I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT 19
1348#define I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK (0x1 << I40E_PFINT_ICR0_ENA_MAL_DETECT_SHIFT)
1349#define I40E_PFINT_ICR0_ENA_GRST_SHIFT 20
1350#define I40E_PFINT_ICR0_ENA_GRST_MASK (0x1 << I40E_PFINT_ICR0_ENA_GRST_SHIFT)
1351#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT 21
1352#define I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK (0x1 << I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_SHIFT)
1353#define I40E_PFINT_ICR0_ENA_GPIO_SHIFT 22
1354#define I40E_PFINT_ICR0_ENA_GPIO_MASK (0x1 << I40E_PFINT_ICR0_ENA_GPIO_SHIFT)
1355#define I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT 23
1356#define I40E_PFINT_ICR0_ENA_TIMESYNC_MASK (0x1 << I40E_PFINT_ICR0_ENA_TIMESYNC_SHIFT)
1357#define I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT 24
1358#define I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK (0x1 << I40E_PFINT_ICR0_ENA_STORM_DETECT_SHIFT)
1359#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25
1360#define I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK (0x1 << I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
1361#define I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT 26
1362#define I40E_PFINT_ICR0_ENA_HMC_ERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_HMC_ERR_SHIFT)
1363#define I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT 28
1364#define I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK (0x1 << I40E_PFINT_ICR0_ENA_PE_CRITERR_SHIFT)
1365#define I40E_PFINT_ICR0_ENA_VFLR_SHIFT 29
1366#define I40E_PFINT_ICR0_ENA_VFLR_MASK (0x1 << I40E_PFINT_ICR0_ENA_VFLR_SHIFT)
1367#define I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT 30
1368#define I40E_PFINT_ICR0_ENA_ADMINQ_MASK (0x1 << I40E_PFINT_ICR0_ENA_ADMINQ_SHIFT)
1369#define I40E_PFINT_ICR0_ENA_RSVD_SHIFT 31
1370#define I40E_PFINT_ICR0_ENA_RSVD_MASK (0x1 << I40E_PFINT_ICR0_ENA_RSVD_SHIFT)
1371#define I40E_PFINT_ITR0(_i) (0x00038000 + ((_i) * 128)) /* _i=0...2 */
1372#define I40E_PFINT_ITR0_MAX_INDEX 2
1373#define I40E_PFINT_ITR0_INTERVAL_SHIFT 0
1374#define I40E_PFINT_ITR0_INTERVAL_MASK (0xFFF << I40E_PFINT_ITR0_INTERVAL_SHIFT)
1375#define I40E_PFINT_ITRN(_i, _INTPF) (0x00030000 + ((_i) * 2048 + (_INTPF) * 4))
1376#define I40E_PFINT_ITRN_MAX_INDEX 2
1377#define I40E_PFINT_ITRN_INTERVAL_SHIFT 0
1378#define I40E_PFINT_ITRN_INTERVAL_MASK (0xFFF << I40E_PFINT_ITRN_INTERVAL_SHIFT)
1379#define I40E_PFINT_LNKLST0 0x00038500
1380#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
1381#define I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK (0x7FF << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT)
1382#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
1383#define I40E_PFINT_LNKLST0_FIRSTQ_TYPE_MASK (0x3 << I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
1384#define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */
1385#define I40E_PFINT_LNKLSTN_MAX_INDEX 511
1386#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
1387#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK (0x7FF << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
1388#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
1389#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_MASK (0x3 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
1390#define I40E_PFINT_RATE0 0x00038580
1391#define I40E_PFINT_RATE0_INTERVAL_SHIFT 0
1392#define I40E_PFINT_RATE0_INTERVAL_MASK (0x3F << I40E_PFINT_RATE0_INTERVAL_SHIFT)
1393#define I40E_PFINT_RATE0_INTRL_ENA_SHIFT 6
1394#define I40E_PFINT_RATE0_INTRL_ENA_MASK (0x1 << I40E_PFINT_RATE0_INTRL_ENA_SHIFT)
1395#define I40E_PFINT_RATEN(_INTPF) (0x00035800 + ((_INTPF) * 4)) /* _i=0...511 */
1396#define I40E_PFINT_RATEN_MAX_INDEX 511
1397#define I40E_PFINT_RATEN_INTERVAL_SHIFT 0
1398#define I40E_PFINT_RATEN_INTERVAL_MASK (0x3F << I40E_PFINT_RATEN_INTERVAL_SHIFT)
1399#define I40E_PFINT_RATEN_INTRL_ENA_SHIFT 6
1400#define I40E_PFINT_RATEN_INTRL_ENA_MASK (0x1 << I40E_PFINT_RATEN_INTRL_ENA_SHIFT)
1401#define I40E_PFINT_STAT_CTL0 0x00038400
1402#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
1403#define I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK (0x3 << I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
1404#define I40E_QINT_RQCTL(_Q) (0x0003A000 + ((_Q) * 4)) /* _i=0...1535 */
1405#define I40E_QINT_RQCTL_MAX_INDEX 1535
1406#define I40E_QINT_RQCTL_MSIX_INDX_SHIFT 0
1407#define I40E_QINT_RQCTL_MSIX_INDX_MASK (0xFF << I40E_QINT_RQCTL_MSIX_INDX_SHIFT)
1408#define I40E_QINT_RQCTL_ITR_INDX_SHIFT 11
1409#define I40E_QINT_RQCTL_ITR_INDX_MASK (0x3 << I40E_QINT_RQCTL_ITR_INDX_SHIFT)
1410#define I40E_QINT_RQCTL_MSIX0_INDX_SHIFT 13
1411#define I40E_QINT_RQCTL_MSIX0_INDX_MASK (0x7 << I40E_QINT_RQCTL_MSIX0_INDX_SHIFT)
1412#define I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT 16
1413#define I40E_QINT_RQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)
1414#define I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT 27
1415#define I40E_QINT_RQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT)
1416#define I40E_QINT_RQCTL_CAUSE_ENA_SHIFT 30
1417#define I40E_QINT_RQCTL_CAUSE_ENA_MASK (0x1 << I40E_QINT_RQCTL_CAUSE_ENA_SHIFT)
1418#define I40E_QINT_RQCTL_INTEVENT_SHIFT 31
1419#define I40E_QINT_RQCTL_INTEVENT_MASK (0x1 << I40E_QINT_RQCTL_INTEVENT_SHIFT)
1420#define I40E_QINT_TQCTL(_Q) (0x0003C000 + ((_Q) * 4)) /* _i=0...1535 */
1421#define I40E_QINT_TQCTL_MAX_INDEX 1535
1422#define I40E_QINT_TQCTL_MSIX_INDX_SHIFT 0
1423#define I40E_QINT_TQCTL_MSIX_INDX_MASK (0xFF << I40E_QINT_TQCTL_MSIX_INDX_SHIFT)
1424#define I40E_QINT_TQCTL_ITR_INDX_SHIFT 11
1425#define I40E_QINT_TQCTL_ITR_INDX_MASK (0x3 << I40E_QINT_TQCTL_ITR_INDX_SHIFT)
1426#define I40E_QINT_TQCTL_MSIX0_INDX_SHIFT 13
1427#define I40E_QINT_TQCTL_MSIX0_INDX_MASK (0x7 << I40E_QINT_TQCTL_MSIX0_INDX_SHIFT)
1428#define I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT 16
1429#define I40E_QINT_TQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT)
1430#define I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT 27
1431#define I40E_QINT_TQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT)
1432#define I40E_QINT_TQCTL_CAUSE_ENA_SHIFT 30
1433#define I40E_QINT_TQCTL_CAUSE_ENA_MASK (0x1 << I40E_QINT_TQCTL_CAUSE_ENA_SHIFT)
1434#define I40E_QINT_TQCTL_INTEVENT_SHIFT 31
1435#define I40E_QINT_TQCTL_INTEVENT_MASK (0x1 << I40E_QINT_TQCTL_INTEVENT_SHIFT)
1436#define I40E_VFINT_DYN_CTL0(_VF) (0x0002A400 + ((_VF) * 4)) /* _i=0...127 */
1437#define I40E_VFINT_DYN_CTL0_MAX_INDEX 127
1438#define I40E_VFINT_DYN_CTL0_INTENA_SHIFT 0
1439#define I40E_VFINT_DYN_CTL0_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTL0_INTENA_SHIFT)
1440#define I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT 1
1441#define I40E_VFINT_DYN_CTL0_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTL0_CLEARPBA_SHIFT)
1442#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT 2
1443#define I40E_VFINT_DYN_CTL0_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTL0_SWINT_TRIG_SHIFT)
1444#define I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT 3
1445#define I40E_VFINT_DYN_CTL0_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT)
1446#define I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT 5
1447#define I40E_VFINT_DYN_CTL0_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT)
1448#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT 24
1449#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTL0_SW_ITR_INDX_ENA_SHIFT)
1450#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT 25
1451#define I40E_VFINT_DYN_CTL0_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL0_SW_ITR_INDX_SHIFT)
1452#define I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT 31
1453#define I40E_VFINT_DYN_CTL0_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTL0_INTENA_MSK_SHIFT)
1454#define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */
1455#define I40E_VFINT_DYN_CTLN_MAX_INDEX 511
1456#define I40E_VFINT_DYN_CTLN_INTENA_SHIFT 0
1457#define I40E_VFINT_DYN_CTLN_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTLN_INTENA_SHIFT)
1458#define I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT 1
1459#define I40E_VFINT_DYN_CTLN_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTLN_CLEARPBA_SHIFT)
1460#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT 2
1461#define I40E_VFINT_DYN_CTLN_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTLN_SWINT_TRIG_SHIFT)
1462#define I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT 3
1463#define I40E_VFINT_DYN_CTLN_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN_ITR_INDX_SHIFT)
1464#define I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT 5
1465#define I40E_VFINT_DYN_CTLN_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTLN_INTERVAL_SHIFT)
1466#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT 24
1467#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTLN_SW_ITR_INDX_ENA_SHIFT)
1468#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT 25
1469#define I40E_VFINT_DYN_CTLN_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN_SW_ITR_INDX_SHIFT)
1470#define I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT 31
1471#define I40E_VFINT_DYN_CTLN_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTLN_INTENA_MSK_SHIFT)
1472#define I40E_VFINT_ICR0(_VF) (0x0002BC00 + ((_VF) * 4)) /* _i=0...127 */
1473#define I40E_VFINT_ICR0_MAX_INDEX 127
1474#define I40E_VFINT_ICR0_INTEVENT_SHIFT 0
1475#define I40E_VFINT_ICR0_INTEVENT_MASK (0x1 << I40E_VFINT_ICR0_INTEVENT_SHIFT)
1476#define I40E_VFINT_ICR0_QUEUE_0_SHIFT 1
1477#define I40E_VFINT_ICR0_QUEUE_0_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_0_SHIFT)
1478#define I40E_VFINT_ICR0_QUEUE_1_SHIFT 2
1479#define I40E_VFINT_ICR0_QUEUE_1_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_1_SHIFT)
1480#define I40E_VFINT_ICR0_QUEUE_2_SHIFT 3
1481#define I40E_VFINT_ICR0_QUEUE_2_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_2_SHIFT)
1482#define I40E_VFINT_ICR0_QUEUE_3_SHIFT 4
1483#define I40E_VFINT_ICR0_QUEUE_3_MASK (0x1 << I40E_VFINT_ICR0_QUEUE_3_SHIFT)
1484#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT 25
1485#define I40E_VFINT_ICR0_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_LINK_STAT_CHANGE_SHIFT)
1486#define I40E_VFINT_ICR0_ADMINQ_SHIFT 30
1487#define I40E_VFINT_ICR0_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ADMINQ_SHIFT)
1488#define I40E_VFINT_ICR0_SWINT_SHIFT 31
1489#define I40E_VFINT_ICR0_SWINT_MASK (0x1 << I40E_VFINT_ICR0_SWINT_SHIFT)
1490#define I40E_VFINT_ICR0_ENA(_VF) (0x0002C000 + ((_VF) * 4)) /* _i=0...127 */
1491#define I40E_VFINT_ICR0_ENA_MAX_INDEX 127
1492#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT 25
1493#define I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_ENA_LINK_STAT_CHANGE_SHIFT)
1494#define I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT 30
1495#define I40E_VFINT_ICR0_ENA_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ENA_ADMINQ_SHIFT)
1496#define I40E_VFINT_ICR0_ENA_RSVD_SHIFT 31
1497#define I40E_VFINT_ICR0_ENA_RSVD_MASK (0x1 << I40E_VFINT_ICR0_ENA_RSVD_SHIFT)
1498#define I40E_VFINT_ITR0(_i, _VF) (0x00028000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...2, _VF=0...127 */
1499#define I40E_VFINT_ITR0_MAX_INDEX 2
1500#define I40E_VFINT_ITR0_INTERVAL_SHIFT 0
1501#define I40E_VFINT_ITR0_INTERVAL_MASK (0xFFF << I40E_VFINT_ITR0_INTERVAL_SHIFT)
1502#define I40E_VFINT_ITRN(_i, _INTVF) (0x00020000 + ((_i) * 2048 + (_INTVF) * 4))
1503#define I40E_VFINT_ITRN_MAX_INDEX 2
1504#define I40E_VFINT_ITRN_INTERVAL_SHIFT 0
1505#define I40E_VFINT_ITRN_INTERVAL_MASK (0xFFF << I40E_VFINT_ITRN_INTERVAL_SHIFT)
1506#define I40E_VFINT_STAT_CTL0(_VF) (0x0002A000 + ((_VF) * 4)) /* _i=0...127 */
1507#define I40E_VFINT_STAT_CTL0_MAX_INDEX 127
1508#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT 2
1509#define I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_MASK (0x3 << I40E_VFINT_STAT_CTL0_OTHER_ITR_INDX_SHIFT)
1510#define I40E_VPINT_AEQCTL(_VF) (0x0002B800 + ((_VF) * 4)) /* _i=0...127 */
1511#define I40E_VPINT_AEQCTL_MAX_INDEX 127
1512#define I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT 0
1513#define I40E_VPINT_AEQCTL_MSIX_INDX_MASK (0xFF << I40E_VPINT_AEQCTL_MSIX_INDX_SHIFT)
1514#define I40E_VPINT_AEQCTL_ITR_INDX_SHIFT 11
1515#define I40E_VPINT_AEQCTL_ITR_INDX_MASK (0x3 << I40E_VPINT_AEQCTL_ITR_INDX_SHIFT)
1516#define I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT 13
1517#define I40E_VPINT_AEQCTL_MSIX0_INDX_MASK (0x7 << I40E_VPINT_AEQCTL_MSIX0_INDX_SHIFT)
1518#define I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT 30
1519#define I40E_VPINT_AEQCTL_CAUSE_ENA_MASK (0x1 << I40E_VPINT_AEQCTL_CAUSE_ENA_SHIFT)
1520#define I40E_VPINT_AEQCTL_INTEVENT_SHIFT 31
1521#define I40E_VPINT_AEQCTL_INTEVENT_MASK (0x1 << I40E_VPINT_AEQCTL_INTEVENT_SHIFT)
1522#define I40E_VPINT_CEQCTL(_INTVF) (0x00026800 + ((_INTVF) * 4)) /* _i=0...511 */
1523#define I40E_VPINT_CEQCTL_MAX_INDEX 511
1524#define I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT 0
1525#define I40E_VPINT_CEQCTL_MSIX_INDX_MASK (0xFF << I40E_VPINT_CEQCTL_MSIX_INDX_SHIFT)
1526#define I40E_VPINT_CEQCTL_ITR_INDX_SHIFT 11
1527#define I40E_VPINT_CEQCTL_ITR_INDX_MASK (0x3 << I40E_VPINT_CEQCTL_ITR_INDX_SHIFT)
1528#define I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT 13
1529#define I40E_VPINT_CEQCTL_MSIX0_INDX_MASK (0x7 << I40E_VPINT_CEQCTL_MSIX0_INDX_SHIFT)
1530#define I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT 16
1531#define I40E_VPINT_CEQCTL_NEXTQ_INDX_MASK (0x7FF << I40E_VPINT_CEQCTL_NEXTQ_INDX_SHIFT)
1532#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT 27
1533#define I40E_VPINT_CEQCTL_NEXTQ_TYPE_MASK (0x3 << I40E_VPINT_CEQCTL_NEXTQ_TYPE_SHIFT)
1534#define I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT 30
1535#define I40E_VPINT_CEQCTL_CAUSE_ENA_MASK (0x1 << I40E_VPINT_CEQCTL_CAUSE_ENA_SHIFT)
1536#define I40E_VPINT_CEQCTL_INTEVENT_SHIFT 31
1537#define I40E_VPINT_CEQCTL_INTEVENT_MASK (0x1 << I40E_VPINT_CEQCTL_INTEVENT_SHIFT)
1538#define I40E_VPINT_LNKLST0(_VF) (0x0002A800 + ((_VF) * 4)) /* _i=0...127 */
1539#define I40E_VPINT_LNKLST0_MAX_INDEX 127
1540#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT 0
1541#define I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK (0x7FF << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT)
1542#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT 11
1543#define I40E_VPINT_LNKLST0_FIRSTQ_TYPE_MASK (0x3 << I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT)
1544#define I40E_VPINT_LNKLSTN(_INTVF) (0x00025000 + ((_INTVF) * 4)) /* _i=0...511 */
1545#define I40E_VPINT_LNKLSTN_MAX_INDEX 511
1546#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT 0
1547#define I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK (0x7FF << I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT)
1548#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT 11
1549#define I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_MASK (0x3 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT)
1550#define I40E_VPINT_RATE0(_VF) (0x0002AC00 + ((_VF) * 4)) /* _i=0...127 */
1551#define I40E_VPINT_RATE0_MAX_INDEX 127
1552#define I40E_VPINT_RATE0_INTERVAL_SHIFT 0
1553#define I40E_VPINT_RATE0_INTERVAL_MASK (0x3F << I40E_VPINT_RATE0_INTERVAL_SHIFT)
1554#define I40E_VPINT_RATE0_INTRL_ENA_SHIFT 6
1555#define I40E_VPINT_RATE0_INTRL_ENA_MASK (0x1 << I40E_VPINT_RATE0_INTRL_ENA_SHIFT)
1556#define I40E_VPINT_RATEN(_INTVF) (0x00025800 + ((_INTVF) * 4)) /* _i=0...511 */
1557#define I40E_VPINT_RATEN_MAX_INDEX 511
1558#define I40E_VPINT_RATEN_INTERVAL_SHIFT 0
1559#define I40E_VPINT_RATEN_INTERVAL_MASK (0x3F << I40E_VPINT_RATEN_INTERVAL_SHIFT)
1560#define I40E_VPINT_RATEN_INTRL_ENA_SHIFT 6
1561#define I40E_VPINT_RATEN_INTRL_ENA_MASK (0x1 << I40E_VPINT_RATEN_INTRL_ENA_SHIFT)
1562#define I40E_GL_RDPU_CNTRL 0x00051060
1563#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT 0
1564#define I40E_GL_RDPU_CNTRL_RX_PAD_EN_MASK (0x1 << I40E_GL_RDPU_CNTRL_RX_PAD_EN_SHIFT)
1565#define I40E_GL_RDPU_CNTRL_ECO_SHIFT 1
1566#define I40E_GL_RDPU_CNTRL_ECO_MASK (0x7FFFFFFF << I40E_GL_RDPU_CNTRL_ECO_SHIFT)
1567#define I40E_GLLAN_RCTL_0 0x0012A500
1568#define I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT 0
1569#define I40E_GLLAN_RCTL_0_PXE_MODE_MASK (0x1 << I40E_GLLAN_RCTL_0_PXE_MODE_SHIFT)
1570#define I40E_GLLAN_TSOMSK_F 0x000442D8
1571#define I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT 0
1572#define I40E_GLLAN_TSOMSK_F_TCPMSKF_MASK (0xFFF << I40E_GLLAN_TSOMSK_F_TCPMSKF_SHIFT)
1573#define I40E_GLLAN_TSOMSK_L 0x000442E0
1574#define I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT 0
1575#define I40E_GLLAN_TSOMSK_L_TCPMSKL_MASK (0xFFF << I40E_GLLAN_TSOMSK_L_TCPMSKL_SHIFT)
1576#define I40E_GLLAN_TSOMSK_M 0x000442DC
1577#define I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT 0
1578#define I40E_GLLAN_TSOMSK_M_TCPMSKM_MASK (0xFFF << I40E_GLLAN_TSOMSK_M_TCPMSKM_SHIFT)
1579#define I40E_PFLAN_QALLOC 0x001C0400
1580#define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0
1581#define I40E_PFLAN_QALLOC_FIRSTQ_MASK (0x7FF << I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)
1582#define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16
1583#define I40E_PFLAN_QALLOC_LASTQ_MASK (0x7FF << I40E_PFLAN_QALLOC_LASTQ_SHIFT)
1584#define I40E_PFLAN_QALLOC_VALID_SHIFT 31
1585#define I40E_PFLAN_QALLOC_VALID_MASK (0x1 << I40E_PFLAN_QALLOC_VALID_SHIFT)
1586#define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */
1587#define I40E_QRX_ENA_MAX_INDEX 1535
1588#define I40E_QRX_ENA_QENA_REQ_SHIFT 0
1589#define I40E_QRX_ENA_QENA_REQ_MASK (0x1 << I40E_QRX_ENA_QENA_REQ_SHIFT)
1590#define I40E_QRX_ENA_FAST_QDIS_SHIFT 1
1591#define I40E_QRX_ENA_FAST_QDIS_MASK (0x1 << I40E_QRX_ENA_FAST_QDIS_SHIFT)
1592#define I40E_QRX_ENA_QENA_STAT_SHIFT 2
1593#define I40E_QRX_ENA_QENA_STAT_MASK (0x1 << I40E_QRX_ENA_QENA_STAT_SHIFT)
1594#define I40E_QRX_TAIL(_Q) (0x00128000 + ((_Q) * 4)) /* _i=0...1535 */
1595#define I40E_QRX_TAIL_MAX_INDEX 1535
1596#define I40E_QRX_TAIL_TAIL_SHIFT 0
1597#define I40E_QRX_TAIL_TAIL_MASK (0x1FFF << I40E_QRX_TAIL_TAIL_SHIFT)
1598#define I40E_QTX_CTL(_Q) (0x00104000 + ((_Q) * 4)) /* _i=0...1535 */
1599#define I40E_QTX_CTL_MAX_INDEX 1535
1600#define I40E_QTX_CTL_PFVF_Q_SHIFT 0
1601#define I40E_QTX_CTL_PFVF_Q_MASK (0x3 << I40E_QTX_CTL_PFVF_Q_SHIFT)
1602#define I40E_QTX_CTL_PF_INDX_SHIFT 2
1603#define I40E_QTX_CTL_PF_INDX_MASK (0xF << I40E_QTX_CTL_PF_INDX_SHIFT)
1604#define I40E_QTX_CTL_VFVM_INDX_SHIFT 7
1605#define I40E_QTX_CTL_VFVM_INDX_MASK (0x1FF << I40E_QTX_CTL_VFVM_INDX_SHIFT)
1606#define I40E_QTX_ENA(_Q) (0x00100000 + ((_Q) * 4)) /* _i=0...1535 */
1607#define I40E_QTX_ENA_MAX_INDEX 1535
1608#define I40E_QTX_ENA_QENA_REQ_SHIFT 0
1609#define I40E_QTX_ENA_QENA_REQ_MASK (0x1 << I40E_QTX_ENA_QENA_REQ_SHIFT)
1610#define I40E_QTX_ENA_FAST_QDIS_SHIFT 1
1611#define I40E_QTX_ENA_FAST_QDIS_MASK (0x1 << I40E_QTX_ENA_FAST_QDIS_SHIFT)
1612#define I40E_QTX_ENA_QENA_STAT_SHIFT 2
1613#define I40E_QTX_ENA_QENA_STAT_MASK (0x1 << I40E_QTX_ENA_QENA_STAT_SHIFT)
1614#define I40E_QTX_HEAD(_Q) (0x000E4000 + ((_Q) * 4)) /* _i=0...1535 */
1615#define I40E_QTX_HEAD_MAX_INDEX 1535
1616#define I40E_QTX_HEAD_HEAD_SHIFT 0
1617#define I40E_QTX_HEAD_HEAD_MASK (0x1FFF << I40E_QTX_HEAD_HEAD_SHIFT)
1618#define I40E_QTX_HEAD_RS_PENDING_SHIFT 16
1619#define I40E_QTX_HEAD_RS_PENDING_MASK (0x1 << I40E_QTX_HEAD_RS_PENDING_SHIFT)
1620#define I40E_QTX_TAIL(_Q) (0x00108000 + ((_Q) * 4)) /* _i=0...1535 */
1621#define I40E_QTX_TAIL_MAX_INDEX 1535
1622#define I40E_QTX_TAIL_TAIL_SHIFT 0
1623#define I40E_QTX_TAIL_TAIL_MASK (0x1FFF << I40E_QTX_TAIL_TAIL_SHIFT)
1624#define I40E_VPLAN_MAPENA(_VF) (0x00074000 + ((_VF) * 4)) /* _i=0...127 */
1625#define I40E_VPLAN_MAPENA_MAX_INDEX 127
1626#define I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT 0
1627#define I40E_VPLAN_MAPENA_TXRX_ENA_MASK (0x1 << I40E_VPLAN_MAPENA_TXRX_ENA_SHIFT)
1628#define I40E_VPLAN_QTABLE(_i, _VF) (0x00070000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */
1629#define I40E_VPLAN_QTABLE_MAX_INDEX 15
1630#define I40E_VPLAN_QTABLE_QINDEX_SHIFT 0
1631#define I40E_VPLAN_QTABLE_QINDEX_MASK (0x7FF << I40E_VPLAN_QTABLE_QINDEX_SHIFT)
1632#define I40E_VSILAN_QBASE(_VSI) (0x0020C800 + ((_VSI) * 4)) /* _i=0...383 */
1633#define I40E_VSILAN_QBASE_MAX_INDEX 383
1634#define I40E_VSILAN_QBASE_VSIBASE_SHIFT 0
1635#define I40E_VSILAN_QBASE_VSIBASE_MASK (0x7FF << I40E_VSILAN_QBASE_VSIBASE_SHIFT)
1636#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT 11
1637#define I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK (0x1 << I40E_VSILAN_QBASE_VSIQTABLE_ENA_SHIFT)
1638#define I40E_VSILAN_QTABLE(_i, _VSI) (0x00200000 + ((_i) * 2048 + (_VSI) * 4))
1639#define I40E_VSILAN_QTABLE_MAX_INDEX 15
1640#define I40E_VSILAN_QTABLE_QINDEX_0_SHIFT 0
1641#define I40E_VSILAN_QTABLE_QINDEX_0_MASK (0x7FF << I40E_VSILAN_QTABLE_QINDEX_0_SHIFT)
1642#define I40E_VSILAN_QTABLE_QINDEX_1_SHIFT 16
1643#define I40E_VSILAN_QTABLE_QINDEX_1_MASK (0x7FF << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT)
1644#define I40E_PRTGL_SAH 0x001E2140
1645#define I40E_PRTGL_SAH_FC_SAH_SHIFT 0
1646#define I40E_PRTGL_SAH_FC_SAH_MASK (0xFFFF << I40E_PRTGL_SAH_FC_SAH_SHIFT)
1647#define I40E_PRTGL_SAH_MFS_SHIFT 16
1648#define I40E_PRTGL_SAH_MFS_MASK (0xFFFF << I40E_PRTGL_SAH_MFS_SHIFT)
1649#define I40E_PRTGL_SAL 0x001E2120
1650#define I40E_PRTGL_SAL_FC_SAL_SHIFT 0
1651#define I40E_PRTGL_SAL_FC_SAL_MASK (0xFFFFFFFF << I40E_PRTGL_SAL_FC_SAL_SHIFT)
1652#define I40E_PRTMAC_HLCTLA 0x001E4760
1653#define I40E_PRTMAC_HLCTLA_DROP_US_PKTS_SHIFT 0
1654#define I40E_PRTMAC_HLCTLA_DROP_US_PKTS_MASK (0x1 << I40E_PRTMAC_HLCTLA_DROP_US_PKTS_SHIFT)
1655#define I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_SHIFT 1
1656#define I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_MASK (0x1 << I40E_PRTMAC_HLCTLA_RX_FWRD_CTRL_SHIFT)
1657#define I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_SHIFT 2
1658#define I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_MASK (0x1 << I40E_PRTMAC_HLCTLA_CHOP_OS_PKT_SHIFT)
1659#define I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_SHIFT 4
1660#define I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_MASK (0x7 << I40E_PRTMAC_HLCTLA_TX_HYSTERESIS_SHIFT)
1661#define I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_SHIFT 7
1662#define I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_MASK (0x1 << I40E_PRTMAC_HLCTLA_HYS_FLUSH_PKT_SHIFT)
1663#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP 0x001E3130
1664#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_SHIFT 0
1665#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GCP_HSEC_CTL_RX_CHECK_SA_GCP_SHIFT)
1666#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP 0x001E3290
1667#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_SHIFT 0
1668#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_GPP_HSEC_CTL_RX_CHECK_SA_GPP_SHIFT)
1669#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP 0x001E3310
1670#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_SHIFT 0
1671#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_SA_PPP_HSEC_CTL_RX_CHECK_SA_PPP_SHIFT)
1672#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP 0x001E3100
1673#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_SHIFT 0
1674#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GCP_HSEC_CTL_RX_CHECK_UCAST_GCP_SHIFT)
1675#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP 0x001E3280
1676#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_SHIFT 0
1677#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_GPP_HSEC_CTL_RX_CHECK_UCAST_GPP_SHIFT)
1678#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP 0x001E3300
1679#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_SHIFT 0
1680#define I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_CHECK_UCAST_PPP_HSEC_CTL_RX_CHECK_UCAST_PPP_SHIFT)
1681#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001E30E0
1682#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT 0
1683#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GCP_HSEC_CTL_RX_ENABLE_GCP_SHIFT)
1684#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP 0x001E3260
1685#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT 0
1686#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_GPP_HSEC_CTL_RX_ENABLE_GPP_SHIFT)
1687#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP 0x001E32E0
1688#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT 0
1689#define I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_ENABLE_PPP_HSEC_CTL_RX_ENABLE_PPP_SHIFT)
1690#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL 0x001E3360
1691#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT 0
1692#define I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL_HSEC_CTL_RX_FORWARD_CONTROL_SHIFT)
1693#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1 0x001E3110
1694#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT 0
1695#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_HSEC_CTL_RX_PAUSE_DA_UCAST_PART1_SHIFT)
1696#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2 0x001E3120
1697#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT 0
1698#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_HSEC_CTL_RX_PAUSE_DA_UCAST_PART2_SHIFT)
1699#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE 0x001E30C0
1700#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT 0
1701#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_MASK (0x1FF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_HSEC_CTL_RX_PAUSE_ENABLE_SHIFT)
1702#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1 0x001E3140
1703#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT 0
1704#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART1_HSEC_CTL_RX_PAUSE_SA_PART1_SHIFT)
1705#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2 0x001E3150
1706#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT 0
1707#define I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_RX_PAUSE_SA_PART2_HSEC_CTL_RX_PAUSE_SA_PART2_SHIFT)
1708#define I40E_PRTMAC_HSEC_CTL_TX_ENABLE 0x001E3000
1709#define I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_SHIFT 0
1710#define I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_MASK (0x1 << I40E_PRTMAC_HSEC_CTL_TX_ENABLE_HSEC_CTL_TX_ENABLE_SHIFT)
1711#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE 0x001E30D0
1712#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT 0
1713#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_MASK (0x1FF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_HSEC_CTL_TX_PAUSE_ENABLE_SHIFT)
1714#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E3370 + ((_i) * 16))
1715#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
1716#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT 0
1717#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_SHIFT)
1718#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3400 + ((_i) * 16))
1719#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MAX_INDEX 8
1720#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT 0
1721#define I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_SHIFT)
1722#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1 0x001E34B0
1723#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT 0
1724#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_MASK (0xFFFFFFFF << I40E_PRTMAC_HSEC_CTL_TX_SA_PART1_HSEC_CTL_TX_SA_PART1_SHIFT)
1725#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2 0x001E34C0
1726#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT 0
1727#define I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_MASK (0xFFFF << I40E_PRTMAC_HSEC_CTL_TX_SA_PART2_HSEC_CTL_TX_SA_PART2_SHIFT)
1728#define I40E_PRTMAC_HSECTL1 0x001E3560
1729#define I40E_PRTMAC_HSECTL1_DROP_US_PKTS_SHIFT 0
1730#define I40E_PRTMAC_HSECTL1_DROP_US_PKTS_MASK (0x1 << I40E_PRTMAC_HSECTL1_DROP_US_PKTS_SHIFT)
1731#define I40E_PRTMAC_HSECTL1_PAD_US_PKT_SHIFT 3
1732#define I40E_PRTMAC_HSECTL1_PAD_US_PKT_MASK (0x1 << I40E_PRTMAC_HSECTL1_PAD_US_PKT_SHIFT)
1733#define I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_SHIFT 4
1734#define I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_MASK (0x7 << I40E_PRTMAC_HSECTL1_TX_HYSTERESIS_SHIFT)
1735#define I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_SHIFT 7
1736#define I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_MASK (0x1 << I40E_PRTMAC_HSECTL1_HYS_FLUSH_PKT_SHIFT)
1737#define I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_SHIFT 30
1738#define I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_MASK (0x1 << I40E_PRTMAC_HSECTL1_EN_SFD_CHECK_SHIFT)
1739#define I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_SHIFT 31
1740#define I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_MASK (0x1 << I40E_PRTMAC_HSECTL1_EN_PREAMBLE_CHECK_SHIFT)
1741#define I40E_PRTMAC_PCS_XAUI_SWAP_A 0x0008C480
1742#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT 0
1743#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE3_SHIFT)
1744#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT 2
1745#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE2_SHIFT)
1746#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT 4
1747#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE1_SHIFT)
1748#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT 6
1749#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_TX_LANE0_SHIFT)
1750#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT 8
1751#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE3_SHIFT)
1752#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT 10
1753#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE2_SHIFT)
1754#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT 12
1755#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE1_SHIFT)
1756#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT 14
1757#define I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_A_SWAP_RX_LANE0_SHIFT)
1758#define I40E_PRTMAC_PCS_XAUI_SWAP_B 0x0008C484
1759#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT 0
1760#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE3_SHIFT)
1761#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT 2
1762#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE2_SHIFT)
1763#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT 4
1764#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE1_SHIFT)
1765#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT 6
1766#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_TX_LANE0_SHIFT)
1767#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT 8
1768#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE3_SHIFT)
1769#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT 10
1770#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE2_SHIFT)
1771#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT 12
1772#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE1_SHIFT)
1773#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT 14
1774#define I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_MASK (0x3 << I40E_PRTMAC_PCS_XAUI_SWAP_B_SWAP_RX_LANE0_SHIFT)
1775#define I40E_GL_MNG_FWSM 0x000B6134
1776#define I40E_GL_MNG_FWSM_FW_MODES_SHIFT 0
1777#define I40E_GL_MNG_FWSM_FW_MODES_MASK (0x3FF << I40E_GL_MNG_FWSM_FW_MODES_SHIFT)
1778#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT 10
1779#define I40E_GL_MNG_FWSM_EEP_RELOAD_IND_MASK (0x1 << I40E_GL_MNG_FWSM_EEP_RELOAD_IND_SHIFT)
1780#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT 11
1781#define I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_MASK (0xF << I40E_GL_MNG_FWSM_CRC_ERROR_MODULE_SHIFT)
1782#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT 15
1783#define I40E_GL_MNG_FWSM_FW_STATUS_VALID_MASK (0x1 << I40E_GL_MNG_FWSM_FW_STATUS_VALID_SHIFT)
1784#define I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT 19
1785#define I40E_GL_MNG_FWSM_EXT_ERR_IND_MASK (0x3F << I40E_GL_MNG_FWSM_EXT_ERR_IND_SHIFT)
1786#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT 26
1787#define I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES0_CONFIG_ERR_SHIFT)
1788#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT 27
1789#define I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES1_CONFIG_ERR_SHIFT)
1790#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT 28
1791#define I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES2_CONFIG_ERR_SHIFT)
1792#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT 29
1793#define I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_MASK (0x1 << I40E_GL_MNG_FWSM_PHY_SERDES3_CONFIG_ERR_SHIFT)
1794#define I40E_GL_MNG_HWARB_CTRL 0x000B6130
1795#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT 0
1796#define I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_MASK (0x1 << I40E_GL_MNG_HWARB_CTRL_NCSI_ARB_EN_SHIFT)
1797#define I40E_PRT_MNG_FTFT_DATA(_i) (0x000852A0 + ((_i) * 32)) /* _i=0...31 */
1798#define I40E_PRT_MNG_FTFT_DATA_MAX_INDEX 31
1799#define I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT 0
1800#define I40E_PRT_MNG_FTFT_DATA_DWORD_MASK (0xFFFFFFFF << I40E_PRT_MNG_FTFT_DATA_DWORD_SHIFT)
1801#define I40E_PRT_MNG_FTFT_LENGTH 0x00085260
1802#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT 0
1803#define I40E_PRT_MNG_FTFT_LENGTH_LENGTH_MASK (0xFF << I40E_PRT_MNG_FTFT_LENGTH_LENGTH_SHIFT)
1804#define I40E_PRT_MNG_FTFT_MASK(_i) (0x00085160 + ((_i) * 32)) /* _i=0...7 */
1805#define I40E_PRT_MNG_FTFT_MASK_MAX_INDEX 7
1806#define I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT 0
1807#define I40E_PRT_MNG_FTFT_MASK_MASK_MASK (0xFFFF << I40E_PRT_MNG_FTFT_MASK_MASK_SHIFT)
1808#define I40E_PRT_MNG_MANC 0x00256A20
1809#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT 0
1810#define I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_MASK (0x1 << I40E_PRT_MNG_MANC_FLOW_CONTROL_DISCARD_SHIFT)
1811#define I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT 1
1812#define I40E_PRT_MNG_MANC_NCSI_DISCARD_MASK (0x1 << I40E_PRT_MNG_MANC_NCSI_DISCARD_SHIFT)
1813#define I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT 17
1814#define I40E_PRT_MNG_MANC_RCV_TCO_EN_MASK (0x1 << I40E_PRT_MNG_MANC_RCV_TCO_EN_SHIFT)
1815#define I40E_PRT_MNG_MANC_RCV_ALL_SHIFT 19
1816#define I40E_PRT_MNG_MANC_RCV_ALL_MASK (0x1 << I40E_PRT_MNG_MANC_RCV_ALL_SHIFT)
1817#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT 25
1818#define I40E_PRT_MNG_MANC_FIXED_NET_TYPE_MASK (0x1 << I40E_PRT_MNG_MANC_FIXED_NET_TYPE_SHIFT)
1819#define I40E_PRT_MNG_MANC_NET_TYPE_SHIFT 26
1820#define I40E_PRT_MNG_MANC_NET_TYPE_MASK (0x1 << I40E_PRT_MNG_MANC_NET_TYPE_SHIFT)
1821#define I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT 28
1822#define I40E_PRT_MNG_MANC_EN_BMC2OS_MASK (0x1 << I40E_PRT_MNG_MANC_EN_BMC2OS_SHIFT)
1823#define I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT 29
1824#define I40E_PRT_MNG_MANC_EN_BMC2NET_MASK (0x1 << I40E_PRT_MNG_MANC_EN_BMC2NET_SHIFT)
1825#define I40E_PRT_MNG_MAVTV(_i) (0x00255900 + ((_i) * 32)) /* _i=0...7 */
1826#define I40E_PRT_MNG_MAVTV_MAX_INDEX 7
1827#define I40E_PRT_MNG_MAVTV_VID_SHIFT 0
1828#define I40E_PRT_MNG_MAVTV_VID_MASK (0xFFF << I40E_PRT_MNG_MAVTV_VID_SHIFT)
1829#define I40E_PRT_MNG_MDEF(_i) (0x00255D00 + ((_i) * 32))
1830#define I40E_PRT_MNG_MDEF_MAX_INDEX 7
1831#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT 0
1832#define I40E_PRT_MNG_MDEF_MAC_EXACT_AND_MASK (0xF << I40E_PRT_MNG_MDEF_MAC_EXACT_AND_SHIFT)
1833#define I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT 4
1834#define I40E_PRT_MNG_MDEF_BROADCAST_AND_MASK (0x1 << I40E_PRT_MNG_MDEF_BROADCAST_AND_SHIFT)
1835#define I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT 5
1836#define I40E_PRT_MNG_MDEF_VLAN_AND_MASK (0xFF << I40E_PRT_MNG_MDEF_VLAN_AND_SHIFT)
1837#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT 13
1838#define I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_MASK (0xF << I40E_PRT_MNG_MDEF_IPV4_ADDRESS_AND_SHIFT)
1839#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT 17
1840#define I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_MASK (0xF << I40E_PRT_MNG_MDEF_IPV6_ADDRESS_AND_SHIFT)
1841#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT 21
1842#define I40E_PRT_MNG_MDEF_MAC_EXACT_OR_MASK (0xF << I40E_PRT_MNG_MDEF_MAC_EXACT_OR_SHIFT)
1843#define I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT 25
1844#define I40E_PRT_MNG_MDEF_BROADCAST_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_BROADCAST_OR_SHIFT)
1845#define I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT 26
1846#define I40E_PRT_MNG_MDEF_MULTICAST_AND_MASK (0x1 << I40E_PRT_MNG_MDEF_MULTICAST_AND_SHIFT)
1847#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT 27
1848#define I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_ARP_REQUEST_OR_SHIFT)
1849#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT 28
1850#define I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_ARP_RESPONSE_OR_SHIFT)
1851#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT 29
1852#define I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_NEIGHBOR_DISCOVERY_134_OR_SHIFT)
1853#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT 30
1854#define I40E_PRT_MNG_MDEF_PORT_0X298_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_PORT_0X298_OR_SHIFT)
1855#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT 31
1856#define I40E_PRT_MNG_MDEF_PORT_0X26F_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_PORT_0X26F_OR_SHIFT)
1857#define I40E_PRT_MNG_MDEF_EXT(_i) (0x00255F00 + ((_i) * 32))
1858#define I40E_PRT_MNG_MDEF_EXT_MAX_INDEX 7
1859#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT 0
1860#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_MASK (0xF << I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_AND_SHIFT)
1861#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT 4
1862#define I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_MASK (0xF << I40E_PRT_MNG_MDEF_EXT_L2_ETHERTYPE_OR_SHIFT)
1863#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT 8
1864#define I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_MASK (0xFFFF << I40E_PRT_MNG_MDEF_EXT_FLEX_PORT_OR_SHIFT)
1865#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT 24
1866#define I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_FLEX_TCO_SHIFT)
1867#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT 25
1868#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_135_OR_SHIFT)
1869#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT 26
1870#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_136_OR_SHIFT)
1871#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT 27
1872#define I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_NEIGHBOR_DISCOVERY_137_OR_SHIFT)
1873#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT 28
1874#define I40E_PRT_MNG_MDEF_EXT_ICMP_OR_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_ICMP_OR_SHIFT)
1875#define I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT 29
1876#define I40E_PRT_MNG_MDEF_EXT_MLD_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_MLD_SHIFT)
1877#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT 30
1878#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_APPLY_TO_NETWORK_TRAFFIC_SHIFT)
1879#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT 31
1880#define I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_MASK (0x1 << I40E_PRT_MNG_MDEF_EXT_APPLY_TO_HOST_TRAFFIC_SHIFT)
1881#define I40E_PRT_MNG_MDEFVSI(_i) (0x00256580 + ((_i) * 32)) /* _i=0...3 */
1882#define I40E_PRT_MNG_MDEFVSI_MAX_INDEX 3
1883#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT 0
1884#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_MASK (0xFFFF << I40E_PRT_MNG_MDEFVSI_MDEFVSI_2N_SHIFT)
1885#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT 16
1886#define I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_MASK (0xFFFF << I40E_PRT_MNG_MDEFVSI_MDEFVSI_2NP1_SHIFT)
1887#define I40E_PRT_MNG_METF(_i) (0x00256780 + ((_i) * 32)) /* _i=0...3 */
1888#define I40E_PRT_MNG_METF_MAX_INDEX 3
1889#define I40E_PRT_MNG_METF_ETYPE_SHIFT 0
1890#define I40E_PRT_MNG_METF_ETYPE_MASK (0xFFFF << I40E_PRT_MNG_METF_ETYPE_SHIFT)
1891#define I40E_PRT_MNG_METF_POLARITY_SHIFT 30
1892#define I40E_PRT_MNG_METF_POLARITY_MASK (0x1 << I40E_PRT_MNG_METF_POLARITY_SHIFT)
1893#define I40E_PRT_MNG_MFUTP(_i) (0x00254E00 + ((_i) * 32)) /* _i=0...15 */
1894#define I40E_PRT_MNG_MFUTP_MAX_INDEX 15
1895#define I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT 0
1896#define I40E_PRT_MNG_MFUTP_MFUTP_N_MASK (0xFFFF << I40E_PRT_MNG_MFUTP_MFUTP_N_SHIFT)
1897#define I40E_PRT_MNG_MFUTP_UDP_SHIFT 16
1898#define I40E_PRT_MNG_MFUTP_UDP_MASK (0x1 << I40E_PRT_MNG_MFUTP_UDP_SHIFT)
1899#define I40E_PRT_MNG_MFUTP_TCP_SHIFT 17
1900#define I40E_PRT_MNG_MFUTP_TCP_MASK (0x1 << I40E_PRT_MNG_MFUTP_TCP_SHIFT)
1901#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT 18
1902#define I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_MASK (0x1 << I40E_PRT_MNG_MFUTP_SOURCE_DESTINATION_SHIFT)
1903#define I40E_PRT_MNG_MIPAF4(_i) (0x00256280 + ((_i) * 32)) /* _i=0...3 */
1904#define I40E_PRT_MNG_MIPAF4_MAX_INDEX 3
1905#define I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT 0
1906#define I40E_PRT_MNG_MIPAF4_MIPAF_MASK (0xFFFFFFFF << I40E_PRT_MNG_MIPAF4_MIPAF_SHIFT)
1907#define I40E_PRT_MNG_MIPAF6(_i) (0x00254200 + ((_i) * 32)) /* _i=0...15 */
1908#define I40E_PRT_MNG_MIPAF6_MAX_INDEX 15
1909#define I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT 0
1910#define I40E_PRT_MNG_MIPAF6_MIPAF_MASK (0xFFFFFFFF << I40E_PRT_MNG_MIPAF6_MIPAF_SHIFT)
1911#define I40E_PRT_MNG_MMAH(_i) (0x00256380 + ((_i) * 32)) /* _i=0...3 */
1912#define I40E_PRT_MNG_MMAH_MAX_INDEX 3
1913#define I40E_PRT_MNG_MMAH_MMAH_SHIFT 0
1914#define I40E_PRT_MNG_MMAH_MMAH_MASK (0xFFFF << I40E_PRT_MNG_MMAH_MMAH_SHIFT)
1915#define I40E_PRT_MNG_MMAL(_i) (0x00256480 + ((_i) * 32)) /* _i=0...3 */
1916#define I40E_PRT_MNG_MMAL_MAX_INDEX 3
1917#define I40E_PRT_MNG_MMAL_MMAL_SHIFT 0
1918#define I40E_PRT_MNG_MMAL_MMAL_MASK (0xFFFFFFFF << I40E_PRT_MNG_MMAL_MMAL_SHIFT)
1919#define I40E_PRT_MNG_MNGONLY 0x00256A60
1920#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT 0
1921#define I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_MASK (0xFF << I40E_PRT_MNG_MNGONLY_EXCLUSIVE_TO_MANAGEABILITY_SHIFT)
1922#define I40E_PRT_MNG_MSFM 0x00256AA0
1923#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT 0
1924#define I40E_PRT_MNG_MSFM_PORT_26F_UDP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_26F_UDP_SHIFT)
1925#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT 1
1926#define I40E_PRT_MNG_MSFM_PORT_26F_TCP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_26F_TCP_SHIFT)
1927#define I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT 2
1928#define I40E_PRT_MNG_MSFM_PORT_298_UDP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_298_UDP_SHIFT)
1929#define I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT 3
1930#define I40E_PRT_MNG_MSFM_PORT_298_TCP_MASK (0x1 << I40E_PRT_MNG_MSFM_PORT_298_TCP_SHIFT)
1931#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT 4
1932#define I40E_PRT_MNG_MSFM_IPV6_0_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_0_MASK_SHIFT)
1933#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT 5
1934#define I40E_PRT_MNG_MSFM_IPV6_1_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_1_MASK_SHIFT)
1935#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT 6
1936#define I40E_PRT_MNG_MSFM_IPV6_2_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_2_MASK_SHIFT)
1937#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT 7
1938#define I40E_PRT_MNG_MSFM_IPV6_3_MASK_MASK (0x1 << I40E_PRT_MNG_MSFM_IPV6_3_MASK_SHIFT)
1939#define I40E_MSIX_PBA(_i) (0x00004900 + ((_i) * 4)) /* _i=0...5 */
1940#define I40E_MSIX_PBA_MAX_INDEX 5
1941#define I40E_MSIX_PBA_PENBIT_SHIFT 0
1942#define I40E_MSIX_PBA_PENBIT_MASK (0xFFFFFFFF << I40E_MSIX_PBA_PENBIT_SHIFT)
1943#define I40E_MSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...128 */
1944#define I40E_MSIX_TADD_MAX_INDEX 128
1945#define I40E_MSIX_TADD_MSIXTADD10_SHIFT 0
1946#define I40E_MSIX_TADD_MSIXTADD10_MASK (0x3 << I40E_MSIX_TADD_MSIXTADD10_SHIFT)
1947#define I40E_MSIX_TADD_MSIXTADD_SHIFT 2
1948#define I40E_MSIX_TADD_MSIXTADD_MASK (0x3FFFFFFF << I40E_MSIX_TADD_MSIXTADD_SHIFT)
1949#define I40E_MSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...128 */
1950#define I40E_MSIX_TMSG_MAX_INDEX 128
1951#define I40E_MSIX_TMSG_MSIXTMSG_SHIFT 0
1952#define I40E_MSIX_TMSG_MSIXTMSG_MASK (0xFFFFFFFF << I40E_MSIX_TMSG_MSIXTMSG_SHIFT)
1953#define I40E_MSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...128 */
1954#define I40E_MSIX_TUADD_MAX_INDEX 128
1955#define I40E_MSIX_TUADD_MSIXTUADD_SHIFT 0
1956#define I40E_MSIX_TUADD_MSIXTUADD_MASK (0xFFFFFFFF << I40E_MSIX_TUADD_MSIXTUADD_SHIFT)
1957#define I40E_MSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...128 */
1958#define I40E_MSIX_TVCTRL_MAX_INDEX 128
1959#define I40E_MSIX_TVCTRL_MASK_SHIFT 0
1960#define I40E_MSIX_TVCTRL_MASK_MASK (0x1 << I40E_MSIX_TVCTRL_MASK_SHIFT)
1961#define I40E_VFMSIX_PBA1(_i) (0x00004944 + ((_i) * 4)) /* _i=0...19 */
1962#define I40E_VFMSIX_PBA1_MAX_INDEX 19
1963#define I40E_VFMSIX_PBA1_PENBIT_SHIFT 0
1964#define I40E_VFMSIX_PBA1_PENBIT_MASK (0xFFFFFFFF << I40E_VFMSIX_PBA1_PENBIT_SHIFT)
1965#define I40E_VFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */
1966#define I40E_VFMSIX_TADD1_MAX_INDEX 639
1967#define I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT 0
1968#define I40E_VFMSIX_TADD1_MSIXTADD10_MASK (0x3 << I40E_VFMSIX_TADD1_MSIXTADD10_SHIFT)
1969#define I40E_VFMSIX_TADD1_MSIXTADD_SHIFT 2
1970#define I40E_VFMSIX_TADD1_MSIXTADD_MASK (0x3FFFFFFF << I40E_VFMSIX_TADD1_MSIXTADD_SHIFT)
1971#define I40E_VFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */
1972#define I40E_VFMSIX_TMSG1_MAX_INDEX 639
1973#define I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT 0
1974#define I40E_VFMSIX_TMSG1_MSIXTMSG_MASK (0xFFFFFFFF << I40E_VFMSIX_TMSG1_MSIXTMSG_SHIFT)
1975#define I40E_VFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */
1976#define I40E_VFMSIX_TUADD1_MAX_INDEX 639
1977#define I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT 0
1978#define I40E_VFMSIX_TUADD1_MSIXTUADD_MASK (0xFFFFFFFF << I40E_VFMSIX_TUADD1_MSIXTUADD_SHIFT)
1979#define I40E_VFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */
1980#define I40E_VFMSIX_TVCTRL1_MAX_INDEX 639
1981#define I40E_VFMSIX_TVCTRL1_MASK_SHIFT 0
1982#define I40E_VFMSIX_TVCTRL1_MASK_MASK (0x1 << I40E_VFMSIX_TVCTRL1_MASK_SHIFT)
1983#define I40E_GLNVM_FLA 0x000B6108
1984#define I40E_GLNVM_FLA_FL_SCK_SHIFT 0
1985#define I40E_GLNVM_FLA_FL_SCK_MASK (0x1 << I40E_GLNVM_FLA_FL_SCK_SHIFT)
1986#define I40E_GLNVM_FLA_FL_CE_SHIFT 1
1987#define I40E_GLNVM_FLA_FL_CE_MASK (0x1 << I40E_GLNVM_FLA_FL_CE_SHIFT)
1988#define I40E_GLNVM_FLA_FL_SI_SHIFT 2
1989#define I40E_GLNVM_FLA_FL_SI_MASK (0x1 << I40E_GLNVM_FLA_FL_SI_SHIFT)
1990#define I40E_GLNVM_FLA_FL_SO_SHIFT 3
1991#define I40E_GLNVM_FLA_FL_SO_MASK (0x1 << I40E_GLNVM_FLA_FL_SO_SHIFT)
1992#define I40E_GLNVM_FLA_FL_REQ_SHIFT 4
1993#define I40E_GLNVM_FLA_FL_REQ_MASK (0x1 << I40E_GLNVM_FLA_FL_REQ_SHIFT)
1994#define I40E_GLNVM_FLA_FL_GNT_SHIFT 5
1995#define I40E_GLNVM_FLA_FL_GNT_MASK (0x1 << I40E_GLNVM_FLA_FL_GNT_SHIFT)
1996#define I40E_GLNVM_FLA_LOCKED_SHIFT 6
1997#define I40E_GLNVM_FLA_LOCKED_MASK (0x1 << I40E_GLNVM_FLA_LOCKED_SHIFT)
1998#define I40E_GLNVM_FLA_FL_SADDR_SHIFT 18
1999#define I40E_GLNVM_FLA_FL_SADDR_MASK (0x7FF << I40E_GLNVM_FLA_FL_SADDR_SHIFT)
2000#define I40E_GLNVM_FLA_FL_BUSY_SHIFT 30
2001#define I40E_GLNVM_FLA_FL_BUSY_MASK (0x1 << I40E_GLNVM_FLA_FL_BUSY_SHIFT)
2002#define I40E_GLNVM_FLA_FL_DER_SHIFT 31
2003#define I40E_GLNVM_FLA_FL_DER_MASK (0x1 << I40E_GLNVM_FLA_FL_DER_SHIFT)
2004#define I40E_GLNVM_FLASHID 0x000B6104
2005#define I40E_GLNVM_FLASHID_FLASHID_SHIFT 0
2006#define I40E_GLNVM_FLASHID_FLASHID_MASK (0xFFFFFF << I40E_GLNVM_FLASHID_FLASHID_SHIFT)
2007#define I40E_GLNVM_GENS 0x000B6100
2008#define I40E_GLNVM_GENS_NVM_PRES_SHIFT 0
2009#define I40E_GLNVM_GENS_NVM_PRES_MASK (0x1 << I40E_GLNVM_GENS_NVM_PRES_SHIFT)
2010#define I40E_GLNVM_GENS_SR_SIZE_SHIFT 5
2011#define I40E_GLNVM_GENS_SR_SIZE_MASK (0x7 << I40E_GLNVM_GENS_SR_SIZE_SHIFT)
2012#define I40E_GLNVM_GENS_BANK1VAL_SHIFT 8
2013#define I40E_GLNVM_GENS_BANK1VAL_MASK (0x1 << I40E_GLNVM_GENS_BANK1VAL_SHIFT)
2014#define I40E_GLNVM_GENS_ALT_PRST_SHIFT 23
2015#define I40E_GLNVM_GENS_ALT_PRST_MASK (0x1 << I40E_GLNVM_GENS_ALT_PRST_SHIFT)
2016#define I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT 25
2017#define I40E_GLNVM_GENS_FL_AUTO_RD_MASK (0x1 << I40E_GLNVM_GENS_FL_AUTO_RD_SHIFT)
2018#define I40E_GLNVM_PROTCSR(_i) (0x000B6010 + ((_i) * 4)) /* _i=0...59 */
2019#define I40E_GLNVM_PROTCSR_MAX_INDEX 59
2020#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT 0
2021#define I40E_GLNVM_PROTCSR_ADDR_BLOCK_MASK (0xFFFFFF << I40E_GLNVM_PROTCSR_ADDR_BLOCK_SHIFT)
2022#define I40E_GLNVM_SRCTL 0x000B6110
2023#define I40E_GLNVM_SRCTL_SRBUSY_SHIFT 0
2024#define I40E_GLNVM_SRCTL_SRBUSY_MASK (0x1 << I40E_GLNVM_SRCTL_SRBUSY_SHIFT)
2025#define I40E_GLNVM_SRCTL_ADDR_SHIFT 14
2026#define I40E_GLNVM_SRCTL_ADDR_MASK (0x7FFF << I40E_GLNVM_SRCTL_ADDR_SHIFT)
2027#define I40E_GLNVM_SRCTL_WRITE_SHIFT 29
2028#define I40E_GLNVM_SRCTL_WRITE_MASK (0x1 << I40E_GLNVM_SRCTL_WRITE_SHIFT)
2029#define I40E_GLNVM_SRCTL_START_SHIFT 30
2030#define I40E_GLNVM_SRCTL_START_MASK (0x1 << I40E_GLNVM_SRCTL_START_SHIFT)
2031#define I40E_GLNVM_SRCTL_DONE_SHIFT 31
2032#define I40E_GLNVM_SRCTL_DONE_MASK (0x1 << I40E_GLNVM_SRCTL_DONE_SHIFT)
2033#define I40E_GLNVM_SRDATA 0x000B6114
2034#define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0
2035#define I40E_GLNVM_SRDATA_WRDATA_MASK (0xFFFF << I40E_GLNVM_SRDATA_WRDATA_SHIFT)
2036#define I40E_GLNVM_SRDATA_RDDATA_SHIFT 16
2037#define I40E_GLNVM_SRDATA_RDDATA_MASK (0xFFFF << I40E_GLNVM_SRDATA_RDDATA_SHIFT)
2038#define I40E_GLPCI_BYTCTH 0x0009C484
2039#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT 0
2040#define I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_MASK (0xFFFFFFFF << I40E_GLPCI_BYTCTH_PCI_COUNT_BW_BCT_SHIFT)
2041#define I40E_GLPCI_BYTCTL 0x0009C488
2042#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT 0
2043#define I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_MASK (0xFFFFFFFF << I40E_GLPCI_BYTCTL_PCI_COUNT_BW_BCT_SHIFT)
2044#define I40E_GLPCI_CAPCTRL 0x000BE4A4
2045#define I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT 0
2046#define I40E_GLPCI_CAPCTRL_VPD_EN_MASK (0x1 << I40E_GLPCI_CAPCTRL_VPD_EN_SHIFT)
2047#define I40E_GLPCI_CAPSUP 0x000BE4A8
2048#define I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT 0
2049#define I40E_GLPCI_CAPSUP_PCIE_VER_MASK (0x1 << I40E_GLPCI_CAPSUP_PCIE_VER_SHIFT)
2050#define I40E_GLPCI_CAPSUP_LTR_EN_SHIFT 2
2051#define I40E_GLPCI_CAPSUP_LTR_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_LTR_EN_SHIFT)
2052#define I40E_GLPCI_CAPSUP_TPH_EN_SHIFT 3
2053#define I40E_GLPCI_CAPSUP_TPH_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_TPH_EN_SHIFT)
2054#define I40E_GLPCI_CAPSUP_ARI_EN_SHIFT 4
2055#define I40E_GLPCI_CAPSUP_ARI_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ARI_EN_SHIFT)
2056#define I40E_GLPCI_CAPSUP_IOV_EN_SHIFT 5
2057#define I40E_GLPCI_CAPSUP_IOV_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_IOV_EN_SHIFT)
2058#define I40E_GLPCI_CAPSUP_ACS_EN_SHIFT 6
2059#define I40E_GLPCI_CAPSUP_ACS_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ACS_EN_SHIFT)
2060#define I40E_GLPCI_CAPSUP_SEC_EN_SHIFT 7
2061#define I40E_GLPCI_CAPSUP_SEC_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_SEC_EN_SHIFT)
2062#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT 16
2063#define I40E_GLPCI_CAPSUP_ECRC_GEN_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ECRC_GEN_EN_SHIFT)
2064#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT 17
2065#define I40E_GLPCI_CAPSUP_ECRC_CHK_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_ECRC_CHK_EN_SHIFT)
2066#define I40E_GLPCI_CAPSUP_IDO_EN_SHIFT 18
2067#define I40E_GLPCI_CAPSUP_IDO_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_IDO_EN_SHIFT)
2068#define I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT 19
2069#define I40E_GLPCI_CAPSUP_MSI_MASK_MASK (0x1 << I40E_GLPCI_CAPSUP_MSI_MASK_SHIFT)
2070#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT 20
2071#define I40E_GLPCI_CAPSUP_CSR_CONF_EN_MASK (0x1 << I40E_GLPCI_CAPSUP_CSR_CONF_EN_SHIFT)
2072#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT 30
2073#define I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_MASK (0x1 << I40E_GLPCI_CAPSUP_LOAD_SUBSYS_ID_SHIFT)
2074#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT 31
2075#define I40E_GLPCI_CAPSUP_LOAD_DEV_ID_MASK (0x1 << I40E_GLPCI_CAPSUP_LOAD_DEV_ID_SHIFT)
2076#define I40E_GLPCI_CNF 0x000BE4C0
2077#define I40E_GLPCI_CNF_FLEX10_SHIFT 1
2078#define I40E_GLPCI_CNF_FLEX10_MASK (0x1 << I40E_GLPCI_CNF_FLEX10_SHIFT)
2079#define I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT 2
2080#define I40E_GLPCI_CNF_WAKE_PIN_EN_MASK (0x1 << I40E_GLPCI_CNF_WAKE_PIN_EN_SHIFT)
2081#define I40E_GLPCI_CNF2 0x000BE494
2082#define I40E_GLPCI_CNF2_RO_DIS_SHIFT 0
2083#define I40E_GLPCI_CNF2_RO_DIS_MASK (0x1 << I40E_GLPCI_CNF2_RO_DIS_SHIFT)
2084#define I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT 1
2085#define I40E_GLPCI_CNF2_CACHELINE_SIZE_MASK (0x1 << I40E_GLPCI_CNF2_CACHELINE_SIZE_SHIFT)
2086#define I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT 2
2087#define I40E_GLPCI_CNF2_MSI_X_PF_N_MASK (0x7FF << I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT)
2088#define I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT 13
2089#define I40E_GLPCI_CNF2_MSI_X_VF_N_MASK (0x7FF << I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT)
2090#define I40E_GLPCI_DREVID 0x0009C480
2091#define I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT 0
2092#define I40E_GLPCI_DREVID_DEFAULT_REVID_MASK (0xFF << I40E_GLPCI_DREVID_DEFAULT_REVID_SHIFT)
2093#define I40E_GLPCI_GSCL_1 0x0009C48C
2094#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT 0
2095#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_0_SHIFT)
2096#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT 1
2097#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_1_SHIFT)
2098#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT 2
2099#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_2_SHIFT)
2100#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT 3
2101#define I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_EN_3_SHIFT)
2102#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT 4
2103#define I40E_GLPCI_GSCL_1_LBC_ENABLE_0_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_0_SHIFT)
2104#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT 5
2105#define I40E_GLPCI_GSCL_1_LBC_ENABLE_1_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_1_SHIFT)
2106#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT 6
2107#define I40E_GLPCI_GSCL_1_LBC_ENABLE_2_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_2_SHIFT)
2108#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT 7
2109#define I40E_GLPCI_GSCL_1_LBC_ENABLE_3_MASK (0x1 << I40E_GLPCI_GSCL_1_LBC_ENABLE_3_SHIFT)
2110#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT 8
2111#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EN_SHIFT)
2112#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT 9
2113#define I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_MASK (0x1F << I40E_GLPCI_GSCL_1_PCI_COUNT_LAT_EV_SHIFT)
2114#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT 14
2115#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EN_SHIFT)
2116#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT 15
2117#define I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_MASK (0x1F << I40E_GLPCI_GSCL_1_PCI_COUNT_BW_EV_SHIFT)
2118#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT 28
2119#define I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_64_BIT_EN_SHIFT)
2120#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT 29
2121#define I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_RESET_SHIFT)
2122#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT 30
2123#define I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_STOP_SHIFT)
2124#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT 31
2125#define I40E_GLPCI_GSCL_1_GIO_COUNT_START_MASK (0x1 << I40E_GLPCI_GSCL_1_GIO_COUNT_START_SHIFT)
2126#define I40E_GLPCI_GSCL_2 0x0009C490
2127#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT 0
2128#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_0_SHIFT)
2129#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT 8
2130#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_1_SHIFT)
2131#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT 16
2132#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_2_SHIFT)
2133#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT 24
2134#define I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_MASK (0xFF << I40E_GLPCI_GSCL_2_GIO_EVENT_NUM_3_SHIFT)
2135#define I40E_GLPCI_GSCL_5_8(_i) (0x0009C494 + ((_i) * 4)) /* _i=0...3 */
2136#define I40E_GLPCI_GSCL_5_8_MAX_INDEX 3
2137#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT 0
2138#define I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_MASK (0xFFFF << I40E_GLPCI_GSCL_5_8_LBC_THRESHOLD_N_SHIFT)
2139#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT 16
2140#define I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_MASK (0xFFFF << I40E_GLPCI_GSCL_5_8_LBC_TIMER_N_SHIFT)
2141#define I40E_GLPCI_GSCN_0_3(_i) (0x0009C4A4 + ((_i) * 4)) /* _i=0...3 */
2142#define I40E_GLPCI_GSCN_0_3_MAX_INDEX 3
2143#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT 0
2144#define I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_MASK (0xFFFFFFFF << I40E_GLPCI_GSCN_0_3_EVENT_COUNTER_SHIFT)
2145#define I40E_GLPCI_LATCT 0x0009C4B4
2146#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT 0
2147#define I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_MASK (0xFFFFFFFF << I40E_GLPCI_LATCT_PCI_COUNT_LAT_CT_SHIFT)
2148#define I40E_GLPCI_LBARCTRL 0x000BE484
2149#define I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT 0
2150#define I40E_GLPCI_LBARCTRL_PREFBAR_MASK (0x1 << I40E_GLPCI_LBARCTRL_PREFBAR_SHIFT)
2151#define I40E_GLPCI_LBARCTRL_BAR32_SHIFT 1
2152#define I40E_GLPCI_LBARCTRL_BAR32_MASK (0x1 << I40E_GLPCI_LBARCTRL_BAR32_SHIFT)
2153#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT 3
2154#define I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_MASK (0x1 << I40E_GLPCI_LBARCTRL_FLASH_EXPOSE_SHIFT)
2155#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT 4
2156#define I40E_GLPCI_LBARCTRL_PE_DB_SIZE_MASK (0x3 << I40E_GLPCI_LBARCTRL_PE_DB_SIZE_SHIFT)
2157#define I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT 6
2158#define I40E_GLPCI_LBARCTRL_FL_SIZE_MASK (0x7 << I40E_GLPCI_LBARCTRL_FL_SIZE_SHIFT)
2159#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT 10
2160#define I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_MASK (0x1 << I40E_GLPCI_LBARCTRL_VF_PE_DB_SIZE_SHIFT)
2161#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT 11
2162#define I40E_GLPCI_LBARCTRL_EXROM_SIZE_MASK (0x7 << I40E_GLPCI_LBARCTRL_EXROM_SIZE_SHIFT)
2163#define I40E_GLPCI_LINKCAP 0x000BE4AC
2164#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT 0
2165#define I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_MASK (0x3F << I40E_GLPCI_LINKCAP_LINK_SPEEDS_VECTOR_SHIFT)
2166#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT 6
2167#define I40E_GLPCI_LINKCAP_MAX_PAYLOAD_MASK (0x7 << I40E_GLPCI_LINKCAP_MAX_PAYLOAD_SHIFT)
2168#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT 9
2169#define I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_MASK (0xF << I40E_GLPCI_LINKCAP_MAX_LINK_WIDTH_SHIFT)
2170#define I40E_GLPCI_PCIERR 0x000BE4FC
2171#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT 0
2172#define I40E_GLPCI_PCIERR_PCIE_ERR_REP_MASK (0xFFFFFFFF << I40E_GLPCI_PCIERR_PCIE_ERR_REP_SHIFT)
2173#define I40E_GLPCI_PKTCT 0x0009C4BC
2174#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT 0
2175#define I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_MASK (0xFFFFFFFF << I40E_GLPCI_PKTCT_PCI_COUNT_BW_PCT_SHIFT)
2176#define I40E_GLPCI_PMSUP 0x000BE4B0
2177#define I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT 0
2178#define I40E_GLPCI_PMSUP_ASPM_SUP_MASK (0x3 << I40E_GLPCI_PMSUP_ASPM_SUP_SHIFT)
2179#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT 2
2180#define I40E_GLPCI_PMSUP_L0S_EXIT_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L0S_EXIT_LAT_SHIFT)
2181#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT 5
2182#define I40E_GLPCI_PMSUP_L1_EXIT_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L1_EXIT_LAT_SHIFT)
2183#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT 8
2184#define I40E_GLPCI_PMSUP_L0S_ACC_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L0S_ACC_LAT_SHIFT)
2185#define I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT 11
2186#define I40E_GLPCI_PMSUP_L1_ACC_LAT_MASK (0x7 << I40E_GLPCI_PMSUP_L1_ACC_LAT_SHIFT)
2187#define I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT 14
2188#define I40E_GLPCI_PMSUP_SLOT_CLK_MASK (0x1 << I40E_GLPCI_PMSUP_SLOT_CLK_SHIFT)
2189#define I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT 15
2190#define I40E_GLPCI_PMSUP_OBFF_SUP_MASK (0x3 << I40E_GLPCI_PMSUP_OBFF_SUP_SHIFT)
2191#define I40E_GLPCI_PWRDATA 0x000BE490
2192#define I40E_GLPCI_PWRDATA_D0_POWER_SHIFT 0
2193#define I40E_GLPCI_PWRDATA_D0_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_D0_POWER_SHIFT)
2194#define I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT 8
2195#define I40E_GLPCI_PWRDATA_COMM_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_COMM_POWER_SHIFT)
2196#define I40E_GLPCI_PWRDATA_D3_POWER_SHIFT 16
2197#define I40E_GLPCI_PWRDATA_D3_POWER_MASK (0xFF << I40E_GLPCI_PWRDATA_D3_POWER_SHIFT)
2198#define I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT 24
2199#define I40E_GLPCI_PWRDATA_DATA_SCALE_MASK (0x3 << I40E_GLPCI_PWRDATA_DATA_SCALE_SHIFT)
2200#define I40E_GLPCI_REVID 0x000BE4B4
2201#define I40E_GLPCI_REVID_NVM_REVID_SHIFT 0
2202#define I40E_GLPCI_REVID_NVM_REVID_MASK (0xFF << I40E_GLPCI_REVID_NVM_REVID_SHIFT)
2203#define I40E_GLPCI_SERH 0x000BE49C
2204#define I40E_GLPCI_SERH_SER_NUM_H_SHIFT 0
2205#define I40E_GLPCI_SERH_SER_NUM_H_MASK (0xFFFF << I40E_GLPCI_SERH_SER_NUM_H_SHIFT)
2206#define I40E_GLPCI_SERL 0x000BE498
2207#define I40E_GLPCI_SERL_SER_NUM_L_SHIFT 0
2208#define I40E_GLPCI_SERL_SER_NUM_L_MASK (0xFFFFFFFF << I40E_GLPCI_SERL_SER_NUM_L_SHIFT)
2209#define I40E_GLPCI_SUBSYSID 0x000BE48C
2210#define I40E_GLPCI_SUBSYSID_SUB_VEN_ID_SHIFT 0
2211#define I40E_GLPCI_SUBSYSID_SUB_VEN_ID_MASK (0xFFFF << I40E_GLPCI_SUBSYSID_SUB_VEN_ID_SHIFT)
2212#define I40E_GLPCI_SUBSYSID_SUB_ID_SHIFT 16
2213#define I40E_GLPCI_SUBSYSID_SUB_ID_MASK (0xFFFF << I40E_GLPCI_SUBSYSID_SUB_ID_SHIFT)
2214#define I40E_GLPCI_UPADD 0x000BE4F8
2215#define I40E_GLPCI_UPADD_ADDRESS_SHIFT 1
2216#define I40E_GLPCI_UPADD_ADDRESS_MASK (0x7FFFFFFF << I40E_GLPCI_UPADD_ADDRESS_SHIFT)
2217#define I40E_GLPCI_VFSUP 0x000BE4B8
2218#define I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT 0
2219#define I40E_GLPCI_VFSUP_VF_PREFETCH_MASK (0x1 << I40E_GLPCI_VFSUP_VF_PREFETCH_SHIFT)
2220#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT 1
2221#define I40E_GLPCI_VFSUP_VR_BAR_TYPE_MASK (0x1 << I40E_GLPCI_VFSUP_VR_BAR_TYPE_SHIFT)
2222#define I40E_PF_FUNC_RID 0x0009C000
2223#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT 0
2224#define I40E_PF_FUNC_RID_FUNCTION_NUMBER_MASK (0x7 << I40E_PF_FUNC_RID_FUNCTION_NUMBER_SHIFT)
2225#define I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT 3
2226#define I40E_PF_FUNC_RID_DEVICE_NUMBER_MASK (0x1F << I40E_PF_FUNC_RID_DEVICE_NUMBER_SHIFT)
2227#define I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT 8
2228#define I40E_PF_FUNC_RID_BUS_NUMBER_MASK (0xFF << I40E_PF_FUNC_RID_BUS_NUMBER_SHIFT)
2229#define I40E_PF_PCI_CIAA 0x0009C080
2230#define I40E_PF_PCI_CIAA_ADDRESS_SHIFT 0
2231#define I40E_PF_PCI_CIAA_ADDRESS_MASK (0xFFF << I40E_PF_PCI_CIAA_ADDRESS_SHIFT)
2232#define I40E_PF_PCI_CIAA_VF_NUM_SHIFT 12
2233#define I40E_PF_PCI_CIAA_VF_NUM_MASK (0x7F << I40E_PF_PCI_CIAA_VF_NUM_SHIFT)
2234#define I40E_PF_PCI_CIAD 0x0009C100
2235#define I40E_PF_PCI_CIAD_DATA_SHIFT 0
2236#define I40E_PF_PCI_CIAD_DATA_MASK (0xFFFFFFFF << I40E_PF_PCI_CIAD_DATA_SHIFT)
2237#define I40E_PFPCI_CLASS 0x000BE400
2238#define I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT 0
2239#define I40E_PFPCI_CLASS_STORAGE_CLASS_MASK (0x1 << I40E_PFPCI_CLASS_STORAGE_CLASS_SHIFT)
2240#define I40E_PFPCI_CNF 0x000BE000
2241#define I40E_PFPCI_CNF_MSI_EN_SHIFT 2
2242#define I40E_PFPCI_CNF_MSI_EN_MASK (0x1 << I40E_PFPCI_CNF_MSI_EN_SHIFT)
2243#define I40E_PFPCI_CNF_EXROM_DIS_SHIFT 3
2244#define I40E_PFPCI_CNF_EXROM_DIS_MASK (0x1 << I40E_PFPCI_CNF_EXROM_DIS_SHIFT)
2245#define I40E_PFPCI_CNF_IO_BAR_SHIFT 4
2246#define I40E_PFPCI_CNF_IO_BAR_MASK (0x1 << I40E_PFPCI_CNF_IO_BAR_SHIFT)
2247#define I40E_PFPCI_CNF_INT_PIN_SHIFT 5
2248#define I40E_PFPCI_CNF_INT_PIN_MASK (0x3 << I40E_PFPCI_CNF_INT_PIN_SHIFT)
2249#define I40E_PFPCI_FACTPS 0x0009C180
2250#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT 0
2251#define I40E_PFPCI_FACTPS_FUNC_POWER_STATE_MASK (0x3 << I40E_PFPCI_FACTPS_FUNC_POWER_STATE_SHIFT)
2252#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT 3
2253#define I40E_PFPCI_FACTPS_FUNC_AUX_EN_MASK (0x1 << I40E_PFPCI_FACTPS_FUNC_AUX_EN_SHIFT)
2254#define I40E_PFPCI_FUNC 0x000BE200
2255#define I40E_PFPCI_FUNC_FUNC_DIS_SHIFT 0
2256#define I40E_PFPCI_FUNC_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC_FUNC_DIS_SHIFT)
2257#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT 1
2258#define I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC_ALLOW_FUNC_DIS_SHIFT)
2259#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT 2
2260#define I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_MASK (0x1 << I40E_PFPCI_FUNC_DIS_FUNC_ON_PORT_DIS_SHIFT)
2261#define I40E_PFPCI_FUNC2 0x000BE180
2262#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT 0
2263#define I40E_PFPCI_FUNC2_EMP_FUNC_DIS_MASK (0x1 << I40E_PFPCI_FUNC2_EMP_FUNC_DIS_SHIFT)
2264#define I40E_PFPCI_ICAUSE 0x0009C200
2265#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT 0
2266#define I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_MASK (0xFFFFFFFF << I40E_PFPCI_ICAUSE_PCIE_ERR_CAUSE_SHIFT)
2267#define I40E_PFPCI_IENA 0x0009C280
2268#define I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT 0
2269#define I40E_PFPCI_IENA_PCIE_ERR_EN_MASK (0xFFFFFFFF << I40E_PFPCI_IENA_PCIE_ERR_EN_SHIFT)
2270#define I40E_PFPCI_PFDEVID 0x000BE080
2271#define I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_SHIFT 0
2272#define I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_MASK (0xFFFF << I40E_PFPCI_PFDEVID_PF_DEV_ID_LAN_SHIFT)
2273#define I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_SHIFT 16
2274#define I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_MASK (0xFFFF << I40E_PFPCI_PFDEVID_PF_DEV_ID_SAN_SHIFT)
2275#define I40E_PFPCI_PM 0x000BE300
2276#define I40E_PFPCI_PM_PME_EN_SHIFT 0
2277#define I40E_PFPCI_PM_PME_EN_MASK (0x1 << I40E_PFPCI_PM_PME_EN_SHIFT)
2278#define I40E_PFPCI_STATUS1 0x000BE280
2279#define I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT 0
2280#define I40E_PFPCI_STATUS1_FUNC_VALID_MASK (0x1 << I40E_PFPCI_STATUS1_FUNC_VALID_SHIFT)
2281#define I40E_PFPCI_VFDEVID 0x000BE100
2282#define I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_SHIFT 0
2283#define I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_MASK (0xFFFF << I40E_PFPCI_VFDEVID_VF_DEV_ID_LAN_SHIFT)
2284#define I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_SHIFT 16
2285#define I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_MASK (0xFFFF << I40E_PFPCI_VFDEVID_VF_DEV_ID_SAN_SHIFT)
2286#define I40E_PFPCI_VMINDEX 0x0009C300
2287#define I40E_PFPCI_VMINDEX_VMINDEX_SHIFT 0
2288#define I40E_PFPCI_VMINDEX_VMINDEX_MASK (0x1FF << I40E_PFPCI_VMINDEX_VMINDEX_SHIFT)
2289#define I40E_PFPCI_VMPEND 0x0009C380
2290#define I40E_PFPCI_VMPEND_PENDING_SHIFT 0
2291#define I40E_PFPCI_VMPEND_PENDING_MASK (0x1 << I40E_PFPCI_VMPEND_PENDING_SHIFT)
2292#define I40E_GLPE_CPUSTATUS0 0x0000D040
2293#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT 0
2294#define I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS0_PECPUSTATUS0_SHIFT)
2295#define I40E_GLPE_CPUSTATUS1 0x0000D044
2296#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT 0
2297#define I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS1_PECPUSTATUS1_SHIFT)
2298#define I40E_GLPE_CPUSTATUS2 0x0000D048
2299#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT 0
2300#define I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_MASK (0xFFFFFFFF << I40E_GLPE_CPUSTATUS2_PECPUSTATUS2_SHIFT)
2301#define I40E_GLPE_PFFLMOBJCTRL(_i) (0x0000D480 + ((_i) * 4)) /* _i=0...15 */
2302#define I40E_GLPE_PFFLMOBJCTRL_MAX_INDEX 15
2303#define I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0
2304#define I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK (0x7 << I40E_GLPE_PFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT)
2305#define I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8
2306#define I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_MASK (0x7 << I40E_GLPE_PFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT)
2307#define I40E_GLPE_VFFLMOBJCTRL(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...31 */
2308#define I40E_GLPE_VFFLMOBJCTRL_MAX_INDEX 31
2309#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT 0
2310#define I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_MASK (0x7 << I40E_GLPE_VFFLMOBJCTRL_XMIT_BLOCKSIZE_SHIFT)
2311#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT 8
2312#define I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_MASK (0x7 << I40E_GLPE_VFFLMOBJCTRL_Q1_BLOCKSIZE_SHIFT)
2313#define I40E_GLPE_VFFLMQ1ALLOCERR(_i) (0x0000C700 + ((_i) * 4)) /* _i=0...31 */
2314#define I40E_GLPE_VFFLMQ1ALLOCERR_MAX_INDEX 31
2315#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
2316#define I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_GLPE_VFFLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
2317#define I40E_GLPE_VFFLMXMITALLOCERR(_i) (0x0000C600 + ((_i) * 4)) /* _i=0...31 */
2318#define I40E_GLPE_VFFLMXMITALLOCERR_MAX_INDEX 31
2319#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
2320#define I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_GLPE_VFFLMXMITALLOCERR_ERROR_COUNT_SHIFT)
2321#define I40E_GLPE_VFUDACTRL(_i) (0x0000C000 + ((_i) * 4)) /* _i=0...31 */
2322#define I40E_GLPE_VFUDACTRL_MAX_INDEX 31
2323#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT 0
2324#define I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV4MCFRAGRESBP_SHIFT)
2325#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT 1
2326#define I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV4UCFRAGRESBP_SHIFT)
2327#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT 2
2328#define I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV6MCFRAGRESBP_SHIFT)
2329#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT 3
2330#define I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_MASK (0x1 << I40E_GLPE_VFUDACTRL_IPV6UCFRAGRESBP_SHIFT)
2331#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
2332#define I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_MASK (0x1 << I40E_GLPE_VFUDACTRL_UDPMCFRAGRESFAIL_SHIFT)
2333#define I40E_GLPE_VFUDAUCFBQPN(_i) (0x0000C100 + ((_i) * 4)) /* _i=0...31 */
2334#define I40E_GLPE_VFUDAUCFBQPN_MAX_INDEX 31
2335#define I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT 0
2336#define I40E_GLPE_VFUDAUCFBQPN_QPN_MASK (0x3FFFF << I40E_GLPE_VFUDAUCFBQPN_QPN_SHIFT)
2337#define I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT 31
2338#define I40E_GLPE_VFUDAUCFBQPN_VALID_MASK (0x1 << I40E_GLPE_VFUDAUCFBQPN_VALID_SHIFT)
2339#define I40E_PFPE_AEQALLOC 0x00131180
2340#define I40E_PFPE_AEQALLOC_AECOUNT_SHIFT 0
2341#define I40E_PFPE_AEQALLOC_AECOUNT_MASK (0xFFFFFFFF << I40E_PFPE_AEQALLOC_AECOUNT_SHIFT)
2342#define I40E_PFPE_CCQPHIGH 0x00008200
2343#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
2344#define I40E_PFPE_CCQPHIGH_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_PFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
2345#define I40E_PFPE_CCQPLOW 0x00008180
2346#define I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT 0
2347#define I40E_PFPE_CCQPLOW_PECCQPLOW_MASK (0xFFFFFFFF << I40E_PFPE_CCQPLOW_PECCQPLOW_SHIFT)
2348#define I40E_PFPE_CCQPSTATUS 0x00008100
2349#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
2350#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_MASK (0x1 << I40E_PFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
2351#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
2352#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_MASK (0x1 << I40E_PFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
2353#define I40E_PFPE_CQACK 0x00131100
2354#define I40E_PFPE_CQACK_PECQID_SHIFT 0
2355#define I40E_PFPE_CQACK_PECQID_MASK (0x1FFFF << I40E_PFPE_CQACK_PECQID_SHIFT)
2356#define I40E_PFPE_CQARM 0x00131080
2357#define I40E_PFPE_CQARM_PECQID_SHIFT 0
2358#define I40E_PFPE_CQARM_PECQID_MASK (0x1FFFF << I40E_PFPE_CQARM_PECQID_SHIFT)
2359#define I40E_PFPE_CQPDB 0x00008000
2360#define I40E_PFPE_CQPDB_WQHEAD_SHIFT 0
2361#define I40E_PFPE_CQPDB_WQHEAD_MASK (0x7FF << I40E_PFPE_CQPDB_WQHEAD_SHIFT)
2362#define I40E_PFPE_CQPERRCODES 0x00008880
2363#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
2364#define I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_MASK (0xFFFF << I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
2365#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
2366#define I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
2367#define I40E_PFPE_CQPTAIL 0x00008080
2368#define I40E_PFPE_CQPTAIL_WQTAIL_SHIFT 0
2369#define I40E_PFPE_CQPTAIL_WQTAIL_MASK (0x7FF << I40E_PFPE_CQPTAIL_WQTAIL_SHIFT)
2370#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
2371#define I40E_PFPE_CQPTAIL_CQP_OP_ERR_MASK (0x1 << I40E_PFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
2372#define I40E_PFPE_FLMQ1ALLOCERR 0x00008980
2373#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT 0
2374#define I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_PFPE_FLMQ1ALLOCERR_ERROR_COUNT_SHIFT)
2375#define I40E_PFPE_FLMXMITALLOCERR 0x00008900
2376#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT 0
2377#define I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_MASK (0xFFFF << I40E_PFPE_FLMXMITALLOCERR_ERROR_COUNT_SHIFT)
2378#define I40E_PFPE_IPCONFIG0 0x00008280
2379#define I40E_PFPE_IPCONFIG0_PEIPID_SHIFT 0
2380#define I40E_PFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_PFPE_IPCONFIG0_PEIPID_SHIFT)
2381#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
2382#define I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_PFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
2383#define I40E_PFPE_IPCONFIG0_USEUPPERIDRANGE_SHIFT 17
2384#define I40E_PFPE_IPCONFIG0_USEUPPERIDRANGE_MASK (0x1 << I40E_PFPE_IPCONFIG0_USEUPPERIDRANGE_SHIFT)
2385#define I40E_PFPE_MRTEIDXMASK 0x00008600
2386#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
2387#define I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK (0x1F << I40E_PFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
2388#define I40E_PFPE_RCVUNEXPECTEDERROR 0x00008680
2389#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
2390#define I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_PFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
2391#define I40E_PFPE_TCPNOWTIMER 0x00008580
2392#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
2393#define I40E_PFPE_TCPNOWTIMER_TCP_NOW_MASK (0xFFFFFFFF << I40E_PFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
2394#define I40E_PFPE_UDACTRL 0x00008700
2395#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT 0
2396#define I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV4MCFRAGRESBP_SHIFT)
2397#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT 1
2398#define I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV4UCFRAGRESBP_SHIFT)
2399#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT 2
2400#define I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV6MCFRAGRESBP_SHIFT)
2401#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT 3
2402#define I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_MASK (0x1 << I40E_PFPE_UDACTRL_IPV6UCFRAGRESBP_SHIFT)
2403#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT 4
2404#define I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_MASK (0x1 << I40E_PFPE_UDACTRL_UDPMCFRAGRESFAIL_SHIFT)
2405#define I40E_PFPE_UDAUCFBQPN 0x00008780
2406#define I40E_PFPE_UDAUCFBQPN_QPN_SHIFT 0
2407#define I40E_PFPE_UDAUCFBQPN_QPN_MASK (0x3FFFF << I40E_PFPE_UDAUCFBQPN_QPN_SHIFT)
2408#define I40E_PFPE_UDAUCFBQPN_VALID_SHIFT 31
2409#define I40E_PFPE_UDAUCFBQPN_VALID_MASK (0x1 << I40E_PFPE_UDAUCFBQPN_VALID_SHIFT)
2410#define I40E_PFPE_WQEALLOC 0x00138C00
2411#define I40E_PFPE_WQEALLOC_PEQPID_SHIFT 0
2412#define I40E_PFPE_WQEALLOC_PEQPID_MASK (0x3FFFF << I40E_PFPE_WQEALLOC_PEQPID_SHIFT)
2413#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
2414#define I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_MASK (0xFFF << I40E_PFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
2415#define I40E_VFPE_AEQALLOC(_VF) (0x00130C00 + ((_VF) * 4)) /* _i=0...127 */
2416#define I40E_VFPE_AEQALLOC_MAX_INDEX 127
2417#define I40E_VFPE_AEQALLOC_AECOUNT_SHIFT 0
2418#define I40E_VFPE_AEQALLOC_AECOUNT_MASK (0xFFFFFFFF << I40E_VFPE_AEQALLOC_AECOUNT_SHIFT)
2419#define I40E_VFPE_CCQPHIGH(_VF) (0x00001000 + ((_VF) * 4)) /* _i=0...127 */
2420#define I40E_VFPE_CCQPHIGH_MAX_INDEX 127
2421#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT 0
2422#define I40E_VFPE_CCQPHIGH_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_VFPE_CCQPHIGH_PECCQPHIGH_SHIFT)
2423#define I40E_VFPE_CCQPLOW(_VF) (0x00000C00 + ((_VF) * 4)) /* _i=0...127 */
2424#define I40E_VFPE_CCQPLOW_MAX_INDEX 127
2425#define I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT 0
2426#define I40E_VFPE_CCQPLOW_PECCQPLOW_MASK (0xFFFFFFFF << I40E_VFPE_CCQPLOW_PECCQPLOW_SHIFT)
2427#define I40E_VFPE_CCQPSTATUS(_VF) (0x00000800 + ((_VF) * 4)) /* _i=0...127 */
2428#define I40E_VFPE_CCQPSTATUS_MAX_INDEX 127
2429#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT 0
2430#define I40E_VFPE_CCQPSTATUS_CCQP_DONE_MASK (0x1 << I40E_VFPE_CCQPSTATUS_CCQP_DONE_SHIFT)
2431#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT 31
2432#define I40E_VFPE_CCQPSTATUS_CCQP_ERR_MASK (0x1 << I40E_VFPE_CCQPSTATUS_CCQP_ERR_SHIFT)
2433#define I40E_VFPE_CQACK(_VF) (0x00130800 + ((_VF) * 4)) /* _i=0...127 */
2434#define I40E_VFPE_CQACK_MAX_INDEX 127
2435#define I40E_VFPE_CQACK_PECQID_SHIFT 0
2436#define I40E_VFPE_CQACK_PECQID_MASK (0x1FFFF << I40E_VFPE_CQACK_PECQID_SHIFT)
2437#define I40E_VFPE_CQARM(_VF) (0x00130400 + ((_VF) * 4)) /* _i=0...127 */
2438#define I40E_VFPE_CQARM_MAX_INDEX 127
2439#define I40E_VFPE_CQARM_PECQID_SHIFT 0
2440#define I40E_VFPE_CQARM_PECQID_MASK (0x1FFFF << I40E_VFPE_CQARM_PECQID_SHIFT)
2441#define I40E_VFPE_CQPDB(_VF) (0x00000000 + ((_VF) * 4)) /* _i=0...127 */
2442#define I40E_VFPE_CQPDB_MAX_INDEX 127
2443#define I40E_VFPE_CQPDB_WQHEAD_SHIFT 0
2444#define I40E_VFPE_CQPDB_WQHEAD_MASK (0x7FF << I40E_VFPE_CQPDB_WQHEAD_SHIFT)
2445#define I40E_VFPE_CQPERRCODES(_VF) (0x00001800 + ((_VF) * 4)) /* _i=0...127 */
2446#define I40E_VFPE_CQPERRCODES_MAX_INDEX 127
2447#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT 0
2448#define I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES_CQP_MINOR_CODE_SHIFT)
2449#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT 16
2450#define I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES_CQP_MAJOR_CODE_SHIFT)
2451#define I40E_VFPE_CQPTAIL(_VF) (0x00000400 + ((_VF) * 4)) /* _i=0...127 */
2452#define I40E_VFPE_CQPTAIL_MAX_INDEX 127
2453#define I40E_VFPE_CQPTAIL_WQTAIL_SHIFT 0
2454#define I40E_VFPE_CQPTAIL_WQTAIL_MASK (0x7FF << I40E_VFPE_CQPTAIL_WQTAIL_SHIFT)
2455#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT 31
2456#define I40E_VFPE_CQPTAIL_CQP_OP_ERR_MASK (0x1 << I40E_VFPE_CQPTAIL_CQP_OP_ERR_SHIFT)
2457#define I40E_VFPE_IPCONFIG0(_VF) (0x00001400 + ((_VF) * 4)) /* _i=0...127 */
2458#define I40E_VFPE_IPCONFIG0_MAX_INDEX 127
2459#define I40E_VFPE_IPCONFIG0_PEIPID_SHIFT 0
2460#define I40E_VFPE_IPCONFIG0_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG0_PEIPID_SHIFT)
2461#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT 16
2462#define I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG0_USEENTIREIDRANGE_SHIFT)
2463#define I40E_VFPE_IPCONFIG0_USEUPPERIDRANGE_SHIFT 17
2464#define I40E_VFPE_IPCONFIG0_USEUPPERIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG0_USEUPPERIDRANGE_SHIFT)
2465#define I40E_VFPE_MRTEIDXMASK(_VF) (0x00003000 + ((_VF) * 4)) /* _i=0...127 */
2466#define I40E_VFPE_MRTEIDXMASK_MAX_INDEX 127
2467#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT 0
2468#define I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_MASK (0x1F << I40E_VFPE_MRTEIDXMASK_MRTEIDXMASKBITS_SHIFT)
2469#define I40E_VFPE_RCVUNEXPECTEDERROR(_VF) (0x00003400 + ((_VF) * 4))
2470#define I40E_VFPE_RCVUNEXPECTEDERROR_MAX_INDEX 127
2471#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT 0
2472#define I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_VFPE_RCVUNEXPECTEDERROR_TCP_RX_UNEXP_ERR_SHIFT)
2473#define I40E_VFPE_TCPNOWTIMER(_VF) (0x00002C00 + ((_VF) * 4)) /* _i=0...127 */
2474#define I40E_VFPE_TCPNOWTIMER_MAX_INDEX 127
2475#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT 0
2476#define I40E_VFPE_TCPNOWTIMER_TCP_NOW_MASK (0xFFFFFFFF << I40E_VFPE_TCPNOWTIMER_TCP_NOW_SHIFT)
2477#define I40E_VFPE_WQEALLOC(_VF) (0x00138000 + ((_VF) * 4)) /* _i=0...127 */
2478#define I40E_VFPE_WQEALLOC_MAX_INDEX 127
2479#define I40E_VFPE_WQEALLOC_PEQPID_SHIFT 0
2480#define I40E_VFPE_WQEALLOC_PEQPID_MASK (0x3FFFF << I40E_VFPE_WQEALLOC_PEQPID_SHIFT)
2481#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT 20
2482#define I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_MASK (0xFFF << I40E_VFPE_WQEALLOC_WQE_DESC_INDEX_SHIFT)
2483#define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */
2484#define I40E_GLPES_PFIP4RXDISCARD_MAX_INDEX 15
2485#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
2486#define I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
2487#define I40E_GLPES_PFIP4RXFRAGSHI(_i) (0x00010804 + ((_i) * 8)) /* _i=0...15 */
2488#define I40E_GLPES_PFIP4RXFRAGSHI_MAX_INDEX 15
2489#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
2490#define I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
2491#define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */
2492#define I40E_GLPES_PFIP4RXFRAGSLO_MAX_INDEX 15
2493#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
2494#define I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
2495#define I40E_GLPES_PFIP4RXMCOCTSHI(_i) (0x00010A04 + ((_i) * 8))
2496#define I40E_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX 15
2497#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
2498#define I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
2499#define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8))
2500#define I40E_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX 15
2501#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
2502#define I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
2503#define I40E_GLPES_PFIP4RXMCPKTSHI(_i) (0x00010C04 + ((_i) * 8))
2504#define I40E_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX 15
2505#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
2506#define I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
2507#define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8))
2508#define I40E_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX 15
2509#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
2510#define I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
2511#define I40E_GLPES_PFIP4RXOCTSHI(_i) (0x00010204 + ((_i) * 8)) /* _i=0...15 */
2512#define I40E_GLPES_PFIP4RXOCTSHI_MAX_INDEX 15
2513#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
2514#define I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
2515#define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */
2516#define I40E_GLPES_PFIP4RXOCTSLO_MAX_INDEX 15
2517#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
2518#define I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
2519#define I40E_GLPES_PFIP4RXPKTSHI(_i) (0x00010404 + ((_i) * 8)) /* _i=0...15 */
2520#define I40E_GLPES_PFIP4RXPKTSHI_MAX_INDEX 15
2521#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
2522#define I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
2523#define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */
2524#define I40E_GLPES_PFIP4RXPKTSLO_MAX_INDEX 15
2525#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
2526#define I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
2527#define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */
2528#define I40E_GLPES_PFIP4RXTRUNC_MAX_INDEX 15
2529#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
2530#define I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
2531#define I40E_GLPES_PFIP4TXFRAGSHI(_i) (0x00011E04 + ((_i) * 8)) /* _i=0...15 */
2532#define I40E_GLPES_PFIP4TXFRAGSHI_MAX_INDEX 15
2533#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
2534#define I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
2535#define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */
2536#define I40E_GLPES_PFIP4TXFRAGSLO_MAX_INDEX 15
2537#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
2538#define I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
2539#define I40E_GLPES_PFIP4TXMCOCTSHI(_i) (0x00012004 + ((_i) * 8))
2540#define I40E_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX 15
2541#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
2542#define I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
2543#define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8))
2544#define I40E_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX 15
2545#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
2546#define I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
2547#define I40E_GLPES_PFIP4TXMCPKTSHI(_i) (0x00012204 + ((_i) * 8))
2548#define I40E_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX 15
2549#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
2550#define I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
2551#define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8))
2552#define I40E_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX 15
2553#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
2554#define I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
2555#define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */
2556#define I40E_GLPES_PFIP4TXNOROUTE_MAX_INDEX 15
2557#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
2558#define I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_PFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
2559#define I40E_GLPES_PFIP4TXOCTSHI(_i) (0x00011A04 + ((_i) * 8)) /* _i=0...15 */
2560#define I40E_GLPES_PFIP4TXOCTSHI_MAX_INDEX 15
2561#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
2562#define I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
2563#define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */
2564#define I40E_GLPES_PFIP4TXOCTSLO_MAX_INDEX 15
2565#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
2566#define I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
2567#define I40E_GLPES_PFIP4TXPKTSHI(_i) (0x00011C04 + ((_i) * 8)) /* _i=0...15 */
2568#define I40E_GLPES_PFIP4TXPKTSHI_MAX_INDEX 15
2569#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
2570#define I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
2571#define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */
2572#define I40E_GLPES_PFIP4TXPKTSLO_MAX_INDEX 15
2573#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
2574#define I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
2575#define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */
2576#define I40E_GLPES_PFIP6RXDISCARD_MAX_INDEX 15
2577#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
2578#define I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
2579#define I40E_GLPES_PFIP6RXFRAGSHI(_i) (0x00011404 + ((_i) * 8)) /* _i=0...15 */
2580#define I40E_GLPES_PFIP6RXFRAGSHI_MAX_INDEX 15
2581#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
2582#define I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
2583#define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */
2584#define I40E_GLPES_PFIP6RXFRAGSLO_MAX_INDEX 15
2585#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
2586#define I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
2587#define I40E_GLPES_PFIP6RXMCOCTSHI(_i) (0x00011604 + ((_i) * 8))
2588#define I40E_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX 15
2589#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
2590#define I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
2591#define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8))
2592#define I40E_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX 15
2593#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
2594#define I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
2595#define I40E_GLPES_PFIP6RXMCPKTSHI(_i) (0x00011804 + ((_i) * 8))
2596#define I40E_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX 15
2597#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
2598#define I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
2599#define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8))
2600#define I40E_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX 15
2601#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
2602#define I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
2603#define I40E_GLPES_PFIP6RXOCTSHI(_i) (0x00010E04 + ((_i) * 8)) /* _i=0...15 */
2604#define I40E_GLPES_PFIP6RXOCTSHI_MAX_INDEX 15
2605#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
2606#define I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
2607#define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */
2608#define I40E_GLPES_PFIP6RXOCTSLO_MAX_INDEX 15
2609#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
2610#define I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
2611#define I40E_GLPES_PFIP6RXPKTSHI(_i) (0x00011004 + ((_i) * 8)) /* _i=0...15 */
2612#define I40E_GLPES_PFIP6RXPKTSHI_MAX_INDEX 15
2613#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
2614#define I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
2615#define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */
2616#define I40E_GLPES_PFIP6RXPKTSLO_MAX_INDEX 15
2617#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
2618#define I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
2619#define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */
2620#define I40E_GLPES_PFIP6RXTRUNC_MAX_INDEX 15
2621#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
2622#define I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
2623#define I40E_GLPES_PFIP6TXFRAGSHI(_i) (0x00012804 + ((_i) * 8)) /* _i=0...15 */
2624#define I40E_GLPES_PFIP6TXFRAGSHI_MAX_INDEX 15
2625#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
2626#define I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
2627#define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */
2628#define I40E_GLPES_PFIP6TXFRAGSLO_MAX_INDEX 15
2629#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
2630#define I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
2631#define I40E_GLPES_PFIP6TXMCOCTSHI(_i) (0x00012A04 + ((_i) * 8))
2632#define I40E_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX 15
2633#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
2634#define I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
2635#define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8))
2636#define I40E_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX 15
2637#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
2638#define I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
2639#define I40E_GLPES_PFIP6TXMCPKTSHI(_i) (0x00012C04 + ((_i) * 8))
2640#define I40E_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX 15
2641#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
2642#define I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
2643#define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8))
2644#define I40E_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX 15
2645#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
2646#define I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
2647#define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */
2648#define I40E_GLPES_PFIP6TXNOROUTE_MAX_INDEX 15
2649#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
2650#define I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_PFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
2651#define I40E_GLPES_PFIP6TXOCTSHI(_i) (0x00012404 + ((_i) * 8)) /* _i=0...15 */
2652#define I40E_GLPES_PFIP6TXOCTSHI_MAX_INDEX 15
2653#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
2654#define I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
2655#define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */
2656#define I40E_GLPES_PFIP6TXOCTSLO_MAX_INDEX 15
2657#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
2658#define I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
2659#define I40E_GLPES_PFIP6TXPKTSHI(_i) (0x00012604 + ((_i) * 8)) /* _i=0...15 */
2660#define I40E_GLPES_PFIP6TXPKTSHI_MAX_INDEX 15
2661#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
2662#define I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
2663#define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */
2664#define I40E_GLPES_PFIP6TXPKTSLO_MAX_INDEX 15
2665#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
2666#define I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
2667#define I40E_GLPES_PFRDMARXRDSHI(_i) (0x00013E04 + ((_i) * 8)) /* _i=0...15 */
2668#define I40E_GLPES_PFRDMARXRDSHI_MAX_INDEX 15
2669#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
2670#define I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
2671#define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */
2672#define I40E_GLPES_PFRDMARXRDSLO_MAX_INDEX 15
2673#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
2674#define I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
2675#define I40E_GLPES_PFRDMARXSNDSHI(_i) (0x00014004 + ((_i) * 8)) /* _i=0...15 */
2676#define I40E_GLPES_PFRDMARXSNDSHI_MAX_INDEX 15
2677#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
2678#define I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
2679#define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */
2680#define I40E_GLPES_PFRDMARXSNDSLO_MAX_INDEX 15
2681#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
2682#define I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
2683#define I40E_GLPES_PFRDMARXWRSHI(_i) (0x00013C04 + ((_i) * 8)) /* _i=0...15 */
2684#define I40E_GLPES_PFRDMARXWRSHI_MAX_INDEX 15
2685#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
2686#define I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
2687#define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */
2688#define I40E_GLPES_PFRDMARXWRSLO_MAX_INDEX 15
2689#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
2690#define I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
2691#define I40E_GLPES_PFRDMATXRDSHI(_i) (0x00014404 + ((_i) * 8)) /* _i=0...15 */
2692#define I40E_GLPES_PFRDMATXRDSHI_MAX_INDEX 15
2693#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
2694#define I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
2695#define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */
2696#define I40E_GLPES_PFRDMATXRDSLO_MAX_INDEX 15
2697#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
2698#define I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
2699#define I40E_GLPES_PFRDMATXSNDSHI(_i) (0x00014604 + ((_i) * 8)) /* _i=0...15 */
2700#define I40E_GLPES_PFRDMATXSNDSHI_MAX_INDEX 15
2701#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
2702#define I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
2703#define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */
2704#define I40E_GLPES_PFRDMATXSNDSLO_MAX_INDEX 15
2705#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
2706#define I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
2707#define I40E_GLPES_PFRDMATXWRSHI(_i) (0x00014204 + ((_i) * 8)) /* _i=0...15 */
2708#define I40E_GLPES_PFRDMATXWRSHI_MAX_INDEX 15
2709#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
2710#define I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
2711#define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */
2712#define I40E_GLPES_PFRDMATXWRSLO_MAX_INDEX 15
2713#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
2714#define I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
2715#define I40E_GLPES_PFRDMAVBNDHI(_i) (0x00014804 + ((_i) * 8)) /* _i=0...15 */
2716#define I40E_GLPES_PFRDMAVBNDHI_MAX_INDEX 15
2717#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
2718#define I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
2719#define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */
2720#define I40E_GLPES_PFRDMAVBNDLO_MAX_INDEX 15
2721#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
2722#define I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
2723#define I40E_GLPES_PFRDMAVINVHI(_i) (0x00014A04 + ((_i) * 8)) /* _i=0...15 */
2724#define I40E_GLPES_PFRDMAVINVHI_MAX_INDEX 15
2725#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT 0
2726#define I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVINVHI_RDMAVINVHI_SHIFT)
2727#define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */
2728#define I40E_GLPES_PFRDMAVINVLO_MAX_INDEX 15
2729#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT 0
2730#define I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_MASK (0xFFFFFFFF << I40E_GLPES_PFRDMAVINVLO_RDMAVINVLO_SHIFT)
2731#define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */
2732#define I40E_GLPES_PFRXVLANERR_MAX_INDEX 15
2733#define I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT 0
2734#define I40E_GLPES_PFRXVLANERR_RXVLANERR_MASK (0xFFFFFF << I40E_GLPES_PFRXVLANERR_RXVLANERR_SHIFT)
2735#define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */
2736#define I40E_GLPES_PFTCPRTXSEG_MAX_INDEX 15
2737#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT 0
2738#define I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPRTXSEG_TCPRTXSEG_SHIFT)
2739#define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */
2740#define I40E_GLPES_PFTCPRXOPTERR_MAX_INDEX 15
2741#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
2742#define I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_MASK (0xFFFFFF << I40E_GLPES_PFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
2743#define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4))
2744#define I40E_GLPES_PFTCPRXPROTOERR_MAX_INDEX 15
2745#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
2746#define I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_MASK (0xFFFFFF << I40E_GLPES_PFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
2747#define I40E_GLPES_PFTCPRXSEGSHI(_i) (0x00013004 + ((_i) * 8)) /* _i=0...15 */
2748#define I40E_GLPES_PFTCPRXSEGSHI_MAX_INDEX 15
2749#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
2750#define I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_MASK (0xFFFF << I40E_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
2751#define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */
2752#define I40E_GLPES_PFTCPRXSEGSLO_MAX_INDEX 15
2753#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
2754#define I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
2755#define I40E_GLPES_PFTCPTXSEGHI(_i) (0x00013404 + ((_i) * 8)) /* _i=0...15 */
2756#define I40E_GLPES_PFTCPTXSEGHI_MAX_INDEX 15
2757#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
2758#define I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_MASK (0xFFFF << I40E_GLPES_PFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
2759#define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */
2760#define I40E_GLPES_PFTCPTXSEGLO_MAX_INDEX 15
2761#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
2762#define I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_MASK (0xFFFFFFFF << I40E_GLPES_PFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
2763#define I40E_GLPES_PFUDPRXPKTSHI(_i) (0x00013804 + ((_i) * 8)) /* _i=0...15 */
2764#define I40E_GLPES_PFUDPRXPKTSHI_MAX_INDEX 15
2765#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
2766#define I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
2767#define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */
2768#define I40E_GLPES_PFUDPRXPKTSLO_MAX_INDEX 15
2769#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
2770#define I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
2771#define I40E_GLPES_PFUDPTXPKTSHI(_i) (0x00013A04 + ((_i) * 8)) /* _i=0...15 */
2772#define I40E_GLPES_PFUDPTXPKTSHI_MAX_INDEX 15
2773#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
2774#define I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_MASK (0xFFFF << I40E_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
2775#define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */
2776#define I40E_GLPES_PFUDPTXPKTSLO_MAX_INDEX 15
2777#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
2778#define I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
2779#define I40E_GLPES_RDMARXMULTFPDUSHI 0x0001E014
2780#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT 0
2781#define I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_MASK (0xFFFFFF << I40E_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_SHIFT)
2782#define I40E_GLPES_RDMARXMULTFPDUSLO 0x0001E010
2783#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT 0
2784#define I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_SHIFT)
2785#define I40E_GLPES_RDMARXOOODDPHI 0x0001E01C
2786#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT 0
2787#define I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_MASK (0xFFFFFF << I40E_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_SHIFT)
2788#define I40E_GLPES_RDMARXOOODDPLO 0x0001E018
2789#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT 0
2790#define I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_SHIFT)
2791#define I40E_GLPES_RDMARXOOONOMARK 0x0001E004
2792#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT 0
2793#define I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXOOONOMARK_RDMAOOONOMARK_SHIFT)
2794#define I40E_GLPES_RDMARXUNALIGN 0x0001E000
2795#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT 0
2796#define I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_MASK (0xFFFFFFFF << I40E_GLPES_RDMARXUNALIGN_RDMRXAUNALIGN_SHIFT)
2797#define I40E_GLPES_TCPRXFOURHOLEHI 0x0001E044
2798#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT 0
2799#define I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_SHIFT)
2800#define I40E_GLPES_TCPRXFOURHOLELO 0x0001E040
2801#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT 0
2802#define I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_SHIFT)
2803#define I40E_GLPES_TCPRXONEHOLEHI 0x0001E02C
2804#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT 0
2805#define I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_SHIFT)
2806#define I40E_GLPES_TCPRXONEHOLELO 0x0001E028
2807#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT 0
2808#define I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_SHIFT)
2809#define I40E_GLPES_TCPRXPUREACKHI 0x0001E024
2810#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT 0
2811#define I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXPUREACKHI_TCPRXPUREACKSHI_SHIFT)
2812#define I40E_GLPES_TCPRXPUREACKSLO 0x0001E020
2813#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT 0
2814#define I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_SHIFT)
2815#define I40E_GLPES_TCPRXTHREEHOLEHI 0x0001E03C
2816#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT 0
2817#define I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_SHIFT)
2818#define I40E_GLPES_TCPRXTHREEHOLELO 0x0001E038
2819#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT 0
2820#define I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_SHIFT)
2821#define I40E_GLPES_TCPRXTWOHOLEHI 0x0001E034
2822#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT 0
2823#define I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_MASK (0xFFFFFF << I40E_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_SHIFT)
2824#define I40E_GLPES_TCPRXTWOHOLELO 0x0001E030
2825#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT 0
2826#define I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_MASK (0xFFFFFFFF << I40E_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_SHIFT)
2827#define I40E_GLPES_TCPRXUNEXPERR 0x0001E008
2828#define I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_SHIFT 0
2829#define I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_MASK (0xFFFFFF << I40E_GLPES_TCPRXUNEXPERR_TCPRXUNEXPERR_SHIFT)
2830#define I40E_GLPES_TCPTXRETRANSFASTHI 0x0001E04C
2831#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT 0
2832#define I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_SHIFT)
2833#define I40E_GLPES_TCPTXRETRANSFASTLO 0x0001E048
2834#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT 0
2835#define I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_SHIFT)
2836#define I40E_GLPES_TCPTXTOUTSFASTHI 0x0001E054
2837#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT 0
2838#define I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_SHIFT)
2839#define I40E_GLPES_TCPTXTOUTSFASTLO 0x0001E050
2840#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT 0
2841#define I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_SHIFT)
2842#define I40E_GLPES_TCPTXTOUTSHI 0x0001E05C
2843#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT 0
2844#define I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_MASK (0xFFFFFF << I40E_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_SHIFT)
2845#define I40E_GLPES_TCPTXTOUTSLO 0x0001E058
2846#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT 0
2847#define I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_MASK (0xFFFFFFFF << I40E_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_SHIFT)
2848#define I40E_GLPES_VFIP4RXDISCARD(_i) (0x00018600 + ((_i) * 4)) /* _i=0...31 */
2849#define I40E_GLPES_VFIP4RXDISCARD_MAX_INDEX 31
2850#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT 0
2851#define I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXDISCARD_IP4RXDISCARD_SHIFT)
2852#define I40E_GLPES_VFIP4RXFRAGSHI(_i) (0x00018804 + ((_i) * 4)) /* _i=0...31 */
2853#define I40E_GLPES_VFIP4RXFRAGSHI_MAX_INDEX 31
2854#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT 0
2855#define I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXFRAGSHI_IP4RXFRAGSHI_SHIFT)
2856#define I40E_GLPES_VFIP4RXFRAGSLO(_i) (0x00018800 + ((_i) * 4)) /* _i=0...31 */
2857#define I40E_GLPES_VFIP4RXFRAGSLO_MAX_INDEX 31
2858#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT 0
2859#define I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXFRAGSLO_IP4RXFRAGSLO_SHIFT)
2860#define I40E_GLPES_VFIP4RXMCOCTSHI(_i) (0x00018A04 + ((_i) * 4))
2861#define I40E_GLPES_VFIP4RXMCOCTSHI_MAX_INDEX 31
2862#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT 0
2863#define I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXMCOCTSHI_IP4RXMCOCTSHI_SHIFT)
2864#define I40E_GLPES_VFIP4RXMCOCTSLO(_i) (0x00018A00 + ((_i) * 4))
2865#define I40E_GLPES_VFIP4RXMCOCTSLO_MAX_INDEX 31
2866#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT 0
2867#define I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXMCOCTSLO_IP4RXMCOCTSLO_SHIFT)
2868#define I40E_GLPES_VFIP4RXMCPKTSHI(_i) (0x00018C04 + ((_i) * 4))
2869#define I40E_GLPES_VFIP4RXMCPKTSHI_MAX_INDEX 31
2870#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT 0
2871#define I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXMCPKTSHI_IP4RXMCPKTSHI_SHIFT)
2872#define I40E_GLPES_VFIP4RXMCPKTSLO(_i) (0x00018C00 + ((_i) * 4))
2873#define I40E_GLPES_VFIP4RXMCPKTSLO_MAX_INDEX 31
2874#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT 0
2875#define I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXMCPKTSLO_IP4RXMCPKTSLO_SHIFT)
2876#define I40E_GLPES_VFIP4RXOCTSHI(_i) (0x00018204 + ((_i) * 4)) /* _i=0...31 */
2877#define I40E_GLPES_VFIP4RXOCTSHI_MAX_INDEX 31
2878#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT 0
2879#define I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXOCTSHI_IP4RXOCTSHI_SHIFT)
2880#define I40E_GLPES_VFIP4RXOCTSLO(_i) (0x00018200 + ((_i) * 4)) /* _i=0...31 */
2881#define I40E_GLPES_VFIP4RXOCTSLO_MAX_INDEX 31
2882#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT 0
2883#define I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXOCTSLO_IP4RXOCTSLO_SHIFT)
2884#define I40E_GLPES_VFIP4RXPKTSHI(_i) (0x00018404 + ((_i) * 4)) /* _i=0...31 */
2885#define I40E_GLPES_VFIP4RXPKTSHI_MAX_INDEX 31
2886#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT 0
2887#define I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4RXPKTSHI_IP4RXPKTSHI_SHIFT)
2888#define I40E_GLPES_VFIP4RXPKTSLO(_i) (0x00018400 + ((_i) * 4)) /* _i=0...31 */
2889#define I40E_GLPES_VFIP4RXPKTSLO_MAX_INDEX 31
2890#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT 0
2891#define I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXPKTSLO_IP4RXPKTSLO_SHIFT)
2892#define I40E_GLPES_VFIP4RXTRUNC(_i) (0x00018700 + ((_i) * 4)) /* _i=0...31 */
2893#define I40E_GLPES_VFIP4RXTRUNC_MAX_INDEX 31
2894#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT 0
2895#define I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4RXTRUNC_IP4RXTRUNC_SHIFT)
2896#define I40E_GLPES_VFIP4TXFRAGSHI(_i) (0x00019E04 + ((_i) * 4)) /* _i=0...31 */
2897#define I40E_GLPES_VFIP4TXFRAGSHI_MAX_INDEX 31
2898#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT 0
2899#define I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXFRAGSHI_IP4TXFRAGSHI_SHIFT)
2900#define I40E_GLPES_VFIP4TXFRAGSLO(_i) (0x00019E00 + ((_i) * 4)) /* _i=0...31 */
2901#define I40E_GLPES_VFIP4TXFRAGSLO_MAX_INDEX 31
2902#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT 0
2903#define I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXFRAGSLO_IP4TXFRAGSLO_SHIFT)
2904#define I40E_GLPES_VFIP4TXMCOCTSHI(_i) (0x0001A004 + ((_i) * 4))
2905#define I40E_GLPES_VFIP4TXMCOCTSHI_MAX_INDEX 31
2906#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT 0
2907#define I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXMCOCTSHI_IP4TXMCOCTSHI_SHIFT)
2908#define I40E_GLPES_VFIP4TXMCOCTSLO(_i) (0x0001A000 + ((_i) * 4))
2909#define I40E_GLPES_VFIP4TXMCOCTSLO_MAX_INDEX 31
2910#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT 0
2911#define I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXMCOCTSLO_IP4TXMCOCTSLO_SHIFT)
2912#define I40E_GLPES_VFIP4TXMCPKTSHI(_i) (0x0001A204 + ((_i) * 4))
2913#define I40E_GLPES_VFIP4TXMCPKTSHI_MAX_INDEX 31
2914#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT 0
2915#define I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXMCPKTSHI_IP4TXMCPKTSHI_SHIFT)
2916#define I40E_GLPES_VFIP4TXMCPKTSLO(_i) (0x0001A200 + ((_i) * 4))
2917#define I40E_GLPES_VFIP4TXMCPKTSLO_MAX_INDEX 31
2918#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT 0
2919#define I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXMCPKTSLO_IP4TXMCPKTSLO_SHIFT)
2920#define I40E_GLPES_VFIP4TXNOROUTE(_i) (0x0001AE00 + ((_i) * 4)) /* _i=0...31 */
2921#define I40E_GLPES_VFIP4TXNOROUTE_MAX_INDEX 31
2922#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT 0
2923#define I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_VFIP4TXNOROUTE_IP4TXNOROUTE_SHIFT)
2924#define I40E_GLPES_VFIP4TXOCTSHI(_i) (0x00019A04 + ((_i) * 4)) /* _i=0...31 */
2925#define I40E_GLPES_VFIP4TXOCTSHI_MAX_INDEX 31
2926#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT 0
2927#define I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXOCTSHI_IP4TXOCTSHI_SHIFT)
2928#define I40E_GLPES_VFIP4TXOCTSLO(_i) (0x00019A00 + ((_i) * 4)) /* _i=0...31 */
2929#define I40E_GLPES_VFIP4TXOCTSLO_MAX_INDEX 31
2930#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT 0
2931#define I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXOCTSLO_IP4TXOCTSLO_SHIFT)
2932#define I40E_GLPES_VFIP4TXPKTSHI(_i) (0x00019C04 + ((_i) * 4)) /* _i=0...31 */
2933#define I40E_GLPES_VFIP4TXPKTSHI_MAX_INDEX 31
2934#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT 0
2935#define I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP4TXPKTSHI_IP4TXPKTSHI_SHIFT)
2936#define I40E_GLPES_VFIP4TXPKTSLO(_i) (0x00019C00 + ((_i) * 4)) /* _i=0...31 */
2937#define I40E_GLPES_VFIP4TXPKTSLO_MAX_INDEX 31
2938#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT 0
2939#define I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP4TXPKTSLO_IP4TXPKTSLO_SHIFT)
2940#define I40E_GLPES_VFIP6RXDISCARD(_i) (0x00019200 + ((_i) * 4)) /* _i=0...31 */
2941#define I40E_GLPES_VFIP6RXDISCARD_MAX_INDEX 31
2942#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT 0
2943#define I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXDISCARD_IP6RXDISCARD_SHIFT)
2944#define I40E_GLPES_VFIP6RXFRAGSHI(_i) (0x00019404 + ((_i) * 4)) /* _i=0...31 */
2945#define I40E_GLPES_VFIP6RXFRAGSHI_MAX_INDEX 31
2946#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT 0
2947#define I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXFRAGSHI_IP6RXFRAGSHI_SHIFT)
2948#define I40E_GLPES_VFIP6RXFRAGSLO(_i) (0x00019400 + ((_i) * 4)) /* _i=0...31 */
2949#define I40E_GLPES_VFIP6RXFRAGSLO_MAX_INDEX 31
2950#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT 0
2951#define I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXFRAGSLO_IP6RXFRAGSLO_SHIFT)
2952#define I40E_GLPES_VFIP6RXMCOCTSHI(_i) (0x00019604 + ((_i) * 4))
2953#define I40E_GLPES_VFIP6RXMCOCTSHI_MAX_INDEX 31
2954#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT 0
2955#define I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXMCOCTSHI_IP6RXMCOCTSHI_SHIFT)
2956#define I40E_GLPES_VFIP6RXMCOCTSLO(_i) (0x00019600 + ((_i) * 4))
2957#define I40E_GLPES_VFIP6RXMCOCTSLO_MAX_INDEX 31
2958#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT 0
2959#define I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXMCOCTSLO_IP6RXMCOCTSLO_SHIFT)
2960#define I40E_GLPES_VFIP6RXMCPKTSHI(_i) (0x00019804 + ((_i) * 4))
2961#define I40E_GLPES_VFIP6RXMCPKTSHI_MAX_INDEX 31
2962#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT 0
2963#define I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXMCPKTSHI_IP6RXMCPKTSHI_SHIFT)
2964#define I40E_GLPES_VFIP6RXMCPKTSLO(_i) (0x00019800 + ((_i) * 4))
2965#define I40E_GLPES_VFIP6RXMCPKTSLO_MAX_INDEX 31
2966#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT 0
2967#define I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXMCPKTSLO_IP6RXMCPKTSLO_SHIFT)
2968#define I40E_GLPES_VFIP6RXOCTSHI(_i) (0x00018E04 + ((_i) * 4)) /* _i=0...31 */
2969#define I40E_GLPES_VFIP6RXOCTSHI_MAX_INDEX 31
2970#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT 0
2971#define I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXOCTSHI_IP6RXOCTSHI_SHIFT)
2972#define I40E_GLPES_VFIP6RXOCTSLO(_i) (0x00018E00 + ((_i) * 4)) /* _i=0...31 */
2973#define I40E_GLPES_VFIP6RXOCTSLO_MAX_INDEX 31
2974#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT 0
2975#define I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXOCTSLO_IP6RXOCTSLO_SHIFT)
2976#define I40E_GLPES_VFIP6RXPKTSHI(_i) (0x00019004 + ((_i) * 4)) /* _i=0...31 */
2977#define I40E_GLPES_VFIP6RXPKTSHI_MAX_INDEX 31
2978#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT 0
2979#define I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6RXPKTSHI_IP6RXPKTSHI_SHIFT)
2980#define I40E_GLPES_VFIP6RXPKTSLO(_i) (0x00019000 + ((_i) * 4)) /* _i=0...31 */
2981#define I40E_GLPES_VFIP6RXPKTSLO_MAX_INDEX 31
2982#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT 0
2983#define I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXPKTSLO_IP6RXPKTSLO_SHIFT)
2984#define I40E_GLPES_VFIP6RXTRUNC(_i) (0x00019300 + ((_i) * 4)) /* _i=0...31 */
2985#define I40E_GLPES_VFIP6RXTRUNC_MAX_INDEX 31
2986#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT 0
2987#define I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6RXTRUNC_IP6RXTRUNC_SHIFT)
2988#define I40E_GLPES_VFIP6TXFRAGSHI(_i) (0x0001A804 + ((_i) * 4)) /* _i=0...31 */
2989#define I40E_GLPES_VFIP6TXFRAGSHI_MAX_INDEX 31
2990#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT 0
2991#define I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXFRAGSHI_IP6TXFRAGSHI_SHIFT)
2992#define I40E_GLPES_VFIP6TXFRAGSLO(_i) (0x0001A800 + ((_i) * 4)) /* _i=0...31 */
2993#define I40E_GLPES_VFIP6TXFRAGSLO_MAX_INDEX 31
2994#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT 0
2995#define I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXFRAGSLO_IP6TXFRAGSLO_SHIFT)
2996#define I40E_GLPES_VFIP6TXMCOCTSHI(_i) (0x0001AA04 + ((_i) * 4))
2997#define I40E_GLPES_VFIP6TXMCOCTSHI_MAX_INDEX 31
2998#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT 0
2999#define I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXMCOCTSHI_IP6TXMCOCTSHI_SHIFT)
3000#define I40E_GLPES_VFIP6TXMCOCTSLO(_i) (0x0001AA00 + ((_i) * 4))
3001#define I40E_GLPES_VFIP6TXMCOCTSLO_MAX_INDEX 31
3002#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT 0
3003#define I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXMCOCTSLO_IP6TXMCOCTSLO_SHIFT)
3004#define I40E_GLPES_VFIP6TXMCPKTSHI(_i) (0x0001AC04 + ((_i) * 4))
3005#define I40E_GLPES_VFIP6TXMCPKTSHI_MAX_INDEX 31
3006#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT 0
3007#define I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXMCPKTSHI_IP6TXMCPKTSHI_SHIFT)
3008#define I40E_GLPES_VFIP6TXMCPKTSLO(_i) (0x0001AC00 + ((_i) * 4))
3009#define I40E_GLPES_VFIP6TXMCPKTSLO_MAX_INDEX 31
3010#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT 0
3011#define I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXMCPKTSLO_IP6TXMCPKTSLO_SHIFT)
3012#define I40E_GLPES_VFIP6TXNOROUTE(_i) (0x0001AF00 + ((_i) * 4)) /* _i=0...31 */
3013#define I40E_GLPES_VFIP6TXNOROUTE_MAX_INDEX 31
3014#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT 0
3015#define I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_MASK (0xFFFFFF << I40E_GLPES_VFIP6TXNOROUTE_IP6TXNOROUTE_SHIFT)
3016#define I40E_GLPES_VFIP6TXOCTSHI(_i) (0x0001A404 + ((_i) * 4)) /* _i=0...31 */
3017#define I40E_GLPES_VFIP6TXOCTSHI_MAX_INDEX 31
3018#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT 0
3019#define I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXOCTSHI_IP6TXOCTSHI_SHIFT)
3020#define I40E_GLPES_VFIP6TXOCTSLO(_i) (0x0001A400 + ((_i) * 4)) /* _i=0...31 */
3021#define I40E_GLPES_VFIP6TXOCTSLO_MAX_INDEX 31
3022#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT 0
3023#define I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXOCTSLO_IP6TXOCTSLO_SHIFT)
3024#define I40E_GLPES_VFIP6TXPKTSHI(_i) (0x0001A604 + ((_i) * 4)) /* _i=0...31 */
3025#define I40E_GLPES_VFIP6TXPKTSHI_MAX_INDEX 31
3026#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT 0
3027#define I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFIP6TXPKTSHI_IP6TXPKTSHI_SHIFT)
3028#define I40E_GLPES_VFIP6TXPKTSLO(_i) (0x0001A600 + ((_i) * 4)) /* _i=0...31 */
3029#define I40E_GLPES_VFIP6TXPKTSLO_MAX_INDEX 31
3030#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT 0
3031#define I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFIP6TXPKTSLO_IP6TXPKTSLO_SHIFT)
3032#define I40E_GLPES_VFRDMARXRDSHI(_i) (0x0001BE04 + ((_i) * 4)) /* _i=0...31 */
3033#define I40E_GLPES_VFRDMARXRDSHI_MAX_INDEX 31
3034#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT 0
3035#define I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXRDSHI_RDMARXRDSHI_SHIFT)
3036#define I40E_GLPES_VFRDMARXRDSLO(_i) (0x0001BE00 + ((_i) * 4)) /* _i=0...31 */
3037#define I40E_GLPES_VFRDMARXRDSLO_MAX_INDEX 31
3038#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT 0
3039#define I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXRDSLO_RDMARXRDSLO_SHIFT)
3040#define I40E_GLPES_VFRDMARXSNDSHI(_i) (0x0001C004 + ((_i) * 4)) /* _i=0...31 */
3041#define I40E_GLPES_VFRDMARXSNDSHI_MAX_INDEX 31
3042#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT 0
3043#define I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXSNDSHI_RDMARXSNDSHI_SHIFT)
3044#define I40E_GLPES_VFRDMARXSNDSLO(_i) (0x0001C000 + ((_i) * 4)) /* _i=0...31 */
3045#define I40E_GLPES_VFRDMARXSNDSLO_MAX_INDEX 31
3046#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT 0
3047#define I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXSNDSLO_RDMARXSNDSLO_SHIFT)
3048#define I40E_GLPES_VFRDMARXWRSHI(_i) (0x0001BC04 + ((_i) * 4)) /* _i=0...31 */
3049#define I40E_GLPES_VFRDMARXWRSHI_MAX_INDEX 31
3050#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT 0
3051#define I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_VFRDMARXWRSHI_RDMARXWRSHI_SHIFT)
3052#define I40E_GLPES_VFRDMARXWRSLO(_i) (0x0001BC00 + ((_i) * 4)) /* _i=0...31 */
3053#define I40E_GLPES_VFRDMARXWRSLO_MAX_INDEX 31
3054#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT 0
3055#define I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMARXWRSLO_RDMARXWRSLO_SHIFT)
3056#define I40E_GLPES_VFRDMATXRDSHI(_i) (0x0001C404 + ((_i) * 4)) /* _i=0...31 */
3057#define I40E_GLPES_VFRDMATXRDSHI_MAX_INDEX 31
3058#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT 0
3059#define I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXRDSHI_RDMARXRDSHI_SHIFT)
3060#define I40E_GLPES_VFRDMATXRDSLO(_i) (0x0001C400 + ((_i) * 4)) /* _i=0...31 */
3061#define I40E_GLPES_VFRDMATXRDSLO_MAX_INDEX 31
3062#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT 0
3063#define I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXRDSLO_RDMARXRDSLO_SHIFT)
3064#define I40E_GLPES_VFRDMATXSNDSHI(_i) (0x0001C604 + ((_i) * 4)) /* _i=0...31 */
3065#define I40E_GLPES_VFRDMATXSNDSHI_MAX_INDEX 31
3066#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT 0
3067#define I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXSNDSHI_RDMARXSNDSHI_SHIFT)
3068#define I40E_GLPES_VFRDMATXSNDSLO(_i) (0x0001C600 + ((_i) * 4)) /* _i=0...31 */
3069#define I40E_GLPES_VFRDMATXSNDSLO_MAX_INDEX 31
3070#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT 0
3071#define I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXSNDSLO_RDMARXSNDSLO_SHIFT)
3072#define I40E_GLPES_VFRDMATXWRSHI(_i) (0x0001C204 + ((_i) * 4)) /* _i=0...31 */
3073#define I40E_GLPES_VFRDMATXWRSHI_MAX_INDEX 31
3074#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT 0
3075#define I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_MASK (0xFFFF << I40E_GLPES_VFRDMATXWRSHI_RDMARXWRSHI_SHIFT)
3076#define I40E_GLPES_VFRDMATXWRSLO(_i) (0x0001C200 + ((_i) * 4)) /* _i=0...31 */
3077#define I40E_GLPES_VFRDMATXWRSLO_MAX_INDEX 31
3078#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT 0
3079#define I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMATXWRSLO_RDMARXWRSLO_SHIFT)
3080#define I40E_GLPES_VFRDMAVBNDHI(_i) (0x0001C804 + ((_i) * 4)) /* _i=0...31 */
3081#define I40E_GLPES_VFRDMAVBNDHI_MAX_INDEX 31
3082#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT 0
3083#define I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVBNDHI_RDMAVBNDHI_SHIFT)
3084#define I40E_GLPES_VFRDMAVBNDLO(_i) (0x0001C800 + ((_i) * 4)) /* _i=0...31 */
3085#define I40E_GLPES_VFRDMAVBNDLO_MAX_INDEX 31
3086#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT 0
3087#define I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVBNDLO_RDMAVBNDLO_SHIFT)
3088#define I40E_GLPES_VFRDMAVINVHI(_i) (0x0001CA04 + ((_i) * 4)) /* _i=0...31 */
3089#define I40E_GLPES_VFRDMAVINVHI_MAX_INDEX 31
3090#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT 0
3091#define I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVINVHI_RDMAVINVHI_SHIFT)
3092#define I40E_GLPES_VFRDMAVINVLO(_i) (0x0001CA00 + ((_i) * 4)) /* _i=0...31 */
3093#define I40E_GLPES_VFRDMAVINVLO_MAX_INDEX 31
3094#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT 0
3095#define I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_MASK (0xFFFFFFFF << I40E_GLPES_VFRDMAVINVLO_RDMAVINVLO_SHIFT)
3096#define I40E_GLPES_VFRXVLANERR(_i) (0x00018000 + ((_i) * 4)) /* _i=0...31 */
3097#define I40E_GLPES_VFRXVLANERR_MAX_INDEX 31
3098#define I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT 0
3099#define I40E_GLPES_VFRXVLANERR_RXVLANERR_MASK (0xFFFFFF << I40E_GLPES_VFRXVLANERR_RXVLANERR_SHIFT)
3100#define I40E_GLPES_VFTCPRTXSEG(_i) (0x0001B600 + ((_i) * 4)) /* _i=0...31 */
3101#define I40E_GLPES_VFTCPRTXSEG_MAX_INDEX 31
3102#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT 0
3103#define I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPRTXSEG_TCPRTXSEG_SHIFT)
3104#define I40E_GLPES_VFTCPRXOPTERR(_i) (0x0001B200 + ((_i) * 4)) /* _i=0...31 */
3105#define I40E_GLPES_VFTCPRXOPTERR_MAX_INDEX 31
3106#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT 0
3107#define I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_MASK (0xFFFFFF << I40E_GLPES_VFTCPRXOPTERR_TCPRXOPTERR_SHIFT)
3108#define I40E_GLPES_VFTCPRXPROTOERR(_i) (0x0001B300 + ((_i) * 4))
3109#define I40E_GLPES_VFTCPRXPROTOERR_MAX_INDEX 31
3110#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT 0
3111#define I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_MASK (0xFFFFFF << I40E_GLPES_VFTCPRXPROTOERR_TCPRXPROTOERR_SHIFT)
3112#define I40E_GLPES_VFTCPRXSEGSHI(_i) (0x0001B004 + ((_i) * 4)) /* _i=0...31 */
3113#define I40E_GLPES_VFTCPRXSEGSHI_MAX_INDEX 31
3114#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT 0
3115#define I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_MASK (0xFFFF << I40E_GLPES_VFTCPRXSEGSHI_TCPRXSEGSHI_SHIFT)
3116#define I40E_GLPES_VFTCPRXSEGSLO(_i) (0x0001B000 + ((_i) * 4)) /* _i=0...31 */
3117#define I40E_GLPES_VFTCPRXSEGSLO_MAX_INDEX 31
3118#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT 0
3119#define I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPRXSEGSLO_TCPRXSEGSLO_SHIFT)
3120#define I40E_GLPES_VFTCPTXSEGHI(_i) (0x0001B404 + ((_i) * 4)) /* _i=0...31 */
3121#define I40E_GLPES_VFTCPTXSEGHI_MAX_INDEX 31
3122#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT 0
3123#define I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_MASK (0xFFFF << I40E_GLPES_VFTCPTXSEGHI_TCPTXSEGHI_SHIFT)
3124#define I40E_GLPES_VFTCPTXSEGLO(_i) (0x0001B400 + ((_i) * 4)) /* _i=0...31 */
3125#define I40E_GLPES_VFTCPTXSEGLO_MAX_INDEX 31
3126#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT 0
3127#define I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_MASK (0xFFFFFFFF << I40E_GLPES_VFTCPTXSEGLO_TCPTXSEGLO_SHIFT)
3128#define I40E_GLPES_VFUDPRXPKTSHI(_i) (0x0001B804 + ((_i) * 4)) /* _i=0...31 */
3129#define I40E_GLPES_VFUDPRXPKTSHI_MAX_INDEX 31
3130#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT 0
3131#define I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFUDPRXPKTSHI_UDPRXPKTSHI_SHIFT)
3132#define I40E_GLPES_VFUDPRXPKTSLO(_i) (0x0001B800 + ((_i) * 4)) /* _i=0...31 */
3133#define I40E_GLPES_VFUDPRXPKTSLO_MAX_INDEX 31
3134#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT 0
3135#define I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFUDPRXPKTSLO_UDPRXPKTSLO_SHIFT)
3136#define I40E_GLPES_VFUDPTXPKTSHI(_i) (0x0001BA04 + ((_i) * 4)) /* _i=0...31 */
3137#define I40E_GLPES_VFUDPTXPKTSHI_MAX_INDEX 31
3138#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT 0
3139#define I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_MASK (0xFFFF << I40E_GLPES_VFUDPTXPKTSHI_UDPTXPKTSHI_SHIFT)
3140#define I40E_GLPES_VFUDPTXPKTSLO(_i) (0x0001BA00 + ((_i) * 4)) /* _i=0...31 */
3141#define I40E_GLPES_VFUDPTXPKTSLO_MAX_INDEX 31
3142#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT 0
3143#define I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_MASK (0xFFFFFFFF << I40E_GLPES_VFUDPTXPKTSLO_UDPTXPKTSLO_SHIFT)
3144#define I40E_GLPM_DMACR 0x000881F4
3145#define I40E_GLPM_DMACR_DMACWT_SHIFT 0
3146#define I40E_GLPM_DMACR_DMACWT_MASK (0xFFFF << I40E_GLPM_DMACR_DMACWT_SHIFT)
3147#define I40E_GLPM_DMACR_EXIT_DC_SHIFT 29
3148#define I40E_GLPM_DMACR_EXIT_DC_MASK (0x1 << I40E_GLPM_DMACR_EXIT_DC_SHIFT)
3149#define I40E_GLPM_DMACR_LX_COALESCING_INDICATION_SHIFT 30
3150#define I40E_GLPM_DMACR_LX_COALESCING_INDICATION_MASK (0x1 << I40E_GLPM_DMACR_LX_COALESCING_INDICATION_SHIFT)
3151#define I40E_GLPM_DMACR_DMAC_EN_SHIFT 31
3152#define I40E_GLPM_DMACR_DMAC_EN_MASK (0x1 << I40E_GLPM_DMACR_DMAC_EN_SHIFT)
3153#define I40E_GLPM_LTRC 0x000BE500
3154#define I40E_GLPM_LTRC_SLTRV_SHIFT 0
3155#define I40E_GLPM_LTRC_SLTRV_MASK (0x3FF << I40E_GLPM_LTRC_SLTRV_SHIFT)
3156#define I40E_GLPM_LTRC_SSCALE_SHIFT 10
3157#define I40E_GLPM_LTRC_SSCALE_MASK (0x7 << I40E_GLPM_LTRC_SSCALE_SHIFT)
3158#define I40E_GLPM_LTRC_LTRS_REQUIREMENT_SHIFT 15
3159#define I40E_GLPM_LTRC_LTRS_REQUIREMENT_MASK (0x1 << I40E_GLPM_LTRC_LTRS_REQUIREMENT_SHIFT)
3160#define I40E_GLPM_LTRC_NSLTRV_SHIFT 16
3161#define I40E_GLPM_LTRC_NSLTRV_MASK (0x3FF << I40E_GLPM_LTRC_NSLTRV_SHIFT)
3162#define I40E_GLPM_LTRC_NSSCALE_SHIFT 26
3163#define I40E_GLPM_LTRC_NSSCALE_MASK (0x7 << I40E_GLPM_LTRC_NSSCALE_SHIFT)
3164#define I40E_GLPM_LTRC_LTR_SEND_SHIFT 30
3165#define I40E_GLPM_LTRC_LTR_SEND_MASK (0x1 << I40E_GLPM_LTRC_LTR_SEND_SHIFT)
3166#define I40E_GLPM_LTRC_LTRNS_REQUIREMENT_SHIFT 31
3167#define I40E_GLPM_LTRC_LTRNS_REQUIREMENT_MASK (0x1 << I40E_GLPM_LTRC_LTRNS_REQUIREMENT_SHIFT)
3168#define I40E_PRTPM_EEE_STAT 0x001E4320
3169#define I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT 29
3170#define I40E_PRTPM_EEE_STAT_EEE_NEG_MASK (0x1 << I40E_PRTPM_EEE_STAT_EEE_NEG_SHIFT)
3171#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT 30
3172#define I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK (0x1 << I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT)
3173#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT 31
3174#define I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK (0x1 << I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT)
3175#define I40E_PRTPM_EEEC 0x001E4380
3176#define I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT 16
3177#define I40E_PRTPM_EEEC_TW_WAKE_MIN_MASK (0x3F << I40E_PRTPM_EEEC_TW_WAKE_MIN_SHIFT)
3178#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT 24
3179#define I40E_PRTPM_EEEC_TX_LU_LPI_DLY_MASK (0x3 << I40E_PRTPM_EEEC_TX_LU_LPI_DLY_SHIFT)
3180#define I40E_PRTPM_EEEC_TEEE_DLY_SHIFT 26
3181#define I40E_PRTPM_EEEC_TEEE_DLY_MASK (0x3F << I40E_PRTPM_EEEC_TEEE_DLY_SHIFT)
3182#define I40E_PRTPM_EEEFWD 0x001E4400
3183#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT 31
3184#define I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_MASK (0x1 << I40E_PRTPM_EEEFWD_EEE_FW_CONFIG_DONE_SHIFT)
3185#define I40E_PRTPM_EEER 0x001E4360
3186#define I40E_PRTPM_EEER_TW_SYSTEM_SHIFT 0
3187#define I40E_PRTPM_EEER_TW_SYSTEM_MASK (0xFFFF << I40E_PRTPM_EEER_TW_SYSTEM_SHIFT)
3188#define I40E_PRTPM_EEER_TX_LPI_EN_SHIFT 16
3189#define I40E_PRTPM_EEER_TX_LPI_EN_MASK (0x1 << I40E_PRTPM_EEER_TX_LPI_EN_SHIFT)
3190#define I40E_PRTPM_EEETXC 0x001E43E0
3191#define I40E_PRTPM_EEETXC_TW_PHY_SHIFT 0
3192#define I40E_PRTPM_EEETXC_TW_PHY_MASK (0xFFFF << I40E_PRTPM_EEETXC_TW_PHY_SHIFT)
3193#define I40E_PRTPM_GC 0x000B8140
3194#define I40E_PRTPM_GC_EMP_LINK_ON_SHIFT 0
3195#define I40E_PRTPM_GC_EMP_LINK_ON_MASK (0x1 << I40E_PRTPM_GC_EMP_LINK_ON_SHIFT)
3196#define I40E_PRTPM_GC_MNG_VETO_SHIFT 1
3197#define I40E_PRTPM_GC_MNG_VETO_MASK (0x1 << I40E_PRTPM_GC_MNG_VETO_SHIFT)
3198#define I40E_PRTPM_GC_RATD_SHIFT 2
3199#define I40E_PRTPM_GC_RATD_MASK (0x1 << I40E_PRTPM_GC_RATD_SHIFT)
3200#define I40E_PRTPM_GC_LCDMP_SHIFT 3
3201#define I40E_PRTPM_GC_LCDMP_MASK (0x1 << I40E_PRTPM_GC_LCDMP_SHIFT)
3202#define I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT 31
3203#define I40E_PRTPM_GC_LPLU_ASSERTED_MASK (0x1 << I40E_PRTPM_GC_LPLU_ASSERTED_SHIFT)
3204#define I40E_PRTPM_HPTC 0x000AC800
3205#define I40E_PRTPM_HPTC_HIGH_PRI_TC_SHIFT 0
3206#define I40E_PRTPM_HPTC_HIGH_PRI_TC_MASK (0xFF << I40E_PRTPM_HPTC_HIGH_PRI_TC_SHIFT)
3207#define I40E_PRTPM_RLPIC 0x001E43A0
3208#define I40E_PRTPM_RLPIC_ERLPIC_SHIFT 0
3209#define I40E_PRTPM_RLPIC_ERLPIC_MASK (0xFFFFFFFF << I40E_PRTPM_RLPIC_ERLPIC_SHIFT)
3210#define I40E_PRTPM_TLPIC 0x001E43C0
3211#define I40E_PRTPM_TLPIC_ETLPIC_SHIFT 0
3212#define I40E_PRTPM_TLPIC_ETLPIC_MASK (0xFFFFFFFF << I40E_PRTPM_TLPIC_ETLPIC_SHIFT)
3213#define I40E_GLRPB_DPSS 0x000AC828
3214#define I40E_GLRPB_DPSS_DPS_TCN_SHIFT 0
3215#define I40E_GLRPB_DPSS_DPS_TCN_MASK (0xFFFFF << I40E_GLRPB_DPSS_DPS_TCN_SHIFT)
3216#define I40E_GLRPB_GHW 0x000AC830
3217#define I40E_GLRPB_GHW_GHW_SHIFT 0
3218#define I40E_GLRPB_GHW_GHW_MASK (0xFFFFF << I40E_GLRPB_GHW_GHW_SHIFT)
3219#define I40E_GLRPB_GLW 0x000AC834
3220#define I40E_GLRPB_GLW_GLW_SHIFT 0
3221#define I40E_GLRPB_GLW_GLW_MASK (0xFFFFF << I40E_GLRPB_GLW_GLW_SHIFT)
3222#define I40E_GLRPB_PHW 0x000AC844
3223#define I40E_GLRPB_PHW_PHW_SHIFT 0
3224#define I40E_GLRPB_PHW_PHW_MASK (0xFFFFF << I40E_GLRPB_PHW_PHW_SHIFT)
3225#define I40E_GLRPB_PLW 0x000AC848
3226#define I40E_GLRPB_PLW_PLW_SHIFT 0
3227#define I40E_GLRPB_PLW_PLW_MASK (0xFFFFF << I40E_GLRPB_PLW_PLW_SHIFT)
3228#define I40E_PRTRPB_DHW(_i) (0x000AC100 + ((_i) * 32)) /* _i=0...7 */
3229#define I40E_PRTRPB_DHW_MAX_INDEX 7
3230#define I40E_PRTRPB_DHW_DHW_TCN_SHIFT 0
3231#define I40E_PRTRPB_DHW_DHW_TCN_MASK (0xFFFFF << I40E_PRTRPB_DHW_DHW_TCN_SHIFT)
3232#define I40E_PRTRPB_DLW(_i) (0x000AC220 + ((_i) * 32)) /* _i=0...7 */
3233#define I40E_PRTRPB_DLW_MAX_INDEX 7
3234#define I40E_PRTRPB_DLW_DLW_TCN_SHIFT 0
3235#define I40E_PRTRPB_DLW_DLW_TCN_MASK (0xFFFFF << I40E_PRTRPB_DLW_DLW_TCN_SHIFT)
3236#define I40E_PRTRPB_DPS(_i) (0x000AC320 + ((_i) * 32)) /* _i=0...7 */
3237#define I40E_PRTRPB_DPS_MAX_INDEX 7
3238#define I40E_PRTRPB_DPS_DPS_TCN_SHIFT 0
3239#define I40E_PRTRPB_DPS_DPS_TCN_MASK (0xFFFFF << I40E_PRTRPB_DPS_DPS_TCN_SHIFT)
3240#define I40E_PRTRPB_SHT(_i) (0x000AC480 + ((_i) * 32)) /* _i=0...7 */
3241#define I40E_PRTRPB_SHT_MAX_INDEX 7
3242#define I40E_PRTRPB_SHT_SHT_TCN_SHIFT 0
3243#define I40E_PRTRPB_SHT_SHT_TCN_MASK (0xFFFFF << I40E_PRTRPB_SHT_SHT_TCN_SHIFT)
3244#define I40E_PRTRPB_SHW 0x000AC580
3245#define I40E_PRTRPB_SHW_SHW_SHIFT 0
3246#define I40E_PRTRPB_SHW_SHW_MASK (0xFFFFF << I40E_PRTRPB_SHW_SHW_SHIFT)
3247#define I40E_PRTRPB_SLT(_i) (0x000AC5A0 + ((_i) * 32)) /* _i=0...7 */
3248#define I40E_PRTRPB_SLT_MAX_INDEX 7
3249#define I40E_PRTRPB_SLT_SLT_TCN_SHIFT 0
3250#define I40E_PRTRPB_SLT_SLT_TCN_MASK (0xFFFFF << I40E_PRTRPB_SLT_SLT_TCN_SHIFT)
3251#define I40E_PRTRPB_SLW 0x000AC6A0
3252#define I40E_PRTRPB_SLW_SLW_SHIFT 0
3253#define I40E_PRTRPB_SLW_SLW_MASK (0xFFFFF << I40E_PRTRPB_SLW_SLW_SHIFT)
3254#define I40E_PRTRPB_SPS 0x000AC7C0
3255#define I40E_PRTRPB_SPS_SPS_SHIFT 0
3256#define I40E_PRTRPB_SPS_SPS_MASK (0xFFFFF << I40E_PRTRPB_SPS_SPS_SHIFT)
3257#define I40E_GLQF_APBVT(_i) (0x00260000 + ((_i) * 4)) /* _i=0...2047 */
3258#define I40E_GLQF_APBVT_MAX_INDEX 2047
3259#define I40E_GLQF_APBVT_APBVT_SHIFT 0
3260#define I40E_GLQF_APBVT_APBVT_MASK (0xFFFFFFFF << I40E_GLQF_APBVT_APBVT_SHIFT)
3261#define I40E_GLQF_CTL 0x00269BA4
3262#define I40E_GLQF_CTL_HTOEP_SHIFT 1
3263#define I40E_GLQF_CTL_HTOEP_MASK (0x1 << I40E_GLQF_CTL_HTOEP_SHIFT)
3264#define I40E_GLQF_CTL_HTOEP_FCOE_SHIFT 2
3265#define I40E_GLQF_CTL_HTOEP_FCOE_MASK (0x1 << I40E_GLQF_CTL_HTOEP_FCOE_SHIFT)
3266#define I40E_GLQF_CTL_PCNT_ALLOC_SHIFT 3
3267#define I40E_GLQF_CTL_PCNT_ALLOC_MASK (0x7 << I40E_GLQF_CTL_PCNT_ALLOC_SHIFT)
3268#define I40E_GLQF_CTL_DDPLPEN_SHIFT 7
3269#define I40E_GLQF_CTL_DDPLPEN_MASK (0x1 << I40E_GLQF_CTL_DDPLPEN_SHIFT)
3270#define I40E_GLQF_CTL_MAXPEBLEN_SHIFT 8
3271#define I40E_GLQF_CTL_MAXPEBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXPEBLEN_SHIFT)
3272#define I40E_GLQF_CTL_MAXFCBLEN_SHIFT 11
3273#define I40E_GLQF_CTL_MAXFCBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXFCBLEN_SHIFT)
3274#define I40E_GLQF_CTL_MAXFDBLEN_SHIFT 14
3275#define I40E_GLQF_CTL_MAXFDBLEN_MASK (0x7 << I40E_GLQF_CTL_MAXFDBLEN_SHIFT)
3276#define I40E_GLQF_CTL_FDBEST_SHIFT 17
3277#define I40E_GLQF_CTL_FDBEST_MASK (0xFF << I40E_GLQF_CTL_FDBEST_SHIFT)
3278#define I40E_GLQF_CTL_PROGPRIO_SHIFT 25
3279#define I40E_GLQF_CTL_PROGPRIO_MASK (0x1 << I40E_GLQF_CTL_PROGPRIO_SHIFT)
3280#define I40E_GLQF_CTL_INVALPRIO_SHIFT 26
3281#define I40E_GLQF_CTL_INVALPRIO_MASK (0x1 << I40E_GLQF_CTL_INVALPRIO_SHIFT)
3282#define I40E_GLQF_CTL_IGNORE_IP_SHIFT 27
3283#define I40E_GLQF_CTL_IGNORE_IP_MASK (0x1 << I40E_GLQF_CTL_IGNORE_IP_SHIFT)
3284#define I40E_GLQF_FDCNT_0 0x00269BAC
3285#define I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT 0
3286#define I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK (0x1FFF << I40E_GLQF_FDCNT_0_GUARANT_CNT_SHIFT)
3287#define I40E_GLQF_FDCNT_0_BESTCNT_SHIFT 13
3288#define I40E_GLQF_FDCNT_0_BESTCNT_MASK (0x1FFF << I40E_GLQF_FDCNT_0_BESTCNT_SHIFT)
3289#define I40E_GLQF_HSYM(_i) (0x00269D00 + ((_i) * 4)) /* _i=0...63 */
3290#define I40E_GLQF_HSYM_MAX_INDEX 63
3291#define I40E_GLQF_HSYM_SYMH_ENA_SHIFT 0
3292#define I40E_GLQF_HSYM_SYMH_ENA_MASK (0x1 << I40E_GLQF_HSYM_SYMH_ENA_SHIFT)
3293#define I40E_GLQF_PCNT(_i) (0x00266800 + ((_i) * 4)) /* _i=0...511 */
3294#define I40E_GLQF_PCNT_MAX_INDEX 511
3295#define I40E_GLQF_PCNT_PCNT_SHIFT 0
3296#define I40E_GLQF_PCNT_PCNT_MASK (0xFFFFFFFF << I40E_GLQF_PCNT_PCNT_SHIFT)
3297#define I40E_GLQF_SWAP(_i, _j) (0x00267E00 + ((_i) * 4 + (_j) * 8)) /* _i=0...1, _j=0...63 */
3298#define I40E_GLQF_SWAP_MAX_INDEX 1
3299#define I40E_GLQF_SWAP_OFF0_SRC0_SHIFT 0
3300#define I40E_GLQF_SWAP_OFF0_SRC0_MASK (0x3F << I40E_GLQF_SWAP_OFF0_SRC0_SHIFT)
3301#define I40E_GLQF_SWAP_OFF0_SRC1_SHIFT 6
3302#define I40E_GLQF_SWAP_OFF0_SRC1_MASK (0x3F << I40E_GLQF_SWAP_OFF0_SRC1_SHIFT)
3303#define I40E_GLQF_SWAP_FLEN0_SHIFT 12
3304#define I40E_GLQF_SWAP_FLEN0_MASK (0xF << I40E_GLQF_SWAP_FLEN0_SHIFT)
3305#define I40E_GLQF_SWAP_OFF1_SRC0_SHIFT 16
3306#define I40E_GLQF_SWAP_OFF1_SRC0_MASK (0x3F << I40E_GLQF_SWAP_OFF1_SRC0_SHIFT)
3307#define I40E_GLQF_SWAP_OFF1_SRC1_SHIFT 22
3308#define I40E_GLQF_SWAP_OFF1_SRC1_MASK (0x3F << I40E_GLQF_SWAP_OFF1_SRC1_SHIFT)
3309#define I40E_GLQF_SWAP_FLEN1_SHIFT 28
3310#define I40E_GLQF_SWAP_FLEN1_MASK (0xF << I40E_GLQF_SWAP_FLEN1_SHIFT)
3311#define I40E_PFQF_CTL_0 0x001C0AC0
3312#define I40E_PFQF_CTL_0_PEHSIZE_SHIFT 0
3313#define I40E_PFQF_CTL_0_PEHSIZE_MASK (0x1F << I40E_PFQF_CTL_0_PEHSIZE_SHIFT)
3314#define I40E_PFQF_CTL_0_PEDSIZE_SHIFT 5
3315#define I40E_PFQF_CTL_0_PEDSIZE_MASK (0x1F << I40E_PFQF_CTL_0_PEDSIZE_SHIFT)
3316#define I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT 10
3317#define I40E_PFQF_CTL_0_PFFCHSIZE_MASK (0xF << I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT)
3318#define I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT 14
3319#define I40E_PFQF_CTL_0_PFFCDSIZE_MASK (0x3 << I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT)
3320#define I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT 16
3321#define I40E_PFQF_CTL_0_HASHLUTSIZE_MASK (0x1 << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT)
3322#define I40E_PFQF_CTL_0_FD_ENA_SHIFT 17
3323#define I40E_PFQF_CTL_0_FD_ENA_MASK (0x1 << I40E_PFQF_CTL_0_FD_ENA_SHIFT)
3324#define I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT 18
3325#define I40E_PFQF_CTL_0_ETYPE_ENA_MASK (0x1 << I40E_PFQF_CTL_0_ETYPE_ENA_SHIFT)
3326#define I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT 19
3327#define I40E_PFQF_CTL_0_MACVLAN_ENA_MASK (0x1 << I40E_PFQF_CTL_0_MACVLAN_ENA_SHIFT)
3328#define I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT 20
3329#define I40E_PFQF_CTL_0_VFFCHSIZE_MASK (0xF << I40E_PFQF_CTL_0_VFFCHSIZE_SHIFT)
3330#define I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT 24
3331#define I40E_PFQF_CTL_0_VFFCDSIZE_MASK (0x3 << I40E_PFQF_CTL_0_VFFCDSIZE_SHIFT)
3332#define I40E_PFQF_CTL_1 0x00245D80
3333#define I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT 0
3334#define I40E_PFQF_CTL_1_CLEARFDTABLE_MASK (0x1 << I40E_PFQF_CTL_1_CLEARFDTABLE_SHIFT)
3335#define I40E_PFQF_FDALLOC 0x00246280
3336#define I40E_PFQF_FDALLOC_FDALLOC_SHIFT 0
3337#define I40E_PFQF_FDALLOC_FDALLOC_MASK (0xFF << I40E_PFQF_FDALLOC_FDALLOC_SHIFT)
3338#define I40E_PFQF_FDALLOC_FDBEST_SHIFT 8
3339#define I40E_PFQF_FDALLOC_FDBEST_MASK (0xFF << I40E_PFQF_FDALLOC_FDBEST_SHIFT)
3340#define I40E_PFQF_FDSTAT 0x00246380
3341#define I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT 0
3342#define I40E_PFQF_FDSTAT_GUARANT_CNT_MASK (0x1FFF << I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT)
3343#define I40E_PFQF_FDSTAT_BEST_CNT_SHIFT 16
3344#define I40E_PFQF_FDSTAT_BEST_CNT_MASK (0x1FFF << I40E_PFQF_FDSTAT_BEST_CNT_SHIFT)
3345#define I40E_PFQF_HENA(_i) (0x00245900 + ((_i) * 128)) /* _i=0...1 */
3346#define I40E_PFQF_HENA_MAX_INDEX 1
3347#define I40E_PFQF_HENA_PTYPE_ENA_SHIFT 0
3348#define I40E_PFQF_HENA_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_PFQF_HENA_PTYPE_ENA_SHIFT)
3349#define I40E_PFQF_HKEY(_i) (0x00244800 + ((_i) * 128)) /* _i=0...12 */
3350#define I40E_PFQF_HKEY_MAX_INDEX 12
3351#define I40E_PFQF_HKEY_KEY_0_SHIFT 0
3352#define I40E_PFQF_HKEY_KEY_0_MASK (0xFF << I40E_PFQF_HKEY_KEY_0_SHIFT)
3353#define I40E_PFQF_HKEY_KEY_1_SHIFT 8
3354#define I40E_PFQF_HKEY_KEY_1_MASK (0xFF << I40E_PFQF_HKEY_KEY_1_SHIFT)
3355#define I40E_PFQF_HKEY_KEY_2_SHIFT 16
3356#define I40E_PFQF_HKEY_KEY_2_MASK (0xFF << I40E_PFQF_HKEY_KEY_2_SHIFT)
3357#define I40E_PFQF_HKEY_KEY_3_SHIFT 24
3358#define I40E_PFQF_HKEY_KEY_3_MASK (0xFF << I40E_PFQF_HKEY_KEY_3_SHIFT)
3359#define I40E_PFQF_HLUT(_i) (0x00240000 + ((_i) * 128)) /* _i=0...127 */
3360#define I40E_PFQF_HLUT_MAX_INDEX 127
3361#define I40E_PFQF_HLUT_LUT0_SHIFT 0
3362#define I40E_PFQF_HLUT_LUT0_MASK (0x3F << I40E_PFQF_HLUT_LUT0_SHIFT)
3363#define I40E_PFQF_HLUT_LUT1_SHIFT 8
3364#define I40E_PFQF_HLUT_LUT1_MASK (0x3F << I40E_PFQF_HLUT_LUT1_SHIFT)
3365#define I40E_PFQF_HLUT_LUT2_SHIFT 16
3366#define I40E_PFQF_HLUT_LUT2_MASK (0x3F << I40E_PFQF_HLUT_LUT2_SHIFT)
3367#define I40E_PFQF_HLUT_LUT3_SHIFT 24
3368#define I40E_PFQF_HLUT_LUT3_MASK (0x3F << I40E_PFQF_HLUT_LUT3_SHIFT)
3369#define I40E_PFQF_HREGION(_i) (0x00245400 + ((_i) * 128)) /* _i=0...7 */
3370#define I40E_PFQF_HREGION_MAX_INDEX 7
3371#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
3372#define I40E_PFQF_HREGION_OVERRIDE_ENA_0_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
3373#define I40E_PFQF_HREGION_REGION_0_SHIFT 1
3374#define I40E_PFQF_HREGION_REGION_0_MASK (0x7 << I40E_PFQF_HREGION_REGION_0_SHIFT)
3375#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
3376#define I40E_PFQF_HREGION_OVERRIDE_ENA_1_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
3377#define I40E_PFQF_HREGION_REGION_1_SHIFT 5
3378#define I40E_PFQF_HREGION_REGION_1_MASK (0x7 << I40E_PFQF_HREGION_REGION_1_SHIFT)
3379#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
3380#define I40E_PFQF_HREGION_OVERRIDE_ENA_2_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
3381#define I40E_PFQF_HREGION_REGION_2_SHIFT 9
3382#define I40E_PFQF_HREGION_REGION_2_MASK (0x7 << I40E_PFQF_HREGION_REGION_2_SHIFT)
3383#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
3384#define I40E_PFQF_HREGION_OVERRIDE_ENA_3_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
3385#define I40E_PFQF_HREGION_REGION_3_SHIFT 13
3386#define I40E_PFQF_HREGION_REGION_3_MASK (0x7 << I40E_PFQF_HREGION_REGION_3_SHIFT)
3387#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
3388#define I40E_PFQF_HREGION_OVERRIDE_ENA_4_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
3389#define I40E_PFQF_HREGION_REGION_4_SHIFT 17
3390#define I40E_PFQF_HREGION_REGION_4_MASK (0x7 << I40E_PFQF_HREGION_REGION_4_SHIFT)
3391#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
3392#define I40E_PFQF_HREGION_OVERRIDE_ENA_5_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
3393#define I40E_PFQF_HREGION_REGION_5_SHIFT 21
3394#define I40E_PFQF_HREGION_REGION_5_MASK (0x7 << I40E_PFQF_HREGION_REGION_5_SHIFT)
3395#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
3396#define I40E_PFQF_HREGION_OVERRIDE_ENA_6_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
3397#define I40E_PFQF_HREGION_REGION_6_SHIFT 25
3398#define I40E_PFQF_HREGION_REGION_6_MASK (0x7 << I40E_PFQF_HREGION_REGION_6_SHIFT)
3399#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
3400#define I40E_PFQF_HREGION_OVERRIDE_ENA_7_MASK (0x1 << I40E_PFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
3401#define I40E_PFQF_HREGION_REGION_7_SHIFT 29
3402#define I40E_PFQF_HREGION_REGION_7_MASK (0x7 << I40E_PFQF_HREGION_REGION_7_SHIFT)
3403#define I40E_PRTQF_CTL_0 0x00256E60
3404#define I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT 0
3405#define I40E_PRTQF_CTL_0_HSYM_ENA_MASK (0x1 << I40E_PRTQF_CTL_0_HSYM_ENA_SHIFT)
3406#define I40E_PRTQF_FD_FLXINSET(_i) (0x00253800 + ((_i) * 32)) /* _i=0...63 */
3407#define I40E_PRTQF_FD_FLXINSET_MAX_INDEX 63
3408#define I40E_PRTQF_FD_FLXINSET_INSET_SHIFT 0
3409#define I40E_PRTQF_FD_FLXINSET_INSET_MASK (0xFF << I40E_PRTQF_FD_FLXINSET_INSET_SHIFT)
3410#define I40E_PRTQF_FD_MSK(_i, _j) (0x00252000 + ((_i) * 64 + (_j) * 32)) /* _i=0...63, _j=0...1 */
3411#define I40E_PRTQF_FD_MSK_MAX_INDEX 63
3412#define I40E_PRTQF_FD_MSK_MASK_SHIFT 0
3413#define I40E_PRTQF_FD_MSK_MASK_MASK (0xFFFF << I40E_PRTQF_FD_MSK_MASK_SHIFT)
3414#define I40E_PRTQF_FD_MSK_OFFSET_SHIFT 16
3415#define I40E_PRTQF_FD_MSK_OFFSET_MASK (0x3F << I40E_PRTQF_FD_MSK_OFFSET_SHIFT)
3416#define I40E_PRTQF_FLX_PIT(_i) (0x00255200 + ((_i) * 32)) /* _i=0...8 */
3417#define I40E_PRTQF_FLX_PIT_MAX_INDEX 8
3418#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT 0
3419#define I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK (0x3F << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
3420#define I40E_PRTQF_FLX_PIT_FSIZE_SHIFT 6
3421#define I40E_PRTQF_FLX_PIT_FSIZE_MASK (0xF << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
3422#define I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT 10
3423#define I40E_PRTQF_FLX_PIT_DEST_OFF_MASK (0x3F << I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
3424#define I40E_VFQF_HENA1(_i, _VF) (0x00230800 + ((_i) * 1024 + (_VF) * 4))
3425#define I40E_VFQF_HENA1_MAX_INDEX 1
3426#define I40E_VFQF_HENA1_PTYPE_ENA_SHIFT 0
3427#define I40E_VFQF_HENA1_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_VFQF_HENA1_PTYPE_ENA_SHIFT)
3428#define I40E_VFQF_HKEY1(_i, _VF) (0x00228000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...12, _VF=0...127 */
3429#define I40E_VFQF_HKEY1_MAX_INDEX 12
3430#define I40E_VFQF_HKEY1_KEY_0_SHIFT 0
3431#define I40E_VFQF_HKEY1_KEY_0_MASK (0xFF << I40E_VFQF_HKEY1_KEY_0_SHIFT)
3432#define I40E_VFQF_HKEY1_KEY_1_SHIFT 8
3433#define I40E_VFQF_HKEY1_KEY_1_MASK (0xFF << I40E_VFQF_HKEY1_KEY_1_SHIFT)
3434#define I40E_VFQF_HKEY1_KEY_2_SHIFT 16
3435#define I40E_VFQF_HKEY1_KEY_2_MASK (0xFF << I40E_VFQF_HKEY1_KEY_2_SHIFT)
3436#define I40E_VFQF_HKEY1_KEY_3_SHIFT 24
3437#define I40E_VFQF_HKEY1_KEY_3_MASK (0xFF << I40E_VFQF_HKEY1_KEY_3_SHIFT)
3438#define I40E_VFQF_HLUT1(_i, _VF) (0x00220000 + ((_i) * 1024 + (_VF) * 4)) /* _i=0...15, _VF=0...127 */
3439#define I40E_VFQF_HLUT1_MAX_INDEX 15
3440#define I40E_VFQF_HLUT1_LUT0_SHIFT 0
3441#define I40E_VFQF_HLUT1_LUT0_MASK (0xF << I40E_VFQF_HLUT1_LUT0_SHIFT)
3442#define I40E_VFQF_HLUT1_LUT1_SHIFT 8
3443#define I40E_VFQF_HLUT1_LUT1_MASK (0xF << I40E_VFQF_HLUT1_LUT1_SHIFT)
3444#define I40E_VFQF_HLUT1_LUT2_SHIFT 16
3445#define I40E_VFQF_HLUT1_LUT2_MASK (0xF << I40E_VFQF_HLUT1_LUT2_SHIFT)
3446#define I40E_VFQF_HLUT1_LUT3_SHIFT 24
3447#define I40E_VFQF_HLUT1_LUT3_MASK (0xF << I40E_VFQF_HLUT1_LUT3_SHIFT)
3448#define I40E_VFQF_HREGION1(_i, _VF) (0x0022E000 + ((_i) * 1024 + (_VF) * 4))
3449#define I40E_VFQF_HREGION1_MAX_INDEX 7
3450#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT 0
3451#define I40E_VFQF_HREGION1_OVERRIDE_ENA_0_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_0_SHIFT)
3452#define I40E_VFQF_HREGION1_REGION_0_SHIFT 1
3453#define I40E_VFQF_HREGION1_REGION_0_MASK (0x7 << I40E_VFQF_HREGION1_REGION_0_SHIFT)
3454#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT 4
3455#define I40E_VFQF_HREGION1_OVERRIDE_ENA_1_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_1_SHIFT)
3456#define I40E_VFQF_HREGION1_REGION_1_SHIFT 5
3457#define I40E_VFQF_HREGION1_REGION_1_MASK (0x7 << I40E_VFQF_HREGION1_REGION_1_SHIFT)
3458#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT 8
3459#define I40E_VFQF_HREGION1_OVERRIDE_ENA_2_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_2_SHIFT)
3460#define I40E_VFQF_HREGION1_REGION_2_SHIFT 9
3461#define I40E_VFQF_HREGION1_REGION_2_MASK (0x7 << I40E_VFQF_HREGION1_REGION_2_SHIFT)
3462#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT 12
3463#define I40E_VFQF_HREGION1_OVERRIDE_ENA_3_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_3_SHIFT)
3464#define I40E_VFQF_HREGION1_REGION_3_SHIFT 13
3465#define I40E_VFQF_HREGION1_REGION_3_MASK (0x7 << I40E_VFQF_HREGION1_REGION_3_SHIFT)
3466#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT 16
3467#define I40E_VFQF_HREGION1_OVERRIDE_ENA_4_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_4_SHIFT)
3468#define I40E_VFQF_HREGION1_REGION_4_SHIFT 17
3469#define I40E_VFQF_HREGION1_REGION_4_MASK (0x7 << I40E_VFQF_HREGION1_REGION_4_SHIFT)
3470#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT 20
3471#define I40E_VFQF_HREGION1_OVERRIDE_ENA_5_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_5_SHIFT)
3472#define I40E_VFQF_HREGION1_REGION_5_SHIFT 21
3473#define I40E_VFQF_HREGION1_REGION_5_MASK (0x7 << I40E_VFQF_HREGION1_REGION_5_SHIFT)
3474#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT 24
3475#define I40E_VFQF_HREGION1_OVERRIDE_ENA_6_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_6_SHIFT)
3476#define I40E_VFQF_HREGION1_REGION_6_SHIFT 25
3477#define I40E_VFQF_HREGION1_REGION_6_MASK (0x7 << I40E_VFQF_HREGION1_REGION_6_SHIFT)
3478#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT 28
3479#define I40E_VFQF_HREGION1_OVERRIDE_ENA_7_MASK (0x1 << I40E_VFQF_HREGION1_OVERRIDE_ENA_7_SHIFT)
3480#define I40E_VFQF_HREGION1_REGION_7_SHIFT 29
3481#define I40E_VFQF_HREGION1_REGION_7_MASK (0x7 << I40E_VFQF_HREGION1_REGION_7_SHIFT)
3482#define I40E_VPQF_CTL(_VF) (0x001C0000 + ((_VF) * 4)) /* _i=0...127 */
3483#define I40E_VPQF_CTL_MAX_INDEX 127
3484#define I40E_VPQF_CTL_PEHSIZE_SHIFT 0
3485#define I40E_VPQF_CTL_PEHSIZE_MASK (0x1F << I40E_VPQF_CTL_PEHSIZE_SHIFT)
3486#define I40E_VPQF_CTL_PEDSIZE_SHIFT 5
3487#define I40E_VPQF_CTL_PEDSIZE_MASK (0x1F << I40E_VPQF_CTL_PEDSIZE_SHIFT)
3488#define I40E_VPQF_CTL_FCHSIZE_SHIFT 10
3489#define I40E_VPQF_CTL_FCHSIZE_MASK (0xF << I40E_VPQF_CTL_FCHSIZE_SHIFT)
3490#define I40E_VPQF_CTL_FCDSIZE_SHIFT 14
3491#define I40E_VPQF_CTL_FCDSIZE_MASK (0x3 << I40E_VPQF_CTL_FCDSIZE_SHIFT)
3492#define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) /* _i=0...383 */
3493#define I40E_VSIQF_CTL_MAX_INDEX 383
3494#define I40E_VSIQF_CTL_FCOE_ENA_SHIFT 0
3495#define I40E_VSIQF_CTL_FCOE_ENA_MASK (0x1 << I40E_VSIQF_CTL_FCOE_ENA_SHIFT)
3496#define I40E_VSIQF_CTL_PETCP_ENA_SHIFT 1
3497#define I40E_VSIQF_CTL_PETCP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PETCP_ENA_SHIFT)
3498#define I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT 2
3499#define I40E_VSIQF_CTL_PEUUDP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEUUDP_ENA_SHIFT)
3500#define I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT 3
3501#define I40E_VSIQF_CTL_PEMUDP_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEMUDP_ENA_SHIFT)
3502#define I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT 4
3503#define I40E_VSIQF_CTL_PEUFRAG_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEUFRAG_ENA_SHIFT)
3504#define I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT 5
3505#define I40E_VSIQF_CTL_PEMFRAG_ENA_MASK (0x1 << I40E_VSIQF_CTL_PEMFRAG_ENA_SHIFT)
3506#define I40E_VSIQF_TCREGION(_i, _VSI) (0x00206000 + ((_i) * 2048 + (_VSI) * 4))
3507#define I40E_VSIQF_TCREGION_MAX_INDEX 7
3508#define I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT 0
3509#define I40E_VSIQF_TCREGION_TC_OFFSET_MASK (0x1FF << I40E_VSIQF_TCREGION_TC_OFFSET_SHIFT)
3510#define I40E_VSIQF_TCREGION_TC_SIZE_SHIFT 9
3511#define I40E_VSIQF_TCREGION_TC_SIZE_MASK (0x7 << I40E_VSIQF_TCREGION_TC_SIZE_SHIFT)
3512#define I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT 16
3513#define I40E_VSIQF_TCREGION_TC_OFFSET2_MASK (0x1FF << I40E_VSIQF_TCREGION_TC_OFFSET2_SHIFT)
3514#define I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT 25
3515#define I40E_VSIQF_TCREGION_TC_SIZE2_MASK (0x7 << I40E_VSIQF_TCREGION_TC_SIZE2_SHIFT)
3516#define I40E_GL_FCOECRC(_i) (0x00314d80 + ((_i) * 8)) /* _i=0...143 */
3517#define I40E_GL_FCOECRC_MAX_INDEX 143
3518#define I40E_GL_FCOECRC_FCOECRC_SHIFT 0
3519#define I40E_GL_FCOECRC_FCOECRC_MASK (0xFFFFFFFF << I40E_GL_FCOECRC_FCOECRC_SHIFT)
3520#define I40E_GL_FCOEDDPC(_i) (0x00314480 + ((_i) * 8)) /* _i=0...143 */
3521#define I40E_GL_FCOEDDPC_MAX_INDEX 143
3522#define I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT 0
3523#define I40E_GL_FCOEDDPC_FCOEDDPC_MASK (0xFFFFFFFF << I40E_GL_FCOEDDPC_FCOEDDPC_SHIFT)
3524#define I40E_GL_FCOEDDPEC(_i) (0x00314900 + ((_i) * 8)) /* _i=0...143 */
3525#define I40E_GL_FCOEDDPEC_MAX_INDEX 143
3526#define I40E_GL_FCOEDDPEC_CFOEDDPEC_SHIFT 0
3527#define I40E_GL_FCOEDDPEC_CFOEDDPEC_MASK (0xFFFFFFFF << I40E_GL_FCOEDDPEC_CFOEDDPEC_SHIFT)
3528#define I40E_GL_FCOEDIFEC(_i) (0x00318480 + ((_i) * 8)) /* _i=0...143 */
3529#define I40E_GL_FCOEDIFEC_MAX_INDEX 143
3530#define I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT 0
3531#define I40E_GL_FCOEDIFEC_FCOEDIFRC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFEC_FCOEDIFRC_SHIFT)
3532#define I40E_GL_FCOEDIFRC(_i) (0x00318000 + ((_i) * 8)) /* _i=0...143 */
3533#define I40E_GL_FCOEDIFRC_MAX_INDEX 143
3534#define I40E_GL_FCOEDIFRC_FCOEDIFRC_SHIFT 0
3535#define I40E_GL_FCOEDIFRC_FCOEDIFRC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFRC_FCOEDIFRC_SHIFT)
3536#define I40E_GL_FCOEDIFTCL(_i) (0x00354000 + ((_i) * 8)) /* _i=0...143 */
3537#define I40E_GL_FCOEDIFTCL_MAX_INDEX 143
3538#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT 0
3539#define I40E_GL_FCOEDIFTCL_FCOEDIFTC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIFTCL_FCOEDIFTC_SHIFT)
3540#define I40E_GL_FCOEDIXAC(_i) (0x0031c000 + ((_i) * 8)) /* _i=0...143 */
3541#define I40E_GL_FCOEDIXAC_MAX_INDEX 143
3542#define I40E_GL_FCOEDIXAC_FCOEDIXAC_SHIFT 0
3543#define I40E_GL_FCOEDIXAC_FCOEDIXAC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXAC_FCOEDIXAC_SHIFT)
3544#define I40E_GL_FCOEDIXEC(_i) (0x0034c000 + ((_i) * 8)) /* _i=0...143 */
3545#define I40E_GL_FCOEDIXEC_MAX_INDEX 143
3546#define I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT 0
3547#define I40E_GL_FCOEDIXEC_FCOEDIXEC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXEC_FCOEDIXEC_SHIFT)
3548#define I40E_GL_FCOEDIXVC(_i) (0x00350000 + ((_i) * 8)) /* _i=0...143 */
3549#define I40E_GL_FCOEDIXVC_MAX_INDEX 143
3550#define I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT 0
3551#define I40E_GL_FCOEDIXVC_FCOEDIXVC_MASK (0xFFFFFFFF << I40E_GL_FCOEDIXVC_FCOEDIXVC_SHIFT)
3552#define I40E_GL_FCOEDWRCH(_i) (0x00320004 + ((_i) * 8)) /* _i=0...143 */
3553#define I40E_GL_FCOEDWRCH_MAX_INDEX 143
3554#define I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT 0
3555#define I40E_GL_FCOEDWRCH_FCOEDWRCH_MASK (0xFFFF << I40E_GL_FCOEDWRCH_FCOEDWRCH_SHIFT)
3556#define I40E_GL_FCOEDWRCL(_i) (0x00320000 + ((_i) * 8)) /* _i=0...143 */
3557#define I40E_GL_FCOEDWRCL_MAX_INDEX 143
3558#define I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT 0
3559#define I40E_GL_FCOEDWRCL_FCOEDWRCL_MASK (0xFFFFFFFF << I40E_GL_FCOEDWRCL_FCOEDWRCL_SHIFT)
3560#define I40E_GL_FCOEDWTCH(_i) (0x00348084 + ((_i) * 8)) /* _i=0...143 */
3561#define I40E_GL_FCOEDWTCH_MAX_INDEX 143
3562#define I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT 0
3563#define I40E_GL_FCOEDWTCH_FCOEDWTCH_MASK (0xFFFF << I40E_GL_FCOEDWTCH_FCOEDWTCH_SHIFT)
3564#define I40E_GL_FCOEDWTCL(_i) (0x00348080 + ((_i) * 8)) /* _i=0...143 */
3565#define I40E_GL_FCOEDWTCL_MAX_INDEX 143
3566#define I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT 0
3567#define I40E_GL_FCOEDWTCL_FCOEDWTCL_MASK (0xFFFFFFFF << I40E_GL_FCOEDWTCL_FCOEDWTCL_SHIFT)
3568#define I40E_GL_FCOELAST(_i) (0x00314000 + ((_i) * 8)) /* _i=0...143 */
3569#define I40E_GL_FCOELAST_MAX_INDEX 143
3570#define I40E_GL_FCOELAST_FCOELAST_SHIFT 0
3571#define I40E_GL_FCOELAST_FCOELAST_MASK (0xFFFFFFFF << I40E_GL_FCOELAST_FCOELAST_SHIFT)
3572#define I40E_GL_FCOEPRC(_i) (0x00315200 + ((_i) * 8)) /* _i=0...143 */
3573#define I40E_GL_FCOEPRC_MAX_INDEX 143
3574#define I40E_GL_FCOEPRC_FCOEPRC_SHIFT 0
3575#define I40E_GL_FCOEPRC_FCOEPRC_MASK (0xFFFFFFFF << I40E_GL_FCOEPRC_FCOEPRC_SHIFT)
3576#define I40E_GL_FCOEPTC(_i) (0x00344C00 + ((_i) * 8)) /* _i=0...143 */
3577#define I40E_GL_FCOEPTC_MAX_INDEX 143
3578#define I40E_GL_FCOEPTC_FCOEPTC_SHIFT 0
3579#define I40E_GL_FCOEPTC_FCOEPTC_MASK (0xFFFFFFFF << I40E_GL_FCOEPTC_FCOEPTC_SHIFT)
3580#define I40E_GL_FCOERPDC(_i) (0x00324000 + ((_i) * 8)) /* _i=0...143 */
3581#define I40E_GL_FCOERPDC_MAX_INDEX 143
3582#define I40E_GL_FCOERPDC_FCOERPDC_SHIFT 0
3583#define I40E_GL_FCOERPDC_FCOERPDC_MASK (0xFFFFFFFF << I40E_GL_FCOERPDC_FCOERPDC_SHIFT)
3584#define I40E_GLPRT_BPRCH(_i) (0x003005E4 + ((_i) * 8)) /* _i=0...3 */
3585#define I40E_GLPRT_BPRCH_MAX_INDEX 3
3586#define I40E_GLPRT_BPRCH_UPRCH_SHIFT 0
3587#define I40E_GLPRT_BPRCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_BPRCH_UPRCH_SHIFT)
3588#define I40E_GLPRT_BPRCL(_i) (0x003005E0 + ((_i) * 8)) /* _i=0...3 */
3589#define I40E_GLPRT_BPRCL_MAX_INDEX 3
3590#define I40E_GLPRT_BPRCL_UPRCH_SHIFT 0
3591#define I40E_GLPRT_BPRCL_UPRCH_MASK (0xFFFFFFFF << I40E_GLPRT_BPRCL_UPRCH_SHIFT)
3592#define I40E_GLPRT_BPTCH(_i) (0x00300A04 + ((_i) * 8)) /* _i=0...3 */
3593#define I40E_GLPRT_BPTCH_MAX_INDEX 3
3594#define I40E_GLPRT_BPTCH_UPRCH_SHIFT 0
3595#define I40E_GLPRT_BPTCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_BPTCH_UPRCH_SHIFT)
3596#define I40E_GLPRT_BPTCL(_i) (0x00300A00 + ((_i) * 8)) /* _i=0...3 */
3597#define I40E_GLPRT_BPTCL_MAX_INDEX 3
3598#define I40E_GLPRT_BPTCL_UPRCH_SHIFT 0
3599#define I40E_GLPRT_BPTCL_UPRCH_MASK (0xFFFFFFFF << I40E_GLPRT_BPTCL_UPRCH_SHIFT)
3600#define I40E_GLPRT_CRCERRS(_i) (0x00300080 + ((_i) * 8)) /* _i=0...3 */
3601#define I40E_GLPRT_CRCERRS_MAX_INDEX 3
3602#define I40E_GLPRT_CRCERRS_CRCERRS_SHIFT 0
3603#define I40E_GLPRT_CRCERRS_CRCERRS_MASK (0xFFFFFFFF << I40E_GLPRT_CRCERRS_CRCERRS_SHIFT)
3604#define I40E_GLPRT_GORCH(_i) (0x00300004 + ((_i) * 8)) /* _i=0...3 */
3605#define I40E_GLPRT_GORCH_MAX_INDEX 3
3606#define I40E_GLPRT_GORCH_GORCH_SHIFT 0
3607#define I40E_GLPRT_GORCH_GORCH_MASK (0xFFFF << I40E_GLPRT_GORCH_GORCH_SHIFT)
3608#define I40E_GLPRT_GORCL(_i) (0x00300000 + ((_i) * 8)) /* _i=0...3 */
3609#define I40E_GLPRT_GORCL_MAX_INDEX 3
3610#define I40E_GLPRT_GORCL_GORCL_SHIFT 0
3611#define I40E_GLPRT_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLPRT_GORCL_GORCL_SHIFT)
3612#define I40E_GLPRT_GOTCH(_i) (0x00300684 + ((_i) * 8)) /* _i=0...3 */
3613#define I40E_GLPRT_GOTCH_MAX_INDEX 3
3614#define I40E_GLPRT_GOTCH_GOTCH_SHIFT 0
3615#define I40E_GLPRT_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLPRT_GOTCH_GOTCH_SHIFT)
3616#define I40E_GLPRT_GOTCL(_i) (0x00300680 + ((_i) * 8)) /* _i=0...3 */
3617#define I40E_GLPRT_GOTCL_MAX_INDEX 3
3618#define I40E_GLPRT_GOTCL_GOTCL_SHIFT 0
3619#define I40E_GLPRT_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLPRT_GOTCL_GOTCL_SHIFT)
3620#define I40E_GLPRT_ILLERRC(_i) (0x003000E0 + ((_i) * 8)) /* _i=0...3 */
3621#define I40E_GLPRT_ILLERRC_MAX_INDEX 3
3622#define I40E_GLPRT_ILLERRC_ILLERRC_SHIFT 0
3623#define I40E_GLPRT_ILLERRC_ILLERRC_MASK (0xFFFFFFFF << I40E_GLPRT_ILLERRC_ILLERRC_SHIFT)
3624#define I40E_GLPRT_LDPC(_i) (0x00300620 + ((_i) * 8)) /* _i=0...3 */
3625#define I40E_GLPRT_LDPC_MAX_INDEX 3
3626#define I40E_GLPRT_LDPC_LDPC_SHIFT 0
3627#define I40E_GLPRT_LDPC_LDPC_MASK (0xFFFFFFFF << I40E_GLPRT_LDPC_LDPC_SHIFT)
3628#define I40E_GLPRT_LXOFFRXC(_i) (0x00300160 + ((_i) * 8)) /* _i=0...3 */
3629#define I40E_GLPRT_LXOFFRXC_MAX_INDEX 3
3630#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT 0
3631#define I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_LXOFFRXC_LXOFFRXCNT_SHIFT)
3632#define I40E_GLPRT_LXOFFTXC(_i) (0x003009A0 + ((_i) * 8)) /* _i=0...3 */
3633#define I40E_GLPRT_LXOFFTXC_MAX_INDEX 3
3634#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT 0
3635#define I40E_GLPRT_LXOFFTXC_LXOFFTXC_MASK (0xFFFFFFFF << I40E_GLPRT_LXOFFTXC_LXOFFTXC_SHIFT)
3636#define I40E_GLPRT_LXONRXC(_i) (0x00300140 + ((_i) * 8)) /* _i=0...3 */
3637#define I40E_GLPRT_LXONRXC_MAX_INDEX 3
3638#define I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT 0
3639#define I40E_GLPRT_LXONRXC_LXONRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_LXONRXC_LXONRXCNT_SHIFT)
3640#define I40E_GLPRT_LXONTXC(_i) (0x00300980 + ((_i) * 8)) /* _i=0...3 */
3641#define I40E_GLPRT_LXONTXC_MAX_INDEX 3
3642#define I40E_GLPRT_LXONTXC_LXONTXC_SHIFT 0
3643#define I40E_GLPRT_LXONTXC_LXONTXC_MASK (0xFFFFFFFF << I40E_GLPRT_LXONTXC_LXONTXC_SHIFT)
3644#define I40E_GLPRT_MLFC(_i) (0x00300020 + ((_i) * 8)) /* _i=0...3 */
3645#define I40E_GLPRT_MLFC_MAX_INDEX 3
3646#define I40E_GLPRT_MLFC_MLFC_SHIFT 0
3647#define I40E_GLPRT_MLFC_MLFC_MASK (0xFFFFFFFF << I40E_GLPRT_MLFC_MLFC_SHIFT)
3648#define I40E_GLPRT_MPRCH(_i) (0x003005C4 + ((_i) * 8)) /* _i=0...3 */
3649#define I40E_GLPRT_MPRCH_MAX_INDEX 3
3650#define I40E_GLPRT_MPRCH_MPRCH_SHIFT 0
3651#define I40E_GLPRT_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLPRT_MPRCH_MPRCH_SHIFT)
3652#define I40E_GLPRT_MPRCL(_i) (0x003005C0 + ((_i) * 8)) /* _i=0...3 */
3653#define I40E_GLPRT_MPRCL_MAX_INDEX 3
3654#define I40E_GLPRT_MPRCL_MPRCL_SHIFT 0
3655#define I40E_GLPRT_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLPRT_MPRCL_MPRCL_SHIFT)
3656#define I40E_GLPRT_MPTCH(_i) (0x003009E4 + ((_i) * 8)) /* _i=0...3 */
3657#define I40E_GLPRT_MPTCH_MAX_INDEX 3
3658#define I40E_GLPRT_MPTCH_MPTCH_SHIFT 0
3659#define I40E_GLPRT_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLPRT_MPTCH_MPTCH_SHIFT)
3660#define I40E_GLPRT_MPTCL(_i) (0x003009E0 + ((_i) * 8)) /* _i=0...3 */
3661#define I40E_GLPRT_MPTCL_MAX_INDEX 3
3662#define I40E_GLPRT_MPTCL_MPTCL_SHIFT 0
3663#define I40E_GLPRT_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLPRT_MPTCL_MPTCL_SHIFT)
3664#define I40E_GLPRT_MRFC(_i) (0x00300040 + ((_i) * 8)) /* _i=0...3 */
3665#define I40E_GLPRT_MRFC_MAX_INDEX 3
3666#define I40E_GLPRT_MRFC_MRFC_SHIFT 0
3667#define I40E_GLPRT_MRFC_MRFC_MASK (0xFFFFFFFF << I40E_GLPRT_MRFC_MRFC_SHIFT)
3668#define I40E_GLPRT_PRC1023H(_i) (0x00300504 + ((_i) * 8)) /* _i=0...3 */
3669#define I40E_GLPRT_PRC1023H_MAX_INDEX 3
3670#define I40E_GLPRT_PRC1023H_PRC1023H_SHIFT 0
3671#define I40E_GLPRT_PRC1023H_PRC1023H_MASK (0xFFFF << I40E_GLPRT_PRC1023H_PRC1023H_SHIFT)
3672#define I40E_GLPRT_PRC1023L(_i) (0x00300500 + ((_i) * 8)) /* _i=0...3 */
3673#define I40E_GLPRT_PRC1023L_MAX_INDEX 3
3674#define I40E_GLPRT_PRC1023L_PRC1023L_SHIFT 0
3675#define I40E_GLPRT_PRC1023L_PRC1023L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC1023L_PRC1023L_SHIFT)
3676#define I40E_GLPRT_PRC127H(_i) (0x003004A4 + ((_i) * 8)) /* _i=0...3 */
3677#define I40E_GLPRT_PRC127H_MAX_INDEX 3
3678#define I40E_GLPRT_PRC127H_PRC127H_SHIFT 0
3679#define I40E_GLPRT_PRC127H_PRC127H_MASK (0xFFFF << I40E_GLPRT_PRC127H_PRC127H_SHIFT)
3680#define I40E_GLPRT_PRC127L(_i) (0x003004A0 + ((_i) * 8)) /* _i=0...3 */
3681#define I40E_GLPRT_PRC127L_MAX_INDEX 3
3682#define I40E_GLPRT_PRC127L_PRC127L_SHIFT 0
3683#define I40E_GLPRT_PRC127L_PRC127L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC127L_PRC127L_SHIFT)
3684#define I40E_GLPRT_PRC1522H(_i) (0x00300524 + ((_i) * 8)) /* _i=0...3 */
3685#define I40E_GLPRT_PRC1522H_MAX_INDEX 3
3686#define I40E_GLPRT_PRC1522H_PRC1522H_SHIFT 0
3687#define I40E_GLPRT_PRC1522H_PRC1522H_MASK (0xFFFF << I40E_GLPRT_PRC1522H_PRC1522H_SHIFT)
3688#define I40E_GLPRT_PRC1522L(_i) (0x00300520 + ((_i) * 8)) /* _i=0...3 */
3689#define I40E_GLPRT_PRC1522L_MAX_INDEX 3
3690#define I40E_GLPRT_PRC1522L_PRC1522L_SHIFT 0
3691#define I40E_GLPRT_PRC1522L_PRC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC1522L_PRC1522L_SHIFT)
3692#define I40E_GLPRT_PRC255H(_i) (0x003004C4 + ((_i) * 8)) /* _i=0...3 */
3693#define I40E_GLPRT_PRC255H_MAX_INDEX 3
3694#define I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT 0
3695#define I40E_GLPRT_PRC255H_PRTPRC255H_MASK (0xFFFF << I40E_GLPRT_PRC255H_PRTPRC255H_SHIFT)
3696#define I40E_GLPRT_PRC255L(_i) (0x003004C0 + ((_i) * 8)) /* _i=0...3 */
3697#define I40E_GLPRT_PRC255L_MAX_INDEX 3
3698#define I40E_GLPRT_PRC255L_PRC255L_SHIFT 0
3699#define I40E_GLPRT_PRC255L_PRC255L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC255L_PRC255L_SHIFT)
3700#define I40E_GLPRT_PRC511H(_i) (0x003004E4 + ((_i) * 8)) /* _i=0...3 */
3701#define I40E_GLPRT_PRC511H_MAX_INDEX 3
3702#define I40E_GLPRT_PRC511H_PRC511H_SHIFT 0
3703#define I40E_GLPRT_PRC511H_PRC511H_MASK (0xFFFF << I40E_GLPRT_PRC511H_PRC511H_SHIFT)
3704#define I40E_GLPRT_PRC511L(_i) (0x003004E0 + ((_i) * 8)) /* _i=0...3 */
3705#define I40E_GLPRT_PRC511L_MAX_INDEX 3
3706#define I40E_GLPRT_PRC511L_PRC511L_SHIFT 0
3707#define I40E_GLPRT_PRC511L_PRC511L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC511L_PRC511L_SHIFT)
3708#define I40E_GLPRT_PRC64H(_i) (0x00300484 + ((_i) * 8)) /* _i=0...3 */
3709#define I40E_GLPRT_PRC64H_MAX_INDEX 3
3710#define I40E_GLPRT_PRC64H_PRC64H_SHIFT 0
3711#define I40E_GLPRT_PRC64H_PRC64H_MASK (0xFFFF << I40E_GLPRT_PRC64H_PRC64H_SHIFT)
3712#define I40E_GLPRT_PRC64L(_i) (0x00300480 + ((_i) * 8)) /* _i=0...3 */
3713#define I40E_GLPRT_PRC64L_MAX_INDEX 3
3714#define I40E_GLPRT_PRC64L_PRC64L_SHIFT 0
3715#define I40E_GLPRT_PRC64L_PRC64L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC64L_PRC64L_SHIFT)
3716#define I40E_GLPRT_PRC9522H(_i) (0x00300544 + ((_i) * 8)) /* _i=0...3 */
3717#define I40E_GLPRT_PRC9522H_MAX_INDEX 3
3718#define I40E_GLPRT_PRC9522H_PRC1522H_SHIFT 0
3719#define I40E_GLPRT_PRC9522H_PRC1522H_MASK (0xFFFF << I40E_GLPRT_PRC9522H_PRC1522H_SHIFT)
3720#define I40E_GLPRT_PRC9522L(_i) (0x00300540 + ((_i) * 8)) /* _i=0...3 */
3721#define I40E_GLPRT_PRC9522L_MAX_INDEX 3
3722#define I40E_GLPRT_PRC9522L_PRC1522L_SHIFT 0
3723#define I40E_GLPRT_PRC9522L_PRC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PRC9522L_PRC1522L_SHIFT)
3724#define I40E_GLPRT_PTC1023H(_i) (0x00300724 + ((_i) * 8)) /* _i=0...3 */
3725#define I40E_GLPRT_PTC1023H_MAX_INDEX 3
3726#define I40E_GLPRT_PTC1023H_PTC1023H_SHIFT 0
3727#define I40E_GLPRT_PTC1023H_PTC1023H_MASK (0xFFFF << I40E_GLPRT_PTC1023H_PTC1023H_SHIFT)
3728#define I40E_GLPRT_PTC1023L(_i) (0x00300720 + ((_i) * 8)) /* _i=0...3 */
3729#define I40E_GLPRT_PTC1023L_MAX_INDEX 3
3730#define I40E_GLPRT_PTC1023L_PTC1023L_SHIFT 0
3731#define I40E_GLPRT_PTC1023L_PTC1023L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC1023L_PTC1023L_SHIFT)
3732#define I40E_GLPRT_PTC127H(_i) (0x003006C4 + ((_i) * 8)) /* _i=0...3 */
3733#define I40E_GLPRT_PTC127H_MAX_INDEX 3
3734#define I40E_GLPRT_PTC127H_PTC127H_SHIFT 0
3735#define I40E_GLPRT_PTC127H_PTC127H_MASK (0xFFFF << I40E_GLPRT_PTC127H_PTC127H_SHIFT)
3736#define I40E_GLPRT_PTC127L(_i) (0x003006C0 + ((_i) * 8)) /* _i=0...3 */
3737#define I40E_GLPRT_PTC127L_MAX_INDEX 3
3738#define I40E_GLPRT_PTC127L_PTC127L_SHIFT 0
3739#define I40E_GLPRT_PTC127L_PTC127L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC127L_PTC127L_SHIFT)
3740#define I40E_GLPRT_PTC1522H(_i) (0x00300744 + ((_i) * 8)) /* _i=0...3 */
3741#define I40E_GLPRT_PTC1522H_MAX_INDEX 3
3742#define I40E_GLPRT_PTC1522H_PTC1522H_SHIFT 0
3743#define I40E_GLPRT_PTC1522H_PTC1522H_MASK (0xFFFF << I40E_GLPRT_PTC1522H_PTC1522H_SHIFT)
3744#define I40E_GLPRT_PTC1522L(_i) (0x00300740 + ((_i) * 8)) /* _i=0...3 */
3745#define I40E_GLPRT_PTC1522L_MAX_INDEX 3
3746#define I40E_GLPRT_PTC1522L_PTC1522L_SHIFT 0
3747#define I40E_GLPRT_PTC1522L_PTC1522L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC1522L_PTC1522L_SHIFT)
3748#define I40E_GLPRT_PTC255H(_i) (0x003006E4 + ((_i) * 8)) /* _i=0...3 */
3749#define I40E_GLPRT_PTC255H_MAX_INDEX 3
3750#define I40E_GLPRT_PTC255H_PTC255H_SHIFT 0
3751#define I40E_GLPRT_PTC255H_PTC255H_MASK (0xFFFF << I40E_GLPRT_PTC255H_PTC255H_SHIFT)
3752#define I40E_GLPRT_PTC255L(_i) (0x003006E0 + ((_i) * 8)) /* _i=0...3 */
3753#define I40E_GLPRT_PTC255L_MAX_INDEX 3
3754#define I40E_GLPRT_PTC255L_PTC255L_SHIFT 0
3755#define I40E_GLPRT_PTC255L_PTC255L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC255L_PTC255L_SHIFT)
3756#define I40E_GLPRT_PTC511H(_i) (0x00300704 + ((_i) * 8)) /* _i=0...3 */
3757#define I40E_GLPRT_PTC511H_MAX_INDEX 3
3758#define I40E_GLPRT_PTC511H_PTC511H_SHIFT 0
3759#define I40E_GLPRT_PTC511H_PTC511H_MASK (0xFFFF << I40E_GLPRT_PTC511H_PTC511H_SHIFT)
3760#define I40E_GLPRT_PTC511L(_i) (0x00300700 + ((_i) * 8)) /* _i=0...3 */
3761#define I40E_GLPRT_PTC511L_MAX_INDEX 3
3762#define I40E_GLPRT_PTC511L_PTC511L_SHIFT 0
3763#define I40E_GLPRT_PTC511L_PTC511L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC511L_PTC511L_SHIFT)
3764#define I40E_GLPRT_PTC64H(_i) (0x003006A4 + ((_i) * 8)) /* _i=0...3 */
3765#define I40E_GLPRT_PTC64H_MAX_INDEX 3
3766#define I40E_GLPRT_PTC64H_PTC64H_SHIFT 0
3767#define I40E_GLPRT_PTC64H_PTC64H_MASK (0xFFFF << I40E_GLPRT_PTC64H_PTC64H_SHIFT)
3768#define I40E_GLPRT_PTC64L(_i) (0x003006A0 + ((_i) * 8)) /* _i=0...3 */
3769#define I40E_GLPRT_PTC64L_MAX_INDEX 3
3770#define I40E_GLPRT_PTC64L_PTC64L_SHIFT 0
3771#define I40E_GLPRT_PTC64L_PTC64L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC64L_PTC64L_SHIFT)
3772#define I40E_GLPRT_PTC9522H(_i) (0x00300764 + ((_i) * 8)) /* _i=0...3 */
3773#define I40E_GLPRT_PTC9522H_MAX_INDEX 3
3774#define I40E_GLPRT_PTC9522H_PTC9522H_SHIFT 0
3775#define I40E_GLPRT_PTC9522H_PTC9522H_MASK (0xFFFF << I40E_GLPRT_PTC9522H_PTC9522H_SHIFT)
3776#define I40E_GLPRT_PTC9522L(_i) (0x00300760 + ((_i) * 8)) /* _i=0...3 */
3777#define I40E_GLPRT_PTC9522L_MAX_INDEX 3
3778#define I40E_GLPRT_PTC9522L_PTC9522L_SHIFT 0
3779#define I40E_GLPRT_PTC9522L_PTC9522L_MASK (0xFFFFFFFF << I40E_GLPRT_PTC9522L_PTC9522L_SHIFT)
3780#define I40E_GLPRT_PXOFFRXC(_i, _j) (0x00300280 + ((_i) * 8 + (_j) * 32))
3781#define I40E_GLPRT_PXOFFRXC_MAX_INDEX 3
3782#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT 0
3783#define I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXOFFRXC_PRPXOFFRXCNT_SHIFT)
3784#define I40E_GLPRT_PXOFFTXC(_i, _j) (0x00300880 + ((_i) * 8 + (_j) * 32))
3785#define I40E_GLPRT_PXOFFTXC_MAX_INDEX 3
3786#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT 0
3787#define I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXOFFTXC_PRPXOFFTXCNT_SHIFT)
3788#define I40E_GLPRT_PXONRXC(_i, _j) (0x00300180 + ((_i) * 8 + (_j) * 32))
3789#define I40E_GLPRT_PXONRXC_MAX_INDEX 3
3790#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT 0
3791#define I40E_GLPRT_PXONRXC_PRPXONRXCNT_MASK (0xFFFFFFFF << I40E_GLPRT_PXONRXC_PRPXONRXCNT_SHIFT)
3792#define I40E_GLPRT_PXONTXC(_i, _j) (0x00300780 + ((_i) * 8 + (_j) * 32))
3793#define I40E_GLPRT_PXONTXC_MAX_INDEX 3
3794#define I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT 0
3795#define I40E_GLPRT_PXONTXC_PRPXONTXC_MASK (0xFFFFFFFF << I40E_GLPRT_PXONTXC_PRPXONTXC_SHIFT)
3796#define I40E_GLPRT_RDPC(_i) (0x00300600 + ((_i) * 8)) /* _i=0...3 */
3797#define I40E_GLPRT_RDPC_MAX_INDEX 3
3798#define I40E_GLPRT_RDPC_RDPC_SHIFT 0
3799#define I40E_GLPRT_RDPC_RDPC_MASK (0xFFFFFFFF << I40E_GLPRT_RDPC_RDPC_SHIFT)
3800#define I40E_GLPRT_RFC(_i) (0x00300560 + ((_i) * 8)) /* _i=0...3 */
3801#define I40E_GLPRT_RFC_MAX_INDEX 3
3802#define I40E_GLPRT_RFC_RFC_SHIFT 0
3803#define I40E_GLPRT_RFC_RFC_MASK (0xFFFFFFFF << I40E_GLPRT_RFC_RFC_SHIFT)
3804#define I40E_GLPRT_RJC(_i) (0x00300580 + ((_i) * 8)) /* _i=0...3 */
3805#define I40E_GLPRT_RJC_MAX_INDEX 3
3806#define I40E_GLPRT_RJC_RJC_SHIFT 0
3807#define I40E_GLPRT_RJC_RJC_MASK (0xFFFFFFFF << I40E_GLPRT_RJC_RJC_SHIFT)
3808#define I40E_GLPRT_RLEC(_i) (0x003000A0 + ((_i) * 8)) /* _i=0...3 */
3809#define I40E_GLPRT_RLEC_MAX_INDEX 3
3810#define I40E_GLPRT_RLEC_RLEC_SHIFT 0
3811#define I40E_GLPRT_RLEC_RLEC_MASK (0xFFFFFFFF << I40E_GLPRT_RLEC_RLEC_SHIFT)
3812#define I40E_GLPRT_ROC(_i) (0x00300120 + ((_i) * 8)) /* _i=0...3 */
3813#define I40E_GLPRT_ROC_MAX_INDEX 3
3814#define I40E_GLPRT_ROC_ROC_SHIFT 0
3815#define I40E_GLPRT_ROC_ROC_MASK (0xFFFFFFFF << I40E_GLPRT_ROC_ROC_SHIFT)
3816#define I40E_GLPRT_RUC(_i) (0x00300100 + ((_i) * 8)) /* _i=0...3 */
3817#define I40E_GLPRT_RUC_MAX_INDEX 3
3818#define I40E_GLPRT_RUC_RUC_SHIFT 0
3819#define I40E_GLPRT_RUC_RUC_MASK (0xFFFFFFFF << I40E_GLPRT_RUC_RUC_SHIFT)
3820#define I40E_GLPRT_RUPP(_i) (0x00300660 + ((_i) * 8)) /* _i=0...3 */
3821#define I40E_GLPRT_RUPP_MAX_INDEX 3
3822#define I40E_GLPRT_RUPP_RUPP_SHIFT 0
3823#define I40E_GLPRT_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLPRT_RUPP_RUPP_SHIFT)
3824#define I40E_GLPRT_RXON2OFFCNT(_i, _j) (0x00300380 + ((_i) * 8 + (_j) * 32))
3825#define I40E_GLPRT_RXON2OFFCNT_MAX_INDEX 3
3826#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT 0
3827#define I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_MASK (0xFFFFFFFF << I40E_GLPRT_RXON2OFFCNT_PRRXON2OFFCNT_SHIFT)
3828#define I40E_GLPRT_STDC(_i) (0x00300640 + ((_i) * 8)) /* _i=0...3 */
3829#define I40E_GLPRT_STDC_MAX_INDEX 3
3830#define I40E_GLPRT_STDC_STDC_SHIFT 0
3831#define I40E_GLPRT_STDC_STDC_MASK (0xFFFFFFFF << I40E_GLPRT_STDC_STDC_SHIFT)
3832#define I40E_GLPRT_TDOLD(_i) (0x00300A20 + ((_i) * 8)) /* _i=0...3 */
3833#define I40E_GLPRT_TDOLD_MAX_INDEX 3
3834#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT 0
3835#define I40E_GLPRT_TDOLD_GLPRT_TDOLD_MASK (0xFFFFFFFF << I40E_GLPRT_TDOLD_GLPRT_TDOLD_SHIFT)
3836#define I40E_GLPRT_TDPC(_i) (0x00375400 + ((_i) * 8)) /* _i=0...3 */
3837#define I40E_GLPRT_TDPC_MAX_INDEX 3
3838#define I40E_GLPRT_TDPC_TDPC_SHIFT 0
3839#define I40E_GLPRT_TDPC_TDPC_MASK (0xFFFFFFFF << I40E_GLPRT_TDPC_TDPC_SHIFT)
3840#define I40E_GLPRT_UPRCH(_i) (0x003005A4 + ((_i) * 8)) /* _i=0...3 */
3841#define I40E_GLPRT_UPRCH_MAX_INDEX 3
3842#define I40E_GLPRT_UPRCH_UPRCH_SHIFT 0
3843#define I40E_GLPRT_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLPRT_UPRCH_UPRCH_SHIFT)
3844#define I40E_GLPRT_UPRCL(_i) (0x003005A0 + ((_i) * 8)) /* _i=0...3 */
3845#define I40E_GLPRT_UPRCL_MAX_INDEX 3
3846#define I40E_GLPRT_UPRCL_UPRCL_SHIFT 0
3847#define I40E_GLPRT_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLPRT_UPRCL_UPRCL_SHIFT)
3848#define I40E_GLPRT_UPTCH(_i) (0x003009C4 + ((_i) * 8)) /* _i=0...3 */
3849#define I40E_GLPRT_UPTCH_MAX_INDEX 3
3850#define I40E_GLPRT_UPTCH_UPTCH_SHIFT 0
3851#define I40E_GLPRT_UPTCH_UPTCH_MASK (0xFFFF << I40E_GLPRT_UPTCH_UPTCH_SHIFT)
3852#define I40E_GLPRT_UPTCL(_i) (0x003009C0 + ((_i) * 8)) /* _i=0...3 */
3853#define I40E_GLPRT_UPTCL_MAX_INDEX 3
3854#define I40E_GLPRT_UPTCL_VUPTCH_SHIFT 0
3855#define I40E_GLPRT_UPTCL_VUPTCH_MASK (0xFFFFFFFF << I40E_GLPRT_UPTCL_VUPTCH_SHIFT)
3856#define I40E_GLSW_BPRCH(_i) (0x00370104 + ((_i) * 8)) /* _i=0...15 */
3857#define I40E_GLSW_BPRCH_MAX_INDEX 15
3858#define I40E_GLSW_BPRCH_BPRCH_SHIFT 0
3859#define I40E_GLSW_BPRCH_BPRCH_MASK (0xFFFF << I40E_GLSW_BPRCH_BPRCH_SHIFT)
3860#define I40E_GLSW_BPRCL(_i) (0x00370100 + ((_i) * 8)) /* _i=0...15 */
3861#define I40E_GLSW_BPRCL_MAX_INDEX 15
3862#define I40E_GLSW_BPRCL_BPRCL_SHIFT 0
3863#define I40E_GLSW_BPRCL_BPRCL_MASK (0xFFFFFFFF << I40E_GLSW_BPRCL_BPRCL_SHIFT)
3864#define I40E_GLSW_BPTCH(_i) (0x00340104 + ((_i) * 8)) /* _i=0...15 */
3865#define I40E_GLSW_BPTCH_MAX_INDEX 15
3866#define I40E_GLSW_BPTCH_BPTCH_SHIFT 0
3867#define I40E_GLSW_BPTCH_BPTCH_MASK (0xFFFF << I40E_GLSW_BPTCH_BPTCH_SHIFT)
3868#define I40E_GLSW_BPTCL(_i) (0x00340100 + ((_i) * 8)) /* _i=0...15 */
3869#define I40E_GLSW_BPTCL_MAX_INDEX 15
3870#define I40E_GLSW_BPTCL_BPTCL_SHIFT 0
3871#define I40E_GLSW_BPTCL_BPTCL_MASK (0xFFFFFFFF << I40E_GLSW_BPTCL_BPTCL_SHIFT)
3872#define I40E_GLSW_GORCH(_i) (0x0035C004 + ((_i) * 8)) /* _i=0...15 */
3873#define I40E_GLSW_GORCH_MAX_INDEX 15
3874#define I40E_GLSW_GORCH_GORCH_SHIFT 0
3875#define I40E_GLSW_GORCH_GORCH_MASK (0xFFFF << I40E_GLSW_GORCH_GORCH_SHIFT)
3876#define I40E_GLSW_GORCL(_i) (0x0035c000 + ((_i) * 8)) /* _i=0...15 */
3877#define I40E_GLSW_GORCL_MAX_INDEX 15
3878#define I40E_GLSW_GORCL_GORCL_SHIFT 0
3879#define I40E_GLSW_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLSW_GORCL_GORCL_SHIFT)
3880#define I40E_GLSW_GOTCH(_i) (0x0032C004 + ((_i) * 8)) /* _i=0...15 */
3881#define I40E_GLSW_GOTCH_MAX_INDEX 15
3882#define I40E_GLSW_GOTCH_GOTCH_SHIFT 0
3883#define I40E_GLSW_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLSW_GOTCH_GOTCH_SHIFT)
3884#define I40E_GLSW_GOTCL(_i) (0x0032c000 + ((_i) * 8)) /* _i=0...15 */
3885#define I40E_GLSW_GOTCL_MAX_INDEX 15
3886#define I40E_GLSW_GOTCL_GOTCL_SHIFT 0
3887#define I40E_GLSW_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLSW_GOTCL_GOTCL_SHIFT)
3888#define I40E_GLSW_MPRCH(_i) (0x00370084 + ((_i) * 8)) /* _i=0...15 */
3889#define I40E_GLSW_MPRCH_MAX_INDEX 15
3890#define I40E_GLSW_MPRCH_MPRCH_SHIFT 0
3891#define I40E_GLSW_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLSW_MPRCH_MPRCH_SHIFT)
3892#define I40E_GLSW_MPRCL(_i) (0x00370080 + ((_i) * 8)) /* _i=0...15 */
3893#define I40E_GLSW_MPRCL_MAX_INDEX 15
3894#define I40E_GLSW_MPRCL_MPRCL_SHIFT 0
3895#define I40E_GLSW_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLSW_MPRCL_MPRCL_SHIFT)
3896#define I40E_GLSW_MPTCH(_i) (0x00340084 + ((_i) * 8)) /* _i=0...15 */
3897#define I40E_GLSW_MPTCH_MAX_INDEX 15
3898#define I40E_GLSW_MPTCH_MPTCH_SHIFT 0
3899#define I40E_GLSW_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLSW_MPTCH_MPTCH_SHIFT)
3900#define I40E_GLSW_MPTCL(_i) (0x00340080 + ((_i) * 8)) /* _i=0...15 */
3901#define I40E_GLSW_MPTCL_MAX_INDEX 15
3902#define I40E_GLSW_MPTCL_MPTCL_SHIFT 0
3903#define I40E_GLSW_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLSW_MPTCL_MPTCL_SHIFT)
3904#define I40E_GLSW_RUPP(_i) (0x00370180 + ((_i) * 8)) /* _i=0...15 */
3905#define I40E_GLSW_RUPP_MAX_INDEX 15
3906#define I40E_GLSW_RUPP_RUPP_SHIFT 0
3907#define I40E_GLSW_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLSW_RUPP_RUPP_SHIFT)
3908#define I40E_GLSW_TDPC(_i) (0x00348000 + ((_i) * 8)) /* _i=0...15 */
3909#define I40E_GLSW_TDPC_MAX_INDEX 15
3910#define I40E_GLSW_TDPC_TDPC_SHIFT 0
3911#define I40E_GLSW_TDPC_TDPC_MASK (0xFFFFFFFF << I40E_GLSW_TDPC_TDPC_SHIFT)
3912#define I40E_GLSW_UPRCH(_i) (0x00370004 + ((_i) * 8)) /* _i=0...15 */
3913#define I40E_GLSW_UPRCH_MAX_INDEX 15
3914#define I40E_GLSW_UPRCH_UPRCH_SHIFT 0
3915#define I40E_GLSW_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLSW_UPRCH_UPRCH_SHIFT)
3916#define I40E_GLSW_UPRCL(_i) (0x00370000 + ((_i) * 8)) /* _i=0...15 */
3917#define I40E_GLSW_UPRCL_MAX_INDEX 15
3918#define I40E_GLSW_UPRCL_UPRCL_SHIFT 0
3919#define I40E_GLSW_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLSW_UPRCL_UPRCL_SHIFT)
3920#define I40E_GLSW_UPTCH(_i) (0x00340004 + ((_i) * 8)) /* _i=0...15 */
3921#define I40E_GLSW_UPTCH_MAX_INDEX 15
3922#define I40E_GLSW_UPTCH_UPTCH_SHIFT 0
3923#define I40E_GLSW_UPTCH_UPTCH_MASK (0xFFFF << I40E_GLSW_UPTCH_UPTCH_SHIFT)
3924#define I40E_GLSW_UPTCL(_i) (0x00340000 + ((_i) * 8)) /* _i=0...15 */
3925#define I40E_GLSW_UPTCL_MAX_INDEX 15
3926#define I40E_GLSW_UPTCL_UPTCL_SHIFT 0
3927#define I40E_GLSW_UPTCL_UPTCL_MASK (0xFFFFFFFF << I40E_GLSW_UPTCL_UPTCL_SHIFT)
3928#define I40E_GLV_BPRCH(_i) (0x0036D804 + ((_i) * 8)) /* _i=0...383 */
3929#define I40E_GLV_BPRCH_MAX_INDEX 383
3930#define I40E_GLV_BPRCH_BPRCH_SHIFT 0
3931#define I40E_GLV_BPRCH_BPRCH_MASK (0xFFFF << I40E_GLV_BPRCH_BPRCH_SHIFT)
3932#define I40E_GLV_BPRCL(_i) (0x0036d800 + ((_i) * 8)) /* _i=0...383 */
3933#define I40E_GLV_BPRCL_MAX_INDEX 383
3934#define I40E_GLV_BPRCL_BPRCL_SHIFT 0
3935#define I40E_GLV_BPRCL_BPRCL_MASK (0xFFFFFFFF << I40E_GLV_BPRCL_BPRCL_SHIFT)
3936#define I40E_GLV_BPTCH(_i) (0x0033D804 + ((_i) * 8)) /* _i=0...383 */
3937#define I40E_GLV_BPTCH_MAX_INDEX 383
3938#define I40E_GLV_BPTCH_BPTCH_SHIFT 0
3939#define I40E_GLV_BPTCH_BPTCH_MASK (0xFFFF << I40E_GLV_BPTCH_BPTCH_SHIFT)
3940#define I40E_GLV_BPTCL(_i) (0x0033d800 + ((_i) * 8)) /* _i=0...383 */
3941#define I40E_GLV_BPTCL_MAX_INDEX 383
3942#define I40E_GLV_BPTCL_BPTCL_SHIFT 0
3943#define I40E_GLV_BPTCL_BPTCL_MASK (0xFFFFFFFF << I40E_GLV_BPTCL_BPTCL_SHIFT)
3944#define I40E_GLV_GORCH(_i) (0x00358004 + ((_i) * 8)) /* _i=0...383 */
3945#define I40E_GLV_GORCH_MAX_INDEX 383
3946#define I40E_GLV_GORCH_GORCH_SHIFT 0
3947#define I40E_GLV_GORCH_GORCH_MASK (0xFFFF << I40E_GLV_GORCH_GORCH_SHIFT)
3948#define I40E_GLV_GORCL(_i) (0x00358000 + ((_i) * 8)) /* _i=0...383 */
3949#define I40E_GLV_GORCL_MAX_INDEX 383
3950#define I40E_GLV_GORCL_GORCL_SHIFT 0
3951#define I40E_GLV_GORCL_GORCL_MASK (0xFFFFFFFF << I40E_GLV_GORCL_GORCL_SHIFT)
3952#define I40E_GLV_GOTCH(_i) (0x00328004 + ((_i) * 8)) /* _i=0...383 */
3953#define I40E_GLV_GOTCH_MAX_INDEX 383
3954#define I40E_GLV_GOTCH_GOTCH_SHIFT 0
3955#define I40E_GLV_GOTCH_GOTCH_MASK (0xFFFF << I40E_GLV_GOTCH_GOTCH_SHIFT)
3956#define I40E_GLV_GOTCL(_i) (0x00328000 + ((_i) * 8)) /* _i=0...383 */
3957#define I40E_GLV_GOTCL_MAX_INDEX 383
3958#define I40E_GLV_GOTCL_GOTCL_SHIFT 0
3959#define I40E_GLV_GOTCL_GOTCL_MASK (0xFFFFFFFF << I40E_GLV_GOTCL_GOTCL_SHIFT)
3960#define I40E_GLV_MPRCH(_i) (0x0036CC04 + ((_i) * 8)) /* _i=0...383 */
3961#define I40E_GLV_MPRCH_MAX_INDEX 383
3962#define I40E_GLV_MPRCH_MPRCH_SHIFT 0
3963#define I40E_GLV_MPRCH_MPRCH_MASK (0xFFFF << I40E_GLV_MPRCH_MPRCH_SHIFT)
3964#define I40E_GLV_MPRCL(_i) (0x0036cc00 + ((_i) * 8)) /* _i=0...383 */
3965#define I40E_GLV_MPRCL_MAX_INDEX 383
3966#define I40E_GLV_MPRCL_MPRCL_SHIFT 0
3967#define I40E_GLV_MPRCL_MPRCL_MASK (0xFFFFFFFF << I40E_GLV_MPRCL_MPRCL_SHIFT)
3968#define I40E_GLV_MPTCH(_i) (0x0033CC04 + ((_i) * 8)) /* _i=0...383 */
3969#define I40E_GLV_MPTCH_MAX_INDEX 383
3970#define I40E_GLV_MPTCH_MPTCH_SHIFT 0
3971#define I40E_GLV_MPTCH_MPTCH_MASK (0xFFFF << I40E_GLV_MPTCH_MPTCH_SHIFT)
3972#define I40E_GLV_MPTCL(_i) (0x0033cc00 + ((_i) * 8)) /* _i=0...383 */
3973#define I40E_GLV_MPTCL_MAX_INDEX 383
3974#define I40E_GLV_MPTCL_MPTCL_SHIFT 0
3975#define I40E_GLV_MPTCL_MPTCL_MASK (0xFFFFFFFF << I40E_GLV_MPTCL_MPTCL_SHIFT)
3976#define I40E_GLV_RDPC(_i) (0x00310000 + ((_i) * 8)) /* _i=0...383 */
3977#define I40E_GLV_RDPC_MAX_INDEX 383
3978#define I40E_GLV_RDPC_RDPC_SHIFT 0
3979#define I40E_GLV_RDPC_RDPC_MASK (0xFFFFFFFF << I40E_GLV_RDPC_RDPC_SHIFT)
3980#define I40E_GLV_RUPP(_i) (0x0036E400 + ((_i) * 8)) /* _i=0...383 */
3981#define I40E_GLV_RUPP_MAX_INDEX 383
3982#define I40E_GLV_RUPP_RUPP_SHIFT 0
3983#define I40E_GLV_RUPP_RUPP_MASK (0xFFFFFFFF << I40E_GLV_RUPP_RUPP_SHIFT)
3984#define I40E_GLV_TEPC(_VSI) (0x00344000 + ((_VSI) * 8)) /* _i=0...383 */
3985#define I40E_GLV_TEPC_MAX_INDEX 383
3986#define I40E_GLV_TEPC_TEPC_SHIFT 0
3987#define I40E_GLV_TEPC_TEPC_MASK (0xFFFFFFFF << I40E_GLV_TEPC_TEPC_SHIFT)
3988#define I40E_GLV_UPRCH(_i) (0x0036C004 + ((_i) * 8)) /* _i=0...383 */
3989#define I40E_GLV_UPRCH_MAX_INDEX 383
3990#define I40E_GLV_UPRCH_UPRCH_SHIFT 0
3991#define I40E_GLV_UPRCH_UPRCH_MASK (0xFFFF << I40E_GLV_UPRCH_UPRCH_SHIFT)
3992#define I40E_GLV_UPRCL(_i) (0x0036c000 + ((_i) * 8)) /* _i=0...383 */
3993#define I40E_GLV_UPRCL_MAX_INDEX 383
3994#define I40E_GLV_UPRCL_UPRCL_SHIFT 0
3995#define I40E_GLV_UPRCL_UPRCL_MASK (0xFFFFFFFF << I40E_GLV_UPRCL_UPRCL_SHIFT)
3996#define I40E_GLV_UPTCH(_i) (0x0033C004 + ((_i) * 8)) /* _i=0...383 */
3997#define I40E_GLV_UPTCH_MAX_INDEX 383
3998#define I40E_GLV_UPTCH_GLVUPTCH_SHIFT 0
3999#define I40E_GLV_UPTCH_GLVUPTCH_MASK (0xFFFF << I40E_GLV_UPTCH_GLVUPTCH_SHIFT)
4000#define I40E_GLV_UPTCL(_i) (0x0033c000 + ((_i) * 8)) /* _i=0...383 */
4001#define I40E_GLV_UPTCL_MAX_INDEX 383
4002#define I40E_GLV_UPTCL_UPTCL_SHIFT 0
4003#define I40E_GLV_UPTCL_UPTCL_MASK (0xFFFFFFFF << I40E_GLV_UPTCL_UPTCL_SHIFT)
4004#define I40E_GLVEBTC_RBCH(_i, _j) (0x00364004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
4005#define I40E_GLVEBTC_RBCH_MAX_INDEX 7
4006#define I40E_GLVEBTC_RBCH_TCBCH_SHIFT 0
4007#define I40E_GLVEBTC_RBCH_TCBCH_MASK (0xFFFF << I40E_GLVEBTC_RBCH_TCBCH_SHIFT)
4008#define I40E_GLVEBTC_RBCL(_i, _j) (0x00364000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
4009#define I40E_GLVEBTC_RBCL_MAX_INDEX 7
4010#define I40E_GLVEBTC_RBCL_TCBCL_SHIFT 0
4011#define I40E_GLVEBTC_RBCL_TCBCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_RBCL_TCBCL_SHIFT)
4012#define I40E_GLVEBTC_RPCH(_i, _j) (0x00368004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
4013#define I40E_GLVEBTC_RPCH_MAX_INDEX 7
4014#define I40E_GLVEBTC_RPCH_TCPCH_SHIFT 0
4015#define I40E_GLVEBTC_RPCH_TCPCH_MASK (0xFFFF << I40E_GLVEBTC_RPCH_TCPCH_SHIFT)
4016#define I40E_GLVEBTC_RPCL(_i, _j) (0x00368000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
4017#define I40E_GLVEBTC_RPCL_MAX_INDEX 7
4018#define I40E_GLVEBTC_RPCL_TCPCL_SHIFT 0
4019#define I40E_GLVEBTC_RPCL_TCPCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_RPCL_TCPCL_SHIFT)
4020#define I40E_GLVEBTC_TBCH(_i, _j) (0x00334004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
4021#define I40E_GLVEBTC_TBCH_MAX_INDEX 7
4022#define I40E_GLVEBTC_TBCH_TCBCH_SHIFT 0
4023#define I40E_GLVEBTC_TBCH_TCBCH_MASK (0xFFFF << I40E_GLVEBTC_TBCH_TCBCH_SHIFT)
4024#define I40E_GLVEBTC_TBCL(_i, _j) (0x00334000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
4025#define I40E_GLVEBTC_TBCL_MAX_INDEX 7
4026#define I40E_GLVEBTC_TBCL_TCBCL_SHIFT 0
4027#define I40E_GLVEBTC_TBCL_TCBCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_TBCL_TCBCL_SHIFT)
4028#define I40E_GLVEBTC_TPCH(_i, _j) (0x00338004 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
4029#define I40E_GLVEBTC_TPCH_MAX_INDEX 7
4030#define I40E_GLVEBTC_TPCH_TCPCH_SHIFT 0
4031#define I40E_GLVEBTC_TPCH_TCPCH_MASK (0xFFFF << I40E_GLVEBTC_TPCH_TCPCH_SHIFT)
4032#define I40E_GLVEBTC_TPCL(_i, _j) (0x00338000 + ((_i) * 8 + (_j) * 64)) /* _i=0...7, _j=0...15 */
4033#define I40E_GLVEBTC_TPCL_MAX_INDEX 7
4034#define I40E_GLVEBTC_TPCL_TCPCL_SHIFT 0
4035#define I40E_GLVEBTC_TPCL_TCPCL_MASK (0xFFFFFFFF << I40E_GLVEBTC_TPCL_TCPCL_SHIFT)
4036#define I40E_GLVEBVL_BPCH(_i) (0x00374804 + ((_i) * 8)) /* _i=0...127 */
4037#define I40E_GLVEBVL_BPCH_MAX_INDEX 127
4038#define I40E_GLVEBVL_BPCH_VLBPCH_SHIFT 0
4039#define I40E_GLVEBVL_BPCH_VLBPCH_MASK (0xFFFF << I40E_GLVEBVL_BPCH_VLBPCH_SHIFT)
4040#define I40E_GLVEBVL_BPCL(_i) (0x00374800 + ((_i) * 8)) /* _i=0...127 */
4041#define I40E_GLVEBVL_BPCL_MAX_INDEX 127
4042#define I40E_GLVEBVL_BPCL_VLBPCL_SHIFT 0
4043#define I40E_GLVEBVL_BPCL_VLBPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_BPCL_VLBPCL_SHIFT)
4044#define I40E_GLVEBVL_GORCH(_i) (0x00360004 + ((_i) * 8)) /* _i=0...127 */
4045#define I40E_GLVEBVL_GORCH_MAX_INDEX 127
4046#define I40E_GLVEBVL_GORCH_VLBCH_SHIFT 0
4047#define I40E_GLVEBVL_GORCH_VLBCH_MASK (0xFFFF << I40E_GLVEBVL_GORCH_VLBCH_SHIFT)
4048#define I40E_GLVEBVL_GORCL(_i) (0x00360000 + ((_i) * 8)) /* _i=0...127 */
4049#define I40E_GLVEBVL_GORCL_MAX_INDEX 127
4050#define I40E_GLVEBVL_GORCL_VLBCL_SHIFT 0
4051#define I40E_GLVEBVL_GORCL_VLBCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_GORCL_VLBCL_SHIFT)
4052#define I40E_GLVEBVL_GOTCH(_i) (0x00330004 + ((_i) * 8)) /* _i=0...127 */
4053#define I40E_GLVEBVL_GOTCH_MAX_INDEX 127
4054#define I40E_GLVEBVL_GOTCH_VLBCH_SHIFT 0
4055#define I40E_GLVEBVL_GOTCH_VLBCH_MASK (0xFFFF << I40E_GLVEBVL_GOTCH_VLBCH_SHIFT)
4056#define I40E_GLVEBVL_GOTCL(_i) (0x00330000 + ((_i) * 8)) /* _i=0...127 */
4057#define I40E_GLVEBVL_GOTCL_MAX_INDEX 127
4058#define I40E_GLVEBVL_GOTCL_VLBCL_SHIFT 0
4059#define I40E_GLVEBVL_GOTCL_VLBCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_GOTCL_VLBCL_SHIFT)
4060#define I40E_GLVEBVL_MPCH(_i) (0x00374404 + ((_i) * 8)) /* _i=0...127 */
4061#define I40E_GLVEBVL_MPCH_MAX_INDEX 127
4062#define I40E_GLVEBVL_MPCH_VLMPCH_SHIFT 0
4063#define I40E_GLVEBVL_MPCH_VLMPCH_MASK (0xFFFF << I40E_GLVEBVL_MPCH_VLMPCH_SHIFT)
4064#define I40E_GLVEBVL_MPCL(_i) (0x00374400 + ((_i) * 8)) /* _i=0...127 */
4065#define I40E_GLVEBVL_MPCL_MAX_INDEX 127
4066#define I40E_GLVEBVL_MPCL_VLMPCL_SHIFT 0
4067#define I40E_GLVEBVL_MPCL_VLMPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_MPCL_VLMPCL_SHIFT)
4068#define I40E_GLVEBVL_UPCH(_i) (0x00374004 + ((_i) * 8)) /* _i=0...127 */
4069#define I40E_GLVEBVL_UPCH_MAX_INDEX 127
4070#define I40E_GLVEBVL_UPCH_VLUPCH_SHIFT 0
4071#define I40E_GLVEBVL_UPCH_VLUPCH_MASK (0xFFFF << I40E_GLVEBVL_UPCH_VLUPCH_SHIFT)
4072#define I40E_GLVEBVL_UPCL(_i) (0x00374000 + ((_i) * 8)) /* _i=0...127 */
4073#define I40E_GLVEBVL_UPCL_MAX_INDEX 127
4074#define I40E_GLVEBVL_UPCL_VLUPCL_SHIFT 0
4075#define I40E_GLVEBVL_UPCL_VLUPCL_MASK (0xFFFFFFFF << I40E_GLVEBVL_UPCL_VLUPCL_SHIFT)
4076#define I40E_GL_MTG_FLU_MSK_H 0x00269F4C
4077#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT 0
4078#define I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_MASK (0xFFFF << I40E_GL_MTG_FLU_MSK_H_MASK_HIGH_SHIFT)
4079#define I40E_GL_MTG_FLU_MSK_L 0x00269F44
4080#define I40E_GL_MTG_FLU_MSK_L_MASK_LOW_SHIFT 0
4081#define I40E_GL_MTG_FLU_MSK_L_MASK_LOW_MASK (0xFFFFFFFF << I40E_GL_MTG_FLU_MSK_L_MASK_LOW_SHIFT)
4082#define I40E_GL_SWR_DEF_ACT(_i) (0x0026CF00 + ((_i) * 4)) /* _i=0...25 */
4083#define I40E_GL_SWR_DEF_ACT_MAX_INDEX 25
4084#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT 0
4085#define I40E_GL_SWR_DEF_ACT_DEF_ACTION_MASK (0xFFFFFFFF << I40E_GL_SWR_DEF_ACT_DEF_ACTION_SHIFT)
4086#define I40E_GL_SWR_DEF_ACT_EN 0x0026CF84
4087#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT 0
4088#define I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_MASK (0xFFFFFFFF << I40E_GL_SWR_DEF_ACT_EN_DEF_ACT_EN_BITMAP_SHIFT)
4089#define I40E_PRT_MSCCNT 0x00256BA0
4090#define I40E_PRT_MSCCNT_CCOUNT_SHIFT 0
4091#define I40E_PRT_MSCCNT_CCOUNT_MASK (0x1FFFFFF << I40E_PRT_MSCCNT_CCOUNT_SHIFT)
4092#define I40E_PRT_SCSTS 0x00256C20
4093#define I40E_PRT_SCSTS_BSCA_SHIFT 0
4094#define I40E_PRT_SCSTS_BSCA_MASK (0x1 << I40E_PRT_SCSTS_BSCA_SHIFT)
4095#define I40E_PRT_SCSTS_BSCAP_SHIFT 1
4096#define I40E_PRT_SCSTS_BSCAP_MASK (0x1 << I40E_PRT_SCSTS_BSCAP_SHIFT)
4097#define I40E_PRT_SCSTS_MSCA_SHIFT 2
4098#define I40E_PRT_SCSTS_MSCA_MASK (0x1 << I40E_PRT_SCSTS_MSCA_SHIFT)
4099#define I40E_PRT_SCSTS_MSCAP_SHIFT 3
4100#define I40E_PRT_SCSTS_MSCAP_MASK (0x1 << I40E_PRT_SCSTS_MSCAP_SHIFT)
4101#define I40E_PRT_SWT_BSCCNT 0x00256C60
4102#define I40E_PRT_SWT_BSCCNT_CCOUNT_SHIFT 0
4103#define I40E_PRT_SWT_BSCCNT_CCOUNT_MASK (0x1FFFFFF << I40E_PRT_SWT_BSCCNT_CCOUNT_SHIFT)
4104#define I40E_PRTTSYN_ADJ 0x001E4280
4105#define I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT 0
4106#define I40E_PRTTSYN_ADJ_TSYNADJ_MASK (0x7FFFFFFF << I40E_PRTTSYN_ADJ_TSYNADJ_SHIFT)
4107#define I40E_PRTTSYN_ADJ_SIGN_SHIFT 31
4108#define I40E_PRTTSYN_ADJ_SIGN_MASK (0x1 << I40E_PRTTSYN_ADJ_SIGN_SHIFT)
4109#define I40E_PRTTSYN_AUX_0(_i) (0x001E42A0 + ((_i) * 32)) /* _i=0...1 */
4110#define I40E_PRTTSYN_AUX_0_MAX_INDEX 1
4111#define I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT 0
4112#define I40E_PRTTSYN_AUX_0_OUT_ENA_MASK (0x1 << I40E_PRTTSYN_AUX_0_OUT_ENA_SHIFT)
4113#define I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT 1
4114#define I40E_PRTTSYN_AUX_0_OUTMOD_MASK (0x3 << I40E_PRTTSYN_AUX_0_OUTMOD_SHIFT)
4115#define I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT 3
4116#define I40E_PRTTSYN_AUX_0_OUTLVL_MASK (0x1 << I40E_PRTTSYN_AUX_0_OUTLVL_SHIFT)
4117#define I40E_PRTTSYN_AUX_0_PULSEW_SHIFT 8
4118#define I40E_PRTTSYN_AUX_0_PULSEW_MASK (0xF << I40E_PRTTSYN_AUX_0_PULSEW_SHIFT)
4119#define I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT 16
4120#define I40E_PRTTSYN_AUX_0_EVNTLVL_MASK (0x3 << I40E_PRTTSYN_AUX_0_EVNTLVL_SHIFT)
4121#define I40E_PRTTSYN_AUX_1(_i) (0x001E42E0 + ((_i) * 32)) /* _i=0...1 */
4122#define I40E_PRTTSYN_AUX_1_MAX_INDEX 1
4123#define I40E_PRTTSYN_AUX_1_INSTNT_SHIFT 0
4124#define I40E_PRTTSYN_AUX_1_INSTNT_MASK (0x1 << I40E_PRTTSYN_AUX_1_INSTNT_SHIFT)
4125#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT 1
4126#define I40E_PRTTSYN_AUX_1_SAMPLE_TIME_MASK (0x1 << I40E_PRTTSYN_AUX_1_SAMPLE_TIME_SHIFT)
4127#define I40E_PRTTSYN_CLKO(_i) (0x001E4240 + ((_i) * 32)) /* _i=0...1 */
4128#define I40E_PRTTSYN_CLKO_MAX_INDEX 1
4129#define I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT 0
4130#define I40E_PRTTSYN_CLKO_TSYNCLKO_MASK (0xFFFFFFFF << I40E_PRTTSYN_CLKO_TSYNCLKO_SHIFT)
4131#define I40E_PRTTSYN_CTL0 0x001E4200
4132#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT 0
4133#define I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_MASK (0x1 << I40E_PRTTSYN_CTL0_CLEAR_TSYNTIMER_SHIFT)
4134#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT 1
4135#define I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_SHIFT)
4136#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT 2
4137#define I40E_PRTTSYN_CTL0_EVENT_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_EVENT_INT_ENA_SHIFT)
4138#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT 3
4139#define I40E_PRTTSYN_CTL0_TGT_INT_ENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TGT_INT_ENA_SHIFT)
4140#define I40E_PRTTSYN_CTL0_PF_ID_SHIFT 8
4141#define I40E_PRTTSYN_CTL0_PF_ID_MASK (0xF << I40E_PRTTSYN_CTL0_PF_ID_SHIFT)
4142#define I40E_PRTTSYN_CTL0_TSYNACT_SHIFT 12
4143#define I40E_PRTTSYN_CTL0_TSYNACT_MASK (0x3 << I40E_PRTTSYN_CTL0_TSYNACT_SHIFT)
4144#define I40E_PRTTSYN_CTL0_TSYNENA_SHIFT 31
4145#define I40E_PRTTSYN_CTL0_TSYNENA_MASK (0x1 << I40E_PRTTSYN_CTL0_TSYNENA_SHIFT)
4146#define I40E_PRTTSYN_CTL1 0x00085020
4147#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT 0
4148#define I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK (0xFF << I40E_PRTTSYN_CTL1_V1MESSTYPE0_SHIFT)
4149#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT 8
4150#define I40E_PRTTSYN_CTL1_V1MESSTYPE1_MASK (0xFF << I40E_PRTTSYN_CTL1_V1MESSTYPE1_SHIFT)
4151#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT 16
4152#define I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK (0xF << I40E_PRTTSYN_CTL1_V2MESSTYPE0_SHIFT)
4153#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT 20
4154#define I40E_PRTTSYN_CTL1_V2MESSTYPE1_MASK (0xF << I40E_PRTTSYN_CTL1_V2MESSTYPE1_SHIFT)
4155#define I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT 24
4156#define I40E_PRTTSYN_CTL1_TSYNTYPE_MASK (0x3 << I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
4157#define I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT 26
4158#define I40E_PRTTSYN_CTL1_UDP_ENA_MASK (0x3 << I40E_PRTTSYN_CTL1_UDP_ENA_SHIFT)
4159#define I40E_PRTTSYN_CTL1_TSYNENA_SHIFT 31
4160#define I40E_PRTTSYN_CTL1_TSYNENA_MASK (0x1 << I40E_PRTTSYN_CTL1_TSYNENA_SHIFT)
4161#define I40E_PRTTSYN_EVNT_H(_i) (0x001E40C0 + ((_i) * 32)) /* _i=0...1 */
4162#define I40E_PRTTSYN_EVNT_H_MAX_INDEX 1
4163#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT 0
4164#define I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_EVNT_H_TSYNEVNT_H_SHIFT)
4165#define I40E_PRTTSYN_EVNT_L(_i) (0x001E4080 + ((_i) * 32)) /* _i=0...1 */
4166#define I40E_PRTTSYN_EVNT_L_MAX_INDEX 1
4167#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT 0
4168#define I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_EVNT_L_TSYNEVNT_L_SHIFT)
4169#define I40E_PRTTSYN_INC_H 0x001E4060
4170#define I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT 0
4171#define I40E_PRTTSYN_INC_H_TSYNINC_H_MASK (0x3F << I40E_PRTTSYN_INC_H_TSYNINC_H_SHIFT)
4172#define I40E_PRTTSYN_INC_L 0x001E4040
4173#define I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT 0
4174#define I40E_PRTTSYN_INC_L_TSYNINC_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_INC_L_TSYNINC_L_SHIFT)
4175#define I40E_PRTTSYN_RXTIME_H(_i) (0x00085040 + ((_i) * 32)) /* _i=0...3 */
4176#define I40E_PRTTSYN_RXTIME_H_MAX_INDEX 3
4177#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT 0
4178#define I40E_PRTTSYN_RXTIME_H_RXTIEM_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_RXTIME_H_RXTIEM_H_SHIFT)
4179#define I40E_PRTTSYN_RXTIME_L(_i) (0x000850C0 + ((_i) * 32)) /* _i=0...3 */
4180#define I40E_PRTTSYN_RXTIME_L_MAX_INDEX 3
4181#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT 0
4182#define I40E_PRTTSYN_RXTIME_L_RXTIEM_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_RXTIME_L_RXTIEM_L_SHIFT)
4183#define I40E_PRTTSYN_STAT_0 0x001E4220
4184#define I40E_PRTTSYN_STAT_0_EVENT0_SHIFT 0
4185#define I40E_PRTTSYN_STAT_0_EVENT0_MASK (0x1 << I40E_PRTTSYN_STAT_0_EVENT0_SHIFT)
4186#define I40E_PRTTSYN_STAT_0_EVENT1_SHIFT 1
4187#define I40E_PRTTSYN_STAT_0_EVENT1_MASK (0x1 << I40E_PRTTSYN_STAT_0_EVENT1_SHIFT)
4188#define I40E_PRTTSYN_STAT_0_TGT0_SHIFT 2
4189#define I40E_PRTTSYN_STAT_0_TGT0_MASK (0x1 << I40E_PRTTSYN_STAT_0_TGT0_SHIFT)
4190#define I40E_PRTTSYN_STAT_0_TGT1_SHIFT 3
4191#define I40E_PRTTSYN_STAT_0_TGT1_MASK (0x1 << I40E_PRTTSYN_STAT_0_TGT1_SHIFT)
4192#define I40E_PRTTSYN_STAT_0_TXTIME_SHIFT 4
4193#define I40E_PRTTSYN_STAT_0_TXTIME_MASK (0x1 << I40E_PRTTSYN_STAT_0_TXTIME_SHIFT)
4194#define I40E_PRTTSYN_STAT_1 0x00085140
4195#define I40E_PRTTSYN_STAT_1_RXT0_SHIFT 0
4196#define I40E_PRTTSYN_STAT_1_RXT0_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT0_SHIFT)
4197#define I40E_PRTTSYN_STAT_1_RXT1_SHIFT 1
4198#define I40E_PRTTSYN_STAT_1_RXT1_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT1_SHIFT)
4199#define I40E_PRTTSYN_STAT_1_RXT2_SHIFT 2
4200#define I40E_PRTTSYN_STAT_1_RXT2_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT2_SHIFT)
4201#define I40E_PRTTSYN_STAT_1_RXT3_SHIFT 3
4202#define I40E_PRTTSYN_STAT_1_RXT3_MASK (0x1 << I40E_PRTTSYN_STAT_1_RXT3_SHIFT)
4203#define I40E_PRTTSYN_TGT_H(_i) (0x001E4180 + ((_i) * 32)) /* _i=0...1 */
4204#define I40E_PRTTSYN_TGT_H_MAX_INDEX 1
4205#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT 0
4206#define I40E_PRTTSYN_TGT_H_TSYNTGTT_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TGT_H_TSYNTGTT_H_SHIFT)
4207#define I40E_PRTTSYN_TGT_L(_i) (0x001E4140 + ((_i) * 32)) /* _i=0...1 */
4208#define I40E_PRTTSYN_TGT_L_MAX_INDEX 1
4209#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT 0
4210#define I40E_PRTTSYN_TGT_L_TSYNTGTT_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TGT_L_TSYNTGTT_L_SHIFT)
4211#define I40E_PRTTSYN_TIME_H 0x001E4120
4212#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT 0
4213#define I40E_PRTTSYN_TIME_H_TSYNTIME_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TIME_H_TSYNTIME_H_SHIFT)
4214#define I40E_PRTTSYN_TIME_L 0x001E4100
4215#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT 0
4216#define I40E_PRTTSYN_TIME_L_TSYNTIME_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TIME_L_TSYNTIME_L_SHIFT)
4217#define I40E_PRTTSYN_TXTIME_H 0x001E41E0
4218#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT 0
4219#define I40E_PRTTSYN_TXTIME_H_TXTIEM_H_MASK (0xFFFFFFFF << I40E_PRTTSYN_TXTIME_H_TXTIEM_H_SHIFT)
4220#define I40E_PRTTSYN_TXTIME_L 0x001E41C0
4221#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT 0
4222#define I40E_PRTTSYN_TXTIME_L_TXTIEM_L_MASK (0xFFFFFFFF << I40E_PRTTSYN_TXTIME_L_TXTIEM_L_SHIFT)
4223#define I40E_GLSCD_QUANTA 0x000B2080
4224#define I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT 0
4225#define I40E_GLSCD_QUANTA_TSCDQUANTA_MASK (0x7 << I40E_GLSCD_QUANTA_TSCDQUANTA_SHIFT)
4226#define I40E_GL_MDET_RX 0x0012A510
4227#define I40E_GL_MDET_RX_FUNCTION_SHIFT 0
4228#define I40E_GL_MDET_RX_FUNCTION_MASK (0xFF << I40E_GL_MDET_RX_FUNCTION_SHIFT)
4229#define I40E_GL_MDET_RX_EVENT_SHIFT 8
4230#define I40E_GL_MDET_RX_EVENT_MASK (0x1FF << I40E_GL_MDET_RX_EVENT_SHIFT)
4231#define I40E_GL_MDET_RX_QUEUE_SHIFT 17
4232#define I40E_GL_MDET_RX_QUEUE_MASK (0x3FFF << I40E_GL_MDET_RX_QUEUE_SHIFT)
4233#define I40E_GL_MDET_RX_VALID_SHIFT 31
4234#define I40E_GL_MDET_RX_VALID_MASK (0x1 << I40E_GL_MDET_RX_VALID_SHIFT)
4235#define I40E_GL_MDET_TX 0x000E6480
4236#define I40E_GL_MDET_TX_FUNCTION_SHIFT 0
4237#define I40E_GL_MDET_TX_FUNCTION_MASK (0xFF << I40E_GL_MDET_TX_FUNCTION_SHIFT)
4238#define I40E_GL_MDET_TX_EVENT_SHIFT 8
4239#define I40E_GL_MDET_TX_EVENT_MASK (0x1FF << I40E_GL_MDET_TX_EVENT_SHIFT)
4240#define I40E_GL_MDET_TX_QUEUE_SHIFT 17
4241#define I40E_GL_MDET_TX_QUEUE_MASK (0x3FFF << I40E_GL_MDET_TX_QUEUE_SHIFT)
4242#define I40E_GL_MDET_TX_VALID_SHIFT 31
4243#define I40E_GL_MDET_TX_VALID_MASK (0x1 << I40E_GL_MDET_TX_VALID_SHIFT)
4244#define I40E_PF_MDET_RX 0x0012A400
4245#define I40E_PF_MDET_RX_VALID_SHIFT 0
4246#define I40E_PF_MDET_RX_VALID_MASK (0x1 << I40E_PF_MDET_RX_VALID_SHIFT)
4247#define I40E_PF_MDET_TX 0x000E6400
4248#define I40E_PF_MDET_TX_VALID_SHIFT 0
4249#define I40E_PF_MDET_TX_VALID_MASK (0x1 << I40E_PF_MDET_TX_VALID_SHIFT)
4250#define I40E_PF_VT_PFALLOC 0x001C0500
4251#define I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT 0
4252#define I40E_PF_VT_PFALLOC_FIRSTVF_MASK (0xFF << I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT)
4253#define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8
4254#define I40E_PF_VT_PFALLOC_LASTVF_MASK (0xFF << I40E_PF_VT_PFALLOC_LASTVF_SHIFT)
4255#define I40E_PF_VT_PFALLOC_VALID_SHIFT 31
4256#define I40E_PF_VT_PFALLOC_VALID_MASK (0x1 << I40E_PF_VT_PFALLOC_VALID_SHIFT)
4257#define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */
4258#define I40E_VP_MDET_RX_MAX_INDEX 127
4259#define I40E_VP_MDET_RX_VALID_SHIFT 0
4260#define I40E_VP_MDET_RX_VALID_MASK (0x1 << I40E_VP_MDET_RX_VALID_SHIFT)
4261#define I40E_VP_MDET_TX(_VF) (0x000E6000 + ((_VF) * 4)) /* _i=0...127 */
4262#define I40E_VP_MDET_TX_MAX_INDEX 127
4263#define I40E_VP_MDET_TX_VALID_SHIFT 0
4264#define I40E_VP_MDET_TX_VALID_MASK (0x1 << I40E_VP_MDET_TX_VALID_SHIFT)
4265#define I40E_GLPM_WUMC 0x0006C800
4266#define I40E_GLPM_WUMC_NOTCO_SHIFT 0
4267#define I40E_GLPM_WUMC_NOTCO_MASK (0x1 << I40E_GLPM_WUMC_NOTCO_SHIFT)
4268#define I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT 1
4269#define I40E_GLPM_WUMC_SRST_PIN_VAL_MASK (0x1 << I40E_GLPM_WUMC_SRST_PIN_VAL_SHIFT)
4270#define I40E_GLPM_WUMC_ROL_MODE_SHIFT 2
4271#define I40E_GLPM_WUMC_ROL_MODE_MASK (0x1 << I40E_GLPM_WUMC_ROL_MODE_SHIFT)
4272#define I40E_GLPM_WUMC_RESERVED_4_SHIFT 3
4273#define I40E_GLPM_WUMC_RESERVED_4_MASK (0x1FFF << I40E_GLPM_WUMC_RESERVED_4_SHIFT)
4274#define I40E_GLPM_WUMC_MNG_WU_PF_SHIFT 16
4275#define I40E_GLPM_WUMC_MNG_WU_PF_MASK (0xFFFF << I40E_GLPM_WUMC_MNG_WU_PF_SHIFT)
4276#define I40E_PFPM_APM 0x000B8080
4277#define I40E_PFPM_APM_APME_SHIFT 0
4278#define I40E_PFPM_APM_APME_MASK (0x1 << I40E_PFPM_APM_APME_SHIFT)
4279#define I40E_PFPM_FHFT_DATA(_i, _j) (0x00060000 + ((_i) * 4096 + (_j) * 128))
4280#define I40E_PFPM_FHFT_DATA_MAX_INDEX 7
4281#define I40E_PFPM_FHFT_DATA_DWORD_SHIFT 0
4282#define I40E_PFPM_FHFT_DATA_DWORD_MASK (0xFFFFFFFF << I40E_PFPM_FHFT_DATA_DWORD_SHIFT)
4283#define I40E_PFPM_FHFT_LENGTH(_i) (0x0006A000 + ((_i) * 128)) /* _i=0...7 */
4284#define I40E_PFPM_FHFT_LENGTH_MAX_INDEX 7
4285#define I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT 0
4286#define I40E_PFPM_FHFT_LENGTH_LENGTH_MASK (0xFF << I40E_PFPM_FHFT_LENGTH_LENGTH_SHIFT)
4287#define I40E_PFPM_FHFT_MASK(_i, _j) (0x00068000 + ((_i) * 1024 + (_j) * 128))
4288#define I40E_PFPM_FHFT_MASK_MAX_INDEX 7
4289#define I40E_PFPM_FHFT_MASK_MASK_SHIFT 0
4290#define I40E_PFPM_FHFT_MASK_MASK_MASK (0xFFFF << I40E_PFPM_FHFT_MASK_MASK_SHIFT)
4291#define I40E_PFPM_PROXYFC 0x00245A80
4292#define I40E_PFPM_PROXYFC_PPROXYE_SHIFT 0
4293#define I40E_PFPM_PROXYFC_PPROXYE_MASK (0x1 << I40E_PFPM_PROXYFC_PPROXYE_SHIFT)
4294#define I40E_PFPM_PROXYFC_EX_SHIFT 1
4295#define I40E_PFPM_PROXYFC_EX_MASK (0x1 << I40E_PFPM_PROXYFC_EX_SHIFT)
4296#define I40E_PFPM_PROXYFC_ARP_SHIFT 4
4297#define I40E_PFPM_PROXYFC_ARP_MASK (0x1 << I40E_PFPM_PROXYFC_ARP_SHIFT)
4298#define I40E_PFPM_PROXYFC_ARP_DIRECTED_SHIFT 5
4299#define I40E_PFPM_PROXYFC_ARP_DIRECTED_MASK (0x1 << I40E_PFPM_PROXYFC_ARP_DIRECTED_SHIFT)
4300#define I40E_PFPM_PROXYFC_NS_SHIFT 9
4301#define I40E_PFPM_PROXYFC_NS_MASK (0x1 << I40E_PFPM_PROXYFC_NS_SHIFT)
4302#define I40E_PFPM_PROXYFC_NS_DIRECTED_SHIFT 10
4303#define I40E_PFPM_PROXYFC_NS_DIRECTED_MASK (0x1 << I40E_PFPM_PROXYFC_NS_DIRECTED_SHIFT)
4304#define I40E_PFPM_PROXYFC_MLD_SHIFT 12
4305#define I40E_PFPM_PROXYFC_MLD_MASK (0x1 << I40E_PFPM_PROXYFC_MLD_SHIFT)
4306#define I40E_PFPM_PROXYS 0x00245B80
4307#define I40E_PFPM_PROXYS_EX_SHIFT 1
4308#define I40E_PFPM_PROXYS_EX_MASK (0x1 << I40E_PFPM_PROXYS_EX_SHIFT)
4309#define I40E_PFPM_PROXYS_ARP_SHIFT 4
4310#define I40E_PFPM_PROXYS_ARP_MASK (0x1 << I40E_PFPM_PROXYS_ARP_SHIFT)
4311#define I40E_PFPM_PROXYS_ARP_DIRECTED_SHIFT 5
4312#define I40E_PFPM_PROXYS_ARP_DIRECTED_MASK (0x1 << I40E_PFPM_PROXYS_ARP_DIRECTED_SHIFT)
4313#define I40E_PFPM_PROXYS_NS_SHIFT 9
4314#define I40E_PFPM_PROXYS_NS_MASK (0x1 << I40E_PFPM_PROXYS_NS_SHIFT)
4315#define I40E_PFPM_PROXYS_NS_DIRECTED_SHIFT 10
4316#define I40E_PFPM_PROXYS_NS_DIRECTED_MASK (0x1 << I40E_PFPM_PROXYS_NS_DIRECTED_SHIFT)
4317#define I40E_PFPM_PROXYS_MLD_SHIFT 12
4318#define I40E_PFPM_PROXYS_MLD_MASK (0x1 << I40E_PFPM_PROXYS_MLD_SHIFT)
4319#define I40E_PFPM_WUC 0x0006B200
4320#define I40E_PFPM_WUC_EN_APM_D0_SHIFT 5
4321#define I40E_PFPM_WUC_EN_APM_D0_MASK (0x1 << I40E_PFPM_WUC_EN_APM_D0_SHIFT)
4322#define I40E_PFPM_WUFC 0x0006B400
4323#define I40E_PFPM_WUFC_LNKC_SHIFT 0
4324#define I40E_PFPM_WUFC_LNKC_MASK (0x1 << I40E_PFPM_WUFC_LNKC_SHIFT)
4325#define I40E_PFPM_WUFC_MAG_SHIFT 1
4326#define I40E_PFPM_WUFC_MAG_MASK (0x1 << I40E_PFPM_WUFC_MAG_SHIFT)
4327#define I40E_PFPM_WUFC_MNG_SHIFT 3
4328#define I40E_PFPM_WUFC_MNG_MASK (0x1 << I40E_PFPM_WUFC_MNG_SHIFT)
4329#define I40E_PFPM_WUFC_FLX0_ACT_SHIFT 4
4330#define I40E_PFPM_WUFC_FLX0_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX0_ACT_SHIFT)
4331#define I40E_PFPM_WUFC_FLX1_ACT_SHIFT 5
4332#define I40E_PFPM_WUFC_FLX1_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX1_ACT_SHIFT)
4333#define I40E_PFPM_WUFC_FLX2_ACT_SHIFT 6
4334#define I40E_PFPM_WUFC_FLX2_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX2_ACT_SHIFT)
4335#define I40E_PFPM_WUFC_FLX3_ACT_SHIFT 7
4336#define I40E_PFPM_WUFC_FLX3_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX3_ACT_SHIFT)
4337#define I40E_PFPM_WUFC_FLX4_ACT_SHIFT 8
4338#define I40E_PFPM_WUFC_FLX4_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX4_ACT_SHIFT)
4339#define I40E_PFPM_WUFC_FLX5_ACT_SHIFT 9
4340#define I40E_PFPM_WUFC_FLX5_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX5_ACT_SHIFT)
4341#define I40E_PFPM_WUFC_FLX6_ACT_SHIFT 10
4342#define I40E_PFPM_WUFC_FLX6_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX6_ACT_SHIFT)
4343#define I40E_PFPM_WUFC_FLX7_ACT_SHIFT 11
4344#define I40E_PFPM_WUFC_FLX7_ACT_MASK (0x1 << I40E_PFPM_WUFC_FLX7_ACT_SHIFT)
4345#define I40E_PFPM_WUFC_FLX0_SHIFT 16
4346#define I40E_PFPM_WUFC_FLX0_MASK (0x1 << I40E_PFPM_WUFC_FLX0_SHIFT)
4347#define I40E_PFPM_WUFC_FLX1_SHIFT 17
4348#define I40E_PFPM_WUFC_FLX1_MASK (0x1 << I40E_PFPM_WUFC_FLX1_SHIFT)
4349#define I40E_PFPM_WUFC_FLX2_SHIFT 18
4350#define I40E_PFPM_WUFC_FLX2_MASK (0x1 << I40E_PFPM_WUFC_FLX2_SHIFT)
4351#define I40E_PFPM_WUFC_FLX3_SHIFT 19
4352#define I40E_PFPM_WUFC_FLX3_MASK (0x1 << I40E_PFPM_WUFC_FLX3_SHIFT)
4353#define I40E_PFPM_WUFC_FLX4_SHIFT 20
4354#define I40E_PFPM_WUFC_FLX4_MASK (0x1 << I40E_PFPM_WUFC_FLX4_SHIFT)
4355#define I40E_PFPM_WUFC_FLX5_SHIFT 21
4356#define I40E_PFPM_WUFC_FLX5_MASK (0x1 << I40E_PFPM_WUFC_FLX5_SHIFT)
4357#define I40E_PFPM_WUFC_FLX6_SHIFT 22
4358#define I40E_PFPM_WUFC_FLX6_MASK (0x1 << I40E_PFPM_WUFC_FLX6_SHIFT)
4359#define I40E_PFPM_WUFC_FLX7_SHIFT 23
4360#define I40E_PFPM_WUFC_FLX7_MASK (0x1 << I40E_PFPM_WUFC_FLX7_SHIFT)
4361#define I40E_PFPM_WUFC_FW_RST_WK_SHIFT 31
4362#define I40E_PFPM_WUFC_FW_RST_WK_MASK (0x1 << I40E_PFPM_WUFC_FW_RST_WK_SHIFT)
4363#define I40E_PFPM_WUS 0x0006B600
4364#define I40E_PFPM_WUS_LNKC_SHIFT 0
4365#define I40E_PFPM_WUS_LNKC_MASK (0x1 << I40E_PFPM_WUS_LNKC_SHIFT)
4366#define I40E_PFPM_WUS_MAG_SHIFT 1
4367#define I40E_PFPM_WUS_MAG_MASK (0x1 << I40E_PFPM_WUS_MAG_SHIFT)
4368#define I40E_PFPM_WUS_PME_STATUS_SHIFT 2
4369#define I40E_PFPM_WUS_PME_STATUS_MASK (0x1 << I40E_PFPM_WUS_PME_STATUS_SHIFT)
4370#define I40E_PFPM_WUS_MNG_SHIFT 3
4371#define I40E_PFPM_WUS_MNG_MASK (0x1 << I40E_PFPM_WUS_MNG_SHIFT)
4372#define I40E_PFPM_WUS_FLX0_SHIFT 16
4373#define I40E_PFPM_WUS_FLX0_MASK (0x1 << I40E_PFPM_WUS_FLX0_SHIFT)
4374#define I40E_PFPM_WUS_FLX1_SHIFT 17
4375#define I40E_PFPM_WUS_FLX1_MASK (0x1 << I40E_PFPM_WUS_FLX1_SHIFT)
4376#define I40E_PFPM_WUS_FLX2_SHIFT 18
4377#define I40E_PFPM_WUS_FLX2_MASK (0x1 << I40E_PFPM_WUS_FLX2_SHIFT)
4378#define I40E_PFPM_WUS_FLX3_SHIFT 19
4379#define I40E_PFPM_WUS_FLX3_MASK (0x1 << I40E_PFPM_WUS_FLX3_SHIFT)
4380#define I40E_PFPM_WUS_FLX4_SHIFT 20
4381#define I40E_PFPM_WUS_FLX4_MASK (0x1 << I40E_PFPM_WUS_FLX4_SHIFT)
4382#define I40E_PFPM_WUS_FLX5_SHIFT 21
4383#define I40E_PFPM_WUS_FLX5_MASK (0x1 << I40E_PFPM_WUS_FLX5_SHIFT)
4384#define I40E_PFPM_WUS_FLX6_SHIFT 22
4385#define I40E_PFPM_WUS_FLX6_MASK (0x1 << I40E_PFPM_WUS_FLX6_SHIFT)
4386#define I40E_PFPM_WUS_FLX7_SHIFT 23
4387#define I40E_PFPM_WUS_FLX7_MASK (0x1 << I40E_PFPM_WUS_FLX7_SHIFT)
4388#define I40E_PFPM_WUS_FW_RST_WK_SHIFT 31
4389#define I40E_PFPM_WUS_FW_RST_WK_MASK (0x1 << I40E_PFPM_WUS_FW_RST_WK_SHIFT)
4390#define I40E_PRTPM_FHFHR 0x0006C000
4391#define I40E_PRTPM_FHFHR_UNICAST_SHIFT 0
4392#define I40E_PRTPM_FHFHR_UNICAST_MASK (0x1 << I40E_PRTPM_FHFHR_UNICAST_SHIFT)
4393#define I40E_PRTPM_FHFHR_MULTICAST_SHIFT 1
4394#define I40E_PRTPM_FHFHR_MULTICAST_MASK (0x1 << I40E_PRTPM_FHFHR_MULTICAST_SHIFT)
4395#define I40E_PRTPM_SAH(_i) (0x001E44C0 + ((_i) * 32)) /* _i=0...3 */
4396#define I40E_PRTPM_SAH_MAX_INDEX 3
4397#define I40E_PRTPM_SAH_PFPM_SAH_SHIFT 0
4398#define I40E_PRTPM_SAH_PFPM_SAH_MASK (0xFFFF << I40E_PRTPM_SAH_PFPM_SAH_SHIFT)
4399#define I40E_PRTPM_SAH_PF_NUM_SHIFT 26
4400#define I40E_PRTPM_SAH_PF_NUM_MASK (0xF << I40E_PRTPM_SAH_PF_NUM_SHIFT)
4401#define I40E_PRTPM_SAH_MC_MAG_EN_SHIFT 30
4402#define I40E_PRTPM_SAH_MC_MAG_EN_MASK (0x1 << I40E_PRTPM_SAH_MC_MAG_EN_SHIFT)
4403#define I40E_PRTPM_SAH_AV_SHIFT 31
4404#define I40E_PRTPM_SAH_AV_MASK (0x1 << I40E_PRTPM_SAH_AV_SHIFT)
4405#define I40E_PRTPM_SAL(_i) (0x001E4440 + ((_i) * 32)) /* _i=0...3 */
4406#define I40E_PRTPM_SAL_MAX_INDEX 3
4407#define I40E_PRTPM_SAL_PFPM_SAL_SHIFT 0
4408#define I40E_PRTPM_SAL_PFPM_SAL_MASK (0xFFFFFFFF << I40E_PRTPM_SAL_PFPM_SAL_SHIFT)
4409#define I40E_VF_ARQBAH1 0x00006000
4410#define I40E_VF_ARQBAH1_ARQBAH_SHIFT 0
4411#define I40E_VF_ARQBAH1_ARQBAH_MASK (0xFFFFFFFF << I40E_VF_ARQBAH1_ARQBAH_SHIFT)
4412#define I40E_VF_ARQBAL1 0x00006C00
4413#define I40E_VF_ARQBAL1_ARQBAL_SHIFT 0
4414#define I40E_VF_ARQBAL1_ARQBAL_MASK (0xFFFFFFFF << I40E_VF_ARQBAL1_ARQBAL_SHIFT)
4415#define I40E_VF_ARQH1 0x00007400
4416#define I40E_VF_ARQH1_ARQH_SHIFT 0
4417#define I40E_VF_ARQH1_ARQH_MASK (0x3FF << I40E_VF_ARQH1_ARQH_SHIFT)
4418#define I40E_VF_ARQLEN1 0x00008000
4419#define I40E_VF_ARQLEN1_ARQLEN_SHIFT 0
4420#define I40E_VF_ARQLEN1_ARQLEN_MASK (0x3FF << I40E_VF_ARQLEN1_ARQLEN_SHIFT)
4421#define I40E_VF_ARQLEN1_ARQVFE_SHIFT 28
4422#define I40E_VF_ARQLEN1_ARQVFE_MASK (0x1 << I40E_VF_ARQLEN1_ARQVFE_SHIFT)
4423#define I40E_VF_ARQLEN1_ARQOVFL_SHIFT 29
4424#define I40E_VF_ARQLEN1_ARQOVFL_MASK (0x1 << I40E_VF_ARQLEN1_ARQOVFL_SHIFT)
4425#define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30
4426#define I40E_VF_ARQLEN1_ARQCRIT_MASK (0x1 << I40E_VF_ARQLEN1_ARQCRIT_SHIFT)
4427#define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31
4428#define I40E_VF_ARQLEN1_ARQENABLE_MASK (0x1 << I40E_VF_ARQLEN1_ARQENABLE_SHIFT)
4429#define I40E_VF_ARQT1 0x00007000
4430#define I40E_VF_ARQT1_ARQT_SHIFT 0
4431#define I40E_VF_ARQT1_ARQT_MASK (0x3FF << I40E_VF_ARQT1_ARQT_SHIFT)
4432#define I40E_VF_ATQBAH1 0x00007800
4433#define I40E_VF_ATQBAH1_ATQBAH_SHIFT 0
4434#define I40E_VF_ATQBAH1_ATQBAH_MASK (0xFFFFFFFF << I40E_VF_ATQBAH1_ATQBAH_SHIFT)
4435#define I40E_VF_ATQBAL1 0x00007C00
4436#define I40E_VF_ATQBAL1_ATQBAL_SHIFT 0
4437#define I40E_VF_ATQBAL1_ATQBAL_MASK (0xFFFFFFFF << I40E_VF_ATQBAL1_ATQBAL_SHIFT)
4438#define I40E_VF_ATQH1 0x00006400
4439#define I40E_VF_ATQH1_ATQH_SHIFT 0
4440#define I40E_VF_ATQH1_ATQH_MASK (0x3FF << I40E_VF_ATQH1_ATQH_SHIFT)
4441#define I40E_VF_ATQLEN1 0x00006800
4442#define I40E_VF_ATQLEN1_ATQLEN_SHIFT 0
4443#define I40E_VF_ATQLEN1_ATQLEN_MASK (0x3FF << I40E_VF_ATQLEN1_ATQLEN_SHIFT)
4444#define I40E_VF_ATQLEN1_ATQVFE_SHIFT 28
4445#define I40E_VF_ATQLEN1_ATQVFE_MASK (0x1 << I40E_VF_ATQLEN1_ATQVFE_SHIFT)
4446#define I40E_VF_ATQLEN1_ATQOVFL_SHIFT 29
4447#define I40E_VF_ATQLEN1_ATQOVFL_MASK (0x1 << I40E_VF_ATQLEN1_ATQOVFL_SHIFT)
4448#define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30
4449#define I40E_VF_ATQLEN1_ATQCRIT_MASK (0x1 << I40E_VF_ATQLEN1_ATQCRIT_SHIFT)
4450#define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31
4451#define I40E_VF_ATQLEN1_ATQENABLE_MASK (0x1 << I40E_VF_ATQLEN1_ATQENABLE_SHIFT)
4452#define I40E_VF_ATQT1 0x00008400
4453#define I40E_VF_ATQT1_ATQT_SHIFT 0
4454#define I40E_VF_ATQT1_ATQT_MASK (0x3FF << I40E_VF_ATQT1_ATQT_SHIFT)
4455#define I40E_VFGEN_RSTAT 0x00008800
4456#define I40E_VFGEN_RSTAT_VFR_STATE_SHIFT 0
4457#define I40E_VFGEN_RSTAT_VFR_STATE_MASK (0x3 << I40E_VFGEN_RSTAT_VFR_STATE_SHIFT)
4458#define I40E_VFINT_DYN_CTL01 0x00005C00
4459#define I40E_VFINT_DYN_CTL01_INTENA_SHIFT 0
4460#define I40E_VFINT_DYN_CTL01_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTL01_INTENA_SHIFT)
4461#define I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1
4462#define I40E_VFINT_DYN_CTL01_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTL01_CLEARPBA_SHIFT)
4463#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2
4464#define I40E_VFINT_DYN_CTL01_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)
4465#define I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3
4466#define I40E_VFINT_DYN_CTL01_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT)
4467#define I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT 5
4468#define I40E_VFINT_DYN_CTL01_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT)
4469#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24
4470#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)
4471#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25
4472#define I40E_VFINT_DYN_CTL01_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
4473#define I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT 31
4474#define I40E_VFINT_DYN_CTL01_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTL01_INTENA_MSK_SHIFT)
4475#define I40E_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4))
4476#define I40E_VFINT_DYN_CTLN1_MAX_INDEX 15
4477#define I40E_VFINT_DYN_CTLN1_INTENA_SHIFT 0
4478#define I40E_VFINT_DYN_CTLN1_INTENA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_INTENA_SHIFT)
4479#define I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1
4480#define I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)
4481#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2
4482#define I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK (0x1 << I40E_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
4483#define I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3
4484#define I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)
4485#define I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5
4486#define I40E_VFINT_DYN_CTLN1_INTERVAL_MASK (0xFFF << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT)
4487#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24
4488#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK (0x1 << I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
4489#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25
4490#define I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK (0x3 << I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
4491#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31
4492#define I40E_VFINT_DYN_CTLN1_INTENA_MSK_MASK (0x1 << I40E_VFINT_DYN_CTLN1_INTENA_MSK_SHIFT)
4493#define I40E_VFINT_ICR0_ENA1 0x00005000
4494#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25
4495#define I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)
4496#define I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30
4497#define I40E_VFINT_ICR0_ENA1_ADMINQ_MASK (0x1 << I40E_VFINT_ICR0_ENA1_ADMINQ_SHIFT)
4498#define I40E_VFINT_ICR0_ENA1_RSVD_SHIFT 31
4499#define I40E_VFINT_ICR0_ENA1_RSVD_MASK (0x1 << I40E_VFINT_ICR0_ENA1_RSVD_SHIFT)
4500#define I40E_VFINT_ICR01 0x00004800
4501#define I40E_VFINT_ICR01_INTEVENT_SHIFT 0
4502#define I40E_VFINT_ICR01_INTEVENT_MASK (0x1 << I40E_VFINT_ICR01_INTEVENT_SHIFT)
4503#define I40E_VFINT_ICR01_QUEUE_0_SHIFT 1
4504#define I40E_VFINT_ICR01_QUEUE_0_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_0_SHIFT)
4505#define I40E_VFINT_ICR01_QUEUE_1_SHIFT 2
4506#define I40E_VFINT_ICR01_QUEUE_1_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_1_SHIFT)
4507#define I40E_VFINT_ICR01_QUEUE_2_SHIFT 3
4508#define I40E_VFINT_ICR01_QUEUE_2_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_2_SHIFT)
4509#define I40E_VFINT_ICR01_QUEUE_3_SHIFT 4
4510#define I40E_VFINT_ICR01_QUEUE_3_MASK (0x1 << I40E_VFINT_ICR01_QUEUE_3_SHIFT)
4511#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25
4512#define I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK (0x1 << I40E_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)
4513#define I40E_VFINT_ICR01_ADMINQ_SHIFT 30
4514#define I40E_VFINT_ICR01_ADMINQ_MASK (0x1 << I40E_VFINT_ICR01_ADMINQ_SHIFT)
4515#define I40E_VFINT_ICR01_SWINT_SHIFT 31
4516#define I40E_VFINT_ICR01_SWINT_MASK (0x1 << I40E_VFINT_ICR01_SWINT_SHIFT)
4517#define I40E_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */
4518#define I40E_VFINT_ITR01_MAX_INDEX 2
4519#define I40E_VFINT_ITR01_INTERVAL_SHIFT 0
4520#define I40E_VFINT_ITR01_INTERVAL_MASK (0xFFF << I40E_VFINT_ITR01_INTERVAL_SHIFT)
4521#define I40E_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4))
4522#define I40E_VFINT_ITRN1_MAX_INDEX 2
4523#define I40E_VFINT_ITRN1_INTERVAL_SHIFT 0
4524#define I40E_VFINT_ITRN1_INTERVAL_MASK (0xFFF << I40E_VFINT_ITRN1_INTERVAL_SHIFT)
4525#define I40E_VFINT_STAT_CTL01 0x00005400
4526#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2
4527#define I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_MASK (0x3 << I40E_VFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
4528#define I40E_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */
4529#define I40E_QRX_TAIL1_MAX_INDEX 15
4530#define I40E_QRX_TAIL1_TAIL_SHIFT 0
4531#define I40E_QRX_TAIL1_TAIL_MASK (0x1FFF << I40E_QRX_TAIL1_TAIL_SHIFT)
4532#define I40E_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */
4533#define I40E_QTX_TAIL1_MAX_INDEX 15
4534#define I40E_QTX_TAIL1_TAIL_SHIFT 0
4535#define I40E_QTX_TAIL1_TAIL_MASK (0x1FFF << I40E_QTX_TAIL1_TAIL_SHIFT)
4536#define I40E_VFMSIX_PBA 0x00002000
4537#define I40E_VFMSIX_PBA_PENBIT_SHIFT 0
4538#define I40E_VFMSIX_PBA_PENBIT_MASK (0xFFFFFFFF << I40E_VFMSIX_PBA_PENBIT_SHIFT)
4539#define I40E_VFMSIX_TADD(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */
4540#define I40E_VFMSIX_TADD_MAX_INDEX 16
4541#define I40E_VFMSIX_TADD_MSIXTADD10_SHIFT 0
4542#define I40E_VFMSIX_TADD_MSIXTADD10_MASK (0x3 << I40E_VFMSIX_TADD_MSIXTADD10_SHIFT)
4543#define I40E_VFMSIX_TADD_MSIXTADD_SHIFT 2
4544#define I40E_VFMSIX_TADD_MSIXTADD_MASK (0x3FFFFFFF << I40E_VFMSIX_TADD_MSIXTADD_SHIFT)
4545#define I40E_VFMSIX_TMSG(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */
4546#define I40E_VFMSIX_TMSG_MAX_INDEX 16
4547#define I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT 0
4548#define I40E_VFMSIX_TMSG_MSIXTMSG_MASK (0xFFFFFFFF << I40E_VFMSIX_TMSG_MSIXTMSG_SHIFT)
4549#define I40E_VFMSIX_TUADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */
4550#define I40E_VFMSIX_TUADD_MAX_INDEX 16
4551#define I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT 0
4552#define I40E_VFMSIX_TUADD_MSIXTUADD_MASK (0xFFFFFFFF << I40E_VFMSIX_TUADD_MSIXTUADD_SHIFT)
4553#define I40E_VFMSIX_TVCTRL(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */
4554#define I40E_VFMSIX_TVCTRL_MAX_INDEX 16
4555#define I40E_VFMSIX_TVCTRL_MASK_SHIFT 0
4556#define I40E_VFMSIX_TVCTRL_MASK_MASK (0x1 << I40E_VFMSIX_TVCTRL_MASK_SHIFT)
4557#define I40E_VFCM_PE_ERRDATA 0x0000DC00
4558#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
4559#define I40E_VFCM_PE_ERRDATA_ERROR_CODE_MASK (0xF << I40E_VFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
4560#define I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
4561#define I40E_VFCM_PE_ERRDATA_Q_TYPE_MASK (0x7 << I40E_VFCM_PE_ERRDATA_Q_TYPE_SHIFT)
4562#define I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT 8
4563#define I40E_VFCM_PE_ERRDATA_Q_NUM_MASK (0x3FFFF << I40E_VFCM_PE_ERRDATA_Q_NUM_SHIFT)
4564#define I40E_VFCM_PE_ERRINFO 0x0000D800
4565#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
4566#define I40E_VFCM_PE_ERRINFO_ERROR_VALID_MASK (0x1 << I40E_VFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
4567#define I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
4568#define I40E_VFCM_PE_ERRINFO_ERROR_INST_MASK (0x7 << I40E_VFCM_PE_ERRINFO_ERROR_INST_SHIFT)
4569#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
4570#define I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
4571#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
4572#define I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
4573#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
4574#define I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK (0xFF << I40E_VFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
4575#define I40E_VFPE_AEQALLOC1 0x0000A400
4576#define I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT 0
4577#define I40E_VFPE_AEQALLOC1_AECOUNT_MASK (0xFFFFFFFF << I40E_VFPE_AEQALLOC1_AECOUNT_SHIFT)
4578#define I40E_VFPE_CCQPHIGH1 0x00009800
4579#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0
4580#define I40E_VFPE_CCQPHIGH1_PECCQPHIGH_MASK (0xFFFFFFFF << I40E_VFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)
4581#define I40E_VFPE_CCQPLOW1 0x0000AC00
4582#define I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT 0
4583#define I40E_VFPE_CCQPLOW1_PECCQPLOW_MASK (0xFFFFFFFF << I40E_VFPE_CCQPLOW1_PECCQPLOW_SHIFT)
4584#define I40E_VFPE_CCQPSTATUS1 0x0000B800
4585#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0
4586#define I40E_VFPE_CCQPSTATUS1_CCQP_DONE_MASK (0x1 << I40E_VFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)
4587#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31
4588#define I40E_VFPE_CCQPSTATUS1_CCQP_ERR_MASK (0x1 << I40E_VFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)
4589#define I40E_VFPE_CQACK1 0x0000B000
4590#define I40E_VFPE_CQACK1_PECQID_SHIFT 0
4591#define I40E_VFPE_CQACK1_PECQID_MASK (0x1FFFF << I40E_VFPE_CQACK1_PECQID_SHIFT)
4592#define I40E_VFPE_CQARM1 0x0000B400
4593#define I40E_VFPE_CQARM1_PECQID_SHIFT 0
4594#define I40E_VFPE_CQARM1_PECQID_MASK (0x1FFFF << I40E_VFPE_CQARM1_PECQID_SHIFT)
4595#define I40E_VFPE_CQPDB1 0x0000BC00
4596#define I40E_VFPE_CQPDB1_WQHEAD_SHIFT 0
4597#define I40E_VFPE_CQPDB1_WQHEAD_MASK (0x7FF << I40E_VFPE_CQPDB1_WQHEAD_SHIFT)
4598#define I40E_VFPE_CQPERRCODES1 0x00009C00
4599#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0
4600#define I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
4601#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16
4602#define I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK (0xFFFF << I40E_VFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
4603#define I40E_VFPE_CQPTAIL1 0x0000A000
4604#define I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT 0
4605#define I40E_VFPE_CQPTAIL1_WQTAIL_MASK (0x7FF << I40E_VFPE_CQPTAIL1_WQTAIL_SHIFT)
4606#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31
4607#define I40E_VFPE_CQPTAIL1_CQP_OP_ERR_MASK (0x1 << I40E_VFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)
4608#define I40E_VFPE_IPCONFIG01 0x00008C00
4609#define I40E_VFPE_IPCONFIG01_PEIPID_SHIFT 0
4610#define I40E_VFPE_IPCONFIG01_PEIPID_MASK (0xFFFF << I40E_VFPE_IPCONFIG01_PEIPID_SHIFT)
4611#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16
4612#define I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
4613#define I40E_VFPE_IPCONFIG01_USEUPPERIDRANGE_SHIFT 17
4614#define I40E_VFPE_IPCONFIG01_USEUPPERIDRANGE_MASK (0x1 << I40E_VFPE_IPCONFIG01_USEUPPERIDRANGE_SHIFT)
4615#define I40E_VFPE_MRTEIDXMASK1 0x00009000
4616#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0
4617#define I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK (0x1F << I40E_VFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
4618#define I40E_VFPE_RCVUNEXPECTEDERROR1 0x00009400
4619#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0
4620#define I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK (0xFFFFFF << I40E_VFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)
4621#define I40E_VFPE_TCPNOWTIMER1 0x0000A800
4622#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0
4623#define I40E_VFPE_TCPNOWTIMER1_TCP_NOW_MASK (0xFFFFFFFF << I40E_VFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)
4624#define I40E_VFPE_WQEALLOC1 0x0000C000
4625#define I40E_VFPE_WQEALLOC1_PEQPID_SHIFT 0
4626#define I40E_VFPE_WQEALLOC1_PEQPID_MASK (0x3FFFF << I40E_VFPE_WQEALLOC1_PEQPID_SHIFT)
4627#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20
4628#define I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_MASK (0xFFF << I40E_VFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)
4629#define I40E_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */
4630#define I40E_VFQF_HENA_MAX_INDEX 1
4631#define I40E_VFQF_HENA_PTYPE_ENA_SHIFT 0
4632#define I40E_VFQF_HENA_PTYPE_ENA_MASK (0xFFFFFFFF << I40E_VFQF_HENA_PTYPE_ENA_SHIFT)
4633#define I40E_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */
4634#define I40E_VFQF_HKEY_MAX_INDEX 12
4635#define I40E_VFQF_HKEY_KEY_0_SHIFT 0
4636#define I40E_VFQF_HKEY_KEY_0_MASK (0xFF << I40E_VFQF_HKEY_KEY_0_SHIFT)
4637#define I40E_VFQF_HKEY_KEY_1_SHIFT 8
4638#define I40E_VFQF_HKEY_KEY_1_MASK (0xFF << I40E_VFQF_HKEY_KEY_1_SHIFT)
4639#define I40E_VFQF_HKEY_KEY_2_SHIFT 16
4640#define I40E_VFQF_HKEY_KEY_2_MASK (0xFF << I40E_VFQF_HKEY_KEY_2_SHIFT)
4641#define I40E_VFQF_HKEY_KEY_3_SHIFT 24
4642#define I40E_VFQF_HKEY_KEY_3_MASK (0xFF << I40E_VFQF_HKEY_KEY_3_SHIFT)
4643#define I40E_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */
4644#define I40E_VFQF_HLUT_MAX_INDEX 15
4645#define I40E_VFQF_HLUT_LUT0_SHIFT 0
4646#define I40E_VFQF_HLUT_LUT0_MASK (0xF << I40E_VFQF_HLUT_LUT0_SHIFT)
4647#define I40E_VFQF_HLUT_LUT1_SHIFT 8
4648#define I40E_VFQF_HLUT_LUT1_MASK (0xF << I40E_VFQF_HLUT_LUT1_SHIFT)
4649#define I40E_VFQF_HLUT_LUT2_SHIFT 16
4650#define I40E_VFQF_HLUT_LUT2_MASK (0xF << I40E_VFQF_HLUT_LUT2_SHIFT)
4651#define I40E_VFQF_HLUT_LUT3_SHIFT 24
4652#define I40E_VFQF_HLUT_LUT3_MASK (0xF << I40E_VFQF_HLUT_LUT3_SHIFT)
4653#define I40E_VFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */
4654#define I40E_VFQF_HREGION_MAX_INDEX 7
4655#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
4656#define I40E_VFQF_HREGION_OVERRIDE_ENA_0_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
4657#define I40E_VFQF_HREGION_REGION_0_SHIFT 1
4658#define I40E_VFQF_HREGION_REGION_0_MASK (0x7 << I40E_VFQF_HREGION_REGION_0_SHIFT)
4659#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
4660#define I40E_VFQF_HREGION_OVERRIDE_ENA_1_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
4661#define I40E_VFQF_HREGION_REGION_1_SHIFT 5
4662#define I40E_VFQF_HREGION_REGION_1_MASK (0x7 << I40E_VFQF_HREGION_REGION_1_SHIFT)
4663#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
4664#define I40E_VFQF_HREGION_OVERRIDE_ENA_2_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
4665#define I40E_VFQF_HREGION_REGION_2_SHIFT 9
4666#define I40E_VFQF_HREGION_REGION_2_MASK (0x7 << I40E_VFQF_HREGION_REGION_2_SHIFT)
4667#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
4668#define I40E_VFQF_HREGION_OVERRIDE_ENA_3_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
4669#define I40E_VFQF_HREGION_REGION_3_SHIFT 13
4670#define I40E_VFQF_HREGION_REGION_3_MASK (0x7 << I40E_VFQF_HREGION_REGION_3_SHIFT)
4671#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
4672#define I40E_VFQF_HREGION_OVERRIDE_ENA_4_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
4673#define I40E_VFQF_HREGION_REGION_4_SHIFT 17
4674#define I40E_VFQF_HREGION_REGION_4_MASK (0x7 << I40E_VFQF_HREGION_REGION_4_SHIFT)
4675#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
4676#define I40E_VFQF_HREGION_OVERRIDE_ENA_5_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
4677#define I40E_VFQF_HREGION_REGION_5_SHIFT 21
4678#define I40E_VFQF_HREGION_REGION_5_MASK (0x7 << I40E_VFQF_HREGION_REGION_5_SHIFT)
4679#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
4680#define I40E_VFQF_HREGION_OVERRIDE_ENA_6_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
4681#define I40E_VFQF_HREGION_REGION_6_SHIFT 25
4682#define I40E_VFQF_HREGION_REGION_6_MASK (0x7 << I40E_VFQF_HREGION_REGION_6_SHIFT)
4683#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
4684#define I40E_VFQF_HREGION_OVERRIDE_ENA_7_MASK (0x1 << I40E_VFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
4685#define I40E_VFQF_HREGION_REGION_7_SHIFT 29
4686#define I40E_VFQF_HREGION_REGION_7_MASK (0x7 << I40E_VFQF_HREGION_REGION_7_SHIFT)
4687
4688#endif
diff --git a/drivers/net/ethernet/intel/i40e/i40e_status.h b/drivers/net/ethernet/intel/i40e/i40e_status.h
new file mode 100644
index 000000000000..5e5bcddac573
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_status.h
@@ -0,0 +1,101 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_STATUS_H_
29#define _I40E_STATUS_H_
30
31/* Error Codes */
32enum i40e_status_code {
33 I40E_SUCCESS = 0,
34 I40E_ERR_NVM = -1,
35 I40E_ERR_NVM_CHECKSUM = -2,
36 I40E_ERR_PHY = -3,
37 I40E_ERR_CONFIG = -4,
38 I40E_ERR_PARAM = -5,
39 I40E_ERR_MAC_TYPE = -6,
40 I40E_ERR_UNKNOWN_PHY = -7,
41 I40E_ERR_LINK_SETUP = -8,
42 I40E_ERR_ADAPTER_STOPPED = -9,
43 I40E_ERR_INVALID_MAC_ADDR = -10,
44 I40E_ERR_DEVICE_NOT_SUPPORTED = -11,
45 I40E_ERR_MASTER_REQUESTS_PENDING = -12,
46 I40E_ERR_INVALID_LINK_SETTINGS = -13,
47 I40E_ERR_AUTONEG_NOT_COMPLETE = -14,
48 I40E_ERR_RESET_FAILED = -15,
49 I40E_ERR_SWFW_SYNC = -16,
50 I40E_ERR_NO_AVAILABLE_VSI = -17,
51 I40E_ERR_NO_MEMORY = -18,
52 I40E_ERR_BAD_PTR = -19,
53 I40E_ERR_RING_FULL = -20,
54 I40E_ERR_INVALID_PD_ID = -21,
55 I40E_ERR_INVALID_QP_ID = -22,
56 I40E_ERR_INVALID_CQ_ID = -23,
57 I40E_ERR_INVALID_CEQ_ID = -24,
58 I40E_ERR_INVALID_AEQ_ID = -25,
59 I40E_ERR_INVALID_SIZE = -26,
60 I40E_ERR_INVALID_ARP_INDEX = -27,
61 I40E_ERR_INVALID_FPM_FUNC_ID = -28,
62 I40E_ERR_QP_INVALID_MSG_SIZE = -29,
63 I40E_ERR_QP_TOOMANY_WRS_POSTED = -30,
64 I40E_ERR_INVALID_FRAG_COUNT = -31,
65 I40E_ERR_QUEUE_EMPTY = -32,
66 I40E_ERR_INVALID_ALIGNMENT = -33,
67 I40E_ERR_FLUSHED_QUEUE = -34,
68 I40E_ERR_INVALID_PUSH_PAGE_INDEX = -35,
69 I40E_ERR_INVALID_IMM_DATA_SIZE = -36,
70 I40E_ERR_TIMEOUT = -37,
71 I40E_ERR_OPCODE_MISMATCH = -38,
72 I40E_ERR_CQP_COMPL_ERROR = -39,
73 I40E_ERR_INVALID_VF_ID = -40,
74 I40E_ERR_INVALID_HMCFN_ID = -41,
75 I40E_ERR_BACKING_PAGE_ERROR = -42,
76 I40E_ERR_NO_PBLCHUNKS_AVAILABLE = -43,
77 I40E_ERR_INVALID_PBLE_INDEX = -44,
78 I40E_ERR_INVALID_SD_INDEX = -45,
79 I40E_ERR_INVALID_PAGE_DESC_INDEX = -46,
80 I40E_ERR_INVALID_SD_TYPE = -47,
81 I40E_ERR_MEMCPY_FAILED = -48,
82 I40E_ERR_INVALID_HMC_OBJ_INDEX = -49,
83 I40E_ERR_INVALID_HMC_OBJ_COUNT = -50,
84 I40E_ERR_INVALID_SRQ_ARM_LIMIT = -51,
85 I40E_ERR_SRQ_ENABLED = -52,
86 I40E_ERR_ADMIN_QUEUE_ERROR = -53,
87 I40E_ERR_ADMIN_QUEUE_TIMEOUT = -54,
88 I40E_ERR_BUF_TOO_SHORT = -55,
89 I40E_ERR_ADMIN_QUEUE_FULL = -56,
90 I40E_ERR_ADMIN_QUEUE_NO_WORK = -57,
91 I40E_ERR_BAD_IWARP_CQE = -58,
92 I40E_ERR_NVM_BLANK_MODE = -59,
93 I40E_ERR_NOT_IMPLEMENTED = -60,
94 I40E_ERR_PE_DOORBELL_NOT_ENABLED = -61,
95 I40E_ERR_DIAG_TEST_FAILED = -62,
96 I40E_ERR_NOT_READY = -63,
97 I40E_NOT_SUPPORTED = -64,
98 I40E_ERR_FIRMWARE_API_VERSION = -65,
99};
100
101#endif /* _I40E_STATUS_H_ */
diff --git a/drivers/net/ethernet/intel/i40e/i40e_type.h b/drivers/net/ethernet/intel/i40e/i40e_type.h
new file mode 100644
index 000000000000..f3f22b20f02f
--- /dev/null
+++ b/drivers/net/ethernet/intel/i40e/i40e_type.h
@@ -0,0 +1,1154 @@
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 *
22 * Contact Information:
23 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 *
26 ******************************************************************************/
27
28#ifndef _I40E_TYPE_H_
29#define _I40E_TYPE_H_
30
31#include "i40e_status.h"
32#include "i40e_osdep.h"
33#include "i40e_register.h"
34#include "i40e_adminq.h"
35#include "i40e_hmc.h"
36#include "i40e_lan_hmc.h"
37
38/* Device IDs */
39#define I40E_SFP_XL710_DEVICE_ID 0x1572
40#define I40E_SFP_X710_DEVICE_ID 0x1573
41#define I40E_QEMU_DEVICE_ID 0x1574
42#define I40E_KX_A_DEVICE_ID 0x157F
43#define I40E_KX_B_DEVICE_ID 0x1580
44#define I40E_KX_C_DEVICE_ID 0x1581
45#define I40E_KX_D_DEVICE_ID 0x1582
46#define I40E_QSFP_A_DEVICE_ID 0x1583
47#define I40E_QSFP_B_DEVICE_ID 0x1584
48#define I40E_QSFP_C_DEVICE_ID 0x1585
49#define I40E_VF_DEVICE_ID 0x154C
50#define I40E_VF_HV_DEVICE_ID 0x1571
51
52#define I40E_FW_API_VERSION_MAJOR 0x0001
53#define I40E_FW_API_VERSION_MINOR 0x0000
54
55#define I40E_MAX_VSI_QP 16
56#define I40E_MAX_VF_VSI 3
57#define I40E_MAX_CHAINED_RX_BUFFERS 5
58
59/* Max default timeout in ms, */
60#define I40E_MAX_NVM_TIMEOUT 18000
61
62/* Check whether address is multicast. This is little-endian specific check.*/
63#define I40E_IS_MULTICAST(address) \
64 (bool)(((u8 *)(address))[0] & ((u8)0x01))
65
66/* Check whether an address is broadcast. */
67#define I40E_IS_BROADCAST(address) \
68 ((((u8 *)(address))[0] == ((u8)0xff)) && \
69 (((u8 *)(address))[1] == ((u8)0xff)))
70
71/* Switch from mc to the 2usec global time (this is the GTIME resolution) */
72#define I40E_MS_TO_GTIME(time) (((time) * 1000) / 2)
73
74/* forward declaration */
75struct i40e_hw;
76typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
77
78#define I40E_ETH_LENGTH_OF_ADDRESS 6
79
80/* Data type manipulation macros. */
81
82#define I40E_DESC_UNUSED(R) \
83 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
84 (R)->next_to_clean - (R)->next_to_use - 1)
85
86/* bitfields for Tx queue mapping in QTX_CTL */
87#define I40E_QTX_CTL_VF_QUEUE 0x0
88#define I40E_QTX_CTL_PF_QUEUE 0x2
89
90/* debug masks */
91enum i40e_debug_mask {
92 I40E_DEBUG_INIT = 0x00000001,
93 I40E_DEBUG_RELEASE = 0x00000002,
94
95 I40E_DEBUG_LINK = 0x00000010,
96 I40E_DEBUG_PHY = 0x00000020,
97 I40E_DEBUG_HMC = 0x00000040,
98 I40E_DEBUG_NVM = 0x00000080,
99 I40E_DEBUG_LAN = 0x00000100,
100 I40E_DEBUG_FLOW = 0x00000200,
101 I40E_DEBUG_DCB = 0x00000400,
102 I40E_DEBUG_DIAG = 0x00000800,
103
104 I40E_DEBUG_AQ_MESSAGE = 0x01000000, /* for i40e_debug() */
105 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
106 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
107 I40E_DEBUG_AQ_COMMAND = 0x06000000, /* for i40e_debug_aq() */
108 I40E_DEBUG_AQ = 0x0F000000,
109
110 I40E_DEBUG_USER = 0xF0000000,
111
112 I40E_DEBUG_ALL = 0xFFFFFFFF
113};
114
115/* These are structs for managing the hardware information and the operations.
116 * The structures of function pointers are filled out at init time when we
117 * know for sure exactly which hardware we're working with. This gives us the
118 * flexibility of using the same main driver code but adapting to slightly
119 * different hardware needs as new parts are developed. For this architecture,
120 * the Firmware and AdminQ are intended to insulate the driver from most of the
121 * future changes, but these structures will also do part of the job.
122 */
123enum i40e_mac_type {
124 I40E_MAC_UNKNOWN = 0,
125 I40E_MAC_X710,
126 I40E_MAC_XL710,
127 I40E_MAC_VF,
128 I40E_MAC_GENERIC,
129};
130
131enum i40e_media_type {
132 I40E_MEDIA_TYPE_UNKNOWN = 0,
133 I40E_MEDIA_TYPE_FIBER,
134 I40E_MEDIA_TYPE_BASET,
135 I40E_MEDIA_TYPE_BACKPLANE,
136 I40E_MEDIA_TYPE_CX4,
137 I40E_MEDIA_TYPE_VIRTUAL
138};
139
140enum i40e_fc_mode {
141 I40E_FC_NONE = 0,
142 I40E_FC_RX_PAUSE,
143 I40E_FC_TX_PAUSE,
144 I40E_FC_FULL,
145 I40E_FC_PFC,
146 I40E_FC_DEFAULT
147};
148
149enum i40e_vsi_type {
150 I40E_VSI_MAIN = 0,
151 I40E_VSI_VMDQ1,
152 I40E_VSI_VMDQ2,
153 I40E_VSI_CTRL,
154 I40E_VSI_FCOE,
155 I40E_VSI_MIRROR,
156 I40E_VSI_SRIOV,
157 I40E_VSI_FDIR,
158 I40E_VSI_TYPE_UNKNOWN
159};
160
161enum i40e_queue_type {
162 I40E_QUEUE_TYPE_RX = 0,
163 I40E_QUEUE_TYPE_TX,
164 I40E_QUEUE_TYPE_PE_CEQ,
165 I40E_QUEUE_TYPE_UNKNOWN
166};
167
168struct i40e_link_status {
169 enum i40e_aq_phy_type phy_type;
170 enum i40e_aq_link_speed link_speed;
171 u8 link_info;
172 u8 an_info;
173 u8 ext_info;
174 /* is Link Status Event notification to SW enabled */
175 bool lse_enable;
176};
177
178struct i40e_phy_info {
179 struct i40e_link_status link_info;
180 struct i40e_link_status link_info_old;
181 u32 autoneg_advertised;
182 u32 phy_id;
183 u32 module_type;
184 bool get_link_info;
185 enum i40e_media_type media_type;
186};
187
188#define I40E_HW_CAP_MAX_GPIO 30
189/* Capabilities of a PF or a VF or the whole device */
190struct i40e_hw_capabilities {
191 u32 switch_mode;
192#define I40E_NVM_IMAGE_TYPE_EVB 0x0
193#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
194#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
195
196 u32 management_mode;
197 u32 npar_enable;
198 u32 os2bmc;
199 u32 valid_functions;
200 bool sr_iov_1_1;
201 bool vmdq;
202 bool evb_802_1_qbg; /* Edge Virtual Bridging */
203 bool evb_802_1_qbh; /* Bridge Port Extension */
204 bool dcb;
205 bool fcoe;
206 bool mfp_mode_1;
207 bool mgmt_cem;
208 bool ieee_1588;
209 bool iwarp;
210 bool fd;
211 u32 fd_filters_guaranteed;
212 u32 fd_filters_best_effort;
213 bool rss;
214 u32 rss_table_size;
215 u32 rss_table_entry_width;
216 bool led[I40E_HW_CAP_MAX_GPIO];
217 bool sdp[I40E_HW_CAP_MAX_GPIO];
218 u32 nvm_image_type;
219 u32 num_flow_director_filters;
220 u32 num_vfs;
221 u32 vf_base_id;
222 u32 num_vsis;
223 u32 num_rx_qp;
224 u32 num_tx_qp;
225 u32 base_queue;
226 u32 num_msix_vectors;
227 u32 num_msix_vectors_vf;
228 u32 led_pin_num;
229 u32 sdp_pin_num;
230 u32 mdio_port_num;
231 u32 mdio_port_mode;
232 u8 rx_buf_chain_len;
233 u32 enabled_tcmap;
234 u32 maxtc;
235};
236
237struct i40e_mac_info {
238 enum i40e_mac_type type;
239 u8 addr[I40E_ETH_LENGTH_OF_ADDRESS];
240 u8 perm_addr[I40E_ETH_LENGTH_OF_ADDRESS];
241 u8 san_addr[I40E_ETH_LENGTH_OF_ADDRESS];
242 u16 max_fcoeq;
243};
244
245enum i40e_aq_resources_ids {
246 I40E_NVM_RESOURCE_ID = 1
247};
248
249enum i40e_aq_resource_access_type {
250 I40E_RESOURCE_READ = 1,
251 I40E_RESOURCE_WRITE
252};
253
254struct i40e_nvm_info {
255 u64 hw_semaphore_timeout; /* 2usec global time (GTIME resolution) */
256 u64 hw_semaphore_wait; /* - || - */
257 u32 timeout; /* [ms] */
258 u16 sr_size; /* Shadow RAM size in words */
259 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
260 u16 version; /* NVM package version */
261 u32 eetrack; /* NVM data version */
262};
263
264/* PCI bus types */
265enum i40e_bus_type {
266 i40e_bus_type_unknown = 0,
267 i40e_bus_type_pci,
268 i40e_bus_type_pcix,
269 i40e_bus_type_pci_express,
270 i40e_bus_type_reserved
271};
272
273/* PCI bus speeds */
274enum i40e_bus_speed {
275 i40e_bus_speed_unknown = 0,
276 i40e_bus_speed_33 = 33,
277 i40e_bus_speed_66 = 66,
278 i40e_bus_speed_100 = 100,
279 i40e_bus_speed_120 = 120,
280 i40e_bus_speed_133 = 133,
281 i40e_bus_speed_2500 = 2500,
282 i40e_bus_speed_5000 = 5000,
283 i40e_bus_speed_8000 = 8000,
284 i40e_bus_speed_reserved
285};
286
287/* PCI bus widths */
288enum i40e_bus_width {
289 i40e_bus_width_unknown = 0,
290 i40e_bus_width_pcie_x1 = 1,
291 i40e_bus_width_pcie_x2 = 2,
292 i40e_bus_width_pcie_x4 = 4,
293 i40e_bus_width_pcie_x8 = 8,
294 i40e_bus_width_32 = 32,
295 i40e_bus_width_64 = 64,
296 i40e_bus_width_reserved
297};
298
299/* Bus parameters */
300struct i40e_bus_info {
301 enum i40e_bus_speed speed;
302 enum i40e_bus_width width;
303 enum i40e_bus_type type;
304
305 u16 func;
306 u16 device;
307 u16 lan_id;
308};
309
310/* Flow control (FC) parameters */
311struct i40e_fc_info {
312 enum i40e_fc_mode current_mode; /* FC mode in effect */
313 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
314};
315
316#define I40E_MAX_TRAFFIC_CLASS 8
317#define I40E_MAX_USER_PRIORITY 8
318#define I40E_DCBX_MAX_APPS 32
319#define I40E_LLDPDU_SIZE 1500
320
321/* IEEE 802.1Qaz ETS Configuration data */
322struct i40e_ieee_ets_config {
323 u8 willing;
324 u8 cbs;
325 u8 maxtcs;
326 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
327 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
328 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
329};
330
331/* IEEE 802.1Qaz ETS Recommendation data */
332struct i40e_ieee_ets_recommend {
333 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
334 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
335 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
336};
337
338/* IEEE 802.1Qaz PFC Configuration data */
339struct i40e_ieee_pfc_config {
340 u8 willing;
341 u8 mbc;
342 u8 pfccap;
343 u8 pfcenable;
344};
345
346/* IEEE 802.1Qaz Application Priority data */
347struct i40e_ieee_app_priority_table {
348 u8 priority;
349 u8 selector;
350 u16 protocolid;
351};
352
353struct i40e_dcbx_config {
354 u32 numapps;
355 struct i40e_ieee_ets_config etscfg;
356 struct i40e_ieee_ets_recommend etsrec;
357 struct i40e_ieee_pfc_config pfc;
358 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
359};
360
361/* Port hardware description */
362struct i40e_hw {
363 u8 __iomem *hw_addr;
364 void *back;
365
366 /* function pointer structs */
367 struct i40e_phy_info phy;
368 struct i40e_mac_info mac;
369 struct i40e_bus_info bus;
370 struct i40e_nvm_info nvm;
371 struct i40e_fc_info fc;
372
373 /* pci info */
374 u16 device_id;
375 u16 vendor_id;
376 u16 subsystem_device_id;
377 u16 subsystem_vendor_id;
378 u8 revision_id;
379 u8 port;
380 bool adapter_stopped;
381
382 /* capabilities for entire device and PCI func */
383 struct i40e_hw_capabilities dev_caps;
384 struct i40e_hw_capabilities func_caps;
385
386 /* Flow Director shared filter space */
387 u16 fdir_shared_filter_count;
388
389 /* device profile info */
390 u8 pf_id;
391 u16 main_vsi_seid;
392
393 /* Closest numa node to the device */
394 u16 numa_node;
395
396 /* Admin Queue info */
397 struct i40e_adminq_info aq;
398
399 /* HMC info */
400 struct i40e_hmc_info hmc; /* HMC info struct */
401
402 /* LLDP/DCBX Status */
403 u16 dcbx_status;
404
405 /* DCBX info */
406 struct i40e_dcbx_config local_dcbx_config;
407 struct i40e_dcbx_config remote_dcbx_config;
408
409 /* debug mask */
410 u32 debug_mask;
411};
412
413struct i40e_driver_version {
414 u8 major_version;
415 u8 minor_version;
416 u8 build_version;
417 u8 subbuild_version;
418};
419
420/* RX Descriptors */
421union i40e_16byte_rx_desc {
422 struct {
423 __le64 pkt_addr; /* Packet buffer address */
424 __le64 hdr_addr; /* Header buffer address */
425 } read;
426 struct {
427 struct {
428 struct {
429 union {
430 __le16 mirroring_status;
431 __le16 fcoe_ctx_id;
432 } mirr_fcoe;
433 __le16 l2tag1;
434 } lo_dword;
435 union {
436 __le32 rss; /* RSS Hash */
437 __le32 fd_id; /* Flow director filter id */
438 __le32 fcoe_param; /* FCoE DDP Context id */
439 } hi_dword;
440 } qword0;
441 struct {
442 /* ext status/error/pktype/length */
443 __le64 status_error_len;
444 } qword1;
445 } wb; /* writeback */
446};
447
448union i40e_32byte_rx_desc {
449 struct {
450 __le64 pkt_addr; /* Packet buffer address */
451 __le64 hdr_addr; /* Header buffer address */
452 /* bit 0 of hdr_buffer_addr is DD bit */
453 __le64 rsvd1;
454 __le64 rsvd2;
455 } read;
456 struct {
457 struct {
458 struct {
459 union {
460 __le16 mirroring_status;
461 __le16 fcoe_ctx_id;
462 } mirr_fcoe;
463 __le16 l2tag1;
464 } lo_dword;
465 union {
466 __le32 rss; /* RSS Hash */
467 __le32 fcoe_param; /* FCoE DDP Context id */
468 } hi_dword;
469 } qword0;
470 struct {
471 /* status/error/pktype/length */
472 __le64 status_error_len;
473 } qword1;
474 struct {
475 __le16 ext_status; /* extended status */
476 __le16 rsvd;
477 __le16 l2tag2_1;
478 __le16 l2tag2_2;
479 } qword2;
480 struct {
481 union {
482 __le32 flex_bytes_lo;
483 __le32 pe_status;
484 } lo_dword;
485 union {
486 __le32 flex_bytes_hi;
487 __le32 fd_id;
488 } hi_dword;
489 } qword3;
490 } wb; /* writeback */
491};
492
493#define I40E_RXD_QW1_STATUS_SHIFT 0
494#define I40E_RXD_QW1_STATUS_MASK (0x7FFFUL << I40E_RXD_QW1_STATUS_SHIFT)
495
496enum i40e_rx_desc_status_bits {
497 /* Note: These are predefined bit offsets */
498 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
499 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
500 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
501 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
502 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
503 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 3 BITS */
504 I40E_RX_DESC_STATUS_PIF_SHIFT = 8,
505 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
506 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
507 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
508 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14
509};
510
511#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
512#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x7UL << \
513 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
514
515enum i40e_rx_desc_fltstat_values {
516 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
517 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
518 I40E_RX_DESC_FLTSTAT_RSV = 2,
519 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
520};
521
522#define I40E_RXD_QW1_ERROR_SHIFT 19
523#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
524
525enum i40e_rx_desc_error_bits {
526 /* Note: These are predefined bit offsets */
527 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
528 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
529 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
530 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
531 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
532 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
533 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
534 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6
535};
536
537enum i40e_rx_desc_error_l3l4e_fcoe_masks {
538 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
539 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
540 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
541 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
542 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
543};
544
545#define I40E_RXD_QW1_PTYPE_SHIFT 30
546#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
547
548/* Packet type non-ip values */
549enum i40e_rx_l2_ptype {
550 I40E_RX_PTYPE_L2_RESERVED = 0,
551 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
552 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
553 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
554 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
555 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
556 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
557 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
558 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
559 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
560 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
561 I40E_RX_PTYPE_L2_ARP = 11,
562 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
563 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
564 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
565 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
566 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
567 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
568 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
569 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
570 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
571 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21
572};
573
574struct i40e_rx_ptype_decoded {
575 u32 ptype:8;
576 u32 known:1;
577 u32 outer_ip:1;
578 u32 outer_ip_ver:1;
579 u32 outer_frag:1;
580 u32 tunnel_type:3;
581 u32 tunnel_end_prot:2;
582 u32 tunnel_end_frag:1;
583 u32 inner_prot:4;
584 u32 payload_layer:3;
585};
586
587enum i40e_rx_ptype_outer_ip {
588 I40E_RX_PTYPE_OUTER_L2 = 0,
589 I40E_RX_PTYPE_OUTER_IP = 1
590};
591
592enum i40e_rx_ptype_outer_ip_ver {
593 I40E_RX_PTYPE_OUTER_NONE = 0,
594 I40E_RX_PTYPE_OUTER_IPV4 = 0,
595 I40E_RX_PTYPE_OUTER_IPV6 = 1
596};
597
598enum i40e_rx_ptype_outer_fragmented {
599 I40E_RX_PTYPE_NOT_FRAG = 0,
600 I40E_RX_PTYPE_FRAG = 1
601};
602
603enum i40e_rx_ptype_tunnel_type {
604 I40E_RX_PTYPE_TUNNEL_NONE = 0,
605 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
606 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
607 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
608 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
609};
610
611enum i40e_rx_ptype_tunnel_end_prot {
612 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
613 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
614 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
615};
616
617enum i40e_rx_ptype_inner_prot {
618 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
619 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
620 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
621 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
622 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
623 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
624};
625
626enum i40e_rx_ptype_payload_layer {
627 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
628 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
629 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
630 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
631};
632
633#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
634#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
635 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
636
637#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
638#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
639 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
640
641#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
642#define I40E_RXD_QW1_LENGTH_SPH_MASK (0x1ULL << \
643 I40E_RXD_QW1_LENGTH_SPH_SHIFT)
644
645enum i40e_rx_desc_ext_status_bits {
646 /* Note: These are predefined bit offsets */
647 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
648 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
649 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
650 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
651 I40E_RX_DESC_EXT_STATUS_FTYPE_SHIFT = 6, /* 3 BITS */
652 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
653 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
654 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
655};
656
657enum i40e_rx_desc_pe_status_bits {
658 /* Note: These are predefined bit offsets */
659 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
660 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
661 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
662 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
663 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
664 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
665 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
666 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
667 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
668};
669
670#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
671#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
672
673#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
674#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
675 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
676
677#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
678#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
679 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
680
681enum i40e_rx_prog_status_desc_status_bits {
682 /* Note: These are predefined bit offsets */
683 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
684 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
685};
686
687enum i40e_rx_prog_status_desc_prog_id_masks {
688 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
689 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
690 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
691};
692
693enum i40e_rx_prog_status_desc_error_bits {
694 /* Note: These are predefined bit offsets */
695 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
696 I40E_RX_PROG_STATUS_DESC_NO_FD_QUOTA_SHIFT = 1,
697 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
698 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
699};
700
701/* TX Descriptor */
702struct i40e_tx_desc {
703 __le64 buffer_addr; /* Address of descriptor's data buf */
704 __le64 cmd_type_offset_bsz;
705};
706
707#define I40E_TXD_QW1_DTYPE_SHIFT 0
708#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
709
710enum i40e_tx_desc_dtype_value {
711 I40E_TX_DESC_DTYPE_DATA = 0x0,
712 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
713 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
714 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
715 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
716 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
717 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
718 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
719 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
720 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
721};
722
723#define I40E_TXD_QW1_CMD_SHIFT 4
724#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
725
726enum i40e_tx_desc_cmd_bits {
727 I40E_TX_DESC_CMD_EOP = 0x0001,
728 I40E_TX_DESC_CMD_RS = 0x0002,
729 I40E_TX_DESC_CMD_ICRC = 0x0004,
730 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
731 I40E_TX_DESC_CMD_DUMMY = 0x0010,
732 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
733 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
734 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
735 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
736 I40E_TX_DESC_CMD_FCOET = 0x0080,
737 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
738 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
739 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
740 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
741 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
742 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
743 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
744 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
745};
746
747#define I40E_TXD_QW1_OFFSET_SHIFT 16
748#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
749 I40E_TXD_QW1_OFFSET_SHIFT)
750
751enum i40e_tx_desc_length_fields {
752 /* Note: These are predefined bit offsets */
753 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
754 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
755 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
756};
757
758#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
759#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
760 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
761
762#define I40E_TXD_QW1_L2TAG1_SHIFT 48
763#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
764
765/* Context descriptors */
766struct i40e_tx_context_desc {
767 __le32 tunneling_params;
768 __le16 l2tag2;
769 __le16 rsvd;
770 __le64 type_cmd_tso_mss;
771};
772
773#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
774#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
775
776#define I40E_TXD_CTX_QW1_CMD_SHIFT 4
777#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
778
779enum i40e_tx_ctx_desc_cmd_bits {
780 I40E_TX_CTX_DESC_TSO = 0x01,
781 I40E_TX_CTX_DESC_TSYN = 0x02,
782 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
783 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
784 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
785 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
786 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
787 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
788 I40E_TX_CTX_DESC_SWPE = 0x40
789};
790
791#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
792#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
793 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
794
795#define I40E_TXD_CTX_QW1_MSS_SHIFT 50
796#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
797 I40E_TXD_CTX_QW1_MSS_SHIFT)
798
799#define I40E_TXD_CTX_QW1_VSI_SHIFT 50
800#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
801
802#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
803#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
804 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
805
806enum i40e_tx_ctx_desc_eipt_offload {
807 I40E_TX_CTX_EXT_IP_NONE = 0x0,
808 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
809 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
810 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
811};
812
813#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
814#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
815 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
816
817#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
818#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
819
820#define I40E_TXD_CTX_UDP_TUNNELING (0x1ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
821#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
822
823#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
824#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK (0x1ULL << \
825 I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
826
827#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
828
829#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
830#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
831 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
832
833#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
834#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
835 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
836
837struct i40e_filter_program_desc {
838 __le32 qindex_flex_ptype_vsi;
839 __le32 rsvd;
840 __le32 dtype_cmd_cntindex;
841 __le32 fd_id;
842};
843#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
844#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
845 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
846#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
847#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
848 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
849#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
850#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
851 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
852
853/* Packet Classifier Types for filters */
854enum i40e_filter_pctype {
855 /* Note: Value 0-25 are reserved for future use */
856 I40E_FILTER_PCTYPE_IPV4_TEREDO_UDP = 26,
857 I40E_FILTER_PCTYPE_IPV6_TEREDO_UDP = 27,
858 I40E_FILTER_PCTYPE_NONF_IPV4_1588_UDP = 28,
859 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
860 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
861 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
862 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN = 32,
863 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
864 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
865 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
866 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
867 /* Note: Value 37 is reserved for future use */
868 I40E_FILTER_PCTYPE_NONF_IPV6_1588_UDP = 38,
869 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
870 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
871 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
872 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN = 42,
873 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
874 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
875 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
876 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
877 /* Note: Value 47 is reserved for future use */
878 I40E_FILTER_PCTYPE_FCOE_OX = 48,
879 I40E_FILTER_PCTYPE_FCOE_RX = 49,
880 /* Note: Value 50-62 are reserved for future use */
881 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
882};
883
884enum i40e_filter_program_desc_dest {
885 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
886 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
887 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
888};
889
890enum i40e_filter_program_desc_fd_status {
891 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
892 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
893 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
894 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
895};
896
897#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
898#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
899 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
900
901#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
902#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
903 I40E_TXD_FLTR_QW1_CMD_SHIFT)
904
905#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
906#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
907
908enum i40e_filter_program_desc_pcmd {
909 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
910 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
911};
912
913#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
914#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
915
916#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
917#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK (0x1ULL << \
918 I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
919
920#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
921 I40E_TXD_FLTR_QW1_CMD_SHIFT)
922#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
923 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
924
925#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
926#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
927 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
928
929enum i40e_filter_type {
930 I40E_FLOW_DIRECTOR_FLTR = 0,
931 I40E_PE_QUAD_HASH_FLTR = 1,
932 I40E_ETHERTYPE_FLTR,
933 I40E_FCOE_CTX_FLTR,
934 I40E_MAC_VLAN_FLTR,
935 I40E_HASH_FLTR
936};
937
938struct i40e_vsi_context {
939 u16 seid;
940 u16 uplink_seid;
941 u16 vsi_number;
942 u16 vsis_allocated;
943 u16 vsis_unallocated;
944 u16 flags;
945 u8 pf_num;
946 u8 vf_num;
947 u8 connection_type;
948 struct i40e_aqc_vsi_properties_data info;
949};
950
951/* Statistics collected by each port, VSI, VEB, and S-channel */
952struct i40e_eth_stats {
953 u64 rx_bytes; /* gorc */
954 u64 rx_unicast; /* uprc */
955 u64 rx_multicast; /* mprc */
956 u64 rx_broadcast; /* bprc */
957 u64 rx_discards; /* rdpc */
958 u64 rx_errors; /* repc */
959 u64 rx_missed; /* rmpc */
960 u64 rx_unknown_protocol; /* rupp */
961 u64 tx_bytes; /* gotc */
962 u64 tx_unicast; /* uptc */
963 u64 tx_multicast; /* mptc */
964 u64 tx_broadcast; /* bptc */
965 u64 tx_discards; /* tdpc */
966 u64 tx_errors; /* tepc */
967};
968
969/* Statistics collected by the MAC */
970struct i40e_hw_port_stats {
971 /* eth stats collected by the port */
972 struct i40e_eth_stats eth;
973
974 /* additional port specific stats */
975 u64 tx_dropped_link_down; /* tdold */
976 u64 crc_errors; /* crcerrs */
977 u64 illegal_bytes; /* illerrc */
978 u64 error_bytes; /* errbc */
979 u64 mac_local_faults; /* mlfc */
980 u64 mac_remote_faults; /* mrfc */
981 u64 rx_length_errors; /* rlec */
982 u64 link_xon_rx; /* lxonrxc */
983 u64 link_xoff_rx; /* lxoffrxc */
984 u64 priority_xon_rx[8]; /* pxonrxc[8] */
985 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
986 u64 link_xon_tx; /* lxontxc */
987 u64 link_xoff_tx; /* lxofftxc */
988 u64 priority_xon_tx[8]; /* pxontxc[8] */
989 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
990 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
991 u64 rx_size_64; /* prc64 */
992 u64 rx_size_127; /* prc127 */
993 u64 rx_size_255; /* prc255 */
994 u64 rx_size_511; /* prc511 */
995 u64 rx_size_1023; /* prc1023 */
996 u64 rx_size_1522; /* prc1522 */
997 u64 rx_size_big; /* prc9522 */
998 u64 rx_undersize; /* ruc */
999 u64 rx_fragments; /* rfc */
1000 u64 rx_oversize; /* roc */
1001 u64 rx_jabber; /* rjc */
1002 u64 tx_size_64; /* ptc64 */
1003 u64 tx_size_127; /* ptc127 */
1004 u64 tx_size_255; /* ptc255 */
1005 u64 tx_size_511; /* ptc511 */
1006 u64 tx_size_1023; /* ptc1023 */
1007 u64 tx_size_1522; /* ptc1522 */
1008 u64 tx_size_big; /* ptc9522 */
1009 u64 mac_short_packet_dropped; /* mspdc */
1010 u64 checksum_error; /* xec */
1011};
1012
1013/* Checksum and Shadow RAM pointers */
1014#define I40E_SR_NVM_CONTROL_WORD 0x00
1015#define I40E_SR_EMP_MODULE_PTR 0x0F
1016#define I40E_SR_NVM_IMAGE_VERSION 0x18
1017#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1018#define I40E_SR_NVM_EETRACK_LO 0x2D
1019#define I40E_SR_NVM_EETRACK_HI 0x2E
1020#define I40E_SR_VPD_PTR 0x2F
1021#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1022#define I40E_SR_SW_CHECKSUM_WORD 0x3F
1023
1024/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1025#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1026#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1027#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1028#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1029
1030/* Shadow RAM related */
1031#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1032#define I40E_SR_WORDS_IN_1KB 512
1033/* Checksum should be calculated such that after adding all the words,
1034 * including the checksum word itself, the sum should be 0xBABA.
1035 */
1036#define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1037
1038#define I40E_SRRD_SRCTL_ATTEMPTS 100000
1039
1040enum i40e_switch_element_types {
1041 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1042 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1043 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1044 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1045 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1046 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1047 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1048 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1049 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1050};
1051
1052/* Supported EtherType filters */
1053enum i40e_ether_type_index {
1054 I40E_ETHER_TYPE_1588 = 0,
1055 I40E_ETHER_TYPE_FIP = 1,
1056 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1057 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1058 I40E_ETHER_TYPE_LLDP = 4,
1059 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1060 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1061 I40E_ETHER_TYPE_QCN_CNM = 7,
1062 I40E_ETHER_TYPE_8021X = 8,
1063 I40E_ETHER_TYPE_ARP = 9,
1064 I40E_ETHER_TYPE_RSV1 = 10,
1065 I40E_ETHER_TYPE_RSV2 = 11,
1066};
1067
1068/* Filter context base size is 1K */
1069#define I40E_HASH_FILTER_BASE_SIZE 1024
1070/* Supported Hash filter values */
1071enum i40e_hash_filter_size {
1072 I40E_HASH_FILTER_SIZE_1K = 0,
1073 I40E_HASH_FILTER_SIZE_2K = 1,
1074 I40E_HASH_FILTER_SIZE_4K = 2,
1075 I40E_HASH_FILTER_SIZE_8K = 3,
1076 I40E_HASH_FILTER_SIZE_16K = 4,
1077 I40E_HASH_FILTER_SIZE_32K = 5,
1078 I40E_HASH_FILTER_SIZE_64K = 6,
1079 I40E_HASH_FILTER_SIZE_128K = 7,
1080 I40E_HASH_FILTER_SIZE_256K = 8,
1081 I40E_HASH_FILTER_SIZE_512K = 9,
1082 I40E_HASH_FILTER_SIZE_1M = 10,
1083};
1084
1085/* DMA context base size is 0.5K */
1086#define I40E_DMA_CNTX_BASE_SIZE 512
1087/* Supported DMA context values */
1088enum i40e_dma_cntx_size {
1089 I40E_DMA_CNTX_SIZE_512 = 0,
1090 I40E_DMA_CNTX_SIZE_1K = 1,
1091 I40E_DMA_CNTX_SIZE_2K = 2,
1092 I40E_DMA_CNTX_SIZE_4K = 3,
1093 I40E_DMA_CNTX_SIZE_8K = 4,
1094 I40E_DMA_CNTX_SIZE_16K = 5,
1095 I40E_DMA_CNTX_SIZE_32K = 6,
1096 I40E_DMA_CNTX_SIZE_64K = 7,
1097 I40E_DMA_CNTX_SIZE_128K = 8,
1098 I40E_DMA_CNTX_SIZE_256K = 9,
1099};
1100
1101/* Supported Hash look up table (LUT) sizes */
1102enum i40e_hash_lut_size {
1103 I40E_HASH_LUT_SIZE_128 = 0,
1104 I40E_HASH_LUT_SIZE_512 = 1,
1105};
1106
1107/* Structure to hold a per PF filter control settings */
1108struct i40e_filter_control_settings {
1109 /* number of PE Quad Hash filter buckets */
1110 enum i40e_hash_filter_size pe_filt_num;
1111 /* number of PE Quad Hash contexts */
1112 enum i40e_dma_cntx_size pe_cntx_num;
1113 /* number of FCoE filter buckets */
1114 enum i40e_hash_filter_size fcoe_filt_num;
1115 /* number of FCoE DDP contexts */
1116 enum i40e_dma_cntx_size fcoe_cntx_num;
1117 /* size of the Hash LUT */
1118 enum i40e_hash_lut_size hash_lut_size;
1119 /* enable FDIR filters for PF and its VFs */
1120 bool enable_fdir;
1121 /* enable Ethertype filters for PF and its VFs */
1122 bool enable_ethtype;
1123 /* enable MAC/VLAN filters for PF and its VFs */
1124 bool enable_macvlan;
1125};
1126
1127/* Structure to hold device level control filter counts */
1128struct i40e_control_filter_stats {
1129 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1130 u16 etype_used; /* Used perfect EtherType filters */
1131 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1132 u16 etype_free; /* Un-used perfect EtherType filters */
1133};
1134
1135enum i40e_reset_type {
1136 I40E_RESET_POR = 0,
1137 I40E_RESET_CORER = 1,
1138 I40E_RESET_GLOBR = 2,
1139 I40E_RESET_EMPR = 3,
1140};
1141
1142/* IEEE 802.1AB LLDP Agent Variables from NVM */
1143#define I40E_NVM_LLDP_CFG_PTR 0xF
1144struct i40e_lldp_variables {
1145 u16 length;
1146 u16 adminstatus;
1147 u16 msgfasttx;
1148 u16 msgtxinterval;
1149 u16 txparams;
1150 u16 timers;
1151 u16 crc8;
1152};
1153
1154#endif /* _I40E_TYPE_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 07:11:20 -0500