diff options
author | Emmanuel Grumbach <emmanuel.grumbach@intel.com> | 2012-12-24 07:27:11 -0500 |
---|---|---|
committer | Johannes Berg <johannes.berg@intel.com> | 2013-01-03 09:30:19 -0500 |
commit | 4fd442db98dadf33ecce6d489bbbc95f6e8d3b31 (patch) | |
tree | 9eff5b52f5533a4864050a2829b9e849879b990a /drivers/net | |
parent | 7a65d17053c758109477f420e813ba2d826b0eae (diff) |
iwlwifi: virtualize SRAM access
Different transports implement the access to the SRAM in
different ways. Virtualize it.
Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/wireless/iwlwifi/dvm/debugfs.c | 4 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/dvm/mac80211.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/dvm/main.c | 13 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-io.c | 56 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-io.h | 15 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-test.c | 7 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/iwl-trans.h | 43 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/pcie/trans.c | 41 | ||||
-rw-r--r-- | drivers/net/wireless/iwlwifi/pcie/tx.c | 26 |
9 files changed, 109 insertions, 98 deletions
diff --git a/drivers/net/wireless/iwlwifi/dvm/debugfs.c b/drivers/net/wireless/iwlwifi/dvm/debugfs.c index 5b9533eef54d..72c74af38138 100644 --- a/drivers/net/wireless/iwlwifi/dvm/debugfs.c +++ b/drivers/net/wireless/iwlwifi/dvm/debugfs.c | |||
@@ -157,7 +157,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file, | |||
157 | sram = priv->dbgfs_sram_offset & ~0x3; | 157 | sram = priv->dbgfs_sram_offset & ~0x3; |
158 | 158 | ||
159 | /* read the first u32 from sram */ | 159 | /* read the first u32 from sram */ |
160 | val = iwl_read_targ_mem(priv->trans, sram); | 160 | val = iwl_trans_read_mem32(priv->trans, sram); |
161 | 161 | ||
162 | for (; len; len--) { | 162 | for (; len; len--) { |
163 | /* put the address at the start of every line */ | 163 | /* put the address at the start of every line */ |
@@ -176,7 +176,7 @@ static ssize_t iwl_dbgfs_sram_read(struct file *file, | |||
176 | if (++offset == 4) { | 176 | if (++offset == 4) { |
177 | sram += 4; | 177 | sram += 4; |
178 | offset = 0; | 178 | offset = 0; |
179 | val = iwl_read_targ_mem(priv->trans, sram); | 179 | val = iwl_trans_read_mem32(priv->trans, sram); |
180 | } | 180 | } |
181 | 181 | ||
182 | /* put in extra spaces and split lines for human readability */ | 182 | /* put in extra spaces and split lines for human readability */ |
diff --git a/drivers/net/wireless/iwlwifi/dvm/mac80211.c b/drivers/net/wireless/iwlwifi/dvm/mac80211.c index 8965a9824f50..9c1f055f4316 100644 --- a/drivers/net/wireless/iwlwifi/dvm/mac80211.c +++ b/drivers/net/wireless/iwlwifi/dvm/mac80211.c | |||
@@ -479,7 +479,7 @@ static int iwlagn_mac_resume(struct ieee80211_hw *hw) | |||
479 | } | 479 | } |
480 | 480 | ||
481 | if (priv->wowlan_sram) | 481 | if (priv->wowlan_sram) |
482 | _iwl_read_targ_mem_dwords( | 482 | iwl_trans_read_mem( |
483 | priv->trans, 0x800000, | 483 | priv->trans, 0x800000, |
484 | priv->wowlan_sram, | 484 | priv->wowlan_sram, |
485 | img->sec[IWL_UCODE_SECTION_DATA].len / 4); | 485 | img->sec[IWL_UCODE_SECTION_DATA].len / 4); |
diff --git a/drivers/net/wireless/iwlwifi/dvm/main.c b/drivers/net/wireless/iwlwifi/dvm/main.c index c4caedd4fa9c..517d7ae549d3 100644 --- a/drivers/net/wireless/iwlwifi/dvm/main.c +++ b/drivers/net/wireless/iwlwifi/dvm/main.c | |||
@@ -408,7 +408,8 @@ static void iwl_continuous_event_trace(struct iwl_priv *priv) | |||
408 | 408 | ||
409 | base = priv->device_pointers.log_event_table; | 409 | base = priv->device_pointers.log_event_table; |
410 | if (iwlagn_hw_valid_rtc_data_addr(base)) { | 410 | if (iwlagn_hw_valid_rtc_data_addr(base)) { |
411 | iwl_read_targ_mem_bytes(priv->trans, base, &read, sizeof(read)); | 411 | iwl_trans_read_mem_bytes(priv->trans, base, |
412 | &read, sizeof(read)); | ||
412 | capacity = read.capacity; | 413 | capacity = read.capacity; |
413 | mode = read.mode; | 414 | mode = read.mode; |
414 | num_wraps = read.wrap_counter; | 415 | num_wraps = read.wrap_counter; |
@@ -1627,7 +1628,7 @@ static void iwl_dump_nic_error_log(struct iwl_priv *priv) | |||
1627 | } | 1628 | } |
1628 | 1629 | ||
1629 | /*TODO: Update dbgfs with ISR error stats obtained below */ | 1630 | /*TODO: Update dbgfs with ISR error stats obtained below */ |
1630 | iwl_read_targ_mem_bytes(trans, base, &table, sizeof(table)); | 1631 | iwl_trans_read_mem_bytes(trans, base, &table, sizeof(table)); |
1631 | 1632 | ||
1632 | if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { | 1633 | if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) { |
1633 | IWL_ERR(trans, "Start IWL Error Log Dump:\n"); | 1634 | IWL_ERR(trans, "Start IWL Error Log Dump:\n"); |
@@ -1835,10 +1836,10 @@ int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log, | |||
1835 | } | 1836 | } |
1836 | 1837 | ||
1837 | /* event log header */ | 1838 | /* event log header */ |
1838 | capacity = iwl_read_targ_mem(trans, base); | 1839 | capacity = iwl_trans_read_mem32(trans, base); |
1839 | mode = iwl_read_targ_mem(trans, base + (1 * sizeof(u32))); | 1840 | mode = iwl_trans_read_mem32(trans, base + (1 * sizeof(u32))); |
1840 | num_wraps = iwl_read_targ_mem(trans, base + (2 * sizeof(u32))); | 1841 | num_wraps = iwl_trans_read_mem32(trans, base + (2 * sizeof(u32))); |
1841 | next_entry = iwl_read_targ_mem(trans, base + (3 * sizeof(u32))); | 1842 | next_entry = iwl_trans_read_mem32(trans, base + (3 * sizeof(u32))); |
1842 | 1843 | ||
1843 | if (capacity > logsize) { | 1844 | if (capacity > logsize) { |
1844 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d " | 1845 | IWL_ERR(priv, "Log capacity %d is bogus, limit to %d " |
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.c b/drivers/net/wireless/iwlwifi/iwl-io.c index cb36fedd157a..2bd84adbb5ae 100644 --- a/drivers/net/wireless/iwlwifi/iwl-io.c +++ b/drivers/net/wireless/iwlwifi/iwl-io.c | |||
@@ -226,59 +226,3 @@ void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask) | |||
226 | spin_unlock_irqrestore(&trans->reg_lock, flags); | 226 | spin_unlock_irqrestore(&trans->reg_lock, flags); |
227 | } | 227 | } |
228 | EXPORT_SYMBOL_GPL(iwl_clear_bits_prph); | 228 | EXPORT_SYMBOL_GPL(iwl_clear_bits_prph); |
229 | |||
230 | void _iwl_read_targ_mem_dwords(struct iwl_trans *trans, u32 addr, | ||
231 | void *buf, int dwords) | ||
232 | { | ||
233 | unsigned long flags; | ||
234 | int offs; | ||
235 | u32 *vals = buf; | ||
236 | |||
237 | spin_lock_irqsave(&trans->reg_lock, flags); | ||
238 | if (likely(iwl_trans_grab_nic_access(trans, false))) { | ||
239 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); | ||
240 | for (offs = 0; offs < dwords; offs++) | ||
241 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | ||
242 | iwl_trans_release_nic_access(trans); | ||
243 | } | ||
244 | spin_unlock_irqrestore(&trans->reg_lock, flags); | ||
245 | } | ||
246 | EXPORT_SYMBOL_GPL(_iwl_read_targ_mem_dwords); | ||
247 | |||
248 | u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr) | ||
249 | { | ||
250 | u32 value; | ||
251 | |||
252 | _iwl_read_targ_mem_dwords(trans, addr, &value, 1); | ||
253 | |||
254 | return value; | ||
255 | } | ||
256 | EXPORT_SYMBOL_GPL(iwl_read_targ_mem); | ||
257 | |||
258 | int _iwl_write_targ_mem_dwords(struct iwl_trans *trans, u32 addr, | ||
259 | const void *buf, int dwords) | ||
260 | { | ||
261 | unsigned long flags; | ||
262 | int offs, result = 0; | ||
263 | const u32 *vals = buf; | ||
264 | |||
265 | spin_lock_irqsave(&trans->reg_lock, flags); | ||
266 | if (likely(iwl_trans_grab_nic_access(trans, false))) { | ||
267 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); | ||
268 | for (offs = 0; offs < dwords; offs++) | ||
269 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]); | ||
270 | iwl_trans_release_nic_access(trans); | ||
271 | } else { | ||
272 | result = -EBUSY; | ||
273 | } | ||
274 | spin_unlock_irqrestore(&trans->reg_lock, flags); | ||
275 | |||
276 | return result; | ||
277 | } | ||
278 | EXPORT_SYMBOL_GPL(_iwl_write_targ_mem_dwords); | ||
279 | |||
280 | int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val) | ||
281 | { | ||
282 | return _iwl_write_targ_mem_dwords(trans, addr, &val, 1); | ||
283 | } | ||
284 | EXPORT_SYMBOL_GPL(iwl_write_targ_mem); | ||
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.h b/drivers/net/wireless/iwlwifi/iwl-io.h index 40eb0a1709b1..dc478068596b 100644 --- a/drivers/net/wireless/iwlwifi/iwl-io.h +++ b/drivers/net/wireless/iwlwifi/iwl-io.h | |||
@@ -74,19 +74,4 @@ void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 ofs, | |||
74 | u32 bits, u32 mask); | 74 | u32 bits, u32 mask); |
75 | void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask); | 75 | void iwl_clear_bits_prph(struct iwl_trans *trans, u32 ofs, u32 mask); |
76 | 76 | ||
77 | void _iwl_read_targ_mem_dwords(struct iwl_trans *trans, u32 addr, | ||
78 | void *buf, int dwords); | ||
79 | |||
80 | #define iwl_read_targ_mem_bytes(trans, addr, buf, bufsize) \ | ||
81 | do { \ | ||
82 | BUILD_BUG_ON((bufsize) % sizeof(u32)); \ | ||
83 | _iwl_read_targ_mem_dwords(trans, addr, buf, \ | ||
84 | (bufsize) / sizeof(u32));\ | ||
85 | } while (0) | ||
86 | |||
87 | int _iwl_write_targ_mem_dwords(struct iwl_trans *trans, u32 addr, | ||
88 | const void *buf, int dwords); | ||
89 | |||
90 | u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr); | ||
91 | int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val); | ||
92 | #endif | 77 | #endif |
diff --git a/drivers/net/wireless/iwlwifi/iwl-test.c b/drivers/net/wireless/iwlwifi/iwl-test.c index 08c1cfec8590..f8d8df8f96c3 100644 --- a/drivers/net/wireless/iwlwifi/iwl-test.c +++ b/drivers/net/wireless/iwlwifi/iwl-test.c | |||
@@ -476,9 +476,8 @@ static int iwl_test_indirect_read(struct iwl_test *tst, u32 addr, u32 size) | |||
476 | iwl_trans_release_nic_access(trans); | 476 | iwl_trans_release_nic_access(trans); |
477 | spin_unlock_irqrestore(&trans->reg_lock, flags); | 477 | spin_unlock_irqrestore(&trans->reg_lock, flags); |
478 | } else { /* target memory (SRAM) */ | 478 | } else { /* target memory (SRAM) */ |
479 | _iwl_read_targ_mem_dwords(trans, addr, | 479 | iwl_trans_read_mem(trans, addr, tst->mem.addr, |
480 | tst->mem.addr, | 480 | tst->mem.size / 4); |
481 | tst->mem.size / 4); | ||
482 | } | 481 | } |
483 | 482 | ||
484 | tst->mem.nchunks = | 483 | tst->mem.nchunks = |
@@ -522,7 +521,7 @@ static int iwl_test_indirect_write(struct iwl_test *tst, u32 addr, | |||
522 | *(u32 *)(buf+i)); | 521 | *(u32 *)(buf+i)); |
523 | } | 522 | } |
524 | } else if (iwl_test_valid_hw_addr(tst, addr)) { | 523 | } else if (iwl_test_valid_hw_addr(tst, addr)) { |
525 | _iwl_write_targ_mem_dwords(trans, addr, buf, size / 4); | 524 | iwl_trans_write_mem(trans, addr, buf, size / 4); |
526 | } else { | 525 | } else { |
527 | return -EINVAL; | 526 | return -EINVAL; |
528 | } | 527 | } |
diff --git a/drivers/net/wireless/iwlwifi/iwl-trans.h b/drivers/net/wireless/iwlwifi/iwl-trans.h index 1d1f5d0e5726..7584d5522f15 100644 --- a/drivers/net/wireless/iwlwifi/iwl-trans.h +++ b/drivers/net/wireless/iwlwifi/iwl-trans.h | |||
@@ -390,6 +390,8 @@ struct iwl_trans; | |||
390 | * @read32: read a u32 register at offset ofs from the BAR | 390 | * @read32: read a u32 register at offset ofs from the BAR |
391 | * @read_prph: read a DWORD from a periphery register | 391 | * @read_prph: read a DWORD from a periphery register |
392 | * @write_prph: write a DWORD to a periphery register | 392 | * @write_prph: write a DWORD to a periphery register |
393 | * @read_mem: read device's SRAM in DWORD | ||
394 | * @write_mem: write device's SRAM in DWORD | ||
393 | * @configure: configure parameters required by the transport layer from | 395 | * @configure: configure parameters required by the transport layer from |
394 | * the op_mode. May be called several times before start_fw, can't be | 396 | * the op_mode. May be called several times before start_fw, can't be |
395 | * called after that. | 397 | * called after that. |
@@ -430,6 +432,10 @@ struct iwl_trans_ops { | |||
430 | u32 (*read32)(struct iwl_trans *trans, u32 ofs); | 432 | u32 (*read32)(struct iwl_trans *trans, u32 ofs); |
431 | u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); | 433 | u32 (*read_prph)(struct iwl_trans *trans, u32 ofs); |
432 | void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); | 434 | void (*write_prph)(struct iwl_trans *trans, u32 ofs, u32 val); |
435 | int (*read_mem)(struct iwl_trans *trans, u32 addr, | ||
436 | void *buf, int dwords); | ||
437 | int (*write_mem)(struct iwl_trans *trans, u32 addr, | ||
438 | void *buf, int dwords); | ||
433 | void (*configure)(struct iwl_trans *trans, | 439 | void (*configure)(struct iwl_trans *trans, |
434 | const struct iwl_trans_config *trans_cfg); | 440 | const struct iwl_trans_config *trans_cfg); |
435 | void (*set_pmi)(struct iwl_trans *trans, bool state); | 441 | void (*set_pmi)(struct iwl_trans *trans, bool state); |
@@ -645,7 +651,7 @@ static inline int iwl_trans_wait_tx_queue_empty(struct iwl_trans *trans) | |||
645 | } | 651 | } |
646 | 652 | ||
647 | static inline int iwl_trans_dbgfs_register(struct iwl_trans *trans, | 653 | static inline int iwl_trans_dbgfs_register(struct iwl_trans *trans, |
648 | struct dentry *dir) | 654 | struct dentry *dir) |
649 | { | 655 | { |
650 | return trans->ops->dbgfs_register(trans, dir); | 656 | return trans->ops->dbgfs_register(trans, dir); |
651 | } | 657 | } |
@@ -688,6 +694,41 @@ static inline void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, | |||
688 | return trans->ops->write_prph(trans, ofs, val); | 694 | return trans->ops->write_prph(trans, ofs, val); |
689 | } | 695 | } |
690 | 696 | ||
697 | static inline int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, | ||
698 | void *buf, int dwords) | ||
699 | { | ||
700 | return trans->ops->read_mem(trans, addr, buf, dwords); | ||
701 | } | ||
702 | |||
703 | #define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ | ||
704 | do { \ | ||
705 | if (__builtin_constant_p(bufsize)) \ | ||
706 | BUILD_BUG_ON((bufsize) % sizeof(u32)); \ | ||
707 | iwl_trans_read_mem(trans, addr, buf, (bufsize) / sizeof(u32));\ | ||
708 | } while (0) | ||
709 | |||
710 | static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) | ||
711 | { | ||
712 | u32 value; | ||
713 | |||
714 | if (WARN_ON(iwl_trans_read_mem(trans, addr, &value, 1))) | ||
715 | return 0xa5a5a5a5; | ||
716 | |||
717 | return value; | ||
718 | } | ||
719 | |||
720 | static inline int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, | ||
721 | void *buf, int dwords) | ||
722 | { | ||
723 | return trans->ops->write_mem(trans, addr, buf, dwords); | ||
724 | } | ||
725 | |||
726 | static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, | ||
727 | u32 val) | ||
728 | { | ||
729 | return iwl_trans_write_mem(trans, addr, &val, 1); | ||
730 | } | ||
731 | |||
691 | static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) | 732 | static inline void iwl_trans_set_pmi(struct iwl_trans *trans, bool state) |
692 | { | 733 | { |
693 | trans->ops->set_pmi(trans, state); | 734 | trans->ops->set_pmi(trans, state); |
diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c index 80b05d821688..3a40607ed542 100644 --- a/drivers/net/wireless/iwlwifi/pcie/trans.c +++ b/drivers/net/wireless/iwlwifi/pcie/trans.c | |||
@@ -820,6 +820,45 @@ static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) | |||
820 | mmiowb(); | 820 | mmiowb(); |
821 | } | 821 | } |
822 | 822 | ||
823 | static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, | ||
824 | void *buf, int dwords) | ||
825 | { | ||
826 | unsigned long flags; | ||
827 | int offs, ret = 0; | ||
828 | u32 *vals = buf; | ||
829 | |||
830 | spin_lock_irqsave(&trans->reg_lock, flags); | ||
831 | if (likely(iwl_trans_grab_nic_access(trans, false))) { | ||
832 | iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr); | ||
833 | for (offs = 0; offs < dwords; offs++) | ||
834 | vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT); | ||
835 | iwl_trans_release_nic_access(trans); | ||
836 | } else { | ||
837 | ret = -EBUSY; | ||
838 | } | ||
839 | spin_unlock_irqrestore(&trans->reg_lock, flags); | ||
840 | return ret; | ||
841 | } | ||
842 | |||
843 | static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, | ||
844 | void *buf, int dwords) | ||
845 | { | ||
846 | unsigned long flags; | ||
847 | int offs, ret = 0; | ||
848 | u32 *vals = buf; | ||
849 | |||
850 | spin_lock_irqsave(&trans->reg_lock, flags); | ||
851 | if (likely(iwl_trans_grab_nic_access(trans, false))) { | ||
852 | iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr); | ||
853 | for (offs = 0; offs < dwords; offs++) | ||
854 | iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]); | ||
855 | iwl_trans_release_nic_access(trans); | ||
856 | } else { | ||
857 | ret = -EBUSY; | ||
858 | } | ||
859 | spin_unlock_irqrestore(&trans->reg_lock, flags); | ||
860 | return ret; | ||
861 | } | ||
823 | 862 | ||
824 | #define IWL_FLUSH_WAIT_MS 2000 | 863 | #define IWL_FLUSH_WAIT_MS 2000 |
825 | 864 | ||
@@ -1298,6 +1337,8 @@ static const struct iwl_trans_ops trans_ops_pcie = { | |||
1298 | .read32 = iwl_trans_pcie_read32, | 1337 | .read32 = iwl_trans_pcie_read32, |
1299 | .read_prph = iwl_trans_pcie_read_prph, | 1338 | .read_prph = iwl_trans_pcie_read_prph, |
1300 | .write_prph = iwl_trans_pcie_write_prph, | 1339 | .write_prph = iwl_trans_pcie_write_prph, |
1340 | .read_mem = iwl_trans_pcie_read_mem, | ||
1341 | .write_mem = iwl_trans_pcie_write_mem, | ||
1301 | .configure = iwl_trans_pcie_configure, | 1342 | .configure = iwl_trans_pcie_configure, |
1302 | .set_pmi = iwl_trans_pcie_set_pmi, | 1343 | .set_pmi = iwl_trans_pcie_set_pmi, |
1303 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, | 1344 | .grab_nic_access = iwl_trans_pcie_grab_nic_access, |
diff --git a/drivers/net/wireless/iwlwifi/pcie/tx.c b/drivers/net/wireless/iwlwifi/pcie/tx.c index 7af8f0b55d2d..d25fc8aaccc6 100644 --- a/drivers/net/wireless/iwlwifi/pcie/tx.c +++ b/drivers/net/wireless/iwlwifi/pcie/tx.c | |||
@@ -160,7 +160,7 @@ static void iwl_pcie_txq_stuck_timer(unsigned long data) | |||
160 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", | 160 | IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", |
161 | txq->q.read_ptr, txq->q.write_ptr); | 161 | txq->q.read_ptr, txq->q.write_ptr); |
162 | 162 | ||
163 | iwl_read_targ_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); | 163 | iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); |
164 | 164 | ||
165 | iwl_print_hex_error(trans, buf, sizeof(buf)); | 165 | iwl_print_hex_error(trans, buf, sizeof(buf)); |
166 | 166 | ||
@@ -173,9 +173,9 @@ static void iwl_pcie_txq_stuck_timer(unsigned long data) | |||
173 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; | 173 | u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; |
174 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); | 174 | bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); |
175 | u32 tbl_dw = | 175 | u32 tbl_dw = |
176 | iwl_read_targ_mem(trans, | 176 | iwl_trans_read_mem32(trans, |
177 | trans_pcie->scd_base_addr + | 177 | trans_pcie->scd_base_addr + |
178 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); | 178 | SCD_TRANS_TBL_OFFSET_QUEUE(i)); |
179 | 179 | ||
180 | if (i & 0x1) | 180 | if (i & 0x1) |
181 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; | 181 | tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; |
@@ -659,16 +659,16 @@ void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr) | |||
659 | /* reset conext data memory */ | 659 | /* reset conext data memory */ |
660 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; | 660 | for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND; |
661 | a += 4) | 661 | a += 4) |
662 | iwl_write_targ_mem(trans, a, 0); | 662 | iwl_trans_write_mem32(trans, a, 0); |
663 | /* reset tx status memory */ | 663 | /* reset tx status memory */ |
664 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; | 664 | for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND; |
665 | a += 4) | 665 | a += 4) |
666 | iwl_write_targ_mem(trans, a, 0); | 666 | iwl_trans_write_mem32(trans, a, 0); |
667 | for (; a < trans_pcie->scd_base_addr + | 667 | for (; a < trans_pcie->scd_base_addr + |
668 | SCD_TRANS_TBL_OFFSET_QUEUE( | 668 | SCD_TRANS_TBL_OFFSET_QUEUE( |
669 | trans->cfg->base_params->num_of_queues); | 669 | trans->cfg->base_params->num_of_queues); |
670 | a += 4) | 670 | a += 4) |
671 | iwl_write_targ_mem(trans, a, 0); | 671 | iwl_trans_write_mem32(trans, a, 0); |
672 | 672 | ||
673 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, | 673 | iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, |
674 | trans_pcie->scd_bc_tbls.dma >> 10); | 674 | trans_pcie->scd_bc_tbls.dma >> 10); |
@@ -1005,14 +1005,14 @@ static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid, | |||
1005 | tbl_dw_addr = trans_pcie->scd_base_addr + | 1005 | tbl_dw_addr = trans_pcie->scd_base_addr + |
1006 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); | 1006 | SCD_TRANS_TBL_OFFSET_QUEUE(txq_id); |
1007 | 1007 | ||
1008 | tbl_dw = iwl_read_targ_mem(trans, tbl_dw_addr); | 1008 | tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr); |
1009 | 1009 | ||
1010 | if (txq_id & 0x1) | 1010 | if (txq_id & 0x1) |
1011 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); | 1011 | tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); |
1012 | else | 1012 | else |
1013 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); | 1013 | tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); |
1014 | 1014 | ||
1015 | iwl_write_targ_mem(trans, tbl_dw_addr, tbl_dw); | 1015 | iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw); |
1016 | 1016 | ||
1017 | return 0; | 1017 | return 0; |
1018 | } | 1018 | } |
@@ -1071,9 +1071,9 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo, | |||
1071 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); | 1071 | iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn); |
1072 | 1072 | ||
1073 | /* Set up Tx window size and frame limit for this queue */ | 1073 | /* Set up Tx window size and frame limit for this queue */ |
1074 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + | 1074 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
1075 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); | 1075 | SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0); |
1076 | iwl_write_targ_mem(trans, trans_pcie->scd_base_addr + | 1076 | iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr + |
1077 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), | 1077 | SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), |
1078 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & | 1078 | ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) & |
1079 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | | 1079 | SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) | |
@@ -1104,8 +1104,8 @@ void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id) | |||
1104 | 1104 | ||
1105 | iwl_pcie_txq_set_inactive(trans, txq_id); | 1105 | iwl_pcie_txq_set_inactive(trans, txq_id); |
1106 | 1106 | ||
1107 | _iwl_write_targ_mem_dwords(trans, stts_addr, | 1107 | iwl_trans_write_mem(trans, stts_addr, (void *)zero_val, |
1108 | zero_val, ARRAY_SIZE(zero_val)); | 1108 | ARRAY_SIZE(zero_val)); |
1109 | 1109 | ||
1110 | iwl_pcie_txq_unmap(trans, txq_id); | 1110 | iwl_pcie_txq_unmap(trans, txq_id); |
1111 | 1111 | ||