diff options
author | Emil Tantilov <emil.s.tantilov@intel.com> | 2013-10-22 04:21:04 -0400 |
---|---|---|
committer | Jeff Kirsher <jeffrey.t.kirsher@intel.com> | 2013-10-24 10:03:12 -0400 |
commit | 2e0103810c6fed6a736c4a3af87b0f5c6bd8cd5b (patch) | |
tree | d5d115b623ee5739a83e2aaabfc4a6c3b5af3edb /drivers/net | |
parent | c0798edfb32497a886308a2614fd0a4e6da499c0 (diff) |
ixgbe: fix rx-usecs range checks for BQL
This patch resolves an issue where the logic used to detect changes in rx-usecs
was incorrect and was masked by the call to ixgbe_update_rsc().
Setting rx-usecs between 0,2-9 and 1,10 and up requires a reset to allow
ixgbe_configure_tx_ring() to set the correct value for TXDCTL.WTHRESH in
order to avoid Tx hangs with BQL enabled.
Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Diffstat (limited to 'drivers/net')
-rw-r--r-- | drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c index 90aac31b3551..4e7c9b098b58 100644 --- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c | |||
@@ -2257,13 +2257,13 @@ static int ixgbe_set_coalesce(struct net_device *netdev, | |||
2257 | 2257 | ||
2258 | #if IS_ENABLED(CONFIG_BQL) | 2258 | #if IS_ENABLED(CONFIG_BQL) |
2259 | /* detect ITR changes that require update of TXDCTL.WTHRESH */ | 2259 | /* detect ITR changes that require update of TXDCTL.WTHRESH */ |
2260 | if ((adapter->tx_itr_setting > 1) && | 2260 | if ((adapter->tx_itr_setting != 1) && |
2261 | (adapter->tx_itr_setting < IXGBE_100K_ITR)) { | 2261 | (adapter->tx_itr_setting < IXGBE_100K_ITR)) { |
2262 | if ((tx_itr_prev == 1) || | 2262 | if ((tx_itr_prev == 1) || |
2263 | (tx_itr_prev > IXGBE_100K_ITR)) | 2263 | (tx_itr_prev >= IXGBE_100K_ITR)) |
2264 | need_reset = true; | 2264 | need_reset = true; |
2265 | } else { | 2265 | } else { |
2266 | if ((tx_itr_prev > 1) && | 2266 | if ((tx_itr_prev != 1) && |
2267 | (tx_itr_prev < IXGBE_100K_ITR)) | 2267 | (tx_itr_prev < IXGBE_100K_ITR)) |
2268 | need_reset = true; | 2268 | need_reset = true; |
2269 | } | 2269 | } |