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authorMichael Chan <mchan@broadcom.com>2007-05-03 16:23:41 -0400
committerDavid S. Miller <davem@davemloft.net>2007-05-03 16:23:41 -0400
commit27a005b883984ef3a3cf24e7ddd78eb78902f494 (patch)
treec2fbdb130239e7f7ad718cea0cd8cb1a78528da4 /drivers/net
parent605a9e20aaea23f31a5403e969bd4ab4d0405dab (diff)
[BNX2]: Add support for 5709 Serdes.
Add PCI ID and code to support the 5709 Serdes PHY. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/bnx2.c203
-rw-r--r--drivers/net/bnx2.h36
2 files changed, 227 insertions, 12 deletions
diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 944f547a7406..ab589090d634 100644
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -84,6 +84,7 @@ typedef enum {
84 BCM5708, 84 BCM5708,
85 BCM5708S, 85 BCM5708S,
86 BCM5709, 86 BCM5709,
87 BCM5709S,
87} board_t; 88} board_t;
88 89
89/* indexed by board_t, above */ 90/* indexed by board_t, above */
@@ -98,6 +99,7 @@ static const struct {
98 { "Broadcom NetXtreme II BCM5708 1000Base-T" }, 99 { "Broadcom NetXtreme II BCM5708 1000Base-T" },
99 { "Broadcom NetXtreme II BCM5708 1000Base-SX" }, 100 { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
100 { "Broadcom NetXtreme II BCM5709 1000Base-T" }, 101 { "Broadcom NetXtreme II BCM5709 1000Base-T" },
102 { "Broadcom NetXtreme II BCM5709 1000Base-SX" },
101 }; 103 };
102 104
103static struct pci_device_id bnx2_pci_tbl[] = { 105static struct pci_device_id bnx2_pci_tbl[] = {
@@ -117,6 +119,8 @@ static struct pci_device_id bnx2_pci_tbl[] = {
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S }, 119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
118 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709, 120 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 }, 121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
122 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709S,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709S },
120 { 0, } 124 { 0, }
121}; 125};
122 126
@@ -700,6 +704,45 @@ bnx2_resolve_flow_ctrl(struct bnx2 *bp)
700} 704}
701 705
702static int 706static int
707bnx2_5709s_linkup(struct bnx2 *bp)
708{
709 u32 val, speed;
710
711 bp->link_up = 1;
712
713 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_GP_STATUS);
714 bnx2_read_phy(bp, MII_BNX2_GP_TOP_AN_STATUS1, &val);
715 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
716
717 if ((bp->autoneg & AUTONEG_SPEED) == 0) {
718 bp->line_speed = bp->req_line_speed;
719 bp->duplex = bp->req_duplex;
720 return 0;
721 }
722 speed = val & MII_BNX2_GP_TOP_AN_SPEED_MSK;
723 switch (speed) {
724 case MII_BNX2_GP_TOP_AN_SPEED_10:
725 bp->line_speed = SPEED_10;
726 break;
727 case MII_BNX2_GP_TOP_AN_SPEED_100:
728 bp->line_speed = SPEED_100;
729 break;
730 case MII_BNX2_GP_TOP_AN_SPEED_1G:
731 case MII_BNX2_GP_TOP_AN_SPEED_1GKV:
732 bp->line_speed = SPEED_1000;
733 break;
734 case MII_BNX2_GP_TOP_AN_SPEED_2_5G:
735 bp->line_speed = SPEED_2500;
736 break;
737 }
738 if (val & MII_BNX2_GP_TOP_AN_FD)
739 bp->duplex = DUPLEX_FULL;
740 else
741 bp->duplex = DUPLEX_HALF;
742 return 0;
743}
744
745static int
703bnx2_5708s_linkup(struct bnx2 *bp) 746bnx2_5708s_linkup(struct bnx2 *bp)
704{ 747{
705 u32 val; 748 u32 val;
@@ -898,6 +941,24 @@ bnx2_set_mac_link(struct bnx2 *bp)
898 return 0; 941 return 0;
899} 942}
900 943
944static void
945bnx2_enable_bmsr1(struct bnx2 *bp)
946{
947 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
948 (CHIP_NUM(bp) == CHIP_NUM_5709))
949 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
950 MII_BNX2_BLK_ADDR_GP_STATUS);
951}
952
953static void
954bnx2_disable_bmsr1(struct bnx2 *bp)
955{
956 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
957 (CHIP_NUM(bp) == CHIP_NUM_5709))
958 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
959 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
960}
961
901static int 962static int
902bnx2_test_and_enable_2g5(struct bnx2 *bp) 963bnx2_test_and_enable_2g5(struct bnx2 *bp)
903{ 964{
@@ -910,6 +971,9 @@ bnx2_test_and_enable_2g5(struct bnx2 *bp)
910 if (bp->autoneg & AUTONEG_SPEED) 971 if (bp->autoneg & AUTONEG_SPEED)
911 bp->advertising |= ADVERTISED_2500baseX_Full; 972 bp->advertising |= ADVERTISED_2500baseX_Full;
912 973
974 if (CHIP_NUM(bp) == CHIP_NUM_5709)
975 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
976
913 bnx2_read_phy(bp, bp->mii_up1, &up1); 977 bnx2_read_phy(bp, bp->mii_up1, &up1);
914 if (!(up1 & BCM5708S_UP1_2G5)) { 978 if (!(up1 & BCM5708S_UP1_2G5)) {
915 up1 |= BCM5708S_UP1_2G5; 979 up1 |= BCM5708S_UP1_2G5;
@@ -917,6 +981,10 @@ bnx2_test_and_enable_2g5(struct bnx2 *bp)
917 ret = 0; 981 ret = 0;
918 } 982 }
919 983
984 if (CHIP_NUM(bp) == CHIP_NUM_5709)
985 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
986 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
987
920 return ret; 988 return ret;
921} 989}
922 990
@@ -929,6 +997,9 @@ bnx2_test_and_disable_2g5(struct bnx2 *bp)
929 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) 997 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
930 return 0; 998 return 0;
931 999
1000 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1001 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1002
932 bnx2_read_phy(bp, bp->mii_up1, &up1); 1003 bnx2_read_phy(bp, bp->mii_up1, &up1);
933 if (up1 & BCM5708S_UP1_2G5) { 1004 if (up1 & BCM5708S_UP1_2G5) {
934 up1 &= ~BCM5708S_UP1_2G5; 1005 up1 &= ~BCM5708S_UP1_2G5;
@@ -936,6 +1007,10 @@ bnx2_test_and_disable_2g5(struct bnx2 *bp)
936 ret = 1; 1007 ret = 1;
937 } 1008 }
938 1009
1010 if (CHIP_NUM(bp) == CHIP_NUM_5709)
1011 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1012 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1013
939 return ret; 1014 return ret;
940} 1015}
941 1016
@@ -947,7 +1022,21 @@ bnx2_enable_forced_2g5(struct bnx2 *bp)
947 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) 1022 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
948 return; 1023 return;
949 1024
950 if (CHIP_NUM(bp) == CHIP_NUM_5708) { 1025 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1026 u32 val;
1027
1028 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1029 MII_BNX2_BLK_ADDR_SERDES_DIG);
1030 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1031 val &= ~MII_BNX2_SD_MISC1_FORCE_MSK;
1032 val |= MII_BNX2_SD_MISC1_FORCE | MII_BNX2_SD_MISC1_FORCE_2_5G;
1033 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1034
1035 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1036 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1037 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1038
1039 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
951 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1040 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
952 bmcr |= BCM5708S_BMCR_FORCE_2500; 1041 bmcr |= BCM5708S_BMCR_FORCE_2500;
953 } 1042 }
@@ -968,7 +1057,20 @@ bnx2_disable_forced_2g5(struct bnx2 *bp)
968 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)) 1057 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
969 return; 1058 return;
970 1059
971 if (CHIP_NUM(bp) == CHIP_NUM_5708) { 1060 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1061 u32 val;
1062
1063 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1064 MII_BNX2_BLK_ADDR_SERDES_DIG);
1065 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_MISC1, &val);
1066 val &= ~MII_BNX2_SD_MISC1_FORCE;
1067 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_MISC1, val);
1068
1069 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR,
1070 MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1071 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
1072
1073 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
972 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr); 1074 bnx2_read_phy(bp, bp->mii_bmcr, &bmcr);
973 bmcr &= ~BCM5708S_BMCR_FORCE_2500; 1075 bmcr &= ~BCM5708S_BMCR_FORCE_2500;
974 } 1076 }
@@ -991,8 +1093,10 @@ bnx2_set_link(struct bnx2 *bp)
991 1093
992 link_up = bp->link_up; 1094 link_up = bp->link_up;
993 1095
994 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 1096 bnx2_enable_bmsr1(bp);
995 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 1097 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1098 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
1099 bnx2_disable_bmsr1(bp);
996 1100
997 if ((bp->phy_flags & PHY_SERDES_FLAG) && 1101 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
998 (CHIP_NUM(bp) == CHIP_NUM_5706)) { 1102 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
@@ -1013,6 +1117,8 @@ bnx2_set_link(struct bnx2 *bp)
1013 bnx2_5706s_linkup(bp); 1117 bnx2_5706s_linkup(bp);
1014 else if (CHIP_NUM(bp) == CHIP_NUM_5708) 1118 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1015 bnx2_5708s_linkup(bp); 1119 bnx2_5708s_linkup(bp);
1120 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1121 bnx2_5709s_linkup(bp);
1016 } 1122 }
1017 else { 1123 else {
1018 bnx2_copper_linkup(bp); 1124 bnx2_copper_linkup(bp);
@@ -1119,7 +1225,15 @@ bnx2_setup_serdes_phy(struct bnx2 *bp)
1119 new_bmcr = bmcr & ~BMCR_ANENABLE; 1225 new_bmcr = bmcr & ~BMCR_ANENABLE;
1120 new_bmcr |= BMCR_SPEED1000; 1226 new_bmcr |= BMCR_SPEED1000;
1121 1227
1122 if (CHIP_NUM(bp) == CHIP_NUM_5708) { 1228 if (CHIP_NUM(bp) == CHIP_NUM_5709) {
1229 if (bp->req_line_speed == SPEED_2500)
1230 bnx2_enable_forced_2g5(bp);
1231 else if (bp->req_line_speed == SPEED_1000) {
1232 bnx2_disable_forced_2g5(bp);
1233 new_bmcr &= ~0x2000;
1234 }
1235
1236 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1123 if (bp->req_line_speed == SPEED_2500) 1237 if (bp->req_line_speed == SPEED_2500)
1124 new_bmcr |= BCM5708S_BMCR_FORCE_2500; 1238 new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1125 else 1239 else
@@ -1302,6 +1416,9 @@ bnx2_setup_copper_phy(struct bnx2 *bp)
1302 bnx2_resolve_flow_ctrl(bp); 1416 bnx2_resolve_flow_ctrl(bp);
1303 bnx2_set_mac_link(bp); 1417 bnx2_set_mac_link(bp);
1304 } 1418 }
1419 } else {
1420 bnx2_resolve_flow_ctrl(bp);
1421 bnx2_set_mac_link(bp);
1305 } 1422 }
1306 return 0; 1423 return 0;
1307} 1424}
@@ -1321,10 +1438,63 @@ bnx2_setup_phy(struct bnx2 *bp)
1321} 1438}
1322 1439
1323static int 1440static int
1441bnx2_init_5709s_phy(struct bnx2 *bp)
1442{
1443 u32 val;
1444
1445 bp->mii_bmcr = MII_BMCR + 0x10;
1446 bp->mii_bmsr = MII_BMSR + 0x10;
1447 bp->mii_bmsr1 = MII_BNX2_GP_TOP_AN_STATUS1;
1448 bp->mii_adv = MII_ADVERTISE + 0x10;
1449 bp->mii_lpa = MII_LPA + 0x10;
1450 bp->mii_up1 = MII_BNX2_OVER1G_UP1;
1451
1452 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_AER);
1453 bnx2_write_phy(bp, MII_BNX2_AER_AER, MII_BNX2_AER_AER_AN_MMD);
1454
1455 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1456 bnx2_reset_phy(bp);
1457
1458 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_SERDES_DIG);
1459
1460 bnx2_read_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, &val);
1461 val &= ~MII_BNX2_SD_1000XCTL1_AUTODET;
1462 val |= MII_BNX2_SD_1000XCTL1_FIBER;
1463 bnx2_write_phy(bp, MII_BNX2_SERDES_DIG_1000XCTL1, val);
1464
1465 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_OVER1G);
1466 bnx2_read_phy(bp, MII_BNX2_OVER1G_UP1, &val);
1467 if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG)
1468 val |= BCM5708S_UP1_2G5;
1469 else
1470 val &= ~BCM5708S_UP1_2G5;
1471 bnx2_write_phy(bp, MII_BNX2_OVER1G_UP1, val);
1472
1473 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_BAM_NXTPG);
1474 bnx2_read_phy(bp, MII_BNX2_BAM_NXTPG_CTL, &val);
1475 val |= MII_BNX2_NXTPG_CTL_T2 | MII_BNX2_NXTPG_CTL_BAM;
1476 bnx2_write_phy(bp, MII_BNX2_BAM_NXTPG_CTL, val);
1477
1478 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_CL73_USERB0);
1479
1480 val = MII_BNX2_CL73_BAM_EN | MII_BNX2_CL73_BAM_STA_MGR_EN |
1481 MII_BNX2_CL73_BAM_NP_AFT_BP_EN;
1482 bnx2_write_phy(bp, MII_BNX2_CL73_BAM_CTL1, val);
1483
1484 bnx2_write_phy(bp, MII_BNX2_BLK_ADDR, MII_BNX2_BLK_ADDR_COMBO_IEEEB0);
1485
1486 return 0;
1487}
1488
1489static int
1324bnx2_init_5708s_phy(struct bnx2 *bp) 1490bnx2_init_5708s_phy(struct bnx2 *bp)
1325{ 1491{
1326 u32 val; 1492 u32 val;
1327 1493
1494 bnx2_reset_phy(bp);
1495
1496 bp->mii_up1 = BCM5708S_UP1;
1497
1328 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3); 1498 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1329 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE); 1499 bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1330 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG); 1500 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
@@ -1377,6 +1547,8 @@ bnx2_init_5708s_phy(struct bnx2 *bp)
1377static int 1547static int
1378bnx2_init_5706s_phy(struct bnx2 *bp) 1548bnx2_init_5706s_phy(struct bnx2 *bp)
1379{ 1549{
1550 bnx2_reset_phy(bp);
1551
1380 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG; 1552 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1381 1553
1382 if (CHIP_NUM(bp) == CHIP_NUM_5706) 1554 if (CHIP_NUM(bp) == CHIP_NUM_5706)
@@ -1414,6 +1586,8 @@ bnx2_init_copper_phy(struct bnx2 *bp)
1414{ 1586{
1415 u32 val; 1587 u32 val;
1416 1588
1589 bnx2_reset_phy(bp);
1590
1417 if (bp->phy_flags & PHY_CRC_FIX_FLAG) { 1591 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1418 bnx2_write_phy(bp, 0x18, 0x0c00); 1592 bnx2_write_phy(bp, 0x18, 0x0c00);
1419 bnx2_write_phy(bp, 0x17, 0x000a); 1593 bnx2_write_phy(bp, 0x17, 0x000a);
@@ -1470,13 +1644,12 @@ bnx2_init_phy(struct bnx2 *bp)
1470 1644
1471 bp->mii_bmcr = MII_BMCR; 1645 bp->mii_bmcr = MII_BMCR;
1472 bp->mii_bmsr = MII_BMSR; 1646 bp->mii_bmsr = MII_BMSR;
1647 bp->mii_bmsr1 = MII_BMSR;
1473 bp->mii_adv = MII_ADVERTISE; 1648 bp->mii_adv = MII_ADVERTISE;
1474 bp->mii_lpa = MII_LPA; 1649 bp->mii_lpa = MII_LPA;
1475 1650
1476 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK); 1651 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1477 1652
1478 bnx2_reset_phy(bp);
1479
1480 bnx2_read_phy(bp, MII_PHYSID1, &val); 1653 bnx2_read_phy(bp, MII_PHYSID1, &val);
1481 bp->phy_id = val << 16; 1654 bp->phy_id = val << 16;
1482 bnx2_read_phy(bp, MII_PHYSID2, &val); 1655 bnx2_read_phy(bp, MII_PHYSID2, &val);
@@ -1487,6 +1660,8 @@ bnx2_init_phy(struct bnx2 *bp)
1487 rc = bnx2_init_5706s_phy(bp); 1660 rc = bnx2_init_5706s_phy(bp);
1488 else if (CHIP_NUM(bp) == CHIP_NUM_5708) 1661 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1489 rc = bnx2_init_5708s_phy(bp); 1662 rc = bnx2_init_5708s_phy(bp);
1663 else if (CHIP_NUM(bp) == CHIP_NUM_5709)
1664 rc = bnx2_init_5709s_phy(bp);
1490 } 1665 }
1491 else { 1666 else {
1492 rc = bnx2_init_copper_phy(bp); 1667 rc = bnx2_init_copper_phy(bp);
@@ -4262,8 +4437,10 @@ bnx2_test_link(struct bnx2 *bp)
4262 u32 bmsr; 4437 u32 bmsr;
4263 4438
4264 spin_lock_bh(&bp->phy_lock); 4439 spin_lock_bh(&bp->phy_lock);
4265 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 4440 bnx2_enable_bmsr1(bp);
4266 bnx2_read_phy(bp, bp->mii_bmsr, &bmsr); 4441 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4442 bnx2_read_phy(bp, bp->mii_bmsr1, &bmsr);
4443 bnx2_disable_bmsr1(bp);
4267 spin_unlock_bh(&bp->phy_lock); 4444 spin_unlock_bh(&bp->phy_lock);
4268 4445
4269 if (bmsr & BMSR_LSTATUS) { 4446 if (bmsr & BMSR_LSTATUS) {
@@ -4407,7 +4584,7 @@ bnx2_timer(unsigned long data)
4407 if (bp->phy_flags & PHY_SERDES_FLAG) { 4584 if (bp->phy_flags & PHY_SERDES_FLAG) {
4408 if (CHIP_NUM(bp) == CHIP_NUM_5706) 4585 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4409 bnx2_5706_serdes_timer(bp); 4586 bnx2_5706_serdes_timer(bp);
4410 else if (CHIP_NUM(bp) == CHIP_NUM_5708) 4587 else
4411 bnx2_5708_serdes_timer(bp); 4588 bnx2_5708_serdes_timer(bp);
4412 } 4589 }
4413 4590
@@ -4910,8 +5087,10 @@ bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4910 5087
4911 advertising = cmd->advertising; 5088 advertising = cmd->advertising;
4912 5089
4913 } 5090 } else if (cmd->advertising == ADVERTISED_2500baseX_Full) {
4914 else if (cmd->advertising == ADVERTISED_1000baseT_Full) { 5091 if (!(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
5092 return -EINVAL;
5093 } else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4915 advertising = cmd->advertising; 5094 advertising = cmd->advertising;
4916 } 5095 }
4917 else if (cmd->advertising == ADVERTISED_1000baseT_Half) { 5096 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index d4a85d7b5ebe..124bd03cff3e 100644
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -6296,6 +6296,41 @@ struct l2_fhdr {
6296#define MII_BNX2_DSP_ADDRESS 0x17 6296#define MII_BNX2_DSP_ADDRESS 0x17
6297#define MII_BNX2_DSP_EXPAND_REG 0x0f00 6297#define MII_BNX2_DSP_EXPAND_REG 0x0f00
6298 6298
6299#define MII_BNX2_BLK_ADDR 0x1f
6300#define MII_BNX2_BLK_ADDR_IEEE0 0x0000
6301#define MII_BNX2_BLK_ADDR_GP_STATUS 0x8120
6302#define MII_BNX2_GP_TOP_AN_STATUS1 0x1b
6303#define MII_BNX2_GP_TOP_AN_SPEED_MSK 0x3f00
6304#define MII_BNX2_GP_TOP_AN_SPEED_10 0x0000
6305#define MII_BNX2_GP_TOP_AN_SPEED_100 0x0100
6306#define MII_BNX2_GP_TOP_AN_SPEED_1G 0x0200
6307#define MII_BNX2_GP_TOP_AN_SPEED_2_5G 0x0300
6308#define MII_BNX2_GP_TOP_AN_SPEED_1GKV 0x0d00
6309#define MII_BNX2_GP_TOP_AN_FD 0x8
6310#define MII_BNX2_BLK_ADDR_SERDES_DIG 0x8300
6311#define MII_BNX2_SERDES_DIG_1000XCTL1 0x10
6312#define MII_BNX2_SD_1000XCTL1_FIBER 0x01
6313#define MII_BNX2_SD_1000XCTL1_AUTODET 0x10
6314#define MII_BNX2_SERDES_DIG_MISC1 0x18
6315#define MII_BNX2_SD_MISC1_FORCE_MSK 0xf
6316#define MII_BNX2_SD_MISC1_FORCE_2_5G 0x0
6317#define MII_BNX2_SD_MISC1_FORCE 0x10
6318#define MII_BNX2_BLK_ADDR_OVER1G 0x8320
6319#define MII_BNX2_OVER1G_UP1 0x19
6320#define MII_BNX2_BLK_ADDR_BAM_NXTPG 0x8350
6321#define MII_BNX2_BAM_NXTPG_CTL 0x10
6322#define MII_BNX2_NXTPG_CTL_BAM 0x1
6323#define MII_BNX2_NXTPG_CTL_T2 0x2
6324#define MII_BNX2_BLK_ADDR_CL73_USERB0 0x8370
6325#define MII_BNX2_CL73_BAM_CTL1 0x12
6326#define MII_BNX2_CL73_BAM_EN 0x8000
6327#define MII_BNX2_CL73_BAM_STA_MGR_EN 0x4000
6328#define MII_BNX2_CL73_BAM_NP_AFT_BP_EN 0x2000
6329#define MII_BNX2_BLK_ADDR_AER 0xffd0
6330#define MII_BNX2_AER_AER 0x1e
6331#define MII_BNX2_AER_AER_AN_MMD 0x3800
6332#define MII_BNX2_BLK_ADDR_COMBO_IEEEB0 0xffe0
6333
6299#define MIN_ETHERNET_PACKET_SIZE 60 6334#define MIN_ETHERNET_PACKET_SIZE 60
6300#define MAX_ETHERNET_PACKET_SIZE 1514 6335#define MAX_ETHERNET_PACKET_SIZE 1514
6301#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014 6336#define MAX_ETHERNET_JUMBO_PACKET_SIZE 9014
@@ -6500,6 +6535,7 @@ struct bnx2 {
6500 6535
6501 u32 mii_bmcr; 6536 u32 mii_bmcr;
6502 u32 mii_bmsr; 6537 u32 mii_bmsr;
6538 u32 mii_bmsr1;
6503 u32 mii_adv; 6539 u32 mii_adv;
6504 u32 mii_lpa; 6540 u32 mii_lpa;
6505 u32 mii_up1; 6541 u32 mii_up1;