aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2012-12-13 15:14:47 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2012-12-13 15:14:47 -0500
commit193c0d682525987db59ac3a24531a77e4947aa95 (patch)
tree7b58346171c4d07e2c2ee6c3c469c325495149a4 /drivers/net
parent8b0cab14951fbf8126795ab301835a8f8126a988 (diff)
parent1cb73f8c479e66541fefd3f7fa547b1fa56cdc54 (diff)
Merge tag 'for-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI update from Bjorn Helgaas: "Host bridge hotplug: - Untangle _PRT from struct pci_bus (Bjorn Helgaas) - Request _OSC control before scanning root bus (Taku Izumi) - Assign resources when adding host bridge (Yinghai Lu) - Remove root bus when removing host bridge (Yinghai Lu) - Remove _PRT during hot remove (Yinghai Lu) SRIOV - Add sysfs knobs to control numVFs (Don Dutile) Power management - Notify devices when power resource turned on (Huang Ying) Bug fixes - Work around broken _SEG on HP xw9300 (Bjorn Helgaas) - Keep runtime PM enabled for unbound PCI devices (Huang Ying) - Fix Optimus dual-GPU runtime D3 suspend issue (Dave Airlie) - Fix xen frontend shutdown issue (David Vrabel) - Work around PLX PCI 9050 BAR alignment erratum (Ian Abbott) Miscellaneous - Add GPL license for drivers/pci/ioapic (Andrew Cooks) - Add standard PCI-X, PCIe ASPM register #defines (Bjorn Helgaas) - NumaChip remote PCI support (Daniel Blueman) - Fix PCIe Link Capabilities Supported Link Speed definition (Jingoo Han) - Convert dev_printk() to dev_info(), etc (Joe Perches) - Add support for non PCI BAR ROM data (Matthew Garrett) - Add x86 support for host bridge translation offset (Mike Yoknis) - Report success only when every driver supports AER (Vijay Pandarathil)" Fix up trivial conflicts. * tag 'for-3.8' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (48 commits) PCI: Use phys_addr_t for physical ROM address x86/PCI: Add NumaChip remote PCI support ath9k: Use standard #defines for PCIe Capability ASPM fields iwlwifi: Use standard #defines for PCIe Capability ASPM fields iwlwifi: collapse wrapper for pcie_capability_read_word() iwlegacy: Use standard #defines for PCIe Capability ASPM fields iwlegacy: collapse wrapper for pcie_capability_read_word() cxgb3: Use standard #defines for PCIe Capability ASPM fields PCI: Add standard PCIe Capability Link ASPM field names PCI/portdrv: Use PCI Express Capability accessors PCI: Use standard PCIe Capability Link register field names x86: Use PCI setup data PCI: Add support for non-BAR ROMs PCI: Add pcibios_add_device EFI: Stash ROMs if they're not in the PCI BAR PCI: Add and use standard PCI-X Capability register names PCI/PM: Keep runtime PM enabled for unbound PCI devices xen-pcifront: Handle backend CLOSED without CLOSING PCI: SRIOV control and status via sysfs (documentation) PCI/AER: Report success only when every device has AER-aware driver ...
Diffstat (limited to 'drivers/net')
-rw-r--r--drivers/net/ethernet/chelsio/cxgb3/t3_hw.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/pci.c8
-rw-r--r--drivers/net/wireless/iwlegacy/4965.h4
-rw-r--r--drivers/net/wireless/iwlegacy/common.c10
-rw-r--r--drivers/net/wireless/iwlegacy/common.h12
-rw-r--r--drivers/net/wireless/iwlwifi/pcie/trans.c8
6 files changed, 12 insertions, 32 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
index aef45d3113ba..3dee68612c9e 100644
--- a/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb3/t3_hw.c
@@ -3307,7 +3307,7 @@ static void config_pcie(struct adapter *adap)
3307 G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE)); 3307 G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));
3308 log2_width = fls(adap->params.pci.width) - 1; 3308 log2_width = fls(adap->params.pci.width) - 1;
3309 acklat = ack_lat[log2_width][pldsize]; 3309 acklat = ack_lat[log2_width][pldsize];
3310 if (val & 1) /* check LOsEnable */ 3310 if (val & PCI_EXP_LNKCTL_ASPM_L0S) /* check LOsEnable */
3311 acklat += fst_trn_tx * 4; 3311 acklat += fst_trn_tx * 4;
3312 rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4; 3312 rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4;
3313 3313
diff --git a/drivers/net/wireless/ath/ath9k/pci.c b/drivers/net/wireless/ath/ath9k/pci.c
index 8e9b826f878b..7ae73fbd9136 100644
--- a/drivers/net/wireless/ath/ath9k/pci.c
+++ b/drivers/net/wireless/ath/ath9k/pci.c
@@ -114,23 +114,23 @@ static void ath_pci_aspm_init(struct ath_common *common)
114 114
115 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) && 115 if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&
116 (AR_SREV_9285(ah))) { 116 (AR_SREV_9285(ah))) {
117 /* Bluetooth coexistance requires disabling ASPM. */ 117 /* Bluetooth coexistence requires disabling ASPM. */
118 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL, 118 pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,
119 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 119 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
120 120
121 /* 121 /*
122 * Both upstream and downstream PCIe components should 122 * Both upstream and downstream PCIe components should
123 * have the same ASPM settings. 123 * have the same ASPM settings.
124 */ 124 */
125 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL, 125 pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,
126 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 126 PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);
127 127
128 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n"); 128 ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");
129 return; 129 return;
130 } 130 }
131 131
132 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm); 132 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);
133 if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) { 133 if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) {
134 ah->aspm_enabled = true; 134 ah->aspm_enabled = true;
135 /* Initialize PCIe PM and SERDES registers. */ 135 /* Initialize PCIe PM and SERDES registers. */
136 ath9k_hw_configpcipowersave(ah, false); 136 ath9k_hw_configpcipowersave(ah, false);
diff --git a/drivers/net/wireless/iwlegacy/4965.h b/drivers/net/wireless/iwlegacy/4965.h
index 2d092f328547..1b15b0b2292b 100644
--- a/drivers/net/wireless/iwlegacy/4965.h
+++ b/drivers/net/wireless/iwlegacy/4965.h
@@ -917,10 +917,6 @@ struct il4965_scd_bc_tbl {
917/* PCI registers */ 917/* PCI registers */
918#define PCI_CFG_RETRY_TIMEOUT 0x041 918#define PCI_CFG_RETRY_TIMEOUT 0x041
919 919
920/* PCI register values */
921#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
922#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
923
924#define IL4965_DEFAULT_TX_RETRY 15 920#define IL4965_DEFAULT_TX_RETRY 15
925 921
926/* EEPROM */ 922/* EEPROM */
diff --git a/drivers/net/wireless/iwlegacy/common.c b/drivers/net/wireless/iwlegacy/common.c
index 318ed3c9fe74..7e16d10a7f14 100644
--- a/drivers/net/wireless/iwlegacy/common.c
+++ b/drivers/net/wireless/iwlegacy/common.c
@@ -1183,9 +1183,10 @@ EXPORT_SYMBOL(il_power_update_mode);
1183void 1183void
1184il_power_initialize(struct il_priv *il) 1184il_power_initialize(struct il_priv *il)
1185{ 1185{
1186 u16 lctl = il_pcie_link_ctl(il); 1186 u16 lctl;
1187 1187
1188 il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); 1188 pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
1189 il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
1189 1190
1190 il->power_data.debug_sleep_level_override = -1; 1191 il->power_data.debug_sleep_level_override = -1;
1191 1192
@@ -4233,9 +4234,8 @@ il_apm_init(struct il_priv *il)
4233 * power savings, even without L1. 4234 * power savings, even without L1.
4234 */ 4235 */
4235 if (il->cfg->set_l0s) { 4236 if (il->cfg->set_l0s) {
4236 lctl = il_pcie_link_ctl(il); 4237 pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);
4237 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == 4238 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
4238 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
4239 /* L1-ASPM enabled; disable(!) L0S */ 4239 /* L1-ASPM enabled; disable(!) L0S */
4240 il_set_bit(il, CSR_GIO_REG, 4240 il_set_bit(il, CSR_GIO_REG,
4241 CSR_GIO_REG_VAL_L0S_ENABLED); 4241 CSR_GIO_REG_VAL_L0S_ENABLED);
diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index e254cba4557a..a9a569f432fb 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -1829,14 +1829,6 @@ int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
1829 * PCI * 1829 * PCI *
1830 *****************************************************/ 1830 *****************************************************/
1831 1831
1832static inline u16
1833il_pcie_link_ctl(struct il_priv *il)
1834{
1835 u16 pci_lnk_ctl;
1836 pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &pci_lnk_ctl);
1837 return pci_lnk_ctl;
1838}
1839
1840void il_bg_watchdog(unsigned long data); 1832void il_bg_watchdog(unsigned long data);
1841u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval); 1833u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1842__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon, 1834__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
@@ -2434,10 +2426,6 @@ struct il_tfd {
2434/* PCI registers */ 2426/* PCI registers */
2435#define PCI_CFG_RETRY_TIMEOUT 0x041 2427#define PCI_CFG_RETRY_TIMEOUT 0x041
2436 2428
2437/* PCI register values */
2438#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
2439#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
2440
2441struct il_rate_info { 2429struct il_rate_info {
2442 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */ 2430 u8 plcp; /* uCode API: RATE_6M_PLCP, etc. */
2443 u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */ 2431 u8 plcp_siso; /* uCode API: RATE_SISO_6M_PLCP, etc. */
diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index d66cad4a7d6a..35708b959ad6 100644
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -94,8 +94,6 @@ static void iwl_pcie_set_pwr_vmain(struct iwl_trans *trans)
94 94
95/* PCI registers */ 95/* PCI registers */
96#define PCI_CFG_RETRY_TIMEOUT 0x041 96#define PCI_CFG_RETRY_TIMEOUT 0x041
97#define PCI_CFG_LINK_CTRL_VAL_L0S_EN 0x01
98#define PCI_CFG_LINK_CTRL_VAL_L1_EN 0x02
99 97
100static void iwl_pcie_apm_config(struct iwl_trans *trans) 98static void iwl_pcie_apm_config(struct iwl_trans *trans)
101{ 99{
@@ -111,9 +109,7 @@ static void iwl_pcie_apm_config(struct iwl_trans *trans)
111 * power savings, even without L1. 109 * power savings, even without L1.
112 */ 110 */
113 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 111 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
114 112 if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
115 if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==
116 PCI_CFG_LINK_CTRL_VAL_L1_EN) {
117 /* L1-ASPM enabled; disable(!) L0S */ 113 /* L1-ASPM enabled; disable(!) L0S */
118 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 114 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
119 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n"); 115 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
@@ -122,7 +118,7 @@ static void iwl_pcie_apm_config(struct iwl_trans *trans)
122 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED); 118 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
123 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n"); 119 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
124 } 120 }
125 trans->pm_support = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN); 121 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
126} 122}
127 123
128/* 124/*