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authorLuis R. Rodriguez <lrodriguez@atheros.com>2010-04-15 17:38:14 -0400
committerJohn W. Linville <linville@tuxdriver.com>2010-04-16 15:43:19 -0400
commit8fe6536850ae49609704a263cbc7542133536922 (patch)
tree68560fc5132795bbd422d8ecfdf62014f59d8598 /drivers/net/wireless
parentaed1baf1ab10f4b6bd40952a9deb791dbba48f3a (diff)
ath9k_hw: Move some RF ops to the private callbacks
The PHY split is easier done in a few steps. First move the RF ops to the private ops and rename them accordingly. We split PHY stuff up first for the AR5008 and AR9002 families. There are some callbacks that AR9002 share with the AR5008 familiy so we set those first, if AR9002 has some different callbacks it will override them upon hardware init. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/ath/ath9k/Makefile3
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/ar5008_phy.c (renamed from drivers/net/wireless/ath/ath9k/phy.c)882
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_phy.c450
-rw-r--r--drivers/net/wireless/ath/ath9k/ar9002_phy.h581
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c1
-rw-r--r--drivers/net/wireless/ath/ath9k/hw-ops.h113
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c467
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.h46
-rw-r--r--drivers/net/wireless/ath/ath9k/init.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.h576
14 files changed, 1673 insertions, 1452 deletions
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 97133beda269..db63ba298049 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -14,13 +14,14 @@ ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
14obj-$(CONFIG_ATH9K) += ath9k.o 14obj-$(CONFIG_ATH9K) += ath9k.o
15 15
16ath9k_hw-y:= hw.o \ 16ath9k_hw-y:= hw.o \
17 ar9002_phy.o \
18 ar5008_phy.o \
17 eeprom.o \ 19 eeprom.o \
18 eeprom_def.o \ 20 eeprom_def.o \
19 eeprom_4k.o \ 21 eeprom_4k.o \
20 eeprom_9287.o \ 22 eeprom_9287.o \
21 calib.o \ 23 calib.o \
22 ani.o \ 24 ani.o \
23 phy.o \
24 btcoex.o \ 25 btcoex.o \
25 mac.o \ 26 mac.o \
26 27
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 2a0cd64c2bfb..031802c8c125 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "hw.h" 17#include "hw.h"
18#include "ar9002_phy.h"
18 19
19static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah, 20static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
20 struct ath9k_channel *chan) 21 struct ath9k_channel *chan)
diff --git a/drivers/net/wireless/ath/ath9k/phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index 02d40dfd3a91..982b0d3877f8 100644
--- a/drivers/net/wireless/ath/ath9k/phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2008-2009 Atheros Communications Inc. 2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 * 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any 4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above 5 * purpose with or without fee is hereby granted, provided that the above
@@ -14,408 +14,15 @@
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */ 15 */
16 16
17/**
18 * DOC: Programming Atheros 802.11n analog front end radios
19 *
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
24 *
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
28 *
29 * The following single-chips exist with a respective embedded radio:
30 *
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
35 *
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
38 *
39 * AR9287 - 11n single-band 1x1 MIMO for USB
40 */
41
42#include "hw.h" 17#include "hw.h"
43 18#include "hw-ops.h"
44/** 19#include "../regd.h"
45 * ath9k_hw_ar9280_set_channel - set channel on single-chip device 20#include "ar9002_phy.h"
46 * @ah: atheros hardware structure
47 * @chan:
48 *
49 * This is the function to change channel on single-chip devices, that is
50 * all devices after ar9280.
51 *
52 * This function takes the channel value in MHz and sets
53 * hardware channel value. Assumes writes have been enabled to analog bus.
54 *
55 * Actual Expression,
56 *
57 * For 2GHz channel,
58 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
59 * (freq_ref = 40MHz)
60 *
61 * For 5GHz channel,
62 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
63 * (freq_ref = 40MHz/(24>>amodeRefSel))
64 */
65int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
66{
67 u16 bMode, fracMode, aModeRefSel = 0;
68 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
69 struct chan_centers centers;
70 u32 refDivA = 24;
71
72 ath9k_hw_get_channel_centers(ah, chan, &centers);
73 freq = centers.synth_center;
74
75 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
76 reg32 &= 0xc0000000;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
79 u32 txctl;
80 int regWrites = 0;
81
82 bMode = 1;
83 fracMode = 1;
84 aModeRefSel = 0;
85 channelSel = (freq * 0x10000) / 15;
86
87 if (AR_SREV_9287_11_OR_LATER(ah)) {
88 if (freq == 2484) {
89 /* Enable channel spreading for channel 14 */
90 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
91 1, regWrites);
92 } else {
93 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
94 1, regWrites);
95 }
96 } else {
97 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
98 if (freq == 2484) {
99 /* Enable channel spreading for channel 14 */
100 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
101 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
102 } else {
103 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
104 txctl &~ AR_PHY_CCK_TX_CTRL_JAPAN);
105 }
106 }
107 } else {
108 bMode = 0;
109 fracMode = 0;
110
111 switch(ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
112 case 0:
113 if ((freq % 20) == 0) {
114 aModeRefSel = 3;
115 } else if ((freq % 10) == 0) {
116 aModeRefSel = 2;
117 }
118 if (aModeRefSel)
119 break;
120 case 1:
121 default:
122 aModeRefSel = 0;
123 /*
124 * Enable 2G (fractional) mode for channels
125 * which are 5MHz spaced.
126 */
127 fracMode = 1;
128 refDivA = 1;
129 channelSel = (freq * 0x8000) / 15;
130
131 /* RefDivA setting */
132 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
133 AR_AN_SYNTH9_REFDIVA, refDivA);
134
135 }
136
137 if (!fracMode) {
138 ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
139 channelSel = ndiv & 0x1ff;
140 channelFrac = (ndiv & 0xfffffe00) * 2;
141 channelSel = (channelSel << 17) | channelFrac;
142 }
143 }
144
145 reg32 = reg32 |
146 (bMode << 29) |
147 (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
148
149 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
150
151 ah->curchan = chan;
152 ah->curchan_rad_index = -1;
153
154 return 0;
155}
156
157/**
158 * ath9k_hw_9280_spur_mitigate - convert baseband spur frequency
159 * @ah: atheros hardware structure
160 * @chan:
161 *
162 * For single-chip solutions. Converts to baseband spur frequency given the
163 * input channel frequency and compute register settings below.
164 */
165void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
166{
167 int bb_spur = AR_NO_SPUR;
168 int freq;
169 int bin, cur_bin;
170 int bb_spur_off, spur_subchannel_sd;
171 int spur_freq_sd;
172 int spur_delta_phase;
173 int denominator;
174 int upper, lower, cur_vit_mask;
175 int tmp, newVal;
176 int i;
177 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
178 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
179 };
180 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
181 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
182 };
183 int inc[4] = { 0, 100, 0, 0 };
184 struct chan_centers centers;
185
186 int8_t mask_m[123];
187 int8_t mask_p[123];
188 int8_t mask_amt;
189 int tmp_mask;
190 int cur_bb_spur;
191 bool is2GHz = IS_CHAN_2GHZ(chan);
192
193 memset(&mask_m, 0, sizeof(int8_t) * 123);
194 memset(&mask_p, 0, sizeof(int8_t) * 123);
195
196 ath9k_hw_get_channel_centers(ah, chan, &centers);
197 freq = centers.synth_center;
198
199 ah->config.spurmode = SPUR_ENABLE_EEPROM;
200 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
201 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
202
203 if (is2GHz)
204 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
205 else
206 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
207
208 if (AR_NO_SPUR == cur_bb_spur)
209 break;
210 cur_bb_spur = cur_bb_spur - freq;
211
212 if (IS_CHAN_HT40(chan)) {
213 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
214 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
215 bb_spur = cur_bb_spur;
216 break;
217 }
218 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
219 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
220 bb_spur = cur_bb_spur;
221 break;
222 }
223 }
224
225 if (AR_NO_SPUR == bb_spur) {
226 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
227 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
228 return;
229 } else {
230 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
231 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
232 }
233
234 bin = bb_spur * 320;
235
236 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
237
238 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
239 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
240 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
241 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
242 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
243
244 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
245 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
246 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
247 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
248 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
249 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
250
251 if (IS_CHAN_HT40(chan)) {
252 if (bb_spur < 0) {
253 spur_subchannel_sd = 1;
254 bb_spur_off = bb_spur + 10;
255 } else {
256 spur_subchannel_sd = 0;
257 bb_spur_off = bb_spur - 10;
258 }
259 } else {
260 spur_subchannel_sd = 0;
261 bb_spur_off = bb_spur;
262 }
263
264 if (IS_CHAN_HT40(chan))
265 spur_delta_phase =
266 ((bb_spur * 262144) /
267 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
268 else
269 spur_delta_phase =
270 ((bb_spur * 524288) /
271 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
272
273 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
274 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
275
276 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
277 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
278 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
279 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
280
281 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
282 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
283
284 cur_bin = -6000;
285 upper = bin + 100;
286 lower = bin - 100;
287
288 for (i = 0; i < 4; i++) {
289 int pilot_mask = 0;
290 int chan_mask = 0;
291 int bp = 0;
292 for (bp = 0; bp < 30; bp++) {
293 if ((cur_bin > lower) && (cur_bin < upper)) {
294 pilot_mask = pilot_mask | 0x1 << bp;
295 chan_mask = chan_mask | 0x1 << bp;
296 }
297 cur_bin += 100;
298 }
299 cur_bin += inc[i];
300 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
301 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
302 }
303
304 cur_vit_mask = 6100;
305 upper = bin + 120;
306 lower = bin - 120;
307
308 for (i = 0; i < 123; i++) {
309 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
310
311 /* workaround for gcc bug #37014 */
312 volatile int tmp_v = abs(cur_vit_mask - bin);
313
314 if (tmp_v < 75)
315 mask_amt = 1;
316 else
317 mask_amt = 0;
318 if (cur_vit_mask < 0)
319 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
320 else
321 mask_p[cur_vit_mask / 100] = mask_amt;
322 }
323 cur_vit_mask -= 100;
324 }
325
326 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
327 | (mask_m[48] << 26) | (mask_m[49] << 24)
328 | (mask_m[50] << 22) | (mask_m[51] << 20)
329 | (mask_m[52] << 18) | (mask_m[53] << 16)
330 | (mask_m[54] << 14) | (mask_m[55] << 12)
331 | (mask_m[56] << 10) | (mask_m[57] << 8)
332 | (mask_m[58] << 6) | (mask_m[59] << 4)
333 | (mask_m[60] << 2) | (mask_m[61] << 0);
334 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
335 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
336
337 tmp_mask = (mask_m[31] << 28)
338 | (mask_m[32] << 26) | (mask_m[33] << 24)
339 | (mask_m[34] << 22) | (mask_m[35] << 20)
340 | (mask_m[36] << 18) | (mask_m[37] << 16)
341 | (mask_m[48] << 14) | (mask_m[39] << 12)
342 | (mask_m[40] << 10) | (mask_m[41] << 8)
343 | (mask_m[42] << 6) | (mask_m[43] << 4)
344 | (mask_m[44] << 2) | (mask_m[45] << 0);
345 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
346 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
347
348 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
349 | (mask_m[18] << 26) | (mask_m[18] << 24)
350 | (mask_m[20] << 22) | (mask_m[20] << 20)
351 | (mask_m[22] << 18) | (mask_m[22] << 16)
352 | (mask_m[24] << 14) | (mask_m[24] << 12)
353 | (mask_m[25] << 10) | (mask_m[26] << 8)
354 | (mask_m[27] << 6) | (mask_m[28] << 4)
355 | (mask_m[29] << 2) | (mask_m[30] << 0);
356 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
357 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
358
359 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
360 | (mask_m[2] << 26) | (mask_m[3] << 24)
361 | (mask_m[4] << 22) | (mask_m[5] << 20)
362 | (mask_m[6] << 18) | (mask_m[7] << 16)
363 | (mask_m[8] << 14) | (mask_m[9] << 12)
364 | (mask_m[10] << 10) | (mask_m[11] << 8)
365 | (mask_m[12] << 6) | (mask_m[13] << 4)
366 | (mask_m[14] << 2) | (mask_m[15] << 0);
367 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
368 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
369
370 tmp_mask = (mask_p[15] << 28)
371 | (mask_p[14] << 26) | (mask_p[13] << 24)
372 | (mask_p[12] << 22) | (mask_p[11] << 20)
373 | (mask_p[10] << 18) | (mask_p[9] << 16)
374 | (mask_p[8] << 14) | (mask_p[7] << 12)
375 | (mask_p[6] << 10) | (mask_p[5] << 8)
376 | (mask_p[4] << 6) | (mask_p[3] << 4)
377 | (mask_p[2] << 2) | (mask_p[1] << 0);
378 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
379 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
380
381 tmp_mask = (mask_p[30] << 28)
382 | (mask_p[29] << 26) | (mask_p[28] << 24)
383 | (mask_p[27] << 22) | (mask_p[26] << 20)
384 | (mask_p[25] << 18) | (mask_p[24] << 16)
385 | (mask_p[23] << 14) | (mask_p[22] << 12)
386 | (mask_p[21] << 10) | (mask_p[20] << 8)
387 | (mask_p[19] << 6) | (mask_p[18] << 4)
388 | (mask_p[17] << 2) | (mask_p[16] << 0);
389 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
390 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
391
392 tmp_mask = (mask_p[45] << 28)
393 | (mask_p[44] << 26) | (mask_p[43] << 24)
394 | (mask_p[42] << 22) | (mask_p[41] << 20)
395 | (mask_p[40] << 18) | (mask_p[39] << 16)
396 | (mask_p[38] << 14) | (mask_p[37] << 12)
397 | (mask_p[36] << 10) | (mask_p[35] << 8)
398 | (mask_p[34] << 6) | (mask_p[33] << 4)
399 | (mask_p[32] << 2) | (mask_p[31] << 0);
400 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
401 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
402
403 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
404 | (mask_p[59] << 26) | (mask_p[58] << 24)
405 | (mask_p[57] << 22) | (mask_p[56] << 20)
406 | (mask_p[55] << 18) | (mask_p[54] << 16)
407 | (mask_p[53] << 14) | (mask_p[52] << 12)
408 | (mask_p[51] << 10) | (mask_p[50] << 8)
409 | (mask_p[49] << 6) | (mask_p[48] << 4)
410 | (mask_p[47] << 2) | (mask_p[46] << 0);
411 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
412 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
413}
414 21
415/* All code below is for non single-chip solutions */ 22/* All code below is for non single-chip solutions */
416 23
417/** 24/**
418 * ath9k_phy_modify_rx_buffer() - perform analog swizzling of parameters 25 * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
419 * @rfbuf: 26 * @rfbuf:
420 * @reg32: 27 * @reg32:
421 * @numBits: 28 * @numBits:
@@ -425,9 +32,9 @@ void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
425 * Performs analog "swizzling" of parameters into their location. 32 * Performs analog "swizzling" of parameters into their location.
426 * Used on external AR2133/AR5133 radios. 33 * Used on external AR2133/AR5133 radios.
427 */ 34 */
428static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, 35static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
429 u32 numBits, u32 firstBit, 36 u32 numBits, u32 firstBit,
430 u32 column) 37 u32 column)
431{ 38{
432 u32 tmp32, mask, arrayEntry, lastBit; 39 u32 tmp32, mask, arrayEntry, lastBit;
433 int32_t bitPosition, bitsLeft; 40 int32_t bitPosition, bitsLeft;
@@ -478,16 +85,15 @@ static void ath9k_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
478 * 2nd Mod: 85 * 2nd Mod:
479 * Less than 2412 uses value of 0, 2412 and above uses value of 2 86 * Less than 2412 uses value of 0, 2412 and above uses value of 2
480 */ 87 */
481static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq) 88static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
482{ 89{
483 struct ath_common *common = ath9k_hw_common(ah); 90 struct ath_common *common = ath9k_hw_common(ah);
484 u32 tmp_reg; 91 u32 tmp_reg;
485 int reg_writes = 0; 92 int reg_writes = 0;
486 u32 new_bias = 0; 93 u32 new_bias = 0;
487 94
488 if (!AR_SREV_5416(ah) || synth_freq >= 3000) { 95 if (!AR_SREV_5416(ah) || synth_freq >= 3000)
489 return; 96 return;
490 }
491 97
492 BUG_ON(AR_SREV_9280_10_OR_LATER(ah)); 98 BUG_ON(AR_SREV_9280_10_OR_LATER(ah));
493 99
@@ -506,14 +112,14 @@ static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
506 new_bias, synth_freq); 112 new_bias, synth_freq);
507 113
508 /* swizzle rf_pwd_icsyndiv */ 114 /* swizzle rf_pwd_icsyndiv */
509 ath9k_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3); 115 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
510 116
511 /* write Bank 6 with new params */ 117 /* write Bank 6 with new params */
512 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes); 118 REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
513} 119}
514 120
515/** 121/**
516 * ath9k_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios 122 * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
517 * @ah: atheros hardware stucture 123 * @ah: atheros hardware stucture
518 * @chan: 124 * @chan:
519 * 125 *
@@ -521,7 +127,7 @@ static void ath9k_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
521 * the channel value. Assumes writes enabled to analog bus and bank6 register 127 * the channel value. Assumes writes enabled to analog bus and bank6 register
522 * cache in ah->analogBank6Data. 128 * cache in ah->analogBank6Data.
523 */ 129 */
524int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) 130static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
525{ 131{
526 struct ath_common *common = ath9k_hw_common(ah); 132 struct ath_common *common = ath9k_hw_common(ah);
527 u32 channelSel = 0; 133 u32 channelSel = 0;
@@ -582,7 +188,7 @@ int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
582 return -EINVAL; 188 return -EINVAL;
583 } 189 }
584 190
585 ath9k_hw_force_bias(ah, freq); 191 ar5008_hw_force_bias(ah, freq);
586 192
587 reg32 = 193 reg32 =
588 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) | 194 (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
@@ -597,14 +203,15 @@ int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
597} 203}
598 204
599/** 205/**
600 * ath9k_hw_spur_mitigate - convert baseband spur frequency for external radios 206 * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
601 * @ah: atheros hardware structure 207 * @ah: atheros hardware structure
602 * @chan: 208 * @chan:
603 * 209 *
604 * For non single-chip solutions. Converts to baseband spur frequency given the 210 * For non single-chip solutions. Converts to baseband spur frequency given the
605 * input channel frequency and compute register settings below. 211 * input channel frequency and compute register settings below.
606 */ 212 */
607void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan) 213static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
214 struct ath9k_channel *chan)
608{ 215{
609 int bb_spur = AR_NO_SPUR; 216 int bb_spur = AR_NO_SPUR;
610 int bin, cur_bin; 217 int bin, cur_bin;
@@ -806,12 +413,12 @@ void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
806} 413}
807 414
808/** 415/**
809 * ath9k_hw_rf_alloc_ext_banks - allocates banks for external radio programming 416 * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
810 * @ah: atheros hardware structure 417 * @ah: atheros hardware structure
811 * 418 *
812 * Only required for older devices with external AR2133/AR5133 radios. 419 * Only required for older devices with external AR2133/AR5133 radios.
813 */ 420 */
814int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah) 421static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
815{ 422{
816#define ATH_ALLOC_BANK(bank, size) do { \ 423#define ATH_ALLOC_BANK(bank, size) do { \
817 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \ 424 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
@@ -843,12 +450,11 @@ int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
843 450
844 451
845/** 452/**
846 * ath9k_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers 453 * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
847 * @ah: atheros hardware struture 454 * @ah: atheros hardware struture
848 * For the external AR2133/AR5133 radios banks. 455 * For the external AR2133/AR5133 radios banks.
849 */ 456 */
850void 457static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
851ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
852{ 458{
853#define ATH_FREE_BANK(bank) do { \ 459#define ATH_FREE_BANK(bank) do { \
854 kfree(bank); \ 460 kfree(bank); \
@@ -871,7 +477,7 @@ ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
871} 477}
872 478
873/* * 479/* *
874 * ath9k_hw_set_rf_regs - programs rf registers based on EEPROM 480 * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
875 * @ah: atheros hardware structure 481 * @ah: atheros hardware structure
876 * @chan: 482 * @chan:
877 * @modesIndex: 483 * @modesIndex:
@@ -882,8 +488,9 @@ ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
882 * all rf registers. This routine requires access to the analog 488 * all rf registers. This routine requires access to the analog
883 * rf device. This is not required for single-chip devices. 489 * rf device. This is not required for single-chip devices.
884 */ 490 */
885bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan, 491static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
886 u16 modesIndex) 492 struct ath9k_channel *chan,
493 u16 modesIndex)
887{ 494{
888 u32 eepMinorRev; 495 u32 eepMinorRev;
889 u32 ob5GHz = 0, db5GHz = 0; 496 u32 ob5GHz = 0, db5GHz = 0;
@@ -926,17 +533,17 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
926 if (IS_CHAN_2GHZ(chan)) { 533 if (IS_CHAN_2GHZ(chan)) {
927 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2); 534 ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
928 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2); 535 db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
929 ath9k_phy_modify_rx_buffer(ah->analogBank6Data, 536 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
930 ob2GHz, 3, 197, 0); 537 ob2GHz, 3, 197, 0);
931 ath9k_phy_modify_rx_buffer(ah->analogBank6Data, 538 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
932 db2GHz, 3, 194, 0); 539 db2GHz, 3, 194, 0);
933 } else { 540 } else {
934 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5); 541 ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
935 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5); 542 db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
936 ath9k_phy_modify_rx_buffer(ah->analogBank6Data, 543 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
937 ob5GHz, 3, 203, 0); 544 ob5GHz, 3, 203, 0);
938 ath9k_phy_modify_rx_buffer(ah->analogBank6Data, 545 ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
939 db5GHz, 3, 200, 0); 546 db5GHz, 3, 200, 0);
940 } 547 }
941 } 548 }
942 549
@@ -959,3 +566,426 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah, struct ath9k_channel *chan,
959 566
960 return true; 567 return true;
961} 568}
569
570static void ar5008_hw_init_bb(struct ath_hw *ah,
571 struct ath9k_channel *chan)
572{
573 u32 synthDelay;
574
575 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
576 if (IS_CHAN_B(chan))
577 synthDelay = (4 * synthDelay) / 22;
578 else
579 synthDelay /= 10;
580
581 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
582
583 udelay(synthDelay + BASE_ACTIVATE_DELAY);
584}
585
586static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
587{
588 int rx_chainmask, tx_chainmask;
589
590 rx_chainmask = ah->rxchainmask;
591 tx_chainmask = ah->txchainmask;
592
593 switch (rx_chainmask) {
594 case 0x5:
595 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
596 AR_PHY_SWAP_ALT_CHAIN);
597 case 0x3:
598 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
599 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
600 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
601 break;
602 }
603 case 0x1:
604 case 0x2:
605 case 0x7:
606 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
607 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
608 break;
609 default:
610 break;
611 }
612
613 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
614 if (tx_chainmask == 0x5) {
615 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
616 AR_PHY_SWAP_ALT_CHAIN);
617 }
618 if (AR_SREV_9100(ah))
619 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
620 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
621}
622
623static void ar5008_hw_override_ini(struct ath_hw *ah,
624 struct ath9k_channel *chan)
625{
626 u32 val;
627
628 /*
629 * Set the RX_ABORT and RX_DIS and clear if off only after
630 * RXE is set for MAC. This prevents frames with corrupted
631 * descriptor status.
632 */
633 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
634
635 if (AR_SREV_9280_10_OR_LATER(ah)) {
636 val = REG_READ(ah, AR_PCU_MISC_MODE2);
637
638 if (!AR_SREV_9271(ah))
639 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
640
641 if (AR_SREV_9287_10_OR_LATER(ah))
642 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
643
644 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
645 }
646
647 if (!AR_SREV_5416_20_OR_LATER(ah) ||
648 AR_SREV_9280_10_OR_LATER(ah))
649 return;
650 /*
651 * Disable BB clock gating
652 * Necessary to avoid issues on AR5416 2.0
653 */
654 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
655
656 /*
657 * Disable RIFS search on some chips to avoid baseband
658 * hang issues.
659 */
660 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
661 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
662 val &= ~AR_PHY_RIFS_INIT_DELAY;
663 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
664 }
665}
666
667static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
668 struct ath9k_channel *chan)
669{
670 u32 phymode;
671 u32 enableDacFifo = 0;
672
673 if (AR_SREV_9285_10_OR_LATER(ah))
674 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
675 AR_PHY_FC_ENABLE_DAC_FIFO);
676
677 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
678 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
679
680 if (IS_CHAN_HT40(chan)) {
681 phymode |= AR_PHY_FC_DYN2040_EN;
682
683 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
684 (chan->chanmode == CHANNEL_G_HT40PLUS))
685 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
686
687 }
688 REG_WRITE(ah, AR_PHY_TURBO, phymode);
689
690 ath9k_hw_set11nmac2040(ah);
691
692 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
693 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
694}
695
696
697static int ar5008_hw_process_ini(struct ath_hw *ah,
698 struct ath9k_channel *chan)
699{
700 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
701 int i, regWrites = 0;
702 struct ieee80211_channel *channel = chan->chan;
703 u32 modesIndex, freqIndex;
704
705 switch (chan->chanmode) {
706 case CHANNEL_A:
707 case CHANNEL_A_HT20:
708 modesIndex = 1;
709 freqIndex = 1;
710 break;
711 case CHANNEL_A_HT40PLUS:
712 case CHANNEL_A_HT40MINUS:
713 modesIndex = 2;
714 freqIndex = 1;
715 break;
716 case CHANNEL_G:
717 case CHANNEL_G_HT20:
718 case CHANNEL_B:
719 modesIndex = 4;
720 freqIndex = 2;
721 break;
722 case CHANNEL_G_HT40PLUS:
723 case CHANNEL_G_HT40MINUS:
724 modesIndex = 3;
725 freqIndex = 2;
726 break;
727
728 default:
729 return -EINVAL;
730 }
731
732 if (AR_SREV_9287_12_OR_LATER(ah)) {
733 /* Enable ASYNC FIFO */
734 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
735 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
736 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
737 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
738 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
739 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
740 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
741 }
742
743 /*
744 * Set correct baseband to analog shift setting to
745 * access analog chips.
746 */
747 REG_WRITE(ah, AR_PHY(0), 0x00000007);
748
749 /* Write ADDAC shifts */
750 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
751 ah->eep_ops->set_addac(ah, chan);
752
753 if (AR_SREV_5416_22_OR_LATER(ah)) {
754 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
755 } else {
756 struct ar5416IniArray temp;
757 u32 addacSize =
758 sizeof(u32) * ah->iniAddac.ia_rows *
759 ah->iniAddac.ia_columns;
760
761 /* For AR5416 2.0/2.1 */
762 memcpy(ah->addac5416_21,
763 ah->iniAddac.ia_array, addacSize);
764
765 /* override CLKDRV value at [row, column] = [31, 1] */
766 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
767
768 temp.ia_array = ah->addac5416_21;
769 temp.ia_columns = ah->iniAddac.ia_columns;
770 temp.ia_rows = ah->iniAddac.ia_rows;
771 REG_WRITE_ARRAY(&temp, 1, regWrites);
772 }
773
774 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
775
776 for (i = 0; i < ah->iniModes.ia_rows; i++) {
777 u32 reg = INI_RA(&ah->iniModes, i, 0);
778 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
779
780 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
781 val &= ~AR_AN_TOP2_PWDCLKIND;
782
783 REG_WRITE(ah, reg, val);
784
785 if (reg >= 0x7800 && reg < 0x78a0
786 && ah->config.analog_shiftreg) {
787 udelay(100);
788 }
789
790 DO_DELAY(regWrites);
791 }
792
793 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
794 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
795
796 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
797 AR_SREV_9287_10_OR_LATER(ah))
798 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
799
800 if (AR_SREV_9271_10(ah))
801 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
802 modesIndex, regWrites);
803
804 /* Write common array parameters */
805 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
806 u32 reg = INI_RA(&ah->iniCommon, i, 0);
807 u32 val = INI_RA(&ah->iniCommon, i, 1);
808
809 REG_WRITE(ah, reg, val);
810
811 if (reg >= 0x7800 && reg < 0x78a0
812 && ah->config.analog_shiftreg) {
813 udelay(100);
814 }
815
816 DO_DELAY(regWrites);
817 }
818
819 if (AR_SREV_9271(ah)) {
820 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
821 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
822 modesIndex, regWrites);
823 else
824 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
825 modesIndex, regWrites);
826 }
827
828 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
829
830 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
831 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
832 regWrites);
833 }
834
835 ar5008_hw_override_ini(ah, chan);
836 ar5008_hw_set_channel_regs(ah, chan);
837 ar5008_hw_init_chain_masks(ah);
838 ath9k_olc_init(ah);
839
840 /* Set TX power */
841 ah->eep_ops->set_txpower(ah, chan,
842 ath9k_regd_get_ctl(regulatory, chan),
843 channel->max_antenna_gain * 2,
844 channel->max_power * 2,
845 min((u32) MAX_RATE_POWER,
846 (u32) regulatory->power_limit));
847
848 /* Write analog registers */
849 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
850 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
851 "ar5416SetRfRegs failed\n");
852 return -EIO;
853 }
854
855 return 0;
856}
857
858static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
859{
860 u32 rfMode = 0;
861
862 if (chan == NULL)
863 return;
864
865 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
866 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
867
868 if (!AR_SREV_9280_10_OR_LATER(ah))
869 rfMode |= (IS_CHAN_5GHZ(chan)) ?
870 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
871
872 if ((AR_SREV_9280_20(ah) || AR_SREV_9300_20_OR_LATER(ah))
873 && IS_CHAN_A_5MHZ_SPACED(chan))
874 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
875
876 REG_WRITE(ah, AR_PHY_MODE, rfMode);
877}
878
879static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
880{
881 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
882}
883
884static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
885 struct ath9k_channel *chan)
886{
887 u32 coef_scaled, ds_coef_exp, ds_coef_man;
888 u32 clockMhzScaled = 0x64000000;
889 struct chan_centers centers;
890
891 if (IS_CHAN_HALF_RATE(chan))
892 clockMhzScaled = clockMhzScaled >> 1;
893 else if (IS_CHAN_QUARTER_RATE(chan))
894 clockMhzScaled = clockMhzScaled >> 2;
895
896 ath9k_hw_get_channel_centers(ah, chan, &centers);
897 coef_scaled = clockMhzScaled / centers.synth_center;
898
899 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
900 &ds_coef_exp);
901
902 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
903 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
904 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
905 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
906
907 coef_scaled = (9 * coef_scaled) / 10;
908
909 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
910 &ds_coef_exp);
911
912 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
913 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
914 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
915 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
916}
917
918static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
919{
920 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
921 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
922 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
923}
924
925static void ar5008_hw_rfbus_done(struct ath_hw *ah)
926{
927 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
928 if (IS_CHAN_B(ah->curchan))
929 synthDelay = (4 * synthDelay) / 22;
930 else
931 synthDelay /= 10;
932
933 udelay(synthDelay + BASE_ACTIVATE_DELAY);
934
935 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
936}
937
938static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
939{
940 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
941 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
942
943 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
944 AR_GPIO_INPUT_MUX2_RFSILENT);
945
946 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
947 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
948}
949
950static void ar5008_restore_chainmask(struct ath_hw *ah)
951{
952 int rx_chainmask = ah->rxchainmask;
953
954 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
955 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
956 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
957 }
958}
959
960static void ar5008_set_diversity(struct ath_hw *ah, bool value)
961{
962 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
963 if (value)
964 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
965 else
966 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
967 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
968}
969
970void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
971{
972 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
973
974 priv_ops->rf_set_freq = ar5008_hw_set_channel;
975 priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
976
977 priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
978 priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
979 priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
980 priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
981 priv_ops->init_bb = ar5008_hw_init_bb;
982 priv_ops->process_ini = ar5008_hw_process_ini;
983 priv_ops->set_rfmode = ar5008_hw_set_rfmode;
984 priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
985 priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
986 priv_ops->rfbus_req = ar5008_hw_rfbus_req;
987 priv_ops->rfbus_done = ar5008_hw_rfbus_done;
988 priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
989 priv_ops->restore_chainmask = ar5008_restore_chainmask;
990 priv_ops->set_diversity = ar5008_set_diversity;
991}
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.c b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
new file mode 100644
index 000000000000..29b50ca0a0cc
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.c
@@ -0,0 +1,450 @@
1/*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17/**
18 * DOC: Programming Atheros 802.11n analog front end radios
19 *
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
24 *
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
28 *
29 * The following single-chips exist with a respective embedded radio:
30 *
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
35 *
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
38 *
39 * AR9287 - 11n single-band 1x1 MIMO for USB
40 */
41
42#include "hw.h"
43#include "ar9002_phy.h"
44
45/**
46 * ar9002_hw_set_channel - set channel on single-chip device
47 * @ah: atheros hardware structure
48 * @chan:
49 *
50 * This is the function to change channel on single-chip devices, that is
51 * all devices after ar9280.
52 *
53 * This function takes the channel value in MHz and sets
54 * hardware channel value. Assumes writes have been enabled to analog bus.
55 *
56 * Actual Expression,
57 *
58 * For 2GHz channel,
59 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
60 * (freq_ref = 40MHz)
61 *
62 * For 5GHz channel,
63 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
64 * (freq_ref = 40MHz/(24>>amodeRefSel))
65 */
66static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
67{
68 u16 bMode, fracMode, aModeRefSel = 0;
69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
70 struct chan_centers centers;
71 u32 refDivA = 24;
72
73 ath9k_hw_get_channel_centers(ah, chan, &centers);
74 freq = centers.synth_center;
75
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
77 reg32 &= 0xc0000000;
78
79 if (freq < 4800) { /* 2 GHz, fractional mode */
80 u32 txctl;
81 int regWrites = 0;
82
83 bMode = 1;
84 fracMode = 1;
85 aModeRefSel = 0;
86 channelSel = (freq * 0x10000) / 15;
87
88 if (AR_SREV_9287_11_OR_LATER(ah)) {
89 if (freq == 2484) {
90 /* Enable channel spreading for channel 14 */
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
92 1, regWrites);
93 } else {
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
95 1, regWrites);
96 }
97 } else {
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
99 if (freq == 2484) {
100 /* Enable channel spreading for channel 14 */
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
102 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
103 } else {
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
105 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
106 }
107 }
108 } else {
109 bMode = 0;
110 fracMode = 0;
111
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
113 case 0:
114 if ((freq % 20) == 0)
115 aModeRefSel = 3;
116 else if ((freq % 10) == 0)
117 aModeRefSel = 2;
118 if (aModeRefSel)
119 break;
120 case 1:
121 default:
122 aModeRefSel = 0;
123 /*
124 * Enable 2G (fractional) mode for channels
125 * which are 5MHz spaced.
126 */
127 fracMode = 1;
128 refDivA = 1;
129 channelSel = (freq * 0x8000) / 15;
130
131 /* RefDivA setting */
132 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
133 AR_AN_SYNTH9_REFDIVA, refDivA);
134
135 }
136
137 if (!fracMode) {
138 ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
139 channelSel = ndiv & 0x1ff;
140 channelFrac = (ndiv & 0xfffffe00) * 2;
141 channelSel = (channelSel << 17) | channelFrac;
142 }
143 }
144
145 reg32 = reg32 |
146 (bMode << 29) |
147 (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
148
149 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
150
151 ah->curchan = chan;
152 ah->curchan_rad_index = -1;
153
154 return 0;
155}
156
157/**
158 * ar9002_hw_spur_mitigate - convert baseband spur frequency
159 * @ah: atheros hardware structure
160 * @chan:
161 *
162 * For single-chip solutions. Converts to baseband spur frequency given the
163 * input channel frequency and compute register settings below.
164 */
165static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
166 struct ath9k_channel *chan)
167{
168 int bb_spur = AR_NO_SPUR;
169 int freq;
170 int bin, cur_bin;
171 int bb_spur_off, spur_subchannel_sd;
172 int spur_freq_sd;
173 int spur_delta_phase;
174 int denominator;
175 int upper, lower, cur_vit_mask;
176 int tmp, newVal;
177 int i;
178 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
179 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
180 };
181 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
182 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
183 };
184 int inc[4] = { 0, 100, 0, 0 };
185 struct chan_centers centers;
186
187 int8_t mask_m[123];
188 int8_t mask_p[123];
189 int8_t mask_amt;
190 int tmp_mask;
191 int cur_bb_spur;
192 bool is2GHz = IS_CHAN_2GHZ(chan);
193
194 memset(&mask_m, 0, sizeof(int8_t) * 123);
195 memset(&mask_p, 0, sizeof(int8_t) * 123);
196
197 ath9k_hw_get_channel_centers(ah, chan, &centers);
198 freq = centers.synth_center;
199
200 ah->config.spurmode = SPUR_ENABLE_EEPROM;
201 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
202 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
203
204 if (is2GHz)
205 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
206 else
207 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
208
209 if (AR_NO_SPUR == cur_bb_spur)
210 break;
211 cur_bb_spur = cur_bb_spur - freq;
212
213 if (IS_CHAN_HT40(chan)) {
214 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
215 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
216 bb_spur = cur_bb_spur;
217 break;
218 }
219 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
220 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
221 bb_spur = cur_bb_spur;
222 break;
223 }
224 }
225
226 if (AR_NO_SPUR == bb_spur) {
227 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
228 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
229 return;
230 } else {
231 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
232 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
233 }
234
235 bin = bb_spur * 320;
236
237 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
238
239 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
240 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
241 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
242 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
243 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
244
245 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
246 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
247 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
248 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
249 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
250 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
251
252 if (IS_CHAN_HT40(chan)) {
253 if (bb_spur < 0) {
254 spur_subchannel_sd = 1;
255 bb_spur_off = bb_spur + 10;
256 } else {
257 spur_subchannel_sd = 0;
258 bb_spur_off = bb_spur - 10;
259 }
260 } else {
261 spur_subchannel_sd = 0;
262 bb_spur_off = bb_spur;
263 }
264
265 if (IS_CHAN_HT40(chan))
266 spur_delta_phase =
267 ((bb_spur * 262144) /
268 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
269 else
270 spur_delta_phase =
271 ((bb_spur * 524288) /
272 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
273
274 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
275 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
276
277 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
278 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
279 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
280 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
281
282 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
283 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
284
285 cur_bin = -6000;
286 upper = bin + 100;
287 lower = bin - 100;
288
289 for (i = 0; i < 4; i++) {
290 int pilot_mask = 0;
291 int chan_mask = 0;
292 int bp = 0;
293 for (bp = 0; bp < 30; bp++) {
294 if ((cur_bin > lower) && (cur_bin < upper)) {
295 pilot_mask = pilot_mask | 0x1 << bp;
296 chan_mask = chan_mask | 0x1 << bp;
297 }
298 cur_bin += 100;
299 }
300 cur_bin += inc[i];
301 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
302 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
303 }
304
305 cur_vit_mask = 6100;
306 upper = bin + 120;
307 lower = bin - 120;
308
309 for (i = 0; i < 123; i++) {
310 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
311
312 /* workaround for gcc bug #37014 */
313 volatile int tmp_v = abs(cur_vit_mask - bin);
314
315 if (tmp_v < 75)
316 mask_amt = 1;
317 else
318 mask_amt = 0;
319 if (cur_vit_mask < 0)
320 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
321 else
322 mask_p[cur_vit_mask / 100] = mask_amt;
323 }
324 cur_vit_mask -= 100;
325 }
326
327 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
328 | (mask_m[48] << 26) | (mask_m[49] << 24)
329 | (mask_m[50] << 22) | (mask_m[51] << 20)
330 | (mask_m[52] << 18) | (mask_m[53] << 16)
331 | (mask_m[54] << 14) | (mask_m[55] << 12)
332 | (mask_m[56] << 10) | (mask_m[57] << 8)
333 | (mask_m[58] << 6) | (mask_m[59] << 4)
334 | (mask_m[60] << 2) | (mask_m[61] << 0);
335 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
336 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
337
338 tmp_mask = (mask_m[31] << 28)
339 | (mask_m[32] << 26) | (mask_m[33] << 24)
340 | (mask_m[34] << 22) | (mask_m[35] << 20)
341 | (mask_m[36] << 18) | (mask_m[37] << 16)
342 | (mask_m[48] << 14) | (mask_m[39] << 12)
343 | (mask_m[40] << 10) | (mask_m[41] << 8)
344 | (mask_m[42] << 6) | (mask_m[43] << 4)
345 | (mask_m[44] << 2) | (mask_m[45] << 0);
346 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
347 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
348
349 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
350 | (mask_m[18] << 26) | (mask_m[18] << 24)
351 | (mask_m[20] << 22) | (mask_m[20] << 20)
352 | (mask_m[22] << 18) | (mask_m[22] << 16)
353 | (mask_m[24] << 14) | (mask_m[24] << 12)
354 | (mask_m[25] << 10) | (mask_m[26] << 8)
355 | (mask_m[27] << 6) | (mask_m[28] << 4)
356 | (mask_m[29] << 2) | (mask_m[30] << 0);
357 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
358 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
359
360 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
361 | (mask_m[2] << 26) | (mask_m[3] << 24)
362 | (mask_m[4] << 22) | (mask_m[5] << 20)
363 | (mask_m[6] << 18) | (mask_m[7] << 16)
364 | (mask_m[8] << 14) | (mask_m[9] << 12)
365 | (mask_m[10] << 10) | (mask_m[11] << 8)
366 | (mask_m[12] << 6) | (mask_m[13] << 4)
367 | (mask_m[14] << 2) | (mask_m[15] << 0);
368 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
369 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
370
371 tmp_mask = (mask_p[15] << 28)
372 | (mask_p[14] << 26) | (mask_p[13] << 24)
373 | (mask_p[12] << 22) | (mask_p[11] << 20)
374 | (mask_p[10] << 18) | (mask_p[9] << 16)
375 | (mask_p[8] << 14) | (mask_p[7] << 12)
376 | (mask_p[6] << 10) | (mask_p[5] << 8)
377 | (mask_p[4] << 6) | (mask_p[3] << 4)
378 | (mask_p[2] << 2) | (mask_p[1] << 0);
379 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
380 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
381
382 tmp_mask = (mask_p[30] << 28)
383 | (mask_p[29] << 26) | (mask_p[28] << 24)
384 | (mask_p[27] << 22) | (mask_p[26] << 20)
385 | (mask_p[25] << 18) | (mask_p[24] << 16)
386 | (mask_p[23] << 14) | (mask_p[22] << 12)
387 | (mask_p[21] << 10) | (mask_p[20] << 8)
388 | (mask_p[19] << 6) | (mask_p[18] << 4)
389 | (mask_p[17] << 2) | (mask_p[16] << 0);
390 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
391 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
392
393 tmp_mask = (mask_p[45] << 28)
394 | (mask_p[44] << 26) | (mask_p[43] << 24)
395 | (mask_p[42] << 22) | (mask_p[41] << 20)
396 | (mask_p[40] << 18) | (mask_p[39] << 16)
397 | (mask_p[38] << 14) | (mask_p[37] << 12)
398 | (mask_p[36] << 10) | (mask_p[35] << 8)
399 | (mask_p[34] << 6) | (mask_p[33] << 4)
400 | (mask_p[32] << 2) | (mask_p[31] << 0);
401 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
402 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
403
404 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
405 | (mask_p[59] << 26) | (mask_p[58] << 24)
406 | (mask_p[57] << 22) | (mask_p[56] << 20)
407 | (mask_p[55] << 18) | (mask_p[54] << 16)
408 | (mask_p[53] << 14) | (mask_p[52] << 12)
409 | (mask_p[51] << 10) | (mask_p[50] << 8)
410 | (mask_p[49] << 6) | (mask_p[48] << 4)
411 | (mask_p[47] << 2) | (mask_p[46] << 0);
412 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
413 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
414}
415
416static void ar9002_olc_init(struct ath_hw *ah)
417{
418 u32 i;
419
420 if (!OLC_FOR_AR9280_20_LATER)
421 return;
422
423 if (OLC_FOR_AR9287_10_LATER) {
424 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
425 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
426 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
427 AR9287_AN_TXPC0_TXPCMODE,
428 AR9287_AN_TXPC0_TXPCMODE_S,
429 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
430 udelay(100);
431 } else {
432 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
433 ah->originalGain[i] =
434 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
435 AR_PHY_TX_GAIN);
436 ah->PDADCdelta = 0;
437 }
438}
439
440void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
441{
442 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
443
444 priv_ops->set_rf_regs = NULL;
445 priv_ops->rf_alloc_ext_banks = NULL;
446 priv_ops->rf_free_ext_banks = NULL;
447 priv_ops->rf_set_freq = ar9002_hw_set_channel;
448 priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
449 priv_ops->olc_init = ar9002_olc_init;
450}
diff --git a/drivers/net/wireless/ath/ath9k/ar9002_phy.h b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
new file mode 100644
index 000000000000..4fe204ed3a7c
--- /dev/null
+++ b/drivers/net/wireless/ath/ath9k/ar9002_phy.h
@@ -0,0 +1,581 @@
1/*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16#ifndef AR9002_PHY_H
17#define AR9002_PHY_H
18
19#define AR_PHY_TEST 0x9800
20#define PHY_AGC_CLR 0x10000000
21#define RFSILENT_BB 0x00002000
22
23#define AR_PHY_TURBO 0x9804
24#define AR_PHY_FC_TURBO_MODE 0x00000001
25#define AR_PHY_FC_TURBO_SHORT 0x00000002
26#define AR_PHY_FC_DYN2040_EN 0x00000004
27#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
28#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
29/* For 25 MHz channel spacing -- not used but supported by hw */
30#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
31#define AR_PHY_FC_HT_EN 0x00000040
32#define AR_PHY_FC_SHORT_GI_40 0x00000080
33#define AR_PHY_FC_WALSH 0x00000100
34#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
35#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
36
37#define AR_PHY_TEST2 0x9808
38
39#define AR_PHY_TIMING2 0x9810
40#define AR_PHY_TIMING3 0x9814
41#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
42#define AR_PHY_TIMING3_DSC_MAN_S 17
43#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
44#define AR_PHY_TIMING3_DSC_EXP_S 13
45
46#define AR_PHY_CHIP_ID_REV_0 0x80
47#define AR_PHY_CHIP_ID_REV_1 0x81
48#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
49
50#define AR_PHY_ACTIVE 0x981C
51#define AR_PHY_ACTIVE_EN 0x00000001
52#define AR_PHY_ACTIVE_DIS 0x00000000
53
54#define AR_PHY_RF_CTL2 0x9824
55#define AR_PHY_TX_END_DATA_START 0x000000FF
56#define AR_PHY_TX_END_DATA_START_S 0
57#define AR_PHY_TX_END_PA_ON 0x0000FF00
58#define AR_PHY_TX_END_PA_ON_S 8
59
60#define AR_PHY_RF_CTL3 0x9828
61#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
62#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
63
64#define AR_PHY_ADC_CTL 0x982C
65#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
66#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
67#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
68#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
69#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
70#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
71#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
72
73#define AR_PHY_ADC_SERIAL_CTL 0x9830
74#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
75#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
76
77#define AR_PHY_RF_CTL4 0x9834
78#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
79#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
80#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
81#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
82#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
83#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
84#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
85#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
86
87#define AR_PHY_TSTDAC_CONST 0x983c
88
89#define AR_PHY_SETTLING 0x9844
90#define AR_PHY_SETTLING_SWITCH 0x00003F80
91#define AR_PHY_SETTLING_SWITCH_S 7
92
93#define AR_PHY_RXGAIN 0x9848
94#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
95#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
96#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
97#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
98#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
99#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
100#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
101#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
102
103#define AR_PHY_DESIRED_SZ 0x9850
104#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
105#define AR_PHY_DESIRED_SZ_ADC_S 0
106#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
107#define AR_PHY_DESIRED_SZ_PGA_S 8
108#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
109#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
110
111#define AR_PHY_FIND_SIG 0x9858
112#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
113#define AR_PHY_FIND_SIG_FIRSTEP_S 12
114#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
115#define AR_PHY_FIND_SIG_FIRPWR_S 18
116
117#define AR_PHY_AGC_CTL1 0x985C
118#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
119#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
120#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
121#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
122
123#define AR_PHY_AGC_CONTROL 0x9860
124#define AR_PHY_AGC_CONTROL_CAL 0x00000001
125#define AR_PHY_AGC_CONTROL_NF 0x00000002
126#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
127#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
128#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
129
130#define AR_PHY_CCA 0x9864
131#define AR_PHY_MINCCA_PWR 0x0FF80000
132#define AR_PHY_MINCCA_PWR_S 19
133#define AR_PHY_CCA_THRESH62 0x0007F000
134#define AR_PHY_CCA_THRESH62_S 12
135#define AR9280_PHY_MINCCA_PWR 0x1FF00000
136#define AR9280_PHY_MINCCA_PWR_S 20
137#define AR9280_PHY_CCA_THRESH62 0x000FF000
138#define AR9280_PHY_CCA_THRESH62_S 12
139
140#define AR_PHY_SFCORR_LOW 0x986C
141#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
142#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
143#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
144#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
145#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
146#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
147#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
148
149#define AR_PHY_SFCORR 0x9868
150#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
151#define AR_PHY_SFCORR_M2COUNT_THR_S 0
152#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
153#define AR_PHY_SFCORR_M1_THRESH_S 17
154#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
155#define AR_PHY_SFCORR_M2_THRESH_S 24
156
157#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
158#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
159#define AR_PHY_SYNTH_CONTROL 0x9874
160#define AR_PHY_SLEEP_SCAL 0x9878
161
162#define AR_PHY_PLL_CTL 0x987c
163#define AR_PHY_PLL_CTL_40 0xaa
164#define AR_PHY_PLL_CTL_40_5413 0x04
165#define AR_PHY_PLL_CTL_44 0xab
166#define AR_PHY_PLL_CTL_44_2133 0xeb
167#define AR_PHY_PLL_CTL_40_2133 0xea
168
169#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
170#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
171#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
172#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
173#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
174#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
175#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
176#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
177#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
178#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
179#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
180#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
181#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
182#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
183
184#define AR_PHY_RX_DELAY 0x9914
185#define AR_PHY_SEARCH_START_DELAY 0x9918
186#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
187
188#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
189#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
190#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
191#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
192#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
193#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
194#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
195#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
196#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
197
198#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
199#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
200#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
201#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
202
203#define AR_PHY_TIMING5 0x9924
204#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
205#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
206
207#define AR_PHY_POWER_TX_RATE1 0x9934
208#define AR_PHY_POWER_TX_RATE2 0x9938
209#define AR_PHY_POWER_TX_RATE_MAX 0x993c
210#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
211
212#define AR_PHY_FRAME_CTL 0x9944
213#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
214#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
215
216#define AR_PHY_TXPWRADJ 0x994C
217#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
218#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
219#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
220#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
221
222#define AR_PHY_RADAR_EXT 0x9940
223#define AR_PHY_RADAR_EXT_ENA 0x00004000
224
225#define AR_PHY_RADAR_0 0x9954
226#define AR_PHY_RADAR_0_ENA 0x00000001
227#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
228#define AR_PHY_RADAR_0_INBAND 0x0000003e
229#define AR_PHY_RADAR_0_INBAND_S 1
230#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
231#define AR_PHY_RADAR_0_PRSSI_S 6
232#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
233#define AR_PHY_RADAR_0_HEIGHT_S 12
234#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
235#define AR_PHY_RADAR_0_RRSSI_S 18
236#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
237#define AR_PHY_RADAR_0_FIRPWR_S 24
238
239#define AR_PHY_RADAR_1 0x9958
240#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
241#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
242#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
243#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
244#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
245#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
246#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
247#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
248#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
249#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
250#define AR_PHY_RADAR_1_MAXLEN_S 0
251
252#define AR_PHY_SWITCH_CHAIN_0 0x9960
253#define AR_PHY_SWITCH_COM 0x9964
254
255#define AR_PHY_SIGMA_DELTA 0x996C
256#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
257#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
258#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
259#define AR_PHY_SIGMA_DELTA_FILT2_S 3
260#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
261#define AR_PHY_SIGMA_DELTA_FILT1_S 8
262#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
263#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
264
265#define AR_PHY_RESTART 0x9970
266#define AR_PHY_RESTART_DIV_GC 0x001C0000
267#define AR_PHY_RESTART_DIV_GC_S 18
268
269#define AR_PHY_RFBUS_REQ 0x997C
270#define AR_PHY_RFBUS_REQ_EN 0x00000001
271
272#define AR_PHY_TIMING7 0x9980
273#define AR_PHY_TIMING8 0x9984
274#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
275#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
276
277#define AR_PHY_BIN_MASK2_1 0x9988
278#define AR_PHY_BIN_MASK2_2 0x998c
279#define AR_PHY_BIN_MASK2_3 0x9990
280#define AR_PHY_BIN_MASK2_4 0x9994
281
282#define AR_PHY_BIN_MASK_1 0x9900
283#define AR_PHY_BIN_MASK_2 0x9904
284#define AR_PHY_BIN_MASK_3 0x9908
285
286#define AR_PHY_MASK_CTL 0x990c
287
288#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
289#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
290
291#define AR_PHY_TIMING9 0x9998
292#define AR_PHY_TIMING10 0x999c
293#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
294#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
295
296#define AR_PHY_TIMING11 0x99a0
297#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
298#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
299#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
300#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
301#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
302#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
303
304#define AR_PHY_RX_CHAINMASK 0x99a4
305#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
306#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
307#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
308
309#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
310#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
311#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
312#define AR_PHY_9285_ANT_DIV_CTL_S 24
313#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
314#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
315#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
316#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
317#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
318#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
319#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
320#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
321#define AR_PHY_9285_ANT_DIV_LNA1 2
322#define AR_PHY_9285_ANT_DIV_LNA2 1
323#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
324#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
325#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
326#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
327
328#define AR_PHY_EXT_CCA0 0x99b8
329#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
330#define AR_PHY_EXT_CCA0_THRESH62_S 0
331
332#define AR_PHY_EXT_CCA 0x99bc
333#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
334#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
335#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
336#define AR_PHY_EXT_CCA_THRESH62_S 16
337#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
338#define AR_PHY_EXT_MINCCA_PWR_S 23
339#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
340#define AR9280_PHY_EXT_MINCCA_PWR_S 16
341
342#define AR_PHY_SFCORR_EXT 0x99c0
343#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
344#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
345#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
346#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
347#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
348#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
349#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
350#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
351#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
352
353#define AR_PHY_HALFGI 0x99D0
354#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
355#define AR_PHY_HALFGI_DSC_MAN_S 4
356#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
357#define AR_PHY_HALFGI_DSC_EXP_S 0
358
359#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
360#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
361
362#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
363
364#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
365#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
366
367#define AR_PHY_M_SLEEP 0x99f0
368#define AR_PHY_REFCLKDLY 0x99f4
369#define AR_PHY_REFCLKPD 0x99f8
370
371#define AR_PHY_CALMODE 0x99f0
372
373#define AR_PHY_CALMODE_IQ 0x00000000
374#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
375#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
376#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
377
378#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
379#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
380#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
381#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
382
383#define AR_PHY_CURRENT_RSSI 0x9c1c
384#define AR9280_PHY_CURRENT_RSSI 0x9c3c
385
386#define AR_PHY_RFBUS_GRANT 0x9C20
387#define AR_PHY_RFBUS_GRANT_EN 0x00000001
388
389#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
390#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
391
392#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
393
394#define AR_PHY_MODE 0xA200
395#define AR_PHY_MODE_ASYNCFIFO 0x80
396#define AR_PHY_MODE_AR2133 0x08
397#define AR_PHY_MODE_AR5111 0x00
398#define AR_PHY_MODE_AR5112 0x08
399#define AR_PHY_MODE_DYNAMIC 0x04
400#define AR_PHY_MODE_RF2GHZ 0x02
401#define AR_PHY_MODE_RF5GHZ 0x00
402#define AR_PHY_MODE_CCK 0x01
403#define AR_PHY_MODE_OFDM 0x00
404#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
405
406#define AR_PHY_CCK_TX_CTRL 0xA204
407#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
408#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
409#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
410
411#define AR_PHY_CCK_DETECT 0xA208
412#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
413#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
414/* [12:6] settling time for antenna switch */
415#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
416#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
417#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
418#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
419
420#define AR_PHY_GAIN_2GHZ 0xA20C
421#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
422#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
423#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
424#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
425#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
426#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
427
428#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
429#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
430#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
431#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
432#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
433#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
434#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
435#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
436
437#define AR_PHY_CCK_RXCTRL4 0xA21C
438#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
439#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
440
441#define AR_PHY_DAG_CTRLCCK 0xA228
442#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
443#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
444#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
445
446#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
447#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
448
449#define AR_PHY_POWER_TX_RATE3 0xA234
450#define AR_PHY_POWER_TX_RATE4 0xA238
451
452#define AR_PHY_SCRM_SEQ_XR 0xA23C
453#define AR_PHY_HEADER_DETECT_XR 0xA240
454#define AR_PHY_CHIRP_DETECTED_XR 0xA244
455#define AR_PHY_BLUETOOTH 0xA254
456
457#define AR_PHY_TPCRG1 0xA258
458#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
459#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
460
461#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
462#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
463#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
464#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
465#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
466#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
467
468#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
469#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
470
471#define AR_PHY_TX_PWRCTRL4 0xa264
472#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
473#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
474#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
475#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
476
477#define AR_PHY_TX_PWRCTRL6_0 0xa270
478#define AR_PHY_TX_PWRCTRL6_1 0xb270
479#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
480#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
481
482#define AR_PHY_TX_PWRCTRL7 0xa274
483#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
484#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
485
486#define AR_PHY_TX_PWRCTRL9 0xa27C
487#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
488#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
489#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
490#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
491
492#define AR_PHY_TX_GAIN_TBL1 0xa300
493#define AR_PHY_TX_GAIN 0x0007F000
494#define AR_PHY_TX_GAIN_S 12
495
496#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
497#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
498#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
499#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
500
501#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
502#define AR_PHY_MASK2_M_31_45 0xa3a4
503#define AR_PHY_MASK2_M_16_30 0xa3a8
504#define AR_PHY_MASK2_M_00_15 0xa3ac
505#define AR_PHY_MASK2_P_15_01 0xa3b8
506#define AR_PHY_MASK2_P_30_16 0xa3bc
507#define AR_PHY_MASK2_P_45_31 0xa3c0
508#define AR_PHY_MASK2_P_61_45 0xa3c4
509#define AR_PHY_SPUR_REG 0x994c
510
511#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
512#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
513
514#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
515#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
516#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
517#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
518#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
519#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
520
521#define AR_PHY_PILOT_MASK_01_30 0xa3b0
522#define AR_PHY_PILOT_MASK_31_60 0xa3b4
523
524#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
525#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
526
527#define AR_PHY_ANALOG_SWAP 0xa268
528#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
529
530#define AR_PHY_TPCRG5 0xA26C
531#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
532#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
533#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
534#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
535#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
536#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
537#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
538#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
539#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
540#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
541
542/* Carrier leak calibration control, do it after AGC calibration */
543#define AR_PHY_CL_CAL_CTL 0xA358
544#define AR_PHY_CL_CAL_ENABLE 0x00000002
545#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
546
547#define AR_PHY_POWER_TX_RATE5 0xA38C
548#define AR_PHY_POWER_TX_RATE6 0xA390
549
550#define AR_PHY_CAL_CHAINMASK 0xA39C
551
552#define AR_PHY_POWER_TX_SUB 0xA3C8
553#define AR_PHY_POWER_TX_RATE7 0xA3CC
554#define AR_PHY_POWER_TX_RATE8 0xA3D0
555#define AR_PHY_POWER_TX_RATE9 0xA3D4
556
557#define AR_PHY_XPA_CFG 0xA3D8
558#define AR_PHY_FORCE_XPA_CFG 0x000000001
559#define AR_PHY_FORCE_XPA_CFG_S 0
560
561#define AR_PHY_CH1_CCA 0xa864
562#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
563#define AR_PHY_CH1_MINCCA_PWR_S 19
564#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
565#define AR9280_PHY_CH1_MINCCA_PWR_S 20
566
567#define AR_PHY_CH2_CCA 0xb864
568#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
569#define AR_PHY_CH2_MINCCA_PWR_S 19
570
571#define AR_PHY_CH1_EXT_CCA 0xa9bc
572#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
573#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
574#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
575#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
576
577#define AR_PHY_CH2_EXT_CCA 0xb9bc
578#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
579#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
580
581#endif
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 064f5b51dfcd..eba85adb7cd3 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "hw.h" 17#include "hw.h"
18#include "ar9002_phy.h"
18 19
19/* We can tune this as we go by monitoring really low values */ 20/* We can tune this as we go by monitoring really low values */
20#define ATH9K_NF_TOO_LOW -60 21#define ATH9K_NF_TOO_LOW -60
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index 0354fe50f8e0..97279a5e01e8 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "hw.h" 17#include "hw.h"
18#include "ar9002_phy.h"
18 19
19static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah) 20static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
20{ 21{
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index d8ca94c3fa0c..e57c5b48c039 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "hw.h" 17#include "hw.h"
18#include "ar9002_phy.h"
18 19
19static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah) 20static int ath9k_hw_AR9287_get_eeprom_ver(struct ath_hw *ah)
20{ 21{
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index 404a0341242c..99f16a3a5be8 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#include "hw.h" 17#include "hw.h"
18#include "ar9002_phy.h"
18 19
19static void ath9k_get_txgain_index(struct ath_hw *ah, 20static void ath9k_get_txgain_index(struct ath_hw *ah,
20 struct ath9k_channel *chan, 21 struct ath9k_channel *chan,
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
index ee33146cda15..81f3d03f0dbf 100644
--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
@@ -28,4 +28,117 @@ static inline void ath9k_hw_configpcipowersave(struct ath_hw *ah,
28 ath9k_hw_ops(ah)->config_pci_powersave(ah, restore, power_off); 28 ath9k_hw_ops(ah)->config_pci_powersave(ah, restore, power_off);
29} 29}
30 30
31/* Private hardware call ops */
32
33/* PHY ops */
34
35static inline int ath9k_hw_rf_set_freq(struct ath_hw *ah,
36 struct ath9k_channel *chan)
37{
38 return ath9k_hw_private_ops(ah)->rf_set_freq(ah, chan);
39}
40
41static inline void ath9k_hw_spur_mitigate_freq(struct ath_hw *ah,
42 struct ath9k_channel *chan)
43{
44 ath9k_hw_private_ops(ah)->spur_mitigate_freq(ah, chan);
45}
46
47static inline int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah)
48{
49 if (!ath9k_hw_private_ops(ah)->rf_alloc_ext_banks)
50 return 0;
51
52 return ath9k_hw_private_ops(ah)->rf_alloc_ext_banks(ah);
53}
54
55static inline void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah)
56{
57 if (!ath9k_hw_private_ops(ah)->rf_free_ext_banks)
58 return;
59
60 ath9k_hw_private_ops(ah)->rf_free_ext_banks(ah);
61}
62
63static inline bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
64 struct ath9k_channel *chan,
65 u16 modesIndex)
66{
67 if (!ath9k_hw_private_ops(ah)->set_rf_regs)
68 return true;
69
70 return ath9k_hw_private_ops(ah)->set_rf_regs(ah, chan, modesIndex);
71}
72
73static inline void ath9k_hw_init_bb(struct ath_hw *ah,
74 struct ath9k_channel *chan)
75{
76 return ath9k_hw_private_ops(ah)->init_bb(ah, chan);
77}
78
79static inline void ath9k_hw_set_channel_regs(struct ath_hw *ah,
80 struct ath9k_channel *chan)
81{
82 return ath9k_hw_private_ops(ah)->set_channel_regs(ah, chan);
83}
84
85static inline int ath9k_hw_process_ini(struct ath_hw *ah,
86 struct ath9k_channel *chan)
87{
88 return ath9k_hw_private_ops(ah)->process_ini(ah, chan);
89}
90
91static inline void ath9k_olc_init(struct ath_hw *ah)
92{
93 if (!ath9k_hw_private_ops(ah)->olc_init)
94 return;
95
96 return ath9k_hw_private_ops(ah)->olc_init(ah);
97}
98
99static inline void ath9k_hw_set_rfmode(struct ath_hw *ah,
100 struct ath9k_channel *chan)
101{
102 return ath9k_hw_private_ops(ah)->set_rfmode(ah, chan);
103}
104
105static inline void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
106{
107 return ath9k_hw_private_ops(ah)->mark_phy_inactive(ah);
108}
109
110static inline void ath9k_hw_set_delta_slope(struct ath_hw *ah,
111 struct ath9k_channel *chan)
112{
113 return ath9k_hw_private_ops(ah)->set_delta_slope(ah, chan);
114}
115
116static inline bool ath9k_hw_rfbus_req(struct ath_hw *ah)
117{
118 return ath9k_hw_private_ops(ah)->rfbus_req(ah);
119}
120
121static inline void ath9k_hw_rfbus_done(struct ath_hw *ah)
122{
123 return ath9k_hw_private_ops(ah)->rfbus_done(ah);
124}
125
126static inline void ath9k_enable_rfkill(struct ath_hw *ah)
127{
128 return ath9k_hw_private_ops(ah)->enable_rfkill(ah);
129}
130
131static inline void ath9k_hw_restore_chainmask(struct ath_hw *ah)
132{
133 if (!ath9k_hw_private_ops(ah)->restore_chainmask)
134 return;
135
136 return ath9k_hw_private_ops(ah)->restore_chainmask(ah);
137}
138
139static inline void ath9k_hw_set_diversity(struct ath_hw *ah, bool value)
140{
141 return ath9k_hw_private_ops(ah)->set_diversity(ah, value);
142}
143
31#endif /* ATH9K_HW_OPS_H */ 144#endif /* ATH9K_HW_OPS_H */
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 6f447cdbd05c..2ab061381fcf 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -29,7 +29,6 @@
29static void ar9002_hw_attach_ops(struct ath_hw *ah); 29static void ar9002_hw_attach_ops(struct ath_hw *ah);
30 30
31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type); 31static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
33 32
34MODULE_AUTHOR("Atheros Communications"); 33MODULE_AUTHOR("Atheros Communications");
35MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards."); 34MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
@@ -535,14 +534,12 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
535 ah->eep_ops->get_eeprom_ver(ah), 534 ah->eep_ops->get_eeprom_ver(ah),
536 ah->eep_ops->get_eeprom_rev(ah)); 535 ah->eep_ops->get_eeprom_rev(ah));
537 536
538 if (!AR_SREV_9280_10_OR_LATER(ah)) { 537 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
539 ecode = ath9k_hw_rf_alloc_ext_banks(ah); 538 if (ecode) {
540 if (ecode) { 539 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
541 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL, 540 "Failed allocating banks for "
542 "Failed allocating banks for " 541 "external radio\n");
543 "external radio\n"); 542 return ecode;
544 return ecode;
545 }
546 } 543 }
547 544
548 if (!AR_SREV_9100(ah)) { 545 if (!AR_SREV_9100(ah)) {
@@ -913,20 +910,12 @@ static int __ath9k_hw_init(struct ath_hw *ah)
913 if (AR_SREV_9271(ah)) 910 if (AR_SREV_9271(ah))
914 ah->is_pciexpress = false; 911 ah->is_pciexpress = false;
915 912
916 /* XXX: move this to its own hw op */
917 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID); 913 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
918
919 ath9k_hw_init_cal_settings(ah); 914 ath9k_hw_init_cal_settings(ah);
920 915
921 ah->ani_function = ATH9K_ANI_ALL; 916 ah->ani_function = ATH9K_ANI_ALL;
922 if (AR_SREV_9280_10_OR_LATER(ah)) { 917 if (AR_SREV_9280_10_OR_LATER(ah))
923 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL; 918 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
924 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
925 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
926 } else {
927 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
928 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
929 }
930 919
931 ath9k_hw_init_mode_regs(ah); 920 ath9k_hw_init_mode_regs(ah);
932 921
@@ -1014,22 +1003,6 @@ int ath9k_hw_init(struct ath_hw *ah)
1014} 1003}
1015EXPORT_SYMBOL(ath9k_hw_init); 1004EXPORT_SYMBOL(ath9k_hw_init);
1016 1005
1017static void ath9k_hw_init_bb(struct ath_hw *ah,
1018 struct ath9k_channel *chan)
1019{
1020 u32 synthDelay;
1021
1022 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1023 if (IS_CHAN_B(chan))
1024 synthDelay = (4 * synthDelay) / 22;
1025 else
1026 synthDelay /= 10;
1027
1028 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1029
1030 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1031}
1032
1033static void ath9k_hw_init_qos(struct ath_hw *ah) 1006static void ath9k_hw_init_qos(struct ath_hw *ah)
1034{ 1007{
1035 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa); 1008 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
@@ -1121,43 +1094,6 @@ static void ath9k_hw_init_pll(struct ath_hw *ah,
1121 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK); 1094 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1122} 1095}
1123 1096
1124static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1125{
1126 int rx_chainmask, tx_chainmask;
1127
1128 rx_chainmask = ah->rxchainmask;
1129 tx_chainmask = ah->txchainmask;
1130
1131 switch (rx_chainmask) {
1132 case 0x5:
1133 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1134 AR_PHY_SWAP_ALT_CHAIN);
1135 case 0x3:
1136 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1137 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1138 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1139 break;
1140 }
1141 case 0x1:
1142 case 0x2:
1143 case 0x7:
1144 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1145 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1146 break;
1147 default:
1148 break;
1149 }
1150
1151 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1152 if (tx_chainmask == 0x5) {
1153 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1154 AR_PHY_SWAP_ALT_CHAIN);
1155 }
1156 if (AR_SREV_9100(ah))
1157 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1158 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1159}
1160
1161static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, 1097static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1162 enum nl80211_iftype opmode) 1098 enum nl80211_iftype opmode)
1163{ 1099{
@@ -1277,8 +1213,7 @@ void ath9k_hw_deinit(struct ath_hw *ah)
1277 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP); 1213 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1278 1214
1279free_hw: 1215free_hw:
1280 if (!AR_SREV_9280_10_OR_LATER(ah)) 1216 ath9k_hw_rf_free_ext_banks(ah);
1281 ath9k_hw_rf_free_ext_banks(ah);
1282} 1217}
1283EXPORT_SYMBOL(ath9k_hw_deinit); 1218EXPORT_SYMBOL(ath9k_hw_deinit);
1284 1219
@@ -1286,73 +1221,7 @@ EXPORT_SYMBOL(ath9k_hw_deinit);
1286/* INI */ 1221/* INI */
1287/*******/ 1222/*******/
1288 1223
1289static void ath9k_hw_override_ini(struct ath_hw *ah, 1224u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1290 struct ath9k_channel *chan)
1291{
1292 u32 val;
1293
1294 /*
1295 * Set the RX_ABORT and RX_DIS and clear if off only after
1296 * RXE is set for MAC. This prevents frames with corrupted
1297 * descriptor status.
1298 */
1299 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1300
1301 if (AR_SREV_9280_10_OR_LATER(ah)) {
1302 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1303
1304 if (!AR_SREV_9271(ah))
1305 val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1306
1307 if (AR_SREV_9287_10_OR_LATER(ah))
1308 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1309
1310 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1311 }
1312
1313 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1314 AR_SREV_9280_10_OR_LATER(ah))
1315 return;
1316 /*
1317 * Disable BB clock gating
1318 * Necessary to avoid issues on AR5416 2.0
1319 */
1320 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1321
1322 /*
1323 * Disable RIFS search on some chips to avoid baseband
1324 * hang issues.
1325 */
1326 if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1327 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1328 val &= ~AR_PHY_RIFS_INIT_DELAY;
1329 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1330 }
1331}
1332
1333static void ath9k_olc_init(struct ath_hw *ah)
1334{
1335 u32 i;
1336
1337 if (OLC_FOR_AR9287_10_LATER) {
1338 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1339 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1340 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1341 AR9287_AN_TXPC0_TXPCMODE,
1342 AR9287_AN_TXPC0_TXPCMODE_S,
1343 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1344 udelay(100);
1345 } else {
1346 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1347 ah->originalGain[i] =
1348 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1349 AR_PHY_TX_GAIN);
1350 ah->PDADCdelta = 0;
1351 }
1352}
1353
1354static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1355 struct ath9k_channel *chan)
1356{ 1225{
1357 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band); 1226 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1358 1227
@@ -1366,184 +1235,10 @@ static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1366 return ctl; 1235 return ctl;
1367} 1236}
1368 1237
1369static int ath9k_hw_process_ini(struct ath_hw *ah,
1370 struct ath9k_channel *chan)
1371{
1372 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1373 int i, regWrites = 0;
1374 struct ieee80211_channel *channel = chan->chan;
1375 u32 modesIndex, freqIndex;
1376
1377 switch (chan->chanmode) {
1378 case CHANNEL_A:
1379 case CHANNEL_A_HT20:
1380 modesIndex = 1;
1381 freqIndex = 1;
1382 break;
1383 case CHANNEL_A_HT40PLUS:
1384 case CHANNEL_A_HT40MINUS:
1385 modesIndex = 2;
1386 freqIndex = 1;
1387 break;
1388 case CHANNEL_G:
1389 case CHANNEL_G_HT20:
1390 case CHANNEL_B:
1391 modesIndex = 4;
1392 freqIndex = 2;
1393 break;
1394 case CHANNEL_G_HT40PLUS:
1395 case CHANNEL_G_HT40MINUS:
1396 modesIndex = 3;
1397 freqIndex = 2;
1398 break;
1399
1400 default:
1401 return -EINVAL;
1402 }
1403
1404 /* Set correct baseband to analog shift setting to access analog chips */
1405 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1406
1407 /* Write ADDAC shifts */
1408 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1409 ah->eep_ops->set_addac(ah, chan);
1410
1411 if (AR_SREV_5416_22_OR_LATER(ah)) {
1412 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1413 } else {
1414 struct ar5416IniArray temp;
1415 u32 addacSize =
1416 sizeof(u32) * ah->iniAddac.ia_rows *
1417 ah->iniAddac.ia_columns;
1418
1419 /* For AR5416 2.0/2.1 */
1420 memcpy(ah->addac5416_21,
1421 ah->iniAddac.ia_array, addacSize);
1422
1423 /* override CLKDRV value at [row, column] = [31, 1] */
1424 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1425
1426 temp.ia_array = ah->addac5416_21;
1427 temp.ia_columns = ah->iniAddac.ia_columns;
1428 temp.ia_rows = ah->iniAddac.ia_rows;
1429 REG_WRITE_ARRAY(&temp, 1, regWrites);
1430 }
1431
1432 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1433
1434 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1435 u32 reg = INI_RA(&ah->iniModes, i, 0);
1436 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1437
1438 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
1439 val &= ~AR_AN_TOP2_PWDCLKIND;
1440
1441 REG_WRITE(ah, reg, val);
1442
1443 if (reg >= 0x7800 && reg < 0x78a0
1444 && ah->config.analog_shiftreg) {
1445 udelay(100);
1446 }
1447
1448 DO_DELAY(regWrites);
1449 }
1450
1451 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1452 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1453
1454 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1455 AR_SREV_9287_10_OR_LATER(ah))
1456 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1457
1458 if (AR_SREV_9271_10(ah))
1459 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1460 modesIndex, regWrites);
1461
1462 /* Write common array parameters */
1463 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1464 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1465 u32 val = INI_RA(&ah->iniCommon, i, 1);
1466
1467 REG_WRITE(ah, reg, val);
1468
1469 if (reg >= 0x7800 && reg < 0x78a0
1470 && ah->config.analog_shiftreg) {
1471 udelay(100);
1472 }
1473
1474 DO_DELAY(regWrites);
1475 }
1476
1477 if (AR_SREV_9271(ah)) {
1478 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1479 REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1480 modesIndex, regWrites);
1481 else
1482 REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1483 modesIndex, regWrites);
1484 }
1485
1486 REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
1487
1488 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1489 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1490 regWrites);
1491 }
1492
1493 ath9k_hw_override_ini(ah, chan);
1494 ath9k_hw_set_regs(ah, chan);
1495 ath9k_hw_init_chain_masks(ah);
1496
1497 if (OLC_FOR_AR9280_20_LATER)
1498 ath9k_olc_init(ah);
1499
1500 /* Set TX power */
1501 ah->eep_ops->set_txpower(ah, chan,
1502 ath9k_regd_get_ctl(regulatory, chan),
1503 channel->max_antenna_gain * 2,
1504 channel->max_power * 2,
1505 min((u32) MAX_RATE_POWER,
1506 (u32) regulatory->power_limit));
1507
1508 /* Write analog registers */
1509 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1510 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1511 "ar5416SetRfRegs failed\n");
1512 return -EIO;
1513 }
1514
1515 return 0;
1516}
1517
1518/****************************************/ 1238/****************************************/
1519/* Reset and Channel Switching Routines */ 1239/* Reset and Channel Switching Routines */
1520/****************************************/ 1240/****************************************/
1521 1241
1522static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1523{
1524 u32 rfMode = 0;
1525
1526 if (chan == NULL)
1527 return;
1528
1529 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1530 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1531
1532 if (!AR_SREV_9280_10_OR_LATER(ah))
1533 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1534 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1535
1536 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1537 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1538
1539 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1540}
1541
1542static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1543{
1544 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1545}
1546
1547static inline void ath9k_hw_set_dma(struct ath_hw *ah) 1242static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1548{ 1243{
1549 u32 regval; 1244 u32 regval;
@@ -1620,10 +1315,8 @@ static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1620 } 1315 }
1621} 1316}
1622 1317
1623static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, 1318void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1624 u32 coef_scaled, 1319 u32 *coef_mantissa, u32 *coef_exponent)
1625 u32 *coef_mantissa,
1626 u32 *coef_exponent)
1627{ 1320{
1628 u32 coef_exp, coef_man; 1321 u32 coef_exp, coef_man;
1629 1322
@@ -1639,40 +1332,6 @@ static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1639 *coef_exponent = coef_exp - 16; 1332 *coef_exponent = coef_exp - 16;
1640} 1333}
1641 1334
1642static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1643 struct ath9k_channel *chan)
1644{
1645 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1646 u32 clockMhzScaled = 0x64000000;
1647 struct chan_centers centers;
1648
1649 if (IS_CHAN_HALF_RATE(chan))
1650 clockMhzScaled = clockMhzScaled >> 1;
1651 else if (IS_CHAN_QUARTER_RATE(chan))
1652 clockMhzScaled = clockMhzScaled >> 2;
1653
1654 ath9k_hw_get_channel_centers(ah, chan, &centers);
1655 coef_scaled = clockMhzScaled / centers.synth_center;
1656
1657 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1658 &ds_coef_exp);
1659
1660 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1661 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1662 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1663 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1664
1665 coef_scaled = (9 * coef_scaled) / 10;
1666
1667 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1668 &ds_coef_exp);
1669
1670 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1671 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1672 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1673 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1674}
1675
1676static bool ath9k_hw_set_reset(struct ath_hw *ah, int type) 1335static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1677{ 1336{
1678 u32 rst_flags; 1337 u32 rst_flags;
@@ -1779,34 +1438,6 @@ static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1779 } 1438 }
1780} 1439}
1781 1440
1782static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1783{
1784 u32 phymode;
1785 u32 enableDacFifo = 0;
1786
1787 if (AR_SREV_9285_10_OR_LATER(ah))
1788 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1789 AR_PHY_FC_ENABLE_DAC_FIFO);
1790
1791 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1792 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1793
1794 if (IS_CHAN_HT40(chan)) {
1795 phymode |= AR_PHY_FC_DYN2040_EN;
1796
1797 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1798 (chan->chanmode == CHANNEL_G_HT40PLUS))
1799 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1800
1801 }
1802 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1803
1804 ath9k_hw_set11nmac2040(ah);
1805
1806 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1807 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1808}
1809
1810static bool ath9k_hw_chip_reset(struct ath_hw *ah, 1441static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1811 struct ath9k_channel *chan) 1442 struct ath9k_channel *chan)
1812{ 1443{
@@ -1832,7 +1463,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1832 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah); 1463 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1833 struct ath_common *common = ath9k_hw_common(ah); 1464 struct ath_common *common = ath9k_hw_common(ah);
1834 struct ieee80211_channel *channel = chan->chan; 1465 struct ieee80211_channel *channel = chan->chan;
1835 u32 synthDelay, qnum; 1466 u32 qnum;
1836 int r; 1467 int r;
1837 1468
1838 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1469 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
@@ -1844,17 +1475,15 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1844 } 1475 }
1845 } 1476 }
1846 1477
1847 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1478 if (!ath9k_hw_rfbus_req(ah)) {
1848 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1849 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1850 ath_print(common, ATH_DBG_FATAL, 1479 ath_print(common, ATH_DBG_FATAL,
1851 "Could not kill baseband RX\n"); 1480 "Could not kill baseband RX\n");
1852 return false; 1481 return false;
1853 } 1482 }
1854 1483
1855 ath9k_hw_set_regs(ah, chan); 1484 ath9k_hw_set_channel_regs(ah, chan);
1856 1485
1857 r = ah->ath9k_hw_rf_set_freq(ah, chan); 1486 r = ath9k_hw_rf_set_freq(ah, chan);
1858 if (r) { 1487 if (r) {
1859 ath_print(common, ATH_DBG_FATAL, 1488 ath_print(common, ATH_DBG_FATAL,
1860 "Failed to set channel\n"); 1489 "Failed to set channel\n");
@@ -1868,20 +1497,12 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1868 min((u32) MAX_RATE_POWER, 1497 min((u32) MAX_RATE_POWER,
1869 (u32) regulatory->power_limit)); 1498 (u32) regulatory->power_limit));
1870 1499
1871 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY; 1500 ath9k_hw_rfbus_done(ah);
1872 if (IS_CHAN_B(chan))
1873 synthDelay = (4 * synthDelay) / 22;
1874 else
1875 synthDelay /= 10;
1876
1877 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1878
1879 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1880 1501
1881 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1502 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1882 ath9k_hw_set_delta_slope(ah, chan); 1503 ath9k_hw_set_delta_slope(ah, chan);
1883 1504
1884 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 1505 ath9k_hw_spur_mitigate_freq(ah, chan);
1885 1506
1886 if (!chan->oneTimeCalsDone) 1507 if (!chan->oneTimeCalsDone)
1887 chan->oneTimeCalsDone = true; 1508 chan->oneTimeCalsDone = true;
@@ -1889,18 +1510,6 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1889 return true; 1510 return true;
1890} 1511}
1891 1512
1892static void ath9k_enable_rfkill(struct ath_hw *ah)
1893{
1894 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1895 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1896
1897 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1898 AR_GPIO_INPUT_MUX2_RFSILENT);
1899
1900 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1901 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1902}
1903
1904int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 1513int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1905 bool bChannelChange) 1514 bool bChannelChange)
1906{ 1515{
@@ -1910,7 +1519,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1910 u32 saveDefAntenna; 1519 u32 saveDefAntenna;
1911 u32 macStaId1; 1520 u32 macStaId1;
1912 u64 tsf = 0; 1521 u64 tsf = 0;
1913 int i, rx_chainmask, r; 1522 int i, r;
1914 1523
1915 ah->txchainmask = common->tx_chainmask; 1524 ah->txchainmask = common->tx_chainmask;
1916 ah->rxchainmask = common->rx_chainmask; 1525 ah->rxchainmask = common->rx_chainmask;
@@ -1982,16 +1591,6 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1982 if (AR_SREV_9280_10_OR_LATER(ah)) 1591 if (AR_SREV_9280_10_OR_LATER(ah))
1983 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); 1592 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1984 1593
1985 if (AR_SREV_9287_12_OR_LATER(ah)) {
1986 /* Enable ASYNC FIFO */
1987 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1988 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
1989 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
1990 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1991 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1992 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
1993 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
1994 }
1995 r = ath9k_hw_process_ini(ah, chan); 1594 r = ath9k_hw_process_ini(ah, chan);
1996 if (r) 1595 if (r)
1997 return r; 1596 return r;
@@ -2016,7 +1615,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2016 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan)) 1615 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2017 ath9k_hw_set_delta_slope(ah, chan); 1616 ath9k_hw_set_delta_slope(ah, chan);
2018 1617
2019 ah->ath9k_hw_spur_mitigate_freq(ah, chan); 1618 ath9k_hw_spur_mitigate_freq(ah, chan);
2020 ah->eep_ops->set_board_values(ah, chan); 1619 ah->eep_ops->set_board_values(ah, chan);
2021 1620
2022 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 1621 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
@@ -2038,7 +1637,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2038 1637
2039 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR); 1638 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2040 1639
2041 r = ah->ath9k_hw_rf_set_freq(ah, chan); 1640 r = ath9k_hw_rf_set_freq(ah, chan);
2042 if (r) 1641 if (r)
2043 return r; 1642 return r;
2044 1643
@@ -2095,12 +1694,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2095 if (!ath9k_hw_init_cal(ah, chan)) 1694 if (!ath9k_hw_init_cal(ah, chan))
2096 return -EIO; 1695 return -EIO;
2097 1696
2098 rx_chainmask = ah->rxchainmask; 1697 ath9k_hw_restore_chainmask(ah);
2099 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2100 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2101 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2102 }
2103
2104 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ); 1698 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2105 1699
2106 /* 1700 /*
@@ -3322,10 +2916,6 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3322 case ATH9K_CAP_TKIP_SPLIT: 2916 case ATH9K_CAP_TKIP_SPLIT:
3323 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ? 2917 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3324 false : true; 2918 false : true;
3325 case ATH9K_CAP_DIVERSITY:
3326 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3327 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3328 true : false;
3329 case ATH9K_CAP_MCAST_KEYSRCH: 2919 case ATH9K_CAP_MCAST_KEYSRCH:
3330 switch (capability) { 2920 switch (capability) {
3331 case 0: 2921 case 0:
@@ -3368,8 +2958,6 @@ EXPORT_SYMBOL(ath9k_hw_getcapability);
3368bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 2958bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3369 u32 capability, u32 setting, int *status) 2959 u32 capability, u32 setting, int *status)
3370{ 2960{
3371 u32 v;
3372
3373 switch (type) { 2961 switch (type) {
3374 case ATH9K_CAP_TKIP_MIC: 2962 case ATH9K_CAP_TKIP_MIC:
3375 if (setting) 2963 if (setting)
@@ -3379,14 +2967,6 @@ bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3379 ah->sta_id1_defaults &= 2967 ah->sta_id1_defaults &=
3380 ~AR_STA_ID1_CRPT_MIC_ENABLE; 2968 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3381 return true; 2969 return true;
3382 case ATH9K_CAP_DIVERSITY:
3383 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3384 if (setting)
3385 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3386 else
3387 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3388 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3389 return true;
3390 case ATH9K_CAP_MCAST_KEYSRCH: 2970 case ATH9K_CAP_MCAST_KEYSRCH:
3391 if (setting) 2971 if (setting)
3392 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH; 2972 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
@@ -3981,4 +3561,9 @@ static void ar9002_hw_attach_ops(struct ath_hw *ah)
3981 priv_ops->macversion_supported = ar9002_hw_macversion_supported; 3561 priv_ops->macversion_supported = ar9002_hw_macversion_supported;
3982 3562
3983 ops->config_pci_powersave = ar9002_hw_configpcipowersave; 3563 ops->config_pci_powersave = ar9002_hw_configpcipowersave;
3564
3565 if (AR_SREV_9280_10_OR_LATER(ah))
3566 ar9002_hw_attach_phy_ops(ah);
3567 else
3568 ar5008_hw_attach_phy_ops(ah);
3984} 3569}
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index dfe8502866bb..d740e9cc721c 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -171,7 +171,6 @@ enum ath9k_capability_type {
171 ATH9K_CAP_CIPHER = 0, 171 ATH9K_CAP_CIPHER = 0,
172 ATH9K_CAP_TKIP_MIC, 172 ATH9K_CAP_TKIP_MIC,
173 ATH9K_CAP_TKIP_SPLIT, 173 ATH9K_CAP_TKIP_SPLIT,
174 ATH9K_CAP_DIVERSITY,
175 ATH9K_CAP_TXPOW, 174 ATH9K_CAP_TXPOW,
176 ATH9K_CAP_MCAST_KEYSRCH, 175 ATH9K_CAP_MCAST_KEYSRCH,
177 ATH9K_CAP_DS 176 ATH9K_CAP_DS
@@ -449,11 +448,41 @@ struct ath_gen_timer_table {
449 * @init_cal_settings: Initializes calibration settings 448 * @init_cal_settings: Initializes calibration settings
450 * @init_mode_regs: Initializes mode registers 449 * @init_mode_regs: Initializes mode registers
451 * @macversion_supported: If this specific mac revision is supported 450 * @macversion_supported: If this specific mac revision is supported
451 *
452 * @rf_set_freq: change frequency
453 * @spur_mitigate_freq: spur mitigation
454 * @rf_alloc_ext_banks:
455 * @rf_free_ext_banks:
456 * @set_rf_regs:
452 */ 457 */
453struct ath_hw_private_ops { 458struct ath_hw_private_ops {
454 void (*init_cal_settings)(struct ath_hw *ah); 459 void (*init_cal_settings)(struct ath_hw *ah);
455 void (*init_mode_regs)(struct ath_hw *ah); 460 void (*init_mode_regs)(struct ath_hw *ah);
456 bool (*macversion_supported)(u32 macversion); 461 bool (*macversion_supported)(u32 macversion);
462
463 /* PHY ops */
464 int (*rf_set_freq)(struct ath_hw *ah,
465 struct ath9k_channel *chan);
466 void (*spur_mitigate_freq)(struct ath_hw *ah,
467 struct ath9k_channel *chan);
468 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
469 void (*rf_free_ext_banks)(struct ath_hw *ah);
470 bool (*set_rf_regs)(struct ath_hw *ah,
471 struct ath9k_channel *chan,
472 u16 modesIndex);
473 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
474 void (*init_bb)(struct ath_hw *ah,
475 struct ath9k_channel *chan);
476 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
477 void (*olc_init)(struct ath_hw *ah);
478 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
479 void (*mark_phy_inactive)(struct ath_hw *ah);
480 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
481 bool (*rfbus_req)(struct ath_hw *ah);
482 void (*rfbus_done)(struct ath_hw *ah);
483 void (*enable_rfkill)(struct ath_hw *ah);
484 void (*restore_chainmask)(struct ath_hw *ah);
485 void (*set_diversity)(struct ath_hw *ah, bool value);
457}; 486};
458 487
459/** 488/**
@@ -563,13 +592,6 @@ struct ath_hw {
563 DONT_USE_32KHZ, 592 DONT_USE_32KHZ,
564 } enable_32kHz_clock; 593 } enable_32kHz_clock;
565 594
566 /* Callback for radio frequency change */
567 int (*ath9k_hw_rf_set_freq)(struct ath_hw *ah, struct ath9k_channel *chan);
568
569 /* Callback for baseband spur frequency */
570 void (*ath9k_hw_spur_mitigate_freq)(struct ath_hw *ah,
571 struct ath9k_channel *chan);
572
573 /* Private to hardware code */ 595 /* Private to hardware code */
574 struct ath_hw_private_ops private_ops; 596 struct ath_hw_private_ops private_ops;
575 /* Accessed by the lower level driver */ 597 /* Accessed by the lower level driver */
@@ -675,6 +697,7 @@ bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
675 u32 capability, u32 *result); 697 u32 capability, u32 *result);
676bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type, 698bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
677 u32 capability, u32 setting, int *status); 699 u32 capability, u32 setting, int *status);
700u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
678 701
679/* Key Cache Management */ 702/* Key Cache Management */
680bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry); 703bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
@@ -752,6 +775,13 @@ void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
752/* HTC */ 775/* HTC */
753void ath9k_hw_htc_resetinit(struct ath_hw *ah); 776void ath9k_hw_htc_resetinit(struct ath_hw *ah);
754 777
778/* PHY */
779void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
780 u32 *coef_mantissa, u32 *coef_exponent);
781
782void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
783void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
784
755#define ATH_PCIE_CAP_LINK_CTRL 0x70 785#define ATH_PCIE_CAP_LINK_CTRL 0x70
756#define ATH_PCIE_CAP_LINK_L0S 1 786#define ATH_PCIE_CAP_LINK_L0S 1
757#define ATH_PCIE_CAP_LINK_L1 2 787#define ATH_PCIE_CAP_LINK_L1 2
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index 62682cc2e216..1956c611503e 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -512,7 +512,7 @@ static void ath9k_init_misc(struct ath_softc *sc)
512 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask; 512 common->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
513 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask; 513 common->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
514 514
515 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_DIVERSITY, 1, true, NULL); 515 ath9k_hw_set_diversity(sc->sc_ah, true);
516 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah); 516 sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
517 517
518 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) 518 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
diff --git a/drivers/net/wireless/ath/ath9k/phy.h b/drivers/net/wireless/ath/ath9k/phy.h
index 4b6e494bd984..b90815205a14 100644
--- a/drivers/net/wireless/ath/ath9k/phy.h
+++ b/drivers/net/wireless/ath/ath9k/phy.h
@@ -17,501 +17,11 @@
17#ifndef PHY_H 17#ifndef PHY_H
18#define PHY_H 18#define PHY_H
19 19
20/* Single chip radio settings */
21int ath9k_hw_ar9280_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
22void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
23
24/* Routines below are for non single-chip solutions */
25int ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan);
26void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
27
28int ath9k_hw_rf_alloc_ext_banks(struct ath_hw *ah);
29void ath9k_hw_rf_free_ext_banks(struct ath_hw *ah);
30
31bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
32 struct ath9k_channel *chan,
33 u16 modesIndex);
34
35#define AR_PHY_BASE 0x9800 20#define AR_PHY_BASE 0x9800
36#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2)) 21#define AR_PHY(_n) (AR_PHY_BASE + ((_n)<<2))
37 22
38#define AR_PHY_TEST 0x9800
39#define PHY_AGC_CLR 0x10000000
40#define RFSILENT_BB 0x00002000
41
42#define AR_PHY_TURBO 0x9804
43#define AR_PHY_FC_TURBO_MODE 0x00000001
44#define AR_PHY_FC_TURBO_SHORT 0x00000002
45#define AR_PHY_FC_DYN2040_EN 0x00000004
46#define AR_PHY_FC_DYN2040_PRI_ONLY 0x00000008
47#define AR_PHY_FC_DYN2040_PRI_CH 0x00000010
48/* For 25 MHz channel spacing -- not used but supported by hw */
49#define AR_PHY_FC_DYN2040_EXT_CH 0x00000020
50#define AR_PHY_FC_HT_EN 0x00000040
51#define AR_PHY_FC_SHORT_GI_40 0x00000080
52#define AR_PHY_FC_WALSH 0x00000100
53#define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200
54#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800
55
56#define AR_PHY_TEST2 0x9808
57
58#define AR_PHY_TIMING2 0x9810
59#define AR_PHY_TIMING3 0x9814
60#define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
61#define AR_PHY_TIMING3_DSC_MAN_S 17
62#define AR_PHY_TIMING3_DSC_EXP 0x0001E000
63#define AR_PHY_TIMING3_DSC_EXP_S 13
64
65#define AR_PHY_CHIP_ID 0x9818
66#define AR_PHY_CHIP_ID_REV_0 0x80
67#define AR_PHY_CHIP_ID_REV_1 0x81
68#define AR_PHY_CHIP_ID_9160_REV_0 0xb0
69
70#define AR_PHY_ACTIVE 0x981C
71#define AR_PHY_ACTIVE_EN 0x00000001
72#define AR_PHY_ACTIVE_DIS 0x00000000
73
74#define AR_PHY_RF_CTL2 0x9824
75#define AR_PHY_TX_END_DATA_START 0x000000FF
76#define AR_PHY_TX_END_DATA_START_S 0
77#define AR_PHY_TX_END_PA_ON 0x0000FF00
78#define AR_PHY_TX_END_PA_ON_S 8
79
80#define AR_PHY_RF_CTL3 0x9828
81#define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
82#define AR_PHY_TX_END_TO_A2_RX_ON_S 16
83
84#define AR_PHY_ADC_CTL 0x982C
85#define AR_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
86#define AR_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
87#define AR_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
88#define AR_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
89#define AR_PHY_ADC_CTL_OFF_PWDADC 0x00008000
90#define AR_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
91#define AR_PHY_ADC_CTL_ON_INBUFGAIN_S 16
92
93#define AR_PHY_ADC_SERIAL_CTL 0x9830
94#define AR_PHY_SEL_INTERNAL_ADDAC 0x00000000
95#define AR_PHY_SEL_EXTERNAL_RADIO 0x00000001
96
97#define AR_PHY_RF_CTL4 0x9834
98#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF 0xFF000000
99#define AR_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
100#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00FF0000
101#define AR_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
102#define AR_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000FF00
103#define AR_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
104#define AR_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000FF
105#define AR_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
106
107#define AR_PHY_TSTDAC_CONST 0x983c
108
109#define AR_PHY_SETTLING 0x9844
110#define AR_PHY_SETTLING_SWITCH 0x00003F80
111#define AR_PHY_SETTLING_SWITCH_S 7
112
113#define AR_PHY_RXGAIN 0x9848
114#define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
115#define AR_PHY_RXGAIN_TXRX_ATTEN_S 12
116#define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
117#define AR_PHY_RXGAIN_TXRX_RF_MAX_S 18
118#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
119#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7
120#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
121#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14
122
123#define AR_PHY_DESIRED_SZ 0x9850
124#define AR_PHY_DESIRED_SZ_ADC 0x000000FF
125#define AR_PHY_DESIRED_SZ_ADC_S 0
126#define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
127#define AR_PHY_DESIRED_SZ_PGA_S 8
128#define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
129#define AR_PHY_DESIRED_SZ_TOT_DES_S 20
130
131#define AR_PHY_FIND_SIG 0x9858
132#define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
133#define AR_PHY_FIND_SIG_FIRSTEP_S 12
134#define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
135#define AR_PHY_FIND_SIG_FIRPWR_S 18
136
137#define AR_PHY_AGC_CTL1 0x985C
138#define AR_PHY_AGC_CTL1_COARSE_LOW 0x00007F80
139#define AR_PHY_AGC_CTL1_COARSE_LOW_S 7
140#define AR_PHY_AGC_CTL1_COARSE_HIGH 0x003F8000
141#define AR_PHY_AGC_CTL1_COARSE_HIGH_S 15
142
143#define AR_PHY_AGC_CONTROL 0x9860
144#define AR_PHY_AGC_CONTROL_CAL 0x00000001
145#define AR_PHY_AGC_CONTROL_NF 0x00000002
146#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
147#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
148#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
149
150#define AR_PHY_CCA 0x9864
151#define AR_PHY_MINCCA_PWR 0x0FF80000
152#define AR_PHY_MINCCA_PWR_S 19
153#define AR_PHY_CCA_THRESH62 0x0007F000
154#define AR_PHY_CCA_THRESH62_S 12
155#define AR9280_PHY_MINCCA_PWR 0x1FF00000
156#define AR9280_PHY_MINCCA_PWR_S 20
157#define AR9280_PHY_CCA_THRESH62 0x000FF000
158#define AR9280_PHY_CCA_THRESH62_S 12
159
160#define AR_PHY_SFCORR_LOW 0x986C
161#define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
162#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
163#define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
164#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
165#define AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
166#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
167#define AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
168
169#define AR_PHY_SFCORR 0x9868
170#define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
171#define AR_PHY_SFCORR_M2COUNT_THR_S 0
172#define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
173#define AR_PHY_SFCORR_M1_THRESH_S 17
174#define AR_PHY_SFCORR_M2_THRESH 0x7F000000
175#define AR_PHY_SFCORR_M2_THRESH_S 24
176
177#define AR_PHY_SLEEP_CTR_CONTROL 0x9870
178#define AR_PHY_SLEEP_CTR_LIMIT 0x9874
179#define AR_PHY_SYNTH_CONTROL 0x9874
180#define AR_PHY_SLEEP_SCAL 0x9878
181
182#define AR_PHY_PLL_CTL 0x987c
183#define AR_PHY_PLL_CTL_40 0xaa
184#define AR_PHY_PLL_CTL_40_5413 0x04
185#define AR_PHY_PLL_CTL_44 0xab
186#define AR_PHY_PLL_CTL_44_2133 0xeb
187#define AR_PHY_PLL_CTL_40_2133 0xea
188
189#define AR_PHY_SPECTRAL_SCAN 0x9910 /* AR9280 spectral scan configuration register */
190#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
191#define AR_PHY_SPECTRAL_SCAN_ENA 0x00000001 /* Enable spectral scan, reg 68, bit 0 */
192#define AR_PHY_SPECTRAL_SCAN_ENA_S 0 /* Enable spectral scan, reg 68, bit 0 */
193#define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002 /* Activate spectral scan reg 68, bit 1*/
194#define AR_PHY_SPECTRAL_SCAN_ACTIVE_S 1 /* Activate spectral scan reg 68, bit 1*/
195#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0 /* Interval for FFT reports, reg 68, bits 4-7*/
196#define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD_S 4
197#define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00 /* Interval for FFT reports, reg 68, bits 8-15*/
198#define AR_PHY_SPECTRAL_SCAN_PERIOD_S 8
199#define AR_PHY_SPECTRAL_SCAN_COUNT 0x00FF0000 /* Number of reports, reg 68, bits 16-23*/
200#define AR_PHY_SPECTRAL_SCAN_COUNT_S 16
201#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x01000000 /* Short repeat, reg 68, bit 24*/
202#define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT_S 24 /* Short repeat, reg 68, bit 24*/
203
204#define AR_PHY_RX_DELAY 0x9914
205#define AR_PHY_SEARCH_START_DELAY 0x9918
206#define AR_PHY_RX_DELAY_DELAY 0x00003FFF
207
208#define AR_PHY_TIMING_CTRL4(_i) (0x9920 + ((_i) << 12))
209#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F
210#define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
211#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7E0
212#define AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
213#define AR_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
214#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xF000
215#define AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
216#define AR_PHY_TIMING_CTRL4_DO_CAL 0x10000
217
218#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
219#define AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
220#define AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
221#define AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
222
223#define AR_PHY_TIMING5 0x9924
224#define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
225#define AR_PHY_TIMING5_CYCPWR_THR1_S 1
226
227#define AR_PHY_POWER_TX_RATE1 0x9934
228#define AR_PHY_POWER_TX_RATE2 0x9938
229#define AR_PHY_POWER_TX_RATE_MAX 0x993c
230#define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
231
232#define AR_PHY_FRAME_CTL 0x9944
233#define AR_PHY_FRAME_CTL_TX_CLIP 0x00000038
234#define AR_PHY_FRAME_CTL_TX_CLIP_S 3
235
236#define AR_PHY_TXPWRADJ 0x994C
237#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA 0x00000FC0
238#define AR_PHY_TXPWRADJ_CCK_GAIN_DELTA_S 6
239#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX 0x00FC0000
240#define AR_PHY_TXPWRADJ_CCK_PCDAC_INDEX_S 18
241
242#define AR_PHY_RADAR_EXT 0x9940
243#define AR_PHY_RADAR_EXT_ENA 0x00004000
244
245#define AR_PHY_RADAR_0 0x9954
246#define AR_PHY_RADAR_0_ENA 0x00000001
247#define AR_PHY_RADAR_0_FFT_ENA 0x80000000
248#define AR_PHY_RADAR_0_INBAND 0x0000003e
249#define AR_PHY_RADAR_0_INBAND_S 1
250#define AR_PHY_RADAR_0_PRSSI 0x00000FC0
251#define AR_PHY_RADAR_0_PRSSI_S 6
252#define AR_PHY_RADAR_0_HEIGHT 0x0003F000
253#define AR_PHY_RADAR_0_HEIGHT_S 12
254#define AR_PHY_RADAR_0_RRSSI 0x00FC0000
255#define AR_PHY_RADAR_0_RRSSI_S 18
256#define AR_PHY_RADAR_0_FIRPWR 0x7F000000
257#define AR_PHY_RADAR_0_FIRPWR_S 24
258
259#define AR_PHY_RADAR_1 0x9958
260#define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
261#define AR_PHY_RADAR_1_USE_FIR128 0x00400000
262#define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
263#define AR_PHY_RADAR_1_RELPWR_THRESH_S 16
264#define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
265#define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
266#define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
267#define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
268#define AR_PHY_RADAR_1_RELSTEP_THRESH_S 8
269#define AR_PHY_RADAR_1_MAXLEN 0x000000FF
270#define AR_PHY_RADAR_1_MAXLEN_S 0
271
272#define AR_PHY_SWITCH_CHAIN_0 0x9960
273#define AR_PHY_SWITCH_COM 0x9964
274
275#define AR_PHY_SIGMA_DELTA 0x996C
276#define AR_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
277#define AR_PHY_SIGMA_DELTA_ADC_SEL_S 0
278#define AR_PHY_SIGMA_DELTA_FILT2 0x000000F8
279#define AR_PHY_SIGMA_DELTA_FILT2_S 3
280#define AR_PHY_SIGMA_DELTA_FILT1 0x00001F00
281#define AR_PHY_SIGMA_DELTA_FILT1_S 8
282#define AR_PHY_SIGMA_DELTA_ADC_CLIP 0x01FFE000
283#define AR_PHY_SIGMA_DELTA_ADC_CLIP_S 13
284
285#define AR_PHY_RESTART 0x9970
286#define AR_PHY_RESTART_DIV_GC 0x001C0000
287#define AR_PHY_RESTART_DIV_GC_S 18
288
289#define AR_PHY_RFBUS_REQ 0x997C
290#define AR_PHY_RFBUS_REQ_EN 0x00000001
291
292#define AR_PHY_TIMING7 0x9980
293#define AR_PHY_TIMING8 0x9984
294#define AR_PHY_TIMING8_PILOT_MASK_2 0x000FFFFF
295#define AR_PHY_TIMING8_PILOT_MASK_2_S 0
296
297#define AR_PHY_BIN_MASK2_1 0x9988
298#define AR_PHY_BIN_MASK2_2 0x998c
299#define AR_PHY_BIN_MASK2_3 0x9990
300#define AR_PHY_BIN_MASK2_4 0x9994
301
302#define AR_PHY_BIN_MASK_1 0x9900
303#define AR_PHY_BIN_MASK_2 0x9904
304#define AR_PHY_BIN_MASK_3 0x9908
305
306#define AR_PHY_MASK_CTL 0x990c
307
308#define AR_PHY_BIN_MASK2_4_MASK_4 0x00003FFF
309#define AR_PHY_BIN_MASK2_4_MASK_4_S 0
310
311#define AR_PHY_TIMING9 0x9998
312#define AR_PHY_TIMING10 0x999c
313#define AR_PHY_TIMING10_PILOT_MASK_2 0x000FFFFF
314#define AR_PHY_TIMING10_PILOT_MASK_2_S 0
315
316#define AR_PHY_TIMING11 0x99a0
317#define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
318#define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
319#define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
320#define AR_PHY_TIMING11_SPUR_FREQ_SD_S 20
321#define AR_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
322#define AR_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
323
324#define AR_PHY_RX_CHAINMASK 0x99a4
325#define AR_PHY_NEW_ADC_DC_GAIN_CORR(_i) (0x99b4 + ((_i) << 12))
326#define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
327#define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
328
329#define AR_PHY_MULTICHAIN_GAIN_CTL 0x99ac
330#define AR_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
331#define AR_PHY_9285_ANT_DIV_CTL 0x01000000
332#define AR_PHY_9285_ANT_DIV_CTL_S 24
333#define AR_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
334#define AR_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
335#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
336#define AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
337#define AR_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
338#define AR_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
339#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
340#define AR_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
341#define AR_PHY_9285_ANT_DIV_LNA1 2
342#define AR_PHY_9285_ANT_DIV_LNA2 1
343#define AR_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
344#define AR_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
345#define AR_PHY_9285_ANT_DIV_GAINTB_0 0
346#define AR_PHY_9285_ANT_DIV_GAINTB_1 1
347
348#define AR_PHY_EXT_CCA0 0x99b8
349#define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
350#define AR_PHY_EXT_CCA0_THRESH62_S 0
351
352#define AR_PHY_EXT_CCA 0x99bc
353#define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00
354#define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9
355#define AR_PHY_EXT_CCA_THRESH62 0x007F0000
356#define AR_PHY_EXT_CCA_THRESH62_S 16
357#define AR_PHY_EXT_MINCCA_PWR 0xFF800000
358#define AR_PHY_EXT_MINCCA_PWR_S 23
359#define AR9280_PHY_EXT_MINCCA_PWR 0x01FF0000
360#define AR9280_PHY_EXT_MINCCA_PWR_S 16
361
362#define AR_PHY_SFCORR_EXT 0x99c0
363#define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
364#define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
365#define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
366#define AR_PHY_SFCORR_EXT_M2_THRESH_S 7
367#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
368#define AR_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
369#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
370#define AR_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
371#define AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
372
373#define AR_PHY_HALFGI 0x99D0
374#define AR_PHY_HALFGI_DSC_MAN 0x0007FFF0
375#define AR_PHY_HALFGI_DSC_MAN_S 4
376#define AR_PHY_HALFGI_DSC_EXP 0x0000000F
377#define AR_PHY_HALFGI_DSC_EXP_S 0
378
379#define AR_PHY_CHAN_INFO_MEMORY 0x99DC
380#define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
381
382#define AR_PHY_HEAVY_CLIP_ENABLE 0x99E0
383
384#define AR_PHY_HEAVY_CLIP_FACTOR_RIFS 0x99EC
385#define AR_PHY_RIFS_INIT_DELAY 0x03ff0000
386
387#define AR_PHY_M_SLEEP 0x99f0
388#define AR_PHY_REFCLKDLY 0x99f4
389#define AR_PHY_REFCLKPD 0x99f8
390
391#define AR_PHY_CALMODE 0x99f0
392
393#define AR_PHY_CALMODE_IQ 0x00000000
394#define AR_PHY_CALMODE_ADC_GAIN 0x00000001
395#define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
396#define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
397
398#define AR_PHY_CAL_MEAS_0(_i) (0x9c10 + ((_i) << 12))
399#define AR_PHY_CAL_MEAS_1(_i) (0x9c14 + ((_i) << 12))
400#define AR_PHY_CAL_MEAS_2(_i) (0x9c18 + ((_i) << 12))
401#define AR_PHY_CAL_MEAS_3(_i) (0x9c1c + ((_i) << 12))
402
403#define AR_PHY_CURRENT_RSSI 0x9c1c
404#define AR9280_PHY_CURRENT_RSSI 0x9c3c
405
406#define AR_PHY_RFBUS_GRANT 0x9C20
407#define AR_PHY_RFBUS_GRANT_EN 0x00000001
408
409#define AR_PHY_CHAN_INFO_GAIN_DIFF 0x9CF4
410#define AR_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
411
412#define AR_PHY_CHAN_INFO_GAIN 0x9CFC
413
414#define AR_PHY_MODE 0xA200
415#define AR_PHY_MODE_ASYNCFIFO 0x80
416#define AR_PHY_MODE_AR2133 0x08
417#define AR_PHY_MODE_AR5111 0x00
418#define AR_PHY_MODE_AR5112 0x08
419#define AR_PHY_MODE_DYNAMIC 0x04
420#define AR_PHY_MODE_RF2GHZ 0x02
421#define AR_PHY_MODE_RF5GHZ 0x00
422#define AR_PHY_MODE_CCK 0x01
423#define AR_PHY_MODE_OFDM 0x00
424#define AR_PHY_MODE_DYN_CCK_DISABLE 0x100
425
426#define AR_PHY_CCK_TX_CTRL 0xA204
427#define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
428#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000C
429#define AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
430
431#define AR_PHY_CCK_DETECT 0xA208
432#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
433#define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
434/* [12:6] settling time for antenna switch */
435#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
436#define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
437#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
438#define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
439
440#define AR_PHY_GAIN_2GHZ 0xA20C
441#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00FC0000
442#define AR_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
443#define AR_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003C00
444#define AR_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
445#define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F
446#define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
447
448#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000
449#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
450#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000
451#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
452#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0
453#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
454#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F
455#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
456
457#define AR_PHY_CCK_RXCTRL4 0xA21C
458#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01F80000
459#define AR_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
460
461#define AR_PHY_DAG_CTRLCCK 0xA228
462#define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
463#define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
464#define AR_PHY_DAG_CTRLCCK_RSSI_THR_S 10
465
466#define AR_PHY_FORCE_CLKEN_CCK 0xA22C
467#define AR_PHY_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
468
469#define AR_PHY_POWER_TX_RATE3 0xA234
470#define AR_PHY_POWER_TX_RATE4 0xA238
471
472#define AR_PHY_SCRM_SEQ_XR 0xA23C
473#define AR_PHY_HEADER_DETECT_XR 0xA240
474#define AR_PHY_CHIRP_DETECTED_XR 0xA244
475#define AR_PHY_BLUETOOTH 0xA254
476
477#define AR_PHY_TPCRG1 0xA258
478#define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
479#define AR_PHY_TPCRG1_NUM_PD_GAIN_S 14
480
481#define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
482#define AR_PHY_TPCRG1_PD_GAIN_1_S 16
483#define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
484#define AR_PHY_TPCRG1_PD_GAIN_2_S 18
485#define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
486#define AR_PHY_TPCRG1_PD_GAIN_3_S 20
487
488#define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
489#define AR_PHY_TPCRG1_PD_CAL_ENABLE_S 22
490
491#define AR_PHY_TX_PWRCTRL4 0xa264
492#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
493#define AR_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
494#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001FE
495#define AR_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
496
497#define AR_PHY_TX_PWRCTRL6_0 0xa270
498#define AR_PHY_TX_PWRCTRL6_1 0xb270
499#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
500#define AR_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
501
502#define AR_PHY_TX_PWRCTRL7 0xa274
503#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000 23#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX 0x0007E000
504#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13 24#define AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX_S 13
505#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01F80000
506#define AR_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
507
508#define AR_PHY_TX_PWRCTRL9 0xa27C
509#define AR_PHY_TX_DESIRED_SCALE_CCK 0x00007C00
510#define AR_PHY_TX_DESIRED_SCALE_CCK_S 10
511#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
512#define AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
513
514#define AR_PHY_TX_GAIN_TBL1 0xa300
515#define AR_PHY_TX_GAIN_CLC 0x0000001E 25#define AR_PHY_TX_GAIN_CLC 0x0000001E
516#define AR_PHY_TX_GAIN_CLC_S 1 26#define AR_PHY_TX_GAIN_CLC_S 1
517#define AR_PHY_TX_GAIN 0x0007F000 27#define AR_PHY_TX_GAIN 0x0007F000
@@ -523,91 +33,6 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
523#define AR_PHY_CLC_Q0 0x0000ffd0 33#define AR_PHY_CLC_Q0 0x0000ffd0
524#define AR_PHY_CLC_Q0_S 5 34#define AR_PHY_CLC_Q0_S 5
525 35
526#define AR_PHY_CH0_TX_PWRCTRL11 0xa398
527#define AR_PHY_CH1_TX_PWRCTRL11 0xb398
528#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP 0x0000FC00
529#define AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP_S 10
530
531#define AR_PHY_VIT_MASK2_M_46_61 0xa3a0
532#define AR_PHY_MASK2_M_31_45 0xa3a4
533#define AR_PHY_MASK2_M_16_30 0xa3a8
534#define AR_PHY_MASK2_M_00_15 0xa3ac
535#define AR_PHY_MASK2_P_15_01 0xa3b8
536#define AR_PHY_MASK2_P_30_16 0xa3bc
537#define AR_PHY_MASK2_P_45_31 0xa3c0
538#define AR_PHY_MASK2_P_61_45 0xa3c4
539#define AR_PHY_SPUR_REG 0x994c
540
541#define AR_PHY_SPUR_REG_MASK_RATE_CNTL (0xFF << 18)
542#define AR_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
543
544#define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
545#define AR_PHY_SPUR_REG_MASK_RATE_SELECT (0xFF << 9)
546#define AR_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
547#define AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
548#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7F
549#define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
550
551#define AR_PHY_PILOT_MASK_01_30 0xa3b0
552#define AR_PHY_PILOT_MASK_31_60 0xa3b4
553
554#define AR_PHY_CHANNEL_MASK_01_30 0x99d4
555#define AR_PHY_CHANNEL_MASK_31_60 0x99d8
556
557#define AR_PHY_ANALOG_SWAP 0xa268
558#define AR_PHY_SWAP_ALT_CHAIN 0x00000040
559
560#define AR_PHY_TPCRG5 0xA26C
561#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
562#define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
563#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
564#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
565#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
566#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
567#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
568#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
569#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
570#define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
571
572/* Carrier leak calibration control, do it after AGC calibration */
573#define AR_PHY_CL_CAL_CTL 0xA358
574#define AR_PHY_CL_CAL_ENABLE 0x00000002
575#define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
576
577#define AR_PHY_POWER_TX_RATE5 0xA38C
578#define AR_PHY_POWER_TX_RATE6 0xA390
579
580#define AR_PHY_CAL_CHAINMASK 0xA39C
581
582#define AR_PHY_POWER_TX_SUB 0xA3C8
583#define AR_PHY_POWER_TX_RATE7 0xA3CC
584#define AR_PHY_POWER_TX_RATE8 0xA3D0
585#define AR_PHY_POWER_TX_RATE9 0xA3D4
586
587#define AR_PHY_XPA_CFG 0xA3D8
588#define AR_PHY_FORCE_XPA_CFG 0x000000001
589#define AR_PHY_FORCE_XPA_CFG_S 0
590
591#define AR_PHY_CH1_CCA 0xa864
592#define AR_PHY_CH1_MINCCA_PWR 0x0FF80000
593#define AR_PHY_CH1_MINCCA_PWR_S 19
594#define AR9280_PHY_CH1_MINCCA_PWR 0x1FF00000
595#define AR9280_PHY_CH1_MINCCA_PWR_S 20
596
597#define AR_PHY_CH2_CCA 0xb864
598#define AR_PHY_CH2_MINCCA_PWR 0x0FF80000
599#define AR_PHY_CH2_MINCCA_PWR_S 19
600
601#define AR_PHY_CH1_EXT_CCA 0xa9bc
602#define AR_PHY_CH1_EXT_MINCCA_PWR 0xFF800000
603#define AR_PHY_CH1_EXT_MINCCA_PWR_S 23
604#define AR9280_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
605#define AR9280_PHY_CH1_EXT_MINCCA_PWR_S 16
606
607#define AR_PHY_CH2_EXT_CCA 0xb9bc
608#define AR_PHY_CH2_EXT_MINCCA_PWR 0xFF800000
609#define AR_PHY_CH2_EXT_MINCCA_PWR_S 23
610
611#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \ 36#define REG_WRITE_RF_ARRAY(iniarray, regData, regWr) do { \
612 int r; \ 37 int r; \
613 for (r = 0; r < ((iniarray)->ia_rows); r++) { \ 38 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
@@ -622,6 +47,7 @@ bool ath9k_hw_set_rf_regs(struct ath_hw *ah,
622#define ANTSWAP_AB 0x0001 47#define ANTSWAP_AB 0x0001
623#define REDUCE_CHAIN_0 0x00000050 48#define REDUCE_CHAIN_0 0x00000050
624#define REDUCE_CHAIN_1 0x00000051 49#define REDUCE_CHAIN_1 0x00000051
50#define AR_PHY_CHIP_ID 0x9818
625 51
626#define RF_BANK_SETUP(_bank, _iniarray, _col) do { \ 52#define RF_BANK_SETUP(_bank, _iniarray, _col) do { \
627 int i; \ 53 int i; \
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-12 09:23:35 -0400