diff options
author | Christian Lamparter <chunkeey@web.de> | 2009-03-21 21:36:06 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-03-27 20:13:09 -0400 |
commit | 6cb19353535f9f02fc2a753e3261a255406ba8fa (patch) | |
tree | bc2b398d66759ade10dd80a680e454452d3a7569 /drivers/net/wireless | |
parent | e9348cdd280eb6a1d6d38fef513b578dc9ead363 (diff) |
ar9170: mac/bbp and phy code
MAC/BBP and PHY programming code
Signed-off-by: Christian Lamparter <chunkeey@web.de>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r-- | drivers/net/wireless/ar9170/mac.c | 452 | ||||
-rw-r--r-- | drivers/net/wireless/ar9170/phy.c | 1240 |
2 files changed, 1692 insertions, 0 deletions
diff --git a/drivers/net/wireless/ar9170/mac.c b/drivers/net/wireless/ar9170/mac.c new file mode 100644 index 000000000000..c8fa3073169f --- /dev/null +++ b/drivers/net/wireless/ar9170/mac.c | |||
@@ -0,0 +1,452 @@ | |||
1 | /* | ||
2 | * Atheros AR9170 driver | ||
3 | * | ||
4 | * MAC programming | ||
5 | * | ||
6 | * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; see the file COPYING. If not, see | ||
20 | * http://www.gnu.org/licenses/. | ||
21 | * | ||
22 | * This file incorporates work covered by the following copyright and | ||
23 | * permission notice: | ||
24 | * Copyright (c) 2007-2008 Atheros Communications, Inc. | ||
25 | * | ||
26 | * Permission to use, copy, modify, and/or distribute this software for any | ||
27 | * purpose with or without fee is hereby granted, provided that the above | ||
28 | * copyright notice and this permission notice appear in all copies. | ||
29 | * | ||
30 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
31 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
32 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
33 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
34 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
35 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
36 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
37 | */ | ||
38 | #include "ar9170.h" | ||
39 | #include "cmd.h" | ||
40 | |||
41 | int ar9170_set_qos(struct ar9170 *ar) | ||
42 | { | ||
43 | ar9170_regwrite_begin(ar); | ||
44 | |||
45 | ar9170_regwrite(AR9170_MAC_REG_AC0_CW, ar->edcf[0].cw_min | | ||
46 | (ar->edcf[0].cw_max << 16)); | ||
47 | ar9170_regwrite(AR9170_MAC_REG_AC1_CW, ar->edcf[1].cw_min | | ||
48 | (ar->edcf[1].cw_max << 16)); | ||
49 | ar9170_regwrite(AR9170_MAC_REG_AC2_CW, ar->edcf[2].cw_min | | ||
50 | (ar->edcf[2].cw_max << 16)); | ||
51 | ar9170_regwrite(AR9170_MAC_REG_AC3_CW, ar->edcf[3].cw_min | | ||
52 | (ar->edcf[3].cw_max << 16)); | ||
53 | ar9170_regwrite(AR9170_MAC_REG_AC4_CW, ar->edcf[4].cw_min | | ||
54 | (ar->edcf[4].cw_max << 16)); | ||
55 | |||
56 | ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_AIFS, | ||
57 | ((ar->edcf[0].aifs * 9 + 10)) | | ||
58 | ((ar->edcf[1].aifs * 9 + 10) << 12) | | ||
59 | ((ar->edcf[2].aifs * 9 + 10) << 24)); | ||
60 | ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_AIFS, | ||
61 | ((ar->edcf[2].aifs * 9 + 10) >> 8) | | ||
62 | ((ar->edcf[3].aifs * 9 + 10) << 4) | | ||
63 | ((ar->edcf[4].aifs * 9 + 10) << 16)); | ||
64 | |||
65 | ar9170_regwrite(AR9170_MAC_REG_AC1_AC0_TXOP, | ||
66 | ar->edcf[0].txop | ar->edcf[1].txop << 16); | ||
67 | ar9170_regwrite(AR9170_MAC_REG_AC3_AC2_TXOP, | ||
68 | ar->edcf[1].txop | ar->edcf[3].txop << 16); | ||
69 | |||
70 | ar9170_regwrite_finish(); | ||
71 | |||
72 | return ar9170_regwrite_result(); | ||
73 | } | ||
74 | |||
75 | int ar9170_init_mac(struct ar9170 *ar) | ||
76 | { | ||
77 | ar9170_regwrite_begin(ar); | ||
78 | |||
79 | ar9170_regwrite(AR9170_MAC_REG_ACK_EXTENSION, 0x40); | ||
80 | |||
81 | ar9170_regwrite(AR9170_MAC_REG_RETRY_MAX, 0); | ||
82 | |||
83 | /* enable MMIC */ | ||
84 | ar9170_regwrite(AR9170_MAC_REG_SNIFFER, | ||
85 | AR9170_MAC_REG_SNIFFER_DEFAULTS); | ||
86 | |||
87 | ar9170_regwrite(AR9170_MAC_REG_RX_THRESHOLD, 0xc1f80); | ||
88 | |||
89 | ar9170_regwrite(AR9170_MAC_REG_RX_PE_DELAY, 0x70); | ||
90 | ar9170_regwrite(AR9170_MAC_REG_EIFS_AND_SIFS, 0xa144000); | ||
91 | ar9170_regwrite(AR9170_MAC_REG_SLOT_TIME, 9 << 10); | ||
92 | |||
93 | /* CF-END mode */ | ||
94 | ar9170_regwrite(0x1c3b2c, 0x19000000); | ||
95 | |||
96 | /* NAV protects ACK only (in TXOP) */ | ||
97 | ar9170_regwrite(0x1c3b38, 0x201); | ||
98 | |||
99 | /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */ | ||
100 | /* OTUS set AM to 0x1 */ | ||
101 | ar9170_regwrite(AR9170_MAC_REG_BCN_HT1, 0x8000170); | ||
102 | |||
103 | ar9170_regwrite(AR9170_MAC_REG_BACKOFF_PROTECT, 0x105); | ||
104 | |||
105 | /* AGG test code*/ | ||
106 | /* Aggregation MAX number and timeout */ | ||
107 | ar9170_regwrite(0x1c3b9c, 0x10000a); | ||
108 | |||
109 | ar9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER, | ||
110 | AR9170_MAC_REG_FTF_DEFAULTS); | ||
111 | |||
112 | /* Enable deaggregator, response in sniffer mode */ | ||
113 | ar9170_regwrite(0x1c3c40, 0x1 | 1<<30); | ||
114 | |||
115 | /* rate sets */ | ||
116 | ar9170_regwrite(AR9170_MAC_REG_BASIC_RATE, 0x150f); | ||
117 | ar9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, 0x150f); | ||
118 | ar9170_regwrite(AR9170_MAC_REG_RTS_CTS_RATE, 0x10b01bb); | ||
119 | |||
120 | /* MIMO response control */ | ||
121 | ar9170_regwrite(0x1c3694, 0x4003C1E);/* bit 26~28 otus-AM */ | ||
122 | |||
123 | /* switch MAC to OTUS interface */ | ||
124 | ar9170_regwrite(0x1c3600, 0x3); | ||
125 | |||
126 | ar9170_regwrite(AR9170_MAC_REG_AMPDU_RX_THRESH, 0xffff); | ||
127 | |||
128 | /* set PHY register read timeout (??) */ | ||
129 | ar9170_regwrite(AR9170_MAC_REG_MISC_680, 0xf00008); | ||
130 | |||
131 | /* Disable Rx TimeOut, workaround for BB. */ | ||
132 | ar9170_regwrite(AR9170_MAC_REG_RX_TIMEOUT, 0x0); | ||
133 | |||
134 | /* Set CPU clock frequency to 88/80MHz */ | ||
135 | ar9170_regwrite(AR9170_PWR_REG_CLOCK_SEL, | ||
136 | AR9170_PWR_CLK_AHB_80_88MHZ | | ||
137 | AR9170_PWR_CLK_DAC_160_INV_DLY); | ||
138 | |||
139 | /* Set WLAN DMA interrupt mode: generate int per packet */ | ||
140 | ar9170_regwrite(AR9170_MAC_REG_TXRX_MPI, 0x110011); | ||
141 | |||
142 | ar9170_regwrite(AR9170_MAC_REG_FCS_SELECT, | ||
143 | AR9170_MAC_FCS_FIFO_PROT); | ||
144 | |||
145 | /* Disables the CF_END frame, undocumented register */ | ||
146 | ar9170_regwrite(AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND, | ||
147 | 0x141E0F48); | ||
148 | |||
149 | ar9170_regwrite_finish(); | ||
150 | |||
151 | return ar9170_regwrite_result(); | ||
152 | } | ||
153 | |||
154 | static int ar9170_set_mac_reg(struct ar9170 *ar, const u32 reg, const u8 *mac) | ||
155 | { | ||
156 | static const u8 zero[ETH_ALEN] = { 0 }; | ||
157 | |||
158 | if (!mac) | ||
159 | mac = zero; | ||
160 | |||
161 | ar9170_regwrite_begin(ar); | ||
162 | |||
163 | ar9170_regwrite(reg, | ||
164 | (mac[3] << 24) | (mac[2] << 16) | | ||
165 | (mac[1] << 8) | mac[0]); | ||
166 | |||
167 | ar9170_regwrite(reg + 4, (mac[5] << 8) | mac[4]); | ||
168 | |||
169 | ar9170_regwrite_finish(); | ||
170 | |||
171 | return ar9170_regwrite_result(); | ||
172 | } | ||
173 | |||
174 | int ar9170_update_multicast(struct ar9170 *ar) | ||
175 | { | ||
176 | int err; | ||
177 | |||
178 | ar9170_regwrite_begin(ar); | ||
179 | ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H, | ||
180 | ar->want_mc_hash >> 32); | ||
181 | ar9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L, | ||
182 | ar->want_mc_hash); | ||
183 | |||
184 | ar9170_regwrite_finish(); | ||
185 | err = ar9170_regwrite_result(); | ||
186 | |||
187 | if (err) | ||
188 | return err; | ||
189 | |||
190 | ar->cur_mc_hash = ar->want_mc_hash; | ||
191 | |||
192 | return 0; | ||
193 | } | ||
194 | |||
195 | int ar9170_update_frame_filter(struct ar9170 *ar) | ||
196 | { | ||
197 | int err; | ||
198 | |||
199 | err = ar9170_write_reg(ar, AR9170_MAC_REG_FRAMETYPE_FILTER, | ||
200 | ar->want_filter); | ||
201 | |||
202 | if (err) | ||
203 | return err; | ||
204 | |||
205 | ar->cur_filter = ar->want_filter; | ||
206 | |||
207 | return 0; | ||
208 | } | ||
209 | |||
210 | static int ar9170_set_promiscouous(struct ar9170 *ar) | ||
211 | { | ||
212 | u32 encr_mode, sniffer; | ||
213 | int err; | ||
214 | |||
215 | err = ar9170_read_reg(ar, AR9170_MAC_REG_SNIFFER, &sniffer); | ||
216 | if (err) | ||
217 | return err; | ||
218 | |||
219 | err = ar9170_read_reg(ar, AR9170_MAC_REG_ENCRYPTION, &encr_mode); | ||
220 | if (err) | ||
221 | return err; | ||
222 | |||
223 | if (ar->sniffer_enabled) { | ||
224 | sniffer |= AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC; | ||
225 | |||
226 | /* | ||
227 | * Rx decryption works in place. | ||
228 | * | ||
229 | * If we don't disable it, the hardware will render all | ||
230 | * encrypted frames which are encrypted with an unknown | ||
231 | * key useless. | ||
232 | */ | ||
233 | |||
234 | encr_mode |= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE; | ||
235 | ar->sniffer_enabled = true; | ||
236 | } else { | ||
237 | sniffer &= ~AR9170_MAC_REG_SNIFFER_ENABLE_PROMISC; | ||
238 | |||
239 | if (ar->rx_software_decryption) | ||
240 | encr_mode |= AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE; | ||
241 | else | ||
242 | encr_mode &= ~AR9170_MAC_REG_ENCRYPTION_RX_SOFTWARE; | ||
243 | } | ||
244 | |||
245 | ar9170_regwrite_begin(ar); | ||
246 | ar9170_regwrite(AR9170_MAC_REG_ENCRYPTION, encr_mode); | ||
247 | ar9170_regwrite(AR9170_MAC_REG_SNIFFER, sniffer); | ||
248 | ar9170_regwrite_finish(); | ||
249 | |||
250 | return ar9170_regwrite_result(); | ||
251 | } | ||
252 | |||
253 | int ar9170_set_operating_mode(struct ar9170 *ar) | ||
254 | { | ||
255 | u32 pm_mode = AR9170_MAC_REG_POWERMGT_DEFAULTS; | ||
256 | u8 *mac_addr, *bssid; | ||
257 | int err; | ||
258 | |||
259 | if (ar->vif) { | ||
260 | mac_addr = ar->mac_addr; | ||
261 | bssid = ar->bssid; | ||
262 | |||
263 | switch (ar->vif->type) { | ||
264 | case NL80211_IFTYPE_MESH_POINT: | ||
265 | case NL80211_IFTYPE_ADHOC: | ||
266 | pm_mode |= AR9170_MAC_REG_POWERMGT_IBSS; | ||
267 | break; | ||
268 | /* case NL80211_IFTYPE_AP: | ||
269 | pm_mode |= AR9170_MAC_REG_POWERMGT_AP; | ||
270 | break;*/ | ||
271 | case NL80211_IFTYPE_WDS: | ||
272 | pm_mode |= AR9170_MAC_REG_POWERMGT_AP_WDS; | ||
273 | break; | ||
274 | case NL80211_IFTYPE_MONITOR: | ||
275 | ar->sniffer_enabled = true; | ||
276 | ar->rx_software_decryption = true; | ||
277 | break; | ||
278 | default: | ||
279 | pm_mode |= AR9170_MAC_REG_POWERMGT_STA; | ||
280 | break; | ||
281 | } | ||
282 | } else { | ||
283 | mac_addr = NULL; | ||
284 | bssid = NULL; | ||
285 | } | ||
286 | |||
287 | err = ar9170_set_mac_reg(ar, AR9170_MAC_REG_MAC_ADDR_L, mac_addr); | ||
288 | if (err) | ||
289 | return err; | ||
290 | |||
291 | err = ar9170_set_mac_reg(ar, AR9170_MAC_REG_BSSID_L, bssid); | ||
292 | if (err) | ||
293 | return err; | ||
294 | |||
295 | err = ar9170_set_promiscouous(ar); | ||
296 | if (err) | ||
297 | return err; | ||
298 | |||
299 | ar9170_regwrite_begin(ar); | ||
300 | |||
301 | ar9170_regwrite(AR9170_MAC_REG_POWERMANAGEMENT, pm_mode); | ||
302 | ar9170_regwrite_finish(); | ||
303 | |||
304 | return ar9170_regwrite_result(); | ||
305 | } | ||
306 | |||
307 | int ar9170_set_hwretry_limit(struct ar9170 *ar, unsigned int max_retry) | ||
308 | { | ||
309 | u32 tmp = min_t(u32, 0x33333, max_retry * 0x11111); | ||
310 | |||
311 | return ar9170_write_reg(ar, AR9170_MAC_REG_RETRY_MAX, tmp); | ||
312 | } | ||
313 | |||
314 | int ar9170_set_beacon_timers(struct ar9170 *ar) | ||
315 | { | ||
316 | u32 v = 0; | ||
317 | u32 pretbtt = 0; | ||
318 | |||
319 | v |= ar->hw->conf.beacon_int; | ||
320 | |||
321 | if (ar->vif) { | ||
322 | switch (ar->vif->type) { | ||
323 | case NL80211_IFTYPE_MESH_POINT: | ||
324 | case NL80211_IFTYPE_ADHOC: | ||
325 | v |= BIT(25); | ||
326 | break; | ||
327 | case NL80211_IFTYPE_AP: | ||
328 | v |= BIT(24); | ||
329 | pretbtt = (ar->hw->conf.beacon_int - 6) << 16; | ||
330 | break; | ||
331 | default: | ||
332 | break; | ||
333 | } | ||
334 | |||
335 | v |= ar->vif->bss_conf.dtim_period << 16; | ||
336 | } | ||
337 | |||
338 | ar9170_regwrite_begin(ar); | ||
339 | |||
340 | ar9170_regwrite(AR9170_MAC_REG_PRETBTT, pretbtt); | ||
341 | ar9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, v); | ||
342 | ar9170_regwrite_finish(); | ||
343 | return ar9170_regwrite_result(); | ||
344 | } | ||
345 | |||
346 | int ar9170_update_beacon(struct ar9170 *ar) | ||
347 | { | ||
348 | struct sk_buff *skb; | ||
349 | __le32 *data, *old = NULL; | ||
350 | u32 word; | ||
351 | int i; | ||
352 | |||
353 | skb = ieee80211_beacon_get(ar->hw, ar->vif); | ||
354 | if (!skb) | ||
355 | return -ENOMEM; | ||
356 | |||
357 | data = (__le32 *)skb->data; | ||
358 | if (ar->beacon) | ||
359 | old = (__le32 *)ar->beacon->data; | ||
360 | |||
361 | ar9170_regwrite_begin(ar); | ||
362 | for (i = 0; i < DIV_ROUND_UP(skb->len, 4); i++) { | ||
363 | /* | ||
364 | * XXX: This accesses beyond skb data for up | ||
365 | * to the last 3 bytes!! | ||
366 | */ | ||
367 | |||
368 | if (old && (data[i] == old[i])) | ||
369 | continue; | ||
370 | |||
371 | word = le32_to_cpu(data[i]); | ||
372 | ar9170_regwrite(AR9170_BEACON_BUFFER_ADDRESS + 4 * i, word); | ||
373 | } | ||
374 | |||
375 | /* XXX: use skb->cb info */ | ||
376 | if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ) | ||
377 | ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP, | ||
378 | ((skb->len + 4) << (3+16)) + 0x0400); | ||
379 | else | ||
380 | ar9170_regwrite(AR9170_MAC_REG_BCN_PLCP, | ||
381 | ((skb->len + 4) << (3+16)) + 0x0400); | ||
382 | |||
383 | ar9170_regwrite(AR9170_MAC_REG_BCN_LENGTH, skb->len + 4); | ||
384 | ar9170_regwrite(AR9170_MAC_REG_BCN_ADDR, AR9170_BEACON_BUFFER_ADDRESS); | ||
385 | ar9170_regwrite(AR9170_MAC_REG_BCN_CTRL, 1); | ||
386 | |||
387 | ar9170_regwrite_finish(); | ||
388 | |||
389 | dev_kfree_skb(ar->beacon); | ||
390 | ar->beacon = skb; | ||
391 | |||
392 | return ar9170_regwrite_result(); | ||
393 | } | ||
394 | |||
395 | void ar9170_new_beacon(struct work_struct *work) | ||
396 | { | ||
397 | struct ar9170 *ar = container_of(work, struct ar9170, | ||
398 | beacon_work); | ||
399 | struct sk_buff *skb; | ||
400 | |||
401 | if (unlikely(!IS_STARTED(ar))) | ||
402 | return ; | ||
403 | |||
404 | mutex_lock(&ar->mutex); | ||
405 | |||
406 | if (!ar->vif) | ||
407 | goto out; | ||
408 | |||
409 | ar9170_update_beacon(ar); | ||
410 | |||
411 | rcu_read_lock(); | ||
412 | while ((skb = ieee80211_get_buffered_bc(ar->hw, ar->vif))) | ||
413 | ar9170_op_tx(ar->hw, skb); | ||
414 | |||
415 | rcu_read_unlock(); | ||
416 | |||
417 | out: | ||
418 | mutex_unlock(&ar->mutex); | ||
419 | } | ||
420 | |||
421 | int ar9170_upload_key(struct ar9170 *ar, u8 id, const u8 *mac, u8 ktype, | ||
422 | u8 keyidx, u8 *keydata, int keylen) | ||
423 | { | ||
424 | __le32 vals[7]; | ||
425 | static const u8 bcast[ETH_ALEN] = | ||
426 | { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; | ||
427 | u8 dummy; | ||
428 | |||
429 | mac = mac ? : bcast; | ||
430 | |||
431 | vals[0] = cpu_to_le32((keyidx << 16) + id); | ||
432 | vals[1] = cpu_to_le32(mac[1] << 24 | mac[0] << 16 | ktype); | ||
433 | vals[2] = cpu_to_le32(mac[5] << 24 | mac[4] << 16 | | ||
434 | mac[3] << 8 | mac[2]); | ||
435 | memset(&vals[3], 0, 16); | ||
436 | if (keydata) | ||
437 | memcpy(&vals[3], keydata, keylen); | ||
438 | |||
439 | return ar->exec_cmd(ar, AR9170_CMD_EKEY, | ||
440 | sizeof(vals), (u8 *)vals, | ||
441 | 1, &dummy); | ||
442 | } | ||
443 | |||
444 | int ar9170_disable_key(struct ar9170 *ar, u8 id) | ||
445 | { | ||
446 | __le32 val = cpu_to_le32(id); | ||
447 | u8 dummy; | ||
448 | |||
449 | return ar->exec_cmd(ar, AR9170_CMD_EKEY, | ||
450 | sizeof(val), (u8 *)&val, | ||
451 | 1, &dummy); | ||
452 | } | ||
diff --git a/drivers/net/wireless/ar9170/phy.c b/drivers/net/wireless/ar9170/phy.c new file mode 100644 index 000000000000..6ce20754b8e7 --- /dev/null +++ b/drivers/net/wireless/ar9170/phy.c | |||
@@ -0,0 +1,1240 @@ | |||
1 | /* | ||
2 | * Atheros AR9170 driver | ||
3 | * | ||
4 | * PHY and RF code | ||
5 | * | ||
6 | * Copyright 2008, Johannes Berg <johannes@sipsolutions.net> | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; see the file COPYING. If not, see | ||
20 | * http://www.gnu.org/licenses/. | ||
21 | * | ||
22 | * This file incorporates work covered by the following copyright and | ||
23 | * permission notice: | ||
24 | * Copyright (c) 2007-2008 Atheros Communications, Inc. | ||
25 | * | ||
26 | * Permission to use, copy, modify, and/or distribute this software for any | ||
27 | * purpose with or without fee is hereby granted, provided that the above | ||
28 | * copyright notice and this permission notice appear in all copies. | ||
29 | * | ||
30 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | ||
31 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | ||
32 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | ||
33 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | ||
34 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | ||
35 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | ||
36 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | ||
37 | */ | ||
38 | |||
39 | #include <linux/bitrev.h> | ||
40 | #include "ar9170.h" | ||
41 | #include "cmd.h" | ||
42 | |||
43 | static int ar9170_init_power_cal(struct ar9170 *ar) | ||
44 | { | ||
45 | ar9170_regwrite_begin(ar); | ||
46 | |||
47 | ar9170_regwrite(0x1bc000 + 0x993c, 0x7f); | ||
48 | ar9170_regwrite(0x1bc000 + 0x9934, 0x3f3f3f3f); | ||
49 | ar9170_regwrite(0x1bc000 + 0x9938, 0x3f3f3f3f); | ||
50 | ar9170_regwrite(0x1bc000 + 0xa234, 0x3f3f3f3f); | ||
51 | ar9170_regwrite(0x1bc000 + 0xa238, 0x3f3f3f3f); | ||
52 | ar9170_regwrite(0x1bc000 + 0xa38c, 0x3f3f3f3f); | ||
53 | ar9170_regwrite(0x1bc000 + 0xa390, 0x3f3f3f3f); | ||
54 | ar9170_regwrite(0x1bc000 + 0xa3cc, 0x3f3f3f3f); | ||
55 | ar9170_regwrite(0x1bc000 + 0xa3d0, 0x3f3f3f3f); | ||
56 | ar9170_regwrite(0x1bc000 + 0xa3d4, 0x3f3f3f3f); | ||
57 | |||
58 | ar9170_regwrite_finish(); | ||
59 | return ar9170_regwrite_result(); | ||
60 | } | ||
61 | |||
62 | struct ar9170_phy_init { | ||
63 | u32 reg, _5ghz_20, _5ghz_40, _2ghz_40, _2ghz_20; | ||
64 | }; | ||
65 | |||
66 | static struct ar9170_phy_init ar5416_phy_init[] = { | ||
67 | { 0x1c5800, 0x00000007, 0x00000007, 0x00000007, 0x00000007, }, | ||
68 | { 0x1c5804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, }, | ||
69 | { 0x1c5808, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
70 | { 0x1c580c, 0xad848e19, 0xad848e19, 0xad848e19, 0xad848e19, }, | ||
71 | { 0x1c5810, 0x7d14e000, 0x7d14e000, 0x7d14e000, 0x7d14e000, }, | ||
72 | { 0x1c5814, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, }, | ||
73 | { 0x1c5818, 0x00000090, 0x00000090, 0x00000090, 0x00000090, }, | ||
74 | { 0x1c581c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
75 | { 0x1c5820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, }, | ||
76 | { 0x1c5824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, }, | ||
77 | { 0x1c5828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, }, | ||
78 | { 0x1c582c, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, }, | ||
79 | { 0x1c5830, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
80 | { 0x1c5834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, }, | ||
81 | { 0x1c5838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, }, | ||
82 | { 0x1c583c, 0x00200400, 0x00200400, 0x00200400, 0x00200400, }, | ||
83 | { 0x1c5840, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e, }, | ||
84 | { 0x1c5844, 0x1372161e, 0x13721c1e, 0x13721c24, 0x137216a4, }, | ||
85 | { 0x1c5848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, }, | ||
86 | { 0x1c584c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, }, | ||
87 | { 0x1c5850, 0x6c48b4e4, 0x6c48b4e4, 0x6c48b0e4, 0x6c48b0e4, }, | ||
88 | { 0x1c5854, 0x00000859, 0x00000859, 0x00000859, 0x00000859, }, | ||
89 | { 0x1c5858, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, }, | ||
90 | { 0x1c585c, 0x31395c5e, 0x31395c5e, 0x31395c5e, 0x31395c5e, }, | ||
91 | { 0x1c5860, 0x0004dd10, 0x0004dd10, 0x0004dd20, 0x0004dd20, }, | ||
92 | { 0x1c5868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, }, | ||
93 | { 0x1c586c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, }, | ||
94 | { 0x1c5900, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
95 | { 0x1c5904, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
96 | { 0x1c5908, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
97 | { 0x1c590c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
98 | { 0x1c5914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, }, | ||
99 | { 0x1c5918, 0x00000118, 0x00000230, 0x00000268, 0x00000134, }, | ||
100 | { 0x1c591c, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff, }, | ||
101 | { 0x1c5920, 0x0510081c, 0x0510081c, 0x0510001c, 0x0510001c, }, | ||
102 | { 0x1c5924, 0xd0058a15, 0xd0058a15, 0xd0058a15, 0xd0058a15, }, | ||
103 | { 0x1c5928, 0x00000001, 0x00000001, 0x00000001, 0x00000001, }, | ||
104 | { 0x1c592c, 0x00000004, 0x00000004, 0x00000004, 0x00000004, }, | ||
105 | { 0x1c5934, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | ||
106 | { 0x1c5938, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | ||
107 | { 0x1c593c, 0x0000007f, 0x0000007f, 0x0000007f, 0x0000007f, }, | ||
108 | { 0x1c5944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, }, | ||
109 | { 0x1c5948, 0x9280b212, 0x9280b212, 0x9280b212, 0x9280b212, }, | ||
110 | { 0x1c594c, 0x00020028, 0x00020028, 0x00020028, 0x00020028, }, | ||
111 | { 0x1c5954, 0x5d50e188, 0x5d50e188, 0x5d50e188, 0x5d50e188, }, | ||
112 | { 0x1c5958, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, }, | ||
113 | { 0x1c5960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, }, | ||
114 | { 0x1c5964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, }, | ||
115 | { 0x1c5970, 0x190fb515, 0x190fb515, 0x190fb515, 0x190fb515, }, | ||
116 | { 0x1c5974, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
117 | { 0x1c5978, 0x00000001, 0x00000001, 0x00000001, 0x00000001, }, | ||
118 | { 0x1c597c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
119 | { 0x1c5980, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
120 | { 0x1c5984, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
121 | { 0x1c5988, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
122 | { 0x1c598c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
123 | { 0x1c5990, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
124 | { 0x1c5994, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
125 | { 0x1c5998, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
126 | { 0x1c599c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
127 | { 0x1c59a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
128 | { 0x1c59a4, 0x00000007, 0x00000007, 0x00000007, 0x00000007, }, | ||
129 | { 0x1c59a8, 0x001fff00, 0x001fff00, 0x001fff00, 0x001fff00, }, | ||
130 | { 0x1c59ac, 0x006f00c4, 0x006f00c4, 0x006f00c4, 0x006f00c4, }, | ||
131 | { 0x1c59b0, 0x03051000, 0x03051000, 0x03051000, 0x03051000, }, | ||
132 | { 0x1c59b4, 0x00000820, 0x00000820, 0x00000820, 0x00000820, }, | ||
133 | { 0x1c59c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, }, | ||
134 | { 0x1c59c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, }, | ||
135 | { 0x1c59c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, }, | ||
136 | { 0x1c59cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, }, | ||
137 | { 0x1c59d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, }, | ||
138 | { 0x1c59d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
139 | { 0x1c59d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
140 | { 0x1c59dc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
141 | { 0x1c59e0, 0x00000200, 0x00000200, 0x00000200, 0x00000200, }, | ||
142 | { 0x1c59e4, 0x64646464, 0x64646464, 0x64646464, 0x64646464, }, | ||
143 | { 0x1c59e8, 0x3c787878, 0x3c787878, 0x3c787878, 0x3c787878, }, | ||
144 | { 0x1c59ec, 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa, }, | ||
145 | { 0x1c59f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
146 | { 0x1c59fc, 0x00001042, 0x00001042, 0x00001042, 0x00001042, }, | ||
147 | { 0x1c5a00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
148 | { 0x1c5a04, 0x00000040, 0x00000040, 0x00000040, 0x00000040, }, | ||
149 | { 0x1c5a08, 0x00000080, 0x00000080, 0x00000080, 0x00000080, }, | ||
150 | { 0x1c5a0c, 0x000001a1, 0x000001a1, 0x00000141, 0x00000141, }, | ||
151 | { 0x1c5a10, 0x000001e1, 0x000001e1, 0x00000181, 0x00000181, }, | ||
152 | { 0x1c5a14, 0x00000021, 0x00000021, 0x000001c1, 0x000001c1, }, | ||
153 | { 0x1c5a18, 0x00000061, 0x00000061, 0x00000001, 0x00000001, }, | ||
154 | { 0x1c5a1c, 0x00000168, 0x00000168, 0x00000041, 0x00000041, }, | ||
155 | { 0x1c5a20, 0x000001a8, 0x000001a8, 0x000001a8, 0x000001a8, }, | ||
156 | { 0x1c5a24, 0x000001e8, 0x000001e8, 0x000001e8, 0x000001e8, }, | ||
157 | { 0x1c5a28, 0x00000028, 0x00000028, 0x00000028, 0x00000028, }, | ||
158 | { 0x1c5a2c, 0x00000068, 0x00000068, 0x00000068, 0x00000068, }, | ||
159 | { 0x1c5a30, 0x00000189, 0x00000189, 0x000000a8, 0x000000a8, }, | ||
160 | { 0x1c5a34, 0x000001c9, 0x000001c9, 0x00000169, 0x00000169, }, | ||
161 | { 0x1c5a38, 0x00000009, 0x00000009, 0x000001a9, 0x000001a9, }, | ||
162 | { 0x1c5a3c, 0x00000049, 0x00000049, 0x000001e9, 0x000001e9, }, | ||
163 | { 0x1c5a40, 0x00000089, 0x00000089, 0x00000029, 0x00000029, }, | ||
164 | { 0x1c5a44, 0x00000170, 0x00000170, 0x00000069, 0x00000069, }, | ||
165 | { 0x1c5a48, 0x000001b0, 0x000001b0, 0x00000190, 0x00000190, }, | ||
166 | { 0x1c5a4c, 0x000001f0, 0x000001f0, 0x000001d0, 0x000001d0, }, | ||
167 | { 0x1c5a50, 0x00000030, 0x00000030, 0x00000010, 0x00000010, }, | ||
168 | { 0x1c5a54, 0x00000070, 0x00000070, 0x00000050, 0x00000050, }, | ||
169 | { 0x1c5a58, 0x00000191, 0x00000191, 0x00000090, 0x00000090, }, | ||
170 | { 0x1c5a5c, 0x000001d1, 0x000001d1, 0x00000151, 0x00000151, }, | ||
171 | { 0x1c5a60, 0x00000011, 0x00000011, 0x00000191, 0x00000191, }, | ||
172 | { 0x1c5a64, 0x00000051, 0x00000051, 0x000001d1, 0x000001d1, }, | ||
173 | { 0x1c5a68, 0x00000091, 0x00000091, 0x00000011, 0x00000011, }, | ||
174 | { 0x1c5a6c, 0x000001b8, 0x000001b8, 0x00000051, 0x00000051, }, | ||
175 | { 0x1c5a70, 0x000001f8, 0x000001f8, 0x00000198, 0x00000198, }, | ||
176 | { 0x1c5a74, 0x00000038, 0x00000038, 0x000001d8, 0x000001d8, }, | ||
177 | { 0x1c5a78, 0x00000078, 0x00000078, 0x00000018, 0x00000018, }, | ||
178 | { 0x1c5a7c, 0x00000199, 0x00000199, 0x00000058, 0x00000058, }, | ||
179 | { 0x1c5a80, 0x000001d9, 0x000001d9, 0x00000098, 0x00000098, }, | ||
180 | { 0x1c5a84, 0x00000019, 0x00000019, 0x00000159, 0x00000159, }, | ||
181 | { 0x1c5a88, 0x00000059, 0x00000059, 0x00000199, 0x00000199, }, | ||
182 | { 0x1c5a8c, 0x00000099, 0x00000099, 0x000001d9, 0x000001d9, }, | ||
183 | { 0x1c5a90, 0x000000d9, 0x000000d9, 0x00000019, 0x00000019, }, | ||
184 | { 0x1c5a94, 0x000000f9, 0x000000f9, 0x00000059, 0x00000059, }, | ||
185 | { 0x1c5a98, 0x000000f9, 0x000000f9, 0x00000099, 0x00000099, }, | ||
186 | { 0x1c5a9c, 0x000000f9, 0x000000f9, 0x000000d9, 0x000000d9, }, | ||
187 | { 0x1c5aa0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
188 | { 0x1c5aa4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
189 | { 0x1c5aa8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
190 | { 0x1c5aac, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
191 | { 0x1c5ab0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
192 | { 0x1c5ab4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
193 | { 0x1c5ab8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
194 | { 0x1c5abc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
195 | { 0x1c5ac0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
196 | { 0x1c5ac4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
197 | { 0x1c5ac8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
198 | { 0x1c5acc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
199 | { 0x1c5ad0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
200 | { 0x1c5ad4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
201 | { 0x1c5ad8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
202 | { 0x1c5adc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
203 | { 0x1c5ae0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
204 | { 0x1c5ae4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
205 | { 0x1c5ae8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
206 | { 0x1c5aec, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
207 | { 0x1c5af0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
208 | { 0x1c5af4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
209 | { 0x1c5af8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
210 | { 0x1c5afc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, }, | ||
211 | { 0x1c5b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
212 | { 0x1c5b04, 0x00000001, 0x00000001, 0x00000001, 0x00000001, }, | ||
213 | { 0x1c5b08, 0x00000002, 0x00000002, 0x00000002, 0x00000002, }, | ||
214 | { 0x1c5b0c, 0x00000003, 0x00000003, 0x00000003, 0x00000003, }, | ||
215 | { 0x1c5b10, 0x00000004, 0x00000004, 0x00000004, 0x00000004, }, | ||
216 | { 0x1c5b14, 0x00000005, 0x00000005, 0x00000005, 0x00000005, }, | ||
217 | { 0x1c5b18, 0x00000008, 0x00000008, 0x00000008, 0x00000008, }, | ||
218 | { 0x1c5b1c, 0x00000009, 0x00000009, 0x00000009, 0x00000009, }, | ||
219 | { 0x1c5b20, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, }, | ||
220 | { 0x1c5b24, 0x0000000b, 0x0000000b, 0x0000000b, 0x0000000b, }, | ||
221 | { 0x1c5b28, 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c, }, | ||
222 | { 0x1c5b2c, 0x0000000d, 0x0000000d, 0x0000000d, 0x0000000d, }, | ||
223 | { 0x1c5b30, 0x00000010, 0x00000010, 0x00000010, 0x00000010, }, | ||
224 | { 0x1c5b34, 0x00000011, 0x00000011, 0x00000011, 0x00000011, }, | ||
225 | { 0x1c5b38, 0x00000012, 0x00000012, 0x00000012, 0x00000012, }, | ||
226 | { 0x1c5b3c, 0x00000013, 0x00000013, 0x00000013, 0x00000013, }, | ||
227 | { 0x1c5b40, 0x00000014, 0x00000014, 0x00000014, 0x00000014, }, | ||
228 | { 0x1c5b44, 0x00000015, 0x00000015, 0x00000015, 0x00000015, }, | ||
229 | { 0x1c5b48, 0x00000018, 0x00000018, 0x00000018, 0x00000018, }, | ||
230 | { 0x1c5b4c, 0x00000019, 0x00000019, 0x00000019, 0x00000019, }, | ||
231 | { 0x1c5b50, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, }, | ||
232 | { 0x1c5b54, 0x0000001b, 0x0000001b, 0x0000001b, 0x0000001b, }, | ||
233 | { 0x1c5b58, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, }, | ||
234 | { 0x1c5b5c, 0x0000001d, 0x0000001d, 0x0000001d, 0x0000001d, }, | ||
235 | { 0x1c5b60, 0x00000020, 0x00000020, 0x00000020, 0x00000020, }, | ||
236 | { 0x1c5b64, 0x00000021, 0x00000021, 0x00000021, 0x00000021, }, | ||
237 | { 0x1c5b68, 0x00000022, 0x00000022, 0x00000022, 0x00000022, }, | ||
238 | { 0x1c5b6c, 0x00000023, 0x00000023, 0x00000023, 0x00000023, }, | ||
239 | { 0x1c5b70, 0x00000024, 0x00000024, 0x00000024, 0x00000024, }, | ||
240 | { 0x1c5b74, 0x00000025, 0x00000025, 0x00000025, 0x00000025, }, | ||
241 | { 0x1c5b78, 0x00000028, 0x00000028, 0x00000028, 0x00000028, }, | ||
242 | { 0x1c5b7c, 0x00000029, 0x00000029, 0x00000029, 0x00000029, }, | ||
243 | { 0x1c5b80, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a, }, | ||
244 | { 0x1c5b84, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, }, | ||
245 | { 0x1c5b88, 0x0000002c, 0x0000002c, 0x0000002c, 0x0000002c, }, | ||
246 | { 0x1c5b8c, 0x0000002d, 0x0000002d, 0x0000002d, 0x0000002d, }, | ||
247 | { 0x1c5b90, 0x00000030, 0x00000030, 0x00000030, 0x00000030, }, | ||
248 | { 0x1c5b94, 0x00000031, 0x00000031, 0x00000031, 0x00000031, }, | ||
249 | { 0x1c5b98, 0x00000032, 0x00000032, 0x00000032, 0x00000032, }, | ||
250 | { 0x1c5b9c, 0x00000033, 0x00000033, 0x00000033, 0x00000033, }, | ||
251 | { 0x1c5ba0, 0x00000034, 0x00000034, 0x00000034, 0x00000034, }, | ||
252 | { 0x1c5ba4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
253 | { 0x1c5ba8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
254 | { 0x1c5bac, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
255 | { 0x1c5bb0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
256 | { 0x1c5bb4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
257 | { 0x1c5bb8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
258 | { 0x1c5bbc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
259 | { 0x1c5bc0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
260 | { 0x1c5bc4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
261 | { 0x1c5bc8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
262 | { 0x1c5bcc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
263 | { 0x1c5bd0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
264 | { 0x1c5bd4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
265 | { 0x1c5bd8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
266 | { 0x1c5bdc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
267 | { 0x1c5be0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
268 | { 0x1c5be4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
269 | { 0x1c5be8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
270 | { 0x1c5bec, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
271 | { 0x1c5bf0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
272 | { 0x1c5bf4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, }, | ||
273 | { 0x1c5bf8, 0x00000010, 0x00000010, 0x00000010, 0x00000010, }, | ||
274 | { 0x1c5bfc, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, }, | ||
275 | { 0x1c5c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
276 | { 0x1c5c0c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
277 | { 0x1c5c10, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
278 | { 0x1c5c14, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
279 | { 0x1c5c18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
280 | { 0x1c5c1c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
281 | { 0x1c5c20, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
282 | { 0x1c5c24, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
283 | { 0x1c5c28, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
284 | { 0x1c5c2c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
285 | { 0x1c5c30, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
286 | { 0x1c5c34, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
287 | { 0x1c5c38, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
288 | { 0x1c5c3c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
289 | { 0x1c5cf0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
290 | { 0x1c5cf4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
291 | { 0x1c5cf8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
292 | { 0x1c5cfc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
293 | { 0x1c6200, 0x00000008, 0x00000008, 0x0000000e, 0x0000000e, }, | ||
294 | { 0x1c6204, 0x00000440, 0x00000440, 0x00000440, 0x00000440, }, | ||
295 | { 0x1c6208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, }, | ||
296 | { 0x1c620c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, }, | ||
297 | { 0x1c6210, 0x40806333, 0x40806333, 0x40806333, 0x40806333, }, | ||
298 | { 0x1c6214, 0x00106c10, 0x00106c10, 0x00106c10, 0x00106c10, }, | ||
299 | { 0x1c6218, 0x009c4060, 0x009c4060, 0x009c4060, 0x009c4060, }, | ||
300 | { 0x1c621c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, }, | ||
301 | { 0x1c6220, 0x018830c6, 0x018830c6, 0x018830c6, 0x018830c6, }, | ||
302 | { 0x1c6224, 0x00000400, 0x00000400, 0x00000400, 0x00000400, }, | ||
303 | { 0x1c6228, 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5, }, | ||
304 | { 0x1c622c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
305 | { 0x1c6230, 0x00000108, 0x00000210, 0x00000210, 0x00000108, }, | ||
306 | { 0x1c6234, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | ||
307 | { 0x1c6238, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | ||
308 | { 0x1c623c, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, }, | ||
309 | { 0x1c6240, 0x38490a20, 0x38490a20, 0x38490a20, 0x38490a20, }, | ||
310 | { 0x1c6244, 0x00007bb6, 0x00007bb6, 0x00007bb6, 0x00007bb6, }, | ||
311 | { 0x1c6248, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, }, | ||
312 | { 0x1c624c, 0x00000001, 0x00000001, 0x00000001, 0x00000001, }, | ||
313 | { 0x1c6250, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, }, | ||
314 | { 0x1c6254, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
315 | { 0x1c6258, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380, }, | ||
316 | { 0x1c625c, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, }, | ||
317 | { 0x1c6260, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, }, | ||
318 | { 0x1c6264, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11, }, | ||
319 | { 0x1c6268, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
320 | { 0x1c626c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, }, | ||
321 | { 0x1c6274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, }, | ||
322 | { 0x1c6278, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, }, | ||
323 | { 0x1c627c, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, }, | ||
324 | { 0x1c6300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, }, | ||
325 | { 0x1c6304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, }, | ||
326 | { 0x1c6308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, }, | ||
327 | { 0x1c630c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, }, | ||
328 | { 0x1c6310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, }, | ||
329 | { 0x1c6314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, }, | ||
330 | { 0x1c6318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, }, | ||
331 | { 0x1c631c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, }, | ||
332 | { 0x1c6320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, }, | ||
333 | { 0x1c6324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, }, | ||
334 | { 0x1c6328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, }, | ||
335 | { 0x1c632c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
336 | { 0x1c6330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
337 | { 0x1c6334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
338 | { 0x1c6338, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
339 | { 0x1c633c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
340 | { 0x1c6340, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
341 | { 0x1c6344, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
342 | { 0x1c6348, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, }, | ||
343 | { 0x1c634c, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, }, | ||
344 | { 0x1c6350, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, }, | ||
345 | { 0x1c6354, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff, }, | ||
346 | { 0x1c6358, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, }, | ||
347 | { 0x1c6388, 0x08000000, 0x08000000, 0x08000000, 0x08000000, }, | ||
348 | { 0x1c638c, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | ||
349 | { 0x1c6390, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | ||
350 | { 0x1c6394, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, }, | ||
351 | { 0x1c6398, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, }, | ||
352 | { 0x1c639c, 0x00000007, 0x00000007, 0x00000007, 0x00000007, }, | ||
353 | { 0x1c63a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
354 | { 0x1c63a4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
355 | { 0x1c63a8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
356 | { 0x1c63ac, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
357 | { 0x1c63b0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
358 | { 0x1c63b4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
359 | { 0x1c63b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
360 | { 0x1c63bc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
361 | { 0x1c63c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
362 | { 0x1c63c4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
363 | { 0x1c63c8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
364 | { 0x1c63cc, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | ||
365 | { 0x1c63d0, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | ||
366 | { 0x1c63d4, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, }, | ||
367 | { 0x1c63d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, | ||
368 | { 0x1c63dc, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, }, | ||
369 | { 0x1c63e0, 0x000000c0, 0x000000c0, 0x000000c0, 0x000000c0, }, | ||
370 | { 0x1c6848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, }, | ||
371 | { 0x1c6920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, }, | ||
372 | { 0x1c6960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, }, | ||
373 | { 0x1c720c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, }, | ||
374 | { 0x1c726c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, }, | ||
375 | { 0x1c7848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, }, | ||
376 | { 0x1c7920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, }, | ||
377 | { 0x1c7960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, }, | ||
378 | { 0x1c820c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, }, | ||
379 | { 0x1c826c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, }, | ||
380 | /* { 0x1c8864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, }, */ | ||
381 | { 0x1c8864, 0x0001c600, 0x0001c600, 0x0001c600, 0x0001c600, }, | ||
382 | { 0x1c895c, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, }, | ||
383 | { 0x1c8968, 0x000003ce, 0x000003ce, 0x000003ce, 0x000003ce, }, | ||
384 | { 0x1c89bc, 0x00181400, 0x00181400, 0x00181400, 0x00181400, }, | ||
385 | { 0x1c9270, 0x00820820, 0x00820820, 0x00820820, 0x00820820, }, | ||
386 | { 0x1c935c, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, }, | ||
387 | { 0x1c9360, 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207, }, | ||
388 | { 0x1c9364, 0x17601685, 0x17601685, 0x17601685, 0x17601685, }, | ||
389 | { 0x1c9368, 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104, }, | ||
390 | { 0x1c936c, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03, }, | ||
391 | { 0x1c9370, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, }, | ||
392 | { 0x1c9374, 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803, }, | ||
393 | { 0x1c9378, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682, }, | ||
394 | { 0x1c937c, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482, }, | ||
395 | { 0x1c9380, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, }, | ||
396 | { 0x1c9384, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, } | ||
397 | }; | ||
398 | |||
399 | int ar9170_init_phy(struct ar9170 *ar, enum ieee80211_band band) | ||
400 | { | ||
401 | int i, err; | ||
402 | u32 val; | ||
403 | bool is_2ghz = band == IEEE80211_BAND_2GHZ; | ||
404 | bool is_40mhz = false; /* XXX: for now */ | ||
405 | |||
406 | ar9170_regwrite_begin(ar); | ||
407 | |||
408 | for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) { | ||
409 | if (is_40mhz) { | ||
410 | if (is_2ghz) | ||
411 | val = ar5416_phy_init[i]._2ghz_40; | ||
412 | else | ||
413 | val = ar5416_phy_init[i]._5ghz_40; | ||
414 | } else { | ||
415 | if (is_2ghz) | ||
416 | val = ar5416_phy_init[i]._2ghz_20; | ||
417 | else | ||
418 | val = ar5416_phy_init[i]._5ghz_20; | ||
419 | } | ||
420 | |||
421 | ar9170_regwrite(ar5416_phy_init[i].reg, val); | ||
422 | } | ||
423 | |||
424 | ar9170_regwrite_finish(); | ||
425 | err = ar9170_regwrite_result(); | ||
426 | if (err) | ||
427 | return err; | ||
428 | |||
429 | /* XXX: use EEPROM data here! */ | ||
430 | |||
431 | err = ar9170_init_power_cal(ar); | ||
432 | if (err) | ||
433 | return err; | ||
434 | |||
435 | /* XXX: remove magic! */ | ||
436 | if (is_2ghz) | ||
437 | err = ar9170_write_reg(ar, 0x1d4014, 0x5163); | ||
438 | else | ||
439 | err = ar9170_write_reg(ar, 0x1d4014, 0x5143); | ||
440 | |||
441 | return err; | ||
442 | } | ||
443 | |||
444 | struct ar9170_rf_init { | ||
445 | u32 reg, _5ghz, _2ghz; | ||
446 | }; | ||
447 | |||
448 | static struct ar9170_rf_init ar9170_rf_init[] = { | ||
449 | /* bank 0 */ | ||
450 | { 0x1c58b0, 0x1e5795e5, 0x1e5795e5}, | ||
451 | { 0x1c58e0, 0x02008020, 0x02008020}, | ||
452 | /* bank 1 */ | ||
453 | { 0x1c58b0, 0x02108421, 0x02108421}, | ||
454 | { 0x1c58ec, 0x00000008, 0x00000008}, | ||
455 | /* bank 2 */ | ||
456 | { 0x1c58b0, 0x0e73ff17, 0x0e73ff17}, | ||
457 | { 0x1c58e0, 0x00000420, 0x00000420}, | ||
458 | /* bank 3 */ | ||
459 | { 0x1c58f0, 0x01400018, 0x01c00018}, | ||
460 | /* bank 4 */ | ||
461 | { 0x1c58b0, 0x000001a1, 0x000001a1}, | ||
462 | { 0x1c58e8, 0x00000001, 0x00000001}, | ||
463 | /* bank 5 */ | ||
464 | { 0x1c58b0, 0x00000013, 0x00000013}, | ||
465 | { 0x1c58e4, 0x00000002, 0x00000002}, | ||
466 | /* bank 6 */ | ||
467 | { 0x1c58b0, 0x00000000, 0x00000000}, | ||
468 | { 0x1c58b0, 0x00000000, 0x00000000}, | ||
469 | { 0x1c58b0, 0x00000000, 0x00000000}, | ||
470 | { 0x1c58b0, 0x00000000, 0x00000000}, | ||
471 | { 0x1c58b0, 0x00000000, 0x00000000}, | ||
472 | { 0x1c58b0, 0x00004000, 0x00004000}, | ||
473 | { 0x1c58b0, 0x00006c00, 0x00006c00}, | ||
474 | { 0x1c58b0, 0x00002c00, 0x00002c00}, | ||
475 | { 0x1c58b0, 0x00004800, 0x00004800}, | ||
476 | { 0x1c58b0, 0x00004000, 0x00004000}, | ||
477 | { 0x1c58b0, 0x00006000, 0x00006000}, | ||
478 | { 0x1c58b0, 0x00001000, 0x00001000}, | ||
479 | { 0x1c58b0, 0x00004000, 0x00004000}, | ||
480 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | ||
481 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | ||
482 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | ||
483 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | ||
484 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | ||
485 | { 0x1c58b0, 0x00087c00, 0x00087c00}, | ||
486 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | ||
487 | { 0x1c58b0, 0x00005400, 0x00005400}, | ||
488 | { 0x1c58b0, 0x00000c00, 0x00000c00}, | ||
489 | { 0x1c58b0, 0x00001800, 0x00001800}, | ||
490 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | ||
491 | { 0x1c58b0, 0x00006c00, 0x00006c00}, | ||
492 | { 0x1c58b0, 0x00006c00, 0x00006c00}, | ||
493 | { 0x1c58b0, 0x00007c00, 0x00007c00}, | ||
494 | { 0x1c58b0, 0x00002c00, 0x00002c00}, | ||
495 | { 0x1c58b0, 0x00003c00, 0x00003c00}, | ||
496 | { 0x1c58b0, 0x00003800, 0x00003800}, | ||
497 | { 0x1c58b0, 0x00001c00, 0x00001c00}, | ||
498 | { 0x1c58b0, 0x00000800, 0x00000800}, | ||
499 | { 0x1c58b0, 0x00000408, 0x00000408}, | ||
500 | { 0x1c58b0, 0x00004c15, 0x00004c15}, | ||
501 | { 0x1c58b0, 0x00004188, 0x00004188}, | ||
502 | { 0x1c58b0, 0x0000201e, 0x0000201e}, | ||
503 | { 0x1c58b0, 0x00010408, 0x00010408}, | ||
504 | { 0x1c58b0, 0x00000801, 0x00000801}, | ||
505 | { 0x1c58b0, 0x00000c08, 0x00000c08}, | ||
506 | { 0x1c58b0, 0x0000181e, 0x0000181e}, | ||
507 | { 0x1c58b0, 0x00001016, 0x00001016}, | ||
508 | { 0x1c58b0, 0x00002800, 0x00002800}, | ||
509 | { 0x1c58b0, 0x00004010, 0x00004010}, | ||
510 | { 0x1c58b0, 0x0000081c, 0x0000081c}, | ||
511 | { 0x1c58b0, 0x00000115, 0x00000115}, | ||
512 | { 0x1c58b0, 0x00000015, 0x00000015}, | ||
513 | { 0x1c58b0, 0x00000066, 0x00000066}, | ||
514 | { 0x1c58b0, 0x0000001c, 0x0000001c}, | ||
515 | { 0x1c58b0, 0x00000000, 0x00000000}, | ||
516 | { 0x1c58b0, 0x00000004, 0x00000004}, | ||
517 | { 0x1c58b0, 0x00000015, 0x00000015}, | ||
518 | { 0x1c58b0, 0x0000001f, 0x0000001f}, | ||
519 | { 0x1c58e0, 0x00000000, 0x00000400}, | ||
520 | /* bank 7 */ | ||
521 | { 0x1c58b0, 0x000000a0, 0x000000a0}, | ||
522 | { 0x1c58b0, 0x00000000, 0x00000000}, | ||
523 | { 0x1c58b0, 0x00000040, 0x00000040}, | ||
524 | { 0x1c58f0, 0x0000001c, 0x0000001c}, | ||
525 | }; | ||
526 | |||
527 | static int ar9170_init_rf_banks_0_7(struct ar9170 *ar, bool band5ghz) | ||
528 | { | ||
529 | int err, i; | ||
530 | |||
531 | ar9170_regwrite_begin(ar); | ||
532 | |||
533 | for (i = 0; i < ARRAY_SIZE(ar9170_rf_init); i++) | ||
534 | ar9170_regwrite(ar9170_rf_init[i].reg, | ||
535 | band5ghz ? ar9170_rf_init[i]._5ghz | ||
536 | : ar9170_rf_init[i]._2ghz); | ||
537 | |||
538 | ar9170_regwrite_finish(); | ||
539 | err = ar9170_regwrite_result(); | ||
540 | if (err) | ||
541 | printk(KERN_ERR "%s: rf init failed\n", | ||
542 | wiphy_name(ar->hw->wiphy)); | ||
543 | return err; | ||
544 | } | ||
545 | |||
546 | static int ar9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz, | ||
547 | u32 freq, enum ar9170_bw bw) | ||
548 | { | ||
549 | int err; | ||
550 | u32 d0, d1, td0, td1, fd0, fd1; | ||
551 | u8 chansel; | ||
552 | u8 refsel0 = 1, refsel1 = 0; | ||
553 | u8 lf_synth = 0; | ||
554 | |||
555 | switch (bw) { | ||
556 | case AR9170_BW_40_ABOVE: | ||
557 | freq += 10; | ||
558 | break; | ||
559 | case AR9170_BW_40_BELOW: | ||
560 | freq -= 10; | ||
561 | break; | ||
562 | case AR9170_BW_20: | ||
563 | break; | ||
564 | case __AR9170_NUM_BW: | ||
565 | BUG(); | ||
566 | } | ||
567 | |||
568 | if (band5ghz) { | ||
569 | if (freq % 10) { | ||
570 | chansel = (freq - 4800) / 5; | ||
571 | } else { | ||
572 | chansel = ((freq - 4800) / 10) * 2; | ||
573 | refsel0 = 0; | ||
574 | refsel1 = 1; | ||
575 | } | ||
576 | chansel = byte_rev_table[chansel]; | ||
577 | } else { | ||
578 | if (freq == 2484) { | ||
579 | chansel = 10 + (freq - 2274) / 5; | ||
580 | lf_synth = 1; | ||
581 | } else | ||
582 | chansel = 16 + (freq - 2272) / 5; | ||
583 | chansel *= 4; | ||
584 | chansel = byte_rev_table[chansel]; | ||
585 | } | ||
586 | |||
587 | d1 = chansel; | ||
588 | d0 = 0x21 | | ||
589 | refsel0 << 3 | | ||
590 | refsel1 << 2 | | ||
591 | lf_synth << 1; | ||
592 | td0 = d0 & 0x1f; | ||
593 | td1 = d1 & 0x1f; | ||
594 | fd0 = td1 << 5 | td0; | ||
595 | |||
596 | td0 = (d0 >> 5) & 0x7; | ||
597 | td1 = (d1 >> 5) & 0x7; | ||
598 | fd1 = td1 << 5 | td0; | ||
599 | |||
600 | ar9170_regwrite_begin(ar); | ||
601 | |||
602 | ar9170_regwrite(0x1c58b0, fd0); | ||
603 | ar9170_regwrite(0x1c58e8, fd1); | ||
604 | |||
605 | ar9170_regwrite_finish(); | ||
606 | err = ar9170_regwrite_result(); | ||
607 | if (err) | ||
608 | return err; | ||
609 | |||
610 | msleep(10); | ||
611 | |||
612 | return 0; | ||
613 | } | ||
614 | |||
615 | struct ar9170_phy_freq_params { | ||
616 | u8 coeff_exp; | ||
617 | u16 coeff_man; | ||
618 | u8 coeff_exp_shgi; | ||
619 | u16 coeff_man_shgi; | ||
620 | }; | ||
621 | |||
622 | struct ar9170_phy_freq_entry { | ||
623 | u16 freq; | ||
624 | struct ar9170_phy_freq_params params[__AR9170_NUM_BW]; | ||
625 | }; | ||
626 | |||
627 | /* NB: must be in sync with channel tables in main! */ | ||
628 | static const struct ar9170_phy_freq_entry ar9170_phy_freq_params[] = { | ||
629 | /* | ||
630 | * freq, | ||
631 | * 20MHz, | ||
632 | * 40MHz (below), | ||
633 | * 40Mhz (above), | ||
634 | */ | ||
635 | { 2412, { | ||
636 | { 3, 21737, 3, 19563, }, | ||
637 | { 3, 21827, 3, 19644, }, | ||
638 | { 3, 21647, 3, 19482, }, | ||
639 | } }, | ||
640 | { 2417, { | ||
641 | { 3, 21692, 3, 19523, }, | ||
642 | { 3, 21782, 3, 19604, }, | ||
643 | { 3, 21602, 3, 19442, }, | ||
644 | } }, | ||
645 | { 2422, { | ||
646 | { 3, 21647, 3, 19482, }, | ||
647 | { 3, 21737, 3, 19563, }, | ||
648 | { 3, 21558, 3, 19402, }, | ||
649 | } }, | ||
650 | { 2427, { | ||
651 | { 3, 21602, 3, 19442, }, | ||
652 | { 3, 21692, 3, 19523, }, | ||
653 | { 3, 21514, 3, 19362, }, | ||
654 | } }, | ||
655 | { 2432, { | ||
656 | { 3, 21558, 3, 19402, }, | ||
657 | { 3, 21647, 3, 19482, }, | ||
658 | { 3, 21470, 3, 19323, }, | ||
659 | } }, | ||
660 | { 2437, { | ||
661 | { 3, 21514, 3, 19362, }, | ||
662 | { 3, 21602, 3, 19442, }, | ||
663 | { 3, 21426, 3, 19283, }, | ||
664 | } }, | ||
665 | { 2442, { | ||
666 | { 3, 21470, 3, 19323, }, | ||
667 | { 3, 21558, 3, 19402, }, | ||
668 | { 3, 21382, 3, 19244, }, | ||
669 | } }, | ||
670 | { 2447, { | ||
671 | { 3, 21426, 3, 19283, }, | ||
672 | { 3, 21514, 3, 19362, }, | ||
673 | { 3, 21339, 3, 19205, }, | ||
674 | } }, | ||
675 | { 2452, { | ||
676 | { 3, 21382, 3, 19244, }, | ||
677 | { 3, 21470, 3, 19323, }, | ||
678 | { 3, 21295, 3, 19166, }, | ||
679 | } }, | ||
680 | { 2457, { | ||
681 | { 3, 21339, 3, 19205, }, | ||
682 | { 3, 21426, 3, 19283, }, | ||
683 | { 3, 21252, 3, 19127, }, | ||
684 | } }, | ||
685 | { 2462, { | ||
686 | { 3, 21295, 3, 19166, }, | ||
687 | { 3, 21382, 3, 19244, }, | ||
688 | { 3, 21209, 3, 19088, }, | ||
689 | } }, | ||
690 | { 2467, { | ||
691 | { 3, 21252, 3, 19127, }, | ||
692 | { 3, 21339, 3, 19205, }, | ||
693 | { 3, 21166, 3, 19050, }, | ||
694 | } }, | ||
695 | { 2472, { | ||
696 | { 3, 21209, 3, 19088, }, | ||
697 | { 3, 21295, 3, 19166, }, | ||
698 | { 3, 21124, 3, 19011, }, | ||
699 | } }, | ||
700 | { 2484, { | ||
701 | { 3, 21107, 3, 18996, }, | ||
702 | { 3, 21192, 3, 19073, }, | ||
703 | { 3, 21022, 3, 18920, }, | ||
704 | } }, | ||
705 | { 4920, { | ||
706 | { 4, 21313, 4, 19181, }, | ||
707 | { 4, 21356, 4, 19220, }, | ||
708 | { 4, 21269, 4, 19142, }, | ||
709 | } }, | ||
710 | { 4940, { | ||
711 | { 4, 21226, 4, 19104, }, | ||
712 | { 4, 21269, 4, 19142, }, | ||
713 | { 4, 21183, 4, 19065, }, | ||
714 | } }, | ||
715 | { 4960, { | ||
716 | { 4, 21141, 4, 19027, }, | ||
717 | { 4, 21183, 4, 19065, }, | ||
718 | { 4, 21098, 4, 18988, }, | ||
719 | } }, | ||
720 | { 4980, { | ||
721 | { 4, 21056, 4, 18950, }, | ||
722 | { 4, 21098, 4, 18988, }, | ||
723 | { 4, 21014, 4, 18912, }, | ||
724 | } }, | ||
725 | { 5040, { | ||
726 | { 4, 20805, 4, 18725, }, | ||
727 | { 4, 20846, 4, 18762, }, | ||
728 | { 4, 20764, 4, 18687, }, | ||
729 | } }, | ||
730 | { 5060, { | ||
731 | { 4, 20723, 4, 18651, }, | ||
732 | { 4, 20764, 4, 18687, }, | ||
733 | { 4, 20682, 4, 18614, }, | ||
734 | } }, | ||
735 | { 5080, { | ||
736 | { 4, 20641, 4, 18577, }, | ||
737 | { 4, 20682, 4, 18614, }, | ||
738 | { 4, 20601, 4, 18541, }, | ||
739 | } }, | ||
740 | { 5180, { | ||
741 | { 4, 20243, 4, 18219, }, | ||
742 | { 4, 20282, 4, 18254, }, | ||
743 | { 4, 20204, 4, 18183, }, | ||
744 | } }, | ||
745 | { 5200, { | ||
746 | { 4, 20165, 4, 18148, }, | ||
747 | { 4, 20204, 4, 18183, }, | ||
748 | { 4, 20126, 4, 18114, }, | ||
749 | } }, | ||
750 | { 5220, { | ||
751 | { 4, 20088, 4, 18079, }, | ||
752 | { 4, 20126, 4, 18114, }, | ||
753 | { 4, 20049, 4, 18044, }, | ||
754 | } }, | ||
755 | { 5240, { | ||
756 | { 4, 20011, 4, 18010, }, | ||
757 | { 4, 20049, 4, 18044, }, | ||
758 | { 4, 19973, 4, 17976, }, | ||
759 | } }, | ||
760 | { 5260, { | ||
761 | { 4, 19935, 4, 17941, }, | ||
762 | { 4, 19973, 4, 17976, }, | ||
763 | { 4, 19897, 4, 17907, }, | ||
764 | } }, | ||
765 | { 5280, { | ||
766 | { 4, 19859, 4, 17873, }, | ||
767 | { 4, 19897, 4, 17907, }, | ||
768 | { 4, 19822, 4, 17840, }, | ||
769 | } }, | ||
770 | { 5300, { | ||
771 | { 4, 19784, 4, 17806, }, | ||
772 | { 4, 19822, 4, 17840, }, | ||
773 | { 4, 19747, 4, 17772, }, | ||
774 | } }, | ||
775 | { 5320, { | ||
776 | { 4, 19710, 4, 17739, }, | ||
777 | { 4, 19747, 4, 17772, }, | ||
778 | { 4, 19673, 4, 17706, }, | ||
779 | } }, | ||
780 | { 5500, { | ||
781 | { 4, 19065, 4, 17159, }, | ||
782 | { 4, 19100, 4, 17190, }, | ||
783 | { 4, 19030, 4, 17127, }, | ||
784 | } }, | ||
785 | { 5520, { | ||
786 | { 4, 18996, 4, 17096, }, | ||
787 | { 4, 19030, 4, 17127, }, | ||
788 | { 4, 18962, 4, 17065, }, | ||
789 | } }, | ||
790 | { 5540, { | ||
791 | { 4, 18927, 4, 17035, }, | ||
792 | { 4, 18962, 4, 17065, }, | ||
793 | { 4, 18893, 4, 17004, }, | ||
794 | } }, | ||
795 | { 5560, { | ||
796 | { 4, 18859, 4, 16973, }, | ||
797 | { 4, 18893, 4, 17004, }, | ||
798 | { 4, 18825, 4, 16943, }, | ||
799 | } }, | ||
800 | { 5580, { | ||
801 | { 4, 18792, 4, 16913, }, | ||
802 | { 4, 18825, 4, 16943, }, | ||
803 | { 4, 18758, 4, 16882, }, | ||
804 | } }, | ||
805 | { 5600, { | ||
806 | { 4, 18725, 4, 16852, }, | ||
807 | { 4, 18758, 4, 16882, }, | ||
808 | { 4, 18691, 4, 16822, }, | ||
809 | } }, | ||
810 | { 5620, { | ||
811 | { 4, 18658, 4, 16792, }, | ||
812 | { 4, 18691, 4, 16822, }, | ||
813 | { 4, 18625, 4, 16762, }, | ||
814 | } }, | ||
815 | { 5640, { | ||
816 | { 4, 18592, 4, 16733, }, | ||
817 | { 4, 18625, 4, 16762, }, | ||
818 | { 4, 18559, 4, 16703, }, | ||
819 | } }, | ||
820 | { 5660, { | ||
821 | { 4, 18526, 4, 16673, }, | ||
822 | { 4, 18559, 4, 16703, }, | ||
823 | { 4, 18493, 4, 16644, }, | ||
824 | } }, | ||
825 | { 5680, { | ||
826 | { 4, 18461, 4, 16615, }, | ||
827 | { 4, 18493, 4, 16644, }, | ||
828 | { 4, 18428, 4, 16586, }, | ||
829 | } }, | ||
830 | { 5700, { | ||
831 | { 4, 18396, 4, 16556, }, | ||
832 | { 4, 18428, 4, 16586, }, | ||
833 | { 4, 18364, 4, 16527, }, | ||
834 | } }, | ||
835 | { 5745, { | ||
836 | { 4, 18252, 4, 16427, }, | ||
837 | { 4, 18284, 4, 16455, }, | ||
838 | { 4, 18220, 4, 16398, }, | ||
839 | } }, | ||
840 | { 5765, { | ||
841 | { 4, 18189, 5, 32740, }, | ||
842 | { 4, 18220, 4, 16398, }, | ||
843 | { 4, 18157, 5, 32683, }, | ||
844 | } }, | ||
845 | { 5785, { | ||
846 | { 4, 18126, 5, 32626, }, | ||
847 | { 4, 18157, 5, 32683, }, | ||
848 | { 4, 18094, 5, 32570, }, | ||
849 | } }, | ||
850 | { 5805, { | ||
851 | { 4, 18063, 5, 32514, }, | ||
852 | { 4, 18094, 5, 32570, }, | ||
853 | { 4, 18032, 5, 32458, }, | ||
854 | } }, | ||
855 | { 5825, { | ||
856 | { 4, 18001, 5, 32402, }, | ||
857 | { 4, 18032, 5, 32458, }, | ||
858 | { 4, 17970, 5, 32347, }, | ||
859 | } }, | ||
860 | { 5170, { | ||
861 | { 4, 20282, 4, 18254, }, | ||
862 | { 4, 20321, 4, 18289, }, | ||
863 | { 4, 20243, 4, 18219, }, | ||
864 | } }, | ||
865 | { 5190, { | ||
866 | { 4, 20204, 4, 18183, }, | ||
867 | { 4, 20243, 4, 18219, }, | ||
868 | { 4, 20165, 4, 18148, }, | ||
869 | } }, | ||
870 | { 5210, { | ||
871 | { 4, 20126, 4, 18114, }, | ||
872 | { 4, 20165, 4, 18148, }, | ||
873 | { 4, 20088, 4, 18079, }, | ||
874 | } }, | ||
875 | { 5230, { | ||
876 | { 4, 20049, 4, 18044, }, | ||
877 | { 4, 20088, 4, 18079, }, | ||
878 | { 4, 20011, 4, 18010, }, | ||
879 | } }, | ||
880 | }; | ||
881 | |||
882 | static const struct ar9170_phy_freq_params * | ||
883 | ar9170_get_hw_dyn_params(struct ieee80211_channel *channel, | ||
884 | enum ar9170_bw bw) | ||
885 | { | ||
886 | unsigned int chanidx = 0; | ||
887 | u16 freq = 2412; | ||
888 | |||
889 | if (channel) { | ||
890 | chanidx = channel->hw_value; | ||
891 | freq = channel->center_freq; | ||
892 | } | ||
893 | |||
894 | BUG_ON(chanidx >= ARRAY_SIZE(ar9170_phy_freq_params)); | ||
895 | |||
896 | BUILD_BUG_ON(__AR9170_NUM_BW != 3); | ||
897 | |||
898 | WARN_ON(ar9170_phy_freq_params[chanidx].freq != freq); | ||
899 | |||
900 | return &ar9170_phy_freq_params[chanidx].params[bw]; | ||
901 | } | ||
902 | |||
903 | |||
904 | int ar9170_init_rf(struct ar9170 *ar) | ||
905 | { | ||
906 | const struct ar9170_phy_freq_params *freqpar; | ||
907 | __le32 cmd[7]; | ||
908 | int err; | ||
909 | |||
910 | err = ar9170_init_rf_banks_0_7(ar, false); | ||
911 | if (err) | ||
912 | return err; | ||
913 | |||
914 | err = ar9170_init_rf_bank4_pwr(ar, false, 2412, AR9170_BW_20); | ||
915 | if (err) | ||
916 | return err; | ||
917 | |||
918 | freqpar = ar9170_get_hw_dyn_params(NULL, AR9170_BW_20); | ||
919 | |||
920 | cmd[0] = cpu_to_le32(2412 * 1000); | ||
921 | cmd[1] = cpu_to_le32(0); | ||
922 | cmd[2] = cpu_to_le32(1); | ||
923 | cmd[3] = cpu_to_le32(freqpar->coeff_exp); | ||
924 | cmd[4] = cpu_to_le32(freqpar->coeff_man); | ||
925 | cmd[5] = cpu_to_le32(freqpar->coeff_exp_shgi); | ||
926 | cmd[6] = cpu_to_le32(freqpar->coeff_man_shgi); | ||
927 | |||
928 | /* RF_INIT echoes the command back to us */ | ||
929 | err = ar->exec_cmd(ar, AR9170_CMD_RF_INIT, | ||
930 | sizeof(cmd), (u8 *)cmd, | ||
931 | sizeof(cmd), (u8 *)cmd); | ||
932 | if (err) | ||
933 | return err; | ||
934 | |||
935 | msleep(1000); | ||
936 | |||
937 | return ar9170_echo_test(ar, 0xaabbccdd); | ||
938 | } | ||
939 | |||
940 | static int ar9170_find_freq_idx(int nfreqs, u8 *freqs, u8 f) | ||
941 | { | ||
942 | int idx = nfreqs - 2; | ||
943 | |||
944 | while (idx >= 0) { | ||
945 | if (f >= freqs[idx]) | ||
946 | return idx; | ||
947 | idx--; | ||
948 | } | ||
949 | |||
950 | return 0; | ||
951 | } | ||
952 | |||
953 | static s32 ar9170_interpolate_s32(s32 x, s32 x1, s32 y1, s32 x2, s32 y2) | ||
954 | { | ||
955 | /* nothing to interpolate, it's horizontal */ | ||
956 | if (y2 == y1) | ||
957 | return y1; | ||
958 | |||
959 | /* check if we hit one of the edges */ | ||
960 | if (x == x1) | ||
961 | return y1; | ||
962 | if (x == x2) | ||
963 | return y2; | ||
964 | |||
965 | /* x1 == x2 is bad, hopefully == x */ | ||
966 | if (x2 == x1) | ||
967 | return y1; | ||
968 | |||
969 | return y1 + (((y2 - y1) * (x - x1)) / (x2 - x1)); | ||
970 | } | ||
971 | |||
972 | static u8 ar9170_interpolate_u8(u8 x, u8 x1, u8 y1, u8 x2, u8 y2) | ||
973 | { | ||
974 | #define SHIFT 8 | ||
975 | s32 y; | ||
976 | |||
977 | y = ar9170_interpolate_s32(x << SHIFT, | ||
978 | x1 << SHIFT, y1 << SHIFT, | ||
979 | x2 << SHIFT, y2 << SHIFT); | ||
980 | |||
981 | /* | ||
982 | * XXX: unwrap this expression | ||
983 | * Isn't it just DIV_ROUND_UP(y, 1<<SHIFT)? | ||
984 | * Can we rely on the compiler to optimise away the div? | ||
985 | */ | ||
986 | return (y >> SHIFT) + ((y & (1<<(SHIFT-1))) >> (SHIFT - 1)); | ||
987 | #undef SHIFT | ||
988 | } | ||
989 | |||
990 | static int ar9170_set_power_cal(struct ar9170 *ar, u32 freq, enum ar9170_bw bw) | ||
991 | { | ||
992 | struct ar9170_calibration_target_power_legacy *ctpl; | ||
993 | struct ar9170_calibration_target_power_ht *ctph; | ||
994 | u8 *ctpres; | ||
995 | int ntargets; | ||
996 | int idx, i, n; | ||
997 | u8 ackpower, ackchains, f; | ||
998 | u8 pwr_freqs[AR5416_MAX_NUM_TGT_PWRS]; | ||
999 | |||
1000 | if (freq < 3000) | ||
1001 | f = freq - 2300; | ||
1002 | else | ||
1003 | f = (freq - 4800)/5; | ||
1004 | |||
1005 | /* | ||
1006 | * cycle through the various modes | ||
1007 | * | ||
1008 | * legacy modes first: 5G, 2G CCK, 2G OFDM | ||
1009 | */ | ||
1010 | for (i = 0; i < 3; i++) { | ||
1011 | switch (i) { | ||
1012 | case 0: /* 5 GHz legacy */ | ||
1013 | ctpl = &ar->eeprom.cal_tgt_pwr_5G[0]; | ||
1014 | ntargets = AR5416_NUM_5G_TARGET_PWRS; | ||
1015 | ctpres = ar->power_5G_leg; | ||
1016 | break; | ||
1017 | case 1: /* 2.4 GHz CCK */ | ||
1018 | ctpl = &ar->eeprom.cal_tgt_pwr_2G_cck[0]; | ||
1019 | ntargets = AR5416_NUM_2G_CCK_TARGET_PWRS; | ||
1020 | ctpres = ar->power_2G_cck; | ||
1021 | break; | ||
1022 | case 2: /* 2.4 GHz OFDM */ | ||
1023 | ctpl = &ar->eeprom.cal_tgt_pwr_2G_ofdm[0]; | ||
1024 | ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS; | ||
1025 | ctpres = ar->power_2G_ofdm; | ||
1026 | break; | ||
1027 | default: | ||
1028 | BUG(); | ||
1029 | } | ||
1030 | |||
1031 | for (n = 0; n < ntargets; n++) { | ||
1032 | if (ctpl[n].freq == 0xff) | ||
1033 | break; | ||
1034 | pwr_freqs[n] = ctpl[n].freq; | ||
1035 | } | ||
1036 | ntargets = n; | ||
1037 | idx = ar9170_find_freq_idx(ntargets, pwr_freqs, f); | ||
1038 | for (n = 0; n < 4; n++) | ||
1039 | ctpres[n] = ar9170_interpolate_u8( | ||
1040 | f, | ||
1041 | ctpl[idx + 0].freq, | ||
1042 | ctpl[idx + 0].power[n], | ||
1043 | ctpl[idx + 1].freq, | ||
1044 | ctpl[idx + 1].power[n]); | ||
1045 | } | ||
1046 | |||
1047 | /* | ||
1048 | * HT modes now: 5G HT20, 5G HT40, 2G CCK, 2G OFDM, 2G HT20, 2G HT40 | ||
1049 | */ | ||
1050 | for (i = 0; i < 4; i++) { | ||
1051 | switch (i) { | ||
1052 | case 0: /* 5 GHz HT 20 */ | ||
1053 | ctph = &ar->eeprom.cal_tgt_pwr_5G_ht20[0]; | ||
1054 | ntargets = AR5416_NUM_5G_TARGET_PWRS; | ||
1055 | ctpres = ar->power_5G_ht20; | ||
1056 | break; | ||
1057 | case 1: /* 5 GHz HT 40 */ | ||
1058 | ctph = &ar->eeprom.cal_tgt_pwr_5G_ht40[0]; | ||
1059 | ntargets = AR5416_NUM_5G_TARGET_PWRS; | ||
1060 | ctpres = ar->power_5G_ht40; | ||
1061 | break; | ||
1062 | case 2: /* 2.4 GHz HT 20 */ | ||
1063 | ctph = &ar->eeprom.cal_tgt_pwr_2G_ht20[0]; | ||
1064 | ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS; | ||
1065 | ctpres = ar->power_2G_ht20; | ||
1066 | break; | ||
1067 | case 3: /* 2.4 GHz HT 40 */ | ||
1068 | ctph = &ar->eeprom.cal_tgt_pwr_2G_ht40[0]; | ||
1069 | ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS; | ||
1070 | ctpres = ar->power_2G_ht40; | ||
1071 | break; | ||
1072 | default: | ||
1073 | BUG(); | ||
1074 | } | ||
1075 | |||
1076 | for (n = 0; n < ntargets; n++) { | ||
1077 | if (ctph[n].freq == 0xff) | ||
1078 | break; | ||
1079 | pwr_freqs[n] = ctph[n].freq; | ||
1080 | } | ||
1081 | ntargets = n; | ||
1082 | idx = ar9170_find_freq_idx(ntargets, pwr_freqs, f); | ||
1083 | for (n = 0; n < 8; n++) | ||
1084 | ctpres[n] = ar9170_interpolate_u8( | ||
1085 | f, | ||
1086 | ctph[idx + 0].freq, | ||
1087 | ctph[idx + 0].power[n], | ||
1088 | ctph[idx + 1].freq, | ||
1089 | ctph[idx + 1].power[n]); | ||
1090 | } | ||
1091 | |||
1092 | /* set ACK/CTS TX power */ | ||
1093 | ar9170_regwrite_begin(ar); | ||
1094 | |||
1095 | if (ar->eeprom.tx_mask != 1) | ||
1096 | ackchains = AR9170_TX_PHY_TXCHAIN_2; | ||
1097 | else | ||
1098 | ackchains = AR9170_TX_PHY_TXCHAIN_1; | ||
1099 | |||
1100 | if (freq < 3000) | ||
1101 | ackpower = ar->power_2G_ofdm[0] & 0x3f; | ||
1102 | else | ||
1103 | ackpower = ar->power_5G_leg[0] & 0x3f; | ||
1104 | |||
1105 | ar9170_regwrite(0x1c3694, ackpower << 20 | ackchains << 26); | ||
1106 | ar9170_regwrite(0x1c3bb4, ackpower << 5 | ackchains << 11 | | ||
1107 | ackpower << 21 | ackchains << 27); | ||
1108 | |||
1109 | ar9170_regwrite_finish(); | ||
1110 | return ar9170_regwrite_result(); | ||
1111 | } | ||
1112 | |||
1113 | static int ar9170_calc_noise_dbm(u32 raw_noise) | ||
1114 | { | ||
1115 | if (raw_noise & 0x100) | ||
1116 | return ~((raw_noise & 0x0ff) >> 1); | ||
1117 | else | ||
1118 | return (raw_noise & 0xff) >> 1; | ||
1119 | } | ||
1120 | |||
1121 | int ar9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel, | ||
1122 | enum ar9170_rf_init_mode rfi, enum ar9170_bw bw) | ||
1123 | { | ||
1124 | const struct ar9170_phy_freq_params *freqpar; | ||
1125 | u32 cmd, tmp, offs; | ||
1126 | __le32 vals[8]; | ||
1127 | int i, err; | ||
1128 | bool bandswitch; | ||
1129 | |||
1130 | /* clear BB heavy clip enable */ | ||
1131 | err = ar9170_write_reg(ar, 0x1c59e0, 0x200); | ||
1132 | if (err) | ||
1133 | return err; | ||
1134 | |||
1135 | /* may be NULL at first setup */ | ||
1136 | if (ar->channel) | ||
1137 | bandswitch = ar->channel->band != channel->band; | ||
1138 | else | ||
1139 | bandswitch = true; | ||
1140 | |||
1141 | /* HW workaround */ | ||
1142 | if (!ar->hw->wiphy->bands[IEEE80211_BAND_5GHZ] && | ||
1143 | channel->center_freq <= 2417) | ||
1144 | bandswitch = true; | ||
1145 | |||
1146 | err = ar->exec_cmd(ar, AR9170_CMD_FREQ_START, 0, NULL, 0, NULL); | ||
1147 | if (err) | ||
1148 | return err; | ||
1149 | |||
1150 | if (rfi != AR9170_RFI_NONE || bandswitch) { | ||
1151 | u32 val = 0x400; | ||
1152 | |||
1153 | if (rfi == AR9170_RFI_COLD) | ||
1154 | val = 0x800; | ||
1155 | |||
1156 | /* warm/cold reset BB/ADDA */ | ||
1157 | err = ar9170_write_reg(ar, 0x1d4004, val); | ||
1158 | if (err) | ||
1159 | return err; | ||
1160 | |||
1161 | err = ar9170_write_reg(ar, 0x1d4004, 0x0); | ||
1162 | if (err) | ||
1163 | return err; | ||
1164 | |||
1165 | err = ar9170_init_phy(ar, channel->band); | ||
1166 | if (err) | ||
1167 | return err; | ||
1168 | |||
1169 | err = ar9170_init_rf_banks_0_7(ar, | ||
1170 | channel->band == IEEE80211_BAND_5GHZ); | ||
1171 | if (err) | ||
1172 | return err; | ||
1173 | |||
1174 | cmd = AR9170_CMD_RF_INIT; | ||
1175 | } else { | ||
1176 | cmd = AR9170_CMD_FREQUENCY; | ||
1177 | } | ||
1178 | |||
1179 | err = ar9170_init_rf_bank4_pwr(ar, | ||
1180 | channel->band == IEEE80211_BAND_5GHZ, | ||
1181 | channel->center_freq, bw); | ||
1182 | if (err) | ||
1183 | return err; | ||
1184 | |||
1185 | switch (bw) { | ||
1186 | case AR9170_BW_20: | ||
1187 | tmp = 0x240; | ||
1188 | offs = 0; | ||
1189 | break; | ||
1190 | case AR9170_BW_40_BELOW: | ||
1191 | tmp = 0x2c4; | ||
1192 | offs = 3; | ||
1193 | break; | ||
1194 | case AR9170_BW_40_ABOVE: | ||
1195 | tmp = 0x2d4; | ||
1196 | offs = 1; | ||
1197 | break; | ||
1198 | default: | ||
1199 | BUG(); | ||
1200 | return -ENOSYS; | ||
1201 | } | ||
1202 | |||
1203 | if (0 /* 2 streams capable */) | ||
1204 | tmp |= 0x100; | ||
1205 | |||
1206 | err = ar9170_write_reg(ar, 0x1c5804, tmp); | ||
1207 | if (err) | ||
1208 | return err; | ||
1209 | |||
1210 | err = ar9170_set_power_cal(ar, channel->center_freq, bw); | ||
1211 | if (err) | ||
1212 | return err; | ||
1213 | |||
1214 | freqpar = ar9170_get_hw_dyn_params(channel, bw); | ||
1215 | |||
1216 | vals[0] = cpu_to_le32(channel->center_freq * 1000); | ||
1217 | vals[1] = cpu_to_le32(bw == AR9170_BW_20 ? 0 : 1); | ||
1218 | vals[2] = cpu_to_le32(offs << 2 | 1); | ||
1219 | vals[3] = cpu_to_le32(freqpar->coeff_exp); | ||
1220 | vals[4] = cpu_to_le32(freqpar->coeff_man); | ||
1221 | vals[5] = cpu_to_le32(freqpar->coeff_exp_shgi); | ||
1222 | vals[6] = cpu_to_le32(freqpar->coeff_man_shgi); | ||
1223 | vals[7] = cpu_to_le32(1000); | ||
1224 | |||
1225 | err = ar->exec_cmd(ar, cmd, sizeof(vals), (u8 *)vals, | ||
1226 | sizeof(vals), (u8 *)vals); | ||
1227 | if (err) | ||
1228 | return err; | ||
1229 | |||
1230 | for (i = 0; i < 2; i++) { | ||
1231 | ar->noise[i] = ar9170_calc_noise_dbm( | ||
1232 | (le32_to_cpu(vals[2 + i]) >> 19) & 0x1ff); | ||
1233 | |||
1234 | ar->noise[i + 2] = ar9170_calc_noise_dbm( | ||
1235 | (le32_to_cpu(vals[5 + i]) >> 23) & 0x1ff); | ||
1236 | } | ||
1237 | |||
1238 | ar->channel = channel; | ||
1239 | return 0; | ||
1240 | } | ||