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authorJohn W. Linville <linville@tuxdriver.com>2010-03-10 11:08:50 -0500
committerJohn W. Linville <linville@tuxdriver.com>2010-03-15 15:31:52 -0400
commit200763bb7503102aa364658e2b32cb2463a08d91 (patch)
treeafa71939cc0a86697b3a8b5ac10a97deecc515e7 /drivers/net/wireless
parenta93b7aec657e3bd01ef043dff46d3c27dba26bb3 (diff)
ath5k: remove unused beacon timer code
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless')
-rw-r--r--drivers/net/wireless/ath/ath5k/ath5k.h28
-rw-r--r--drivers/net/wireless/ath/ath5k/pcu.c197
2 files changed, 0 insertions, 225 deletions
diff --git a/drivers/net/wireless/ath/ath5k/ath5k.h b/drivers/net/wireless/ath/ath5k/ath5k.h
index 365eccd777a3..1d7491c85460 100644
--- a/drivers/net/wireless/ath/ath5k/ath5k.h
+++ b/drivers/net/wireless/ath/ath5k/ath5k.h
@@ -613,28 +613,6 @@ struct ath5k_rx_status {
613#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 613#define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
614#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 614#define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
615 615
616#if 0
617/**
618 * struct ath5k_beacon_state - Per-station beacon timer state.
619 * @bs_interval: in TU's, can also include the above flags
620 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
621 * Point Coordination Function capable AP
622 */
623struct ath5k_beacon_state {
624 u32 bs_next_beacon;
625 u32 bs_next_dtim;
626 u32 bs_interval;
627 u8 bs_dtim_period;
628 u8 bs_cfp_period;
629 u16 bs_cfp_max_duration;
630 u16 bs_cfp_du_remain;
631 u16 bs_tim_offset;
632 u16 bs_sleep_duration;
633 u16 bs_bmiss_threshold;
634 u32 bs_cfp_next;
635};
636#endif
637
638 616
639/* 617/*
640 * TSF to TU conversion: 618 * TSF to TU conversion:
@@ -1212,12 +1190,6 @@ u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1212void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1190void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1213void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1191void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1214void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1192void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1215#if 0
1216int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
1217 const struct ath5k_beacon_state *state);
1218void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1219int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1220#endif
1221/* ACK bit rate */ 1193/* ACK bit rate */
1222void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high); 1194void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1223/* Clock rate related functions */ 1195/* Clock rate related functions */
diff --git a/drivers/net/wireless/ath/ath5k/pcu.c b/drivers/net/wireless/ath/ath5k/pcu.c
index 9247123c9b6d..1b9fcb842167 100644
--- a/drivers/net/wireless/ath/ath5k/pcu.c
+++ b/drivers/net/wireless/ath/ath5k/pcu.c
@@ -648,203 +648,6 @@ void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
648 648
649} 649}
650 650
651#if 0
652/*
653 * Set beacon timers
654 */
655int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
656 const struct ath5k_beacon_state *state)
657{
658 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
659
660 /*
661 * TODO: should be changed through *state
662 * review struct ath5k_beacon_state struct
663 *
664 * XXX: These are used for cfp period bellow, are they
665 * ok ? Is it O.K. for tsf here to be 0 or should we use
666 * get_tsf ?
667 */
668 u32 dtim_count = 0; /* XXX */
669 u32 cfp_count = 0; /* XXX */
670 u32 tsf = 0; /* XXX */
671
672 ATH5K_TRACE(ah->ah_sc);
673 /* Return on an invalid beacon state */
674 if (state->bs_interval < 1)
675 return -EINVAL;
676
677 interval = state->bs_interval;
678 dtim = state->bs_dtim_period;
679
680 /*
681 * PCF support?
682 */
683 if (state->bs_cfp_period > 0) {
684 /*
685 * Enable PCF mode and set the CFP
686 * (Contention Free Period) and timer registers
687 */
688 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
689 state->bs_interval;
690 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
691 state->bs_interval;
692
693 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
694 AR5K_STA_ID1_DEFAULT_ANTENNA |
695 AR5K_STA_ID1_PCF);
696 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
697 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
698 AR5K_CFP_DUR);
699 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
700 next_cfp)) << 3, AR5K_TIMER2);
701 } else {
702 /* Disable PCF mode */
703 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
704 AR5K_STA_ID1_DEFAULT_ANTENNA |
705 AR5K_STA_ID1_PCF);
706 }
707
708 /*
709 * Enable the beacon timer register
710 */
711 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
712
713 /*
714 * Start the beacon timers
715 */
716 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &
717 ~(AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
718 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
719 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
720 AR5K_BEACON_PERIOD), AR5K_BEACON);
721
722 /*
723 * Write new beacon miss threshold, if it appears to be valid
724 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
725 * and return if its not in range. We can test this by reading value and
726 * setting value to a largest value and seeing which values register.
727 */
728
729 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
730 state->bs_bmiss_threshold);
731
732 /*
733 * Set sleep control register
734 * XXX: Didn't find this in 5210 code but since this register
735 * exists also in ar5k's 5210 headers i leave it as common code.
736 */
737 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
738 (state->bs_sleep_duration - 3) << 3);
739
740 /*
741 * Set enhanced sleep registers on 5212
742 */
743 if (ah->ah_version == AR5K_AR5212) {
744 if (state->bs_sleep_duration > state->bs_interval &&
745 roundup(state->bs_sleep_duration, interval) ==
746 state->bs_sleep_duration)
747 interval = state->bs_sleep_duration;
748
749 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
750 roundup(state->bs_sleep_duration, dtim) ==
751 state->bs_sleep_duration))
752 dtim = state->bs_sleep_duration;
753
754 if (interval > dtim)
755 return -EINVAL;
756
757 next_beacon = interval == dtim ? state->bs_next_dtim :
758 state->bs_next_beacon;
759
760 ath5k_hw_reg_write(ah,
761 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
762 AR5K_SLEEP0_NEXT_DTIM) |
763 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
764 AR5K_SLEEP0_ENH_SLEEP_EN |
765 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
766
767 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
768 AR5K_SLEEP1_NEXT_TIM) |
769 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
770
771 ath5k_hw_reg_write(ah,
772 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
773 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
774 }
775
776 return 0;
777}
778
779/*
780 * Reset beacon timers
781 */
782void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
783{
784 ATH5K_TRACE(ah->ah_sc);
785 /*
786 * Disable beacon timer
787 */
788 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
789
790 /*
791 * Disable some beacon register values
792 */
793 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
794 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
795 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
796}
797
798/*
799 * Wait for beacon queue to finish
800 */
801int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
802{
803 unsigned int i;
804 int ret;
805
806 ATH5K_TRACE(ah->ah_sc);
807
808 /* 5210 doesn't have QCU*/
809 if (ah->ah_version == AR5K_AR5210) {
810 /*
811 * Wait for beaconn queue to finish by checking
812 * Control Register and Beacon Status Register.
813 */
814 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
815 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
816 ||
817 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
818 break;
819 udelay(10);
820 }
821
822 /* Timeout... */
823 if (i <= 0) {
824 /*
825 * Re-schedule the beacon queue
826 */
827 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
828 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
829 AR5K_BCR);
830
831 return -EIO;
832 }
833 ret = 0;
834 } else {
835 /*5211/5212*/
836 ret = ath5k_hw_register_timeout(ah,
837 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
838 AR5K_QCU_STS_FRMPENDCNT, 0, false);
839
840 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
841 return -EIO;
842 }
843
844 return ret;
845}
846#endif
847
848 651
849/*********************\ 652/*********************\
850* Key table functions * 653* Key table functions *
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 00:07:20 -0500