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authorLuciano Coelho <luciano.coelho@nokia.com>2009-08-06 09:25:28 -0400
committerJohn W. Linville <linville@tuxdriver.com>2009-08-14 09:12:46 -0400
commitf5fc0f86b02afef1119b523623b4cde41475bc8c (patch)
tree793be075412781fef4fcd752032e9b3680eaf96f /drivers/net/wireless/wl12xx/wl1271_acx.h
parentb935df01ed4f0848f29b1e39c4f95d87b0206dea (diff)
wl1271: add wl1271 driver files
This driver supports the wl1271 chipset from Texas Instruments based on the WiLink(tm) 6.0 mobile platform. Support for wl1273 should be relatively easy to add. This chipset is designed for embedded devices, with good powersaving capabilities. The wl1271 chipset is the successor of wl1251 and supports the 802.11b/g/n standards, but currently this driver supports only b/g. More information about this chipset can be found here: http://focus.ti.com/general/docs/wtbu/wtbuproductcontent.tsp?templateId=6123&navigationId=12762&contentId=29993 Signed-off-by: Luciano Coelho <luciano.coelho@nokia.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/wl12xx/wl1271_acx.h')
-rw-r--r--drivers/net/wireless/wl12xx/wl1271_acx.h1221
1 files changed, 1221 insertions, 0 deletions
diff --git a/drivers/net/wireless/wl12xx/wl1271_acx.h b/drivers/net/wireless/wl12xx/wl1271_acx.h
new file mode 100644
index 000000000000..9068daaf0ddf
--- /dev/null
+++ b/drivers/net/wireless/wl12xx/wl1271_acx.h
@@ -0,0 +1,1221 @@
1/*
2 * This file is part of wl1271
3 *
4 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
5 * Copyright (C) 2008-2009 Nokia Corporation
6 *
7 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 */
24
25#ifndef __WL1271_ACX_H__
26#define __WL1271_ACX_H__
27
28#include "wl1271.h"
29#include "wl1271_cmd.h"
30
31/*************************************************************************
32
33 Host Interrupt Register (WiLink -> Host)
34
35**************************************************************************/
36/* HW Initiated interrupt Watchdog timer expiration */
37#define WL1271_ACX_INTR_WATCHDOG BIT(0)
38/* Init sequence is done (masked interrupt, detection through polling only ) */
39#define WL1271_ACX_INTR_INIT_COMPLETE BIT(1)
40/* Event was entered to Event MBOX #A*/
41#define WL1271_ACX_INTR_EVENT_A BIT(2)
42/* Event was entered to Event MBOX #B*/
43#define WL1271_ACX_INTR_EVENT_B BIT(3)
44/* Command processing completion*/
45#define WL1271_ACX_INTR_CMD_COMPLETE BIT(4)
46/* Signaling the host on HW wakeup */
47#define WL1271_ACX_INTR_HW_AVAILABLE BIT(5)
48/* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
49#define WL1271_ACX_INTR_DATA BIT(6)
50/* Trace meassge on MBOX #A */
51#define WL1271_ACX_INTR_TRACE_A BIT(7)
52/* Trace meassge on MBOX #B */
53#define WL1271_ACX_INTR_TRACE_B BIT(8)
54
55#define WL1271_ACX_INTR_ALL 0xFFFFFFFF
56#define WL1271_ACX_ALL_EVENTS_VECTOR (WL1271_ACX_INTR_WATCHDOG | \
57 WL1271_ACX_INTR_INIT_COMPLETE | \
58 WL1271_ACX_INTR_EVENT_A | \
59 WL1271_ACX_INTR_EVENT_B | \
60 WL1271_ACX_INTR_CMD_COMPLETE | \
61 WL1271_ACX_INTR_HW_AVAILABLE | \
62 WL1271_ACX_INTR_DATA)
63
64#define WL1271_INTR_MASK (WL1271_ACX_INTR_EVENT_A | \
65 WL1271_ACX_INTR_EVENT_B | \
66 WL1271_ACX_INTR_DATA)
67
68/* Target's information element */
69struct acx_header {
70 struct wl1271_cmd_header cmd;
71
72 /* acx (or information element) header */
73 u16 id;
74
75 /* payload length (not including headers */
76 u16 len;
77};
78
79struct acx_error_counter {
80 struct acx_header header;
81
82 /* The number of PLCP errors since the last time this */
83 /* information element was interrogated. This field is */
84 /* automatically cleared when it is interrogated.*/
85 u32 PLCP_error;
86
87 /* The number of FCS errors since the last time this */
88 /* information element was interrogated. This field is */
89 /* automatically cleared when it is interrogated.*/
90 u32 FCS_error;
91
92 /* The number of MPDUs without PLCP header errors received*/
93 /* since the last time this information element was interrogated. */
94 /* This field is automatically cleared when it is interrogated.*/
95 u32 valid_frame;
96
97 /* the number of missed sequence numbers in the squentially */
98 /* values of frames seq numbers */
99 u32 seq_num_miss;
100} __attribute__ ((packed));
101
102struct acx_revision {
103 struct acx_header header;
104
105 /*
106 * The WiLink firmware version, an ASCII string x.x.x.x,
107 * that uniquely identifies the current firmware.
108 * The left most digit is incremented each time a
109 * significant change is made to the firmware, such as
110 * code redesign or new platform support.
111 * The second digit is incremented when major enhancements
112 * are added or major fixes are made.
113 * The third digit is incremented for each GA release.
114 * The fourth digit is incremented for each build.
115 * The first two digits identify a firmware release version,
116 * in other words, a unique set of features.
117 * The first three digits identify a GA release.
118 */
119 char fw_version[20];
120
121 /*
122 * This 4 byte field specifies the WiLink hardware version.
123 * bits 0 - 15: Reserved.
124 * bits 16 - 23: Version ID - The WiLink version ID
125 * (1 = first spin, 2 = second spin, and so on).
126 * bits 24 - 31: Chip ID - The WiLink chip ID.
127 */
128 u32 hw_version;
129} __attribute__ ((packed));
130
131enum wl1271_psm_mode {
132 /* Active mode */
133 WL1271_PSM_CAM = 0,
134
135 /* Power save mode */
136 WL1271_PSM_PS = 1,
137
138 /* Extreme low power */
139 WL1271_PSM_ELP = 2,
140};
141
142struct acx_sleep_auth {
143 struct acx_header header;
144
145 /* The sleep level authorization of the device. */
146 /* 0 - Always active*/
147 /* 1 - Power down mode: light / fast sleep*/
148 /* 2 - ELP mode: Deep / Max sleep*/
149 u8 sleep_auth;
150 u8 padding[3];
151} __attribute__ ((packed));
152
153enum {
154 HOSTIF_PCI_MASTER_HOST_INDIRECT,
155 HOSTIF_PCI_MASTER_HOST_DIRECT,
156 HOSTIF_SLAVE,
157 HOSTIF_PKT_RING,
158 HOSTIF_DONTCARE = 0xFF
159};
160
161#define DEFAULT_UCAST_PRIORITY 0
162#define DEFAULT_RX_Q_PRIORITY 0
163#define DEFAULT_NUM_STATIONS 1
164#define DEFAULT_RXQ_PRIORITY 0 /* low 0 .. 15 high */
165#define DEFAULT_RXQ_TYPE 0x07 /* All frames, Data/Ctrl/Mgmt */
166#define TRACE_BUFFER_MAX_SIZE 256
167
168#define DP_RX_PACKET_RING_CHUNK_SIZE 1600
169#define DP_TX_PACKET_RING_CHUNK_SIZE 1600
170#define DP_RX_PACKET_RING_CHUNK_NUM 2
171#define DP_TX_PACKET_RING_CHUNK_NUM 2
172#define DP_TX_COMPLETE_TIME_OUT 20
173#define FW_TX_CMPLT_BLOCK_SIZE 16
174
175#define TX_MSDU_LIFETIME_MIN 0
176#define TX_MSDU_LIFETIME_MAX 3000
177#define TX_MSDU_LIFETIME_DEF 512
178#define RX_MSDU_LIFETIME_MIN 0
179#define RX_MSDU_LIFETIME_MAX 0xFFFFFFFF
180#define RX_MSDU_LIFETIME_DEF 512000
181
182struct acx_rx_msdu_lifetime {
183 struct acx_header header;
184
185 /*
186 * The maximum amount of time, in TU, before the
187 * firmware discards the MSDU.
188 */
189 u32 lifetime;
190} __attribute__ ((packed));
191
192/*
193 * RX Config Options Table
194 * Bit Definition
195 * === ==========
196 * 31:14 Reserved
197 * 13 Copy RX Status - when set, write three receive status words
198 * to top of rx'd MPDUs.
199 * When cleared, do not write three status words (added rev 1.5)
200 * 12 Reserved
201 * 11 RX Complete upon FCS error - when set, give rx complete
202 * interrupt for FCS errors, after the rx filtering, e.g. unicast
203 * frames not to us with FCS error will not generate an interrupt.
204 * 10 SSID Filter Enable - When set, the WiLink discards all beacon,
205 * probe request, and probe response frames with an SSID that does
206 * not match the SSID specified by the host in the START/JOIN
207 * command.
208 * When clear, the WiLink receives frames with any SSID.
209 * 9 Broadcast Filter Enable - When set, the WiLink discards all
210 * broadcast frames. When clear, the WiLink receives all received
211 * broadcast frames.
212 * 8:6 Reserved
213 * 5 BSSID Filter Enable - When set, the WiLink discards any frames
214 * with a BSSID that does not match the BSSID specified by the
215 * host.
216 * When clear, the WiLink receives frames from any BSSID.
217 * 4 MAC Addr Filter - When set, the WiLink discards any frames
218 * with a destination address that does not match the MAC address
219 * of the adaptor.
220 * When clear, the WiLink receives frames destined to any MAC
221 * address.
222 * 3 Promiscuous - When set, the WiLink receives all valid frames
223 * (i.e., all frames that pass the FCS check).
224 * When clear, only frames that pass the other filters specified
225 * are received.
226 * 2 FCS - When set, the WiLink includes the FCS with the received
227 * frame.
228 * When cleared, the FCS is discarded.
229 * 1 PLCP header - When set, write all data from baseband to frame
230 * buffer including PHY header.
231 * 0 Reserved - Always equal to 0.
232 *
233 * RX Filter Options Table
234 * Bit Definition
235 * === ==========
236 * 31:12 Reserved - Always equal to 0.
237 * 11 Association - When set, the WiLink receives all association
238 * related frames (association request/response, reassocation
239 * request/response, and disassociation). When clear, these frames
240 * are discarded.
241 * 10 Auth/De auth - When set, the WiLink receives all authentication
242 * and de-authentication frames. When clear, these frames are
243 * discarded.
244 * 9 Beacon - When set, the WiLink receives all beacon frames.
245 * When clear, these frames are discarded.
246 * 8 Contention Free - When set, the WiLink receives all contention
247 * free frames.
248 * When clear, these frames are discarded.
249 * 7 Control - When set, the WiLink receives all control frames.
250 * When clear, these frames are discarded.
251 * 6 Data - When set, the WiLink receives all data frames.
252 * When clear, these frames are discarded.
253 * 5 FCS Error - When set, the WiLink receives frames that have FCS
254 * errors.
255 * When clear, these frames are discarded.
256 * 4 Management - When set, the WiLink receives all management
257 * frames.
258 * When clear, these frames are discarded.
259 * 3 Probe Request - When set, the WiLink receives all probe request
260 * frames.
261 * When clear, these frames are discarded.
262 * 2 Probe Response - When set, the WiLink receives all probe
263 * response frames.
264 * When clear, these frames are discarded.
265 * 1 RTS/CTS/ACK - When set, the WiLink receives all RTS, CTS and ACK
266 * frames.
267 * When clear, these frames are discarded.
268 * 0 Rsvd Type/Sub Type - When set, the WiLink receives all frames
269 * that have reserved frame types and sub types as defined by the
270 * 802.11 specification.
271 * When clear, these frames are discarded.
272 */
273struct acx_rx_config {
274 struct acx_header header;
275
276 u32 config_options;
277 u32 filter_options;
278} __attribute__ ((packed));
279
280struct acx_packet_detection {
281 struct acx_header header;
282
283 u32 threshold;
284} __attribute__ ((packed));
285
286
287enum acx_slot_type {
288 SLOT_TIME_LONG = 0,
289 SLOT_TIME_SHORT = 1,
290 DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
291 MAX_SLOT_TIMES = 0xFF
292};
293
294#define STATION_WONE_INDEX 0
295
296struct acx_slot {
297 struct acx_header header;
298
299 u8 wone_index; /* Reserved */
300 u8 slot_time;
301 u8 reserved[6];
302} __attribute__ ((packed));
303
304
305#define ADDRESS_GROUP_MAX (8)
306#define ADDRESS_GROUP_MAX_LEN (ETH_ALEN * ADDRESS_GROUP_MAX)
307
308struct acx_dot11_grp_addr_tbl {
309 struct acx_header header;
310
311 u8 enabled;
312 u8 num_groups;
313 u8 pad[2];
314 u8 mac_table[ADDRESS_GROUP_MAX_LEN];
315} __attribute__ ((packed));
316
317
318#define RX_TIMEOUT_PS_POLL_MIN 0
319#define RX_TIMEOUT_PS_POLL_MAX (200000)
320#define RX_TIMEOUT_PS_POLL_DEF (15)
321#define RX_TIMEOUT_UPSD_MIN 0
322#define RX_TIMEOUT_UPSD_MAX (200000)
323#define RX_TIMEOUT_UPSD_DEF (15)
324
325struct acx_rx_timeout {
326 struct acx_header header;
327
328 /*
329 * The longest time the STA will wait to receive
330 * traffic from the AP after a PS-poll has been
331 * transmitted.
332 */
333 u16 ps_poll_timeout;
334
335 /*
336 * The longest time the STA will wait to receive
337 * traffic from the AP after a frame has been sent
338 * from an UPSD enabled queue.
339 */
340 u16 upsd_timeout;
341} __attribute__ ((packed));
342
343#define RTS_THRESHOLD_MIN 0
344#define RTS_THRESHOLD_MAX 4096
345#define RTS_THRESHOLD_DEF 2347
346
347struct acx_rts_threshold {
348 struct acx_header header;
349
350 u16 threshold;
351 u8 pad[2];
352} __attribute__ ((packed));
353
354struct acx_beacon_filter_option {
355 struct acx_header header;
356
357 u8 enable;
358
359 /*
360 * The number of beacons without the unicast TIM
361 * bit set that the firmware buffers before
362 * signaling the host about ready frames.
363 * When set to 0 and the filter is enabled, beacons
364 * without the unicast TIM bit set are dropped.
365 */
366 u8 max_num_beacons;
367 u8 pad[2];
368} __attribute__ ((packed));
369
370/*
371 * ACXBeaconFilterEntry (not 221)
372 * Byte Offset Size (Bytes) Definition
373 * =========== ============ ==========
374 * 0 1 IE identifier
375 * 1 1 Treatment bit mask
376 *
377 * ACXBeaconFilterEntry (221)
378 * Byte Offset Size (Bytes) Definition
379 * =========== ============ ==========
380 * 0 1 IE identifier
381 * 1 1 Treatment bit mask
382 * 2 3 OUI
383 * 5 1 Type
384 * 6 2 Version
385 *
386 *
387 * Treatment bit mask - The information element handling:
388 * bit 0 - The information element is compared and transferred
389 * in case of change.
390 * bit 1 - The information element is transferred to the host
391 * with each appearance or disappearance.
392 * Note that both bits can be set at the same time.
393 */
394#define BEACON_FILTER_TABLE_MAX_IE_NUM (32)
395#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
396#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE (2)
397#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
398#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
399 BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
400 (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
401 BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))
402
403struct acx_beacon_filter_ie_table {
404 struct acx_header header;
405
406 u8 num_ie;
407 u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
408 u8 pad[3];
409} __attribute__ ((packed));
410
411enum {
412 SG_ENABLE = 0,
413 SG_DISABLE,
414 SG_SENSE_NO_ACTIVITY,
415 SG_SENSE_ACTIVE
416};
417
418struct acx_bt_wlan_coex {
419 struct acx_header header;
420
421 /*
422 * 0 -> PTA enabled
423 * 1 -> PTA disabled
424 * 2 -> sense no active mode, i.e.
425 * an interrupt is sent upon
426 * BT activity.
427 * 3 -> PTA is switched on in response
428 * to the interrupt sending.
429 */
430 u8 enable;
431 u8 pad[3];
432} __attribute__ ((packed));
433
434#define PTA_ANTENNA_TYPE_DEF (0)
435#define PTA_BT_HP_MAXTIME_DEF (2000)
436#define PTA_WLAN_HP_MAX_TIME_DEF (5000)
437#define PTA_SENSE_DISABLE_TIMER_DEF (1350)
438#define PTA_PROTECTIVE_RX_TIME_DEF (1500)
439#define PTA_PROTECTIVE_TX_TIME_DEF (1500)
440#define PTA_TIMEOUT_NEXT_BT_LP_PACKET_DEF (3000)
441#define PTA_SIGNALING_TYPE_DEF (1)
442#define PTA_AFH_LEVERAGE_ON_DEF (0)
443#define PTA_NUMBER_QUIET_CYCLE_DEF (0)
444#define PTA_MAX_NUM_CTS_DEF (3)
445#define PTA_NUMBER_OF_WLAN_PACKETS_DEF (2)
446#define PTA_NUMBER_OF_BT_PACKETS_DEF (2)
447#define PTA_PROTECTIVE_RX_TIME_FAST_DEF (1500)
448#define PTA_PROTECTIVE_TX_TIME_FAST_DEF (3000)
449#define PTA_CYCLE_TIME_FAST_DEF (8700)
450#define PTA_RX_FOR_AVALANCHE_DEF (5)
451#define PTA_ELP_HP_DEF (0)
452#define PTA_ANTI_STARVE_PERIOD_DEF (500)
453#define PTA_ANTI_STARVE_NUM_CYCLE_DEF (4)
454#define PTA_ALLOW_PA_SD_DEF (1)
455#define PTA_TIME_BEFORE_BEACON_DEF (6300)
456#define PTA_HPDM_MAX_TIME_DEF (1600)
457#define PTA_TIME_OUT_NEXT_WLAN_DEF (2550)
458#define PTA_AUTO_MODE_NO_CTS_DEF (0)
459#define PTA_BT_HP_RESPECTED_DEF (3)
460#define PTA_WLAN_RX_MIN_RATE_DEF (24)
461#define PTA_ACK_MODE_DEF (1)
462
463struct acx_bt_wlan_coex_param {
464 struct acx_header header;
465
466 /*
467 * The minimum rate of a received WLAN packet in the STA,
468 * during protective mode, of which a new BT-HP request
469 * during this Rx will always be respected and gain the antenna.
470 */
471 u32 min_rate;
472
473 /* Max time the BT HP will be respected. */
474 u16 bt_hp_max_time;
475
476 /* Max time the WLAN HP will be respected. */
477 u16 wlan_hp_max_time;
478
479 /*
480 * The time between the last BT activity
481 * and the moment when the sense mode returns
482 * to SENSE_INACTIVE.
483 */
484 u16 sense_disable_timer;
485
486 /* Time before the next BT HP instance */
487 u16 rx_time_bt_hp;
488 u16 tx_time_bt_hp;
489
490 /* range: 10-20000 default: 1500 */
491 u16 rx_time_bt_hp_fast;
492 u16 tx_time_bt_hp_fast;
493
494 /* range: 2000-65535 default: 8700 */
495 u16 wlan_cycle_fast;
496
497 /* range: 0 - 15000 (Msec) default: 1000 */
498 u16 bt_anti_starvation_period;
499
500 /* range 400-10000(Usec) default: 3000 */
501 u16 next_bt_lp_packet;
502
503 /* Deafult: worst case for BT DH5 traffic */
504 u16 wake_up_beacon;
505
506 /* range: 0-50000(Usec) default: 1050 */
507 u16 hp_dm_max_guard_time;
508
509 /*
510 * This is to prevent both BT & WLAN antenna
511 * starvation.
512 * Range: 100-50000(Usec) default:2550
513 */
514 u16 next_wlan_packet;
515
516 /* 0 -> shared antenna */
517 u8 antenna_type;
518
519 /*
520 * 0 -> TI legacy
521 * 1 -> Palau
522 */
523 u8 signal_type;
524
525 /*
526 * BT AFH status
527 * 0 -> no AFH
528 * 1 -> from dedicated GPIO
529 * 2 -> AFH on (from host)
530 */
531 u8 afh_leverage_on;
532
533 /*
534 * The number of cycles during which no
535 * TX will be sent after 1 cycle of RX
536 * transaction in protective mode
537 */
538 u8 quiet_cycle_num;
539
540 /*
541 * The maximum number of CTSs that will
542 * be sent for receiving RX packet in
543 * protective mode
544 */
545 u8 max_cts;
546
547 /*
548 * The number of WLAN packets
549 * transferred in common mode before
550 * switching to BT.
551 */
552 u8 wlan_packets_num;
553
554 /*
555 * The number of BT packets
556 * transferred in common mode before
557 * switching to WLAN.
558 */
559 u8 bt_packets_num;
560
561 /* range: 1-255 default: 5 */
562 u8 missed_rx_avalanche;
563
564 /* range: 0-1 default: 1 */
565 u8 wlan_elp_hp;
566
567 /* range: 0 - 15 default: 4 */
568 u8 bt_anti_starvation_cycles;
569
570 u8 ack_mode_dual_ant;
571
572 /*
573 * Allow PA_SD assertion/de-assertion
574 * during enabled BT activity.
575 */
576 u8 pa_sd_enable;
577
578 /*
579 * Enable/Disable PTA in auto mode:
580 * Support Both Active & P.S modes
581 */
582 u8 pta_auto_mode_enable;
583
584 /* range: 0 - 20 default: 1 */
585 u8 bt_hp_respected_num;
586} __attribute__ ((packed));
587
588#define CCA_THRSH_ENABLE_ENERGY_D 0x140A
589#define CCA_THRSH_DISABLE_ENERGY_D 0xFFEF
590
591struct acx_energy_detection {
592 struct acx_header header;
593
594 /* The RX Clear Channel Assessment threshold in the PHY */
595 u16 rx_cca_threshold;
596 u8 tx_energy_detection;
597 u8 pad;
598} __attribute__ ((packed));
599
600#define BCN_RX_TIMEOUT_DEF_VALUE 10000
601#define BROADCAST_RX_TIMEOUT_DEF_VALUE 20000
602#define RX_BROADCAST_IN_PS_DEF_VALUE 1
603#define CONSECUTIVE_PS_POLL_FAILURE_DEF 4
604
605struct acx_beacon_broadcast {
606 struct acx_header header;
607
608 u16 beacon_rx_timeout;
609 u16 broadcast_timeout;
610
611 /* Enables receiving of broadcast packets in PS mode */
612 u8 rx_broadcast_in_ps;
613
614 /* Consecutive PS Poll failures before updating the host */
615 u8 ps_poll_threshold;
616 u8 pad[2];
617} __attribute__ ((packed));
618
619struct acx_event_mask {
620 struct acx_header header;
621
622 u32 event_mask;
623 u32 high_event_mask; /* Unused */
624} __attribute__ ((packed));
625
626#define CFG_RX_FCS BIT(2)
627#define CFG_RX_ALL_GOOD BIT(3)
628#define CFG_UNI_FILTER_EN BIT(4)
629#define CFG_BSSID_FILTER_EN BIT(5)
630#define CFG_MC_FILTER_EN BIT(6)
631#define CFG_MC_ADDR0_EN BIT(7)
632#define CFG_MC_ADDR1_EN BIT(8)
633#define CFG_BC_REJECT_EN BIT(9)
634#define CFG_SSID_FILTER_EN BIT(10)
635#define CFG_RX_INT_FCS_ERROR BIT(11)
636#define CFG_RX_INT_ENCRYPTED BIT(12)
637#define CFG_RX_WR_RX_STATUS BIT(13)
638#define CFG_RX_FILTER_NULTI BIT(14)
639#define CFG_RX_RESERVE BIT(15)
640#define CFG_RX_TIMESTAMP_TSF BIT(16)
641
642#define CFG_RX_RSV_EN BIT(0)
643#define CFG_RX_RCTS_ACK BIT(1)
644#define CFG_RX_PRSP_EN BIT(2)
645#define CFG_RX_PREQ_EN BIT(3)
646#define CFG_RX_MGMT_EN BIT(4)
647#define CFG_RX_FCS_ERROR BIT(5)
648#define CFG_RX_DATA_EN BIT(6)
649#define CFG_RX_CTL_EN BIT(7)
650#define CFG_RX_CF_EN BIT(8)
651#define CFG_RX_BCN_EN BIT(9)
652#define CFG_RX_AUTH_EN BIT(10)
653#define CFG_RX_ASSOC_EN BIT(11)
654
655#define SCAN_PASSIVE BIT(0)
656#define SCAN_5GHZ_BAND BIT(1)
657#define SCAN_TRIGGERED BIT(2)
658#define SCAN_PRIORITY_HIGH BIT(3)
659
660struct acx_feature_config {
661 struct acx_header header;
662
663 u32 options;
664 u32 data_flow_options;
665} __attribute__ ((packed));
666
667struct acx_current_tx_power {
668 struct acx_header header;
669
670 u8 current_tx_power;
671 u8 padding[3];
672} __attribute__ ((packed));
673
674enum acx_wake_up_event {
675 WAKE_UP_EVENT_BEACON_BITMAP = 0x01, /* Wake on every Beacon*/
676 WAKE_UP_EVENT_DTIM_BITMAP = 0x02, /* Wake on every DTIM*/
677 WAKE_UP_EVENT_N_DTIM_BITMAP = 0x04, /* Wake on every Nth DTIM */
678 WAKE_UP_EVENT_N_BEACONS_BITMAP = 0x08, /* Wake on every Nth Beacon */
679 WAKE_UP_EVENT_BITS_MASK = 0x0F
680};
681
682struct acx_wake_up_condition {
683 struct acx_header header;
684
685 u8 wake_up_event; /* Only one bit can be set */
686 u8 listen_interval;
687 u8 pad[2];
688} __attribute__ ((packed));
689
690struct acx_aid {
691 struct acx_header header;
692
693 /*
694 * To be set when associated with an AP.
695 */
696 u16 aid;
697 u8 pad[2];
698} __attribute__ ((packed));
699
700enum acx_preamble_type {
701 ACX_PREAMBLE_LONG = 0,
702 ACX_PREAMBLE_SHORT = 1
703};
704
705struct acx_preamble {
706 struct acx_header header;
707
708 /*
709 * When set, the WiLink transmits the frames with a short preamble and
710 * when cleared, the WiLink transmits the frames with a long preamble.
711 */
712 u8 preamble;
713 u8 padding[3];
714} __attribute__ ((packed));
715
716enum acx_ctsprotect_type {
717 CTSPROTECT_DISABLE = 0,
718 CTSPROTECT_ENABLE = 1
719};
720
721struct acx_ctsprotect {
722 struct acx_header header;
723 u8 ctsprotect;
724 u8 padding[3];
725} __attribute__ ((packed));
726
727struct acx_tx_statistics {
728 u32 internal_desc_overflow;
729} __attribute__ ((packed));
730
731struct acx_rx_statistics {
732 u32 out_of_mem;
733 u32 hdr_overflow;
734 u32 hw_stuck;
735 u32 dropped;
736 u32 fcs_err;
737 u32 xfr_hint_trig;
738 u32 path_reset;
739 u32 reset_counter;
740} __attribute__ ((packed));
741
742struct acx_dma_statistics {
743 u32 rx_requested;
744 u32 rx_errors;
745 u32 tx_requested;
746 u32 tx_errors;
747} __attribute__ ((packed));
748
749struct acx_isr_statistics {
750 /* host command complete */
751 u32 cmd_cmplt;
752
753 /* fiqisr() */
754 u32 fiqs;
755
756 /* (INT_STS_ND & INT_TRIG_RX_HEADER) */
757 u32 rx_headers;
758
759 /* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
760 u32 rx_completes;
761
762 /* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
763 u32 rx_mem_overflow;
764
765 /* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
766 u32 rx_rdys;
767
768 /* irqisr() */
769 u32 irqs;
770
771 /* (INT_STS_ND & INT_TRIG_TX_PROC) */
772 u32 tx_procs;
773
774 /* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
775 u32 decrypt_done;
776
777 /* (INT_STS_ND & INT_TRIG_DMA0) */
778 u32 dma0_done;
779
780 /* (INT_STS_ND & INT_TRIG_DMA1) */
781 u32 dma1_done;
782
783 /* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
784 u32 tx_exch_complete;
785
786 /* (INT_STS_ND & INT_TRIG_COMMAND) */
787 u32 commands;
788
789 /* (INT_STS_ND & INT_TRIG_RX_PROC) */
790 u32 rx_procs;
791
792 /* (INT_STS_ND & INT_TRIG_PM_802) */
793 u32 hw_pm_mode_changes;
794
795 /* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
796 u32 host_acknowledges;
797
798 /* (INT_STS_ND & INT_TRIG_PM_PCI) */
799 u32 pci_pm;
800
801 /* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
802 u32 wakeups;
803
804 /* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
805 u32 low_rssi;
806} __attribute__ ((packed));
807
808struct acx_wep_statistics {
809 /* WEP address keys configured */
810 u32 addr_key_count;
811
812 /* default keys configured */
813 u32 default_key_count;
814
815 u32 reserved;
816
817 /* number of times that WEP key not found on lookup */
818 u32 key_not_found;
819
820 /* number of times that WEP key decryption failed */
821 u32 decrypt_fail;
822
823 /* WEP packets decrypted */
824 u32 packets;
825
826 /* WEP decrypt interrupts */
827 u32 interrupt;
828} __attribute__ ((packed));
829
830#define ACX_MISSED_BEACONS_SPREAD 10
831
832struct acx_pwr_statistics {
833 /* the amount of enters into power save mode (both PD & ELP) */
834 u32 ps_enter;
835
836 /* the amount of enters into ELP mode */
837 u32 elp_enter;
838
839 /* the amount of missing beacon interrupts to the host */
840 u32 missing_bcns;
841
842 /* the amount of wake on host-access times */
843 u32 wake_on_host;
844
845 /* the amount of wake on timer-expire */
846 u32 wake_on_timer_exp;
847
848 /* the number of packets that were transmitted with PS bit set */
849 u32 tx_with_ps;
850
851 /* the number of packets that were transmitted with PS bit clear */
852 u32 tx_without_ps;
853
854 /* the number of received beacons */
855 u32 rcvd_beacons;
856
857 /* the number of entering into PowerOn (power save off) */
858 u32 power_save_off;
859
860 /* the number of entries into power save mode */
861 u16 enable_ps;
862
863 /*
864 * the number of exits from power save, not including failed PS
865 * transitions
866 */
867 u16 disable_ps;
868
869 /*
870 * the number of times the TSF counter was adjusted because
871 * of drift
872 */
873 u32 fix_tsf_ps;
874
875 /* Gives statistics about the spread continuous missed beacons.
876 * The 16 LSB are dedicated for the PS mode.
877 * The 16 MSB are dedicated for the PS mode.
878 * cont_miss_bcns_spread[0] - single missed beacon.
879 * cont_miss_bcns_spread[1] - two continuous missed beacons.
880 * cont_miss_bcns_spread[2] - three continuous missed beacons.
881 * ...
882 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
883 */
884 u32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
885
886 /* the number of beacons in awake mode */
887 u32 rcvd_awake_beacons;
888} __attribute__ ((packed));
889
890struct acx_mic_statistics {
891 u32 rx_pkts;
892 u32 calc_failure;
893} __attribute__ ((packed));
894
895struct acx_aes_statistics {
896 u32 encrypt_fail;
897 u32 decrypt_fail;
898 u32 encrypt_packets;
899 u32 decrypt_packets;
900 u32 encrypt_interrupt;
901 u32 decrypt_interrupt;
902} __attribute__ ((packed));
903
904struct acx_event_statistics {
905 u32 heart_beat;
906 u32 calibration;
907 u32 rx_mismatch;
908 u32 rx_mem_empty;
909 u32 rx_pool;
910 u32 oom_late;
911 u32 phy_transmit_error;
912 u32 tx_stuck;
913} __attribute__ ((packed));
914
915struct acx_ps_statistics {
916 u32 pspoll_timeouts;
917 u32 upsd_timeouts;
918 u32 upsd_max_sptime;
919 u32 upsd_max_apturn;
920 u32 pspoll_max_apturn;
921 u32 pspoll_utilization;
922 u32 upsd_utilization;
923} __attribute__ ((packed));
924
925struct acx_rxpipe_statistics {
926 u32 rx_prep_beacon_drop;
927 u32 descr_host_int_trig_rx_data;
928 u32 beacon_buffer_thres_host_int_trig_rx_data;
929 u32 missed_beacon_host_int_trig_rx_data;
930 u32 tx_xfr_host_int_trig_rx_data;
931} __attribute__ ((packed));
932
933struct acx_statistics {
934 struct acx_header header;
935
936 struct acx_tx_statistics tx;
937 struct acx_rx_statistics rx;
938 struct acx_dma_statistics dma;
939 struct acx_isr_statistics isr;
940 struct acx_wep_statistics wep;
941 struct acx_pwr_statistics pwr;
942 struct acx_aes_statistics aes;
943 struct acx_mic_statistics mic;
944 struct acx_event_statistics event;
945 struct acx_ps_statistics ps;
946 struct acx_rxpipe_statistics rxpipe;
947} __attribute__ ((packed));
948
949#define ACX_MAX_RATE_CLASSES 8
950#define ACX_RATE_MASK_UNSPECIFIED 0
951#define ACX_RATE_MASK_ALL 0x1eff
952#define ACX_RATE_RETRY_LIMIT 10
953
954struct acx_rate_class {
955 u32 enabled_rates;
956 u8 short_retry_limit;
957 u8 long_retry_limit;
958 u8 aflags;
959 u8 reserved;
960};
961
962struct acx_rate_policy {
963 struct acx_header header;
964
965 u32 rate_class_cnt;
966 struct acx_rate_class rate_class[ACX_MAX_RATE_CLASSES];
967} __attribute__ ((packed));
968
969#define WL1271_ACX_AC_COUNT 4
970
971struct acx_ac_cfg {
972 struct acx_header header;
973 u8 ac;
974 u8 cw_min;
975 u16 cw_max;
976 u8 aifsn;
977 u8 reserved;
978 u16 tx_op_limit;
979} __attribute__ ((packed));
980
981enum wl1271_acx_ac {
982 WL1271_ACX_AC_BE = 0,
983 WL1271_ACX_AC_BK = 1,
984 WL1271_ACX_AC_VI = 2,
985 WL1271_ACX_AC_VO = 3,
986 WL1271_ACX_AC_CTS2SELF = 4,
987 WL1271_ACX_AC_ANY_TID = 0x1F,
988 WL1271_ACX_AC_INVALID = 0xFF,
989};
990
991enum wl1271_acx_ps_scheme {
992 WL1271_ACX_PS_SCHEME_LEGACY = 0,
993 WL1271_ACX_PS_SCHEME_UPSD_TRIGGER = 1,
994 WL1271_ACX_PS_SCHEME_LEGACY_PSPOLL = 2,
995 WL1271_ACX_PS_SCHEME_SAPSD = 3,
996};
997
998enum wl1271_acx_ack_policy {
999 WL1271_ACX_ACK_POLICY_LEGACY = 0,
1000 WL1271_ACX_ACK_POLICY_NO_ACK = 1,
1001 WL1271_ACX_ACK_POLICY_BLOCK = 2,
1002};
1003
1004#define WL1271_ACX_TID_COUNT 7
1005
1006struct acx_tid_config {
1007 struct acx_header header;
1008 u8 queue_id;
1009 u8 channel_type;
1010 u8 tsid;
1011 u8 ps_scheme;
1012 u8 ack_policy;
1013 u8 padding[3];
1014 u32 apsd_conf[2];
1015} __attribute__ ((packed));
1016
1017struct acx_frag_threshold {
1018 struct acx_header header;
1019 u16 frag_threshold;
1020 u8 padding[2];
1021} __attribute__ ((packed));
1022
1023#define WL1271_ACX_TX_COMPL_TIMEOUT 5
1024#define WL1271_ACX_TX_COMPL_THRESHOLD 5
1025
1026struct acx_tx_config_options {
1027 struct acx_header header;
1028 u16 tx_compl_timeout; /* msec */
1029 u16 tx_compl_threshold; /* number of packets */
1030} __attribute__ ((packed));
1031
1032#define ACX_RX_MEM_BLOCKS 64
1033#define ACX_TX_MIN_MEM_BLOCKS 64
1034#define ACX_TX_DESCRIPTORS 32
1035#define ACX_NUM_SSID_PROFILES 1
1036
1037struct wl1271_acx_config_memory {
1038 struct acx_header header;
1039
1040 u8 rx_mem_block_num;
1041 u8 tx_min_mem_block_num;
1042 u8 num_stations;
1043 u8 num_ssid_profiles;
1044 u32 total_tx_descriptors;
1045} __attribute__ ((packed));
1046
1047struct wl1271_acx_mem_map {
1048 struct acx_header header;
1049
1050 void *code_start;
1051 void *code_end;
1052
1053 void *wep_defkey_start;
1054 void *wep_defkey_end;
1055
1056 void *sta_table_start;
1057 void *sta_table_end;
1058
1059 void *packet_template_start;
1060 void *packet_template_end;
1061
1062 /* Address of the TX result interface (control block) */
1063 u32 tx_result;
1064 u32 tx_result_queue_start;
1065
1066 void *queue_memory_start;
1067 void *queue_memory_end;
1068
1069 u32 packet_memory_pool_start;
1070 u32 packet_memory_pool_end;
1071
1072 void *debug_buffer1_start;
1073 void *debug_buffer1_end;
1074
1075 void *debug_buffer2_start;
1076 void *debug_buffer2_end;
1077
1078 /* Number of blocks FW allocated for TX packets */
1079 u32 num_tx_mem_blocks;
1080
1081 /* Number of blocks FW allocated for RX packets */
1082 u32 num_rx_mem_blocks;
1083
1084 /* the following 4 fields are valid in SLAVE mode only */
1085 u8 *tx_cbuf;
1086 u8 *rx_cbuf;
1087 void *rx_ctrl;
1088 void *tx_ctrl;
1089} __attribute__ ((packed));
1090
1091enum wl1271_acx_rx_queue_type {
1092 RX_QUEUE_TYPE_RX_LOW_PRIORITY, /* All except the high priority */
1093 RX_QUEUE_TYPE_RX_HIGH_PRIORITY, /* Management and voice packets */
1094 RX_QUEUE_TYPE_NUM,
1095 RX_QUEUE_TYPE_MAX = USHORT_MAX
1096};
1097
1098#define WL1271_RX_INTR_THRESHOLD_DEF 0 /* no pacing, send interrupt on
1099 * every event */
1100#define WL1271_RX_INTR_THRESHOLD_MIN 0
1101#define WL1271_RX_INTR_THRESHOLD_MAX 15
1102
1103#define WL1271_RX_INTR_TIMEOUT_DEF 5
1104#define WL1271_RX_INTR_TIMEOUT_MIN 1
1105#define WL1271_RX_INTR_TIMEOUT_MAX 100
1106
1107struct wl1271_acx_rx_config_opt {
1108 struct acx_header header;
1109
1110 u16 mblk_threshold;
1111 u16 threshold;
1112 u16 timeout;
1113 u8 queue_type;
1114 u8 reserved;
1115} __attribute__ ((packed));
1116
1117enum {
1118 ACX_WAKE_UP_CONDITIONS = 0x0002,
1119 ACX_MEM_CFG = 0x0003,
1120 ACX_SLOT = 0x0004,
1121 ACX_AC_CFG = 0x0007,
1122 ACX_MEM_MAP = 0x0008,
1123 ACX_AID = 0x000A,
1124 /* ACX_FW_REV is missing in the ref driver, but seems to work */
1125 ACX_FW_REV = 0x000D,
1126 ACX_MEDIUM_USAGE = 0x000F,
1127 ACX_RX_CFG = 0x0010,
1128 ACX_TX_QUEUE_CFG = 0x0011, /* FIXME: only used by wl1251 */
1129 ACX_STATISTICS = 0x0013, /* Debug API */
1130 ACX_PWR_CONSUMPTION_STATISTICS = 0x0014,
1131 ACX_FEATURE_CFG = 0x0015,
1132 ACX_TID_CFG = 0x001A,
1133 ACX_PS_RX_STREAMING = 0x001B,
1134 ACX_BEACON_FILTER_OPT = 0x001F,
1135 ACX_NOISE_HIST = 0x0021,
1136 ACX_HDK_VERSION = 0x0022, /* ??? */
1137 ACX_PD_THRESHOLD = 0x0023,
1138 ACX_TX_CONFIG_OPT = 0x0024,
1139 ACX_CCA_THRESHOLD = 0x0025,
1140 ACX_EVENT_MBOX_MASK = 0x0026,
1141 ACX_CONN_MONIT_PARAMS = 0x002D,
1142 ACX_CONS_TX_FAILURE = 0x002F,
1143 ACX_BCN_DTIM_OPTIONS = 0x0031,
1144 ACX_SG_ENABLE = 0x0032,
1145 ACX_SG_CFG = 0x0033,
1146 ACX_BEACON_FILTER_TABLE = 0x0038,
1147 ACX_ARP_IP_FILTER = 0x0039,
1148 ACX_ROAMING_STATISTICS_TBL = 0x003B,
1149 ACX_RATE_POLICY = 0x003D,
1150 ACX_CTS_PROTECTION = 0x003E,
1151 ACX_SLEEP_AUTH = 0x003F,
1152 ACX_PREAMBLE_TYPE = 0x0040,
1153 ACX_ERROR_CNT = 0x0041,
1154 ACX_IBSS_FILTER = 0x0044,
1155 ACX_SERVICE_PERIOD_TIMEOUT = 0x0045,
1156 ACX_TSF_INFO = 0x0046,
1157 ACX_CONFIG_PS_WMM = 0x0049,
1158 ACX_ENABLE_RX_DATA_FILTER = 0x004A,
1159 ACX_SET_RX_DATA_FILTER = 0x004B,
1160 ACX_GET_DATA_FILTER_STATISTICS = 0x004C,
1161 ACX_RX_CONFIG_OPT = 0x004E,
1162 ACX_FRAG_CFG = 0x004F,
1163 ACX_BET_ENABLE = 0x0050,
1164 ACX_RSSI_SNR_TRIGGER = 0x0051,
1165 ACX_RSSI_SNR_WEIGHTS = 0x0051,
1166 ACX_KEEP_ALIVE_MODE = 0x0052,
1167 ACX_SET_KEEP_ALIVE_CONFIG = 0x0054,
1168 ACX_BA_SESSION_RESPONDER_POLICY = 0x0055,
1169 ACX_BA_SESSION_INITIATOR_POLICY = 0x0056,
1170 ACX_PEER_HT_CAP = 0x0057,
1171 ACX_HT_BSS_OPERATION = 0x0058,
1172 ACX_COEX_ACTIVITY = 0x0059,
1173 DOT11_RX_MSDU_LIFE_TIME = 0x1004,
1174 DOT11_CUR_TX_PWR = 0x100D,
1175 DOT11_RX_DOT11_MODE = 0x1012,
1176 DOT11_RTS_THRESHOLD = 0x1013,
1177 DOT11_GROUP_ADDRESS_TBL = 0x1014,
1178
1179 MAX_DOT11_IE = DOT11_GROUP_ADDRESS_TBL,
1180
1181 MAX_IE = 0xFFFF
1182};
1183
1184
1185int wl1271_acx_wake_up_conditions(struct wl1271 *wl, u8 wake_up_event,
1186 u8 listen_interval);
1187int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1188int wl1271_acx_fw_version(struct wl1271 *wl, char *buf, size_t len);
1189int wl1271_acx_tx_power(struct wl1271 *wl, int power);
1190int wl1271_acx_feature_cfg(struct wl1271 *wl);
1191int wl1271_acx_mem_map(struct wl1271 *wl,
1192 struct acx_header *mem_map, size_t len);
1193int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl, u32 life_time);
1194int wl1271_acx_rx_config(struct wl1271 *wl, u32 config, u32 filter);
1195int wl1271_acx_pd_threshold(struct wl1271 *wl);
1196int wl1271_acx_slot(struct wl1271 *wl, enum acx_slot_type slot_time);
1197int wl1271_acx_group_address_tbl(struct wl1271 *wl);
1198int wl1271_acx_service_period_timeout(struct wl1271 *wl);
1199int wl1271_acx_rts_threshold(struct wl1271 *wl, u16 rts_threshold);
1200int wl1271_acx_beacon_filter_opt(struct wl1271 *wl);
1201int wl1271_acx_beacon_filter_table(struct wl1271 *wl);
1202int wl1271_acx_sg_enable(struct wl1271 *wl);
1203int wl1271_acx_sg_cfg(struct wl1271 *wl);
1204int wl1271_acx_cca_threshold(struct wl1271 *wl);
1205int wl1271_acx_bcn_dtim_options(struct wl1271 *wl);
1206int wl1271_acx_aid(struct wl1271 *wl, u16 aid);
1207int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1208int wl1271_acx_set_preamble(struct wl1271 *wl, enum acx_preamble_type preamble);
1209int wl1271_acx_cts_protect(struct wl1271 *wl,
1210 enum acx_ctsprotect_type ctsprotect);
1211int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats);
1212int wl1271_acx_rate_policies(struct wl1271 *wl);
1213int wl1271_acx_ac_cfg(struct wl1271 *wl);
1214int wl1271_acx_tid_cfg(struct wl1271 *wl);
1215int wl1271_acx_frag_threshold(struct wl1271 *wl);
1216int wl1271_acx_tx_config_options(struct wl1271 *wl);
1217int wl1271_acx_mem_cfg(struct wl1271 *wl);
1218int wl1271_acx_init_mem_config(struct wl1271 *wl);
1219int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
1220
1221#endif /* __WL1271_ACX_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:27:28 -0500