wlcore: Propagate errors from wl1271_raw_read32

Propagate errors from wl1271_raw_read32. Since the read functions had no
way of returning errors in-band, change their prototypes.
Also rename prefixes of wlcore functions which their prototypes had to
be changed.

Signed-off-by: Ido Yariv <ido@wizery.com>
Signed-off-by: Luciano Coelho <coelho@ti.com>

1 files changed, 82 insertions, 32 deletions

diff --git a/drivers/net/wireless/ti/wl18xx/main.c b/drivers/net/wireless/ti/wl18xx/main.c
index 974a6ff11f6d..f99f003ab182 100644
--- a/drivers/net/wireless/ti/wl18xx/main.c
+++ b/drivers/net/wireless/ti/wl18xx/main.c
@@ -636,45 +636,67 @@ out:
         return ret;
 }
 
-static void wl18xx_set_clk(struct wl1271 *wl)
+static int wl18xx_set_clk(struct wl1271 *wl)
 {
-        u32 clk_freq;
+        u16 clk_freq;
+        int ret;
 
         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 
         /* TODO: PG2: apparently we need to read the clk type */
 
-        clk_freq = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT);
+        ret = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT, &clk_freq);
+        if (ret < 0)
+                goto out;
+
         wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
                      wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
                      wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
                      wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
 
-        wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, wl18xx_clk_table[clk_freq].n);
-        wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M, wl18xx_clk_table[clk_freq].m);
+        ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N,
+                                   wl18xx_clk_table[clk_freq].n);
+        if (ret < 0)
+                goto out;
+
+        ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M,
+                                   wl18xx_clk_table[clk_freq].m);
+        if (ret < 0)
+                goto out;
 
         if (wl18xx_clk_table[clk_freq].swallow) {
                 /* first the 16 lower bits */
-                wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
-                                     wl18xx_clk_table[clk_freq].q &
-                                     PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
+                ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
+                                           wl18xx_clk_table[clk_freq].q &
+                                           PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
+                if (ret < 0)
+                        goto out;
+
                 /* then the 16 higher bits, masked out */
-                wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
-                                     (wl18xx_clk_table[clk_freq].q >> 16) &
-                                     PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
+                ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
+                                        (wl18xx_clk_table[clk_freq].q >> 16) &
+                                        PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
+                if (ret < 0)
+                        goto out;
 
                 /* first the 16 lower bits */
-                wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
-                                     wl18xx_clk_table[clk_freq].p &
-                                     PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
+                ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
+                                           wl18xx_clk_table[clk_freq].p &
+                                           PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
+                if (ret < 0)
+                        goto out;
+
                 /* then the 16 higher bits, masked out */
-                wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
-                                     (wl18xx_clk_table[clk_freq].p >> 16) &
-                                     PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
+                ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
+                                        (wl18xx_clk_table[clk_freq].p >> 16) &
+                                        PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
         } else {
-                wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
-                                     PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
+                ret = wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
+                                           PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
         }
+
+out:
+        return ret;
 }
 
 static void wl18xx_boot_soft_reset(struct wl1271 *wl)
@@ -688,7 +710,11 @@ static void wl18xx_boot_soft_reset(struct wl1271 *wl)
 
 static int wl18xx_pre_boot(struct wl1271 *wl)
 {
-        wl18xx_set_clk(wl);
+        int ret;
+
+        ret = wl18xx_set_clk(wl);
+        if (ret < 0)
+                goto out;
 
         /* Continue the ELP wake up sequence */
         wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
@@ -701,23 +727,30 @@ static int wl18xx_pre_boot(struct wl1271 *wl)
 
         wl18xx_boot_soft_reset(wl);
 
-        return 0;
+out:
+        return ret;
 }
 
-static void wl18xx_pre_upload(struct wl1271 *wl)
+static int wl18xx_pre_upload(struct wl1271 *wl)
 {
         u32 tmp;
+        int ret;
 
         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 
         /* TODO: check if this is all needed */
         wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
 
-        tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
+        ret = wlcore_read_reg(wl, REG_CHIP_ID_B, &tmp);
+        if (ret < 0)
+                goto out;
 
         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 
-        tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
+        ret = wlcore_read32(wl, WL18XX_SCR_PAD2, &tmp);
+
+out:
+        return ret;
 }
 
 static int wl18xx_set_mac_and_phy(struct wl1271 *wl)
@@ -766,7 +799,9 @@ static int wl18xx_boot(struct wl1271 *wl)
         if (ret < 0)
                 goto out;
 
-        wl18xx_pre_upload(wl);
+        ret = wl18xx_pre_upload(wl);
+        if (ret < 0)
+                goto out;
 
         ret = wlcore_boot_upload_firmware(wl);
         if (ret < 0)
@@ -998,18 +1033,24 @@ static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
         }
 }
 
-static s8 wl18xx_get_pg_ver(struct wl1271 *wl)
+static int wl18xx_get_pg_ver(struct wl1271 *wl, s8 *ver)
 {
         u32 fuse;
+        int ret;
 
         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 
-        fuse = wl1271_read32(wl, WL18XX_REG_FUSE_DATA_1_3);
-        fuse = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
+        ret = wlcore_read32(wl, WL18XX_REG_FUSE_DATA_1_3, &fuse);
+        if (ret < 0)
+                goto out;
+
+        if (ver)
+                *ver = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
 
         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 
-        return (s8)fuse;
+out:
+        return ret;
 }
 
 #define WL18XX_CONF_FILE_NAME "ti-connectivity/wl18xx-conf.bin"
@@ -1080,14 +1121,20 @@ static int wl18xx_plt_init(struct wl1271 *wl)
         return wl->ops->boot(wl);
 }
 
-static void wl18xx_get_mac(struct wl1271 *wl)
+static int wl18xx_get_mac(struct wl1271 *wl)
 {
         u32 mac1, mac2;
+        int ret;
 
         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 
-        mac1 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1);
-        mac2 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2);
+        ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1, &mac1);
+        if (ret < 0)
+                goto out;
+
+        ret = wlcore_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2, &mac2);
+        if (ret < 0)
+                goto out;
 
         /* these are the two parts of the BD_ADDR */
         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
@@ -1095,6 +1142,9 @@ static void wl18xx_get_mac(struct wl1271 *wl)
         wl->fuse_nic_addr = (mac1 & 0xffffff);
 
         wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
+
+out:
+        return ret;
 }
 
 static int wl18xx_handle_static_data(struct wl1271 *wl,