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authorLinus Torvalds <torvalds@linux-foundation.org>2011-03-16 19:29:25 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-16 19:29:25 -0400
commit7a6362800cb7d1d618a697a650c7aaed3eb39320 (patch)
tree087f9bc6c13ef1fad4b392c5cf9325cd28fa8523 /drivers/net/wireless/rtlwifi
parent6445ced8670f37cfc2c5e24a9de9b413dbfc788d (diff)
parentceda86a108671294052cbf51660097b6534672f5 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1480 commits) bonding: enable netpoll without checking link status xfrm: Refcount destination entry on xfrm_lookup net: introduce rx_handler results and logic around that bonding: get rid of IFF_SLAVE_INACTIVE netdev->priv_flag bonding: wrap slave state work net: get rid of multiple bond-related netdevice->priv_flags bonding: register slave pointer for rx_handler be2net: Bump up the version number be2net: Copyright notice change. Update to Emulex instead of ServerEngines e1000e: fix kconfig for crc32 dependency netfilter ebtables: fix xt_AUDIT to work with ebtables xen network backend driver bonding: Improve syslog message at device creation time bonding: Call netif_carrier_off after register_netdevice bonding: Incorrect TX queue offset net_sched: fix ip_tos2prio xfrm: fix __xfrm_route_forward() be2net: Fix UDP packet detected status in RX compl Phonet: fix aligned-mode pipe socket buffer header reserve netxen: support for GbE port settings ... Fix up conflicts in drivers/staging/brcm80211/brcmsmac/wl_mac80211.c with the staging updates.
Diffstat (limited to 'drivers/net/wireless/rtlwifi')
-rw-r--r--drivers/net/wireless/rtlwifi/Kconfig24
-rw-r--r--drivers/net/wireless/rtlwifi/Makefile15
-rw-r--r--drivers/net/wireless/rtlwifi/base.c91
-rw-r--r--drivers/net/wireless/rtlwifi/base.h39
-rw-r--r--drivers/net/wireless/rtlwifi/core.c26
-rw-r--r--drivers/net/wireless/rtlwifi/debug.h1
-rw-r--r--drivers/net/wireless/rtlwifi/efuse.c18
-rw-r--r--drivers/net/wireless/rtlwifi/efuse.h3
-rw-r--r--drivers/net/wireless/rtlwifi/pci.c152
-rw-r--r--drivers/net/wireless/rtlwifi/pci.h12
-rw-r--r--drivers/net/wireless/rtlwifi/ps.c58
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/Makefile9
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c1398
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/dm_common.h204
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/fw_common.c (renamed from drivers/net/wireless/rtlwifi/rtl8192ce/fw.c)72
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/fw_common.h (renamed from drivers/net/wireless/rtlwifi/rtl8192ce/fw.h)0
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/main.c39
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c2042
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192c/phy_common.h246
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/Makefile3
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/def.h144
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/dm.c1364
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/dm.h1
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/hw.c158
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/hw.h11
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/led.c6
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/phy.c2081
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/phy.h35
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/reg.h73
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/rf.c10
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/rf.h5
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/sw.c22
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/sw.h14
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/trx.c183
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192ce/trx.h464
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/Makefile14
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/def.h62
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/dm.c113
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/dm.h32
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/hw.c2504
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/hw.h116
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/led.c142
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/led.h37
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/mac.c1144
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/mac.h180
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/phy.c607
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/phy.h36
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/reg.h30
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/rf.c493
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/rf.h47
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/sw.c336
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/sw.h53
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/table.c1888
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/table.h71
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/trx.c687
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192cu/trx.h430
-rw-r--r--drivers/net/wireless/rtlwifi/usb.c1035
-rw-r--r--drivers/net/wireless/rtlwifi/usb.h164
-rw-r--r--drivers/net/wireless/rtlwifi/wifi.h680
59 files changed, 15600 insertions, 4324 deletions
diff --git a/drivers/net/wireless/rtlwifi/Kconfig b/drivers/net/wireless/rtlwifi/Kconfig
index 7f6573f7f470..ce49e0ce7cad 100644
--- a/drivers/net/wireless/rtlwifi/Kconfig
+++ b/drivers/net/wireless/rtlwifi/Kconfig
@@ -1,15 +1,33 @@
1config RTL8192CE 1config RTL8192CE
2 tristate "Realtek RTL8192CE/RTL8188SE Wireless Network Adapter" 2 tristate "Realtek RTL8192CE/RTL8188CE Wireless Network Adapter"
3 depends on MAC80211 && EXPERIMENTAL 3 depends on MAC80211 && PCI && EXPERIMENTAL
4 select FW_LOADER 4 select FW_LOADER
5 select RTLWIFI 5 select RTLWIFI
6 select RTL8192C_COMMON
6 ---help--- 7 ---help---
7 This is the driver for Realtek RTL8192CE/RTL8188CE 802.11n PCIe 8 This is the driver for Realtek RTL8192CE/RTL8188CE 802.11n PCIe
8 wireless network adapters. 9 wireless network adapters.
9 10
10 If you choose to build it as a module, it will be called rtl8192ce 11 If you choose to build it as a module, it will be called rtl8192ce
11 12
13config RTL8192CU
14 tristate "Realtek RTL8192CU/RTL8188CU USB Wireless Network Adapter"
15 depends on MAC80211 && USB && EXPERIMENTAL
16 select FW_LOADER
17 select RTLWIFI
18 select RTL8192C_COMMON
19 ---help---
20 This is the driver for Realtek RTL8192CU/RTL8188CU 802.11n USB
21 wireless network adapters.
22
23 If you choose to build it as a module, it will be called rtl8192cu
24
12config RTLWIFI 25config RTLWIFI
13 tristate 26 tristate
14 depends on RTL8192CE 27 depends on RTL8192CE || RTL8192CU
28 default m
29
30config RTL8192C_COMMON
31 tristate
32 depends on RTL8192CE || RTL8192CU
15 default m 33 default m
diff --git a/drivers/net/wireless/rtlwifi/Makefile b/drivers/net/wireless/rtlwifi/Makefile
index 2a7a4384f8ee..ec9393f24799 100644
--- a/drivers/net/wireless/rtlwifi/Makefile
+++ b/drivers/net/wireless/rtlwifi/Makefile
@@ -5,9 +5,22 @@ rtlwifi-objs := \
5 core.o \ 5 core.o \
6 debug.o \ 6 debug.o \
7 efuse.o \ 7 efuse.o \
8 pci.o \
9 ps.o \ 8 ps.o \
10 rc.o \ 9 rc.o \
11 regd.o 10 regd.o
12 11
12rtl8192c_common-objs += \
13
14ifneq ($(CONFIG_PCI),)
15rtlwifi-objs += pci.o
16endif
17
18ifneq ($(CONFIG_USB),)
19rtlwifi-objs += usb.o
20endif
21
22obj-$(CONFIG_RTL8192C_COMMON) += rtl8192c/
13obj-$(CONFIG_RTL8192CE) += rtl8192ce/ 23obj-$(CONFIG_RTL8192CE) += rtl8192ce/
24obj-$(CONFIG_RTL8192CU) += rtl8192cu/
25
26ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/base.c b/drivers/net/wireless/rtlwifi/base.c
index cf0b73e51fc2..bb0c781f4a1b 100644
--- a/drivers/net/wireless/rtlwifi/base.c
+++ b/drivers/net/wireless/rtlwifi/base.c
@@ -144,7 +144,7 @@ static void _rtl_init_hw_ht_capab(struct ieee80211_hw *hw,
144 ht_cap->mcs.rx_mask[1] = 0xFF; 144 ht_cap->mcs.rx_mask[1] = 0xFF;
145 ht_cap->mcs.rx_mask[4] = 0x01; 145 ht_cap->mcs.rx_mask[4] = 0x01;
146 146
147 ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS15; 147 ht_cap->mcs.rx_highest = cpu_to_le16(MAX_BIT_RATE_40MHZ_MCS15);
148 } else if (get_rf_type(rtlphy) == RF_1T1R) { 148 } else if (get_rf_type(rtlphy) == RF_1T1R) {
149 149
150 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("1T1R\n")); 150 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("1T1R\n"));
@@ -153,7 +153,7 @@ static void _rtl_init_hw_ht_capab(struct ieee80211_hw *hw,
153 ht_cap->mcs.rx_mask[1] = 0x00; 153 ht_cap->mcs.rx_mask[1] = 0x00;
154 ht_cap->mcs.rx_mask[4] = 0x01; 154 ht_cap->mcs.rx_mask[4] = 0x01;
155 155
156 ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS7; 156 ht_cap->mcs.rx_highest = cpu_to_le16(MAX_BIT_RATE_40MHZ_MCS7);
157 } 157 }
158} 158}
159 159
@@ -283,13 +283,7 @@ int rtl_init_core(struct ieee80211_hw *hw)
283 rtlmac->hw = hw; 283 rtlmac->hw = hw;
284 284
285 /* <2> rate control register */ 285 /* <2> rate control register */
286 if (rtl_rate_control_register()) { 286 hw->rate_control_algorithm = "rtl_rc";
287 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
288 ("rtl: Unable to register rtl_rc,"
289 "use default RC !!\n"));
290 } else {
291 hw->rate_control_algorithm = "rtl_rc";
292 }
293 287
294 /* 288 /*
295 * <3> init CRDA must come after init 289 * <3> init CRDA must come after init
@@ -325,8 +319,6 @@ int rtl_init_core(struct ieee80211_hw *hw)
325 319
326void rtl_deinit_core(struct ieee80211_hw *hw) 320void rtl_deinit_core(struct ieee80211_hw *hw)
327{ 321{
328 /*RC*/
329 rtl_rate_control_unregister();
330} 322}
331 323
332void rtl_init_rx_config(struct ieee80211_hw *hw) 324void rtl_init_rx_config(struct ieee80211_hw *hw)
@@ -399,21 +391,21 @@ static void _rtl_query_protection_mode(struct ieee80211_hw *hw,
399 u8 rate_flag = info->control.rates[0].flags; 391 u8 rate_flag = info->control.rates[0].flags;
400 392
401 /* Common Settings */ 393 /* Common Settings */
402 tcb_desc->b_rts_stbc = false; 394 tcb_desc->rts_stbc = false;
403 tcb_desc->b_cts_enable = false; 395 tcb_desc->cts_enable = false;
404 tcb_desc->rts_sc = 0; 396 tcb_desc->rts_sc = 0;
405 tcb_desc->b_rts_bw = false; 397 tcb_desc->rts_bw = false;
406 tcb_desc->b_rts_use_shortpreamble = false; 398 tcb_desc->rts_use_shortpreamble = false;
407 tcb_desc->b_rts_use_shortgi = false; 399 tcb_desc->rts_use_shortgi = false;
408 400
409 if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT) { 401 if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT) {
410 /* Use CTS-to-SELF in protection mode. */ 402 /* Use CTS-to-SELF in protection mode. */
411 tcb_desc->b_rts_enable = true; 403 tcb_desc->rts_enable = true;
412 tcb_desc->b_cts_enable = true; 404 tcb_desc->cts_enable = true;
413 tcb_desc->rts_rate = rtlpriv->cfg->maps[RTL_RC_OFDM_RATE24M]; 405 tcb_desc->rts_rate = rtlpriv->cfg->maps[RTL_RC_OFDM_RATE24M];
414 } else if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) { 406 } else if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
415 /* Use RTS-CTS in protection mode. */ 407 /* Use RTS-CTS in protection mode. */
416 tcb_desc->b_rts_enable = true; 408 tcb_desc->rts_enable = true;
417 tcb_desc->rts_rate = rtlpriv->cfg->maps[RTL_RC_OFDM_RATE24M]; 409 tcb_desc->rts_rate = rtlpriv->cfg->maps[RTL_RC_OFDM_RATE24M];
418 } 410 }
419 411
@@ -429,7 +421,7 @@ static void _rtl_txrate_selectmode(struct ieee80211_hw *hw,
429 if (mac->opmode == NL80211_IFTYPE_STATION) 421 if (mac->opmode == NL80211_IFTYPE_STATION)
430 tcb_desc->ratr_index = 0; 422 tcb_desc->ratr_index = 0;
431 else if (mac->opmode == NL80211_IFTYPE_ADHOC) { 423 else if (mac->opmode == NL80211_IFTYPE_ADHOC) {
432 if (tcb_desc->b_multicast || tcb_desc->b_broadcast) { 424 if (tcb_desc->multicast || tcb_desc->broadcast) {
433 tcb_desc->hw_rate = 425 tcb_desc->hw_rate =
434 rtlpriv->cfg->maps[RTL_RC_CCK_RATE2M]; 426 rtlpriv->cfg->maps[RTL_RC_CCK_RATE2M];
435 tcb_desc->use_driver_rate = 1; 427 tcb_desc->use_driver_rate = 1;
@@ -439,7 +431,7 @@ static void _rtl_txrate_selectmode(struct ieee80211_hw *hw,
439 } 431 }
440 } 432 }
441 433
442 if (rtlpriv->dm.b_useramask) { 434 if (rtlpriv->dm.useramask) {
443 /* TODO we will differentiate adhoc and station futrue */ 435 /* TODO we will differentiate adhoc and station futrue */
444 tcb_desc->mac_id = 0; 436 tcb_desc->mac_id = 0;
445 437
@@ -461,19 +453,19 @@ static void _rtl_query_bandwidth_mode(struct ieee80211_hw *hw,
461 struct rtl_priv *rtlpriv = rtl_priv(hw); 453 struct rtl_priv *rtlpriv = rtl_priv(hw);
462 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 454 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
463 455
464 tcb_desc->b_packet_bw = false; 456 tcb_desc->packet_bw = false;
465 457
466 if (!mac->bw_40 || !mac->ht_enable) 458 if (!mac->bw_40 || !mac->ht_enable)
467 return; 459 return;
468 460
469 if (tcb_desc->b_multicast || tcb_desc->b_broadcast) 461 if (tcb_desc->multicast || tcb_desc->broadcast)
470 return; 462 return;
471 463
472 /*use legency rate, shall use 20MHz */ 464 /*use legency rate, shall use 20MHz */
473 if (tcb_desc->hw_rate <= rtlpriv->cfg->maps[RTL_RC_OFDM_RATE54M]) 465 if (tcb_desc->hw_rate <= rtlpriv->cfg->maps[RTL_RC_OFDM_RATE54M])
474 return; 466 return;
475 467
476 tcb_desc->b_packet_bw = true; 468 tcb_desc->packet_bw = true;
477} 469}
478 470
479static u8 _rtl_get_highest_n_rate(struct ieee80211_hw *hw) 471static u8 _rtl_get_highest_n_rate(struct ieee80211_hw *hw)
@@ -498,7 +490,7 @@ void rtl_get_tcb_desc(struct ieee80211_hw *hw,
498 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw)); 490 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
499 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data); 491 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
500 struct ieee80211_rate *txrate; 492 struct ieee80211_rate *txrate;
501 u16 fc = le16_to_cpu(hdr->frame_control); 493 __le16 fc = hdr->frame_control;
502 494
503 memset(tcb_desc, 0, sizeof(struct rtl_tcb_desc)); 495 memset(tcb_desc, 0, sizeof(struct rtl_tcb_desc));
504 496
@@ -545,9 +537,9 @@ void rtl_get_tcb_desc(struct ieee80211_hw *hw,
545 } 537 }
546 538
547 if (is_multicast_ether_addr(ieee80211_get_DA(hdr))) 539 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)))
548 tcb_desc->b_multicast = 1; 540 tcb_desc->multicast = 1;
549 else if (is_broadcast_ether_addr(ieee80211_get_DA(hdr))) 541 else if (is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
550 tcb_desc->b_broadcast = 1; 542 tcb_desc->broadcast = 1;
551 543
552 _rtl_txrate_selectmode(hw, tcb_desc); 544 _rtl_txrate_selectmode(hw, tcb_desc);
553 _rtl_query_bandwidth_mode(hw, tcb_desc); 545 _rtl_query_bandwidth_mode(hw, tcb_desc);
@@ -570,7 +562,7 @@ bool rtl_tx_mgmt_proc(struct ieee80211_hw *hw, struct sk_buff *skb)
570 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 562 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
571 struct rtl_priv *rtlpriv = rtl_priv(hw); 563 struct rtl_priv *rtlpriv = rtl_priv(hw);
572 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data); 564 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
573 u16 fc = le16_to_cpu(hdr->frame_control); 565 __le16 fc = hdr->frame_control;
574 566
575 if (ieee80211_is_auth(fc)) { 567 if (ieee80211_is_auth(fc)) {
576 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n")); 568 RT_TRACE(rtlpriv, COMP_SEND, DBG_DMESG, ("MAC80211_LINKING\n"));
@@ -587,7 +579,7 @@ bool rtl_action_proc(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
587 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 579 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
588 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data); 580 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
589 struct rtl_priv *rtlpriv = rtl_priv(hw); 581 struct rtl_priv *rtlpriv = rtl_priv(hw);
590 u16 fc = le16_to_cpu(hdr->frame_control); 582 __le16 fc = hdr->frame_control;
591 u8 *act = (u8 *) (((u8 *) skb->data + MAC80211_3ADDR_LEN)); 583 u8 *act = (u8 *) (((u8 *) skb->data + MAC80211_3ADDR_LEN));
592 u8 category; 584 u8 category;
593 585
@@ -632,7 +624,7 @@ u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
632 struct rtl_priv *rtlpriv = rtl_priv(hw); 624 struct rtl_priv *rtlpriv = rtl_priv(hw);
633 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data); 625 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
634 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 626 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
635 u16 fc = le16_to_cpu(hdr->frame_control); 627 __le16 fc = hdr->frame_control;
636 u16 ether_type; 628 u16 ether_type;
637 u8 mac_hdr_len = ieee80211_get_hdrlen_from_skb(skb); 629 u8 mac_hdr_len = ieee80211_get_hdrlen_from_skb(skb);
638 const struct iphdr *ip; 630 const struct iphdr *ip;
@@ -646,7 +638,6 @@ u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
646 ip = (struct iphdr *)((u8 *) skb->data + mac_hdr_len + 638 ip = (struct iphdr *)((u8 *) skb->data + mac_hdr_len +
647 SNAP_SIZE + PROTOC_TYPE_SIZE); 639 SNAP_SIZE + PROTOC_TYPE_SIZE);
648 ether_type = *(u16 *) ((u8 *) skb->data + mac_hdr_len + SNAP_SIZE); 640 ether_type = *(u16 *) ((u8 *) skb->data + mac_hdr_len + SNAP_SIZE);
649 ether_type = ntohs(ether_type);
650 641
651 if (ETH_P_IP == ether_type) { 642 if (ETH_P_IP == ether_type) {
652 if (IPPROTO_UDP == ip->protocol) { 643 if (IPPROTO_UDP == ip->protocol) {
@@ -690,7 +681,8 @@ u8 rtl_is_special_data(struct ieee80211_hw *hw, struct sk_buff *skb, u8 is_tx)
690 } 681 }
691 682
692 return true; 683 return true;
693 } else if (0x86DD == ether_type) { 684 } else if (ETH_P_IPV6 == ether_type) {
685 /* IPv6 */
694 return true; 686 return true;
695 } 687 }
696 688
@@ -777,10 +769,10 @@ void rtl_watchdog_wq_callback(void *data)
777 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 769 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
778 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 770 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
779 771
780 bool b_busytraffic = false; 772 bool busytraffic = false;
781 bool b_higher_busytraffic = false; 773 bool higher_busytraffic = false;
782 bool b_higher_busyrxtraffic = false; 774 bool higher_busyrxtraffic = false;
783 bool b_higher_busytxtraffic = false; 775 bool higher_busytxtraffic = false;
784 776
785 u8 idx = 0; 777 u8 idx = 0;
786 u32 rx_cnt_inp4eriod = 0; 778 u32 rx_cnt_inp4eriod = 0;
@@ -788,7 +780,7 @@ void rtl_watchdog_wq_callback(void *data)
788 u32 aver_rx_cnt_inperiod = 0; 780 u32 aver_rx_cnt_inperiod = 0;
789 u32 aver_tx_cnt_inperiod = 0; 781 u32 aver_tx_cnt_inperiod = 0;
790 782
791 bool benter_ps = false; 783 bool enter_ps = false;
792 784
793 if (is_hal_stop(rtlhal)) 785 if (is_hal_stop(rtlhal))
794 return; 786 return;
@@ -832,29 +824,29 @@ void rtl_watchdog_wq_callback(void *data)
832 824
833 /* (2) check traffic busy */ 825 /* (2) check traffic busy */
834 if (aver_rx_cnt_inperiod > 100 || aver_tx_cnt_inperiod > 100) 826 if (aver_rx_cnt_inperiod > 100 || aver_tx_cnt_inperiod > 100)
835 b_busytraffic = true; 827 busytraffic = true;
836 828
837 /* Higher Tx/Rx data. */ 829 /* Higher Tx/Rx data. */
838 if (aver_rx_cnt_inperiod > 4000 || 830 if (aver_rx_cnt_inperiod > 4000 ||
839 aver_tx_cnt_inperiod > 4000) { 831 aver_tx_cnt_inperiod > 4000) {
840 b_higher_busytraffic = true; 832 higher_busytraffic = true;
841 833
842 /* Extremely high Rx data. */ 834 /* Extremely high Rx data. */
843 if (aver_rx_cnt_inperiod > 5000) 835 if (aver_rx_cnt_inperiod > 5000)
844 b_higher_busyrxtraffic = true; 836 higher_busyrxtraffic = true;
845 else 837 else
846 b_higher_busytxtraffic = false; 838 higher_busytxtraffic = false;
847 } 839 }
848 840
849 if (((rtlpriv->link_info.num_rx_inperiod + 841 if (((rtlpriv->link_info.num_rx_inperiod +
850 rtlpriv->link_info.num_tx_inperiod) > 8) || 842 rtlpriv->link_info.num_tx_inperiod) > 8) ||
851 (rtlpriv->link_info.num_rx_inperiod > 2)) 843 (rtlpriv->link_info.num_rx_inperiod > 2))
852 benter_ps = false; 844 enter_ps = false;
853 else 845 else
854 benter_ps = true; 846 enter_ps = true;
855 847
856 /* LeisurePS only work in infra mode. */ 848 /* LeisurePS only work in infra mode. */
857 if (benter_ps) 849 if (enter_ps)
858 rtl_lps_enter(hw); 850 rtl_lps_enter(hw);
859 else 851 else
860 rtl_lps_leave(hw); 852 rtl_lps_leave(hw);
@@ -863,9 +855,9 @@ void rtl_watchdog_wq_callback(void *data)
863 rtlpriv->link_info.num_rx_inperiod = 0; 855 rtlpriv->link_info.num_rx_inperiod = 0;
864 rtlpriv->link_info.num_tx_inperiod = 0; 856 rtlpriv->link_info.num_tx_inperiod = 0;
865 857
866 rtlpriv->link_info.b_busytraffic = b_busytraffic; 858 rtlpriv->link_info.busytraffic = busytraffic;
867 rtlpriv->link_info.b_higher_busytraffic = b_higher_busytraffic; 859 rtlpriv->link_info.higher_busytraffic = higher_busytraffic;
868 rtlpriv->link_info.b_higher_busyrxtraffic = b_higher_busyrxtraffic; 860 rtlpriv->link_info.higher_busyrxtraffic = higher_busyrxtraffic;
869 861
870} 862}
871 863
@@ -945,11 +937,16 @@ MODULE_DESCRIPTION("Realtek 802.11n PCI wireless core");
945 937
946static int __init rtl_core_module_init(void) 938static int __init rtl_core_module_init(void)
947{ 939{
940 if (rtl_rate_control_register())
941 printk(KERN_ERR "rtlwifi: Unable to register rtl_rc,"
942 "use default RC !!\n");
948 return 0; 943 return 0;
949} 944}
950 945
951static void __exit rtl_core_module_exit(void) 946static void __exit rtl_core_module_exit(void)
952{ 947{
948 /*RC*/
949 rtl_rate_control_unregister();
953} 950}
954 951
955module_init(rtl_core_module_init); 952module_init(rtl_core_module_init);
diff --git a/drivers/net/wireless/rtlwifi/base.h b/drivers/net/wireless/rtlwifi/base.h
index 3de5a14745f1..043045342bc7 100644
--- a/drivers/net/wireless/rtlwifi/base.h
+++ b/drivers/net/wireless/rtlwifi/base.h
@@ -30,6 +30,7 @@
30#define __RTL_BASE_H__ 30#define __RTL_BASE_H__
31 31
32#define RTL_DUMMY_OFFSET 0 32#define RTL_DUMMY_OFFSET 0
33#define RTL_RX_DESC_SIZE 24
33#define RTL_DUMMY_UNIT 8 34#define RTL_DUMMY_UNIT 8
34#define RTL_TX_DUMMY_SIZE (RTL_DUMMY_OFFSET * RTL_DUMMY_UNIT) 35#define RTL_TX_DUMMY_SIZE (RTL_DUMMY_OFFSET * RTL_DUMMY_UNIT)
35#define RTL_TX_DESC_SIZE 32 36#define RTL_TX_DESC_SIZE 32
@@ -52,46 +53,22 @@
52#define FRAME_OFFSET_SEQUENCE 22 53#define FRAME_OFFSET_SEQUENCE 22
53#define FRAME_OFFSET_ADDRESS4 24 54#define FRAME_OFFSET_ADDRESS4 24
54 55
55#define SET_80211_HDR_FRAME_CONTROL(_hdr, _val) \
56 WRITEEF2BYTE(_hdr, _val)
57#define SET_80211_HDR_TYPE_AND_SUBTYPE(_hdr, _val) \
58 WRITEEF1BYTE(_hdr, _val)
59#define SET_80211_HDR_PWR_MGNT(_hdr, _val) \
60 SET_BITS_TO_LE_2BYTE(_hdr, 12, 1, _val)
61#define SET_80211_HDR_TO_DS(_hdr, _val) \
62 SET_BITS_TO_LE_2BYTE(_hdr, 8, 1, _val)
63 56
64#define SET_80211_PS_POLL_AID(_hdr, _val) \ 57#define SET_80211_PS_POLL_AID(_hdr, _val) \
65 WRITEEF2BYTE(((u8 *)(_hdr)) + 2, _val) 58 (*(u16 *)((u8 *)(_hdr) + 2) = le16_to_cpu(_val))
66#define SET_80211_PS_POLL_BSSID(_hdr, _val) \ 59#define SET_80211_PS_POLL_BSSID(_hdr, _val) \
67 CP_MACADDR(((u8 *)(_hdr)) + 4, (u8 *)(_val)) 60 memcpy(((u8 *)(_hdr)) + 4, (u8 *)(_val), ETH_ALEN)
68#define SET_80211_PS_POLL_TA(_hdr, _val) \ 61#define SET_80211_PS_POLL_TA(_hdr, _val) \
69 CP_MACADDR(((u8 *)(_hdr)) + 10, (u8 *)(_val)) 62 memcpy(((u8 *)(_hdr)) + 10, (u8 *)(_val), ETH_ALEN)
70 63
71#define SET_80211_HDR_DURATION(_hdr, _val) \ 64#define SET_80211_HDR_DURATION(_hdr, _val) \
72 WRITEEF2BYTE((u8 *)(_hdr)+FRAME_OFFSET_DURATION, _val) 65 (*(u16 *)((u8 *)(_hdr) + FRAME_OFFSET_DURATION) = le16_to_cpu(_val))
73#define SET_80211_HDR_ADDRESS1(_hdr, _val) \ 66#define SET_80211_HDR_ADDRESS1(_hdr, _val) \
74 CP_MACADDR((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS1, (u8*)(_val)) 67 memcpy((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS1, (u8*)(_val), ETH_ALEN)
75#define SET_80211_HDR_ADDRESS2(_hdr, _val) \ 68#define SET_80211_HDR_ADDRESS2(_hdr, _val) \
76 CP_MACADDR((u8 *)(_hdr) + FRAME_OFFSET_ADDRESS2, (u8 *)(_val)) 69 memcpy((u8 *)(_hdr) + FRAME_OFFSET_ADDRESS2, (u8 *)(_val), ETH_ALEN)
77#define SET_80211_HDR_ADDRESS3(_hdr, _val) \ 70#define SET_80211_HDR_ADDRESS3(_hdr, _val) \
78 CP_MACADDR((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS3, (u8 *)(_val)) 71 memcpy((u8 *)(_hdr)+FRAME_OFFSET_ADDRESS3, (u8 *)(_val), ETH_ALEN)
79#define SET_80211_HDR_FRAGMENT_SEQUENCE(_hdr, _val) \
80 WRITEEF2BYTE((u8 *)(_hdr)+FRAME_OFFSET_SEQUENCE, _val)
81
82#define SET_BEACON_PROBE_RSP_TIME_STAMP_LOW(__phdr, __val) \
83 WRITEEF4BYTE(((u8 *)(__phdr)) + 24, __val)
84#define SET_BEACON_PROBE_RSP_TIME_STAMP_HIGH(__phdr, __val) \
85 WRITEEF4BYTE(((u8 *)(__phdr)) + 28, __val)
86#define SET_BEACON_PROBE_RSP_BEACON_INTERVAL(__phdr, __val) \
87 WRITEEF2BYTE(((u8 *)(__phdr)) + 32, __val)
88#define GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) \
89 READEF2BYTE(((u8 *)(__phdr)) + 34)
90#define SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
91 WRITEEF2BYTE(((u8 *)(__phdr)) + 34, __val)
92#define MASK_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, __val) \
93 SET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr, \
94 (GET_BEACON_PROBE_RSP_CAPABILITY_INFO(__phdr) & (~(__val))))
95 72
96int rtl_init_core(struct ieee80211_hw *hw); 73int rtl_init_core(struct ieee80211_hw *hw);
97void rtl_deinit_core(struct ieee80211_hw *hw); 74void rtl_deinit_core(struct ieee80211_hw *hw);
diff --git a/drivers/net/wireless/rtlwifi/core.c b/drivers/net/wireless/rtlwifi/core.c
index d6a924a05654..e4f4aee8f298 100644
--- a/drivers/net/wireless/rtlwifi/core.c
+++ b/drivers/net/wireless/rtlwifi/core.c
@@ -82,7 +82,7 @@ static void rtl_op_stop(struct ieee80211_hw *hw)
82 mutex_unlock(&rtlpriv->locks.conf_mutex); 82 mutex_unlock(&rtlpriv->locks.conf_mutex);
83} 83}
84 84
85static int rtl_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 85static void rtl_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
86{ 86{
87 struct rtl_priv *rtlpriv = rtl_priv(hw); 87 struct rtl_priv *rtlpriv = rtl_priv(hw);
88 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 88 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
@@ -97,11 +97,10 @@ static int rtl_op_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
97 97
98 rtlpriv->intf_ops->adapter_tx(hw, skb); 98 rtlpriv->intf_ops->adapter_tx(hw, skb);
99 99
100 return NETDEV_TX_OK; 100 return;
101 101
102err_free: 102err_free:
103 dev_kfree_skb_any(skb); 103 dev_kfree_skb_any(skb);
104 return NETDEV_TX_OK;
105} 104}
106 105
107static int rtl_op_add_interface(struct ieee80211_hw *hw, 106static int rtl_op_add_interface(struct ieee80211_hw *hw,
@@ -434,9 +433,9 @@ static int rtl_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
434 433
435 aci = _rtl_get_hal_qnum(queue); 434 aci = _rtl_get_hal_qnum(queue);
436 mac->ac[aci].aifs = param->aifs; 435 mac->ac[aci].aifs = param->aifs;
437 mac->ac[aci].cw_min = param->cw_min; 436 mac->ac[aci].cw_min = cpu_to_le16(param->cw_min);
438 mac->ac[aci].cw_max = param->cw_max; 437 mac->ac[aci].cw_max = cpu_to_le16(param->cw_max);
439 mac->ac[aci].tx_op = param->txop; 438 mac->ac[aci].tx_op = cpu_to_le16(param->txop);
440 memcpy(&mac->edca_param[aci], param, sizeof(*param)); 439 memcpy(&mac->edca_param[aci], param, sizeof(*param));
441 rtlpriv->cfg->ops->set_qos(hw, aci); 440 rtlpriv->cfg->ops->set_qos(hw, aci);
442 return 0; 441 return 0;
@@ -552,6 +551,7 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
552 RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE, 551 RT_TRACE(rtlpriv, COMP_MAC80211, DBG_TRACE,
553 ("BSS_CHANGED_HT\n")); 552 ("BSS_CHANGED_HT\n"));
554 553
554 rcu_read_lock();
555 sta = ieee80211_find_sta(mac->vif, mac->bssid); 555 sta = ieee80211_find_sta(mac->vif, mac->bssid);
556 556
557 if (sta) { 557 if (sta) {
@@ -564,6 +564,7 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
564 mac->current_ampdu_factor = 564 mac->current_ampdu_factor =
565 sta->ht_cap.ampdu_factor; 565 sta->ht_cap.ampdu_factor;
566 } 566 }
567 rcu_read_unlock();
567 568
568 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SHORTGI_DENSITY, 569 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SHORTGI_DENSITY,
569 (u8 *) (&mac->max_mss_density)); 570 (u8 *) (&mac->max_mss_density));
@@ -615,6 +616,7 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
615 else 616 else
616 mac->mode = WIRELESS_MODE_G; 617 mac->mode = WIRELESS_MODE_G;
617 618
619 rcu_read_lock();
618 sta = ieee80211_find_sta(mac->vif, mac->bssid); 620 sta = ieee80211_find_sta(mac->vif, mac->bssid);
619 621
620 if (sta) { 622 if (sta) {
@@ -649,6 +651,7 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
649 */ 651 */
650 } 652 }
651 } 653 }
654 rcu_read_unlock();
652 655
653 /*mac80211 just give us CCK rates any time 656 /*mac80211 just give us CCK rates any time
654 *So we add G rate in basic rates when 657 *So we add G rate in basic rates when
@@ -666,7 +669,7 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
666 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE, 669 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_BASIC_RATE,
667 (u8 *) (&basic_rates)); 670 (u8 *) (&basic_rates));
668 671
669 if (rtlpriv->dm.b_useramask) 672 if (rtlpriv->dm.useramask)
670 rtlpriv->cfg->ops->update_rate_mask(hw, 0); 673 rtlpriv->cfg->ops->update_rate_mask(hw, 0);
671 else 674 else
672 rtlpriv->cfg->ops->update_rate_table(hw); 675 rtlpriv->cfg->ops->update_rate_table(hw);
@@ -681,7 +684,7 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
681 */ 684 */
682 if (changed & BSS_CHANGED_ASSOC) { 685 if (changed & BSS_CHANGED_ASSOC) {
683 if (bss_conf->assoc) { 686 if (bss_conf->assoc) {
684 if (ppsc->b_fwctrl_lps) { 687 if (ppsc->fwctrl_lps) {
685 u8 mstatus = RT_MEDIA_CONNECT; 688 u8 mstatus = RT_MEDIA_CONNECT;
686 rtlpriv->cfg->ops->set_hw_reg(hw, 689 rtlpriv->cfg->ops->set_hw_reg(hw,
687 HW_VAR_H2C_FW_JOINBSSRPT, 690 HW_VAR_H2C_FW_JOINBSSRPT,
@@ -689,7 +692,7 @@ static void rtl_op_bss_info_changed(struct ieee80211_hw *hw,
689 ppsc->report_linked = true; 692 ppsc->report_linked = true;
690 } 693 }
691 } else { 694 } else {
692 if (ppsc->b_fwctrl_lps) { 695 if (ppsc->fwctrl_lps) {
693 u8 mstatus = RT_MEDIA_DISCONNECT; 696 u8 mstatus = RT_MEDIA_DISCONNECT;
694 rtlpriv->cfg->ops->set_hw_reg(hw, 697 rtlpriv->cfg->ops->set_hw_reg(hw,
695 HW_VAR_H2C_FW_JOINBSSRPT, 698 HW_VAR_H2C_FW_JOINBSSRPT,
@@ -748,7 +751,8 @@ static void rtl_op_sta_notify(struct ieee80211_hw *hw,
748static int rtl_op_ampdu_action(struct ieee80211_hw *hw, 751static int rtl_op_ampdu_action(struct ieee80211_hw *hw,
749 struct ieee80211_vif *vif, 752 struct ieee80211_vif *vif,
750 enum ieee80211_ampdu_mlme_action action, 753 enum ieee80211_ampdu_mlme_action action,
751 struct ieee80211_sta *sta, u16 tid, u16 * ssn) 754 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
755 u8 buf_size)
752{ 756{
753 struct rtl_priv *rtlpriv = rtl_priv(hw); 757 struct rtl_priv *rtlpriv = rtl_priv(hw);
754 758
@@ -817,7 +821,7 @@ static void rtl_op_sw_scan_complete(struct ieee80211_hw *hw)
817 /* fix fwlps issue */ 821 /* fix fwlps issue */
818 rtlpriv->cfg->ops->set_network_type(hw, mac->opmode); 822 rtlpriv->cfg->ops->set_network_type(hw, mac->opmode);
819 823
820 if (rtlpriv->dm.b_useramask) 824 if (rtlpriv->dm.useramask)
821 rtlpriv->cfg->ops->update_rate_mask(hw, 0); 825 rtlpriv->cfg->ops->update_rate_mask(hw, 0);
822 else 826 else
823 rtlpriv->cfg->ops->update_rate_table(hw); 827 rtlpriv->cfg->ops->update_rate_table(hw);
diff --git a/drivers/net/wireless/rtlwifi/debug.h b/drivers/net/wireless/rtlwifi/debug.h
index 08bdec2ceda4..e4aa8687408c 100644
--- a/drivers/net/wireless/rtlwifi/debug.h
+++ b/drivers/net/wireless/rtlwifi/debug.h
@@ -105,6 +105,7 @@
105#define COMP_MAC80211 BIT(26) 105#define COMP_MAC80211 BIT(26)
106#define COMP_REGD BIT(27) 106#define COMP_REGD BIT(27)
107#define COMP_CHAN BIT(28) 107#define COMP_CHAN BIT(28)
108#define COMP_USB BIT(29)
108 109
109/*-------------------------------------------------------------- 110/*--------------------------------------------------------------
110 Define the rt_print components 111 Define the rt_print components
diff --git a/drivers/net/wireless/rtlwifi/efuse.c b/drivers/net/wireless/rtlwifi/efuse.c
index 62876cd5c41a..4f92cba6810a 100644
--- a/drivers/net/wireless/rtlwifi/efuse.c
+++ b/drivers/net/wireless/rtlwifi/efuse.c
@@ -1169,21 +1169,3 @@ static u8 efuse_calculate_word_cnts(u8 word_en)
1169 return word_cnts; 1169 return word_cnts;
1170} 1170}
1171 1171
1172void efuse_reset_loader(struct ieee80211_hw *hw)
1173{
1174 struct rtl_priv *rtlpriv = rtl_priv(hw);
1175 u16 tmp_u2b;
1176
1177 tmp_u2b = rtl_read_word(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN]);
1178 rtl_write_word(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN],
1179 (tmp_u2b & ~(BIT(12))));
1180 udelay(10000);
1181 rtl_write_word(rtlpriv, rtlpriv->cfg->maps[SYS_FUNC_EN],
1182 (tmp_u2b | BIT(12)));
1183 udelay(10000);
1184}
1185
1186bool efuse_program_map(struct ieee80211_hw *hw, char *p_filename, u8 tabletype)
1187{
1188 return true;
1189}
diff --git a/drivers/net/wireless/rtlwifi/efuse.h b/drivers/net/wireless/rtlwifi/efuse.h
index 2d39a4df181b..47774dd4c2a6 100644
--- a/drivers/net/wireless/rtlwifi/efuse.h
+++ b/drivers/net/wireless/rtlwifi/efuse.h
@@ -117,8 +117,5 @@ extern bool efuse_shadow_update_chk(struct ieee80211_hw *hw);
117extern void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw); 117extern void rtl_efuse_shadow_map_update(struct ieee80211_hw *hw);
118extern void efuse_force_write_vendor_Id(struct ieee80211_hw *hw); 118extern void efuse_force_write_vendor_Id(struct ieee80211_hw *hw);
119extern void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx); 119extern void efuse_re_pg_section(struct ieee80211_hw *hw, u8 section_idx);
120extern bool efuse_program_map(struct ieee80211_hw *hw,
121 char *p_filename, u8 tabletype);
122extern void efuse_reset_loader(struct ieee80211_hw *hw);
123 120
124#endif 121#endif
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
index 1758d4463247..9cd7703c2a30 100644
--- a/drivers/net/wireless/rtlwifi/pci.c
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -50,7 +50,7 @@ static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
50 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor; 50 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
51 51
52 ppsc->reg_rfps_level = 0; 52 ppsc->reg_rfps_level = 0;
53 ppsc->b_support_aspm = 0; 53 ppsc->support_aspm = 0;
54 54
55 /*Update PCI ASPM setting */ 55 /*Update PCI ASPM setting */
56 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm; 56 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
@@ -115,29 +115,29 @@ static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
115 switch (rtlpci->const_support_pciaspm) { 115 switch (rtlpci->const_support_pciaspm) {
116 case 0:{ 116 case 0:{
117 /*Not support ASPM. */ 117 /*Not support ASPM. */
118 bool b_support_aspm = false; 118 bool support_aspm = false;
119 ppsc->b_support_aspm = b_support_aspm; 119 ppsc->support_aspm = support_aspm;
120 break; 120 break;
121 } 121 }
122 case 1:{ 122 case 1:{
123 /*Support ASPM. */ 123 /*Support ASPM. */
124 bool b_support_aspm = true; 124 bool support_aspm = true;
125 bool b_support_backdoor = true; 125 bool support_backdoor = true;
126 ppsc->b_support_aspm = b_support_aspm; 126 ppsc->support_aspm = support_aspm;
127 127
128 /*if(priv->oem_id == RT_CID_TOSHIBA && 128 /*if(priv->oem_id == RT_CID_TOSHIBA &&
129 !priv->ndis_adapter.amd_l1_patch) 129 !priv->ndis_adapter.amd_l1_patch)
130 b_support_backdoor = false; */ 130 support_backdoor = false; */
131 131
132 ppsc->b_support_backdoor = b_support_backdoor; 132 ppsc->support_backdoor = support_backdoor;
133 133
134 break; 134 break;
135 } 135 }
136 case 2: 136 case 2:
137 /*ASPM value set by chipset. */ 137 /*ASPM value set by chipset. */
138 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) { 138 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
139 bool b_support_aspm = true; 139 bool support_aspm = true;
140 ppsc->b_support_aspm = b_support_aspm; 140 ppsc->support_aspm = support_aspm;
141 } 141 }
142 break; 142 break;
143 default: 143 default:
@@ -476,9 +476,9 @@ static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
476 476
477 skb = __skb_dequeue(&ring->queue); 477 skb = __skb_dequeue(&ring->queue);
478 pci_unmap_single(rtlpci->pdev, 478 pci_unmap_single(rtlpci->pdev,
479 le32_to_cpu(rtlpriv->cfg->ops-> 479 rtlpriv->cfg->ops->
480 get_desc((u8 *) entry, true, 480 get_desc((u8 *) entry, true,
481 HW_DESC_TXBUFF_ADDR)), 481 HW_DESC_TXBUFF_ADDR),
482 skb->len, PCI_DMA_TODEVICE); 482 skb->len, PCI_DMA_TODEVICE);
483 483
484 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE, 484 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
@@ -557,7 +557,7 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
557 return; 557 return;
558 } else { 558 } else {
559 struct ieee80211_hdr *hdr; 559 struct ieee80211_hdr *hdr;
560 u16 fc; 560 __le16 fc;
561 struct sk_buff *new_skb = NULL; 561 struct sk_buff *new_skb = NULL;
562 562
563 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, 563 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
@@ -583,9 +583,9 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
583 */ 583 */
584 584
585 hdr = (struct ieee80211_hdr *)(skb->data); 585 hdr = (struct ieee80211_hdr *)(skb->data);
586 fc = le16_to_cpu(hdr->frame_control); 586 fc = hdr->frame_control;
587 587
588 if (!stats.b_crc) { 588 if (!stats.crc) {
589 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, 589 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
590 sizeof(rx_status)); 590 sizeof(rx_status));
591 591
@@ -666,7 +666,7 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
666 666
667 } 667 }
668done: 668done:
669 bufferaddress = cpu_to_le32(*((dma_addr_t *) skb->cb)); 669 bufferaddress = (u32)(*((dma_addr_t *) skb->cb));
670 tmp_one = 1; 670 tmp_one = 1;
671 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false, 671 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
672 HW_DESC_RXBUFF_ADDR, 672 HW_DESC_RXBUFF_ADDR,
@@ -690,75 +690,6 @@ done:
690 690
691} 691}
692 692
693void _rtl_pci_tx_interrupt(struct ieee80211_hw *hw)
694{
695 struct rtl_priv *rtlpriv = rtl_priv(hw);
696 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
697 int prio;
698
699 for (prio = 0; prio < RTL_PCI_MAX_TX_QUEUE_COUNT; prio++) {
700 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
701
702 while (skb_queue_len(&ring->queue)) {
703 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
704 struct sk_buff *skb;
705 struct ieee80211_tx_info *info;
706 u8 own;
707
708 /*
709 *beacon packet will only use the first
710 *descriptor defautly, and the own may not
711 *be cleared by the hardware, and
712 *beacon will free in prepare beacon
713 */
714 if (prio == BEACON_QUEUE || prio == TXCMD_QUEUE ||
715 prio == HCCA_QUEUE)
716 break;
717
718 own = (u8)rtlpriv->cfg->ops->get_desc((u8 *)entry,
719 true,
720 HW_DESC_OWN);
721
722 if (own)
723 break;
724
725 skb = __skb_dequeue(&ring->queue);
726 pci_unmap_single(rtlpci->pdev,
727 le32_to_cpu(rtlpriv->cfg->ops->
728 get_desc((u8 *) entry,
729 true,
730 HW_DESC_TXBUFF_ADDR)),
731 skb->len, PCI_DMA_TODEVICE);
732
733 ring->idx = (ring->idx + 1) % ring->entries;
734
735 info = IEEE80211_SKB_CB(skb);
736 ieee80211_tx_info_clear_status(info);
737
738 info->flags |= IEEE80211_TX_STAT_ACK;
739 /*info->status.rates[0].count = 1; */
740
741 ieee80211_tx_status_irqsafe(hw, skb);
742
743 if ((ring->entries - skb_queue_len(&ring->queue))
744 == 2 && prio != BEACON_QUEUE) {
745 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
746 ("more desc left, wake "
747 "skb_queue@%d,ring->idx = %d,"
748 "skb_queue_len = 0x%d\n",
749 prio, ring->idx,
750 skb_queue_len(&ring->queue)));
751
752 ieee80211_wake_queue(hw,
753 skb_get_queue_mapping
754 (skb));
755 }
756
757 skb = NULL;
758 }
759 }
760}
761
762static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id) 693static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
763{ 694{
764 struct ieee80211_hw *hw = dev_id; 695 struct ieee80211_hw *hw = dev_id;
@@ -959,17 +890,17 @@ static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
959 rtlhal->hw = hw; 890 rtlhal->hw = hw;
960 rtlpci->pdev = pdev; 891 rtlpci->pdev = pdev;
961 892
962 ppsc->b_inactiveps = false; 893 ppsc->inactiveps = false;
963 ppsc->b_leisure_ps = true; 894 ppsc->leisure_ps = true;
964 ppsc->b_fwctrl_lps = true; 895 ppsc->fwctrl_lps = true;
965 ppsc->b_reg_fwctrl_lps = 3; 896 ppsc->reg_fwctrl_lps = 3;
966 ppsc->reg_max_lps_awakeintvl = 5; 897 ppsc->reg_max_lps_awakeintvl = 5;
967 898
968 if (ppsc->b_reg_fwctrl_lps == 1) 899 if (ppsc->reg_fwctrl_lps == 1)
969 ppsc->fwctrl_psmode = FW_PS_MIN_MODE; 900 ppsc->fwctrl_psmode = FW_PS_MIN_MODE;
970 else if (ppsc->b_reg_fwctrl_lps == 2) 901 else if (ppsc->reg_fwctrl_lps == 2)
971 ppsc->fwctrl_psmode = FW_PS_MAX_MODE; 902 ppsc->fwctrl_psmode = FW_PS_MAX_MODE;
972 else if (ppsc->b_reg_fwctrl_lps == 3) 903 else if (ppsc->reg_fwctrl_lps == 3)
973 ppsc->fwctrl_psmode = FW_PS_DTIM_MODE; 904 ppsc->fwctrl_psmode = FW_PS_DTIM_MODE;
974 905
975 /*Tx/Rx related var */ 906 /*Tx/Rx related var */
@@ -1024,9 +955,8 @@ static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1024 ("queue:%d, ring_addr:%p\n", prio, ring)); 955 ("queue:%d, ring_addr:%p\n", prio, ring));
1025 956
1026 for (i = 0; i < entries; i++) { 957 for (i = 0; i < entries; i++) {
1027 nextdescaddress = cpu_to_le32((u32) dma + 958 nextdescaddress = (u32) dma + ((i + 1) % entries) *
1028 ((i + 1) % entries) * 959 sizeof(*ring);
1029 sizeof(*ring));
1030 960
1031 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]), 961 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1032 true, HW_DESC_TX_NEXTDESC_ADDR, 962 true, HW_DESC_TX_NEXTDESC_ADDR,
@@ -1090,7 +1020,7 @@ static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1090 rtlpci->rxbuffersize, 1020 rtlpci->rxbuffersize,
1091 PCI_DMA_FROMDEVICE); 1021 PCI_DMA_FROMDEVICE);
1092 1022
1093 bufferaddress = cpu_to_le32(*((dma_addr_t *)skb->cb)); 1023 bufferaddress = (u32)(*((dma_addr_t *)skb->cb));
1094 rtlpriv->cfg->ops->set_desc((u8 *)entry, false, 1024 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1095 HW_DESC_RXBUFF_ADDR, 1025 HW_DESC_RXBUFF_ADDR,
1096 (u8 *)&bufferaddress); 1026 (u8 *)&bufferaddress);
@@ -1121,9 +1051,9 @@ static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1121 struct sk_buff *skb = __skb_dequeue(&ring->queue); 1051 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1122 1052
1123 pci_unmap_single(rtlpci->pdev, 1053 pci_unmap_single(rtlpci->pdev,
1124 le32_to_cpu(rtlpriv->cfg-> 1054 rtlpriv->cfg->
1125 ops->get_desc((u8 *) entry, true, 1055 ops->get_desc((u8 *) entry, true,
1126 HW_DESC_TXBUFF_ADDR)), 1056 HW_DESC_TXBUFF_ADDR),
1127 skb->len, PCI_DMA_TODEVICE); 1057 skb->len, PCI_DMA_TODEVICE);
1128 kfree_skb(skb); 1058 kfree_skb(skb);
1129 ring->idx = (ring->idx + 1) % ring->entries; 1059 ring->idx = (ring->idx + 1) % ring->entries;
@@ -1255,11 +1185,11 @@ int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1255 __skb_dequeue(&ring->queue); 1185 __skb_dequeue(&ring->queue);
1256 1186
1257 pci_unmap_single(rtlpci->pdev, 1187 pci_unmap_single(rtlpci->pdev,
1258 le32_to_cpu(rtlpriv->cfg->ops-> 1188 rtlpriv->cfg->ops->
1259 get_desc((u8 *) 1189 get_desc((u8 *)
1260 entry, 1190 entry,
1261 true, 1191 true,
1262 HW_DESC_TXBUFF_ADDR)), 1192 HW_DESC_TXBUFF_ADDR),
1263 skb->len, PCI_DMA_TODEVICE); 1193 skb->len, PCI_DMA_TODEVICE);
1264 kfree_skb(skb); 1194 kfree_skb(skb);
1265 ring->idx = (ring->idx + 1) % ring->entries; 1195 ring->idx = (ring->idx + 1) % ring->entries;
@@ -1273,7 +1203,7 @@ int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1273 return 0; 1203 return 0;
1274} 1204}
1275 1205
1276unsigned int _rtl_mac_to_hwqueue(u16 fc, 1206static unsigned int _rtl_mac_to_hwqueue(__le16 fc,
1277 unsigned int mac80211_queue_index) 1207 unsigned int mac80211_queue_index)
1278{ 1208{
1279 unsigned int hw_queue_index; 1209 unsigned int hw_queue_index;
@@ -1312,7 +1242,7 @@ out:
1312 return hw_queue_index; 1242 return hw_queue_index;
1313} 1243}
1314 1244
1315int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb) 1245static int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1316{ 1246{
1317 struct rtl_priv *rtlpriv = rtl_priv(hw); 1247 struct rtl_priv *rtlpriv = rtl_priv(hw);
1318 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1248 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
@@ -1323,7 +1253,7 @@ int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1323 unsigned int queue_index, hw_queue; 1253 unsigned int queue_index, hw_queue;
1324 unsigned long flags; 1254 unsigned long flags;
1325 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data); 1255 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
1326 u16 fc = le16_to_cpu(hdr->frame_control); 1256 __le16 fc = hdr->frame_control;
1327 u8 *pda_addr = hdr->addr1; 1257 u8 *pda_addr = hdr->addr1;
1328 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1258 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1329 /*ssn */ 1259 /*ssn */
@@ -1429,7 +1359,7 @@ int rtl_pci_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
1429 return 0; 1359 return 0;
1430} 1360}
1431 1361
1432void rtl_pci_deinit(struct ieee80211_hw *hw) 1362static void rtl_pci_deinit(struct ieee80211_hw *hw)
1433{ 1363{
1434 struct rtl_priv *rtlpriv = rtl_priv(hw); 1364 struct rtl_priv *rtlpriv = rtl_priv(hw);
1435 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1365 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
@@ -1444,7 +1374,7 @@ void rtl_pci_deinit(struct ieee80211_hw *hw)
1444 1374
1445} 1375}
1446 1376
1447int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev) 1377static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1448{ 1378{
1449 struct rtl_priv *rtlpriv = rtl_priv(hw); 1379 struct rtl_priv *rtlpriv = rtl_priv(hw);
1450 int err; 1380 int err;
@@ -1461,7 +1391,7 @@ int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1461 return 1; 1391 return 1;
1462} 1392}
1463 1393
1464int rtl_pci_start(struct ieee80211_hw *hw) 1394static int rtl_pci_start(struct ieee80211_hw *hw)
1465{ 1395{
1466 struct rtl_priv *rtlpriv = rtl_priv(hw); 1396 struct rtl_priv *rtlpriv = rtl_priv(hw);
1467 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 1397 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
@@ -1496,7 +1426,7 @@ int rtl_pci_start(struct ieee80211_hw *hw)
1496 return 0; 1426 return 0;
1497} 1427}
1498 1428
1499void rtl_pci_stop(struct ieee80211_hw *hw) 1429static void rtl_pci_stop(struct ieee80211_hw *hw)
1500{ 1430{
1501 struct rtl_priv *rtlpriv = rtl_priv(hw); 1431 struct rtl_priv *rtlpriv = rtl_priv(hw);
1502 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1432 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
@@ -1547,13 +1477,11 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1547 struct pci_dev *bridge_pdev = pdev->bus->self; 1477 struct pci_dev *bridge_pdev = pdev->bus->self;
1548 u16 venderid; 1478 u16 venderid;
1549 u16 deviceid; 1479 u16 deviceid;
1550 u8 revisionid;
1551 u16 irqline; 1480 u16 irqline;
1552 u8 tmp; 1481 u8 tmp;
1553 1482
1554 venderid = pdev->vendor; 1483 venderid = pdev->vendor;
1555 deviceid = pdev->device; 1484 deviceid = pdev->device;
1556 pci_read_config_byte(pdev, 0x8, &revisionid);
1557 pci_read_config_word(pdev, 0x3C, &irqline); 1485 pci_read_config_word(pdev, 0x3C, &irqline);
1558 1486
1559 if (deviceid == RTL_PCI_8192_DID || 1487 if (deviceid == RTL_PCI_8192_DID ||
@@ -1564,7 +1492,7 @@ static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1564 deviceid == RTL_PCI_8173_DID || 1492 deviceid == RTL_PCI_8173_DID ||
1565 deviceid == RTL_PCI_8172_DID || 1493 deviceid == RTL_PCI_8172_DID ||
1566 deviceid == RTL_PCI_8171_DID) { 1494 deviceid == RTL_PCI_8171_DID) {
1567 switch (revisionid) { 1495 switch (pdev->revision) {
1568 case RTL_PCI_REVISION_ID_8192PCIE: 1496 case RTL_PCI_REVISION_ID_8192PCIE:
1569 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, 1497 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1570 ("8192 PCI-E is found - " 1498 ("8192 PCI-E is found - "
@@ -1838,7 +1766,7 @@ fail3:
1838 ieee80211_free_hw(hw); 1766 ieee80211_free_hw(hw);
1839 1767
1840 if (rtlpriv->io.pci_mem_start != 0) 1768 if (rtlpriv->io.pci_mem_start != 0)
1841 pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start); 1769 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1842 1770
1843fail2: 1771fail2:
1844 pci_release_regions(pdev); 1772 pci_release_regions(pdev);
@@ -1888,7 +1816,7 @@ void rtl_pci_disconnect(struct pci_dev *pdev)
1888 } 1816 }
1889 1817
1890 if (rtlpriv->io.pci_mem_start != 0) { 1818 if (rtlpriv->io.pci_mem_start != 0) {
1891 pci_iounmap(pdev, (void *)rtlpriv->io.pci_mem_start); 1819 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
1892 pci_release_regions(pdev); 1820 pci_release_regions(pdev);
1893 } 1821 }
1894 1822
diff --git a/drivers/net/wireless/rtlwifi/pci.h b/drivers/net/wireless/rtlwifi/pci.h
index d36a66939958..0caa81429726 100644
--- a/drivers/net/wireless/rtlwifi/pci.h
+++ b/drivers/net/wireless/rtlwifi/pci.h
@@ -244,34 +244,34 @@ int rtl_pci_resume(struct pci_dev *pdev);
244 244
245static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr) 245static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
246{ 246{
247 return 0xff & readb((u8 *) rtlpriv->io.pci_mem_start + addr); 247 return readb((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
248} 248}
249 249
250static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr) 250static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
251{ 251{
252 return readw((u8 *) rtlpriv->io.pci_mem_start + addr); 252 return readw((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
253} 253}
254 254
255static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr) 255static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
256{ 256{
257 return readl((u8 *) rtlpriv->io.pci_mem_start + addr); 257 return readl((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
258} 258}
259 259
260static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val) 260static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
261{ 261{
262 writeb(val, (u8 *) rtlpriv->io.pci_mem_start + addr); 262 writeb(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
263} 263}
264 264
265static inline void pci_write16_async(struct rtl_priv *rtlpriv, 265static inline void pci_write16_async(struct rtl_priv *rtlpriv,
266 u32 addr, u16 val) 266 u32 addr, u16 val)
267{ 267{
268 writew(val, (u8 *) rtlpriv->io.pci_mem_start + addr); 268 writew(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
269} 269}
270 270
271static inline void pci_write32_async(struct rtl_priv *rtlpriv, 271static inline void pci_write32_async(struct rtl_priv *rtlpriv,
272 u32 addr, u32 val) 272 u32 addr, u32 val)
273{ 273{
274 writel(val, (u8 *) rtlpriv->io.pci_mem_start + addr); 274 writel(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
275} 275}
276 276
277static inline void rtl_pci_raw_write_port_ulong(u32 port, u32 val) 277static inline void rtl_pci_raw_write_port_ulong(u32 port, u32 val)
diff --git a/drivers/net/wireless/rtlwifi/ps.c b/drivers/net/wireless/rtlwifi/ps.c
index d2326c13449e..6b7e217b6b89 100644
--- a/drivers/net/wireless/rtlwifi/ps.c
+++ b/drivers/net/wireless/rtlwifi/ps.c
@@ -86,7 +86,7 @@ bool rtl_ps_set_rf_state(struct ieee80211_hw *hw,
86 struct rtl_priv *rtlpriv = rtl_priv(hw); 86 struct rtl_priv *rtlpriv = rtl_priv(hw);
87 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 87 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
88 enum rf_pwrstate rtstate; 88 enum rf_pwrstate rtstate;
89 bool b_actionallowed = false; 89 bool actionallowed = false;
90 u16 rfwait_cnt = 0; 90 u16 rfwait_cnt = 0;
91 unsigned long flag; 91 unsigned long flag;
92 92
@@ -139,13 +139,13 @@ no_protect:
139 ppsc->rfoff_reason &= (~changesource); 139 ppsc->rfoff_reason &= (~changesource);
140 140
141 if ((changesource == RF_CHANGE_BY_HW) && 141 if ((changesource == RF_CHANGE_BY_HW) &&
142 (ppsc->b_hwradiooff == true)) { 142 (ppsc->hwradiooff == true)) {
143 ppsc->b_hwradiooff = false; 143 ppsc->hwradiooff = false;
144 } 144 }
145 145
146 if (!ppsc->rfoff_reason) { 146 if (!ppsc->rfoff_reason) {
147 ppsc->rfoff_reason = 0; 147 ppsc->rfoff_reason = 0;
148 b_actionallowed = true; 148 actionallowed = true;
149 } 149 }
150 150
151 break; 151 break;
@@ -153,17 +153,17 @@ no_protect:
153 case ERFOFF: 153 case ERFOFF:
154 154
155 if ((changesource == RF_CHANGE_BY_HW) 155 if ((changesource == RF_CHANGE_BY_HW)
156 && (ppsc->b_hwradiooff == false)) { 156 && (ppsc->hwradiooff == false)) {
157 ppsc->b_hwradiooff = true; 157 ppsc->hwradiooff = true;
158 } 158 }
159 159
160 ppsc->rfoff_reason |= changesource; 160 ppsc->rfoff_reason |= changesource;
161 b_actionallowed = true; 161 actionallowed = true;
162 break; 162 break;
163 163
164 case ERFSLEEP: 164 case ERFSLEEP:
165 ppsc->rfoff_reason |= changesource; 165 ppsc->rfoff_reason |= changesource;
166 b_actionallowed = true; 166 actionallowed = true;
167 break; 167 break;
168 168
169 default: 169 default:
@@ -172,7 +172,7 @@ no_protect:
172 break; 172 break;
173 } 173 }
174 174
175 if (b_actionallowed) 175 if (actionallowed)
176 rtlpriv->cfg->ops->set_rf_power_state(hw, state_toset); 176 rtlpriv->cfg->ops->set_rf_power_state(hw, state_toset);
177 177
178 if (!protect_or_not) { 178 if (!protect_or_not) {
@@ -181,7 +181,7 @@ no_protect:
181 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag); 181 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
182 } 182 }
183 183
184 return b_actionallowed; 184 return actionallowed;
185} 185}
186EXPORT_SYMBOL(rtl_ps_set_rf_state); 186EXPORT_SYMBOL(rtl_ps_set_rf_state);
187 187
@@ -191,7 +191,7 @@ static void _rtl_ps_inactive_ps(struct ieee80211_hw *hw)
191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
192 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 192 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
193 193
194 ppsc->b_swrf_processing = true; 194 ppsc->swrf_processing = true;
195 195
196 if (ppsc->inactive_pwrstate == ERFON && rtlhal->interface == INTF_PCI) { 196 if (ppsc->inactive_pwrstate == ERFON && rtlhal->interface == INTF_PCI) {
197 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) && 197 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
@@ -213,7 +213,7 @@ static void _rtl_ps_inactive_ps(struct ieee80211_hw *hw)
213 } 213 }
214 } 214 }
215 215
216 ppsc->b_swrf_processing = false; 216 ppsc->swrf_processing = false;
217} 217}
218 218
219void rtl_ips_nic_off_wq_callback(void *data) 219void rtl_ips_nic_off_wq_callback(void *data)
@@ -239,13 +239,13 @@ void rtl_ips_nic_off_wq_callback(void *data)
239 if (rtlpriv->sec.being_setkey) 239 if (rtlpriv->sec.being_setkey)
240 return; 240 return;
241 241
242 if (ppsc->b_inactiveps) { 242 if (ppsc->inactiveps) {
243 rtstate = ppsc->rfpwr_state; 243 rtstate = ppsc->rfpwr_state;
244 244
245 /* 245 /*
246 *Do not enter IPS in the following conditions: 246 *Do not enter IPS in the following conditions:
247 *(1) RF is already OFF or Sleep 247 *(1) RF is already OFF or Sleep
248 *(2) b_swrf_processing (indicates the IPS is still under going) 248 *(2) swrf_processing (indicates the IPS is still under going)
249 *(3) Connectted (only disconnected can trigger IPS) 249 *(3) Connectted (only disconnected can trigger IPS)
250 *(4) IBSS (send Beacon) 250 *(4) IBSS (send Beacon)
251 *(5) AP mode (send Beacon) 251 *(5) AP mode (send Beacon)
@@ -253,14 +253,14 @@ void rtl_ips_nic_off_wq_callback(void *data)
253 */ 253 */
254 254
255 if (rtstate == ERFON && 255 if (rtstate == ERFON &&
256 !ppsc->b_swrf_processing && 256 !ppsc->swrf_processing &&
257 (mac->link_state == MAC80211_NOLINK) && 257 (mac->link_state == MAC80211_NOLINK) &&
258 !mac->act_scanning) { 258 !mac->act_scanning) {
259 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, 259 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
260 ("IPSEnter(): Turn off RF.\n")); 260 ("IPSEnter(): Turn off RF.\n"));
261 261
262 ppsc->inactive_pwrstate = ERFOFF; 262 ppsc->inactive_pwrstate = ERFOFF;
263 ppsc->b_in_powersavemode = true; 263 ppsc->in_powersavemode = true;
264 264
265 /*rtl_pci_reset_trx_ring(hw); */ 265 /*rtl_pci_reset_trx_ring(hw); */
266 _rtl_ps_inactive_ps(hw); 266 _rtl_ps_inactive_ps(hw);
@@ -290,15 +290,15 @@ void rtl_ips_nic_on(struct ieee80211_hw *hw)
290 290
291 spin_lock_irqsave(&rtlpriv->locks.ips_lock, flags); 291 spin_lock_irqsave(&rtlpriv->locks.ips_lock, flags);
292 292
293 if (ppsc->b_inactiveps) { 293 if (ppsc->inactiveps) {
294 rtstate = ppsc->rfpwr_state; 294 rtstate = ppsc->rfpwr_state;
295 295
296 if (rtstate != ERFON && 296 if (rtstate != ERFON &&
297 !ppsc->b_swrf_processing && 297 !ppsc->swrf_processing &&
298 ppsc->rfoff_reason <= RF_CHANGE_BY_IPS) { 298 ppsc->rfoff_reason <= RF_CHANGE_BY_IPS) {
299 299
300 ppsc->inactive_pwrstate = ERFON; 300 ppsc->inactive_pwrstate = ERFON;
301 ppsc->b_in_powersavemode = false; 301 ppsc->in_powersavemode = false;
302 302
303 _rtl_ps_inactive_ps(hw); 303 _rtl_ps_inactive_ps(hw);
304 } 304 }
@@ -370,9 +370,9 @@ static void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode)
370 * mode and set RPWM to turn RF on. 370 * mode and set RPWM to turn RF on.
371 */ 371 */
372 372
373 if ((ppsc->b_fwctrl_lps) && (ppsc->b_leisure_ps) && 373 if ((ppsc->fwctrl_lps) && (ppsc->leisure_ps) &&
374 ppsc->report_linked) { 374 ppsc->report_linked) {
375 bool b_fw_current_inps; 375 bool fw_current_inps;
376 if (ppsc->dot11_psmode == EACTIVE) { 376 if (ppsc->dot11_psmode == EACTIVE) {
377 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 377 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
378 ("FW LPS leave ps_mode:%x\n", 378 ("FW LPS leave ps_mode:%x\n",
@@ -385,11 +385,11 @@ static void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode)
385 rtlpriv->cfg->ops->set_hw_reg(hw, 385 rtlpriv->cfg->ops->set_hw_reg(hw,
386 HW_VAR_H2C_FW_PWRMODE, 386 HW_VAR_H2C_FW_PWRMODE,
387 (u8 *) (&fw_pwrmode)); 387 (u8 *) (&fw_pwrmode));
388 b_fw_current_inps = false; 388 fw_current_inps = false;
389 389
390 rtlpriv->cfg->ops->set_hw_reg(hw, 390 rtlpriv->cfg->ops->set_hw_reg(hw,
391 HW_VAR_FW_PSMODE_STATUS, 391 HW_VAR_FW_PSMODE_STATUS,
392 (u8 *) (&b_fw_current_inps)); 392 (u8 *) (&fw_current_inps));
393 393
394 } else { 394 } else {
395 if (rtl_get_fwlps_doze(hw)) { 395 if (rtl_get_fwlps_doze(hw)) {
@@ -398,10 +398,10 @@ static void rtl_lps_set_psmode(struct ieee80211_hw *hw, u8 rt_psmode)
398 ppsc->fwctrl_psmode)); 398 ppsc->fwctrl_psmode));
399 399
400 rpwm_val = 0x02; /* RF off */ 400 rpwm_val = 0x02; /* RF off */
401 b_fw_current_inps = true; 401 fw_current_inps = true;
402 rtlpriv->cfg->ops->set_hw_reg(hw, 402 rtlpriv->cfg->ops->set_hw_reg(hw,
403 HW_VAR_FW_PSMODE_STATUS, 403 HW_VAR_FW_PSMODE_STATUS,
404 (u8 *) (&b_fw_current_inps)); 404 (u8 *) (&fw_current_inps));
405 rtlpriv->cfg->ops->set_hw_reg(hw, 405 rtlpriv->cfg->ops->set_hw_reg(hw,
406 HW_VAR_H2C_FW_PWRMODE, 406 HW_VAR_H2C_FW_PWRMODE,
407 (u8 *) (&ppsc->fwctrl_psmode)); 407 (u8 *) (&ppsc->fwctrl_psmode));
@@ -425,13 +425,13 @@ void rtl_lps_enter(struct ieee80211_hw *hw)
425 struct rtl_priv *rtlpriv = rtl_priv(hw); 425 struct rtl_priv *rtlpriv = rtl_priv(hw);
426 unsigned long flag; 426 unsigned long flag;
427 427
428 if (!(ppsc->b_fwctrl_lps && ppsc->b_leisure_ps)) 428 if (!(ppsc->fwctrl_lps && ppsc->leisure_ps))
429 return; 429 return;
430 430
431 if (rtlpriv->sec.being_setkey) 431 if (rtlpriv->sec.being_setkey)
432 return; 432 return;
433 433
434 if (rtlpriv->link_info.b_busytraffic) 434 if (rtlpriv->link_info.busytraffic)
435 return; 435 return;
436 436
437 /*sleep after linked 10s, to let DHCP and 4-way handshake ok enough!! */ 437 /*sleep after linked 10s, to let DHCP and 4-way handshake ok enough!! */
@@ -446,7 +446,7 @@ void rtl_lps_enter(struct ieee80211_hw *hw)
446 446
447 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag); 447 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
448 448
449 if (ppsc->b_leisure_ps) { 449 if (ppsc->leisure_ps) {
450 /* Idle for a while if we connect to AP a while ago. */ 450 /* Idle for a while if we connect to AP a while ago. */
451 if (mac->cnt_after_linked >= 2) { 451 if (mac->cnt_after_linked >= 2) {
452 if (ppsc->dot11_psmode == EACTIVE) { 452 if (ppsc->dot11_psmode == EACTIVE) {
@@ -470,7 +470,7 @@ void rtl_lps_leave(struct ieee80211_hw *hw)
470 470
471 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag); 471 spin_lock_irqsave(&rtlpriv->locks.lps_lock, flag);
472 472
473 if (ppsc->b_fwctrl_lps && ppsc->b_leisure_ps) { 473 if (ppsc->fwctrl_lps && ppsc->leisure_ps) {
474 if (ppsc->dot11_psmode != EACTIVE) { 474 if (ppsc->dot11_psmode != EACTIVE) {
475 475
476 /*FIX ME */ 476 /*FIX ME */
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/Makefile b/drivers/net/wireless/rtlwifi/rtl8192c/Makefile
new file mode 100644
index 000000000000..aee42d7ae8a2
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/Makefile
@@ -0,0 +1,9 @@
1rtl8192c-common-objs := \
2 main.o \
3 dm_common.o \
4 fw_common.o \
5 phy_common.o
6
7obj-$(CONFIG_RTL8192C_COMMON) += rtl8192c-common.o
8
9ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c b/drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c
new file mode 100644
index 000000000000..bb023274414c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/dm_common.c
@@ -0,0 +1,1398 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "dm_common.h"
31
32struct dig_t dm_digtable;
33static struct ps_t dm_pstable;
34
35static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
36 0x7f8001fe,
37 0x788001e2,
38 0x71c001c7,
39 0x6b8001ae,
40 0x65400195,
41 0x5fc0017f,
42 0x5a400169,
43 0x55400155,
44 0x50800142,
45 0x4c000130,
46 0x47c0011f,
47 0x43c0010f,
48 0x40000100,
49 0x3c8000f2,
50 0x390000e4,
51 0x35c000d7,
52 0x32c000cb,
53 0x300000c0,
54 0x2d4000b5,
55 0x2ac000ab,
56 0x288000a2,
57 0x26000098,
58 0x24000090,
59 0x22000088,
60 0x20000080,
61 0x1e400079,
62 0x1c800072,
63 0x1b00006c,
64 0x19800066,
65 0x18000060,
66 0x16c0005b,
67 0x15800056,
68 0x14400051,
69 0x1300004c,
70 0x12000048,
71 0x11000044,
72 0x10000040,
73};
74
75static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
76 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
77 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
78 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
79 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
80 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
81 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
82 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
83 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
84 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
85 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
86 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
87 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
88 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
89 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
90 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
91 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
92 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
93 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
94 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
95 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
96 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
97 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
98 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
99 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
100 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
101 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
102 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
103 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
104 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
105 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
106 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
107 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
108 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
109};
110
111static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
112 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
113 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
114 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
115 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
116 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
117 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
118 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
119 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
120 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
121 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
122 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
123 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
124 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
125 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
126 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
127 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
128 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
129 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
130 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
131 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
132 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
133 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
134 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
135 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
136 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
137 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
138 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
139 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
140 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
141 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
142 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
143 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
144 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
145};
146
147static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
148{
149 dm_digtable.dig_enable_flag = true;
150 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
151 dm_digtable.cur_igvalue = 0x20;
152 dm_digtable.pre_igvalue = 0x0;
153 dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
154 dm_digtable.presta_connectstate = DIG_STA_DISCONNECT;
155 dm_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
156 dm_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
157 dm_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
158 dm_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
159 dm_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
160 dm_digtable.rx_gain_range_max = DM_DIG_MAX;
161 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
162 dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
163 dm_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
164 dm_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
165 dm_digtable.pre_cck_pd_state = CCK_PD_STAGE_MAX;
166 dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
167}
168
169static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
170{
171 struct rtl_priv *rtlpriv = rtl_priv(hw);
172 long rssi_val_min = 0;
173
174 if ((dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
175 (dm_digtable.cursta_connectctate == DIG_STA_CONNECT)) {
176 if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
177 rssi_val_min =
178 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
179 rtlpriv->dm.undecorated_smoothed_pwdb) ?
180 rtlpriv->dm.undecorated_smoothed_pwdb :
181 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
182 else
183 rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
184 } else if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT ||
185 dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
186 rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
187 } else if (dm_digtable.curmultista_connectstate ==
188 DIG_MULTISTA_CONNECT) {
189 rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
190 }
191
192 return (u8) rssi_val_min;
193}
194
195static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
196{
197 u32 ret_value;
198 struct rtl_priv *rtlpriv = rtl_priv(hw);
199 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
200
201 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
202 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
203
204 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
205 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
206 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
207
208 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
209 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
210 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
211 falsealm_cnt->cnt_rate_illegal +
212 falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
213
214 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
215 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
216 falsealm_cnt->cnt_cck_fail = ret_value;
217
218 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
219 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
220 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
221 falsealm_cnt->cnt_rate_illegal +
222 falsealm_cnt->cnt_crc8_fail +
223 falsealm_cnt->cnt_mcs_fail +
224 falsealm_cnt->cnt_cck_fail);
225
226 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
227 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
228 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
229 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
230
231 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
232 ("cnt_parity_fail = %d, cnt_rate_illegal = %d, "
233 "cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
234 falsealm_cnt->cnt_parity_fail,
235 falsealm_cnt->cnt_rate_illegal,
236 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail));
237
238 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
239 ("cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
240 falsealm_cnt->cnt_ofdm_fail,
241 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all));
242}
243
244static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
245{
246 struct rtl_priv *rtlpriv = rtl_priv(hw);
247 u8 value_igi = dm_digtable.cur_igvalue;
248
249 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
250 value_igi--;
251 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
252 value_igi += 0;
253 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
254 value_igi++;
255 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
256 value_igi += 2;
257 if (value_igi > DM_DIG_FA_UPPER)
258 value_igi = DM_DIG_FA_UPPER;
259 else if (value_igi < DM_DIG_FA_LOWER)
260 value_igi = DM_DIG_FA_LOWER;
261 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
262 value_igi = 0x32;
263
264 dm_digtable.cur_igvalue = value_igi;
265 rtl92c_dm_write_dig(hw);
266}
267
268static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
269{
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271
272 if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable.fa_highthresh) {
273 if ((dm_digtable.backoff_val - 2) <
274 dm_digtable.backoff_val_range_min)
275 dm_digtable.backoff_val =
276 dm_digtable.backoff_val_range_min;
277 else
278 dm_digtable.backoff_val -= 2;
279 } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable.fa_lowthresh) {
280 if ((dm_digtable.backoff_val + 2) >
281 dm_digtable.backoff_val_range_max)
282 dm_digtable.backoff_val =
283 dm_digtable.backoff_val_range_max;
284 else
285 dm_digtable.backoff_val += 2;
286 }
287
288 if ((dm_digtable.rssi_val_min + 10 - dm_digtable.backoff_val) >
289 dm_digtable.rx_gain_range_max)
290 dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_max;
291 else if ((dm_digtable.rssi_val_min + 10 -
292 dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
293 dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_min;
294 else
295 dm_digtable.cur_igvalue = dm_digtable.rssi_val_min + 10 -
296 dm_digtable.backoff_val;
297
298 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
299 ("rssi_val_min = %x backoff_val %x\n",
300 dm_digtable.rssi_val_min, dm_digtable.backoff_val));
301
302 rtl92c_dm_write_dig(hw);
303}
304
305static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
306{
307 static u8 binitialized; /* initialized to false */
308 struct rtl_priv *rtlpriv = rtl_priv(hw);
309 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
310 long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
311 bool multi_sta = false;
312
313 if (mac->opmode == NL80211_IFTYPE_ADHOC)
314 multi_sta = true;
315
316 if ((multi_sta == false) || (dm_digtable.cursta_connectctate !=
317 DIG_STA_DISCONNECT)) {
318 binitialized = false;
319 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
320 return;
321 } else if (binitialized == false) {
322 binitialized = true;
323 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
324 dm_digtable.cur_igvalue = 0x20;
325 rtl92c_dm_write_dig(hw);
326 }
327
328 if (dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) {
329 if ((rssi_strength < dm_digtable.rssi_lowthresh) &&
330 (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
331
332 if (dm_digtable.dig_ext_port_stage ==
333 DIG_EXT_PORT_STAGE_2) {
334 dm_digtable.cur_igvalue = 0x20;
335 rtl92c_dm_write_dig(hw);
336 }
337
338 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
339 } else if (rssi_strength > dm_digtable.rssi_highthresh) {
340 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
341 rtl92c_dm_ctrl_initgain_by_fa(hw);
342 }
343 } else if (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
344 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
345 dm_digtable.cur_igvalue = 0x20;
346 rtl92c_dm_write_dig(hw);
347 }
348
349 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
350 ("curmultista_connectstate = "
351 "%x dig_ext_port_stage %x\n",
352 dm_digtable.curmultista_connectstate,
353 dm_digtable.dig_ext_port_stage));
354}
355
356static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
357{
358 struct rtl_priv *rtlpriv = rtl_priv(hw);
359
360 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
361 ("presta_connectstate = %x,"
362 " cursta_connectctate = %x\n",
363 dm_digtable.presta_connectstate,
364 dm_digtable.cursta_connectctate));
365
366 if (dm_digtable.presta_connectstate == dm_digtable.cursta_connectctate
367 || dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT
368 || dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
369
370 if (dm_digtable.cursta_connectctate != DIG_STA_DISCONNECT) {
371 dm_digtable.rssi_val_min =
372 rtl92c_dm_initial_gain_min_pwdb(hw);
373 rtl92c_dm_ctrl_initgain_by_rssi(hw);
374 }
375 } else {
376 dm_digtable.rssi_val_min = 0;
377 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
378 dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
379 dm_digtable.cur_igvalue = 0x20;
380 dm_digtable.pre_igvalue = 0;
381 rtl92c_dm_write_dig(hw);
382 }
383}
384
385static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
386{
387 struct rtl_priv *rtlpriv = rtl_priv(hw);
388 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
389
390 if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
391 dm_digtable.rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
392
393 if (dm_digtable.pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
394 if (dm_digtable.rssi_val_min <= 25)
395 dm_digtable.cur_cck_pd_state =
396 CCK_PD_STAGE_LowRssi;
397 else
398 dm_digtable.cur_cck_pd_state =
399 CCK_PD_STAGE_HighRssi;
400 } else {
401 if (dm_digtable.rssi_val_min <= 20)
402 dm_digtable.cur_cck_pd_state =
403 CCK_PD_STAGE_LowRssi;
404 else
405 dm_digtable.cur_cck_pd_state =
406 CCK_PD_STAGE_HighRssi;
407 }
408 } else {
409 dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
410 }
411
412 if (dm_digtable.pre_cck_pd_state != dm_digtable.cur_cck_pd_state) {
413 if (dm_digtable.cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
414 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
415 dm_digtable.cur_cck_fa_state =
416 CCK_FA_STAGE_High;
417 else
418 dm_digtable.cur_cck_fa_state = CCK_FA_STAGE_Low;
419
420 if (dm_digtable.pre_cck_fa_state !=
421 dm_digtable.cur_cck_fa_state) {
422 if (dm_digtable.cur_cck_fa_state ==
423 CCK_FA_STAGE_Low)
424 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
425 0x83);
426 else
427 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
428 0xcd);
429
430 dm_digtable.pre_cck_fa_state =
431 dm_digtable.cur_cck_fa_state;
432 }
433
434 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
435
436 if (IS_92C_SERIAL(rtlhal->version))
437 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
438 MASKBYTE2, 0xd7);
439 } else {
440 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
441 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
442
443 if (IS_92C_SERIAL(rtlhal->version))
444 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
445 MASKBYTE2, 0xd3);
446 }
447 dm_digtable.pre_cck_pd_state = dm_digtable.cur_cck_pd_state;
448 }
449
450 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
451 ("CCKPDStage=%x\n", dm_digtable.cur_cck_pd_state));
452
453 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
454 ("is92C=%x\n", IS_92C_SERIAL(rtlhal->version)));
455}
456
457static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
458{
459 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
460
461 if (mac->act_scanning == true)
462 return;
463
464 if ((mac->link_state > MAC80211_NOLINK) &&
465 (mac->link_state < MAC80211_LINKED))
466 dm_digtable.cursta_connectctate = DIG_STA_BEFORE_CONNECT;
467 else if (mac->link_state >= MAC80211_LINKED)
468 dm_digtable.cursta_connectctate = DIG_STA_CONNECT;
469 else
470 dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
471
472 rtl92c_dm_initial_gain_sta(hw);
473 rtl92c_dm_initial_gain_multi_sta(hw);
474 rtl92c_dm_cck_packet_detection_thresh(hw);
475
476 dm_digtable.presta_connectstate = dm_digtable.cursta_connectctate;
477
478}
479
480static void rtl92c_dm_dig(struct ieee80211_hw *hw)
481{
482 struct rtl_priv *rtlpriv = rtl_priv(hw);
483
484 if (rtlpriv->dm.dm_initialgain_enable == false)
485 return;
486 if (dm_digtable.dig_enable_flag == false)
487 return;
488
489 rtl92c_dm_ctrl_initgain_by_twoport(hw);
490
491}
492
493static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
494{
495 struct rtl_priv *rtlpriv = rtl_priv(hw);
496
497 rtlpriv->dm.dynamic_txpower_enable = false;
498
499 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
500 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
501}
502
503void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
504{
505 struct rtl_priv *rtlpriv = rtl_priv(hw);
506
507 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
508 ("cur_igvalue = 0x%x, "
509 "pre_igvalue = 0x%x, backoff_val = %d\n",
510 dm_digtable.cur_igvalue, dm_digtable.pre_igvalue,
511 dm_digtable.backoff_val));
512
513 if (dm_digtable.pre_igvalue != dm_digtable.cur_igvalue) {
514 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
515 dm_digtable.cur_igvalue);
516 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
517 dm_digtable.cur_igvalue);
518
519 dm_digtable.pre_igvalue = dm_digtable.cur_igvalue;
520 }
521}
522EXPORT_SYMBOL(rtl92c_dm_write_dig);
523
524static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
525{
526 struct rtl_priv *rtlpriv = rtl_priv(hw);
527 long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
528
529 u8 h2c_parameter[3] = { 0 };
530
531 return;
532
533 if (tmpentry_max_pwdb != 0) {
534 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
535 tmpentry_max_pwdb;
536 } else {
537 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
538 }
539
540 if (tmpentry_min_pwdb != 0xff) {
541 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
542 tmpentry_min_pwdb;
543 } else {
544 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
545 }
546
547 h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
548 h2c_parameter[0] = 0;
549
550 rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
551}
552
553void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
554{
555 struct rtl_priv *rtlpriv = rtl_priv(hw);
556 rtlpriv->dm.current_turbo_edca = false;
557 rtlpriv->dm.is_any_nonbepkts = false;
558 rtlpriv->dm.is_cur_rdlstate = false;
559}
560EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
561
562static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
563{
564 struct rtl_priv *rtlpriv = rtl_priv(hw);
565 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
566 static u64 last_txok_cnt;
567 static u64 last_rxok_cnt;
568 u64 cur_txok_cnt;
569 u64 cur_rxok_cnt;
570 u32 edca_be_ul = 0x5ea42b;
571 u32 edca_be_dl = 0x5ea42b;
572
573 if (mac->opmode == NL80211_IFTYPE_ADHOC)
574 goto dm_checkedcaturbo_exit;
575
576 if (mac->link_state != MAC80211_LINKED) {
577 rtlpriv->dm.current_turbo_edca = false;
578 return;
579 }
580
581 if (!mac->ht_enable) { /*FIX MERGE */
582 if (!(edca_be_ul & 0xffff0000))
583 edca_be_ul |= 0x005e0000;
584
585 if (!(edca_be_dl & 0xffff0000))
586 edca_be_dl |= 0x005e0000;
587 }
588
589 if ((!rtlpriv->dm.is_any_nonbepkts) &&
590 (!rtlpriv->dm.disable_framebursting)) {
591 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
592 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
593 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
594 if (!rtlpriv->dm.is_cur_rdlstate ||
595 !rtlpriv->dm.current_turbo_edca) {
596 rtl_write_dword(rtlpriv,
597 REG_EDCA_BE_PARAM,
598 edca_be_dl);
599 rtlpriv->dm.is_cur_rdlstate = true;
600 }
601 } else {
602 if (rtlpriv->dm.is_cur_rdlstate ||
603 !rtlpriv->dm.current_turbo_edca) {
604 rtl_write_dword(rtlpriv,
605 REG_EDCA_BE_PARAM,
606 edca_be_ul);
607 rtlpriv->dm.is_cur_rdlstate = false;
608 }
609 }
610 rtlpriv->dm.current_turbo_edca = true;
611 } else {
612 if (rtlpriv->dm.current_turbo_edca) {
613 u8 tmp = AC0_BE;
614 rtlpriv->cfg->ops->set_hw_reg(hw,
615 HW_VAR_AC_PARAM,
616 (u8 *) (&tmp));
617 rtlpriv->dm.current_turbo_edca = false;
618 }
619 }
620
621dm_checkedcaturbo_exit:
622 rtlpriv->dm.is_any_nonbepkts = false;
623 last_txok_cnt = rtlpriv->stats.txbytesunicast;
624 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
625}
626
627static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
628 *hw)
629{
630 struct rtl_priv *rtlpriv = rtl_priv(hw);
631 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
632 struct rtl_phy *rtlphy = &(rtlpriv->phy);
633 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
634 u8 thermalvalue, delta, delta_lck, delta_iqk;
635 long ele_a, ele_d, temp_cck, val_x, value32;
636 long val_y, ele_c;
637 u8 ofdm_index[2], cck_index, ofdm_index_old[2], cck_index_old;
638 int i;
639 bool is2t = IS_92C_SERIAL(rtlhal->version);
640 u8 txpwr_level[2] = {0, 0};
641 u8 ofdm_min_index = 6, rf;
642
643 rtlpriv->dm.txpower_trackingInit = true;
644 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
645 ("rtl92c_dm_txpower_tracking_callback_thermalmeter\n"));
646
647 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
648
649 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
650 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
651 "eeprom_thermalmeter 0x%x\n",
652 thermalvalue, rtlpriv->dm.thermalvalue,
653 rtlefuse->eeprom_thermalmeter));
654
655 rtl92c_phy_ap_calibrate(hw, (thermalvalue -
656 rtlefuse->eeprom_thermalmeter));
657 if (is2t)
658 rf = 2;
659 else
660 rf = 1;
661
662 if (thermalvalue) {
663 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
664 MASKDWORD) & MASKOFDM_D;
665
666 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
667 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
668 ofdm_index_old[0] = (u8) i;
669
670 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
671 ("Initial pathA ele_d reg0x%x = 0x%lx, "
672 "ofdm_index=0x%x\n",
673 ROFDM0_XATXIQIMBALANCE,
674 ele_d, ofdm_index_old[0]));
675 break;
676 }
677 }
678
679 if (is2t) {
680 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
681 MASKDWORD) & MASKOFDM_D;
682
683 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
684 if (ele_d == (ofdmswing_table[i] &
685 MASKOFDM_D)) {
686 ofdm_index_old[1] = (u8) i;
687
688 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
689 DBG_LOUD,
690 ("Initial pathB ele_d reg0x%x = "
691 "0x%lx, ofdm_index=0x%x\n",
692 ROFDM0_XBTXIQIMBALANCE, ele_d,
693 ofdm_index_old[1]));
694 break;
695 }
696 }
697 }
698
699 temp_cck =
700 rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
701
702 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
703 if (rtlpriv->dm.cck_inch14) {
704 if (memcmp((void *)&temp_cck,
705 (void *)&cckswing_table_ch14[i][2],
706 4) == 0) {
707 cck_index_old = (u8) i;
708
709 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
710 DBG_LOUD,
711 ("Initial reg0x%x = 0x%lx, "
712 "cck_index=0x%x, ch 14 %d\n",
713 RCCK0_TXFILTER2, temp_cck,
714 cck_index_old,
715 rtlpriv->dm.cck_inch14));
716 break;
717 }
718 } else {
719 if (memcmp((void *)&temp_cck,
720 (void *)
721 &cckswing_table_ch1ch13[i][2],
722 4) == 0) {
723 cck_index_old = (u8) i;
724
725 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
726 DBG_LOUD,
727 ("Initial reg0x%x = 0x%lx, "
728 "cck_index=0x%x, ch14 %d\n",
729 RCCK0_TXFILTER2, temp_cck,
730 cck_index_old,
731 rtlpriv->dm.cck_inch14));
732 break;
733 }
734 }
735 }
736
737 if (!rtlpriv->dm.thermalvalue) {
738 rtlpriv->dm.thermalvalue =
739 rtlefuse->eeprom_thermalmeter;
740 rtlpriv->dm.thermalvalue_lck = thermalvalue;
741 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
742 for (i = 0; i < rf; i++)
743 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
744 rtlpriv->dm.cck_index = cck_index_old;
745 }
746
747 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
748 (thermalvalue - rtlpriv->dm.thermalvalue) :
749 (rtlpriv->dm.thermalvalue - thermalvalue);
750
751 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
752 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
753 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
754
755 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
756 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
757 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
758
759 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
760 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
761 "eeprom_thermalmeter 0x%x delta 0x%x "
762 "delta_lck 0x%x delta_iqk 0x%x\n",
763 thermalvalue, rtlpriv->dm.thermalvalue,
764 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
765 delta_iqk));
766
767 if (delta_lck > 1) {
768 rtlpriv->dm.thermalvalue_lck = thermalvalue;
769 rtl92c_phy_lc_calibrate(hw);
770 }
771
772 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
773 if (thermalvalue > rtlpriv->dm.thermalvalue) {
774 for (i = 0; i < rf; i++)
775 rtlpriv->dm.ofdm_index[i] -= delta;
776 rtlpriv->dm.cck_index -= delta;
777 } else {
778 for (i = 0; i < rf; i++)
779 rtlpriv->dm.ofdm_index[i] += delta;
780 rtlpriv->dm.cck_index += delta;
781 }
782
783 if (is2t) {
784 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
785 ("temp OFDM_A_index=0x%x, "
786 "OFDM_B_index=0x%x,"
787 "cck_index=0x%x\n",
788 rtlpriv->dm.ofdm_index[0],
789 rtlpriv->dm.ofdm_index[1],
790 rtlpriv->dm.cck_index));
791 } else {
792 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
793 ("temp OFDM_A_index=0x%x,"
794 "cck_index=0x%x\n",
795 rtlpriv->dm.ofdm_index[0],
796 rtlpriv->dm.cck_index));
797 }
798
799 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
800 for (i = 0; i < rf; i++)
801 ofdm_index[i] =
802 rtlpriv->dm.ofdm_index[i]
803 + 1;
804 cck_index = rtlpriv->dm.cck_index + 1;
805 } else {
806 for (i = 0; i < rf; i++)
807 ofdm_index[i] =
808 rtlpriv->dm.ofdm_index[i];
809 cck_index = rtlpriv->dm.cck_index;
810 }
811
812 for (i = 0; i < rf; i++) {
813 if (txpwr_level[i] >= 0 &&
814 txpwr_level[i] <= 26) {
815 if (thermalvalue >
816 rtlefuse->eeprom_thermalmeter) {
817 if (delta < 5)
818 ofdm_index[i] -= 1;
819
820 else
821 ofdm_index[i] -= 2;
822 } else if (delta > 5 && thermalvalue <
823 rtlefuse->
824 eeprom_thermalmeter) {
825 ofdm_index[i] += 1;
826 }
827 } else if (txpwr_level[i] >= 27 &&
828 txpwr_level[i] <= 32
829 && thermalvalue >
830 rtlefuse->eeprom_thermalmeter) {
831 if (delta < 5)
832 ofdm_index[i] -= 1;
833
834 else
835 ofdm_index[i] -= 2;
836 } else if (txpwr_level[i] >= 32 &&
837 txpwr_level[i] <= 38 &&
838 thermalvalue >
839 rtlefuse->eeprom_thermalmeter
840 && delta > 5) {
841 ofdm_index[i] -= 1;
842 }
843 }
844
845 if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
846 if (thermalvalue >
847 rtlefuse->eeprom_thermalmeter) {
848 if (delta < 5)
849 cck_index -= 1;
850
851 else
852 cck_index -= 2;
853 } else if (delta > 5 && thermalvalue <
854 rtlefuse->eeprom_thermalmeter) {
855 cck_index += 1;
856 }
857 } else if (txpwr_level[i] >= 27 &&
858 txpwr_level[i] <= 32 &&
859 thermalvalue >
860 rtlefuse->eeprom_thermalmeter) {
861 if (delta < 5)
862 cck_index -= 1;
863
864 else
865 cck_index -= 2;
866 } else if (txpwr_level[i] >= 32 &&
867 txpwr_level[i] <= 38 &&
868 thermalvalue > rtlefuse->eeprom_thermalmeter
869 && delta > 5) {
870 cck_index -= 1;
871 }
872
873 for (i = 0; i < rf; i++) {
874 if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
875 ofdm_index[i] = OFDM_TABLE_SIZE - 1;
876
877 else if (ofdm_index[i] < ofdm_min_index)
878 ofdm_index[i] = ofdm_min_index;
879 }
880
881 if (cck_index > CCK_TABLE_SIZE - 1)
882 cck_index = CCK_TABLE_SIZE - 1;
883 else if (cck_index < 0)
884 cck_index = 0;
885
886 if (is2t) {
887 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
888 ("new OFDM_A_index=0x%x, "
889 "OFDM_B_index=0x%x,"
890 "cck_index=0x%x\n",
891 ofdm_index[0], ofdm_index[1],
892 cck_index));
893 } else {
894 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
895 ("new OFDM_A_index=0x%x,"
896 "cck_index=0x%x\n",
897 ofdm_index[0], cck_index));
898 }
899 }
900
901 if (rtlpriv->dm.txpower_track_control && delta != 0) {
902 ele_d =
903 (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
904 val_x = rtlphy->reg_e94;
905 val_y = rtlphy->reg_e9c;
906
907 if (val_x != 0) {
908 if ((val_x & 0x00000200) != 0)
909 val_x = val_x | 0xFFFFFC00;
910 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
911
912 if ((val_y & 0x00000200) != 0)
913 val_y = val_y | 0xFFFFFC00;
914 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
915
916 value32 = (ele_d << 22) |
917 ((ele_c & 0x3F) << 16) | ele_a;
918
919 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
920 MASKDWORD, value32);
921
922 value32 = (ele_c & 0x000003C0) >> 6;
923 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
924 value32);
925
926 value32 = ((val_x * ele_d) >> 7) & 0x01;
927 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
928 BIT(31), value32);
929
930 value32 = ((val_y * ele_d) >> 7) & 0x01;
931 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
932 BIT(29), value32);
933 } else {
934 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
935 MASKDWORD,
936 ofdmswing_table[ofdm_index[0]]);
937
938 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
939 0x00);
940 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
941 BIT(31) | BIT(29), 0x00);
942 }
943
944 if (!rtlpriv->dm.cck_inch14) {
945 rtl_write_byte(rtlpriv, 0xa22,
946 cckswing_table_ch1ch13[cck_index]
947 [0]);
948 rtl_write_byte(rtlpriv, 0xa23,
949 cckswing_table_ch1ch13[cck_index]
950 [1]);
951 rtl_write_byte(rtlpriv, 0xa24,
952 cckswing_table_ch1ch13[cck_index]
953 [2]);
954 rtl_write_byte(rtlpriv, 0xa25,
955 cckswing_table_ch1ch13[cck_index]
956 [3]);
957 rtl_write_byte(rtlpriv, 0xa26,
958 cckswing_table_ch1ch13[cck_index]
959 [4]);
960 rtl_write_byte(rtlpriv, 0xa27,
961 cckswing_table_ch1ch13[cck_index]
962 [5]);
963 rtl_write_byte(rtlpriv, 0xa28,
964 cckswing_table_ch1ch13[cck_index]
965 [6]);
966 rtl_write_byte(rtlpriv, 0xa29,
967 cckswing_table_ch1ch13[cck_index]
968 [7]);
969 } else {
970 rtl_write_byte(rtlpriv, 0xa22,
971 cckswing_table_ch14[cck_index]
972 [0]);
973 rtl_write_byte(rtlpriv, 0xa23,
974 cckswing_table_ch14[cck_index]
975 [1]);
976 rtl_write_byte(rtlpriv, 0xa24,
977 cckswing_table_ch14[cck_index]
978 [2]);
979 rtl_write_byte(rtlpriv, 0xa25,
980 cckswing_table_ch14[cck_index]
981 [3]);
982 rtl_write_byte(rtlpriv, 0xa26,
983 cckswing_table_ch14[cck_index]
984 [4]);
985 rtl_write_byte(rtlpriv, 0xa27,
986 cckswing_table_ch14[cck_index]
987 [5]);
988 rtl_write_byte(rtlpriv, 0xa28,
989 cckswing_table_ch14[cck_index]
990 [6]);
991 rtl_write_byte(rtlpriv, 0xa29,
992 cckswing_table_ch14[cck_index]
993 [7]);
994 }
995
996 if (is2t) {
997 ele_d = (ofdmswing_table[ofdm_index[1]] &
998 0xFFC00000) >> 22;
999
1000 val_x = rtlphy->reg_eb4;
1001 val_y = rtlphy->reg_ebc;
1002
1003 if (val_x != 0) {
1004 if ((val_x & 0x00000200) != 0)
1005 val_x = val_x | 0xFFFFFC00;
1006 ele_a = ((val_x * ele_d) >> 8) &
1007 0x000003FF;
1008
1009 if ((val_y & 0x00000200) != 0)
1010 val_y = val_y | 0xFFFFFC00;
1011 ele_c = ((val_y * ele_d) >> 8) &
1012 0x00003FF;
1013
1014 value32 = (ele_d << 22) |
1015 ((ele_c & 0x3F) << 16) | ele_a;
1016 rtl_set_bbreg(hw,
1017 ROFDM0_XBTXIQIMBALANCE,
1018 MASKDWORD, value32);
1019
1020 value32 = (ele_c & 0x000003C0) >> 6;
1021 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1022 MASKH4BITS, value32);
1023
1024 value32 = ((val_x * ele_d) >> 7) & 0x01;
1025 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1026 BIT(27), value32);
1027
1028 value32 = ((val_y * ele_d) >> 7) & 0x01;
1029 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1030 BIT(25), value32);
1031 } else {
1032 rtl_set_bbreg(hw,
1033 ROFDM0_XBTXIQIMBALANCE,
1034 MASKDWORD,
1035 ofdmswing_table[ofdm_index
1036 [1]]);
1037 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1038 MASKH4BITS, 0x00);
1039 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1040 BIT(27) | BIT(25), 0x00);
1041 }
1042
1043 }
1044 }
1045
1046 if (delta_iqk > 3) {
1047 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1048 rtl92c_phy_iq_calibrate(hw, false);
1049 }
1050
1051 if (rtlpriv->dm.txpower_track_control)
1052 rtlpriv->dm.thermalvalue = thermalvalue;
1053 }
1054
1055 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("<===\n"));
1056
1057}
1058
1059static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
1060 struct ieee80211_hw *hw)
1061{
1062 struct rtl_priv *rtlpriv = rtl_priv(hw);
1063
1064 rtlpriv->dm.txpower_tracking = true;
1065 rtlpriv->dm.txpower_trackingInit = false;
1066
1067 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1068 ("pMgntInfo->txpower_tracking = %d\n",
1069 rtlpriv->dm.txpower_tracking));
1070}
1071
1072static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1073{
1074 rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
1075}
1076
1077static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
1078{
1079 rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
1080}
1081
1082static void rtl92c_dm_check_txpower_tracking_thermal_meter(
1083 struct ieee80211_hw *hw)
1084{
1085 struct rtl_priv *rtlpriv = rtl_priv(hw);
1086 static u8 tm_trigger;
1087
1088 if (!rtlpriv->dm.txpower_tracking)
1089 return;
1090
1091 if (!tm_trigger) {
1092 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
1093 0x60);
1094 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1095 ("Trigger 92S Thermal Meter!!\n"));
1096 tm_trigger = 1;
1097 return;
1098 } else {
1099 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1100 ("Schedule TxPowerTracking direct call!!\n"));
1101 rtl92c_dm_txpower_tracking_directcall(hw);
1102 tm_trigger = 0;
1103 }
1104}
1105
1106void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1107{
1108 rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
1109}
1110EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
1111
1112void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1113{
1114 struct rtl_priv *rtlpriv = rtl_priv(hw);
1115 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1116
1117 p_ra->ratr_state = DM_RATR_STA_INIT;
1118 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1119
1120 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1121 rtlpriv->dm.useramask = true;
1122 else
1123 rtlpriv->dm.useramask = false;
1124
1125}
1126EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
1127
1128static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1129{
1130 struct rtl_priv *rtlpriv = rtl_priv(hw);
1131 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1132 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1133 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1134 u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
1135
1136 if (is_hal_stop(rtlhal)) {
1137 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1138 ("<---- driver is going to unload\n"));
1139 return;
1140 }
1141
1142 if (!rtlpriv->dm.useramask) {
1143 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1144 ("<---- driver does not control rate adaptive mask\n"));
1145 return;
1146 }
1147
1148 if (mac->link_state == MAC80211_LINKED) {
1149
1150 switch (p_ra->pre_ratr_state) {
1151 case DM_RATR_STA_HIGH:
1152 high_rssithresh_for_ra = 50;
1153 low_rssithresh_for_ra = 20;
1154 break;
1155 case DM_RATR_STA_MIDDLE:
1156 high_rssithresh_for_ra = 55;
1157 low_rssithresh_for_ra = 20;
1158 break;
1159 case DM_RATR_STA_LOW:
1160 high_rssithresh_for_ra = 50;
1161 low_rssithresh_for_ra = 25;
1162 break;
1163 default:
1164 high_rssithresh_for_ra = 50;
1165 low_rssithresh_for_ra = 20;
1166 break;
1167 }
1168
1169 if (rtlpriv->dm.undecorated_smoothed_pwdb >
1170 (long)high_rssithresh_for_ra)
1171 p_ra->ratr_state = DM_RATR_STA_HIGH;
1172 else if (rtlpriv->dm.undecorated_smoothed_pwdb >
1173 (long)low_rssithresh_for_ra)
1174 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
1175 else
1176 p_ra->ratr_state = DM_RATR_STA_LOW;
1177
1178 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
1179 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1180 ("RSSI = %ld\n",
1181 rtlpriv->dm.undecorated_smoothed_pwdb));
1182 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1183 ("RSSI_LEVEL = %d\n", p_ra->ratr_state));
1184 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1185 ("PreState = %d, CurState = %d\n",
1186 p_ra->pre_ratr_state, p_ra->ratr_state));
1187
1188 rtlpriv->cfg->ops->update_rate_mask(hw,
1189 p_ra->ratr_state);
1190
1191 p_ra->pre_ratr_state = p_ra->ratr_state;
1192 }
1193 }
1194}
1195
1196static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1197{
1198 dm_pstable.pre_ccastate = CCA_MAX;
1199 dm_pstable.cur_ccasate = CCA_MAX;
1200 dm_pstable.pre_rfstate = RF_MAX;
1201 dm_pstable.cur_rfstate = RF_MAX;
1202 dm_pstable.rssi_val_min = 0;
1203}
1204
1205static void rtl92c_dm_1r_cca(struct ieee80211_hw *hw)
1206{
1207 struct rtl_priv *rtlpriv = rtl_priv(hw);
1208 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1209
1210 if (dm_pstable.rssi_val_min != 0) {
1211 if (dm_pstable.pre_ccastate == CCA_2R) {
1212 if (dm_pstable.rssi_val_min >= 35)
1213 dm_pstable.cur_ccasate = CCA_1R;
1214 else
1215 dm_pstable.cur_ccasate = CCA_2R;
1216 } else {
1217 if (dm_pstable.rssi_val_min <= 30)
1218 dm_pstable.cur_ccasate = CCA_2R;
1219 else
1220 dm_pstable.cur_ccasate = CCA_1R;
1221 }
1222 } else {
1223 dm_pstable.cur_ccasate = CCA_MAX;
1224 }
1225
1226 if (dm_pstable.pre_ccastate != dm_pstable.cur_ccasate) {
1227 if (dm_pstable.cur_ccasate == CCA_1R) {
1228 if (get_rf_type(rtlphy) == RF_2T2R) {
1229 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
1230 MASKBYTE0, 0x13);
1231 rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x20);
1232 } else {
1233 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
1234 MASKBYTE0, 0x23);
1235 rtl_set_bbreg(hw, 0xe70, 0x7fc00000, 0x10c);
1236 }
1237 } else {
1238 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0,
1239 0x33);
1240 rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x63);
1241 }
1242 dm_pstable.pre_ccastate = dm_pstable.cur_ccasate;
1243 }
1244
1245 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, ("CCAStage = %s\n",
1246 (dm_pstable.cur_ccasate ==
1247 0) ? "1RCCA" : "2RCCA"));
1248}
1249
1250void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
1251{
1252 static u8 initialize;
1253 static u32 reg_874, reg_c70, reg_85c, reg_a74;
1254
1255 if (initialize == 0) {
1256 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1257 MASKDWORD) & 0x1CC000) >> 14;
1258
1259 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
1260 MASKDWORD) & BIT(3)) >> 3;
1261
1262 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1263 MASKDWORD) & 0xFF000000) >> 24;
1264
1265 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
1266
1267 initialize = 1;
1268 }
1269
1270 if (!bforce_in_normal) {
1271 if (dm_pstable.rssi_val_min != 0) {
1272 if (dm_pstable.pre_rfstate == RF_NORMAL) {
1273 if (dm_pstable.rssi_val_min >= 30)
1274 dm_pstable.cur_rfstate = RF_SAVE;
1275 else
1276 dm_pstable.cur_rfstate = RF_NORMAL;
1277 } else {
1278 if (dm_pstable.rssi_val_min <= 25)
1279 dm_pstable.cur_rfstate = RF_NORMAL;
1280 else
1281 dm_pstable.cur_rfstate = RF_SAVE;
1282 }
1283 } else {
1284 dm_pstable.cur_rfstate = RF_MAX;
1285 }
1286 } else {
1287 dm_pstable.cur_rfstate = RF_NORMAL;
1288 }
1289
1290 if (dm_pstable.pre_rfstate != dm_pstable.cur_rfstate) {
1291 if (dm_pstable.cur_rfstate == RF_SAVE) {
1292 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1293 0x1C0000, 0x2);
1294 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
1295 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1296 0xFF000000, 0x63);
1297 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1298 0xC000, 0x2);
1299 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
1300 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1301 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
1302 } else {
1303 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1304 0x1CC000, reg_874);
1305 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
1306 reg_c70);
1307 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
1308 reg_85c);
1309 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
1310 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1311 }
1312
1313 dm_pstable.pre_rfstate = dm_pstable.cur_rfstate;
1314 }
1315}
1316EXPORT_SYMBOL(rtl92c_dm_rf_saving);
1317
1318static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1319{
1320 struct rtl_priv *rtlpriv = rtl_priv(hw);
1321 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1322 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1323
1324 if (((mac->link_state == MAC80211_NOLINK)) &&
1325 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
1326 dm_pstable.rssi_val_min = 0;
1327 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1328 ("Not connected to any\n"));
1329 }
1330
1331 if (mac->link_state == MAC80211_LINKED) {
1332 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1333 dm_pstable.rssi_val_min =
1334 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1335 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1336 ("AP Client PWDB = 0x%lx\n",
1337 dm_pstable.rssi_val_min));
1338 } else {
1339 dm_pstable.rssi_val_min =
1340 rtlpriv->dm.undecorated_smoothed_pwdb;
1341 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1342 ("STA Default Port PWDB = 0x%lx\n",
1343 dm_pstable.rssi_val_min));
1344 }
1345 } else {
1346 dm_pstable.rssi_val_min =
1347 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1348
1349 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1350 ("AP Ext Port PWDB = 0x%lx\n",
1351 dm_pstable.rssi_val_min));
1352 }
1353
1354 if (IS_92C_SERIAL(rtlhal->version))
1355 rtl92c_dm_1r_cca(hw);
1356}
1357
1358void rtl92c_dm_init(struct ieee80211_hw *hw)
1359{
1360 struct rtl_priv *rtlpriv = rtl_priv(hw);
1361
1362 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1363 rtl92c_dm_diginit(hw);
1364 rtl92c_dm_init_dynamic_txpower(hw);
1365 rtl92c_dm_init_edca_turbo(hw);
1366 rtl92c_dm_init_rate_adaptive_mask(hw);
1367 rtl92c_dm_initialize_txpower_tracking(hw);
1368 rtl92c_dm_init_dynamic_bb_powersaving(hw);
1369}
1370EXPORT_SYMBOL(rtl92c_dm_init);
1371
1372void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
1373{
1374 struct rtl_priv *rtlpriv = rtl_priv(hw);
1375 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1376 bool fw_current_inpsmode = false;
1377 bool fw_ps_awake = true;
1378
1379 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1380 (u8 *) (&fw_current_inpsmode));
1381 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1382 (u8 *) (&fw_ps_awake));
1383
1384 if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
1385 fw_ps_awake)
1386 && (!ppsc->rfchange_inprogress)) {
1387 rtl92c_dm_pwdb_monitor(hw);
1388 rtl92c_dm_dig(hw);
1389 rtl92c_dm_false_alarm_counter_statistics(hw);
1390 rtl92c_dm_dynamic_bb_powersaving(hw);
1391 rtlpriv->cfg->ops->dm_dynamic_txpower(hw);
1392 rtl92c_dm_check_txpower_tracking(hw);
1393 rtl92c_dm_refresh_rate_adaptive_mask(hw);
1394 rtl92c_dm_check_edca_turbo(hw);
1395
1396 }
1397}
1398EXPORT_SYMBOL(rtl92c_dm_watchdog);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/dm_common.h b/drivers/net/wireless/rtlwifi/rtl8192c/dm_common.h
new file mode 100644
index 000000000000..b9cbb0a3c03f
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/dm_common.h
@@ -0,0 +1,204 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92COMMON_DM_H__
31#define __RTL92COMMON_DM_H__
32
33#include "../wifi.h"
34#include "../rtl8192ce/def.h"
35#include "../rtl8192ce/reg.h"
36#include "fw_common.h"
37
38#define HAL_DM_DIG_DISABLE BIT(0)
39#define HAL_DM_HIPWR_DISABLE BIT(1)
40
41#define OFDM_TABLE_LENGTH 37
42#define CCK_TABLE_LENGTH 33
43
44#define OFDM_TABLE_SIZE 37
45#define CCK_TABLE_SIZE 33
46
47#define BW_AUTO_SWITCH_HIGH_LOW 25
48#define BW_AUTO_SWITCH_LOW_HIGH 30
49
50#define DM_DIG_THRESH_HIGH 40
51#define DM_DIG_THRESH_LOW 35
52
53#define DM_FALSEALARM_THRESH_LOW 400
54#define DM_FALSEALARM_THRESH_HIGH 1000
55
56#define DM_DIG_MAX 0x3e
57#define DM_DIG_MIN 0x1e
58
59#define DM_DIG_FA_UPPER 0x32
60#define DM_DIG_FA_LOWER 0x20
61#define DM_DIG_FA_TH0 0x20
62#define DM_DIG_FA_TH1 0x100
63#define DM_DIG_FA_TH2 0x200
64
65#define DM_DIG_BACKOFF_MAX 12
66#define DM_DIG_BACKOFF_MIN -4
67#define DM_DIG_BACKOFF_DEFAULT 10
68
69#define RXPATHSELECTION_SS_TH_lOW 30
70#define RXPATHSELECTION_DIFF_TH 18
71
72#define DM_RATR_STA_INIT 0
73#define DM_RATR_STA_HIGH 1
74#define DM_RATR_STA_MIDDLE 2
75#define DM_RATR_STA_LOW 3
76
77#define CTS2SELF_THVAL 30
78#define REGC38_TH 20
79
80#define WAIOTTHVal 25
81
82#define TXHIGHPWRLEVEL_NORMAL 0
83#define TXHIGHPWRLEVEL_LEVEL1 1
84#define TXHIGHPWRLEVEL_LEVEL2 2
85#define TXHIGHPWRLEVEL_BT1 3
86#define TXHIGHPWRLEVEL_BT2 4
87
88#define DM_TYPE_BYFW 0
89#define DM_TYPE_BYDRIVER 1
90
91#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
92#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
93
94struct ps_t {
95 u8 pre_ccastate;
96 u8 cur_ccasate;
97 u8 pre_rfstate;
98 u8 cur_rfstate;
99 long rssi_val_min;
100};
101
102struct dig_t {
103 u8 dig_enable_flag;
104 u8 dig_ext_port_stage;
105 u32 rssi_lowthresh;
106 u32 rssi_highthresh;
107 u32 fa_lowthresh;
108 u32 fa_highthresh;
109 u8 cursta_connectctate;
110 u8 presta_connectstate;
111 u8 curmultista_connectstate;
112 u8 pre_igvalue;
113 u8 cur_igvalue;
114 char backoff_val;
115 char backoff_val_range_max;
116 char backoff_val_range_min;
117 u8 rx_gain_range_max;
118 u8 rx_gain_range_min;
119 u8 rssi_val_min;
120 u8 pre_cck_pd_state;
121 u8 cur_cck_pd_state;
122 u8 pre_cck_fa_state;
123 u8 cur_cck_fa_state;
124 u8 pre_ccastate;
125 u8 cur_ccasate;
126};
127
128struct swat_t {
129 u8 failure_cnt;
130 u8 try_flag;
131 u8 stop_trying;
132 long pre_rssi;
133 long trying_threshold;
134 u8 cur_antenna;
135 u8 pre_antenna;
136};
137
138enum tag_dynamic_init_gain_operation_type_definition {
139 DIG_TYPE_THRESH_HIGH = 0,
140 DIG_TYPE_THRESH_LOW = 1,
141 DIG_TYPE_BACKOFF = 2,
142 DIG_TYPE_RX_GAIN_MIN = 3,
143 DIG_TYPE_RX_GAIN_MAX = 4,
144 DIG_TYPE_ENABLE = 5,
145 DIG_TYPE_DISABLE = 6,
146 DIG_OP_TYPE_MAX
147};
148
149enum tag_cck_packet_detection_threshold_type_definition {
150 CCK_PD_STAGE_LowRssi = 0,
151 CCK_PD_STAGE_HighRssi = 1,
152 CCK_FA_STAGE_Low = 2,
153 CCK_FA_STAGE_High = 3,
154 CCK_PD_STAGE_MAX = 4,
155};
156
157enum dm_1r_cca_e {
158 CCA_1R = 0,
159 CCA_2R = 1,
160 CCA_MAX = 2,
161};
162
163enum dm_rf_e {
164 RF_SAVE = 0,
165 RF_NORMAL = 1,
166 RF_MAX = 2,
167};
168
169enum dm_sw_ant_switch_e {
170 ANS_ANTENNA_B = 1,
171 ANS_ANTENNA_A = 2,
172 ANS_ANTENNA_MAX = 3,
173};
174
175enum dm_dig_ext_port_alg_e {
176 DIG_EXT_PORT_STAGE_0 = 0,
177 DIG_EXT_PORT_STAGE_1 = 1,
178 DIG_EXT_PORT_STAGE_2 = 2,
179 DIG_EXT_PORT_STAGE_3 = 3,
180 DIG_EXT_PORT_STAGE_MAX = 4,
181};
182
183enum dm_dig_connect_e {
184 DIG_STA_DISCONNECT = 0,
185 DIG_STA_CONNECT = 1,
186 DIG_STA_BEFORE_CONNECT = 2,
187 DIG_MULTISTA_DISCONNECT = 3,
188 DIG_MULTISTA_CONNECT = 4,
189 DIG_CONNECT_MAX
190};
191
192extern struct dig_t dm_digtable;
193void rtl92c_dm_init(struct ieee80211_hw *hw);
194void rtl92c_dm_watchdog(struct ieee80211_hw *hw);
195void rtl92c_dm_write_dig(struct ieee80211_hw *hw);
196void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw);
197void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw);
198void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
199void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
200void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
201void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
202void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery);
203
204#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/fw.c b/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.c
index 11dd22b987e7..5ef91374b230 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/fw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.c
@@ -31,10 +31,9 @@
31#include "../wifi.h" 31#include "../wifi.h"
32#include "../pci.h" 32#include "../pci.h"
33#include "../base.h" 33#include "../base.h"
34#include "reg.h" 34#include "../rtl8192ce/reg.h"
35#include "def.h" 35#include "../rtl8192ce/def.h"
36#include "fw.h" 36#include "fw_common.h"
37#include "table.h"
38 37
39static void _rtl92c_enable_fw_download(struct ieee80211_hw *hw, bool enable) 38static void _rtl92c_enable_fw_download(struct ieee80211_hw *hw, bool enable)
40{ 39{
@@ -133,17 +132,15 @@ static void _rtl92c_write_fw(struct ieee80211_hw *hw,
133{ 132{
134 struct rtl_priv *rtlpriv = rtl_priv(hw); 133 struct rtl_priv *rtlpriv = rtl_priv(hw);
135 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 134 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
136 bool is_version_b;
137 u8 *bufferPtr = (u8 *) buffer; 135 u8 *bufferPtr = (u8 *) buffer;
138 136
139 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, ("FW size is %d bytes,\n", size)); 137 RT_TRACE(rtlpriv, COMP_FW, DBG_TRACE, ("FW size is %d bytes,\n", size));
140 138
141 is_version_b = IS_CHIP_VER_B(version); 139 if (IS_CHIP_VER_B(version)) {
142 if (is_version_b) {
143 u32 pageNums, remainSize; 140 u32 pageNums, remainSize;
144 u32 page, offset; 141 u32 page, offset;
145 142
146 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE) 143 if (IS_HARDWARE_TYPE_8192CE(rtlhal))
147 _rtl92c_fill_dummy(bufferPtr, &size); 144 _rtl92c_fill_dummy(bufferPtr, &size);
148 145
149 pageNums = size / FW_8192C_PAGE_SIZE; 146 pageNums = size / FW_8192C_PAGE_SIZE;
@@ -231,14 +228,14 @@ int rtl92c_download_fw(struct ieee80211_hw *hw)
231 u32 fwsize; 228 u32 fwsize;
232 int err; 229 int err;
233 enum version_8192c version = rtlhal->version; 230 enum version_8192c version = rtlhal->version;
231 const struct firmware *firmware;
234 232
235 const struct firmware *firmware = NULL; 233 printk(KERN_INFO "rtl8192cu: Loading firmware file %s\n",
236 234 rtlpriv->cfg->fw_name);
237 err = request_firmware(&firmware, rtlpriv->cfg->fw_name, 235 err = request_firmware(&firmware, rtlpriv->cfg->fw_name,
238 rtlpriv->io.dev); 236 rtlpriv->io.dev);
239 if (err) { 237 if (err) {
240 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, 238 printk(KERN_ERR "rtl8192cu: Firmware loading failed\n");
241 ("Failed to request firmware!\n"));
242 return 1; 239 return 1;
243 } 240 }
244 241
@@ -281,6 +278,7 @@ int rtl92c_download_fw(struct ieee80211_hw *hw)
281 278
282 return 0; 279 return 0;
283} 280}
281EXPORT_SYMBOL(rtl92c_download_fw);
284 282
285static bool _rtl92c_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum) 283static bool _rtl92c_check_fw_read_last_h2c(struct ieee80211_hw *hw, u8 boxnum)
286{ 284{
@@ -318,12 +316,12 @@ static void _rtl92c_fill_h2c_command(struct ieee80211_hw *hw,
318 316
319 while (true) { 317 while (true) {
320 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); 318 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
321 if (rtlhal->b_h2c_setinprogress) { 319 if (rtlhal->h2c_setinprogress) {
322 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, 320 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD,
323 ("H2C set in progress! Wait to set.." 321 ("H2C set in progress! Wait to set.."
324 "element_id(%d).\n", element_id)); 322 "element_id(%d).\n", element_id));
325 323
326 while (rtlhal->b_h2c_setinprogress) { 324 while (rtlhal->h2c_setinprogress) {
327 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, 325 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock,
328 flag); 326 flag);
329 h2c_waitcounter++; 327 h2c_waitcounter++;
@@ -339,7 +337,7 @@ static void _rtl92c_fill_h2c_command(struct ieee80211_hw *hw,
339 } 337 }
340 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); 338 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
341 } else { 339 } else {
342 rtlhal->b_h2c_setinprogress = true; 340 rtlhal->h2c_setinprogress = true;
343 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); 341 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
344 break; 342 break;
345 } 343 }
@@ -495,7 +493,7 @@ static void _rtl92c_fill_h2c_command(struct ieee80211_hw *hw,
495 } 493 }
496 494
497 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag); 495 spin_lock_irqsave(&rtlpriv->locks.h2c_lock, flag);
498 rtlhal->b_h2c_setinprogress = false; 496 rtlhal->h2c_setinprogress = false;
499 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag); 497 spin_unlock_irqrestore(&rtlpriv->locks.h2c_lock, flag);
500 498
501 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("go out\n")); 499 RT_TRACE(rtlpriv, COMP_CMD, DBG_LOUD, ("go out\n"));
@@ -507,7 +505,7 @@ void rtl92c_fill_h2c_cmd(struct ieee80211_hw *hw,
507 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 505 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
508 u32 tmp_cmdbuf[2]; 506 u32 tmp_cmdbuf[2];
509 507
510 if (rtlhal->bfw_ready == false) { 508 if (rtlhal->fw_ready == false) {
511 RT_ASSERT(false, ("return H2C cmd because of Fw " 509 RT_ASSERT(false, ("return H2C cmd because of Fw "
512 "download fail!!!\n")); 510 "download fail!!!\n"));
513 return; 511 return;
@@ -519,6 +517,7 @@ void rtl92c_fill_h2c_cmd(struct ieee80211_hw *hw,
519 517
520 return; 518 return;
521} 519}
520EXPORT_SYMBOL(rtl92c_fill_h2c_cmd);
522 521
523void rtl92c_firmware_selfreset(struct ieee80211_hw *hw) 522void rtl92c_firmware_selfreset(struct ieee80211_hw *hw)
524{ 523{
@@ -539,6 +538,7 @@ void rtl92c_firmware_selfreset(struct ieee80211_hw *hw)
539 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1); 538 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
540 } 539 }
541} 540}
541EXPORT_SYMBOL(rtl92c_firmware_selfreset);
542 542
543void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode) 543void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
544{ 544{
@@ -559,39 +559,7 @@ void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode)
559 rtl92c_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode); 559 rtl92c_fill_h2c_cmd(hw, H2C_SETPWRMODE, 3, u1_h2c_set_pwrmode);
560 560
561} 561}
562 562EXPORT_SYMBOL(rtl92c_set_fw_pwrmode_cmd);
563static bool _rtl92c_cmd_send_packet(struct ieee80211_hw *hw,
564 struct sk_buff *skb)
565{
566 struct rtl_priv *rtlpriv = rtl_priv(hw);
567 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
568 struct rtl8192_tx_ring *ring;
569 struct rtl_tx_desc *pdesc;
570 u8 own;
571 unsigned long flags;
572 struct sk_buff *pskb = NULL;
573
574 ring = &rtlpci->tx_ring[BEACON_QUEUE];
575
576 pskb = __skb_dequeue(&ring->queue);
577 if (pskb)
578 kfree_skb(pskb);
579
580 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
581
582 pdesc = &ring->desc[0];
583 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc, true, HW_DESC_OWN);
584
585 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
586
587 __skb_queue_tail(&ring->queue, skb);
588
589 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
590
591 rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
592
593 return true;
594}
595 563
596#define BEACON_PG 0 /*->1*/ 564#define BEACON_PG 0 /*->1*/
597#define PSPOLL_PG 2 565#define PSPOLL_PG 2
@@ -776,7 +744,7 @@ void rtl92c_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
776 memcpy((u8 *) skb_put(skb, totalpacketlen), 744 memcpy((u8 *) skb_put(skb, totalpacketlen),
777 &reserved_page_packet, totalpacketlen); 745 &reserved_page_packet, totalpacketlen);
778 746
779 rtstatus = _rtl92c_cmd_send_packet(hw, skb); 747 rtstatus = rtlpriv->cfg->ops->cmd_send_packet(hw, skb);
780 748
781 if (rtstatus) 749 if (rtstatus)
782 b_dlok = true; 750 b_dlok = true;
@@ -793,6 +761,7 @@ void rtl92c_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished)
793 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, 761 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
794 ("Set RSVD page location to Fw FAIL!!!!!!.\n")); 762 ("Set RSVD page location to Fw FAIL!!!!!!.\n"));
795} 763}
764EXPORT_SYMBOL(rtl92c_set_fw_rsvdpagepkt);
796 765
797void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus) 766void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
798{ 767{
@@ -802,3 +771,4 @@ void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus)
802 771
803 rtl92c_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm); 772 rtl92c_fill_h2c_cmd(hw, H2C_JOINBSSRPT, 1, u1_joinbssrpt_parm);
804} 773}
774EXPORT_SYMBOL(rtl92c_set_fw_joinbss_report_cmd);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/fw.h b/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.h
index 3db33bd14666..3db33bd14666 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/fw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/fw_common.h
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/main.c b/drivers/net/wireless/rtlwifi/rtl8192c/main.c
new file mode 100644
index 000000000000..2f624fc27499
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/main.c
@@ -0,0 +1,39 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31
32
33MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
34MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
35MODULE_AUTHOR("Georgia <georgia@realtek.com>");
36MODULE_AUTHOR("Ziv Huang <ziv_huang@realtek.com>");
37MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
38MODULE_LICENSE("GPL");
39MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n PCI wireless");
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
new file mode 100644
index 000000000000..a70228278398
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.c
@@ -0,0 +1,2042 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../rtl8192ce/reg.h"
32#include "../rtl8192ce/def.h"
33#include "dm_common.h"
34#include "phy_common.h"
35
36/* Define macro to shorten lines */
37#define MCS_TXPWR mcs_txpwrlevel_origoffset
38
39u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
40{
41 struct rtl_priv *rtlpriv = rtl_priv(hw);
42 u32 returnvalue, originalvalue, bitshift;
43
44 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
45 "bitmask(%#x)\n", regaddr,
46 bitmask));
47 originalvalue = rtl_read_dword(rtlpriv, regaddr);
48 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
49 returnvalue = (originalvalue & bitmask) >> bitshift;
50
51 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
52 "Addr[0x%x]=0x%x\n", bitmask,
53 regaddr, originalvalue));
54
55 return returnvalue;
56
57}
58EXPORT_SYMBOL(rtl92c_phy_query_bb_reg);
59
60void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
61 u32 regaddr, u32 bitmask, u32 data)
62{
63 struct rtl_priv *rtlpriv = rtl_priv(hw);
64 u32 originalvalue, bitshift;
65
66 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
67 " data(%#x)\n", regaddr, bitmask,
68 data));
69
70 if (bitmask != MASKDWORD) {
71 originalvalue = rtl_read_dword(rtlpriv, regaddr);
72 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
73 data = ((originalvalue & (~bitmask)) | (data << bitshift));
74 }
75
76 rtl_write_dword(rtlpriv, regaddr, data);
77
78 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
79 " data(%#x)\n", regaddr, bitmask,
80 data));
81}
82EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
83
84u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
85 enum radio_path rfpath, u32 offset)
86{
87 RT_ASSERT(false, ("deprecated!\n"));
88 return 0;
89}
90EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_read);
91
92void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
93 enum radio_path rfpath, u32 offset,
94 u32 data)
95{
96 RT_ASSERT(false, ("deprecated!\n"));
97}
98EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_write);
99
100u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
101 enum radio_path rfpath, u32 offset)
102{
103 struct rtl_priv *rtlpriv = rtl_priv(hw);
104 struct rtl_phy *rtlphy = &(rtlpriv->phy);
105 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
106 u32 newoffset;
107 u32 tmplong, tmplong2;
108 u8 rfpi_enable = 0;
109 u32 retvalue;
110
111 offset &= 0x3f;
112 newoffset = offset;
113 if (RT_CANNOT_IO(hw)) {
114 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("return all one\n"));
115 return 0xFFFFFFFF;
116 }
117 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
118 if (rfpath == RF90_PATH_A)
119 tmplong2 = tmplong;
120 else
121 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
122 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
123 (newoffset << 23) | BLSSIREADEDGE;
124 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
125 tmplong & (~BLSSIREADEDGE));
126 mdelay(1);
127 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
128 mdelay(1);
129 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
130 tmplong | BLSSIREADEDGE);
131 mdelay(1);
132 if (rfpath == RF90_PATH_A)
133 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
134 BIT(8));
135 else if (rfpath == RF90_PATH_B)
136 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
137 BIT(8));
138 if (rfpi_enable)
139 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
140 BLSSIREADBACKDATA);
141 else
142 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
143 BLSSIREADBACKDATA);
144 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n",
145 rfpath, pphyreg->rflssi_readback,
146 retvalue));
147 return retvalue;
148}
149EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
150
151void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
152 enum radio_path rfpath, u32 offset,
153 u32 data)
154{
155 u32 data_and_addr;
156 u32 newoffset;
157 struct rtl_priv *rtlpriv = rtl_priv(hw);
158 struct rtl_phy *rtlphy = &(rtlpriv->phy);
159 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
160
161 if (RT_CANNOT_IO(hw)) {
162 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("stop\n"));
163 return;
164 }
165 offset &= 0x3f;
166 newoffset = offset;
167 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
168 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
169 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
170 rfpath, pphyreg->rf3wire_offset,
171 data_and_addr));
172}
173EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
174
175u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
176{
177 u32 i;
178
179 for (i = 0; i <= 31; i++) {
180 if (((bitmask >> i) & 0x1) == 1)
181 break;
182 }
183 return i;
184}
185EXPORT_SYMBOL(_rtl92c_phy_calculate_bit_shift);
186
187static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
188{
189 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
190 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
191 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
192 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
193 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
194 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
195 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
196 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
197 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
198 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
199}
200bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
201{
202 struct rtl_priv *rtlpriv = rtl_priv(hw);
203
204 return rtlpriv->cfg->ops->phy_rf6052_config(hw);
205}
206EXPORT_SYMBOL(rtl92c_phy_rf_config);
207
208bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
209{
210 struct rtl_priv *rtlpriv = rtl_priv(hw);
211 struct rtl_phy *rtlphy = &(rtlpriv->phy);
212 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
213 bool rtstatus;
214
215 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n"));
216 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
217 BASEBAND_CONFIG_PHY_REG);
218 if (rtstatus != true) {
219 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
220 return false;
221 }
222 if (rtlphy->rf_type == RF_1T2R) {
223 _rtl92c_phy_bb_config_1t(hw);
224 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n"));
225 }
226 if (rtlefuse->autoload_failflag == false) {
227 rtlphy->pwrgroup_cnt = 0;
228 rtstatus = rtlpriv->cfg->ops->config_bb_with_pgheaderfile(hw,
229 BASEBAND_CONFIG_PHY_REG);
230 }
231 if (rtstatus != true) {
232 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
233 return false;
234 }
235 rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
236 BASEBAND_CONFIG_AGC_TAB);
237 if (rtstatus != true) {
238 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
239 return false;
240 }
241 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
242 RFPGA0_XA_HSSIPARAMETER2,
243 0x200));
244 return true;
245}
246EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);
247
248void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
249 u32 regaddr, u32 bitmask,
250 u32 data)
251{
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 struct rtl_phy *rtlphy = &(rtlpriv->phy);
254
255 if (regaddr == RTXAGC_A_RATE18_06) {
256 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0] = data;
257 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
258 ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
259 rtlphy->pwrgroup_cnt,
260 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][0]));
261 }
262 if (regaddr == RTXAGC_A_RATE54_24) {
263 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1] = data;
264 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
265 ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
266 rtlphy->pwrgroup_cnt,
267 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][1]));
268 }
269 if (regaddr == RTXAGC_A_CCK1_MCS32) {
270 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6] = data;
271 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
272 ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
273 rtlphy->pwrgroup_cnt,
274 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][6]));
275 }
276 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
277 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7] = data;
278 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
279 ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
280 rtlphy->pwrgroup_cnt,
281 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][7]));
282 }
283 if (regaddr == RTXAGC_A_MCS03_MCS00) {
284 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2] = data;
285 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
286 ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
287 rtlphy->pwrgroup_cnt,
288 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][2]));
289 }
290 if (regaddr == RTXAGC_A_MCS07_MCS04) {
291 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3] = data;
292 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
293 ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
294 rtlphy->pwrgroup_cnt,
295 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][3]));
296 }
297 if (regaddr == RTXAGC_A_MCS11_MCS08) {
298 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4] = data;
299 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
300 ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
301 rtlphy->pwrgroup_cnt,
302 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][4]));
303 }
304 if (regaddr == RTXAGC_A_MCS15_MCS12) {
305 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5] = data;
306 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
307 ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
308 rtlphy->pwrgroup_cnt,
309 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][5]));
310 }
311 if (regaddr == RTXAGC_B_RATE18_06) {
312 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8] = data;
313 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
314 ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
315 rtlphy->pwrgroup_cnt,
316 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][8]));
317 }
318 if (regaddr == RTXAGC_B_RATE54_24) {
319 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9] = data;
320
321 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
322 ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
323 rtlphy->pwrgroup_cnt,
324 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][9]));
325 }
326
327 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
328 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14] = data;
329
330 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
331 ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
332 rtlphy->pwrgroup_cnt,
333 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][14]));
334 }
335
336 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
337 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15] = data;
338
339 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
340 ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
341 rtlphy->pwrgroup_cnt,
342 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][15]));
343 }
344
345 if (regaddr == RTXAGC_B_MCS03_MCS00) {
346 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10] = data;
347
348 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
349 ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
350 rtlphy->pwrgroup_cnt,
351 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][10]));
352 }
353
354 if (regaddr == RTXAGC_B_MCS07_MCS04) {
355 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11] = data;
356
357 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
358 ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
359 rtlphy->pwrgroup_cnt,
360 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][11]));
361 }
362
363 if (regaddr == RTXAGC_B_MCS11_MCS08) {
364 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12] = data;
365
366 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
367 ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
368 rtlphy->pwrgroup_cnt,
369 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][12]));
370 }
371
372 if (regaddr == RTXAGC_B_MCS15_MCS12) {
373 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13] = data;
374
375 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
376 ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
377 rtlphy->pwrgroup_cnt,
378 rtlphy->MCS_TXPWR[rtlphy->pwrgroup_cnt][13]));
379
380 rtlphy->pwrgroup_cnt++;
381 }
382}
383EXPORT_SYMBOL(_rtl92c_store_pwrIndex_diffrate_offset);
384
385void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
386{
387 struct rtl_priv *rtlpriv = rtl_priv(hw);
388 struct rtl_phy *rtlphy = &(rtlpriv->phy);
389
390 rtlphy->default_initialgain[0] =
391 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
392 rtlphy->default_initialgain[1] =
393 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
394 rtlphy->default_initialgain[2] =
395 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
396 rtlphy->default_initialgain[3] =
397 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
398
399 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
400 ("Default initial gain (c50=0x%x, "
401 "c58=0x%x, c60=0x%x, c68=0x%x\n",
402 rtlphy->default_initialgain[0],
403 rtlphy->default_initialgain[1],
404 rtlphy->default_initialgain[2],
405 rtlphy->default_initialgain[3]));
406
407 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
408 ROFDM0_RXDETECTOR3, MASKBYTE0);
409 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
410 ROFDM0_RXDETECTOR2, MASKDWORD);
411
412 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
413 ("Default framesync (0x%x) = 0x%x\n",
414 ROFDM0_RXDETECTOR3, rtlphy->framesync));
415}
416
417void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
418{
419 struct rtl_priv *rtlpriv = rtl_priv(hw);
420 struct rtl_phy *rtlphy = &(rtlpriv->phy);
421
422 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
423 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
424 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
425 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
426
427 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
428 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
429 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
430 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
431
432 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
433 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
434
435 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
436 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
437
438 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
439 RFPGA0_XA_LSSIPARAMETER;
440 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
441 RFPGA0_XB_LSSIPARAMETER;
442
443 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
444 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
445 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
446 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
447
448 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
449 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
450 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
451 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
452
453 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
454 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
455
456 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
457 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
458
459 rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
460 RFPGA0_XAB_SWITCHCONTROL;
461 rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
462 RFPGA0_XAB_SWITCHCONTROL;
463 rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
464 RFPGA0_XCD_SWITCHCONTROL;
465 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
466 RFPGA0_XCD_SWITCHCONTROL;
467
468 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
469 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
470 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
471 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
472
473 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
474 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
475 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
476 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
477
478 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
479 ROFDM0_XARXIQIMBALANCE;
480 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
481 ROFDM0_XBRXIQIMBALANCE;
482 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
483 ROFDM0_XCRXIQIMBANLANCE;
484 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
485 ROFDM0_XDRXIQIMBALANCE;
486
487 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
488 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
489 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
490 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
491
492 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
493 ROFDM0_XATXIQIMBALANCE;
494 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
495 ROFDM0_XBTXIQIMBALANCE;
496 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
497 ROFDM0_XCTXIQIMBALANCE;
498 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
499 ROFDM0_XDTXIQIMBALANCE;
500
501 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
502 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
503 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
504 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
505
506 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
507 RFPGA0_XA_LSSIREADBACK;
508 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
509 RFPGA0_XB_LSSIREADBACK;
510 rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
511 RFPGA0_XC_LSSIREADBACK;
512 rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
513 RFPGA0_XD_LSSIREADBACK;
514
515 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
516 TRANSCEIVEA_HSPI_READBACK;
517 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
518 TRANSCEIVEB_HSPI_READBACK;
519
520}
521EXPORT_SYMBOL(_rtl92c_phy_init_bb_rf_register_definition);
522
523void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
524{
525 struct rtl_priv *rtlpriv = rtl_priv(hw);
526 struct rtl_phy *rtlphy = &(rtlpriv->phy);
527 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
528 u8 txpwr_level;
529 long txpwr_dbm;
530
531 txpwr_level = rtlphy->cur_cck_txpwridx;
532 txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw,
533 WIRELESS_MODE_B, txpwr_level);
534 txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
535 rtlefuse->legacy_ht_txpowerdiff;
536 if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
537 WIRELESS_MODE_G,
538 txpwr_level) > txpwr_dbm)
539 txpwr_dbm =
540 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
541 txpwr_level);
542 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
543 if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
544 WIRELESS_MODE_N_24G,
545 txpwr_level) > txpwr_dbm)
546 txpwr_dbm =
547 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
548 txpwr_level);
549 *powerlevel = txpwr_dbm;
550}
551
552static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
553 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
554{
555 struct rtl_priv *rtlpriv = rtl_priv(hw);
556 struct rtl_phy *rtlphy = &(rtlpriv->phy);
557 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
558 u8 index = (channel - 1);
559
560 cckpowerlevel[RF90_PATH_A] =
561 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
562 cckpowerlevel[RF90_PATH_B] =
563 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
564 if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
565 ofdmpowerlevel[RF90_PATH_A] =
566 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
567 ofdmpowerlevel[RF90_PATH_B] =
568 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
569 } else if (get_rf_type(rtlphy) == RF_2T2R) {
570 ofdmpowerlevel[RF90_PATH_A] =
571 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
572 ofdmpowerlevel[RF90_PATH_B] =
573 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
574 }
575}
576
577static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
578 u8 channel, u8 *cckpowerlevel,
579 u8 *ofdmpowerlevel)
580{
581 struct rtl_priv *rtlpriv = rtl_priv(hw);
582 struct rtl_phy *rtlphy = &(rtlpriv->phy);
583
584 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
585 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
586}
587
588void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
589{
590 struct rtl_priv *rtlpriv = rtl_priv(hw);
591 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
592 u8 cckpowerlevel[2], ofdmpowerlevel[2];
593
594 if (rtlefuse->txpwr_fromeprom == false)
595 return;
596 _rtl92c_get_txpower_index(hw, channel,
597 &cckpowerlevel[0], &ofdmpowerlevel[0]);
598 _rtl92c_ccxpower_index_check(hw,
599 channel, &cckpowerlevel[0],
600 &ofdmpowerlevel[0]);
601 rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
602 rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
603 channel);
604}
605EXPORT_SYMBOL(rtl92c_phy_set_txpower_level);
606
607bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
608{
609 struct rtl_priv *rtlpriv = rtl_priv(hw);
610 struct rtl_phy *rtlphy = &(rtlpriv->phy);
611 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
612 u8 idx;
613 u8 rf_path;
614
615 u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
616 WIRELESS_MODE_B,
617 power_indbm);
618 u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
619 WIRELESS_MODE_N_24G,
620 power_indbm);
621 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
622 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
623 else
624 ofdmtxpwridx = 0;
625 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
626 ("%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
627 power_indbm, ccktxpwridx, ofdmtxpwridx));
628 for (idx = 0; idx < 14; idx++) {
629 for (rf_path = 0; rf_path < 2; rf_path++) {
630 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
631 rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
632 ofdmtxpwridx;
633 rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
634 ofdmtxpwridx;
635 }
636 }
637 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
638 return true;
639}
640EXPORT_SYMBOL(rtl92c_phy_update_txpower_dbm);
641
642void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw, u16 beaconinterval)
643{
644}
645EXPORT_SYMBOL(rtl92c_phy_set_beacon_hw_reg);
646
647u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
648 enum wireless_mode wirelessmode,
649 long power_indbm)
650{
651 u8 txpwridx;
652 long offset;
653
654 switch (wirelessmode) {
655 case WIRELESS_MODE_B:
656 offset = -7;
657 break;
658 case WIRELESS_MODE_G:
659 case WIRELESS_MODE_N_24G:
660 offset = -8;
661 break;
662 default:
663 offset = -8;
664 break;
665 }
666
667 if ((power_indbm - offset) > 0)
668 txpwridx = (u8) ((power_indbm - offset) * 2);
669 else
670 txpwridx = 0;
671
672 if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
673 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
674
675 return txpwridx;
676}
677EXPORT_SYMBOL(_rtl92c_phy_dbm_to_txpwr_Idx);
678
679long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
680 enum wireless_mode wirelessmode,
681 u8 txpwridx)
682{
683 long offset;
684 long pwrout_dbm;
685
686 switch (wirelessmode) {
687 case WIRELESS_MODE_B:
688 offset = -7;
689 break;
690 case WIRELESS_MODE_G:
691 case WIRELESS_MODE_N_24G:
692 offset = -8;
693 break;
694 default:
695 offset = -8;
696 break;
697 }
698 pwrout_dbm = txpwridx / 2 + offset;
699 return pwrout_dbm;
700}
701EXPORT_SYMBOL(_rtl92c_phy_txpwr_idx_to_dbm);
702
703void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
704{
705 struct rtl_priv *rtlpriv = rtl_priv(hw);
706 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
707 enum io_type iotype;
708
709 if (!is_hal_stop(rtlhal)) {
710 switch (operation) {
711 case SCAN_OPT_BACKUP:
712 iotype = IO_CMD_PAUSE_DM_BY_SCAN;
713 rtlpriv->cfg->ops->set_hw_reg(hw,
714 HW_VAR_IO_CMD,
715 (u8 *)&iotype);
716
717 break;
718 case SCAN_OPT_RESTORE:
719 iotype = IO_CMD_RESUME_DM_BY_SCAN;
720 rtlpriv->cfg->ops->set_hw_reg(hw,
721 HW_VAR_IO_CMD,
722 (u8 *)&iotype);
723 break;
724 default:
725 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
726 ("Unknown Scan Backup operation.\n"));
727 break;
728 }
729 }
730}
731EXPORT_SYMBOL(rtl92c_phy_scan_operation_backup);
732
733void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
734 enum nl80211_channel_type ch_type)
735{
736 struct rtl_priv *rtlpriv = rtl_priv(hw);
737 struct rtl_phy *rtlphy = &(rtlpriv->phy);
738 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
739 u8 tmp_bw = rtlphy->current_chan_bw;
740
741 if (rtlphy->set_bwmode_inprogress)
742 return;
743 rtlphy->set_bwmode_inprogress = true;
744 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw)))
745 rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw);
746 else {
747 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
748 ("FALSE driver sleep or unload\n"));
749 rtlphy->set_bwmode_inprogress = false;
750 rtlphy->current_chan_bw = tmp_bw;
751 }
752}
753EXPORT_SYMBOL(rtl92c_phy_set_bw_mode);
754
755void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
756{
757 struct rtl_priv *rtlpriv = rtl_priv(hw);
758 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
759 struct rtl_phy *rtlphy = &(rtlpriv->phy);
760 u32 delay;
761
762 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
763 ("switch to channel%d\n", rtlphy->current_channel));
764 if (is_hal_stop(rtlhal))
765 return;
766 do {
767 if (!rtlphy->sw_chnl_inprogress)
768 break;
769 if (!_rtl92c_phy_sw_chnl_step_by_step
770 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
771 &rtlphy->sw_chnl_step, &delay)) {
772 if (delay > 0)
773 mdelay(delay);
774 else
775 continue;
776 } else
777 rtlphy->sw_chnl_inprogress = false;
778 break;
779 } while (true);
780 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
781}
782EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
783
784u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
785{
786 struct rtl_priv *rtlpriv = rtl_priv(hw);
787 struct rtl_phy *rtlphy = &(rtlpriv->phy);
788 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
789
790 if (rtlphy->sw_chnl_inprogress)
791 return 0;
792 if (rtlphy->set_bwmode_inprogress)
793 return 0;
794 RT_ASSERT((rtlphy->current_channel <= 14),
795 ("WIRELESS_MODE_G but channel>14"));
796 rtlphy->sw_chnl_inprogress = true;
797 rtlphy->sw_chnl_stage = 0;
798 rtlphy->sw_chnl_step = 0;
799 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
800 rtl92c_phy_sw_chnl_callback(hw);
801 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
802 ("sw_chnl_inprogress false schdule workitem\n"));
803 rtlphy->sw_chnl_inprogress = false;
804 } else {
805 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
806 ("sw_chnl_inprogress false driver sleep or"
807 " unload\n"));
808 rtlphy->sw_chnl_inprogress = false;
809 }
810 return 1;
811}
812EXPORT_SYMBOL(rtl92c_phy_sw_chnl);
813
814static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
815 u8 channel, u8 *stage, u8 *step,
816 u32 *delay)
817{
818 struct rtl_priv *rtlpriv = rtl_priv(hw);
819 struct rtl_phy *rtlphy = &(rtlpriv->phy);
820 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
821 u32 precommoncmdcnt;
822 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
823 u32 postcommoncmdcnt;
824 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
825 u32 rfdependcmdcnt;
826 struct swchnlcmd *currentcmd = NULL;
827 u8 rfpath;
828 u8 num_total_rfpath = rtlphy->num_total_rfpath;
829
830 precommoncmdcnt = 0;
831 _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
832 MAX_PRECMD_CNT,
833 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
834 _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
835 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
836
837 postcommoncmdcnt = 0;
838
839 _rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
840 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
841
842 rfdependcmdcnt = 0;
843
844 RT_ASSERT((channel >= 1 && channel <= 14),
845 ("illegal channel for Zebra: %d\n", channel));
846
847 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
848 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
849 RF_CHNLBW, channel, 10);
850
851 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
852 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
853 0);
854
855 do {
856 switch (*stage) {
857 case 0:
858 currentcmd = &precommoncmd[*step];
859 break;
860 case 1:
861 currentcmd = &rfdependcmd[*step];
862 break;
863 case 2:
864 currentcmd = &postcommoncmd[*step];
865 break;
866 }
867
868 if (currentcmd->cmdid == CMDID_END) {
869 if ((*stage) == 2) {
870 return true;
871 } else {
872 (*stage)++;
873 (*step) = 0;
874 continue;
875 }
876 }
877
878 switch (currentcmd->cmdid) {
879 case CMDID_SET_TXPOWEROWER_LEVEL:
880 rtl92c_phy_set_txpower_level(hw, channel);
881 break;
882 case CMDID_WRITEPORT_ULONG:
883 rtl_write_dword(rtlpriv, currentcmd->para1,
884 currentcmd->para2);
885 break;
886 case CMDID_WRITEPORT_USHORT:
887 rtl_write_word(rtlpriv, currentcmd->para1,
888 (u16) currentcmd->para2);
889 break;
890 case CMDID_WRITEPORT_UCHAR:
891 rtl_write_byte(rtlpriv, currentcmd->para1,
892 (u8) currentcmd->para2);
893 break;
894 case CMDID_RF_WRITEREG:
895 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
896 rtlphy->rfreg_chnlval[rfpath] =
897 ((rtlphy->rfreg_chnlval[rfpath] &
898 0xfffffc00) | currentcmd->para2);
899
900 rtl_set_rfreg(hw, (enum radio_path)rfpath,
901 currentcmd->para1,
902 RFREG_OFFSET_MASK,
903 rtlphy->rfreg_chnlval[rfpath]);
904 }
905 break;
906 default:
907 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
908 ("switch case not process\n"));
909 break;
910 }
911
912 break;
913 } while (true);
914
915 (*delay) = currentcmd->msdelay;
916 (*step)++;
917 return false;
918}
919
920static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
921 u32 cmdtableidx, u32 cmdtablesz,
922 enum swchnlcmd_id cmdid,
923 u32 para1, u32 para2, u32 msdelay)
924{
925 struct swchnlcmd *pcmd;
926
927 if (cmdtable == NULL) {
928 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
929 return false;
930 }
931
932 if (cmdtableidx >= cmdtablesz)
933 return false;
934
935 pcmd = cmdtable + cmdtableidx;
936 pcmd->cmdid = cmdid;
937 pcmd->para1 = para1;
938 pcmd->para2 = para2;
939 pcmd->msdelay = msdelay;
940 return true;
941}
942
943bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
944{
945 return true;
946}
947EXPORT_SYMBOL(rtl8192_phy_check_is_legal_rfpath);
948
949static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
950{
951 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
952 u8 result = 0x00;
953
954 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
955 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
956 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
957 rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
958 config_pathb ? 0x28160202 : 0x28160502);
959
960 if (config_pathb) {
961 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
962 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
963 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
964 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
965 }
966
967 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
968 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
969 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
970
971 mdelay(IQK_DELAY_TIME);
972
973 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
974 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
975 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
976 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
977
978 if (!(reg_eac & BIT(28)) &&
979 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
980 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
981 result |= 0x01;
982 else
983 return result;
984
985 if (!(reg_eac & BIT(27)) &&
986 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
987 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
988 result |= 0x02;
989 return result;
990}
991
992static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
993{
994 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
995 u8 result = 0x00;
996
997 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
998 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
999 mdelay(IQK_DELAY_TIME);
1000 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1001 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1002 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1003 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1004 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1005 if (!(reg_eac & BIT(31)) &&
1006 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1007 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1008 result |= 0x01;
1009 else
1010 return result;
1011
1012 if (!(reg_eac & BIT(30)) &&
1013 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1014 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1015 result |= 0x02;
1016 return result;
1017}
1018
1019static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
1020 bool iqk_ok, long result[][8],
1021 u8 final_candidate, bool btxonly)
1022{
1023 u32 oldval_0, x, tx0_a, reg;
1024 long y, tx0_c;
1025
1026 if (final_candidate == 0xFF)
1027 return;
1028 else if (iqk_ok) {
1029 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1030 MASKDWORD) >> 22) & 0x3FF;
1031 x = result[final_candidate][0];
1032 if ((x & 0x00000200) != 0)
1033 x = x | 0xFFFFFC00;
1034 tx0_a = (x * oldval_0) >> 8;
1035 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1036 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1037 ((x * oldval_0 >> 7) & 0x1));
1038 y = result[final_candidate][1];
1039 if ((y & 0x00000200) != 0)
1040 y = y | 0xFFFFFC00;
1041 tx0_c = (y * oldval_0) >> 8;
1042 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1043 ((tx0_c & 0x3C0) >> 6));
1044 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1045 (tx0_c & 0x3F));
1046 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1047 ((y * oldval_0 >> 7) & 0x1));
1048 if (btxonly)
1049 return;
1050 reg = result[final_candidate][2];
1051 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1052 reg = result[final_candidate][3] & 0x3F;
1053 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1054 reg = (result[final_candidate][3] >> 6) & 0xF;
1055 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1056 }
1057}
1058
1059static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1060 bool iqk_ok, long result[][8],
1061 u8 final_candidate, bool btxonly)
1062{
1063 u32 oldval_1, x, tx1_a, reg;
1064 long y, tx1_c;
1065
1066 if (final_candidate == 0xFF)
1067 return;
1068 else if (iqk_ok) {
1069 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1070 MASKDWORD) >> 22) & 0x3FF;
1071 x = result[final_candidate][4];
1072 if ((x & 0x00000200) != 0)
1073 x = x | 0xFFFFFC00;
1074 tx1_a = (x * oldval_1) >> 8;
1075 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1076 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1077 ((x * oldval_1 >> 7) & 0x1));
1078 y = result[final_candidate][5];
1079 if ((y & 0x00000200) != 0)
1080 y = y | 0xFFFFFC00;
1081 tx1_c = (y * oldval_1) >> 8;
1082 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1083 ((tx1_c & 0x3C0) >> 6));
1084 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1085 (tx1_c & 0x3F));
1086 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1087 ((y * oldval_1 >> 7) & 0x1));
1088 if (btxonly)
1089 return;
1090 reg = result[final_candidate][6];
1091 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1092 reg = result[final_candidate][7] & 0x3F;
1093 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1094 reg = (result[final_candidate][7] >> 6) & 0xF;
1095 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1096 }
1097}
1098
1099static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
1100 u32 *addareg, u32 *addabackup,
1101 u32 registernum)
1102{
1103 u32 i;
1104
1105 for (i = 0; i < registernum; i++)
1106 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1107}
1108
1109static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
1110 u32 *macreg, u32 *macbackup)
1111{
1112 struct rtl_priv *rtlpriv = rtl_priv(hw);
1113 u32 i;
1114
1115 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1116 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1117 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1118}
1119
1120static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1121 u32 *addareg, u32 *addabackup,
1122 u32 regiesternum)
1123{
1124 u32 i;
1125
1126 for (i = 0; i < regiesternum; i++)
1127 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1128}
1129
1130static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1131 u32 *macreg, u32 *macbackup)
1132{
1133 struct rtl_priv *rtlpriv = rtl_priv(hw);
1134 u32 i;
1135
1136 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1137 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1138 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1139}
1140
1141static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1142 u32 *addareg, bool is_patha_on, bool is2t)
1143{
1144 u32 pathOn;
1145 u32 i;
1146
1147 pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1148 if (false == is2t) {
1149 pathOn = 0x0bdb25a0;
1150 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1151 } else {
1152 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1153 }
1154
1155 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1156 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1157}
1158
1159static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1160 u32 *macreg, u32 *macbackup)
1161{
1162 struct rtl_priv *rtlpriv = rtl_priv(hw);
1163 u32 i;
1164
1165 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1166
1167 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1168 rtl_write_byte(rtlpriv, macreg[i],
1169 (u8) (macbackup[i] & (~BIT(3))));
1170 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1171}
1172
1173static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1174{
1175 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1176 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1177 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1178}
1179
1180static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1181{
1182 u32 mode;
1183
1184 mode = pi_mode ? 0x01000100 : 0x01000000;
1185 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1186 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1187}
1188
1189static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1190 long result[][8], u8 c1, u8 c2)
1191{
1192 u32 i, j, diff, simularity_bitmap, bound;
1193 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1194
1195 u8 final_candidate[2] = { 0xFF, 0xFF };
1196 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1197
1198 if (is2t)
1199 bound = 8;
1200 else
1201 bound = 4;
1202
1203 simularity_bitmap = 0;
1204
1205 for (i = 0; i < bound; i++) {
1206 diff = (result[c1][i] > result[c2][i]) ?
1207 (result[c1][i] - result[c2][i]) :
1208 (result[c2][i] - result[c1][i]);
1209
1210 if (diff > MAX_TOLERANCE) {
1211 if ((i == 2 || i == 6) && !simularity_bitmap) {
1212 if (result[c1][i] + result[c1][i + 1] == 0)
1213 final_candidate[(i / 4)] = c2;
1214 else if (result[c2][i] + result[c2][i + 1] == 0)
1215 final_candidate[(i / 4)] = c1;
1216 else
1217 simularity_bitmap = simularity_bitmap |
1218 (1 << i);
1219 } else
1220 simularity_bitmap =
1221 simularity_bitmap | (1 << i);
1222 }
1223 }
1224
1225 if (simularity_bitmap == 0) {
1226 for (i = 0; i < (bound / 4); i++) {
1227 if (final_candidate[i] != 0xFF) {
1228 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1229 result[3][j] =
1230 result[final_candidate[i]][j];
1231 bresult = false;
1232 }
1233 }
1234 return bresult;
1235 } else if (!(simularity_bitmap & 0x0F)) {
1236 for (i = 0; i < 4; i++)
1237 result[3][i] = result[c1][i];
1238 return false;
1239 } else if (!(simularity_bitmap & 0xF0) && is2t) {
1240 for (i = 4; i < 8; i++)
1241 result[3][i] = result[c1][i];
1242 return false;
1243 } else {
1244 return false;
1245 }
1246
1247}
1248
1249static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1250 long result[][8], u8 t, bool is2t)
1251{
1252 struct rtl_priv *rtlpriv = rtl_priv(hw);
1253 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1254 u32 i;
1255 u8 patha_ok, pathb_ok;
1256 u32 adda_reg[IQK_ADDA_REG_NUM] = {
1257 0x85c, 0xe6c, 0xe70, 0xe74,
1258 0xe78, 0xe7c, 0xe80, 0xe84,
1259 0xe88, 0xe8c, 0xed0, 0xed4,
1260 0xed8, 0xedc, 0xee0, 0xeec
1261 };
1262
1263 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1264 0x522, 0x550, 0x551, 0x040
1265 };
1266
1267 const u32 retrycount = 2;
1268
1269 u32 bbvalue;
1270
1271 if (t == 0) {
1272 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1273
1274 _rtl92c_phy_save_adda_registers(hw, adda_reg,
1275 rtlphy->adda_backup, 16);
1276 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1277 rtlphy->iqk_mac_backup);
1278 }
1279 _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1280 if (t == 0) {
1281 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1282 RFPGA0_XA_HSSIPARAMETER1,
1283 BIT(8));
1284 }
1285 if (!rtlphy->rfpi_enable)
1286 _rtl92c_phy_pi_mode_switch(hw, true);
1287 if (t == 0) {
1288 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1289 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1290 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1291 }
1292 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1293 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1294 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1295 if (is2t) {
1296 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1297 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1298 }
1299 _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1300 rtlphy->iqk_mac_backup);
1301 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1302 if (is2t)
1303 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1304 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1305 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1306 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1307 for (i = 0; i < retrycount; i++) {
1308 patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1309 if (patha_ok == 0x03) {
1310 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1311 0x3FF0000) >> 16;
1312 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1313 0x3FF0000) >> 16;
1314 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1315 0x3FF0000) >> 16;
1316 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1317 0x3FF0000) >> 16;
1318 break;
1319 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1320 result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1321 MASKDWORD) & 0x3FF0000) >>
1322 16;
1323 result[t][1] =
1324 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1325
1326 }
1327
1328 if (is2t) {
1329 _rtl92c_phy_path_a_standby(hw);
1330 _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1331 for (i = 0; i < retrycount; i++) {
1332 pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1333 if (pathb_ok == 0x03) {
1334 result[t][4] = (rtl_get_bbreg(hw,
1335 0xeb4,
1336 MASKDWORD) &
1337 0x3FF0000) >> 16;
1338 result[t][5] =
1339 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1340 0x3FF0000) >> 16;
1341 result[t][6] =
1342 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1343 0x3FF0000) >> 16;
1344 result[t][7] =
1345 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1346 0x3FF0000) >> 16;
1347 break;
1348 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1349 result[t][4] = (rtl_get_bbreg(hw,
1350 0xeb4,
1351 MASKDWORD) &
1352 0x3FF0000) >> 16;
1353 }
1354 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1355 0x3FF0000) >> 16;
1356 }
1357 }
1358 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1359 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1360 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1361 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1362 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1363 if (is2t)
1364 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1365 if (t != 0) {
1366 if (!rtlphy->rfpi_enable)
1367 _rtl92c_phy_pi_mode_switch(hw, false);
1368 _rtl92c_phy_reload_adda_registers(hw, adda_reg,
1369 rtlphy->adda_backup, 16);
1370 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1371 rtlphy->iqk_mac_backup);
1372 }
1373}
1374
1375static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1376 char delta, bool is2t)
1377{
1378 /* This routine is deliberately dummied out for later fixes */
1379#if 0
1380 struct rtl_priv *rtlpriv = rtl_priv(hw);
1381 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1382 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1383
1384 u32 reg_d[PATH_NUM];
1385 u32 tmpreg, index, offset, path, i, pathbound = PATH_NUM, apkbound;
1386
1387 u32 bb_backup[APK_BB_REG_NUM];
1388 u32 bb_reg[APK_BB_REG_NUM] = {
1389 0x904, 0xc04, 0x800, 0xc08, 0x874
1390 };
1391 u32 bb_ap_mode[APK_BB_REG_NUM] = {
1392 0x00000020, 0x00a05430, 0x02040000,
1393 0x000800e4, 0x00204000
1394 };
1395 u32 bb_normal_ap_mode[APK_BB_REG_NUM] = {
1396 0x00000020, 0x00a05430, 0x02040000,
1397 0x000800e4, 0x22204000
1398 };
1399
1400 u32 afe_backup[APK_AFE_REG_NUM];
1401 u32 afe_reg[APK_AFE_REG_NUM] = {
1402 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78,
1403 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
1404 0xed0, 0xed4, 0xed8, 0xedc, 0xee0,
1405 0xeec
1406 };
1407
1408 u32 mac_backup[IQK_MAC_REG_NUM];
1409 u32 mac_reg[IQK_MAC_REG_NUM] = {
1410 0x522, 0x550, 0x551, 0x040
1411 };
1412
1413 u32 apk_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1414 {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
1415 {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
1416 };
1417
1418 u32 apk_normal_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1419 {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},
1420 {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
1421 };
1422
1423 u32 apk_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1424 {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
1425 {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
1426 };
1427
1428 u32 apk_normal_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1429 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},
1430 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
1431 };
1432
1433 u32 afe_on_off[PATH_NUM] = {
1434 0x04db25a4, 0x0b1b25a4
1435 };
1436
1437 u32 apk_offset[PATH_NUM] = { 0xb68, 0xb6c };
1438
1439 u32 apk_normal_offset[PATH_NUM] = { 0xb28, 0xb98 };
1440
1441 u32 apk_value[PATH_NUM] = { 0x92fc0000, 0x12fc0000 };
1442
1443 u32 apk_normal_value[PATH_NUM] = { 0x92680000, 0x12680000 };
1444
1445 const char apk_delta_mapping[APK_BB_REG_NUM][13] = {
1446 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1447 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1448 {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1449 {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1450 {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
1451 };
1452
1453 const u32 apk_normal_setting_value_1[13] = {
1454 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
1455 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
1456 0x12680000, 0x00880000, 0x00880000
1457 };
1458
1459 const u32 apk_normal_setting_value_2[16] = {
1460 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
1461 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
1462 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
1463 0x00050006
1464 };
1465
1466 const u32 apk_result[PATH_NUM][APK_BB_REG_NUM];
1467
1468 long bb_offset, delta_v, delta_offset;
1469
1470 if (!is2t)
1471 pathbound = 1;
1472
1473 for (index = 0; index < PATH_NUM; index++) {
1474 apk_offset[index] = apk_normal_offset[index];
1475 apk_value[index] = apk_normal_value[index];
1476 afe_on_off[index] = 0x6fdb25a4;
1477 }
1478
1479 for (index = 0; index < APK_BB_REG_NUM; index++) {
1480 for (path = 0; path < pathbound; path++) {
1481 apk_rf_init_value[path][index] =
1482 apk_normal_rf_init_value[path][index];
1483 apk_rf_value_0[path][index] =
1484 apk_normal_rf_value_0[path][index];
1485 }
1486 bb_ap_mode[index] = bb_normal_ap_mode[index];
1487
1488 apkbound = 6;
1489 }
1490
1491 for (index = 0; index < APK_BB_REG_NUM; index++) {
1492 if (index == 0)
1493 continue;
1494 bb_backup[index] = rtl_get_bbreg(hw, bb_reg[index], MASKDWORD);
1495 }
1496
1497 _rtl92c_phy_save_mac_registers(hw, mac_reg, mac_backup);
1498
1499 _rtl92c_phy_save_adda_registers(hw, afe_reg, afe_backup, 16);
1500
1501 for (path = 0; path < pathbound; path++) {
1502 if (path == RF90_PATH_A) {
1503 offset = 0xb00;
1504 for (index = 0; index < 11; index++) {
1505 rtl_set_bbreg(hw, offset, MASKDWORD,
1506 apk_normal_setting_value_1
1507 [index]);
1508
1509 offset += 0x04;
1510 }
1511
1512 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1513
1514 offset = 0xb68;
1515 for (; index < 13; index++) {
1516 rtl_set_bbreg(hw, offset, MASKDWORD,
1517 apk_normal_setting_value_1
1518 [index]);
1519
1520 offset += 0x04;
1521 }
1522
1523 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1524
1525 offset = 0xb00;
1526 for (index = 0; index < 16; index++) {
1527 rtl_set_bbreg(hw, offset, MASKDWORD,
1528 apk_normal_setting_value_2
1529 [index]);
1530
1531 offset += 0x04;
1532 }
1533 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1534 } else if (path == RF90_PATH_B) {
1535 offset = 0xb70;
1536 for (index = 0; index < 10; index++) {
1537 rtl_set_bbreg(hw, offset, MASKDWORD,
1538 apk_normal_setting_value_1
1539 [index]);
1540
1541 offset += 0x04;
1542 }
1543 rtl_set_bbreg(hw, 0xb28, MASKDWORD, 0x12680000);
1544 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
1545
1546 offset = 0xb68;
1547 index = 11;
1548 for (; index < 13; index++) {
1549 rtl_set_bbreg(hw, offset, MASKDWORD,
1550 apk_normal_setting_value_1
1551 [index]);
1552
1553 offset += 0x04;
1554 }
1555
1556 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
1557
1558 offset = 0xb60;
1559 for (index = 0; index < 16; index++) {
1560 rtl_set_bbreg(hw, offset, MASKDWORD,
1561 apk_normal_setting_value_2
1562 [index]);
1563
1564 offset += 0x04;
1565 }
1566 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1567 }
1568
1569 reg_d[path] = rtl_get_rfreg(hw, (enum radio_path)path,
1570 0xd, MASKDWORD);
1571
1572 for (index = 0; index < APK_AFE_REG_NUM; index++)
1573 rtl_set_bbreg(hw, afe_reg[index], MASKDWORD,
1574 afe_on_off[path]);
1575
1576 if (path == RF90_PATH_A) {
1577 for (index = 0; index < APK_BB_REG_NUM; index++) {
1578 if (index == 0)
1579 continue;
1580 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD,
1581 bb_ap_mode[index]);
1582 }
1583 }
1584
1585 _rtl92c_phy_mac_setting_calibration(hw, mac_reg, mac_backup);
1586
1587 if (path == 0) {
1588 rtl_set_rfreg(hw, RF90_PATH_B, 0x0, MASKDWORD, 0x10000);
1589 } else {
1590 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASKDWORD,
1591 0x10000);
1592 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1593 0x1000f);
1594 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1595 0x20103);
1596 }
1597
1598 delta_offset = ((delta + 14) / 2);
1599 if (delta_offset < 0)
1600 delta_offset = 0;
1601 else if (delta_offset > 12)
1602 delta_offset = 12;
1603
1604 for (index = 0; index < APK_BB_REG_NUM; index++) {
1605 if (index != 1)
1606 continue;
1607
1608 tmpreg = apk_rf_init_value[path][index];
1609
1610 if (!rtlefuse->apk_thermalmeterignore) {
1611 bb_offset = (tmpreg & 0xF0000) >> 16;
1612
1613 if (!(tmpreg & BIT(15)))
1614 bb_offset = -bb_offset;
1615
1616 delta_v =
1617 apk_delta_mapping[index][delta_offset];
1618
1619 bb_offset += delta_v;
1620
1621 if (bb_offset < 0) {
1622 tmpreg = tmpreg & (~BIT(15));
1623 bb_offset = -bb_offset;
1624 } else {
1625 tmpreg = tmpreg | BIT(15);
1626 }
1627
1628 tmpreg =
1629 (tmpreg & 0xFFF0FFFF) | (bb_offset << 16);
1630 }
1631
1632 rtl_set_rfreg(hw, (enum radio_path)path, 0xc,
1633 MASKDWORD, 0x8992e);
1634 rtl_set_rfreg(hw, (enum radio_path)path, 0x0,
1635 MASKDWORD, apk_rf_value_0[path][index]);
1636 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1637 MASKDWORD, tmpreg);
1638
1639 i = 0;
1640 do {
1641 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80000000);
1642 rtl_set_bbreg(hw, apk_offset[path],
1643 MASKDWORD, apk_value[0]);
1644 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1645 ("PHY_APCalibrate() offset 0x%x "
1646 "value 0x%x\n",
1647 apk_offset[path],
1648 rtl_get_bbreg(hw, apk_offset[path],
1649 MASKDWORD)));
1650
1651 mdelay(3);
1652
1653 rtl_set_bbreg(hw, apk_offset[path],
1654 MASKDWORD, apk_value[1]);
1655 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1656 ("PHY_APCalibrate() offset 0x%x "
1657 "value 0x%x\n",
1658 apk_offset[path],
1659 rtl_get_bbreg(hw, apk_offset[path],
1660 MASKDWORD)));
1661
1662 mdelay(20);
1663
1664 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
1665
1666 if (path == RF90_PATH_A)
1667 tmpreg = rtl_get_bbreg(hw, 0xbd8,
1668 0x03E00000);
1669 else
1670 tmpreg = rtl_get_bbreg(hw, 0xbd8,
1671 0xF8000000);
1672
1673 RTPRINT(rtlpriv, FINIT, INIT_IQK,
1674 ("PHY_APCalibrate() offset "
1675 "0xbd8[25:21] %x\n", tmpreg));
1676
1677 i++;
1678
1679 } while (tmpreg > apkbound && i < 4);
1680
1681 apk_result[path][index] = tmpreg;
1682 }
1683 }
1684
1685 _rtl92c_phy_reload_mac_registers(hw, mac_reg, mac_backup);
1686
1687 for (index = 0; index < APK_BB_REG_NUM; index++) {
1688 if (index == 0)
1689 continue;
1690 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD, bb_backup[index]);
1691 }
1692
1693 _rtl92c_phy_reload_adda_registers(hw, afe_reg, afe_backup, 16);
1694
1695 for (path = 0; path < pathbound; path++) {
1696 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
1697 MASKDWORD, reg_d[path]);
1698
1699 if (path == RF90_PATH_B) {
1700 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
1701 0x1000f);
1702 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
1703 0x20101);
1704 }
1705
1706 if (apk_result[path][1] > 6)
1707 apk_result[path][1] = 6;
1708 }
1709
1710 for (path = 0; path < pathbound; path++) {
1711 rtl_set_rfreg(hw, (enum radio_path)path, 0x3, MASKDWORD,
1712 ((apk_result[path][1] << 15) |
1713 (apk_result[path][1] << 10) |
1714 (apk_result[path][1] << 5) |
1715 apk_result[path][1]));
1716
1717 if (path == RF90_PATH_A)
1718 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1719 ((apk_result[path][1] << 15) |
1720 (apk_result[path][1] << 10) |
1721 (0x00 << 5) | 0x05));
1722 else
1723 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
1724 ((apk_result[path][1] << 15) |
1725 (apk_result[path][1] << 10) |
1726 (0x02 << 5) | 0x05));
1727
1728 rtl_set_rfreg(hw, (enum radio_path)path, 0xe, MASKDWORD,
1729 ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) |
1730 0x08));
1731
1732 }
1733
1734 rtlphy->apk_done = true;
1735#endif
1736}
1737
1738static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1739 bool bmain, bool is2t)
1740{
1741 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1742
1743 if (is_hal_stop(rtlhal)) {
1744 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1745 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1746 }
1747 if (is2t) {
1748 if (bmain)
1749 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1750 BIT(5) | BIT(6), 0x1);
1751 else
1752 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1753 BIT(5) | BIT(6), 0x2);
1754 } else {
1755 if (bmain)
1756 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1757 else
1758 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1759
1760 }
1761}
1762
1763#undef IQK_ADDA_REG_NUM
1764#undef IQK_DELAY_TIME
1765
1766void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1767{
1768 struct rtl_priv *rtlpriv = rtl_priv(hw);
1769 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1770 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1771
1772 long result[4][8];
1773 u8 i, final_candidate;
1774 bool patha_ok, pathb_ok;
1775 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1776 reg_ecc, reg_tmp = 0;
1777 bool is12simular, is13simular, is23simular;
1778 bool start_conttx = false, singletone = false;
1779 u32 iqk_bb_reg[10] = {
1780 ROFDM0_XARXIQIMBALANCE,
1781 ROFDM0_XBRXIQIMBALANCE,
1782 ROFDM0_ECCATHRESHOLD,
1783 ROFDM0_AGCRSSITABLE,
1784 ROFDM0_XATXIQIMBALANCE,
1785 ROFDM0_XBTXIQIMBALANCE,
1786 ROFDM0_XCTXIQIMBALANCE,
1787 ROFDM0_XCTXAFE,
1788 ROFDM0_XDTXAFE,
1789 ROFDM0_RXIQEXTANTA
1790 };
1791
1792 if (recovery) {
1793 _rtl92c_phy_reload_adda_registers(hw,
1794 iqk_bb_reg,
1795 rtlphy->iqk_bb_backup, 10);
1796 return;
1797 }
1798 if (start_conttx || singletone)
1799 return;
1800 for (i = 0; i < 8; i++) {
1801 result[0][i] = 0;
1802 result[1][i] = 0;
1803 result[2][i] = 0;
1804 result[3][i] = 0;
1805 }
1806 final_candidate = 0xff;
1807 patha_ok = false;
1808 pathb_ok = false;
1809 is12simular = false;
1810 is23simular = false;
1811 is13simular = false;
1812 for (i = 0; i < 3; i++) {
1813 if (IS_92C_SERIAL(rtlhal->version))
1814 _rtl92c_phy_iq_calibrate(hw, result, i, true);
1815 else
1816 _rtl92c_phy_iq_calibrate(hw, result, i, false);
1817 if (i == 1) {
1818 is12simular = _rtl92c_phy_simularity_compare(hw,
1819 result, 0,
1820 1);
1821 if (is12simular) {
1822 final_candidate = 0;
1823 break;
1824 }
1825 }
1826 if (i == 2) {
1827 is13simular = _rtl92c_phy_simularity_compare(hw,
1828 result, 0,
1829 2);
1830 if (is13simular) {
1831 final_candidate = 0;
1832 break;
1833 }
1834 is23simular = _rtl92c_phy_simularity_compare(hw,
1835 result, 1,
1836 2);
1837 if (is23simular)
1838 final_candidate = 1;
1839 else {
1840 for (i = 0; i < 8; i++)
1841 reg_tmp += result[3][i];
1842
1843 if (reg_tmp != 0)
1844 final_candidate = 3;
1845 else
1846 final_candidate = 0xFF;
1847 }
1848 }
1849 }
1850 for (i = 0; i < 4; i++) {
1851 reg_e94 = result[i][0];
1852 reg_e9c = result[i][1];
1853 reg_ea4 = result[i][2];
1854 reg_eac = result[i][3];
1855 reg_eb4 = result[i][4];
1856 reg_ebc = result[i][5];
1857 reg_ec4 = result[i][6];
1858 reg_ecc = result[i][7];
1859 }
1860 if (final_candidate != 0xff) {
1861 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1862 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1863 reg_ea4 = result[final_candidate][2];
1864 reg_eac = result[final_candidate][3];
1865 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1866 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1867 reg_ec4 = result[final_candidate][6];
1868 reg_ecc = result[final_candidate][7];
1869 patha_ok = pathb_ok = true;
1870 } else {
1871 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1872 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1873 }
1874 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1875 _rtl92c_phy_path_a_fill_iqk_matrix(hw, patha_ok, result,
1876 final_candidate,
1877 (reg_ea4 == 0));
1878 if (IS_92C_SERIAL(rtlhal->version)) {
1879 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
1880 _rtl92c_phy_path_b_fill_iqk_matrix(hw, pathb_ok,
1881 result,
1882 final_candidate,
1883 (reg_ec4 == 0));
1884 }
1885 _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
1886 rtlphy->iqk_bb_backup, 10);
1887}
1888EXPORT_SYMBOL(rtl92c_phy_iq_calibrate);
1889
1890void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
1891{
1892 struct rtl_priv *rtlpriv = rtl_priv(hw);
1893 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1894 bool start_conttx = false, singletone = false;
1895
1896 if (start_conttx || singletone)
1897 return;
1898 if (IS_92C_SERIAL(rtlhal->version))
1899 rtlpriv->cfg->ops->phy_lc_calibrate(hw, true);
1900 else
1901 rtlpriv->cfg->ops->phy_lc_calibrate(hw, false);
1902}
1903EXPORT_SYMBOL(rtl92c_phy_lc_calibrate);
1904
1905void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
1906{
1907 struct rtl_priv *rtlpriv = rtl_priv(hw);
1908 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1909 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1910
1911 if (rtlphy->apk_done)
1912 return;
1913 if (IS_92C_SERIAL(rtlhal->version))
1914 _rtl92c_phy_ap_calibrate(hw, delta, true);
1915 else
1916 _rtl92c_phy_ap_calibrate(hw, delta, false);
1917}
1918EXPORT_SYMBOL(rtl92c_phy_ap_calibrate);
1919
1920void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1921{
1922 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1923
1924 if (IS_92C_SERIAL(rtlhal->version))
1925 _rtl92c_phy_set_rfpath_switch(hw, bmain, true);
1926 else
1927 _rtl92c_phy_set_rfpath_switch(hw, bmain, false);
1928}
1929EXPORT_SYMBOL(rtl92c_phy_set_rfpath_switch);
1930
1931bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1932{
1933 struct rtl_priv *rtlpriv = rtl_priv(hw);
1934 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1935 bool postprocessing = false;
1936
1937 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1938 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1939 iotype, rtlphy->set_io_inprogress));
1940 do {
1941 switch (iotype) {
1942 case IO_CMD_RESUME_DM_BY_SCAN:
1943 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1944 ("[IO CMD] Resume DM after scan.\n"));
1945 postprocessing = true;
1946 break;
1947 case IO_CMD_PAUSE_DM_BY_SCAN:
1948 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1949 ("[IO CMD] Pause DM before scan.\n"));
1950 postprocessing = true;
1951 break;
1952 default:
1953 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1954 ("switch case not process\n"));
1955 break;
1956 }
1957 } while (false);
1958 if (postprocessing && !rtlphy->set_io_inprogress) {
1959 rtlphy->set_io_inprogress = true;
1960 rtlphy->current_io_type = iotype;
1961 } else {
1962 return false;
1963 }
1964 rtl92c_phy_set_io(hw);
1965 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype));
1966 return true;
1967}
1968EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
1969
1970void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1971{
1972 struct rtl_priv *rtlpriv = rtl_priv(hw);
1973 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1974
1975 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1976 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
1977 rtlphy->current_io_type, rtlphy->set_io_inprogress));
1978 switch (rtlphy->current_io_type) {
1979 case IO_CMD_RESUME_DM_BY_SCAN:
1980 dm_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1981 rtl92c_dm_write_dig(hw);
1982 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1983 break;
1984 case IO_CMD_PAUSE_DM_BY_SCAN:
1985 rtlphy->initgain_backup.xaagccore1 = dm_digtable.cur_igvalue;
1986 dm_digtable.cur_igvalue = 0x17;
1987 rtl92c_dm_write_dig(hw);
1988 break;
1989 default:
1990 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1991 ("switch case not process\n"));
1992 break;
1993 }
1994 rtlphy->set_io_inprogress = false;
1995 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1996 ("<---(%#x)\n", rtlphy->current_io_type));
1997}
1998EXPORT_SYMBOL(rtl92c_phy_set_io);
1999
2000void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
2001{
2002 struct rtl_priv *rtlpriv = rtl_priv(hw);
2003
2004 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2005 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2006 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2007 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2008 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2009 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2010}
2011EXPORT_SYMBOL(rtl92ce_phy_set_rf_on);
2012
2013void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw)
2014{
2015 u32 u4b_tmp;
2016 u8 delay = 5;
2017 struct rtl_priv *rtlpriv = rtl_priv(hw);
2018
2019 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2020 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2021 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2022 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2023 while (u4b_tmp != 0 && delay > 0) {
2024 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
2025 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2026 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2027 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2028 delay--;
2029 }
2030 if (delay == 0) {
2031 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2032 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2033 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2034 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2035 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
2036 ("Switch RF timeout !!!.\n"));
2037 return;
2038 }
2039 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2040 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2041}
2042EXPORT_SYMBOL(_rtl92c_phy_set_rf_sleep);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.h b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.h
new file mode 100644
index 000000000000..53ffb0981586
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192c/phy_common.h
@@ -0,0 +1,246 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_PHY_H__
31#define __RTL92C_PHY_H__
32
33#define MAX_PRECMD_CNT 16
34#define MAX_RFDEPENDCMD_CNT 16
35#define MAX_POSTCMD_CNT 16
36
37#define MAX_DOZE_WAITING_TIMES_9x 64
38
39#define RT_CANNOT_IO(hw) false
40#define HIGHPOWER_RADIOA_ARRAYLEN 22
41
42#define MAX_TOLERANCE 5
43#define IQK_DELAY_TIME 1
44
45#define APK_BB_REG_NUM 5
46#define APK_AFE_REG_NUM 16
47#define APK_CURVE_REG_NUM 4
48#define PATH_NUM 2
49
50#define LOOP_LIMIT 5
51#define MAX_STALL_TIME 50
52#define AntennaDiversityValue 0x80
53#define MAX_TXPWR_IDX_NMODE_92S 63
54#define Reset_Cnt_Limit 3
55
56#define IQK_ADDA_REG_NUM 16
57#define IQK_MAC_REG_NUM 4
58
59#define RF90_PATH_MAX 2
60
61#define CT_OFFSET_MAC_ADDR 0X16
62
63#define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
64#define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
65#define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66
66#define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
67#define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
68
69#define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
70#define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
71
72#define CT_OFFSET_CHANNEL_PLAH 0x75
73#define CT_OFFSET_THERMAL_METER 0x78
74#define CT_OFFSET_RF_OPTION 0x79
75#define CT_OFFSET_VERSION 0x7E
76#define CT_OFFSET_CUSTOMER_ID 0x7F
77
78#define RTL92C_MAX_PATH_NUM 2
79#define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
80enum swchnlcmd_id {
81 CMDID_END,
82 CMDID_SET_TXPOWEROWER_LEVEL,
83 CMDID_BBREGWRITE10,
84 CMDID_WRITEPORT_ULONG,
85 CMDID_WRITEPORT_USHORT,
86 CMDID_WRITEPORT_UCHAR,
87 CMDID_RF_WRITEREG,
88};
89
90struct swchnlcmd {
91 enum swchnlcmd_id cmdid;
92 u32 para1;
93 u32 para2;
94 u32 msdelay;
95};
96
97enum hw90_block_e {
98 HW90_BLOCK_MAC = 0,
99 HW90_BLOCK_PHY0 = 1,
100 HW90_BLOCK_PHY1 = 2,
101 HW90_BLOCK_RF = 3,
102 HW90_BLOCK_MAXIMUM = 4,
103};
104
105enum baseband_config_type {
106 BASEBAND_CONFIG_PHY_REG = 0,
107 BASEBAND_CONFIG_AGC_TAB = 1,
108};
109
110enum ra_offset_area {
111 RA_OFFSET_LEGACY_OFDM1,
112 RA_OFFSET_LEGACY_OFDM2,
113 RA_OFFSET_HT_OFDM1,
114 RA_OFFSET_HT_OFDM2,
115 RA_OFFSET_HT_OFDM3,
116 RA_OFFSET_HT_OFDM4,
117 RA_OFFSET_HT_CCK,
118};
119
120enum antenna_path {
121 ANTENNA_NONE,
122 ANTENNA_D,
123 ANTENNA_C,
124 ANTENNA_CD,
125 ANTENNA_B,
126 ANTENNA_BD,
127 ANTENNA_BC,
128 ANTENNA_BCD,
129 ANTENNA_A,
130 ANTENNA_AD,
131 ANTENNA_AC,
132 ANTENNA_ACD,
133 ANTENNA_AB,
134 ANTENNA_ABD,
135 ANTENNA_ABC,
136 ANTENNA_ABCD
137};
138
139struct r_antenna_select_ofdm {
140 u32 r_tx_antenna:4;
141 u32 r_ant_l:4;
142 u32 r_ant_non_ht:4;
143 u32 r_ant_ht1:4;
144 u32 r_ant_ht2:4;
145 u32 r_ant_ht_s1:4;
146 u32 r_ant_non_ht_s1:4;
147 u32 ofdm_txsc:2;
148 u32 reserved:2;
149};
150
151struct r_antenna_select_cck {
152 u8 r_cckrx_enable_2:2;
153 u8 r_cckrx_enable:2;
154 u8 r_ccktx_enable:4;
155};
156
157struct efuse_contents {
158 u8 mac_addr[ETH_ALEN];
159 u8 cck_tx_power_idx[6];
160 u8 ht40_1s_tx_power_idx[6];
161 u8 ht40_2s_tx_power_idx_diff[3];
162 u8 ht20_tx_power_idx_diff[3];
163 u8 ofdm_tx_power_idx_diff[3];
164 u8 ht40_max_power_offset[3];
165 u8 ht20_max_power_offset[3];
166 u8 channel_plan;
167 u8 thermal_meter;
168 u8 rf_option[5];
169 u8 version;
170 u8 oem_id;
171 u8 regulatory;
172};
173
174struct tx_power_struct {
175 u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
176 u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
177 u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
178 u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
179 u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
180 u8 legacy_ht_txpowerdiff;
181 u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
182 u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
183 u8 pwrgroup_cnt;
184 u32 mcs_original_offset[4][16];
185};
186
187extern u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw,
188 u32 regaddr, u32 bitmask);
189extern void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
190 u32 regaddr, u32 bitmask, u32 data);
191extern u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
192 enum radio_path rfpath, u32 regaddr,
193 u32 bitmask);
194extern void rtl92c_phy_set_rf_reg(struct ieee80211_hw *hw,
195 enum radio_path rfpath, u32 regaddr,
196 u32 bitmask, u32 data);
197extern bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
198extern bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
199extern bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
200extern bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
201 enum radio_path rfpath);
202extern void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
203extern void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw,
204 long *powerlevel);
205extern void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
206extern bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
207 long power_indbm);
208extern void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw,
209 u8 operation);
210extern void rtl92c_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
211extern void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
212 enum nl80211_channel_type ch_type);
213extern void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
214extern u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
215extern void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
216extern void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw,
217 u16 beaconinterval);
218void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
219void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
220void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
221bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
222 enum radio_path rfpath);
223extern bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
224 u32 rfpath);
225extern bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
226 enum rf_pwrstate rfpwr_state);
227void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
228void rtl92c_phy_set_io(struct ieee80211_hw *hw);
229void rtl92c_bb_block_on(struct ieee80211_hw *hw);
230u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
231long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
232 enum wireless_mode wirelessmode,
233 u8 txpwridx);
234u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
235 enum wireless_mode wirelessmode,
236 long power_indbm);
237void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
238static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
239 u32 cmdtableidx, u32 cmdtablesz,
240 enum swchnlcmd_id cmdid, u32 para1,
241 u32 para2, u32 msdelay);
242static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
243 u8 channel, u8 *stage, u8 *step,
244 u32 *delay);
245
246#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/Makefile b/drivers/net/wireless/rtlwifi/rtl8192ce/Makefile
index 0f0be7c763b8..c0cb0cfe7d37 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/Makefile
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/Makefile
@@ -1,6 +1,5 @@
1rtl8192ce-objs := \ 1rtl8192ce-objs := \
2 dm.o \ 2 dm.o \
3 fw.o \
4 hw.o \ 3 hw.o \
5 led.o \ 4 led.o \
6 phy.o \ 5 phy.o \
@@ -10,3 +9,5 @@ rtl8192ce-objs := \
10 trx.o 9 trx.o
11 10
12obj-$(CONFIG_RTL8192CE) += rtl8192ce.o 11obj-$(CONFIG_RTL8192CE) += rtl8192ce.o
12
13ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/def.h b/drivers/net/wireless/rtlwifi/rtl8192ce/def.h
index 83cd64895292..2f577c8828fc 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/def.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/def.h
@@ -121,11 +121,37 @@
121#define CHIP_92C 0x01 121#define CHIP_92C 0x01
122#define CHIP_88C 0x00 122#define CHIP_88C 0x00
123 123
124/* Add vendor information into chip version definition.
125 * Add UMC B-Cut and RTL8723 chip info definition.
126 *
127 * BIT 7 Reserved
128 * BIT 6 UMC BCut
129 * BIT 5 Manufacturer(TSMC/UMC)
130 * BIT 4 TEST/NORMAL
131 * BIT 3 8723 Version
132 * BIT 2 8723?
133 * BIT 1 1T2R?
134 * BIT 0 88C/92C
135*/
136
124enum version_8192c { 137enum version_8192c {
125 VERSION_A_CHIP_92C = 0x01, 138 VERSION_A_CHIP_92C = 0x01,
126 VERSION_A_CHIP_88C = 0x00, 139 VERSION_A_CHIP_88C = 0x00,
127 VERSION_B_CHIP_92C = 0x11, 140 VERSION_B_CHIP_92C = 0x11,
128 VERSION_B_CHIP_88C = 0x10, 141 VERSION_B_CHIP_88C = 0x10,
142 VERSION_TEST_CHIP_88C = 0x00,
143 VERSION_TEST_CHIP_92C = 0x01,
144 VERSION_NORMAL_TSMC_CHIP_88C = 0x10,
145 VERSION_NORMAL_TSMC_CHIP_92C = 0x11,
146 VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x13,
147 VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x30,
148 VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x31,
149 VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x33,
150 VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT = 0x34,
151 VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT = 0x3c,
152 VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x70,
153 VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x71,
154 VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x73,
129 VERSION_UNKNOWN = 0x88, 155 VERSION_UNKNOWN = 0x88,
130}; 156};
131 157
@@ -254,4 +280,122 @@ struct h2c_cmd_8192c {
254 u8 *p_cmdbuffer; 280 u8 *p_cmdbuffer;
255}; 281};
256 282
283static inline u8 _rtl92c_get_chnl_group(u8 chnl)
284{
285 u8 group = 0;
286
287 if (chnl < 3)
288 group = 0;
289 else if (chnl < 9)
290 group = 1;
291 else
292 group = 2;
293
294 return group;
295}
296
297/* NOTE: reference to rtl8192c_rates struct */
298static inline int _rtl92c_rate_mapping(struct ieee80211_hw *hw, bool isHT,
299 u8 desc_rate, bool first_ampdu)
300{
301 struct rtl_priv *rtlpriv = rtl_priv(hw);
302 int rate_idx = 0;
303
304 if (first_ampdu) {
305 if (false == isHT) {
306 switch (desc_rate) {
307 case DESC92C_RATE1M:
308 rate_idx = 0;
309 break;
310 case DESC92C_RATE2M:
311 rate_idx = 1;
312 break;
313 case DESC92C_RATE5_5M:
314 rate_idx = 2;
315 break;
316 case DESC92C_RATE11M:
317 rate_idx = 3;
318 break;
319 case DESC92C_RATE6M:
320 rate_idx = 4;
321 break;
322 case DESC92C_RATE9M:
323 rate_idx = 5;
324 break;
325 case DESC92C_RATE12M:
326 rate_idx = 6;
327 break;
328 case DESC92C_RATE18M:
329 rate_idx = 7;
330 break;
331 case DESC92C_RATE24M:
332 rate_idx = 8;
333 break;
334 case DESC92C_RATE36M:
335 rate_idx = 9;
336 break;
337 case DESC92C_RATE48M:
338 rate_idx = 10;
339 break;
340 case DESC92C_RATE54M:
341 rate_idx = 11;
342 break;
343 default:
344 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
345 ("Rate %d is not support, set to "
346 "1M rate.\n", desc_rate));
347 rate_idx = 0;
348 break;
349 }
350 } else {
351 rate_idx = 11;
352 }
353 return rate_idx;
354 }
355 switch (desc_rate) {
356 case DESC92C_RATE1M:
357 rate_idx = 0;
358 break;
359 case DESC92C_RATE2M:
360 rate_idx = 1;
361 break;
362 case DESC92C_RATE5_5M:
363 rate_idx = 2;
364 break;
365 case DESC92C_RATE11M:
366 rate_idx = 3;
367 break;
368 case DESC92C_RATE6M:
369 rate_idx = 4;
370 break;
371 case DESC92C_RATE9M:
372 rate_idx = 5;
373 break;
374 case DESC92C_RATE12M:
375 rate_idx = 6;
376 break;
377 case DESC92C_RATE18M:
378 rate_idx = 7;
379 break;
380 case DESC92C_RATE24M:
381 rate_idx = 8;
382 break;
383 case DESC92C_RATE36M:
384 rate_idx = 9;
385 break;
386 case DESC92C_RATE48M:
387 rate_idx = 10;
388 break;
389 case DESC92C_RATE54M:
390 rate_idx = 11;
391 break;
392 /* TODO: How to mapping MCS rate? */
393 /* NOTE: referenc to __ieee80211_rx */
394 default:
395 rate_idx = 11;
396 break;
397 }
398 return rate_idx;
399}
400
257#endif 401#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/dm.c b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.c
index 62e7c64e087b..7d76504df4d1 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/dm.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.c
@@ -33,487 +33,15 @@
33#include "def.h" 33#include "def.h"
34#include "phy.h" 34#include "phy.h"
35#include "dm.h" 35#include "dm.h"
36#include "fw.h"
37 36
38struct dig_t dm_digtable; 37void rtl92ce_dm_dynamic_txpower(struct ieee80211_hw *hw)
39static struct ps_t dm_pstable;
40
41static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
42 0x7f8001fe,
43 0x788001e2,
44 0x71c001c7,
45 0x6b8001ae,
46 0x65400195,
47 0x5fc0017f,
48 0x5a400169,
49 0x55400155,
50 0x50800142,
51 0x4c000130,
52 0x47c0011f,
53 0x43c0010f,
54 0x40000100,
55 0x3c8000f2,
56 0x390000e4,
57 0x35c000d7,
58 0x32c000cb,
59 0x300000c0,
60 0x2d4000b5,
61 0x2ac000ab,
62 0x288000a2,
63 0x26000098,
64 0x24000090,
65 0x22000088,
66 0x20000080,
67 0x1e400079,
68 0x1c800072,
69 0x1b00006c,
70 0x19800066,
71 0x18000060,
72 0x16c0005b,
73 0x15800056,
74 0x14400051,
75 0x1300004c,
76 0x12000048,
77 0x11000044,
78 0x10000040,
79};
80
81static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
82 {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
83 {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
84 {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
85 {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
86 {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
87 {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
88 {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
89 {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
90 {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
91 {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
92 {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
93 {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
94 {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
95 {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
96 {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
97 {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
98 {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
99 {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
100 {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
101 {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
102 {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
103 {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
104 {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
105 {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
106 {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
107 {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
108 {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
109 {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
110 {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
111 {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
112 {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
113 {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
114 {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
115};
116
117static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
118 {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
119 {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
120 {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
121 {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
122 {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
123 {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
124 {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
125 {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
126 {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
127 {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
128 {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
129 {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
130 {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
131 {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
132 {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
133 {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
134 {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
135 {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
136 {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
137 {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
138 {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
139 {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
140 {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
141 {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
142 {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
143 {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
144 {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
145 {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
146 {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
147 {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
148 {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
149 {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
150 {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
151};
152
153static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
154{
155 dm_digtable.dig_enable_flag = true;
156 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
157 dm_digtable.cur_igvalue = 0x20;
158 dm_digtable.pre_igvalue = 0x0;
159 dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
160 dm_digtable.presta_connectstate = DIG_STA_DISCONNECT;
161 dm_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
162 dm_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
163 dm_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
164 dm_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
165 dm_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
166 dm_digtable.rx_gain_range_max = DM_DIG_MAX;
167 dm_digtable.rx_gain_range_min = DM_DIG_MIN;
168 dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
169 dm_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
170 dm_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
171 dm_digtable.pre_cck_pd_state = CCK_PD_STAGE_MAX;
172 dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
173}
174
175static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
176{
177 struct rtl_priv *rtlpriv = rtl_priv(hw);
178 long rssi_val_min = 0;
179
180 if ((dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
181 (dm_digtable.cursta_connectctate == DIG_STA_CONNECT)) {
182 if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
183 rssi_val_min =
184 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
185 rtlpriv->dm.undecorated_smoothed_pwdb) ?
186 rtlpriv->dm.undecorated_smoothed_pwdb :
187 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
188 else
189 rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
190 } else if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT ||
191 dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
192 rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
193 } else if (dm_digtable.curmultista_connectstate ==
194 DIG_MULTISTA_CONNECT) {
195 rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
196 }
197
198 return (u8) rssi_val_min;
199}
200
201static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
202{
203 u32 ret_value;
204 struct rtl_priv *rtlpriv = rtl_priv(hw);
205 struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
206
207 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
208 falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
209
210 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
211 falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
212 falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
213
214 ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
215 falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
216 falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
217 falsealm_cnt->cnt_rate_illegal +
218 falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
219
220 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
221 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
222 falsealm_cnt->cnt_cck_fail = ret_value;
223
224 ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
225 falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
226 falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
227 falsealm_cnt->cnt_rate_illegal +
228 falsealm_cnt->cnt_crc8_fail +
229 falsealm_cnt->cnt_mcs_fail +
230 falsealm_cnt->cnt_cck_fail);
231
232 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
233 rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
234 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
235 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
236
237 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
238 ("cnt_parity_fail = %d, cnt_rate_illegal = %d, "
239 "cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
240 falsealm_cnt->cnt_parity_fail,
241 falsealm_cnt->cnt_rate_illegal,
242 falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail));
243
244 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
245 ("cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
246 falsealm_cnt->cnt_ofdm_fail,
247 falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all));
248}
249
250static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
251{
252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 u8 value_igi = dm_digtable.cur_igvalue;
254
255 if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
256 value_igi--;
257 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
258 value_igi += 0;
259 else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
260 value_igi++;
261 else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
262 value_igi += 2;
263 if (value_igi > DM_DIG_FA_UPPER)
264 value_igi = DM_DIG_FA_UPPER;
265 else if (value_igi < DM_DIG_FA_LOWER)
266 value_igi = DM_DIG_FA_LOWER;
267 if (rtlpriv->falsealm_cnt.cnt_all > 10000)
268 value_igi = 0x32;
269
270 dm_digtable.cur_igvalue = value_igi;
271 rtl92c_dm_write_dig(hw);
272}
273
274static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
275{
276 struct rtl_priv *rtlpriv = rtl_priv(hw);
277
278 if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable.fa_highthresh) {
279 if ((dm_digtable.backoff_val - 2) <
280 dm_digtable.backoff_val_range_min)
281 dm_digtable.backoff_val =
282 dm_digtable.backoff_val_range_min;
283 else
284 dm_digtable.backoff_val -= 2;
285 } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable.fa_lowthresh) {
286 if ((dm_digtable.backoff_val + 2) >
287 dm_digtable.backoff_val_range_max)
288 dm_digtable.backoff_val =
289 dm_digtable.backoff_val_range_max;
290 else
291 dm_digtable.backoff_val += 2;
292 }
293
294 if ((dm_digtable.rssi_val_min + 10 - dm_digtable.backoff_val) >
295 dm_digtable.rx_gain_range_max)
296 dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_max;
297 else if ((dm_digtable.rssi_val_min + 10 -
298 dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
299 dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_min;
300 else
301 dm_digtable.cur_igvalue = dm_digtable.rssi_val_min + 10 -
302 dm_digtable.backoff_val;
303
304 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
305 ("rssi_val_min = %x backoff_val %x\n",
306 dm_digtable.rssi_val_min, dm_digtable.backoff_val));
307
308 rtl92c_dm_write_dig(hw);
309}
310
311static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
312{
313 static u8 binitialized; /* initialized to false */
314 struct rtl_priv *rtlpriv = rtl_priv(hw);
315 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
316 long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
317 bool b_multi_sta = false;
318
319 if (mac->opmode == NL80211_IFTYPE_ADHOC)
320 b_multi_sta = true;
321
322 if ((b_multi_sta == false) || (dm_digtable.cursta_connectctate !=
323 DIG_STA_DISCONNECT)) {
324 binitialized = false;
325 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
326 return;
327 } else if (binitialized == false) {
328 binitialized = true;
329 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
330 dm_digtable.cur_igvalue = 0x20;
331 rtl92c_dm_write_dig(hw);
332 }
333
334 if (dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) {
335 if ((rssi_strength < dm_digtable.rssi_lowthresh) &&
336 (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
337
338 if (dm_digtable.dig_ext_port_stage ==
339 DIG_EXT_PORT_STAGE_2) {
340 dm_digtable.cur_igvalue = 0x20;
341 rtl92c_dm_write_dig(hw);
342 }
343
344 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
345 } else if (rssi_strength > dm_digtable.rssi_highthresh) {
346 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
347 rtl92c_dm_ctrl_initgain_by_fa(hw);
348 }
349 } else if (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
350 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
351 dm_digtable.cur_igvalue = 0x20;
352 rtl92c_dm_write_dig(hw);
353 }
354
355 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
356 ("curmultista_connectstate = "
357 "%x dig_ext_port_stage %x\n",
358 dm_digtable.curmultista_connectstate,
359 dm_digtable.dig_ext_port_stage));
360}
361
362static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
363{
364 struct rtl_priv *rtlpriv = rtl_priv(hw);
365
366 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
367 ("presta_connectstate = %x,"
368 " cursta_connectctate = %x\n",
369 dm_digtable.presta_connectstate,
370 dm_digtable.cursta_connectctate));
371
372 if (dm_digtable.presta_connectstate == dm_digtable.cursta_connectctate
373 || dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT
374 || dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
375
376 if (dm_digtable.cursta_connectctate != DIG_STA_DISCONNECT) {
377 dm_digtable.rssi_val_min =
378 rtl92c_dm_initial_gain_min_pwdb(hw);
379 rtl92c_dm_ctrl_initgain_by_rssi(hw);
380 }
381 } else {
382 dm_digtable.rssi_val_min = 0;
383 dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
384 dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
385 dm_digtable.cur_igvalue = 0x20;
386 dm_digtable.pre_igvalue = 0;
387 rtl92c_dm_write_dig(hw);
388 }
389}
390
391static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
392{
393 struct rtl_priv *rtlpriv = rtl_priv(hw);
394 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
395
396 if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
397 dm_digtable.rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
398
399 if (dm_digtable.pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
400 if (dm_digtable.rssi_val_min <= 25)
401 dm_digtable.cur_cck_pd_state =
402 CCK_PD_STAGE_LowRssi;
403 else
404 dm_digtable.cur_cck_pd_state =
405 CCK_PD_STAGE_HighRssi;
406 } else {
407 if (dm_digtable.rssi_val_min <= 20)
408 dm_digtable.cur_cck_pd_state =
409 CCK_PD_STAGE_LowRssi;
410 else
411 dm_digtable.cur_cck_pd_state =
412 CCK_PD_STAGE_HighRssi;
413 }
414 } else {
415 dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
416 }
417
418 if (dm_digtable.pre_cck_pd_state != dm_digtable.cur_cck_pd_state) {
419 if (dm_digtable.cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
420 if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
421 dm_digtable.cur_cck_fa_state =
422 CCK_FA_STAGE_High;
423 else
424 dm_digtable.cur_cck_fa_state = CCK_FA_STAGE_Low;
425
426 if (dm_digtable.pre_cck_fa_state !=
427 dm_digtable.cur_cck_fa_state) {
428 if (dm_digtable.cur_cck_fa_state ==
429 CCK_FA_STAGE_Low)
430 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
431 0x83);
432 else
433 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
434 0xcd);
435
436 dm_digtable.pre_cck_fa_state =
437 dm_digtable.cur_cck_fa_state;
438 }
439
440 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
441
442 if (IS_92C_SERIAL(rtlhal->version))
443 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
444 MASKBYTE2, 0xd7);
445 } else {
446 rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
447 rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
448
449 if (IS_92C_SERIAL(rtlhal->version))
450 rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
451 MASKBYTE2, 0xd3);
452 }
453 dm_digtable.pre_cck_pd_state = dm_digtable.cur_cck_pd_state;
454 }
455
456 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
457 ("CCKPDStage=%x\n", dm_digtable.cur_cck_pd_state));
458
459 RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
460 ("is92C=%x\n", IS_92C_SERIAL(rtlhal->version)));
461}
462
463static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
464{
465 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
466
467 if (mac->act_scanning == true)
468 return;
469
470 if ((mac->link_state > MAC80211_NOLINK) &&
471 (mac->link_state < MAC80211_LINKED))
472 dm_digtable.cursta_connectctate = DIG_STA_BEFORE_CONNECT;
473 else if (mac->link_state >= MAC80211_LINKED)
474 dm_digtable.cursta_connectctate = DIG_STA_CONNECT;
475 else
476 dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
477
478 rtl92c_dm_initial_gain_sta(hw);
479 rtl92c_dm_initial_gain_multi_sta(hw);
480 rtl92c_dm_cck_packet_detection_thresh(hw);
481
482 dm_digtable.presta_connectstate = dm_digtable.cursta_connectctate;
483
484}
485
486static void rtl92c_dm_dig(struct ieee80211_hw *hw)
487{
488 struct rtl_priv *rtlpriv = rtl_priv(hw);
489
490 if (rtlpriv->dm.b_dm_initialgain_enable == false)
491 return;
492 if (dm_digtable.dig_enable_flag == false)
493 return;
494
495 rtl92c_dm_ctrl_initgain_by_twoport(hw);
496
497}
498
499static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
500{
501 struct rtl_priv *rtlpriv = rtl_priv(hw);
502
503 rtlpriv->dm.bdynamic_txpower_enable = false;
504
505 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
506 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
507}
508
509static void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
510{ 38{
511 struct rtl_priv *rtlpriv = rtl_priv(hw); 39 struct rtl_priv *rtlpriv = rtl_priv(hw);
512 struct rtl_phy *rtlphy = &(rtlpriv->phy); 40 struct rtl_phy *rtlphy = &(rtlpriv->phy);
513 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 41 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
514 long undecorated_smoothed_pwdb; 42 long undecorated_smoothed_pwdb;
515 43
516 if (!rtlpriv->dm.bdynamic_txpower_enable) 44 if (!rtlpriv->dm.dynamic_txpower_enable)
517 return; 45 return;
518 46
519 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) { 47 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
@@ -583,891 +111,3 @@ static void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
583 111
584 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl; 112 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
585} 113}
586
587void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
588{
589 struct rtl_priv *rtlpriv = rtl_priv(hw);
590
591 RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
592 ("cur_igvalue = 0x%x, "
593 "pre_igvalue = 0x%x, backoff_val = %d\n",
594 dm_digtable.cur_igvalue, dm_digtable.pre_igvalue,
595 dm_digtable.backoff_val));
596
597 if (dm_digtable.pre_igvalue != dm_digtable.cur_igvalue) {
598 rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
599 dm_digtable.cur_igvalue);
600 rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
601 dm_digtable.cur_igvalue);
602
603 dm_digtable.pre_igvalue = dm_digtable.cur_igvalue;
604 }
605}
606
607static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
608{
609 struct rtl_priv *rtlpriv = rtl_priv(hw);
610 long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
611
612 u8 h2c_parameter[3] = { 0 };
613
614 return;
615
616 if (tmpentry_max_pwdb != 0) {
617 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
618 tmpentry_max_pwdb;
619 } else {
620 rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
621 }
622
623 if (tmpentry_min_pwdb != 0xff) {
624 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
625 tmpentry_min_pwdb;
626 } else {
627 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
628 }
629
630 h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
631 h2c_parameter[0] = 0;
632
633 rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
634}
635
636void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
637{
638 struct rtl_priv *rtlpriv = rtl_priv(hw);
639 rtlpriv->dm.bcurrent_turbo_edca = false;
640 rtlpriv->dm.bis_any_nonbepkts = false;
641 rtlpriv->dm.bis_cur_rdlstate = false;
642}
643
644static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
645{
646 struct rtl_priv *rtlpriv = rtl_priv(hw);
647 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
648 static u64 last_txok_cnt;
649 static u64 last_rxok_cnt;
650 u64 cur_txok_cnt;
651 u64 cur_rxok_cnt;
652 u32 edca_be_ul = 0x5ea42b;
653 u32 edca_be_dl = 0x5ea42b;
654
655 if (mac->opmode == NL80211_IFTYPE_ADHOC)
656 goto dm_checkedcaturbo_exit;
657
658 if (mac->link_state != MAC80211_LINKED) {
659 rtlpriv->dm.bcurrent_turbo_edca = false;
660 return;
661 }
662
663 if (!mac->ht_enable) { /*FIX MERGE */
664 if (!(edca_be_ul & 0xffff0000))
665 edca_be_ul |= 0x005e0000;
666
667 if (!(edca_be_dl & 0xffff0000))
668 edca_be_dl |= 0x005e0000;
669 }
670
671 if ((!rtlpriv->dm.bis_any_nonbepkts) &&
672 (!rtlpriv->dm.b_disable_framebursting)) {
673 cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
674 cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
675 if (cur_rxok_cnt > 4 * cur_txok_cnt) {
676 if (!rtlpriv->dm.bis_cur_rdlstate ||
677 !rtlpriv->dm.bcurrent_turbo_edca) {
678 rtl_write_dword(rtlpriv,
679 REG_EDCA_BE_PARAM,
680 edca_be_dl);
681 rtlpriv->dm.bis_cur_rdlstate = true;
682 }
683 } else {
684 if (rtlpriv->dm.bis_cur_rdlstate ||
685 !rtlpriv->dm.bcurrent_turbo_edca) {
686 rtl_write_dword(rtlpriv,
687 REG_EDCA_BE_PARAM,
688 edca_be_ul);
689 rtlpriv->dm.bis_cur_rdlstate = false;
690 }
691 }
692 rtlpriv->dm.bcurrent_turbo_edca = true;
693 } else {
694 if (rtlpriv->dm.bcurrent_turbo_edca) {
695 u8 tmp = AC0_BE;
696 rtlpriv->cfg->ops->set_hw_reg(hw,
697 HW_VAR_AC_PARAM,
698 (u8 *) (&tmp));
699 rtlpriv->dm.bcurrent_turbo_edca = false;
700 }
701 }
702
703dm_checkedcaturbo_exit:
704 rtlpriv->dm.bis_any_nonbepkts = false;
705 last_txok_cnt = rtlpriv->stats.txbytesunicast;
706 last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
707}
708
709static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
710 *hw)
711{
712 struct rtl_priv *rtlpriv = rtl_priv(hw);
713 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
714 struct rtl_phy *rtlphy = &(rtlpriv->phy);
715 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
716 u8 thermalvalue, delta, delta_lck, delta_iqk;
717 long ele_a, ele_d, temp_cck, val_x, value32;
718 long val_y, ele_c;
719 u8 ofdm_index[2], cck_index, ofdm_index_old[2], cck_index_old;
720 int i;
721 bool is2t = IS_92C_SERIAL(rtlhal->version);
722 u8 txpwr_level[2] = {0, 0};
723 u8 ofdm_min_index = 6, rf;
724
725 rtlpriv->dm.btxpower_trackingInit = true;
726 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
727 ("rtl92c_dm_txpower_tracking_callback_thermalmeter\n"));
728
729 thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
730
731 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
732 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
733 "eeprom_thermalmeter 0x%x\n",
734 thermalvalue, rtlpriv->dm.thermalvalue,
735 rtlefuse->eeprom_thermalmeter));
736
737 rtl92c_phy_ap_calibrate(hw, (thermalvalue -
738 rtlefuse->eeprom_thermalmeter));
739 if (is2t)
740 rf = 2;
741 else
742 rf = 1;
743
744 if (thermalvalue) {
745 ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
746 MASKDWORD) & MASKOFDM_D;
747
748 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
749 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
750 ofdm_index_old[0] = (u8) i;
751
752 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
753 ("Initial pathA ele_d reg0x%x = 0x%lx, "
754 "ofdm_index=0x%x\n",
755 ROFDM0_XATXIQIMBALANCE,
756 ele_d, ofdm_index_old[0]));
757 break;
758 }
759 }
760
761 if (is2t) {
762 ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
763 MASKDWORD) & MASKOFDM_D;
764
765 for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
766 if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
767 ofdm_index_old[1] = (u8) i;
768
769 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
770 DBG_LOUD,
771 ("Initial pathB ele_d reg0x%x = "
772 "0x%lx, ofdm_index=0x%x\n",
773 ROFDM0_XBTXIQIMBALANCE, ele_d,
774 ofdm_index_old[1]));
775 break;
776 }
777 }
778 }
779
780 temp_cck =
781 rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
782
783 for (i = 0; i < CCK_TABLE_LENGTH; i++) {
784 if (rtlpriv->dm.b_cck_inch14) {
785 if (memcmp((void *)&temp_cck,
786 (void *)&cckswing_table_ch14[i][2],
787 4) == 0) {
788 cck_index_old = (u8) i;
789
790 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
791 DBG_LOUD,
792 ("Initial reg0x%x = 0x%lx, "
793 "cck_index=0x%x, ch 14 %d\n",
794 RCCK0_TXFILTER2, temp_cck,
795 cck_index_old,
796 rtlpriv->dm.b_cck_inch14));
797 break;
798 }
799 } else {
800 if (memcmp((void *)&temp_cck,
801 (void *)
802 &cckswing_table_ch1ch13[i][2],
803 4) == 0) {
804 cck_index_old = (u8) i;
805
806 RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
807 DBG_LOUD,
808 ("Initial reg0x%x = 0x%lx, "
809 "cck_index=0x%x, ch14 %d\n",
810 RCCK0_TXFILTER2, temp_cck,
811 cck_index_old,
812 rtlpriv->dm.b_cck_inch14));
813 break;
814 }
815 }
816 }
817
818 if (!rtlpriv->dm.thermalvalue) {
819 rtlpriv->dm.thermalvalue =
820 rtlefuse->eeprom_thermalmeter;
821 rtlpriv->dm.thermalvalue_lck = thermalvalue;
822 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
823 for (i = 0; i < rf; i++)
824 rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
825 rtlpriv->dm.cck_index = cck_index_old;
826 }
827
828 delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
829 (thermalvalue - rtlpriv->dm.thermalvalue) :
830 (rtlpriv->dm.thermalvalue - thermalvalue);
831
832 delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
833 (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
834 (rtlpriv->dm.thermalvalue_lck - thermalvalue);
835
836 delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
837 (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
838 (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
839
840 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
841 ("Readback Thermal Meter = 0x%x pre thermal meter 0x%x "
842 "eeprom_thermalmeter 0x%x delta 0x%x "
843 "delta_lck 0x%x delta_iqk 0x%x\n",
844 thermalvalue, rtlpriv->dm.thermalvalue,
845 rtlefuse->eeprom_thermalmeter, delta, delta_lck,
846 delta_iqk));
847
848 if (delta_lck > 1) {
849 rtlpriv->dm.thermalvalue_lck = thermalvalue;
850 rtl92c_phy_lc_calibrate(hw);
851 }
852
853 if (delta > 0 && rtlpriv->dm.txpower_track_control) {
854 if (thermalvalue > rtlpriv->dm.thermalvalue) {
855 for (i = 0; i < rf; i++)
856 rtlpriv->dm.ofdm_index[i] -= delta;
857 rtlpriv->dm.cck_index -= delta;
858 } else {
859 for (i = 0; i < rf; i++)
860 rtlpriv->dm.ofdm_index[i] += delta;
861 rtlpriv->dm.cck_index += delta;
862 }
863
864 if (is2t) {
865 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
866 ("temp OFDM_A_index=0x%x, "
867 "OFDM_B_index=0x%x,"
868 "cck_index=0x%x\n",
869 rtlpriv->dm.ofdm_index[0],
870 rtlpriv->dm.ofdm_index[1],
871 rtlpriv->dm.cck_index));
872 } else {
873 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
874 ("temp OFDM_A_index=0x%x,"
875 "cck_index=0x%x\n",
876 rtlpriv->dm.ofdm_index[0],
877 rtlpriv->dm.cck_index));
878 }
879
880 if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
881 for (i = 0; i < rf; i++)
882 ofdm_index[i] =
883 rtlpriv->dm.ofdm_index[i]
884 + 1;
885 cck_index = rtlpriv->dm.cck_index + 1;
886 } else {
887 for (i = 0; i < rf; i++)
888 ofdm_index[i] =
889 rtlpriv->dm.ofdm_index[i];
890 cck_index = rtlpriv->dm.cck_index;
891 }
892
893 for (i = 0; i < rf; i++) {
894 if (txpwr_level[i] >= 0 &&
895 txpwr_level[i] <= 26) {
896 if (thermalvalue >
897 rtlefuse->eeprom_thermalmeter) {
898 if (delta < 5)
899 ofdm_index[i] -= 1;
900
901 else
902 ofdm_index[i] -= 2;
903 } else if (delta > 5 && thermalvalue <
904 rtlefuse->
905 eeprom_thermalmeter) {
906 ofdm_index[i] += 1;
907 }
908 } else if (txpwr_level[i] >= 27 &&
909 txpwr_level[i] <= 32
910 && thermalvalue >
911 rtlefuse->eeprom_thermalmeter) {
912 if (delta < 5)
913 ofdm_index[i] -= 1;
914
915 else
916 ofdm_index[i] -= 2;
917 } else if (txpwr_level[i] >= 32 &&
918 txpwr_level[i] <= 38 &&
919 thermalvalue >
920 rtlefuse->eeprom_thermalmeter
921 && delta > 5) {
922 ofdm_index[i] -= 1;
923 }
924 }
925
926 if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
927 if (thermalvalue >
928 rtlefuse->eeprom_thermalmeter) {
929 if (delta < 5)
930 cck_index -= 1;
931
932 else
933 cck_index -= 2;
934 } else if (delta > 5 && thermalvalue <
935 rtlefuse->eeprom_thermalmeter) {
936 cck_index += 1;
937 }
938 } else if (txpwr_level[i] >= 27 &&
939 txpwr_level[i] <= 32 &&
940 thermalvalue >
941 rtlefuse->eeprom_thermalmeter) {
942 if (delta < 5)
943 cck_index -= 1;
944
945 else
946 cck_index -= 2;
947 } else if (txpwr_level[i] >= 32 &&
948 txpwr_level[i] <= 38 &&
949 thermalvalue > rtlefuse->eeprom_thermalmeter
950 && delta > 5) {
951 cck_index -= 1;
952 }
953
954 for (i = 0; i < rf; i++) {
955 if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
956 ofdm_index[i] = OFDM_TABLE_SIZE - 1;
957
958 else if (ofdm_index[i] < ofdm_min_index)
959 ofdm_index[i] = ofdm_min_index;
960 }
961
962 if (cck_index > CCK_TABLE_SIZE - 1)
963 cck_index = CCK_TABLE_SIZE - 1;
964 else if (cck_index < 0)
965 cck_index = 0;
966
967 if (is2t) {
968 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
969 ("new OFDM_A_index=0x%x, "
970 "OFDM_B_index=0x%x,"
971 "cck_index=0x%x\n",
972 ofdm_index[0], ofdm_index[1],
973 cck_index));
974 } else {
975 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
976 ("new OFDM_A_index=0x%x,"
977 "cck_index=0x%x\n",
978 ofdm_index[0], cck_index));
979 }
980 }
981
982 if (rtlpriv->dm.txpower_track_control && delta != 0) {
983 ele_d =
984 (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
985 val_x = rtlphy->reg_e94;
986 val_y = rtlphy->reg_e9c;
987
988 if (val_x != 0) {
989 if ((val_x & 0x00000200) != 0)
990 val_x = val_x | 0xFFFFFC00;
991 ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
992
993 if ((val_y & 0x00000200) != 0)
994 val_y = val_y | 0xFFFFFC00;
995 ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
996
997 value32 = (ele_d << 22) |
998 ((ele_c & 0x3F) << 16) | ele_a;
999
1000 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1001 MASKDWORD, value32);
1002
1003 value32 = (ele_c & 0x000003C0) >> 6;
1004 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
1005 value32);
1006
1007 value32 = ((val_x * ele_d) >> 7) & 0x01;
1008 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1009 BIT(31), value32);
1010
1011 value32 = ((val_y * ele_d) >> 7) & 0x01;
1012 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1013 BIT(29), value32);
1014 } else {
1015 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1016 MASKDWORD,
1017 ofdmswing_table[ofdm_index[0]]);
1018
1019 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
1020 0x00);
1021 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1022 BIT(31) | BIT(29), 0x00);
1023 }
1024
1025 if (!rtlpriv->dm.b_cck_inch14) {
1026 rtl_write_byte(rtlpriv, 0xa22,
1027 cckswing_table_ch1ch13[cck_index]
1028 [0]);
1029 rtl_write_byte(rtlpriv, 0xa23,
1030 cckswing_table_ch1ch13[cck_index]
1031 [1]);
1032 rtl_write_byte(rtlpriv, 0xa24,
1033 cckswing_table_ch1ch13[cck_index]
1034 [2]);
1035 rtl_write_byte(rtlpriv, 0xa25,
1036 cckswing_table_ch1ch13[cck_index]
1037 [3]);
1038 rtl_write_byte(rtlpriv, 0xa26,
1039 cckswing_table_ch1ch13[cck_index]
1040 [4]);
1041 rtl_write_byte(rtlpriv, 0xa27,
1042 cckswing_table_ch1ch13[cck_index]
1043 [5]);
1044 rtl_write_byte(rtlpriv, 0xa28,
1045 cckswing_table_ch1ch13[cck_index]
1046 [6]);
1047 rtl_write_byte(rtlpriv, 0xa29,
1048 cckswing_table_ch1ch13[cck_index]
1049 [7]);
1050 } else {
1051 rtl_write_byte(rtlpriv, 0xa22,
1052 cckswing_table_ch14[cck_index]
1053 [0]);
1054 rtl_write_byte(rtlpriv, 0xa23,
1055 cckswing_table_ch14[cck_index]
1056 [1]);
1057 rtl_write_byte(rtlpriv, 0xa24,
1058 cckswing_table_ch14[cck_index]
1059 [2]);
1060 rtl_write_byte(rtlpriv, 0xa25,
1061 cckswing_table_ch14[cck_index]
1062 [3]);
1063 rtl_write_byte(rtlpriv, 0xa26,
1064 cckswing_table_ch14[cck_index]
1065 [4]);
1066 rtl_write_byte(rtlpriv, 0xa27,
1067 cckswing_table_ch14[cck_index]
1068 [5]);
1069 rtl_write_byte(rtlpriv, 0xa28,
1070 cckswing_table_ch14[cck_index]
1071 [6]);
1072 rtl_write_byte(rtlpriv, 0xa29,
1073 cckswing_table_ch14[cck_index]
1074 [7]);
1075 }
1076
1077 if (is2t) {
1078 ele_d = (ofdmswing_table[ofdm_index[1]] &
1079 0xFFC00000) >> 22;
1080
1081 val_x = rtlphy->reg_eb4;
1082 val_y = rtlphy->reg_ebc;
1083
1084 if (val_x != 0) {
1085 if ((val_x & 0x00000200) != 0)
1086 val_x = val_x | 0xFFFFFC00;
1087 ele_a = ((val_x * ele_d) >> 8) &
1088 0x000003FF;
1089
1090 if ((val_y & 0x00000200) != 0)
1091 val_y = val_y | 0xFFFFFC00;
1092 ele_c = ((val_y * ele_d) >> 8) &
1093 0x00003FF;
1094
1095 value32 = (ele_d << 22) |
1096 ((ele_c & 0x3F) << 16) | ele_a;
1097 rtl_set_bbreg(hw,
1098 ROFDM0_XBTXIQIMBALANCE,
1099 MASKDWORD, value32);
1100
1101 value32 = (ele_c & 0x000003C0) >> 6;
1102 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1103 MASKH4BITS, value32);
1104
1105 value32 = ((val_x * ele_d) >> 7) & 0x01;
1106 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1107 BIT(27), value32);
1108
1109 value32 = ((val_y * ele_d) >> 7) & 0x01;
1110 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1111 BIT(25), value32);
1112 } else {
1113 rtl_set_bbreg(hw,
1114 ROFDM0_XBTXIQIMBALANCE,
1115 MASKDWORD,
1116 ofdmswing_table[ofdm_index
1117 [1]]);
1118 rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
1119 MASKH4BITS, 0x00);
1120 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
1121 BIT(27) | BIT(25), 0x00);
1122 }
1123
1124 }
1125 }
1126
1127 if (delta_iqk > 3) {
1128 rtlpriv->dm.thermalvalue_iqk = thermalvalue;
1129 rtl92c_phy_iq_calibrate(hw, false);
1130 }
1131
1132 if (rtlpriv->dm.txpower_track_control)
1133 rtlpriv->dm.thermalvalue = thermalvalue;
1134 }
1135
1136 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, ("<===\n"));
1137
1138}
1139
1140static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
1141 struct ieee80211_hw *hw)
1142{
1143 struct rtl_priv *rtlpriv = rtl_priv(hw);
1144
1145 rtlpriv->dm.btxpower_tracking = true;
1146 rtlpriv->dm.btxpower_trackingInit = false;
1147
1148 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1149 ("pMgntInfo->btxpower_tracking = %d\n",
1150 rtlpriv->dm.btxpower_tracking));
1151}
1152
1153static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
1154{
1155 rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
1156}
1157
1158static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
1159{
1160 rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
1161}
1162
1163static void rtl92c_dm_check_txpower_tracking_thermal_meter(
1164 struct ieee80211_hw *hw)
1165{
1166 struct rtl_priv *rtlpriv = rtl_priv(hw);
1167 static u8 tm_trigger;
1168
1169 if (!rtlpriv->dm.btxpower_tracking)
1170 return;
1171
1172 if (!tm_trigger) {
1173 rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
1174 0x60);
1175 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1176 ("Trigger 92S Thermal Meter!!\n"));
1177 tm_trigger = 1;
1178 return;
1179 } else {
1180 RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
1181 ("Schedule TxPowerTracking direct call!!\n"));
1182 rtl92c_dm_txpower_tracking_directcall(hw);
1183 tm_trigger = 0;
1184 }
1185}
1186
1187void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
1188{
1189 rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
1190}
1191
1192void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
1193{
1194 struct rtl_priv *rtlpriv = rtl_priv(hw);
1195 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1196
1197 p_ra->ratr_state = DM_RATR_STA_INIT;
1198 p_ra->pre_ratr_state = DM_RATR_STA_INIT;
1199
1200 if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
1201 rtlpriv->dm.b_useramask = true;
1202 else
1203 rtlpriv->dm.b_useramask = false;
1204
1205}
1206
1207static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
1208{
1209 struct rtl_priv *rtlpriv = rtl_priv(hw);
1210 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1211 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1212 struct rate_adaptive *p_ra = &(rtlpriv->ra);
1213 u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
1214
1215 if (is_hal_stop(rtlhal)) {
1216 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1217 ("<---- driver is going to unload\n"));
1218 return;
1219 }
1220
1221 if (!rtlpriv->dm.b_useramask) {
1222 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1223 ("<---- driver does not control rate adaptive mask\n"));
1224 return;
1225 }
1226
1227 if (mac->link_state == MAC80211_LINKED) {
1228
1229 switch (p_ra->pre_ratr_state) {
1230 case DM_RATR_STA_HIGH:
1231 high_rssithresh_for_ra = 50;
1232 low_rssithresh_for_ra = 20;
1233 break;
1234 case DM_RATR_STA_MIDDLE:
1235 high_rssithresh_for_ra = 55;
1236 low_rssithresh_for_ra = 20;
1237 break;
1238 case DM_RATR_STA_LOW:
1239 high_rssithresh_for_ra = 50;
1240 low_rssithresh_for_ra = 25;
1241 break;
1242 default:
1243 high_rssithresh_for_ra = 50;
1244 low_rssithresh_for_ra = 20;
1245 break;
1246 }
1247
1248 if (rtlpriv->dm.undecorated_smoothed_pwdb >
1249 (long)high_rssithresh_for_ra)
1250 p_ra->ratr_state = DM_RATR_STA_HIGH;
1251 else if (rtlpriv->dm.undecorated_smoothed_pwdb >
1252 (long)low_rssithresh_for_ra)
1253 p_ra->ratr_state = DM_RATR_STA_MIDDLE;
1254 else
1255 p_ra->ratr_state = DM_RATR_STA_LOW;
1256
1257 if (p_ra->pre_ratr_state != p_ra->ratr_state) {
1258 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1259 ("RSSI = %ld\n",
1260 rtlpriv->dm.undecorated_smoothed_pwdb));
1261 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1262 ("RSSI_LEVEL = %d\n", p_ra->ratr_state));
1263 RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
1264 ("PreState = %d, CurState = %d\n",
1265 p_ra->pre_ratr_state, p_ra->ratr_state));
1266
1267 rtlpriv->cfg->ops->update_rate_mask(hw,
1268 p_ra->ratr_state);
1269
1270 p_ra->pre_ratr_state = p_ra->ratr_state;
1271 }
1272 }
1273}
1274
1275static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1276{
1277 dm_pstable.pre_ccastate = CCA_MAX;
1278 dm_pstable.cur_ccasate = CCA_MAX;
1279 dm_pstable.pre_rfstate = RF_MAX;
1280 dm_pstable.cur_rfstate = RF_MAX;
1281 dm_pstable.rssi_val_min = 0;
1282}
1283
1284static void rtl92c_dm_1r_cca(struct ieee80211_hw *hw)
1285{
1286 struct rtl_priv *rtlpriv = rtl_priv(hw);
1287 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1288
1289 if (dm_pstable.rssi_val_min != 0) {
1290 if (dm_pstable.pre_ccastate == CCA_2R) {
1291 if (dm_pstable.rssi_val_min >= 35)
1292 dm_pstable.cur_ccasate = CCA_1R;
1293 else
1294 dm_pstable.cur_ccasate = CCA_2R;
1295 } else {
1296 if (dm_pstable.rssi_val_min <= 30)
1297 dm_pstable.cur_ccasate = CCA_2R;
1298 else
1299 dm_pstable.cur_ccasate = CCA_1R;
1300 }
1301 } else {
1302 dm_pstable.cur_ccasate = CCA_MAX;
1303 }
1304
1305 if (dm_pstable.pre_ccastate != dm_pstable.cur_ccasate) {
1306 if (dm_pstable.cur_ccasate == CCA_1R) {
1307 if (get_rf_type(rtlphy) == RF_2T2R) {
1308 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
1309 MASKBYTE0, 0x13);
1310 rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x20);
1311 } else {
1312 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
1313 MASKBYTE0, 0x23);
1314 rtl_set_bbreg(hw, 0xe70, 0x7fc00000, 0x10c);
1315 }
1316 } else {
1317 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0,
1318 0x33);
1319 rtl_set_bbreg(hw, 0xe70, MASKBYTE3, 0x63);
1320 }
1321 dm_pstable.pre_ccastate = dm_pstable.cur_ccasate;
1322 }
1323
1324 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, ("CCAStage = %s\n",
1325 (dm_pstable.cur_ccasate ==
1326 0) ? "1RCCA" : "2RCCA"));
1327}
1328
1329void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
1330{
1331 static u8 initialize;
1332 static u32 reg_874, reg_c70, reg_85c, reg_a74;
1333
1334 if (initialize == 0) {
1335 reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1336 MASKDWORD) & 0x1CC000) >> 14;
1337
1338 reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
1339 MASKDWORD) & BIT(3)) >> 3;
1340
1341 reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1342 MASKDWORD) & 0xFF000000) >> 24;
1343
1344 reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
1345
1346 initialize = 1;
1347 }
1348
1349 if (!bforce_in_normal) {
1350 if (dm_pstable.rssi_val_min != 0) {
1351 if (dm_pstable.pre_rfstate == RF_NORMAL) {
1352 if (dm_pstable.rssi_val_min >= 30)
1353 dm_pstable.cur_rfstate = RF_SAVE;
1354 else
1355 dm_pstable.cur_rfstate = RF_NORMAL;
1356 } else {
1357 if (dm_pstable.rssi_val_min <= 25)
1358 dm_pstable.cur_rfstate = RF_NORMAL;
1359 else
1360 dm_pstable.cur_rfstate = RF_SAVE;
1361 }
1362 } else {
1363 dm_pstable.cur_rfstate = RF_MAX;
1364 }
1365 } else {
1366 dm_pstable.cur_rfstate = RF_NORMAL;
1367 }
1368
1369 if (dm_pstable.pre_rfstate != dm_pstable.cur_rfstate) {
1370 if (dm_pstable.cur_rfstate == RF_SAVE) {
1371 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1372 0x1C0000, 0x2);
1373 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
1374 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
1375 0xFF000000, 0x63);
1376 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1377 0xC000, 0x2);
1378 rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
1379 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1380 rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
1381 } else {
1382 rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
1383 0x1CC000, reg_874);
1384 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
1385 reg_c70);
1386 rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
1387 reg_85c);
1388 rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
1389 rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
1390 }
1391
1392 dm_pstable.pre_rfstate = dm_pstable.cur_rfstate;
1393 }
1394}
1395
1396static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
1397{
1398 struct rtl_priv *rtlpriv = rtl_priv(hw);
1399 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1400 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1401
1402 if (((mac->link_state == MAC80211_NOLINK)) &&
1403 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
1404 dm_pstable.rssi_val_min = 0;
1405 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1406 ("Not connected to any\n"));
1407 }
1408
1409 if (mac->link_state == MAC80211_LINKED) {
1410 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1411 dm_pstable.rssi_val_min =
1412 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1413 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1414 ("AP Client PWDB = 0x%lx\n",
1415 dm_pstable.rssi_val_min));
1416 } else {
1417 dm_pstable.rssi_val_min =
1418 rtlpriv->dm.undecorated_smoothed_pwdb;
1419 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1420 ("STA Default Port PWDB = 0x%lx\n",
1421 dm_pstable.rssi_val_min));
1422 }
1423 } else {
1424 dm_pstable.rssi_val_min =
1425 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
1426
1427 RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
1428 ("AP Ext Port PWDB = 0x%lx\n",
1429 dm_pstable.rssi_val_min));
1430 }
1431
1432 if (IS_92C_SERIAL(rtlhal->version))
1433 rtl92c_dm_1r_cca(hw);
1434}
1435
1436void rtl92c_dm_init(struct ieee80211_hw *hw)
1437{
1438 struct rtl_priv *rtlpriv = rtl_priv(hw);
1439
1440 rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
1441 rtl92c_dm_diginit(hw);
1442 rtl92c_dm_init_dynamic_txpower(hw);
1443 rtl92c_dm_init_edca_turbo(hw);
1444 rtl92c_dm_init_rate_adaptive_mask(hw);
1445 rtl92c_dm_initialize_txpower_tracking(hw);
1446 rtl92c_dm_init_dynamic_bb_powersaving(hw);
1447}
1448
1449void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
1450{
1451 struct rtl_priv *rtlpriv = rtl_priv(hw);
1452 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1453 bool b_fw_current_inpsmode = false;
1454 bool b_fw_ps_awake = true;
1455
1456 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
1457 (u8 *) (&b_fw_current_inpsmode));
1458 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
1459 (u8 *) (&b_fw_ps_awake));
1460
1461 if ((ppsc->rfpwr_state == ERFON) && ((!b_fw_current_inpsmode) &&
1462 b_fw_ps_awake)
1463 && (!ppsc->rfchange_inprogress)) {
1464 rtl92c_dm_pwdb_monitor(hw);
1465 rtl92c_dm_dig(hw);
1466 rtl92c_dm_false_alarm_counter_statistics(hw);
1467 rtl92c_dm_dynamic_bb_powersaving(hw);
1468 rtl92c_dm_dynamic_txpower(hw);
1469 rtl92c_dm_check_txpower_tracking(hw);
1470 rtl92c_dm_refresh_rate_adaptive_mask(hw);
1471 rtl92c_dm_check_edca_turbo(hw);
1472 }
1473}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/dm.h b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.h
index 463439e4074c..36302ebae4a3 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/dm.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/dm.h
@@ -192,5 +192,6 @@ void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw);
192void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw); 192void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw);
193void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw); 193void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
194void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal); 194void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
195void rtl92ce_dm_dynamic_txpower(struct ieee80211_hw *hw);
195 196
196#endif 197#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
index 1c41a0c93506..05477f465a75 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.c
@@ -37,7 +37,6 @@
37#include "def.h" 37#include "def.h"
38#include "phy.h" 38#include "phy.h"
39#include "dm.h" 39#include "dm.h"
40#include "fw.h"
41#include "led.h" 40#include "led.h"
42#include "hw.h" 41#include "hw.h"
43 42
@@ -124,7 +123,7 @@ void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
124 break; 123 break;
125 } 124 }
126 case HW_VAR_FW_PSMODE_STATUS: 125 case HW_VAR_FW_PSMODE_STATUS:
127 *((bool *) (val)) = ppsc->b_fw_current_inpsmode; 126 *((bool *) (val)) = ppsc->fw_current_inpsmode;
128 break; 127 break;
129 case HW_VAR_CORRECT_TSF:{ 128 case HW_VAR_CORRECT_TSF:{
130 u64 tsf; 129 u64 tsf;
@@ -173,15 +172,15 @@ void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
173 break; 172 break;
174 } 173 }
175 case HW_VAR_BASIC_RATE:{ 174 case HW_VAR_BASIC_RATE:{
176 u16 b_rate_cfg = ((u16 *) val)[0]; 175 u16 rate_cfg = ((u16 *) val)[0];
177 u8 rate_index = 0; 176 u8 rate_index = 0;
178 b_rate_cfg = b_rate_cfg & 0x15f; 177 rate_cfg &= 0x15f;
179 b_rate_cfg |= 0x01; 178 rate_cfg |= 0x01;
180 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff); 179 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
181 rtl_write_byte(rtlpriv, REG_RRSR + 1, 180 rtl_write_byte(rtlpriv, REG_RRSR + 1,
182 (b_rate_cfg >> 8)&0xff); 181 (rate_cfg >> 8)&0xff);
183 while (b_rate_cfg > 0x1) { 182 while (rate_cfg > 0x1) {
184 b_rate_cfg = (b_rate_cfg >> 1); 183 rate_cfg = (rate_cfg >> 1);
185 rate_index++; 184 rate_index++;
186 } 185 }
187 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 186 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
@@ -318,15 +317,17 @@ void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
318 } 317 }
319 case HW_VAR_AC_PARAM:{ 318 case HW_VAR_AC_PARAM:{
320 u8 e_aci = *((u8 *) val); 319 u8 e_aci = *((u8 *) val);
321 u32 u4b_ac_param = 0; 320 u32 u4b_ac_param;
321 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
322 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
323 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
322 324
323 u4b_ac_param |= (u32) mac->ac[e_aci].aifs; 325 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
324 u4b_ac_param |= ((u32) mac->ac[e_aci].cw_min 326 u4b_ac_param |= ((u32)cw_min
325 & 0xF) << AC_PARAM_ECW_MIN_OFFSET; 327 & 0xF) << AC_PARAM_ECW_MIN_OFFSET;
326 u4b_ac_param |= ((u32) mac->ac[e_aci].cw_max & 328 u4b_ac_param |= ((u32)cw_max &
327 0xF) << AC_PARAM_ECW_MAX_OFFSET; 329 0xF) << AC_PARAM_ECW_MAX_OFFSET;
328 u4b_ac_param |= (u32) mac->ac[e_aci].tx_op 330 u4b_ac_param |= (u32)tx_op << AC_PARAM_TXOP_OFFSET;
329 << AC_PARAM_TXOP_LIMIT_OFFSET;
330 331
331 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, 332 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
332 ("queue:%x, ac_param:%x\n", e_aci, 333 ("queue:%x, ac_param:%x\n", e_aci,
@@ -469,12 +470,12 @@ void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
469 break; 470 break;
470 } 471 }
471 case HW_VAR_FW_PSMODE_STATUS: 472 case HW_VAR_FW_PSMODE_STATUS:
472 ppsc->b_fw_current_inpsmode = *((bool *) val); 473 ppsc->fw_current_inpsmode = *((bool *) val);
473 break; 474 break;
474 case HW_VAR_H2C_FW_JOINBSSRPT:{ 475 case HW_VAR_H2C_FW_JOINBSSRPT:{
475 u8 mstatus = (*(u8 *) val); 476 u8 mstatus = (*(u8 *) val);
476 u8 tmp_regcr, tmp_reg422; 477 u8 tmp_regcr, tmp_reg422;
477 bool b_recover = false; 478 bool recover = false;
478 479
479 if (mstatus == RT_MEDIA_CONNECT) { 480 if (mstatus == RT_MEDIA_CONNECT) {
480 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, 481 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
@@ -491,7 +492,7 @@ void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
491 rtl_read_byte(rtlpriv, 492 rtl_read_byte(rtlpriv,
492 REG_FWHW_TXQ_CTRL + 2); 493 REG_FWHW_TXQ_CTRL + 2);
493 if (tmp_reg422 & BIT(6)) 494 if (tmp_reg422 & BIT(6))
494 b_recover = true; 495 recover = true;
495 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, 496 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
496 tmp_reg422 & (~BIT(6))); 497 tmp_reg422 & (~BIT(6)));
497 498
@@ -500,7 +501,7 @@ void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
500 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0); 501 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
501 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4)); 502 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
502 503
503 if (b_recover) { 504 if (recover) {
504 rtl_write_byte(rtlpriv, 505 rtl_write_byte(rtlpriv,
505 REG_FWHW_TXQ_CTRL + 2, 506 REG_FWHW_TXQ_CTRL + 2,
506 tmp_reg422); 507 tmp_reg422);
@@ -868,7 +869,7 @@ static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
868 rtl_write_word(rtlpriv, 0x350, 0x870c); 869 rtl_write_word(rtlpriv, 0x350, 0x870c);
869 rtl_write_byte(rtlpriv, 0x352, 0x1); 870 rtl_write_byte(rtlpriv, 0x352, 0x1);
870 871
871 if (ppsc->b_support_backdoor) 872 if (ppsc->support_backdoor)
872 rtl_write_byte(rtlpriv, 0x349, 0x1b); 873 rtl_write_byte(rtlpriv, 0x349, 0x1b);
873 else 874 else
874 rtl_write_byte(rtlpriv, 0x349, 0x03); 875 rtl_write_byte(rtlpriv, 0x349, 0x03);
@@ -940,15 +941,15 @@ int rtl92ce_hw_init(struct ieee80211_hw *hw)
940 ("Failed to download FW. Init HW " 941 ("Failed to download FW. Init HW "
941 "without FW now..\n")); 942 "without FW now..\n"));
942 err = 1; 943 err = 1;
943 rtlhal->bfw_ready = false; 944 rtlhal->fw_ready = false;
944 return err; 945 return err;
945 } else { 946 } else {
946 rtlhal->bfw_ready = true; 947 rtlhal->fw_ready = true;
947 } 948 }
948 949
949 rtlhal->last_hmeboxnum = 0; 950 rtlhal->last_hmeboxnum = 0;
950 rtl92c_phy_mac_config(hw); 951 rtl92ce_phy_mac_config(hw);
951 rtl92c_phy_bb_config(hw); 952 rtl92ce_phy_bb_config(hw);
952 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE; 953 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
953 rtl92c_phy_rf_config(hw); 954 rtl92c_phy_rf_config(hw);
954 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0, 955 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
@@ -1170,21 +1171,20 @@ void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1170{ 1171{
1171 struct rtl_priv *rtlpriv = rtl_priv(hw); 1172 struct rtl_priv *rtlpriv = rtl_priv(hw);
1172 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1173 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1173
1174 u32 u4b_ac_param; 1174 u32 u4b_ac_param;
1175 u16 cw_min = le16_to_cpu(mac->ac[aci].cw_min);
1176 u16 cw_max = le16_to_cpu(mac->ac[aci].cw_max);
1177 u16 tx_op = le16_to_cpu(mac->ac[aci].tx_op);
1175 1178
1176 rtl92c_dm_init_edca_turbo(hw); 1179 rtl92c_dm_init_edca_turbo(hw);
1177
1178 u4b_ac_param = (u32) mac->ac[aci].aifs; 1180 u4b_ac_param = (u32) mac->ac[aci].aifs;
1179 u4b_ac_param |= 1181 u4b_ac_param |= (u32) ((cw_min & 0xF) << AC_PARAM_ECW_MIN_OFFSET);
1180 ((u32) mac->ac[aci].cw_min & 0xF) << AC_PARAM_ECW_MIN_OFFSET; 1182 u4b_ac_param |= (u32) ((cw_max & 0xF) << AC_PARAM_ECW_MAX_OFFSET);
1181 u4b_ac_param |= 1183 u4b_ac_param |= (u32) (tx_op << AC_PARAM_TXOP_OFFSET);
1182 ((u32) mac->ac[aci].cw_max & 0xF) << AC_PARAM_ECW_MAX_OFFSET;
1183 u4b_ac_param |= (u32) mac->ac[aci].tx_op << AC_PARAM_TXOP_LIMIT_OFFSET;
1184 RT_TRACE(rtlpriv, COMP_QOS, DBG_DMESG, 1184 RT_TRACE(rtlpriv, COMP_QOS, DBG_DMESG,
1185 ("queue:%x, ac_param:%x aifs:%x cwmin:%x cwmax:%x txop:%x\n", 1185 ("queue:%x, ac_param:%x aifs:%x cwmin:%x cwmax:%x txop:%x\n",
1186 aci, u4b_ac_param, mac->ac[aci].aifs, mac->ac[aci].cw_min, 1186 aci, u4b_ac_param, mac->ac[aci].aifs, cw_min,
1187 mac->ac[aci].cw_max, mac->ac[aci].tx_op)); 1187 cw_max, tx_op));
1188 switch (aci) { 1188 switch (aci) {
1189 case AC1_BK: 1189 case AC1_BK:
1190 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, u4b_ac_param); 1190 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, u4b_ac_param);
@@ -1237,7 +1237,7 @@ static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1237 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40); 1237 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1238 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2); 1238 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1239 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0); 1239 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1240 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->bfw_ready) 1240 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1241 rtl92c_firmware_selfreset(hw); 1241 rtl92c_firmware_selfreset(hw);
1242 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51); 1242 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1243 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00); 1243 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
@@ -1335,19 +1335,6 @@ void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1335 rtl92ce_enable_interrupt(hw); 1335 rtl92ce_enable_interrupt(hw);
1336} 1336}
1337 1337
1338static u8 _rtl92c_get_chnl_group(u8 chnl)
1339{
1340 u8 group;
1341
1342 if (chnl < 3)
1343 group = 0;
1344 else if (chnl < 9)
1345 group = 1;
1346 else
1347 group = 2;
1348 return group;
1349}
1350
1351static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw, 1338static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1352 bool autoload_fail, 1339 bool autoload_fail,
1353 u8 *hwinfo) 1340 u8 *hwinfo)
@@ -1568,7 +1555,7 @@ static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1568 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f); 1555 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1569 1556
1570 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail) 1557 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1571 rtlefuse->b_apk_thermalmeterignore = true; 1558 rtlefuse->apk_thermalmeterignore = true;
1572 1559
1573 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter; 1560 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1574 RTPRINT(rtlpriv, FINIT, INIT_TxPower, 1561 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
@@ -1625,7 +1612,7 @@ static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1625 1612
1626 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN]; 1613 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1627 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION]; 1614 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1628 rtlefuse->b_txpwr_fromeprom = true; 1615 rtlefuse->txpwr_fromeprom = true;
1629 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID]; 1616 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1630 1617
1631 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, 1618 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
@@ -1668,7 +1655,7 @@ static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1668 1655
1669 switch (rtlhal->oem_id) { 1656 switch (rtlhal->oem_id) {
1670 case RT_CID_819x_HP: 1657 case RT_CID_819x_HP:
1671 pcipriv->ledctl.bled_opendrain = true; 1658 pcipriv->ledctl.led_opendrain = true;
1672 break; 1659 break;
1673 case RT_CID_819x_Lenovo: 1660 case RT_CID_819x_Lenovo:
1674 case RT_CID_DEFAULT: 1661 case RT_CID_DEFAULT:
@@ -1693,10 +1680,10 @@ void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1693 1680
1694 rtlhal->version = _rtl92ce_read_chip_version(hw); 1681 rtlhal->version = _rtl92ce_read_chip_version(hw);
1695 if (get_rf_type(rtlphy) == RF_1T1R) 1682 if (get_rf_type(rtlphy) == RF_1T1R)
1696 rtlpriv->dm.brfpath_rxenable[0] = true; 1683 rtlpriv->dm.rfpath_rxenable[0] = true;
1697 else 1684 else
1698 rtlpriv->dm.brfpath_rxenable[0] = 1685 rtlpriv->dm.rfpath_rxenable[0] =
1699 rtlpriv->dm.brfpath_rxenable[1] = true; 1686 rtlpriv->dm.rfpath_rxenable[1] = true;
1700 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n", 1687 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
1701 rtlhal->version)); 1688 rtlhal->version));
1702 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR); 1689 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
@@ -1725,18 +1712,18 @@ void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw)
1725 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 1712 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1726 1713
1727 u32 ratr_value = (u32) mac->basic_rates; 1714 u32 ratr_value = (u32) mac->basic_rates;
1728 u8 *p_mcsrate = mac->mcs; 1715 u8 *mcsrate = mac->mcs;
1729 u8 ratr_index = 0; 1716 u8 ratr_index = 0;
1730 u8 b_nmode = mac->ht_enable; 1717 u8 nmode = mac->ht_enable;
1731 u8 mimo_ps = 1; 1718 u8 mimo_ps = 1;
1732 u16 shortgi_rate; 1719 u16 shortgi_rate;
1733 u32 tmp_ratr_value; 1720 u32 tmp_ratr_value;
1734 u8 b_curtxbw_40mhz = mac->bw_40; 1721 u8 curtxbw_40mhz = mac->bw_40;
1735 u8 b_curshortgi_40mhz = mac->sgi_40; 1722 u8 curshortgi_40mhz = mac->sgi_40;
1736 u8 b_curshortgi_20mhz = mac->sgi_20; 1723 u8 curshortgi_20mhz = mac->sgi_20;
1737 enum wireless_mode wirelessmode = mac->mode; 1724 enum wireless_mode wirelessmode = mac->mode;
1738 1725
1739 ratr_value |= EF2BYTE((*(u16 *) (p_mcsrate))) << 12; 1726 ratr_value |= ((*(u16 *) (mcsrate))) << 12;
1740 1727
1741 switch (wirelessmode) { 1728 switch (wirelessmode) {
1742 case WIRELESS_MODE_B: 1729 case WIRELESS_MODE_B:
@@ -1750,7 +1737,7 @@ void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw)
1750 break; 1737 break;
1751 case WIRELESS_MODE_N_24G: 1738 case WIRELESS_MODE_N_24G:
1752 case WIRELESS_MODE_N_5G: 1739 case WIRELESS_MODE_N_5G:
1753 b_nmode = 1; 1740 nmode = 1;
1754 if (mimo_ps == 0) { 1741 if (mimo_ps == 0) {
1755 ratr_value &= 0x0007F005; 1742 ratr_value &= 0x0007F005;
1756 } else { 1743 } else {
@@ -1776,9 +1763,8 @@ void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw)
1776 1763
1777 ratr_value &= 0x0FFFFFFF; 1764 ratr_value &= 0x0FFFFFFF;
1778 1765
1779 if (b_nmode && ((b_curtxbw_40mhz && 1766 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) || (!curtxbw_40mhz &&
1780 b_curshortgi_40mhz) || (!b_curtxbw_40mhz && 1767 curshortgi_20mhz))) {
1781 b_curshortgi_20mhz))) {
1782 1768
1783 ratr_value |= 0x10000000; 1769 ratr_value |= 0x10000000;
1784 tmp_ratr_value = (ratr_value >> 12); 1770 tmp_ratr_value = (ratr_value >> 12);
@@ -1806,11 +1792,11 @@ void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
1806 u32 ratr_bitmap = (u32) mac->basic_rates; 1792 u32 ratr_bitmap = (u32) mac->basic_rates;
1807 u8 *p_mcsrate = mac->mcs; 1793 u8 *p_mcsrate = mac->mcs;
1808 u8 ratr_index; 1794 u8 ratr_index;
1809 u8 b_curtxbw_40mhz = mac->bw_40; 1795 u8 curtxbw_40mhz = mac->bw_40;
1810 u8 b_curshortgi_40mhz = mac->sgi_40; 1796 u8 curshortgi_40mhz = mac->sgi_40;
1811 u8 b_curshortgi_20mhz = mac->sgi_20; 1797 u8 curshortgi_20mhz = mac->sgi_20;
1812 enum wireless_mode wirelessmode = mac->mode; 1798 enum wireless_mode wirelessmode = mac->mode;
1813 bool b_shortgi = false; 1799 bool shortgi = false;
1814 u8 rate_mask[5]; 1800 u8 rate_mask[5];
1815 u8 macid = 0; 1801 u8 macid = 0;
1816 u8 mimops = 1; 1802 u8 mimops = 1;
@@ -1852,7 +1838,7 @@ void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
1852 } else { 1838 } else {
1853 if (rtlphy->rf_type == RF_1T2R || 1839 if (rtlphy->rf_type == RF_1T2R ||
1854 rtlphy->rf_type == RF_1T1R) { 1840 rtlphy->rf_type == RF_1T1R) {
1855 if (b_curtxbw_40mhz) { 1841 if (curtxbw_40mhz) {
1856 if (rssi_level == 1) 1842 if (rssi_level == 1)
1857 ratr_bitmap &= 0x000f0000; 1843 ratr_bitmap &= 0x000f0000;
1858 else if (rssi_level == 2) 1844 else if (rssi_level == 2)
@@ -1868,7 +1854,7 @@ void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
1868 ratr_bitmap &= 0x000ff005; 1854 ratr_bitmap &= 0x000ff005;
1869 } 1855 }
1870 } else { 1856 } else {
1871 if (b_curtxbw_40mhz) { 1857 if (curtxbw_40mhz) {
1872 if (rssi_level == 1) 1858 if (rssi_level == 1)
1873 ratr_bitmap &= 0x0f0f0000; 1859 ratr_bitmap &= 0x0f0f0000;
1874 else if (rssi_level == 2) 1860 else if (rssi_level == 2)
@@ -1886,13 +1872,13 @@ void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
1886 } 1872 }
1887 } 1873 }
1888 1874
1889 if ((b_curtxbw_40mhz && b_curshortgi_40mhz) || 1875 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1890 (!b_curtxbw_40mhz && b_curshortgi_20mhz)) { 1876 (!curtxbw_40mhz && curshortgi_20mhz)) {
1891 1877
1892 if (macid == 0) 1878 if (macid == 0)
1893 b_shortgi = true; 1879 shortgi = true;
1894 else if (macid == 1) 1880 else if (macid == 1)
1895 b_shortgi = false; 1881 shortgi = false;
1896 } 1882 }
1897 break; 1883 break;
1898 default: 1884 default:
@@ -1906,9 +1892,9 @@ void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
1906 } 1892 }
1907 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, 1893 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1908 ("ratr_bitmap :%x\n", ratr_bitmap)); 1894 ("ratr_bitmap :%x\n", ratr_bitmap));
1909 *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) | 1895 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
1910 (ratr_index << 28)); 1896 (ratr_index << 28);
1911 rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80; 1897 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
1912 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, " 1898 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
1913 "ratr_val:%x, %x:%x:%x:%x:%x\n", 1899 "ratr_val:%x, %x:%x:%x:%x:%x\n",
1914 ratr_index, ratr_bitmap, 1900 ratr_index, ratr_bitmap,
@@ -1940,13 +1926,13 @@ bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
1940 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 1926 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1941 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate; 1927 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
1942 u8 u1tmp; 1928 u8 u1tmp;
1943 bool b_actuallyset = false; 1929 bool actuallyset = false;
1944 unsigned long flag; 1930 unsigned long flag;
1945 1931
1946 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter)) 1932 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
1947 return false; 1933 return false;
1948 1934
1949 if (ppsc->b_swrf_processing) 1935 if (ppsc->swrf_processing)
1950 return false; 1936 return false;
1951 1937
1952 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag); 1938 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
@@ -1972,24 +1958,24 @@ bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
1972 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL); 1958 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1973 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF; 1959 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
1974 1960
1975 if ((ppsc->b_hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) { 1961 if ((ppsc->hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
1976 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 1962 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1977 ("GPIOChangeRF - HW Radio ON, RF ON\n")); 1963 ("GPIOChangeRF - HW Radio ON, RF ON\n"));
1978 1964
1979 e_rfpowerstate_toset = ERFON; 1965 e_rfpowerstate_toset = ERFON;
1980 ppsc->b_hwradiooff = false; 1966 ppsc->hwradiooff = false;
1981 b_actuallyset = true; 1967 actuallyset = true;
1982 } else if ((ppsc->b_hwradiooff == false) 1968 } else if ((ppsc->hwradiooff == false)
1983 && (e_rfpowerstate_toset == ERFOFF)) { 1969 && (e_rfpowerstate_toset == ERFOFF)) {
1984 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG, 1970 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1985 ("GPIOChangeRF - HW Radio OFF, RF OFF\n")); 1971 ("GPIOChangeRF - HW Radio OFF, RF OFF\n"));
1986 1972
1987 e_rfpowerstate_toset = ERFOFF; 1973 e_rfpowerstate_toset = ERFOFF;
1988 ppsc->b_hwradiooff = true; 1974 ppsc->hwradiooff = true;
1989 b_actuallyset = true; 1975 actuallyset = true;
1990 } 1976 }
1991 1977
1992 if (b_actuallyset) { 1978 if (actuallyset) {
1993 if (e_rfpowerstate_toset == ERFON) { 1979 if (e_rfpowerstate_toset == ERFON) {
1994 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) && 1980 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
1995 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) { 1981 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) {
@@ -2028,7 +2014,7 @@ bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2028 } 2014 }
2029 2015
2030 *valid = 1; 2016 *valid = 1;
2031 return !ppsc->b_hwradiooff; 2017 return !ppsc->hwradiooff;
2032 2018
2033} 2019}
2034 2020
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.h b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.h
index 305c819c8c78..a3dfdb635168 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/hw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/hw.h
@@ -30,6 +30,8 @@
30#ifndef __RTL92CE_HW_H__ 30#ifndef __RTL92CE_HW_H__
31#define __RTL92CE_HW_H__ 31#define __RTL92CE_HW_H__
32 32
33#define H2C_RA_MASK 6
34
33void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val); 35void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
34void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw); 36void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw);
35void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw, 37void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
@@ -53,5 +55,14 @@ void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw);
53void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index, 55void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
54 u8 *p_macaddr, bool is_group, u8 enc_algo, 56 u8 *p_macaddr, bool is_group, u8 enc_algo,
55 bool is_wepkey, bool clear_all); 57 bool is_wepkey, bool clear_all);
58bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
59void rtl92c_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
60void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
61void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
62int rtl92c_download_fw(struct ieee80211_hw *hw);
63void rtl92c_firmware_selfreset(struct ieee80211_hw *hw);
64void rtl92c_fill_h2c_cmd(struct ieee80211_hw *hw,
65 u8 element_id, u32 cmd_len, u8 *p_cmdbuffer);
66bool rtl92ce_phy_mac_config(struct ieee80211_hw *hw);
56 67
57#endif 68#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/led.c b/drivers/net/wireless/rtlwifi/rtl8192ce/led.c
index 78a0569208ea..7b1da8d7508f 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/led.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/led.c
@@ -57,7 +57,7 @@ void rtl92ce_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
57 ("switch case not process\n")); 57 ("switch case not process\n"));
58 break; 58 break;
59 } 59 }
60 pled->b_ledon = true; 60 pled->ledon = true;
61} 61}
62 62
63void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled) 63void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
@@ -76,7 +76,7 @@ void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
76 break; 76 break;
77 case LED_PIN_LED0: 77 case LED_PIN_LED0:
78 ledcfg &= 0xf0; 78 ledcfg &= 0xf0;
79 if (pcipriv->ledctl.bled_opendrain == true) 79 if (pcipriv->ledctl.led_opendrain == true)
80 rtl_write_byte(rtlpriv, REG_LEDCFG2, 80 rtl_write_byte(rtlpriv, REG_LEDCFG2,
81 (ledcfg | BIT(1) | BIT(5) | BIT(6))); 81 (ledcfg | BIT(1) | BIT(5) | BIT(6)));
82 else 82 else
@@ -92,7 +92,7 @@ void rtl92ce_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
92 ("switch case not process\n")); 92 ("switch case not process\n"));
93 break; 93 break;
94 } 94 }
95 pled->b_ledon = false; 95 pled->ledon = false;
96} 96}
97 97
98void rtl92ce_init_sw_leds(struct ieee80211_hw *hw) 98void rtl92ce_init_sw_leds(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
index 45044117139a..d0541e8c6012 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.c
@@ -32,89 +32,13 @@
32#include "../ps.h" 32#include "../ps.h"
33#include "reg.h" 33#include "reg.h"
34#include "def.h" 34#include "def.h"
35#include "hw.h"
35#include "phy.h" 36#include "phy.h"
36#include "rf.h" 37#include "rf.h"
37#include "dm.h" 38#include "dm.h"
38#include "table.h" 39#include "table.h"
39 40
40static u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw, 41u32 rtl92ce_phy_query_rf_reg(struct ieee80211_hw *hw,
41 enum radio_path rfpath, u32 offset);
42static void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
43 enum radio_path rfpath, u32 offset,
44 u32 data);
45static u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
46 enum radio_path rfpath, u32 offset);
47static void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
48 enum radio_path rfpath, u32 offset,
49 u32 data);
50static u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
51static bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
52static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
53static bool _rtl92c_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
54 u8 configtype);
55static bool _rtl92c_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
56 u8 configtype);
57static void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
58static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
59 u32 cmdtableidx, u32 cmdtablesz,
60 enum swchnlcmd_id cmdid, u32 para1,
61 u32 para2, u32 msdelay);
62static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
63 u8 channel, u8 *stage, u8 *step,
64 u32 *delay);
65static u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
66 enum wireless_mode wirelessmode,
67 long power_indbm);
68static bool _rtl92c_phy_config_rf_external_pa(struct ieee80211_hw *hw,
69 enum radio_path rfpath);
70static long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
71 enum wireless_mode wirelessmode,
72 u8 txpwridx);
73u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
74{
75 struct rtl_priv *rtlpriv = rtl_priv(hw);
76 u32 returnvalue, originalvalue, bitshift;
77
78 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
79 "bitmask(%#x)\n", regaddr,
80 bitmask));
81 originalvalue = rtl_read_dword(rtlpriv, regaddr);
82 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
83 returnvalue = (originalvalue & bitmask) >> bitshift;
84
85 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("BBR MASK=0x%x "
86 "Addr[0x%x]=0x%x\n", bitmask,
87 regaddr, originalvalue));
88
89 return returnvalue;
90
91}
92
93void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
94 u32 regaddr, u32 bitmask, u32 data)
95{
96 struct rtl_priv *rtlpriv = rtl_priv(hw);
97 u32 originalvalue, bitshift;
98
99 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
100 " data(%#x)\n", regaddr, bitmask,
101 data));
102
103 if (bitmask != MASKDWORD) {
104 originalvalue = rtl_read_dword(rtlpriv, regaddr);
105 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
106 data = ((originalvalue & (~bitmask)) | (data << bitshift));
107 }
108
109 rtl_write_dword(rtlpriv, regaddr, data);
110
111 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), bitmask(%#x),"
112 " data(%#x)\n", regaddr, bitmask,
113 data));
114
115}
116
117u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
118 enum radio_path rfpath, u32 regaddr, u32 bitmask) 42 enum radio_path rfpath, u32 regaddr, u32 bitmask)
119{ 43{
120 struct rtl_priv *rtlpriv = rtl_priv(hw); 44 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -149,7 +73,7 @@ u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
149 return readback_value; 73 return readback_value;
150} 74}
151 75
152void rtl92c_phy_set_rf_reg(struct ieee80211_hw *hw, 76void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
153 enum radio_path rfpath, 77 enum radio_path rfpath,
154 u32 regaddr, u32 bitmask, u32 data) 78 u32 regaddr, u32 bitmask, u32 data)
155{ 79{
@@ -197,137 +121,25 @@ void rtl92c_phy_set_rf_reg(struct ieee80211_hw *hw,
197 bitmask, data, rfpath)); 121 bitmask, data, rfpath));
198} 122}
199 123
200static u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw, 124bool rtl92ce_phy_mac_config(struct ieee80211_hw *hw)
201 enum radio_path rfpath, u32 offset)
202{
203 RT_ASSERT(false, ("deprecated!\n"));
204 return 0;
205}
206
207static void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
208 enum radio_path rfpath, u32 offset,
209 u32 data)
210{
211 RT_ASSERT(false, ("deprecated!\n"));
212}
213
214static u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
215 enum radio_path rfpath, u32 offset)
216{
217 struct rtl_priv *rtlpriv = rtl_priv(hw);
218 struct rtl_phy *rtlphy = &(rtlpriv->phy);
219 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
220 u32 newoffset;
221 u32 tmplong, tmplong2;
222 u8 rfpi_enable = 0;
223 u32 retvalue;
224
225 offset &= 0x3f;
226 newoffset = offset;
227 if (RT_CANNOT_IO(hw)) {
228 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("return all one\n"));
229 return 0xFFFFFFFF;
230 }
231 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
232 if (rfpath == RF90_PATH_A)
233 tmplong2 = tmplong;
234 else
235 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
236 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
237 (newoffset << 23) | BLSSIREADEDGE;
238 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
239 tmplong & (~BLSSIREADEDGE));
240 mdelay(1);
241 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
242 mdelay(1);
243 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
244 tmplong | BLSSIREADEDGE);
245 mdelay(1);
246 if (rfpath == RF90_PATH_A)
247 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
248 BIT(8));
249 else if (rfpath == RF90_PATH_B)
250 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
251 BIT(8));
252 if (rfpi_enable)
253 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readbackpi,
254 BLSSIREADBACKDATA);
255 else
256 retvalue = rtl_get_bbreg(hw, pphyreg->rflssi_readback,
257 BLSSIREADBACKDATA);
258 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFR-%d Addr[0x%x]=0x%x\n",
259 rfpath, pphyreg->rflssi_readback,
260 retvalue));
261 return retvalue;
262}
263
264static void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
265 enum radio_path rfpath, u32 offset,
266 u32 data)
267{
268 u32 data_and_addr;
269 u32 newoffset;
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_phy *rtlphy = &(rtlpriv->phy);
272 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
273
274 if (RT_CANNOT_IO(hw)) {
275 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("stop\n"));
276 return;
277 }
278 offset &= 0x3f;
279 newoffset = offset;
280 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
281 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
282 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("RFW-%d Addr[0x%x]=0x%x\n",
283 rfpath, pphyreg->rf3wire_offset,
284 data_and_addr));
285}
286
287static u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
288{
289 u32 i;
290
291 for (i = 0; i <= 31; i++) {
292 if (((bitmask >> i) & 0x1) == 1)
293 break;
294 }
295 return i;
296}
297
298static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
299{
300 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
301 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
302 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
303 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
304 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
305 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
306 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
307 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
308 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
309 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
310}
311
312bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
313{ 125{
314 struct rtl_priv *rtlpriv = rtl_priv(hw); 126 struct rtl_priv *rtlpriv = rtl_priv(hw);
315 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 127 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
316 bool is92c = IS_92C_SERIAL(rtlhal->version); 128 bool is92c = IS_92C_SERIAL(rtlhal->version);
317 bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw); 129 bool rtstatus = _rtl92ce_phy_config_mac_with_headerfile(hw);
318 130
319 if (is92c) 131 if (is92c)
320 rtl_write_byte(rtlpriv, 0x14, 0x71); 132 rtl_write_byte(rtlpriv, 0x14, 0x71);
321 return rtstatus; 133 return rtstatus;
322} 134}
323 135
324bool rtl92c_phy_bb_config(struct ieee80211_hw *hw) 136bool rtl92ce_phy_bb_config(struct ieee80211_hw *hw)
325{ 137{
326 bool rtstatus = true; 138 bool rtstatus = true;
327 struct rtl_priv *rtlpriv = rtl_priv(hw); 139 struct rtl_priv *rtlpriv = rtl_priv(hw);
328 u16 regval; 140 u16 regval;
329 u32 regvaldw; 141 u32 regvaldw;
330 u8 b_reg_hwparafile = 1; 142 u8 reg_hwparafile = 1;
331 143
332 _rtl92c_phy_init_bb_rf_register_definition(hw); 144 _rtl92c_phy_init_bb_rf_register_definition(hw);
333 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN); 145 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
@@ -342,56 +154,12 @@ bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
342 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80); 154 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
343 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0); 155 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
344 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23)); 156 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
345 if (b_reg_hwparafile == 1) 157 if (reg_hwparafile == 1)
346 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw); 158 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
347 return rtstatus; 159 return rtstatus;
348} 160}
349 161
350bool rtl92c_phy_rf_config(struct ieee80211_hw *hw) 162bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
351{
352 return rtl92c_phy_rf6052_config(hw);
353}
354
355static bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
356{
357 struct rtl_priv *rtlpriv = rtl_priv(hw);
358 struct rtl_phy *rtlphy = &(rtlpriv->phy);
359 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
360 bool rtstatus;
361
362 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("==>\n"));
363 rtstatus = _rtl92c_phy_config_bb_with_headerfile(hw,
364 BASEBAND_CONFIG_PHY_REG);
365 if (rtstatus != true) {
366 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Write BB Reg Fail!!"));
367 return false;
368 }
369 if (rtlphy->rf_type == RF_1T2R) {
370 _rtl92c_phy_bb_config_1t(hw);
371 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Config to 1T!!\n"));
372 }
373 if (rtlefuse->autoload_failflag == false) {
374 rtlphy->pwrgroup_cnt = 0;
375 rtstatus = _rtl92c_phy_config_bb_with_pgheaderfile(hw,
376 BASEBAND_CONFIG_PHY_REG);
377 }
378 if (rtstatus != true) {
379 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("BB_PG Reg Fail!!"));
380 return false;
381 }
382 rtstatus = _rtl92c_phy_config_bb_with_headerfile(hw,
383 BASEBAND_CONFIG_AGC_TAB);
384 if (rtstatus != true) {
385 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("AGC Table Fail\n"));
386 return false;
387 }
388 rtlphy->bcck_high_power = (bool) (rtl_get_bbreg(hw,
389 RFPGA0_XA_HSSIPARAMETER2,
390 0x200));
391 return true;
392}
393
394static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
395{ 163{
396 struct rtl_priv *rtlpriv = rtl_priv(hw); 164 struct rtl_priv *rtlpriv = rtl_priv(hw);
397 u32 i; 165 u32 i;
@@ -408,11 +176,7 @@ static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
408 return true; 176 return true;
409} 177}
410 178
411void rtl92c_phy_config_bb_external_pa(struct ieee80211_hw *hw) 179bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
412{
413}
414
415static bool _rtl92c_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
416 u8 configtype) 180 u8 configtype)
417{ 181{
418 int i; 182 int i;
@@ -456,7 +220,6 @@ static bool _rtl92c_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
456 phy_regarray_table[i], 220 phy_regarray_table[i],
457 phy_regarray_table[i + 1])); 221 phy_regarray_table[i + 1]));
458 } 222 }
459 rtl92c_phy_config_bb_external_pa(hw);
460 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) { 223 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
461 for (i = 0; i < agctab_arraylen; i = i + 2) { 224 for (i = 0; i < agctab_arraylen; i = i + 2) {
462 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD, 225 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
@@ -472,175 +235,7 @@ static bool _rtl92c_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
472 return true; 235 return true;
473} 236}
474 237
475static void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw, 238bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
476 u32 regaddr, u32 bitmask,
477 u32 data)
478{
479 struct rtl_priv *rtlpriv = rtl_priv(hw);
480 struct rtl_phy *rtlphy = &(rtlpriv->phy);
481
482 if (regaddr == RTXAGC_A_RATE18_06) {
483 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
484 data;
485 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
486 ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
487 rtlphy->pwrgroup_cnt,
488 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
489 pwrgroup_cnt][0]));
490 }
491 if (regaddr == RTXAGC_A_RATE54_24) {
492 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
493 data;
494 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
495 ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
496 rtlphy->pwrgroup_cnt,
497 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
498 pwrgroup_cnt][1]));
499 }
500 if (regaddr == RTXAGC_A_CCK1_MCS32) {
501 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
502 data;
503 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
504 ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
505 rtlphy->pwrgroup_cnt,
506 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
507 pwrgroup_cnt][6]));
508 }
509 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
510 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
511 data;
512 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
513 ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
514 rtlphy->pwrgroup_cnt,
515 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
516 pwrgroup_cnt][7]));
517 }
518 if (regaddr == RTXAGC_A_MCS03_MCS00) {
519 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
520 data;
521 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
522 ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
523 rtlphy->pwrgroup_cnt,
524 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
525 pwrgroup_cnt][2]));
526 }
527 if (regaddr == RTXAGC_A_MCS07_MCS04) {
528 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
529 data;
530 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
531 ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
532 rtlphy->pwrgroup_cnt,
533 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
534 pwrgroup_cnt][3]));
535 }
536 if (regaddr == RTXAGC_A_MCS11_MCS08) {
537 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
538 data;
539 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
540 ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
541 rtlphy->pwrgroup_cnt,
542 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
543 pwrgroup_cnt][4]));
544 }
545 if (regaddr == RTXAGC_A_MCS15_MCS12) {
546 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
547 data;
548 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
549 ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
550 rtlphy->pwrgroup_cnt,
551 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
552 pwrgroup_cnt][5]));
553 }
554 if (regaddr == RTXAGC_B_RATE18_06) {
555 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
556 data;
557 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
558 ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
559 rtlphy->pwrgroup_cnt,
560 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
561 pwrgroup_cnt][8]));
562 }
563 if (regaddr == RTXAGC_B_RATE54_24) {
564 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
565 data;
566
567 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
568 ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
569 rtlphy->pwrgroup_cnt,
570 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
571 pwrgroup_cnt][9]));
572 }
573
574 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
575 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
576 data;
577
578 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
579 ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
580 rtlphy->pwrgroup_cnt,
581 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
582 pwrgroup_cnt][14]));
583 }
584
585 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
586 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
587 data;
588
589 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
590 ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
591 rtlphy->pwrgroup_cnt,
592 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
593 pwrgroup_cnt][15]));
594 }
595
596 if (regaddr == RTXAGC_B_MCS03_MCS00) {
597 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
598 data;
599
600 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
601 ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
602 rtlphy->pwrgroup_cnt,
603 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
604 pwrgroup_cnt][10]));
605 }
606
607 if (regaddr == RTXAGC_B_MCS07_MCS04) {
608 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
609 data;
610
611 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
612 ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
613 rtlphy->pwrgroup_cnt,
614 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
615 pwrgroup_cnt][11]));
616 }
617
618 if (regaddr == RTXAGC_B_MCS11_MCS08) {
619 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
620 data;
621
622 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
623 ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
624 rtlphy->pwrgroup_cnt,
625 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
626 pwrgroup_cnt][12]));
627 }
628
629 if (regaddr == RTXAGC_B_MCS15_MCS12) {
630 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
631 data;
632
633 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
634 ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
635 rtlphy->pwrgroup_cnt,
636 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
637 pwrgroup_cnt][13]));
638
639 rtlphy->pwrgroup_cnt++;
640 }
641}
642
643static bool _rtl92c_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
644 u8 configtype) 239 u8 configtype)
645{ 240{
646 struct rtl_priv *rtlpriv = rtl_priv(hw); 241 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -679,13 +274,7 @@ static bool _rtl92c_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
679 return true; 274 return true;
680} 275}
681 276
682static bool _rtl92c_phy_config_rf_external_pa(struct ieee80211_hw *hw, 277bool rtl92ce_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
683 enum radio_path rfpath)
684{
685 return true;
686}
687
688bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
689 enum radio_path rfpath) 278 enum radio_path rfpath)
690{ 279{
691 280
@@ -740,7 +329,6 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
740 udelay(1); 329 udelay(1);
741 } 330 }
742 } 331 }
743 _rtl92c_phy_config_rf_external_pa(hw, rfpath);
744 break; 332 break;
745 case RF90_PATH_B: 333 case RF90_PATH_B:
746 for (i = 0; i < radiob_arraylen; i = i + 2) { 334 for (i = 0; i < radiob_arraylen; i = i + 2) {
@@ -776,346 +364,7 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
776 return true; 364 return true;
777} 365}
778 366
779void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw) 367void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
780{
781 struct rtl_priv *rtlpriv = rtl_priv(hw);
782 struct rtl_phy *rtlphy = &(rtlpriv->phy);
783
784 rtlphy->default_initialgain[0] =
785 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
786 rtlphy->default_initialgain[1] =
787 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
788 rtlphy->default_initialgain[2] =
789 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
790 rtlphy->default_initialgain[3] =
791 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
792
793 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
794 ("Default initial gain (c50=0x%x, "
795 "c58=0x%x, c60=0x%x, c68=0x%x\n",
796 rtlphy->default_initialgain[0],
797 rtlphy->default_initialgain[1],
798 rtlphy->default_initialgain[2],
799 rtlphy->default_initialgain[3]));
800
801 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
802 ROFDM0_RXDETECTOR3, MASKBYTE0);
803 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
804 ROFDM0_RXDETECTOR2, MASKDWORD);
805
806 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
807 ("Default framesync (0x%x) = 0x%x\n",
808 ROFDM0_RXDETECTOR3, rtlphy->framesync));
809}
810
811static void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
812{
813 struct rtl_priv *rtlpriv = rtl_priv(hw);
814 struct rtl_phy *rtlphy = &(rtlpriv->phy);
815
816 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
817 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
818 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
819 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
820
821 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
822 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
823 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
824 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
825
826 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
827 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
828
829 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
830 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
831
832 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
833 RFPGA0_XA_LSSIPARAMETER;
834 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
835 RFPGA0_XB_LSSIPARAMETER;
836
837 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
838 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
839 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
840 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
841
842 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
843 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
844 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
845 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
846
847 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
848 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
849
850 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
851 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
852
853 rtlphy->phyreg_def[RF90_PATH_A].rfswitch_control =
854 RFPGA0_XAB_SWITCHCONTROL;
855 rtlphy->phyreg_def[RF90_PATH_B].rfswitch_control =
856 RFPGA0_XAB_SWITCHCONTROL;
857 rtlphy->phyreg_def[RF90_PATH_C].rfswitch_control =
858 RFPGA0_XCD_SWITCHCONTROL;
859 rtlphy->phyreg_def[RF90_PATH_D].rfswitch_control =
860 RFPGA0_XCD_SWITCHCONTROL;
861
862 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
863 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
864 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
865 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
866
867 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
868 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
869 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
870 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
871
872 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbalance =
873 ROFDM0_XARXIQIMBALANCE;
874 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbalance =
875 ROFDM0_XBRXIQIMBALANCE;
876 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbalance =
877 ROFDM0_XCRXIQIMBANLANCE;
878 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbalance =
879 ROFDM0_XDRXIQIMBALANCE;
880
881 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
882 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
883 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
884 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
885
886 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbalance =
887 ROFDM0_XATXIQIMBALANCE;
888 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbalance =
889 ROFDM0_XBTXIQIMBALANCE;
890 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbalance =
891 ROFDM0_XCTXIQIMBALANCE;
892 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbalance =
893 ROFDM0_XDTXIQIMBALANCE;
894
895 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
896 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
897 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
898 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
899
900 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readback =
901 RFPGA0_XA_LSSIREADBACK;
902 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readback =
903 RFPGA0_XB_LSSIREADBACK;
904 rtlphy->phyreg_def[RF90_PATH_C].rflssi_readback =
905 RFPGA0_XC_LSSIREADBACK;
906 rtlphy->phyreg_def[RF90_PATH_D].rflssi_readback =
907 RFPGA0_XD_LSSIREADBACK;
908
909 rtlphy->phyreg_def[RF90_PATH_A].rflssi_readbackpi =
910 TRANSCEIVEA_HSPI_READBACK;
911 rtlphy->phyreg_def[RF90_PATH_B].rflssi_readbackpi =
912 TRANSCEIVEB_HSPI_READBACK;
913
914}
915
916void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
917{
918 struct rtl_priv *rtlpriv = rtl_priv(hw);
919 struct rtl_phy *rtlphy = &(rtlpriv->phy);
920 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
921 u8 txpwr_level;
922 long txpwr_dbm;
923
924 txpwr_level = rtlphy->cur_cck_txpwridx;
925 txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw,
926 WIRELESS_MODE_B, txpwr_level);
927 txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
928 rtlefuse->legacy_ht_txpowerdiff;
929 if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
930 WIRELESS_MODE_G,
931 txpwr_level) > txpwr_dbm)
932 txpwr_dbm =
933 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
934 txpwr_level);
935 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
936 if (_rtl92c_phy_txpwr_idx_to_dbm(hw,
937 WIRELESS_MODE_N_24G,
938 txpwr_level) > txpwr_dbm)
939 txpwr_dbm =
940 _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
941 txpwr_level);
942 *powerlevel = txpwr_dbm;
943}
944
945static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
946 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
947{
948 struct rtl_priv *rtlpriv = rtl_priv(hw);
949 struct rtl_phy *rtlphy = &(rtlpriv->phy);
950 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
951 u8 index = (channel - 1);
952
953 cckpowerlevel[RF90_PATH_A] =
954 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
955 cckpowerlevel[RF90_PATH_B] =
956 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
957 if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
958 ofdmpowerlevel[RF90_PATH_A] =
959 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
960 ofdmpowerlevel[RF90_PATH_B] =
961 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
962 } else if (get_rf_type(rtlphy) == RF_2T2R) {
963 ofdmpowerlevel[RF90_PATH_A] =
964 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
965 ofdmpowerlevel[RF90_PATH_B] =
966 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
967 }
968}
969
970static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
971 u8 channel, u8 *cckpowerlevel,
972 u8 *ofdmpowerlevel)
973{
974 struct rtl_priv *rtlpriv = rtl_priv(hw);
975 struct rtl_phy *rtlphy = &(rtlpriv->phy);
976
977 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
978 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
979}
980
981void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
982{
983 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
984 u8 cckpowerlevel[2], ofdmpowerlevel[2];
985
986 if (rtlefuse->b_txpwr_fromeprom == false)
987 return;
988 _rtl92c_get_txpower_index(hw, channel,
989 &cckpowerlevel[0], &ofdmpowerlevel[0]);
990 _rtl92c_ccxpower_index_check(hw,
991 channel, &cckpowerlevel[0],
992 &ofdmpowerlevel[0]);
993 rtl92c_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
994 rtl92c_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
995}
996
997bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
998{
999 struct rtl_priv *rtlpriv = rtl_priv(hw);
1000 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1001 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1002 u8 idx;
1003 u8 rf_path;
1004
1005 u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
1006 WIRELESS_MODE_B,
1007 power_indbm);
1008 u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_Idx(hw,
1009 WIRELESS_MODE_N_24G,
1010 power_indbm);
1011 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
1012 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
1013 else
1014 ofdmtxpwridx = 0;
1015 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
1016 ("%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
1017 power_indbm, ccktxpwridx, ofdmtxpwridx));
1018 for (idx = 0; idx < 14; idx++) {
1019 for (rf_path = 0; rf_path < 2; rf_path++) {
1020 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
1021 rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
1022 ofdmtxpwridx;
1023 rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
1024 ofdmtxpwridx;
1025 }
1026 }
1027 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1028 return true;
1029}
1030
1031void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw, u16 beaconinterval)
1032{
1033}
1034
1035static u8 _rtl92c_phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
1036 enum wireless_mode wirelessmode,
1037 long power_indbm)
1038{
1039 u8 txpwridx;
1040 long offset;
1041
1042 switch (wirelessmode) {
1043 case WIRELESS_MODE_B:
1044 offset = -7;
1045 break;
1046 case WIRELESS_MODE_G:
1047 case WIRELESS_MODE_N_24G:
1048 offset = -8;
1049 break;
1050 default:
1051 offset = -8;
1052 break;
1053 }
1054
1055 if ((power_indbm - offset) > 0)
1056 txpwridx = (u8) ((power_indbm - offset) * 2);
1057 else
1058 txpwridx = 0;
1059
1060 if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
1061 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
1062
1063 return txpwridx;
1064}
1065
1066static long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
1067 enum wireless_mode wirelessmode,
1068 u8 txpwridx)
1069{
1070 long offset;
1071 long pwrout_dbm;
1072
1073 switch (wirelessmode) {
1074 case WIRELESS_MODE_B:
1075 offset = -7;
1076 break;
1077 case WIRELESS_MODE_G:
1078 case WIRELESS_MODE_N_24G:
1079 offset = -8;
1080 break;
1081 default:
1082 offset = -8;
1083 break;
1084 }
1085 pwrout_dbm = txpwridx / 2 + offset;
1086 return pwrout_dbm;
1087}
1088
1089void rtl92c_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
1090{
1091 struct rtl_priv *rtlpriv = rtl_priv(hw);
1092 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1093 enum io_type iotype;
1094
1095 if (!is_hal_stop(rtlhal)) {
1096 switch (operation) {
1097 case SCAN_OPT_BACKUP:
1098 iotype = IO_CMD_PAUSE_DM_BY_SCAN;
1099 rtlpriv->cfg->ops->set_hw_reg(hw,
1100 HW_VAR_IO_CMD,
1101 (u8 *)&iotype);
1102
1103 break;
1104 case SCAN_OPT_RESTORE:
1105 iotype = IO_CMD_RESUME_DM_BY_SCAN;
1106 rtlpriv->cfg->ops->set_hw_reg(hw,
1107 HW_VAR_IO_CMD,
1108 (u8 *)&iotype);
1109 break;
1110 default:
1111 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1112 ("Unknown Scan Backup operation.\n"));
1113 break;
1114 }
1115 }
1116}
1117
1118void rtl92c_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1119{ 368{
1120 struct rtl_priv *rtlpriv = rtl_priv(hw); 369 struct rtl_priv *rtlpriv = rtl_priv(hw);
1121 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw)); 370 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
@@ -1183,645 +432,7 @@ void rtl92c_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
1183 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n")); 432 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
1184} 433}
1185 434
1186void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw, 435void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1187 enum nl80211_channel_type ch_type)
1188{
1189 struct rtl_priv *rtlpriv = rtl_priv(hw);
1190 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1191 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1192 u8 tmp_bw = rtlphy->current_chan_bw;
1193
1194 if (rtlphy->set_bwmode_inprogress)
1195 return;
1196 rtlphy->set_bwmode_inprogress = true;
1197 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw)))
1198 rtl92c_phy_set_bw_mode_callback(hw);
1199 else {
1200 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1201 ("FALSE driver sleep or unload\n"));
1202 rtlphy->set_bwmode_inprogress = false;
1203 rtlphy->current_chan_bw = tmp_bw;
1204 }
1205}
1206
1207void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
1208{
1209 struct rtl_priv *rtlpriv = rtl_priv(hw);
1210 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1211 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1212 u32 delay;
1213
1214 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
1215 ("switch to channel%d\n", rtlphy->current_channel));
1216 if (is_hal_stop(rtlhal))
1217 return;
1218 do {
1219 if (!rtlphy->sw_chnl_inprogress)
1220 break;
1221 if (!_rtl92c_phy_sw_chnl_step_by_step
1222 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
1223 &rtlphy->sw_chnl_step, &delay)) {
1224 if (delay > 0)
1225 mdelay(delay);
1226 else
1227 continue;
1228 } else
1229 rtlphy->sw_chnl_inprogress = false;
1230 break;
1231 } while (true);
1232 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
1233}
1234
1235u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
1236{
1237 struct rtl_priv *rtlpriv = rtl_priv(hw);
1238 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1239 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1240
1241 if (rtlphy->sw_chnl_inprogress)
1242 return 0;
1243 if (rtlphy->set_bwmode_inprogress)
1244 return 0;
1245 RT_ASSERT((rtlphy->current_channel <= 14),
1246 ("WIRELESS_MODE_G but channel>14"));
1247 rtlphy->sw_chnl_inprogress = true;
1248 rtlphy->sw_chnl_stage = 0;
1249 rtlphy->sw_chnl_step = 0;
1250 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
1251 rtl92c_phy_sw_chnl_callback(hw);
1252 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1253 ("sw_chnl_inprogress false schdule workitem\n"));
1254 rtlphy->sw_chnl_inprogress = false;
1255 } else {
1256 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
1257 ("sw_chnl_inprogress false driver sleep or"
1258 " unload\n"));
1259 rtlphy->sw_chnl_inprogress = false;
1260 }
1261 return 1;
1262}
1263
1264static bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
1265 u8 channel, u8 *stage, u8 *step,
1266 u32 *delay)
1267{
1268 struct rtl_priv *rtlpriv = rtl_priv(hw);
1269 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1270 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
1271 u32 precommoncmdcnt;
1272 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
1273 u32 postcommoncmdcnt;
1274 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
1275 u32 rfdependcmdcnt;
1276 struct swchnlcmd *currentcmd = NULL;
1277 u8 rfpath;
1278 u8 num_total_rfpath = rtlphy->num_total_rfpath;
1279
1280 precommoncmdcnt = 0;
1281 _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1282 MAX_PRECMD_CNT,
1283 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
1284 _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1285 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1286
1287 postcommoncmdcnt = 0;
1288
1289 _rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1290 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1291
1292 rfdependcmdcnt = 0;
1293
1294 RT_ASSERT((channel >= 1 && channel <= 14),
1295 ("illegal channel for Zebra: %d\n", channel));
1296
1297 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1298 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
1299 RF_CHNLBW, channel, 10);
1300
1301 _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1302 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
1303 0);
1304
1305 do {
1306 switch (*stage) {
1307 case 0:
1308 currentcmd = &precommoncmd[*step];
1309 break;
1310 case 1:
1311 currentcmd = &rfdependcmd[*step];
1312 break;
1313 case 2:
1314 currentcmd = &postcommoncmd[*step];
1315 break;
1316 }
1317
1318 if (currentcmd->cmdid == CMDID_END) {
1319 if ((*stage) == 2) {
1320 return true;
1321 } else {
1322 (*stage)++;
1323 (*step) = 0;
1324 continue;
1325 }
1326 }
1327
1328 switch (currentcmd->cmdid) {
1329 case CMDID_SET_TXPOWEROWER_LEVEL:
1330 rtl92c_phy_set_txpower_level(hw, channel);
1331 break;
1332 case CMDID_WRITEPORT_ULONG:
1333 rtl_write_dword(rtlpriv, currentcmd->para1,
1334 currentcmd->para2);
1335 break;
1336 case CMDID_WRITEPORT_USHORT:
1337 rtl_write_word(rtlpriv, currentcmd->para1,
1338 (u16) currentcmd->para2);
1339 break;
1340 case CMDID_WRITEPORT_UCHAR:
1341 rtl_write_byte(rtlpriv, currentcmd->para1,
1342 (u8) currentcmd->para2);
1343 break;
1344 case CMDID_RF_WRITEREG:
1345 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1346 rtlphy->rfreg_chnlval[rfpath] =
1347 ((rtlphy->rfreg_chnlval[rfpath] &
1348 0xfffffc00) | currentcmd->para2);
1349
1350 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1351 currentcmd->para1,
1352 RFREG_OFFSET_MASK,
1353 rtlphy->rfreg_chnlval[rfpath]);
1354 }
1355 break;
1356 default:
1357 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1358 ("switch case not process\n"));
1359 break;
1360 }
1361
1362 break;
1363 } while (true);
1364
1365 (*delay) = currentcmd->msdelay;
1366 (*step)++;
1367 return false;
1368}
1369
1370static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1371 u32 cmdtableidx, u32 cmdtablesz,
1372 enum swchnlcmd_id cmdid,
1373 u32 para1, u32 para2, u32 msdelay)
1374{
1375 struct swchnlcmd *pcmd;
1376
1377 if (cmdtable == NULL) {
1378 RT_ASSERT(false, ("cmdtable cannot be NULL.\n"));
1379 return false;
1380 }
1381
1382 if (cmdtableidx >= cmdtablesz)
1383 return false;
1384
1385 pcmd = cmdtable + cmdtableidx;
1386 pcmd->cmdid = cmdid;
1387 pcmd->para1 = para1;
1388 pcmd->para2 = para2;
1389 pcmd->msdelay = msdelay;
1390 return true;
1391}
1392
1393bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
1394{
1395 return true;
1396}
1397
1398static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1399{
1400 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
1401 u8 result = 0x00;
1402
1403 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1404 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1405 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1406 rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
1407 config_pathb ? 0x28160202 : 0x28160502);
1408
1409 if (config_pathb) {
1410 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1411 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1412 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1413 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
1414 }
1415
1416 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
1417 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1418 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1419
1420 mdelay(IQK_DELAY_TIME);
1421
1422 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1423 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1424 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1425 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1426
1427 if (!(reg_eac & BIT(28)) &&
1428 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1429 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1430 result |= 0x01;
1431 else
1432 return result;
1433
1434 if (!(reg_eac & BIT(27)) &&
1435 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1436 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1437 result |= 0x02;
1438 return result;
1439}
1440
1441static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
1442{
1443 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1444 u8 result = 0x00;
1445
1446 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1447 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1448 mdelay(IQK_DELAY_TIME);
1449 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1450 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1451 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1452 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1453 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1454 if (!(reg_eac & BIT(31)) &&
1455 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1456 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1457 result |= 0x01;
1458 else
1459 return result;
1460
1461 if (!(reg_eac & BIT(30)) &&
1462 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1463 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1464 result |= 0x02;
1465 return result;
1466}
1467
1468static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
1469 bool b_iqk_ok, long result[][8],
1470 u8 final_candidate, bool btxonly)
1471{
1472 u32 oldval_0, x, tx0_a, reg;
1473 long y, tx0_c;
1474
1475 if (final_candidate == 0xFF)
1476 return;
1477 else if (b_iqk_ok) {
1478 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1479 MASKDWORD) >> 22) & 0x3FF;
1480 x = result[final_candidate][0];
1481 if ((x & 0x00000200) != 0)
1482 x = x | 0xFFFFFC00;
1483 tx0_a = (x * oldval_0) >> 8;
1484 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1485 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1486 ((x * oldval_0 >> 7) & 0x1));
1487 y = result[final_candidate][1];
1488 if ((y & 0x00000200) != 0)
1489 y = y | 0xFFFFFC00;
1490 tx0_c = (y * oldval_0) >> 8;
1491 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1492 ((tx0_c & 0x3C0) >> 6));
1493 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1494 (tx0_c & 0x3F));
1495 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1496 ((y * oldval_0 >> 7) & 0x1));
1497 if (btxonly)
1498 return;
1499 reg = result[final_candidate][2];
1500 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1501 reg = result[final_candidate][3] & 0x3F;
1502 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1503 reg = (result[final_candidate][3] >> 6) & 0xF;
1504 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1505 }
1506}
1507
1508static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1509 bool b_iqk_ok, long result[][8],
1510 u8 final_candidate, bool btxonly)
1511{
1512 u32 oldval_1, x, tx1_a, reg;
1513 long y, tx1_c;
1514
1515 if (final_candidate == 0xFF)
1516 return;
1517 else if (b_iqk_ok) {
1518 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1519 MASKDWORD) >> 22) & 0x3FF;
1520 x = result[final_candidate][4];
1521 if ((x & 0x00000200) != 0)
1522 x = x | 0xFFFFFC00;
1523 tx1_a = (x * oldval_1) >> 8;
1524 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1525 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1526 ((x * oldval_1 >> 7) & 0x1));
1527 y = result[final_candidate][5];
1528 if ((y & 0x00000200) != 0)
1529 y = y | 0xFFFFFC00;
1530 tx1_c = (y * oldval_1) >> 8;
1531 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1532 ((tx1_c & 0x3C0) >> 6));
1533 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1534 (tx1_c & 0x3F));
1535 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1536 ((y * oldval_1 >> 7) & 0x1));
1537 if (btxonly)
1538 return;
1539 reg = result[final_candidate][6];
1540 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1541 reg = result[final_candidate][7] & 0x3F;
1542 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1543 reg = (result[final_candidate][7] >> 6) & 0xF;
1544 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1545 }
1546}
1547
1548static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
1549 u32 *addareg, u32 *addabackup,
1550 u32 registernum)
1551{
1552 u32 i;
1553
1554 for (i = 0; i < registernum; i++)
1555 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1556}
1557
1558static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
1559 u32 *macreg, u32 *macbackup)
1560{
1561 struct rtl_priv *rtlpriv = rtl_priv(hw);
1562 u32 i;
1563
1564 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1565 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1566 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1567}
1568
1569static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1570 u32 *addareg, u32 *addabackup,
1571 u32 regiesternum)
1572{
1573 u32 i;
1574
1575 for (i = 0; i < regiesternum; i++)
1576 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1577}
1578
1579static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1580 u32 *macreg, u32 *macbackup)
1581{
1582 struct rtl_priv *rtlpriv = rtl_priv(hw);
1583 u32 i;
1584
1585 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1586 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1587 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1588}
1589
1590static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1591 u32 *addareg, bool is_patha_on, bool is2t)
1592{
1593 u32 pathOn;
1594 u32 i;
1595
1596 pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1597 if (false == is2t) {
1598 pathOn = 0x0bdb25a0;
1599 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1600 } else {
1601 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1602 }
1603
1604 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1605 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1606}
1607
1608static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1609 u32 *macreg, u32 *macbackup)
1610{
1611 struct rtl_priv *rtlpriv = rtl_priv(hw);
1612 u32 i;
1613
1614 rtl_write_byte(rtlpriv, macreg[0], 0x3F);
1615
1616 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1617 rtl_write_byte(rtlpriv, macreg[i],
1618 (u8) (macbackup[i] & (~BIT(3))));
1619 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1620}
1621
1622static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1623{
1624 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1625 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1626 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1627}
1628
1629static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1630{
1631 u32 mode;
1632
1633 mode = pi_mode ? 0x01000100 : 0x01000000;
1634 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1635 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1636}
1637
1638static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1639 long result[][8], u8 c1, u8 c2)
1640{
1641 u32 i, j, diff, simularity_bitmap, bound;
1642 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1643
1644 u8 final_candidate[2] = { 0xFF, 0xFF };
1645 bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1646
1647 if (is2t)
1648 bound = 8;
1649 else
1650 bound = 4;
1651
1652 simularity_bitmap = 0;
1653
1654 for (i = 0; i < bound; i++) {
1655 diff = (result[c1][i] > result[c2][i]) ?
1656 (result[c1][i] - result[c2][i]) :
1657 (result[c2][i] - result[c1][i]);
1658
1659 if (diff > MAX_TOLERANCE) {
1660 if ((i == 2 || i == 6) && !simularity_bitmap) {
1661 if (result[c1][i] + result[c1][i + 1] == 0)
1662 final_candidate[(i / 4)] = c2;
1663 else if (result[c2][i] + result[c2][i + 1] == 0)
1664 final_candidate[(i / 4)] = c1;
1665 else
1666 simularity_bitmap = simularity_bitmap |
1667 (1 << i);
1668 } else
1669 simularity_bitmap =
1670 simularity_bitmap | (1 << i);
1671 }
1672 }
1673
1674 if (simularity_bitmap == 0) {
1675 for (i = 0; i < (bound / 4); i++) {
1676 if (final_candidate[i] != 0xFF) {
1677 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1678 result[3][j] =
1679 result[final_candidate[i]][j];
1680 bresult = false;
1681 }
1682 }
1683 return bresult;
1684 } else if (!(simularity_bitmap & 0x0F)) {
1685 for (i = 0; i < 4; i++)
1686 result[3][i] = result[c1][i];
1687 return false;
1688 } else if (!(simularity_bitmap & 0xF0) && is2t) {
1689 for (i = 4; i < 8; i++)
1690 result[3][i] = result[c1][i];
1691 return false;
1692 } else {
1693 return false;
1694 }
1695
1696}
1697
1698static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1699 long result[][8], u8 t, bool is2t)
1700{
1701 struct rtl_priv *rtlpriv = rtl_priv(hw);
1702 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1703 u32 i;
1704 u8 patha_ok, pathb_ok;
1705 u32 adda_reg[IQK_ADDA_REG_NUM] = {
1706 0x85c, 0xe6c, 0xe70, 0xe74,
1707 0xe78, 0xe7c, 0xe80, 0xe84,
1708 0xe88, 0xe8c, 0xed0, 0xed4,
1709 0xed8, 0xedc, 0xee0, 0xeec
1710 };
1711
1712 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1713 0x522, 0x550, 0x551, 0x040
1714 };
1715
1716 const u32 retrycount = 2;
1717
1718 u32 bbvalue;
1719
1720 if (t == 0) {
1721 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1722
1723 _rtl92c_phy_save_adda_registers(hw, adda_reg,
1724 rtlphy->adda_backup, 16);
1725 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1726 rtlphy->iqk_mac_backup);
1727 }
1728 _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1729 if (t == 0) {
1730 rtlphy->b_rfpi_enable = (u8) rtl_get_bbreg(hw,
1731 RFPGA0_XA_HSSIPARAMETER1,
1732 BIT(8));
1733 }
1734 if (!rtlphy->b_rfpi_enable)
1735 _rtl92c_phy_pi_mode_switch(hw, true);
1736 if (t == 0) {
1737 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1738 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1739 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1740 }
1741 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1742 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1743 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1744 if (is2t) {
1745 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1746 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1747 }
1748 _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1749 rtlphy->iqk_mac_backup);
1750 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1751 if (is2t)
1752 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1753 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1754 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1755 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1756 for (i = 0; i < retrycount; i++) {
1757 patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1758 if (patha_ok == 0x03) {
1759 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1760 0x3FF0000) >> 16;
1761 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1762 0x3FF0000) >> 16;
1763 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1764 0x3FF0000) >> 16;
1765 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1766 0x3FF0000) >> 16;
1767 break;
1768 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1769 result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1770 MASKDWORD) & 0x3FF0000) >>
1771 16;
1772 result[t][1] =
1773 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1774
1775 }
1776
1777 if (is2t) {
1778 _rtl92c_phy_path_a_standby(hw);
1779 _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1780 for (i = 0; i < retrycount; i++) {
1781 pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1782 if (pathb_ok == 0x03) {
1783 result[t][4] = (rtl_get_bbreg(hw,
1784 0xeb4,
1785 MASKDWORD) &
1786 0x3FF0000) >> 16;
1787 result[t][5] =
1788 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1789 0x3FF0000) >> 16;
1790 result[t][6] =
1791 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1792 0x3FF0000) >> 16;
1793 result[t][7] =
1794 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1795 0x3FF0000) >> 16;
1796 break;
1797 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1798 result[t][4] = (rtl_get_bbreg(hw,
1799 0xeb4,
1800 MASKDWORD) &
1801 0x3FF0000) >> 16;
1802 }
1803 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1804 0x3FF0000) >> 16;
1805 }
1806 }
1807 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1808 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1809 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1810 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1811 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1812 if (is2t)
1813 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1814 if (t != 0) {
1815 if (!rtlphy->b_rfpi_enable)
1816 _rtl92c_phy_pi_mode_switch(hw, false);
1817 _rtl92c_phy_reload_adda_registers(hw, adda_reg,
1818 rtlphy->adda_backup, 16);
1819 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1820 rtlphy->iqk_mac_backup);
1821 }
1822}
1823
1824static void _rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1825{ 436{
1826 u8 tmpreg; 437 u8 tmpreg;
1827 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal; 438 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
@@ -1866,666 +477,6 @@ static void _rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1866 } 477 }
1867} 478}
1868 479
1869static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1870 char delta, bool is2t)
1871{
1872 /* This routine is deliberately dummied out for later fixes */
1873#if 0
1874 struct rtl_priv *rtlpriv = rtl_priv(hw);
1875 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1876 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1877
1878 u32 reg_d[PATH_NUM];
1879 u32 tmpreg, index, offset, path, i, pathbound = PATH_NUM, apkbound;
1880
1881 u32 bb_backup[APK_BB_REG_NUM];
1882 u32 bb_reg[APK_BB_REG_NUM] = {
1883 0x904, 0xc04, 0x800, 0xc08, 0x874
1884 };
1885 u32 bb_ap_mode[APK_BB_REG_NUM] = {
1886 0x00000020, 0x00a05430, 0x02040000,
1887 0x000800e4, 0x00204000
1888 };
1889 u32 bb_normal_ap_mode[APK_BB_REG_NUM] = {
1890 0x00000020, 0x00a05430, 0x02040000,
1891 0x000800e4, 0x22204000
1892 };
1893
1894 u32 afe_backup[APK_AFE_REG_NUM];
1895 u32 afe_reg[APK_AFE_REG_NUM] = {
1896 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78,
1897 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c,
1898 0xed0, 0xed4, 0xed8, 0xedc, 0xee0,
1899 0xeec
1900 };
1901
1902 u32 mac_backup[IQK_MAC_REG_NUM];
1903 u32 mac_reg[IQK_MAC_REG_NUM] = {
1904 0x522, 0x550, 0x551, 0x040
1905 };
1906
1907 u32 apk_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1908 {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
1909 {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
1910 };
1911
1912 u32 apk_normal_rf_init_value[PATH_NUM][APK_BB_REG_NUM] = {
1913 {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},
1914 {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
1915 };
1916
1917 u32 apk_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1918 {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
1919 {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
1920 };
1921
1922 u32 apk_normal_rf_value_0[PATH_NUM][APK_BB_REG_NUM] = {
1923 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},
1924 {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
1925 };
1926
1927 u32 afe_on_off[PATH_NUM] = {
1928 0x04db25a4, 0x0b1b25a4
1929 };
1930
1931 u32 apk_offset[PATH_NUM] = { 0xb68, 0xb6c };
1932
1933 u32 apk_normal_offset[PATH_NUM] = { 0xb28, 0xb98 };
1934
1935 u32 apk_value[PATH_NUM] = { 0x92fc0000, 0x12fc0000 };
1936
1937 u32 apk_normal_value[PATH_NUM] = { 0x92680000, 0x12680000 };
1938
1939 const char apk_delta_mapping[APK_BB_REG_NUM][13] = {
1940 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1941 {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1942 {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1943 {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
1944 {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
1945 };
1946
1947 const u32 apk_normal_setting_value_1[13] = {
1948 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
1949 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
1950 0x12680000, 0x00880000, 0x00880000
1951 };
1952
1953 const u32 apk_normal_setting_value_2[16] = {
1954 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
1955 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
1956 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
1957 0x00050006
1958 };
1959
1960 const u32 apk_result[PATH_NUM][APK_BB_REG_NUM];
1961
1962 long bb_offset, delta_v, delta_offset;
1963
1964 if (!is2t)
1965 pathbound = 1;
1966
1967 for (index = 0; index < PATH_NUM; index++) {
1968 apk_offset[index] = apk_normal_offset[index];
1969 apk_value[index] = apk_normal_value[index];
1970 afe_on_off[index] = 0x6fdb25a4;
1971 }
1972
1973 for (index = 0; index < APK_BB_REG_NUM; index++) {
1974 for (path = 0; path < pathbound; path++) {
1975 apk_rf_init_value[path][index] =
1976 apk_normal_rf_init_value[path][index];
1977 apk_rf_value_0[path][index] =
1978 apk_normal_rf_value_0[path][index];
1979 }
1980 bb_ap_mode[index] = bb_normal_ap_mode[index];
1981
1982 apkbound = 6;
1983 }
1984
1985 for (index = 0; index < APK_BB_REG_NUM; index++) {
1986 if (index == 0)
1987 continue;
1988 bb_backup[index] = rtl_get_bbreg(hw, bb_reg[index], MASKDWORD);
1989 }
1990
1991 _rtl92c_phy_save_mac_registers(hw, mac_reg, mac_backup);
1992
1993 _rtl92c_phy_save_adda_registers(hw, afe_reg, afe_backup, 16);
1994
1995 for (path = 0; path < pathbound; path++) {
1996 if (path == RF90_PATH_A) {
1997 offset = 0xb00;
1998 for (index = 0; index < 11; index++) {
1999 rtl_set_bbreg(hw, offset, MASKDWORD,
2000 apk_normal_setting_value_1
2001 [index]);
2002
2003 offset += 0x04;
2004 }
2005
2006 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
2007
2008 offset = 0xb68;
2009 for (; index < 13; index++) {
2010 rtl_set_bbreg(hw, offset, MASKDWORD,
2011 apk_normal_setting_value_1
2012 [index]);
2013
2014 offset += 0x04;
2015 }
2016
2017 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
2018
2019 offset = 0xb00;
2020 for (index = 0; index < 16; index++) {
2021 rtl_set_bbreg(hw, offset, MASKDWORD,
2022 apk_normal_setting_value_2
2023 [index]);
2024
2025 offset += 0x04;
2026 }
2027 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
2028 } else if (path == RF90_PATH_B) {
2029 offset = 0xb70;
2030 for (index = 0; index < 10; index++) {
2031 rtl_set_bbreg(hw, offset, MASKDWORD,
2032 apk_normal_setting_value_1
2033 [index]);
2034
2035 offset += 0x04;
2036 }
2037 rtl_set_bbreg(hw, 0xb28, MASKDWORD, 0x12680000);
2038 rtl_set_bbreg(hw, 0xb98, MASKDWORD, 0x12680000);
2039
2040 offset = 0xb68;
2041 index = 11;
2042 for (; index < 13; index++) {
2043 rtl_set_bbreg(hw, offset, MASKDWORD,
2044 apk_normal_setting_value_1
2045 [index]);
2046
2047 offset += 0x04;
2048 }
2049
2050 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x40000000);
2051
2052 offset = 0xb60;
2053 for (index = 0; index < 16; index++) {
2054 rtl_set_bbreg(hw, offset, MASKDWORD,
2055 apk_normal_setting_value_2
2056 [index]);
2057
2058 offset += 0x04;
2059 }
2060 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
2061 }
2062
2063 reg_d[path] = rtl_get_rfreg(hw, (enum radio_path)path,
2064 0xd, MASKDWORD);
2065
2066 for (index = 0; index < APK_AFE_REG_NUM; index++)
2067 rtl_set_bbreg(hw, afe_reg[index], MASKDWORD,
2068 afe_on_off[path]);
2069
2070 if (path == RF90_PATH_A) {
2071 for (index = 0; index < APK_BB_REG_NUM; index++) {
2072 if (index == 0)
2073 continue;
2074 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD,
2075 bb_ap_mode[index]);
2076 }
2077 }
2078
2079 _rtl92c_phy_mac_setting_calibration(hw, mac_reg, mac_backup);
2080
2081 if (path == 0) {
2082 rtl_set_rfreg(hw, RF90_PATH_B, 0x0, MASKDWORD, 0x10000);
2083 } else {
2084 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASKDWORD,
2085 0x10000);
2086 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
2087 0x1000f);
2088 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
2089 0x20103);
2090 }
2091
2092 delta_offset = ((delta + 14) / 2);
2093 if (delta_offset < 0)
2094 delta_offset = 0;
2095 else if (delta_offset > 12)
2096 delta_offset = 12;
2097
2098 for (index = 0; index < APK_BB_REG_NUM; index++) {
2099 if (index != 1)
2100 continue;
2101
2102 tmpreg = apk_rf_init_value[path][index];
2103
2104 if (!rtlefuse->b_apk_thermalmeterignore) {
2105 bb_offset = (tmpreg & 0xF0000) >> 16;
2106
2107 if (!(tmpreg & BIT(15)))
2108 bb_offset = -bb_offset;
2109
2110 delta_v =
2111 apk_delta_mapping[index][delta_offset];
2112
2113 bb_offset += delta_v;
2114
2115 if (bb_offset < 0) {
2116 tmpreg = tmpreg & (~BIT(15));
2117 bb_offset = -bb_offset;
2118 } else {
2119 tmpreg = tmpreg | BIT(15);
2120 }
2121
2122 tmpreg =
2123 (tmpreg & 0xFFF0FFFF) | (bb_offset << 16);
2124 }
2125
2126 rtl_set_rfreg(hw, (enum radio_path)path, 0xc,
2127 MASKDWORD, 0x8992e);
2128 rtl_set_rfreg(hw, (enum radio_path)path, 0x0,
2129 MASKDWORD, apk_rf_value_0[path][index]);
2130 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
2131 MASKDWORD, tmpreg);
2132
2133 i = 0;
2134 do {
2135 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80000000);
2136 rtl_set_bbreg(hw, apk_offset[path],
2137 MASKDWORD, apk_value[0]);
2138 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2139 ("PHY_APCalibrate() offset 0x%x "
2140 "value 0x%x\n",
2141 apk_offset[path],
2142 rtl_get_bbreg(hw, apk_offset[path],
2143 MASKDWORD)));
2144
2145 mdelay(3);
2146
2147 rtl_set_bbreg(hw, apk_offset[path],
2148 MASKDWORD, apk_value[1]);
2149 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2150 ("PHY_APCalibrate() offset 0x%x "
2151 "value 0x%x\n",
2152 apk_offset[path],
2153 rtl_get_bbreg(hw, apk_offset[path],
2154 MASKDWORD)));
2155
2156 mdelay(20);
2157
2158 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x00000000);
2159
2160 if (path == RF90_PATH_A)
2161 tmpreg = rtl_get_bbreg(hw, 0xbd8,
2162 0x03E00000);
2163 else
2164 tmpreg = rtl_get_bbreg(hw, 0xbd8,
2165 0xF8000000);
2166
2167 RTPRINT(rtlpriv, FINIT, INIT_IQK,
2168 ("PHY_APCalibrate() offset "
2169 "0xbd8[25:21] %x\n", tmpreg));
2170
2171 i++;
2172
2173 } while (tmpreg > apkbound && i < 4);
2174
2175 apk_result[path][index] = tmpreg;
2176 }
2177 }
2178
2179 _rtl92c_phy_reload_mac_registers(hw, mac_reg, mac_backup);
2180
2181 for (index = 0; index < APK_BB_REG_NUM; index++) {
2182 if (index == 0)
2183 continue;
2184 rtl_set_bbreg(hw, bb_reg[index], MASKDWORD, bb_backup[index]);
2185 }
2186
2187 _rtl92c_phy_reload_adda_registers(hw, afe_reg, afe_backup, 16);
2188
2189 for (path = 0; path < pathbound; path++) {
2190 rtl_set_rfreg(hw, (enum radio_path)path, 0xd,
2191 MASKDWORD, reg_d[path]);
2192
2193 if (path == RF90_PATH_B) {
2194 rtl_set_rfreg(hw, RF90_PATH_A, 0x10, MASKDWORD,
2195 0x1000f);
2196 rtl_set_rfreg(hw, RF90_PATH_A, 0x11, MASKDWORD,
2197 0x20101);
2198 }
2199
2200 if (apk_result[path][1] > 6)
2201 apk_result[path][1] = 6;
2202 }
2203
2204 for (path = 0; path < pathbound; path++) {
2205 rtl_set_rfreg(hw, (enum radio_path)path, 0x3, MASKDWORD,
2206 ((apk_result[path][1] << 15) |
2207 (apk_result[path][1] << 10) |
2208 (apk_result[path][1] << 5) |
2209 apk_result[path][1]));
2210
2211 if (path == RF90_PATH_A)
2212 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
2213 ((apk_result[path][1] << 15) |
2214 (apk_result[path][1] << 10) |
2215 (0x00 << 5) | 0x05));
2216 else
2217 rtl_set_rfreg(hw, (enum radio_path)path, 0x4, MASKDWORD,
2218 ((apk_result[path][1] << 15) |
2219 (apk_result[path][1] << 10) |
2220 (0x02 << 5) | 0x05));
2221
2222 rtl_set_rfreg(hw, (enum radio_path)path, 0xe, MASKDWORD,
2223 ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) |
2224 0x08));
2225
2226 }
2227
2228 rtlphy->b_apk_done = true;
2229#endif
2230}
2231
2232static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
2233 bool bmain, bool is2t)
2234{
2235 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2236
2237 if (is_hal_stop(rtlhal)) {
2238 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
2239 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
2240 }
2241 if (is2t) {
2242 if (bmain)
2243 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2244 BIT(5) | BIT(6), 0x1);
2245 else
2246 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
2247 BIT(5) | BIT(6), 0x2);
2248 } else {
2249 if (bmain)
2250 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
2251 else
2252 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
2253
2254 }
2255}
2256
2257#undef IQK_ADDA_REG_NUM
2258#undef IQK_DELAY_TIME
2259
2260void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
2261{
2262 struct rtl_priv *rtlpriv = rtl_priv(hw);
2263 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2264 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2265
2266 long result[4][8];
2267 u8 i, final_candidate;
2268 bool b_patha_ok, b_pathb_ok;
2269 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
2270 reg_ecc, reg_tmp = 0;
2271 bool is12simular, is13simular, is23simular;
2272 bool b_start_conttx = false, b_singletone = false;
2273 u32 iqk_bb_reg[10] = {
2274 ROFDM0_XARXIQIMBALANCE,
2275 ROFDM0_XBRXIQIMBALANCE,
2276 ROFDM0_ECCATHRESHOLD,
2277 ROFDM0_AGCRSSITABLE,
2278 ROFDM0_XATXIQIMBALANCE,
2279 ROFDM0_XBTXIQIMBALANCE,
2280 ROFDM0_XCTXIQIMBALANCE,
2281 ROFDM0_XCTXAFE,
2282 ROFDM0_XDTXAFE,
2283 ROFDM0_RXIQEXTANTA
2284 };
2285
2286 if (b_recovery) {
2287 _rtl92c_phy_reload_adda_registers(hw,
2288 iqk_bb_reg,
2289 rtlphy->iqk_bb_backup, 10);
2290 return;
2291 }
2292 if (b_start_conttx || b_singletone)
2293 return;
2294 for (i = 0; i < 8; i++) {
2295 result[0][i] = 0;
2296 result[1][i] = 0;
2297 result[2][i] = 0;
2298 result[3][i] = 0;
2299 }
2300 final_candidate = 0xff;
2301 b_patha_ok = false;
2302 b_pathb_ok = false;
2303 is12simular = false;
2304 is23simular = false;
2305 is13simular = false;
2306 for (i = 0; i < 3; i++) {
2307 if (IS_92C_SERIAL(rtlhal->version))
2308 _rtl92c_phy_iq_calibrate(hw, result, i, true);
2309 else
2310 _rtl92c_phy_iq_calibrate(hw, result, i, false);
2311 if (i == 1) {
2312 is12simular = _rtl92c_phy_simularity_compare(hw,
2313 result, 0,
2314 1);
2315 if (is12simular) {
2316 final_candidate = 0;
2317 break;
2318 }
2319 }
2320 if (i == 2) {
2321 is13simular = _rtl92c_phy_simularity_compare(hw,
2322 result, 0,
2323 2);
2324 if (is13simular) {
2325 final_candidate = 0;
2326 break;
2327 }
2328 is23simular = _rtl92c_phy_simularity_compare(hw,
2329 result, 1,
2330 2);
2331 if (is23simular)
2332 final_candidate = 1;
2333 else {
2334 for (i = 0; i < 8; i++)
2335 reg_tmp += result[3][i];
2336
2337 if (reg_tmp != 0)
2338 final_candidate = 3;
2339 else
2340 final_candidate = 0xFF;
2341 }
2342 }
2343 }
2344 for (i = 0; i < 4; i++) {
2345 reg_e94 = result[i][0];
2346 reg_e9c = result[i][1];
2347 reg_ea4 = result[i][2];
2348 reg_eac = result[i][3];
2349 reg_eb4 = result[i][4];
2350 reg_ebc = result[i][5];
2351 reg_ec4 = result[i][6];
2352 reg_ecc = result[i][7];
2353 }
2354 if (final_candidate != 0xff) {
2355 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
2356 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
2357 reg_ea4 = result[final_candidate][2];
2358 reg_eac = result[final_candidate][3];
2359 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
2360 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
2361 reg_ec4 = result[final_candidate][6];
2362 reg_ecc = result[final_candidate][7];
2363 b_patha_ok = b_pathb_ok = true;
2364 } else {
2365 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
2366 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
2367 }
2368 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
2369 _rtl92c_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
2370 final_candidate,
2371 (reg_ea4 == 0));
2372 if (IS_92C_SERIAL(rtlhal->version)) {
2373 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
2374 _rtl92c_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok,
2375 result,
2376 final_candidate,
2377 (reg_ec4 == 0));
2378 }
2379 _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
2380 rtlphy->iqk_bb_backup, 10);
2381}
2382
2383void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
2384{
2385 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2386 bool b_start_conttx = false, b_singletone = false;
2387
2388 if (b_start_conttx || b_singletone)
2389 return;
2390 if (IS_92C_SERIAL(rtlhal->version))
2391 _rtl92c_phy_lc_calibrate(hw, true);
2392 else
2393 _rtl92c_phy_lc_calibrate(hw, false);
2394}
2395
2396void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, char delta)
2397{
2398 struct rtl_priv *rtlpriv = rtl_priv(hw);
2399 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2400 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2401
2402 if (rtlphy->b_apk_done)
2403 return;
2404 if (IS_92C_SERIAL(rtlhal->version))
2405 _rtl92c_phy_ap_calibrate(hw, delta, true);
2406 else
2407 _rtl92c_phy_ap_calibrate(hw, delta, false);
2408}
2409
2410void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
2411{
2412 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2413
2414 if (IS_92C_SERIAL(rtlhal->version))
2415 _rtl92c_phy_set_rfpath_switch(hw, bmain, true);
2416 else
2417 _rtl92c_phy_set_rfpath_switch(hw, bmain, false);
2418}
2419
2420bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
2421{
2422 struct rtl_priv *rtlpriv = rtl_priv(hw);
2423 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2424 bool b_postprocessing = false;
2425
2426 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2427 ("-->IO Cmd(%#x), set_io_inprogress(%d)\n",
2428 iotype, rtlphy->set_io_inprogress));
2429 do {
2430 switch (iotype) {
2431 case IO_CMD_RESUME_DM_BY_SCAN:
2432 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2433 ("[IO CMD] Resume DM after scan.\n"));
2434 b_postprocessing = true;
2435 break;
2436 case IO_CMD_PAUSE_DM_BY_SCAN:
2437 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2438 ("[IO CMD] Pause DM before scan.\n"));
2439 b_postprocessing = true;
2440 break;
2441 default:
2442 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2443 ("switch case not process\n"));
2444 break;
2445 }
2446 } while (false);
2447 if (b_postprocessing && !rtlphy->set_io_inprogress) {
2448 rtlphy->set_io_inprogress = true;
2449 rtlphy->current_io_type = iotype;
2450 } else {
2451 return false;
2452 }
2453 rtl92c_phy_set_io(hw);
2454 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, ("<--IO Type(%#x)\n", iotype));
2455 return true;
2456}
2457
2458void rtl92c_phy_set_io(struct ieee80211_hw *hw)
2459{
2460 struct rtl_priv *rtlpriv = rtl_priv(hw);
2461 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2462
2463 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2464 ("--->Cmd(%#x), set_io_inprogress(%d)\n",
2465 rtlphy->current_io_type, rtlphy->set_io_inprogress));
2466 switch (rtlphy->current_io_type) {
2467 case IO_CMD_RESUME_DM_BY_SCAN:
2468 dm_digtable.cur_igvalue = rtlphy->initgain_backup.xaagccore1;
2469 rtl92c_dm_write_dig(hw);
2470 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
2471 break;
2472 case IO_CMD_PAUSE_DM_BY_SCAN:
2473 rtlphy->initgain_backup.xaagccore1 = dm_digtable.cur_igvalue;
2474 dm_digtable.cur_igvalue = 0x17;
2475 rtl92c_dm_write_dig(hw);
2476 break;
2477 default:
2478 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2479 ("switch case not process\n"));
2480 break;
2481 }
2482 rtlphy->set_io_inprogress = false;
2483 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
2484 ("<---(%#x)\n", rtlphy->current_io_type));
2485}
2486
2487void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
2488{
2489 struct rtl_priv *rtlpriv = rtl_priv(hw);
2490
2491 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
2492 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2493 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2494 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2495 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2496 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2497}
2498
2499static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
2500{
2501 u32 u4b_tmp;
2502 u8 delay = 5;
2503 struct rtl_priv *rtlpriv = rtl_priv(hw);
2504
2505 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
2506 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2507 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2508 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2509 while (u4b_tmp != 0 && delay > 0) {
2510 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
2511 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
2512 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
2513 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
2514 delay--;
2515 }
2516 if (delay == 0) {
2517 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
2518 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2519 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
2520 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
2521 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
2522 ("Switch RF timeout !!!.\n"));
2523 return;
2524 }
2525 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
2526 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
2527}
2528
2529static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw, 480static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
2530 enum rf_pwrstate rfpwr_state) 481 enum rf_pwrstate rfpwr_state)
2531{ 482{
@@ -2648,7 +599,7 @@ static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
2648 jiffies_to_msecs(jiffies - 599 jiffies_to_msecs(jiffies -
2649 ppsc->last_awake_jiffies))); 600 ppsc->last_awake_jiffies)));
2650 ppsc->last_sleep_jiffies = jiffies; 601 ppsc->last_sleep_jiffies = jiffies;
2651 _rtl92ce_phy_set_rf_sleep(hw); 602 _rtl92c_phy_set_rf_sleep(hw);
2652 break; 603 break;
2653 } 604 }
2654 default: 605 default:
@@ -2663,7 +614,7 @@ static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
2663 return bresult; 614 return bresult;
2664} 615}
2665 616
2666bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw, 617bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
2667 enum rf_pwrstate rfpwr_state) 618 enum rf_pwrstate rfpwr_state)
2668{ 619{
2669 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 620 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.h b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.h
index ca4daee6e9a8..a37267e3fc22 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/phy.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/phy.h
@@ -57,8 +57,6 @@
57#define IQK_MAC_REG_NUM 4 57#define IQK_MAC_REG_NUM 4
58 58
59#define RF90_PATH_MAX 2 59#define RF90_PATH_MAX 2
60#define CHANNEL_MAX_NUMBER 14
61#define CHANNEL_GROUP_MAX 3
62 60
63#define CT_OFFSET_MAC_ADDR 0X16 61#define CT_OFFSET_MAC_ADDR 0X16
64 62
@@ -78,9 +76,7 @@
78#define CT_OFFSET_CUSTOMER_ID 0x7F 76#define CT_OFFSET_CUSTOMER_ID 0x7F
79 77
80#define RTL92C_MAX_PATH_NUM 2 78#define RTL92C_MAX_PATH_NUM 2
81#define CHANNEL_MAX_NUMBER 14 79#define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
82#define CHANNEL_GROUP_MAX 3
83
84enum swchnlcmd_id { 80enum swchnlcmd_id {
85 CMDID_END, 81 CMDID_END,
86 CMDID_SET_TXPOWEROWER_LEVEL, 82 CMDID_SET_TXPOWEROWER_LEVEL,
@@ -195,11 +191,11 @@ extern void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
195extern u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw, 191extern u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
196 enum radio_path rfpath, u32 regaddr, 192 enum radio_path rfpath, u32 regaddr,
197 u32 bitmask); 193 u32 bitmask);
198extern void rtl92c_phy_set_rf_reg(struct ieee80211_hw *hw, 194extern void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
199 enum radio_path rfpath, u32 regaddr, 195 enum radio_path rfpath, u32 regaddr,
200 u32 bitmask, u32 data); 196 u32 bitmask, u32 data);
201extern bool rtl92c_phy_mac_config(struct ieee80211_hw *hw); 197extern bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
202extern bool rtl92c_phy_bb_config(struct ieee80211_hw *hw); 198bool rtl92ce_phy_bb_config(struct ieee80211_hw *hw);
203extern bool rtl92c_phy_rf_config(struct ieee80211_hw *hw); 199extern bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
204extern bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw, 200extern bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
205 enum radio_path rfpath); 201 enum radio_path rfpath);
@@ -227,11 +223,32 @@ bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
227extern bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, 223extern bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
228 u32 rfpath); 224 u32 rfpath);
229bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); 225bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
230extern bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw, 226bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
231 enum rf_pwrstate rfpwr_state); 227 enum rf_pwrstate rfpwr_state);
232void rtl92c_phy_config_bb_external_pa(struct ieee80211_hw *hw);
233void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw); 228void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
234bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype); 229bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
235void rtl92c_phy_set_io(struct ieee80211_hw *hw); 230void rtl92c_phy_set_io(struct ieee80211_hw *hw);
231void rtl92c_bb_block_on(struct ieee80211_hw *hw);
232u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
233 enum radio_path rfpath, u32 offset);
234u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
235 enum radio_path rfpath, u32 offset);
236u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
237void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
238 enum radio_path rfpath, u32 offset,
239 u32 data);
240void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
241 u32 regaddr, u32 bitmask,
242 u32 data);
243void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
244 enum radio_path rfpath, u32 offset,
245 u32 data);
246void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
247 u32 regaddr, u32 bitmask,
248 u32 data);
249bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
250void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
251bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
252void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
236 253
237#endif 254#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
index 875d51465225..b0868a613841 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/reg.h
@@ -63,7 +63,15 @@
63#define REG_LEDCFG3 0x004F 63#define REG_LEDCFG3 0x004F
64#define REG_FSIMR 0x0050 64#define REG_FSIMR 0x0050
65#define REG_FSISR 0x0054 65#define REG_FSISR 0x0054
66 66#define REG_HSIMR 0x0058
67#define REG_HSISR 0x005c
68
69/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
70#define REG_GPIO_PIN_CTRL_2 0x0060
71/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
72#define REG_GPIO_IO_SEL_2 0x0062
73/* RTL8723 WIFI/BT/GPS Multi-Function control source. */
74#define REG_MULTI_FUNC_CTRL 0x0068
67#define REG_MCUFWDL 0x0080 75#define REG_MCUFWDL 0x0080
68 76
69#define REG_HMEBOX_EXT_0 0x0088 77#define REG_HMEBOX_EXT_0 0x0088
@@ -79,6 +87,7 @@
79#define REG_PCIE_MIO_INTD 0x00E8 87#define REG_PCIE_MIO_INTD 0x00E8
80#define REG_HPON_FSM 0x00EC 88#define REG_HPON_FSM 0x00EC
81#define REG_SYS_CFG 0x00F0 89#define REG_SYS_CFG 0x00F0
90#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only.*/
82 91
83#define REG_CR 0x0100 92#define REG_CR 0x0100
84#define REG_PBP 0x0104 93#define REG_PBP 0x0104
@@ -209,6 +218,8 @@
209#define REG_RDG_PIFS 0x0513 218#define REG_RDG_PIFS 0x0513
210#define REG_SIFS_CTX 0x0514 219#define REG_SIFS_CTX 0x0514
211#define REG_SIFS_TRX 0x0516 220#define REG_SIFS_TRX 0x0516
221#define REG_SIFS_CCK 0x0514
222#define REG_SIFS_OFDM 0x0516
212#define REG_AGGR_BREAK_TIME 0x051A 223#define REG_AGGR_BREAK_TIME 0x051A
213#define REG_SLOT 0x051B 224#define REG_SLOT 0x051B
214#define REG_TX_PTCL_CTRL 0x0520 225#define REG_TX_PTCL_CTRL 0x0520
@@ -261,6 +272,10 @@
261#define REG_MAC_SPEC_SIFS 0x063A 272#define REG_MAC_SPEC_SIFS 0x063A
262#define REG_RESP_SIFS_CCK 0x063C 273#define REG_RESP_SIFS_CCK 0x063C
263#define REG_RESP_SIFS_OFDM 0x063E 274#define REG_RESP_SIFS_OFDM 0x063E
275/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
276#define REG_R2T_SIFS 0x063C
277/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
278#define REG_T2T_SIFS 0x063E
264#define REG_ACKTO 0x0640 279#define REG_ACKTO 0x0640
265#define REG_CTS2TO 0x0641 280#define REG_CTS2TO 0x0641
266#define REG_EIFS 0x0642 281#define REG_EIFS 0x0642
@@ -641,9 +656,10 @@
641#define STOPBE BIT(1) 656#define STOPBE BIT(1)
642#define STOPBK BIT(0) 657#define STOPBK BIT(0)
643 658
644#define RCR_APPFCS BIT(31) 659#define RCR_APP_FCS BIT(31)
645#define RCR_APP_MIC BIT(30) 660#define RCR_APP_MIC BIT(30)
646#define RCR_APP_ICV BIT(29) 661#define RCR_APP_ICV BIT(29)
662#define RCR_APP_PHYSTS BIT(28)
647#define RCR_APP_PHYST_RXFF BIT(28) 663#define RCR_APP_PHYST_RXFF BIT(28)
648#define RCR_APP_BA_SSN BIT(27) 664#define RCR_APP_BA_SSN BIT(27)
649#define RCR_ENMBID BIT(24) 665#define RCR_ENMBID BIT(24)
@@ -759,6 +775,7 @@
759 775
760#define BOOT_FROM_EEPROM BIT(4) 776#define BOOT_FROM_EEPROM BIT(4)
761#define EEPROM_EN BIT(5) 777#define EEPROM_EN BIT(5)
778#define EEPROMSEL BOOT_FROM_EEPROM
762 779
763#define AFE_BGEN BIT(0) 780#define AFE_BGEN BIT(0)
764#define AFE_MBEN BIT(1) 781#define AFE_MBEN BIT(1)
@@ -876,6 +893,8 @@
876#define BD_MAC2 BIT(9) 893#define BD_MAC2 BIT(9)
877#define BD_MAC1 BIT(10) 894#define BD_MAC1 BIT(10)
878#define IC_MACPHY_MODE BIT(11) 895#define IC_MACPHY_MODE BIT(11)
896#define BT_FUNC BIT(16)
897#define VENDOR_ID BIT(19)
879#define PAD_HWPD_IDN BIT(22) 898#define PAD_HWPD_IDN BIT(22)
880#define TRP_VAUX_EN BIT(23) 899#define TRP_VAUX_EN BIT(23)
881#define TRP_BT_EN BIT(24) 900#define TRP_BT_EN BIT(24)
@@ -883,6 +902,28 @@
883#define BD_HCI_SEL BIT(26) 902#define BD_HCI_SEL BIT(26)
884#define TYPE_ID BIT(27) 903#define TYPE_ID BIT(27)
885 904
905/* REG_GPIO_OUTSTS (For RTL8723 only) */
906#define EFS_HCI_SEL (BIT(0)|BIT(1))
907#define PAD_HCI_SEL (BIT(2)|BIT(3))
908#define HCI_SEL (BIT(4)|BIT(5))
909#define PKG_SEL_HCI BIT(6)
910#define FEN_GPS BIT(7)
911#define FEN_BT BIT(8)
912#define FEN_WL BIT(9)
913#define FEN_PCI BIT(10)
914#define FEN_USB BIT(11)
915#define BTRF_HWPDN_N BIT(12)
916#define WLRF_HWPDN_N BIT(13)
917#define PDN_BT_N BIT(14)
918#define PDN_GPS_N BIT(15)
919#define BT_CTL_HWPDN BIT(16)
920#define GPS_CTL_HWPDN BIT(17)
921#define PPHY_SUSB BIT(20)
922#define UPHY_SUSB BIT(21)
923#define PCI_SUSEN BIT(22)
924#define USB_SUSEN BIT(23)
925#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
926
886#define CHIP_VER_RTL_MASK 0xF000 927#define CHIP_VER_RTL_MASK 0xF000
887#define CHIP_VER_RTL_SHIFT 12 928#define CHIP_VER_RTL_SHIFT 12
888 929
@@ -1035,7 +1076,7 @@
1035#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1076#define _RARF_RC7(x) (((x) & 0x1F) << 16)
1036#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1077#define _RARF_RC8(x) (((x) & 0x1F) << 24)
1037 1078
1038#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1079#define AC_PARAM_TXOP_OFFSET 16
1039#define AC_PARAM_ECW_MAX_OFFSET 12 1080#define AC_PARAM_ECW_MAX_OFFSET 12
1040#define AC_PARAM_ECW_MIN_OFFSET 8 1081#define AC_PARAM_ECW_MIN_OFFSET 8
1041#define AC_PARAM_AIFS_OFFSET 0 1082#define AC_PARAM_AIFS_OFFSET 0
@@ -1184,6 +1225,30 @@
1184 1225
1185#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1226#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
1186 1227
1228/* REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
1229/* Enable GPIO[9] as WiFi HW PDn source */
1230#define WL_HWPDN_EN BIT(0)
1231/* WiFi HW PDn polarity control */
1232#define WL_HWPDN_SL BIT(1)
1233/* WiFi function enable */
1234#define WL_FUNC_EN BIT(2)
1235/* Enable GPIO[9] as WiFi RF HW PDn source */
1236#define WL_HWROF_EN BIT(3)
1237/* Enable GPIO[11] as BT HW PDn source */
1238#define BT_HWPDN_EN BIT(16)
1239/* BT HW PDn polarity control */
1240#define BT_HWPDN_SL BIT(17)
1241/* BT function enable */
1242#define BT_FUNC_EN BIT(18)
1243/* Enable GPIO[11] as BT/GPS RF HW PDn source */
1244#define BT_HWROF_EN BIT(19)
1245/* Enable GPIO[10] as GPS HW PDn source */
1246#define GPS_HWPDN_EN BIT(20)
1247/* GPS HW PDn polarity control */
1248#define GPS_HWPDN_SL BIT(21)
1249/* GPS function enable */
1250#define GPS_FUNC_EN BIT(22)
1251
1187#define RPMAC_RESET 0x100 1252#define RPMAC_RESET 0x100
1188#define RPMAC_TXSTART 0x104 1253#define RPMAC_TXSTART 0x104
1189#define RPMAC_TXLEGACYSIG 0x108 1254#define RPMAC_TXLEGACYSIG 0x108
@@ -1496,7 +1561,7 @@
1496#define BTXHTSTBC 0x30 1561#define BTXHTSTBC 0x30
1497#define BTXHTADVANCECODING 0x40 1562#define BTXHTADVANCECODING 0x40
1498#define BTXHTSHORTGI 0x80 1563#define BTXHTSHORTGI 0x80
1499#define BTXHTNUMBERHT_LT F 0x300 1564#define BTXHTNUMBERHT_LTF 0x300
1500#define BTXHTCRC8 0x3fc00 1565#define BTXHTCRC8 0x3fc00
1501#define BCOUNTERRESET 0x10000 1566#define BCOUNTERRESET 0x10000
1502#define BNUMOFOFDMTX 0xffff 1567#define BNUMOFOFDMTX 0xffff
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
index ffd8e04c4028..669b1168dbec 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.c
@@ -61,7 +61,7 @@ void rtl92c_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
61 } 61 }
62} 62}
63 63
64void rtl92c_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw, 64void rtl92ce_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
65 u8 *ppowerlevel) 65 u8 *ppowerlevel)
66{ 66{
67 struct rtl_priv *rtlpriv = rtl_priv(hw); 67 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -410,7 +410,7 @@ static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw,
410 } 410 }
411} 411}
412 412
413void rtl92c_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, 413void rtl92ce_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
414 u8 *ppowerlevel, u8 channel) 414 u8 *ppowerlevel, u8 channel)
415{ 415{
416 u32 writeVal[2], powerBase0[2], powerBase1[2]; 416 u32 writeVal[2], powerBase0[2], powerBase1[2];
@@ -430,7 +430,7 @@ void rtl92c_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
430 } 430 }
431} 431}
432 432
433bool rtl92c_phy_rf6052_config(struct ieee80211_hw *hw) 433bool rtl92ce_phy_rf6052_config(struct ieee80211_hw *hw)
434{ 434{
435 struct rtl_priv *rtlpriv = rtl_priv(hw); 435 struct rtl_priv *rtlpriv = rtl_priv(hw);
436 struct rtl_phy *rtlphy = &(rtlpriv->phy); 436 struct rtl_phy *rtlphy = &(rtlpriv->phy);
@@ -484,11 +484,11 @@ static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
484 484
485 switch (rfpath) { 485 switch (rfpath) {
486 case RF90_PATH_A: 486 case RF90_PATH_A:
487 rtstatus = rtl92c_phy_config_rf_with_headerfile(hw, 487 rtstatus = rtl92ce_phy_config_rf_with_headerfile(hw,
488 (enum radio_path) rfpath); 488 (enum radio_path) rfpath);
489 break; 489 break;
490 case RF90_PATH_B: 490 case RF90_PATH_B:
491 rtstatus = rtl92c_phy_config_rf_with_headerfile(hw, 491 rtstatus = rtl92ce_phy_config_rf_with_headerfile(hw,
492 (enum radio_path) rfpath); 492 (enum radio_path) rfpath);
493 break; 493 break;
494 case RF90_PATH_C: 494 case RF90_PATH_C:
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.h b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.h
index d3014f99bb7b..3aa520c1c171 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/rf.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/rf.h
@@ -40,5 +40,8 @@ extern void rtl92c_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
40 u8 *ppowerlevel); 40 u8 *ppowerlevel);
41extern void rtl92c_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw, 41extern void rtl92c_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
42 u8 *ppowerlevel, u8 channel); 42 u8 *ppowerlevel, u8 channel);
43extern bool rtl92c_phy_rf6052_config(struct ieee80211_hw *hw); 43bool rtl92ce_phy_rf6052_config(struct ieee80211_hw *hw);
44bool rtl92ce_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
45 enum radio_path rfpath);
46
44#endif 47#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c
index b366e8862929..b1cc4d44f534 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c
@@ -37,6 +37,7 @@
37#include "phy.h" 37#include "phy.h"
38#include "dm.h" 38#include "dm.h"
39#include "hw.h" 39#include "hw.h"
40#include "rf.h"
40#include "sw.h" 41#include "sw.h"
41#include "trx.h" 42#include "trx.h"
42#include "led.h" 43#include "led.h"
@@ -46,13 +47,13 @@ int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
46 struct rtl_priv *rtlpriv = rtl_priv(hw); 47 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
48 49
49 rtlpriv->dm.b_dm_initialgain_enable = 1; 50 rtlpriv->dm.dm_initialgain_enable = 1;
50 rtlpriv->dm.dm_flag = 0; 51 rtlpriv->dm.dm_flag = 0;
51 rtlpriv->dm.b_disable_framebursting = 0;; 52 rtlpriv->dm.disable_framebursting = 0;
52 rtlpriv->dm.thermalvalue = 0; 53 rtlpriv->dm.thermalvalue = 0;
53 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13); 54 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
54 55
55 rtlpci->receive_config = (RCR_APPFCS | 56 rtlpci->receive_config = (RCR_APP_FCS |
56 RCR_AMF | 57 RCR_AMF |
57 RCR_ADF | 58 RCR_ADF |
58 RCR_APP_MIC | 59 RCR_APP_MIC |
@@ -122,7 +123,7 @@ static struct rtl_hal_ops rtl8192ce_hal_ops = {
122 .switch_channel = rtl92c_phy_sw_chnl, 123 .switch_channel = rtl92c_phy_sw_chnl,
123 .dm_watchdog = rtl92c_dm_watchdog, 124 .dm_watchdog = rtl92c_dm_watchdog,
124 .scan_operation_backup = rtl92c_phy_scan_operation_backup, 125 .scan_operation_backup = rtl92c_phy_scan_operation_backup,
125 .set_rf_power_state = rtl92c_phy_set_rf_power_state, 126 .set_rf_power_state = rtl92ce_phy_set_rf_power_state,
126 .led_control = rtl92ce_led_control, 127 .led_control = rtl92ce_led_control,
127 .set_desc = rtl92ce_set_desc, 128 .set_desc = rtl92ce_set_desc,
128 .get_desc = rtl92ce_get_desc, 129 .get_desc = rtl92ce_get_desc,
@@ -133,8 +134,17 @@ static struct rtl_hal_ops rtl8192ce_hal_ops = {
133 .deinit_sw_leds = rtl92ce_deinit_sw_leds, 134 .deinit_sw_leds = rtl92ce_deinit_sw_leds,
134 .get_bbreg = rtl92c_phy_query_bb_reg, 135 .get_bbreg = rtl92c_phy_query_bb_reg,
135 .set_bbreg = rtl92c_phy_set_bb_reg, 136 .set_bbreg = rtl92c_phy_set_bb_reg,
136 .get_rfreg = rtl92c_phy_query_rf_reg, 137 .get_rfreg = rtl92ce_phy_query_rf_reg,
137 .set_rfreg = rtl92c_phy_set_rf_reg, 138 .set_rfreg = rtl92ce_phy_set_rf_reg,
139 .cmd_send_packet = _rtl92c_cmd_send_packet,
140 .phy_rf6052_config = rtl92ce_phy_rf6052_config,
141 .phy_rf6052_set_cck_txpower = rtl92ce_phy_rf6052_set_cck_txpower,
142 .phy_rf6052_set_ofdm_txpower = rtl92ce_phy_rf6052_set_ofdm_txpower,
143 .config_bb_with_headerfile = _rtl92ce_phy_config_bb_with_headerfile,
144 .config_bb_with_pgheaderfile = _rtl92ce_phy_config_bb_with_pgheaderfile,
145 .phy_lc_calibrate = _rtl92ce_phy_lc_calibrate,
146 .phy_set_bw_mode_callback = rtl92ce_phy_set_bw_mode_callback,
147 .dm_dynamic_txpower = rtl92ce_dm_dynamic_txpower,
138}; 148};
139 149
140static struct rtl_mod_params rtl92ce_mod_params = { 150static struct rtl_mod_params rtl92ce_mod_params = {
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/sw.h b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.h
index de1198c38d4e..36e657668c1e 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/sw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.h
@@ -33,5 +33,19 @@
33int rtl92c_init_sw_vars(struct ieee80211_hw *hw); 33int rtl92c_init_sw_vars(struct ieee80211_hw *hw);
34void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw); 34void rtl92c_deinit_sw_vars(struct ieee80211_hw *hw);
35void rtl92c_init_var_map(struct ieee80211_hw *hw); 35void rtl92c_init_var_map(struct ieee80211_hw *hw);
36bool _rtl92c_cmd_send_packet(struct ieee80211_hw *hw,
37 struct sk_buff *skb);
38void rtl92ce_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
39 u8 *ppowerlevel);
40void rtl92ce_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
41 u8 *ppowerlevel, u8 channel);
42bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
43 u8 configtype);
44bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
45 u8 configtype);
46void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t);
47u32 rtl92ce_phy_query_rf_reg(struct ieee80211_hw *hw,
48 enum radio_path rfpath, u32 regaddr, u32 bitmask);
49void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
36 50
37#endif 51#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
index bf5852f2d634..aa2b5815600f 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.c
@@ -36,7 +36,7 @@
36#include "trx.h" 36#include "trx.h"
37#include "led.h" 37#include "led.h"
38 38
39static enum rtl_desc_qsel _rtl92ce_map_hwqueue_to_fwqueue(u16 fc, 39static enum rtl_desc_qsel _rtl92ce_map_hwqueue_to_fwqueue(__le16 fc,
40 unsigned int 40 unsigned int
41 skb_queue) 41 skb_queue)
42{ 42{
@@ -245,24 +245,24 @@ static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
245 struct rtl_stats *pstats, 245 struct rtl_stats *pstats,
246 struct rx_desc_92c *pdesc, 246 struct rx_desc_92c *pdesc,
247 struct rx_fwinfo_92c *p_drvinfo, 247 struct rx_fwinfo_92c *p_drvinfo,
248 bool bpacket_match_bssid, 248 bool packet_match_bssid,
249 bool bpacket_toself, 249 bool packet_toself,
250 bool b_packet_beacon) 250 bool packet_beacon)
251{ 251{
252 struct rtl_priv *rtlpriv = rtl_priv(hw); 252 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 struct phy_sts_cck_8192s_t *cck_buf; 253 struct phy_sts_cck_8192s_t *cck_buf;
254 s8 rx_pwr_all, rx_pwr[4]; 254 s8 rx_pwr_all, rx_pwr[4];
255 u8 rf_rx_num, evm, pwdb_all; 255 u8 evm, pwdb_all, rf_rx_num = 0;
256 u8 i, max_spatial_stream; 256 u8 i, max_spatial_stream;
257 u32 rssi, total_rssi; 257 u32 rssi, total_rssi = 0;
258 bool is_cck_rate; 258 bool is_cck_rate;
259 259
260 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc); 260 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc);
261 pstats->b_packet_matchbssid = bpacket_match_bssid; 261 pstats->packet_matchbssid = packet_match_bssid;
262 pstats->b_packet_toself = bpacket_toself; 262 pstats->packet_toself = packet_toself;
263 pstats->b_is_cck = is_cck_rate; 263 pstats->is_cck = is_cck_rate;
264 pstats->b_packet_beacon = b_packet_beacon; 264 pstats->packet_beacon = packet_beacon;
265 pstats->b_is_cck = is_cck_rate; 265 pstats->is_cck = is_cck_rate;
266 pstats->rx_mimo_signalquality[0] = -1; 266 pstats->rx_mimo_signalquality[0] = -1;
267 pstats->rx_mimo_signalquality[1] = -1; 267 pstats->rx_mimo_signalquality[1] = -1;
268 268
@@ -315,7 +315,7 @@ static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
315 pstats->rx_pwdb_all = pwdb_all; 315 pstats->rx_pwdb_all = pwdb_all;
316 pstats->recvsignalpower = rx_pwr_all; 316 pstats->recvsignalpower = rx_pwr_all;
317 317
318 if (bpacket_match_bssid) { 318 if (packet_match_bssid) {
319 u8 sq; 319 u8 sq;
320 if (pstats->rx_pwdb_all > 40) 320 if (pstats->rx_pwdb_all > 40)
321 sq = 100; 321 sq = 100;
@@ -334,10 +334,10 @@ static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
334 pstats->rx_mimo_signalquality[1] = -1; 334 pstats->rx_mimo_signalquality[1] = -1;
335 } 335 }
336 } else { 336 } else {
337 rtlpriv->dm.brfpath_rxenable[0] = 337 rtlpriv->dm.rfpath_rxenable[0] =
338 rtlpriv->dm.brfpath_rxenable[1] = true; 338 rtlpriv->dm.rfpath_rxenable[1] = true;
339 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) { 339 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
340 if (rtlpriv->dm.brfpath_rxenable[i]) 340 if (rtlpriv->dm.rfpath_rxenable[i])
341 rf_rx_num++; 341 rf_rx_num++;
342 342
343 rx_pwr[i] = 343 rx_pwr[i] =
@@ -347,7 +347,7 @@ static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
347 rtlpriv->stats.rx_snr_db[i] = 347 rtlpriv->stats.rx_snr_db[i] =
348 (long)(p_drvinfo->rxsnr[i] / 2); 348 (long)(p_drvinfo->rxsnr[i] / 2);
349 349
350 if (bpacket_match_bssid) 350 if (packet_match_bssid)
351 pstats->rx_mimo_signalstrength[i] = (u8) rssi; 351 pstats->rx_mimo_signalstrength[i] = (u8) rssi;
352 } 352 }
353 353
@@ -366,7 +366,7 @@ static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
366 for (i = 0; i < max_spatial_stream; i++) { 366 for (i = 0; i < max_spatial_stream; i++) {
367 evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]); 367 evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]);
368 368
369 if (bpacket_match_bssid) { 369 if (packet_match_bssid) {
370 if (i == 0) 370 if (i == 0)
371 pstats->signalquality = 371 pstats->signalquality =
372 (u8) (evm & 0xff); 372 (u8) (evm & 0xff);
@@ -393,7 +393,7 @@ static void _rtl92ce_process_ui_rssi(struct ieee80211_hw *hw,
393 u8 rfpath; 393 u8 rfpath;
394 u32 last_rssi, tmpval; 394 u32 last_rssi, tmpval;
395 395
396 if (pstats->b_packet_toself || pstats->b_packet_beacon) { 396 if (pstats->packet_toself || pstats->packet_beacon) {
397 rtlpriv->stats.rssi_calculate_cnt++; 397 rtlpriv->stats.rssi_calculate_cnt++;
398 398
399 if (rtlpriv->stats.ui_rssi.total_num++ >= 399 if (rtlpriv->stats.ui_rssi.total_num++ >=
@@ -421,7 +421,7 @@ static void _rtl92ce_process_ui_rssi(struct ieee80211_hw *hw,
421 pstats->rssi = rtlpriv->stats.signal_strength; 421 pstats->rssi = rtlpriv->stats.signal_strength;
422 } 422 }
423 423
424 if (!pstats->b_is_cck && pstats->b_packet_toself) { 424 if (!pstats->is_cck && pstats->packet_toself) {
425 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath; 425 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
426 rfpath++) { 426 rfpath++) {
427 427
@@ -463,7 +463,7 @@ static void _rtl92ce_update_rxsignalstatistics(struct ieee80211_hw *hw,
463 struct rtl_stats *pstats) 463 struct rtl_stats *pstats)
464{ 464{
465 struct rtl_priv *rtlpriv = rtl_priv(hw); 465 struct rtl_priv *rtlpriv = rtl_priv(hw);
466 int weighting; 466 int weighting = 0;
467 467
468 if (rtlpriv->stats.recv_signal_power == 0) 468 if (rtlpriv->stats.recv_signal_power == 0)
469 rtlpriv->stats.recv_signal_power = pstats->recvsignalpower; 469 rtlpriv->stats.recv_signal_power = pstats->recvsignalpower;
@@ -493,7 +493,7 @@ static void _rtl92ce_process_pwdb(struct ieee80211_hw *hw,
493 rtlpriv->dm.undecorated_smoothed_pwdb; 493 rtlpriv->dm.undecorated_smoothed_pwdb;
494 } 494 }
495 495
496 if (pstats->b_packet_toself || pstats->b_packet_beacon) { 496 if (pstats->packet_toself || pstats->packet_beacon) {
497 if (undecorated_smoothed_pwdb < 0) 497 if (undecorated_smoothed_pwdb < 0)
498 undecorated_smoothed_pwdb = pstats->rx_pwdb_all; 498 undecorated_smoothed_pwdb = pstats->rx_pwdb_all;
499 499
@@ -525,7 +525,7 @@ static void _rtl92ce_process_ui_link_quality(struct ieee80211_hw *hw,
525 u32 last_evm, n_spatialstream, tmpval; 525 u32 last_evm, n_spatialstream, tmpval;
526 526
527 if (pstats->signalquality != 0) { 527 if (pstats->signalquality != 0) {
528 if (pstats->b_packet_toself || pstats->b_packet_beacon) { 528 if (pstats->packet_toself || pstats->packet_beacon) {
529 529
530 if (rtlpriv->stats.ui_link_quality.total_num++ >= 530 if (rtlpriv->stats.ui_link_quality.total_num++ >=
531 PHY_LINKQUALITY_SLID_WIN_MAX) { 531 PHY_LINKQUALITY_SLID_WIN_MAX) {
@@ -595,8 +595,8 @@ static void _rtl92ce_process_phyinfo(struct ieee80211_hw *hw,
595 struct rtl_stats *pcurrent_stats) 595 struct rtl_stats *pcurrent_stats)
596{ 596{
597 597
598 if (!pcurrent_stats->b_packet_matchbssid && 598 if (!pcurrent_stats->packet_matchbssid &&
599 !pcurrent_stats->b_packet_beacon) 599 !pcurrent_stats->packet_beacon)
600 return; 600 return;
601 601
602 _rtl92ce_process_ui_rssi(hw, pcurrent_stats); 602 _rtl92ce_process_ui_rssi(hw, pcurrent_stats);
@@ -617,34 +617,36 @@ static void _rtl92ce_translate_rx_signal_stuff(struct ieee80211_hw *hw,
617 u8 *tmp_buf; 617 u8 *tmp_buf;
618 u8 *praddr; 618 u8 *praddr;
619 u8 *psaddr; 619 u8 *psaddr;
620 u16 fc, type; 620 __le16 fc;
621 bool b_packet_matchbssid, b_packet_toself, b_packet_beacon; 621 u16 type, c_fc;
622 bool packet_matchbssid, packet_toself, packet_beacon;
622 623
623 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift; 624 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
624 625
625 hdr = (struct ieee80211_hdr *)tmp_buf; 626 hdr = (struct ieee80211_hdr *)tmp_buf;
626 fc = le16_to_cpu(hdr->frame_control); 627 fc = hdr->frame_control;
628 c_fc = le16_to_cpu(fc);
627 type = WLAN_FC_GET_TYPE(fc); 629 type = WLAN_FC_GET_TYPE(fc);
628 praddr = hdr->addr1; 630 praddr = hdr->addr1;
629 psaddr = hdr->addr2; 631 psaddr = hdr->addr2;
630 632
631 b_packet_matchbssid = 633 packet_matchbssid =
632 ((IEEE80211_FTYPE_CTL != type) && 634 ((IEEE80211_FTYPE_CTL != type) &&
633 (!compare_ether_addr(mac->bssid, 635 (!compare_ether_addr(mac->bssid,
634 (fc & IEEE80211_FCTL_TODS) ? 636 (c_fc & IEEE80211_FCTL_TODS) ?
635 hdr->addr1 : (fc & IEEE80211_FCTL_FROMDS) ? 637 hdr->addr1 : (c_fc & IEEE80211_FCTL_FROMDS) ?
636 hdr->addr2 : hdr->addr3)) && 638 hdr->addr2 : hdr->addr3)) &&
637 (!pstats->b_hwerror) && (!pstats->b_crc) && (!pstats->b_icv)); 639 (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv));
638 640
639 b_packet_toself = b_packet_matchbssid && 641 packet_toself = packet_matchbssid &&
640 (!compare_ether_addr(praddr, rtlefuse->dev_addr)); 642 (!compare_ether_addr(praddr, rtlefuse->dev_addr));
641 643
642 if (ieee80211_is_beacon(fc)) 644 if (ieee80211_is_beacon(fc))
643 b_packet_beacon = true; 645 packet_beacon = true;
644 646
645 _rtl92ce_query_rxphystatus(hw, pstats, pdesc, p_drvinfo, 647 _rtl92ce_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
646 b_packet_matchbssid, b_packet_toself, 648 packet_matchbssid, packet_toself,
647 b_packet_beacon); 649 packet_beacon);
648 650
649 _rtl92ce_process_phyinfo(hw, tmp_buf, pstats); 651 _rtl92ce_process_phyinfo(hw, tmp_buf, pstats);
650} 652}
@@ -662,14 +664,14 @@ bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
662 stats->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) * 664 stats->rx_drvinfo_size = (u8) GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
663 RX_DRV_INFO_SIZE_UNIT; 665 RX_DRV_INFO_SIZE_UNIT;
664 stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03); 666 stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
665 stats->b_icv = (u16) GET_RX_DESC_ICV(pdesc); 667 stats->icv = (u16) GET_RX_DESC_ICV(pdesc);
666 stats->b_crc = (u16) GET_RX_DESC_CRC32(pdesc); 668 stats->crc = (u16) GET_RX_DESC_CRC32(pdesc);
667 stats->b_hwerror = (stats->b_crc | stats->b_icv); 669 stats->hwerror = (stats->crc | stats->icv);
668 stats->decrypted = !GET_RX_DESC_SWDEC(pdesc); 670 stats->decrypted = !GET_RX_DESC_SWDEC(pdesc);
669 stats->rate = (u8) GET_RX_DESC_RXMCS(pdesc); 671 stats->rate = (u8) GET_RX_DESC_RXMCS(pdesc);
670 stats->b_shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc); 672 stats->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
671 stats->b_isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1); 673 stats->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
672 stats->b_isampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1) 674 stats->isampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1)
673 && (GET_RX_DESC_FAGGR(pdesc) == 1)); 675 && (GET_RX_DESC_FAGGR(pdesc) == 1));
674 stats->timestamp_low = GET_RX_DESC_TSFL(pdesc); 676 stats->timestamp_low = GET_RX_DESC_TSFL(pdesc);
675 stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc); 677 stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
@@ -689,7 +691,7 @@ bool rtl92ce_rx_query_desc(struct ieee80211_hw *hw,
689 if (GET_RX_DESC_RXHT(pdesc)) 691 if (GET_RX_DESC_RXHT(pdesc))
690 rx_status->flag |= RX_FLAG_HT; 692 rx_status->flag |= RX_FLAG_HT;
691 693
692 rx_status->flag |= RX_FLAG_TSFT; 694 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
693 695
694 if (stats->decrypted) 696 if (stats->decrypted)
695 rx_status->flag |= RX_FLAG_DECRYPTED; 697 rx_status->flag |= RX_FLAG_DECRYPTED;
@@ -727,27 +729,24 @@ void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
727 struct rtl_mac *mac = rtl_mac(rtl_priv(hw)); 729 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
728 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 730 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
729 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw)); 731 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
730 bool b_defaultadapter = true; 732 bool defaultadapter = true;
731 733 struct ieee80211_sta *sta;
732 struct ieee80211_sta *sta = ieee80211_find_sta(mac->vif, mac->bssid);
733
734 u8 *pdesc = (u8 *) pdesc_tx; 734 u8 *pdesc = (u8 *) pdesc_tx;
735 struct rtl_tcb_desc tcb_desc; 735 struct rtl_tcb_desc tcb_desc;
736 u8 *qc = ieee80211_get_qos_ctl(hdr); 736 u8 *qc = ieee80211_get_qos_ctl(hdr);
737 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 737 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
738 u16 seq_number; 738 u16 seq_number;
739 u16 fc = le16_to_cpu(hdr->frame_control); 739 __le16 fc = hdr->frame_control;
740 u8 rate_flag = info->control.rates[0].flags; 740 u8 rate_flag = info->control.rates[0].flags;
741 741
742 enum rtl_desc_qsel fw_qsel = 742 enum rtl_desc_qsel fw_qsel =
743 _rtl92ce_map_hwqueue_to_fwqueue(le16_to_cpu(hdr->frame_control), 743 _rtl92ce_map_hwqueue_to_fwqueue(fc, queue_index);
744 queue_index);
745 744
746 bool b_firstseg = ((hdr->seq_ctrl & 745 bool firstseg = ((hdr->seq_ctrl &
747 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0); 746 cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
748 747
749 bool b_lastseg = ((hdr->frame_control & 748 bool lastseg = ((hdr->frame_control &
750 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0); 749 cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
751 750
752 dma_addr_t mapping = pci_map_single(rtlpci->pdev, 751 dma_addr_t mapping = pci_map_single(rtlpci->pdev,
753 skb->data, skb->len, 752 skb->data, skb->len,
@@ -759,7 +758,7 @@ void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
759 758
760 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_92c)); 759 CLEAR_PCI_TX_DESC_CONTENT(pdesc, sizeof(struct tx_desc_92c));
761 760
762 if (b_firstseg) { 761 if (firstseg) {
763 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN); 762 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
764 763
765 SET_TX_DESC_TX_RATE(pdesc, tcb_desc.hw_rate); 764 SET_TX_DESC_TX_RATE(pdesc, tcb_desc.hw_rate);
@@ -774,25 +773,25 @@ void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
774 } 773 }
775 SET_TX_DESC_SEQ(pdesc, seq_number); 774 SET_TX_DESC_SEQ(pdesc, seq_number);
776 775
777 SET_TX_DESC_RTS_ENABLE(pdesc, ((tcb_desc.b_rts_enable && 776 SET_TX_DESC_RTS_ENABLE(pdesc, ((tcb_desc.rts_enable &&
778 !tcb_desc. 777 !tcb_desc.
779 b_cts_enable) ? 1 : 0)); 778 cts_enable) ? 1 : 0));
780 SET_TX_DESC_HW_RTS_ENABLE(pdesc, 779 SET_TX_DESC_HW_RTS_ENABLE(pdesc,
781 ((tcb_desc.b_rts_enable 780 ((tcb_desc.rts_enable
782 || tcb_desc.b_cts_enable) ? 1 : 0)); 781 || tcb_desc.cts_enable) ? 1 : 0));
783 SET_TX_DESC_CTS2SELF(pdesc, ((tcb_desc.b_cts_enable) ? 1 : 0)); 782 SET_TX_DESC_CTS2SELF(pdesc, ((tcb_desc.cts_enable) ? 1 : 0));
784 SET_TX_DESC_RTS_STBC(pdesc, ((tcb_desc.b_rts_stbc) ? 1 : 0)); 783 SET_TX_DESC_RTS_STBC(pdesc, ((tcb_desc.rts_stbc) ? 1 : 0));
785 784
786 SET_TX_DESC_RTS_RATE(pdesc, tcb_desc.rts_rate); 785 SET_TX_DESC_RTS_RATE(pdesc, tcb_desc.rts_rate);
787 SET_TX_DESC_RTS_BW(pdesc, 0); 786 SET_TX_DESC_RTS_BW(pdesc, 0);
788 SET_TX_DESC_RTS_SC(pdesc, tcb_desc.rts_sc); 787 SET_TX_DESC_RTS_SC(pdesc, tcb_desc.rts_sc);
789 SET_TX_DESC_RTS_SHORT(pdesc, 788 SET_TX_DESC_RTS_SHORT(pdesc,
790 ((tcb_desc.rts_rate <= DESC92C_RATE54M) ? 789 ((tcb_desc.rts_rate <= DESC92C_RATE54M) ?
791 (tcb_desc.b_rts_use_shortpreamble ? 1 : 0) 790 (tcb_desc.rts_use_shortpreamble ? 1 : 0)
792 : (tcb_desc.b_rts_use_shortgi ? 1 : 0))); 791 : (tcb_desc.rts_use_shortgi ? 1 : 0)));
793 792
794 if (mac->bw_40) { 793 if (mac->bw_40) {
795 if (tcb_desc.b_packet_bw) { 794 if (tcb_desc.packet_bw) {
796 SET_TX_DESC_DATA_BW(pdesc, 1); 795 SET_TX_DESC_DATA_BW(pdesc, 1);
797 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3); 796 SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
798 } else { 797 } else {
@@ -811,10 +810,13 @@ void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
811 SET_TX_DESC_LINIP(pdesc, 0); 810 SET_TX_DESC_LINIP(pdesc, 0);
812 SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb->len); 811 SET_TX_DESC_PKT_SIZE(pdesc, (u16) skb->len);
813 812
813 rcu_read_lock();
814 sta = ieee80211_find_sta(mac->vif, mac->bssid);
814 if (sta) { 815 if (sta) {
815 u8 ampdu_density = sta->ht_cap.ampdu_density; 816 u8 ampdu_density = sta->ht_cap.ampdu_density;
816 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density); 817 SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
817 } 818 }
819 rcu_read_unlock();
818 820
819 if (info->control.hw_key) { 821 if (info->control.hw_key) {
820 struct ieee80211_key_conf *keyconf = 822 struct ieee80211_key_conf *keyconf =
@@ -854,14 +856,14 @@ void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
854 } 856 }
855 } 857 }
856 858
857 SET_TX_DESC_FIRST_SEG(pdesc, (b_firstseg ? 1 : 0)); 859 SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
858 SET_TX_DESC_LAST_SEG(pdesc, (b_lastseg ? 1 : 0)); 860 SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
859 861
860 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) skb->len); 862 SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16) skb->len);
861 863
862 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping)); 864 SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, cpu_to_le32(mapping));
863 865
864 if (rtlpriv->dm.b_useramask) { 866 if (rtlpriv->dm.useramask) {
865 SET_TX_DESC_RATE_ID(pdesc, tcb_desc.ratr_index); 867 SET_TX_DESC_RATE_ID(pdesc, tcb_desc.ratr_index);
866 SET_TX_DESC_MACID(pdesc, tcb_desc.mac_id); 868 SET_TX_DESC_MACID(pdesc, tcb_desc.mac_id);
867 } else { 869 } else {
@@ -869,16 +871,16 @@ void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
869 SET_TX_DESC_MACID(pdesc, tcb_desc.ratr_index); 871 SET_TX_DESC_MACID(pdesc, tcb_desc.ratr_index);
870 } 872 }
871 873
872 if ((!ieee80211_is_data_qos(fc)) && ppsc->b_leisure_ps && 874 if ((!ieee80211_is_data_qos(fc)) && ppsc->leisure_ps &&
873 ppsc->b_fwctrl_lps) { 875 ppsc->fwctrl_lps) {
874 SET_TX_DESC_HWSEQ_EN(pdesc, 1); 876 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
875 SET_TX_DESC_PKT_ID(pdesc, 8); 877 SET_TX_DESC_PKT_ID(pdesc, 8);
876 878
877 if (!b_defaultadapter) 879 if (!defaultadapter)
878 SET_TX_DESC_QOS(pdesc, 1); 880 SET_TX_DESC_QOS(pdesc, 1);
879 } 881 }
880 882
881 SET_TX_DESC_MORE_FRAG(pdesc, (b_lastseg ? 0 : 1)); 883 SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
882 884
883 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || 885 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
884 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) { 886 is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
@@ -889,8 +891,8 @@ void rtl92ce_tx_fill_desc(struct ieee80211_hw *hw,
889} 891}
890 892
891void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw, 893void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw,
892 u8 *pdesc, bool b_firstseg, 894 u8 *pdesc, bool firstseg,
893 bool b_lastseg, struct sk_buff *skb) 895 bool lastseg, struct sk_buff *skb)
894{ 896{
895 struct rtl_priv *rtlpriv = rtl_priv(hw); 897 struct rtl_priv *rtlpriv = rtl_priv(hw);
896 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw)); 898 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
@@ -901,11 +903,11 @@ void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw,
901 PCI_DMA_TODEVICE); 903 PCI_DMA_TODEVICE);
902 904
903 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data); 905 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
904 u16 fc = le16_to_cpu(hdr->frame_control); 906 __le16 fc = hdr->frame_control;
905 907
906 CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE); 908 CLEAR_PCI_TX_DESC_CONTENT(pdesc, TX_DESC_SIZE);
907 909
908 if (b_firstseg) 910 if (firstseg)
909 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN); 911 SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
910 912
911 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M); 913 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
@@ -1029,3 +1031,36 @@ void rtl92ce_tx_polling(struct ieee80211_hw *hw, unsigned int hw_queue)
1029 BIT(0) << (hw_queue)); 1031 BIT(0) << (hw_queue));
1030 } 1032 }
1031} 1033}
1034
1035bool _rtl92c_cmd_send_packet(struct ieee80211_hw *hw,
1036 struct sk_buff *skb)
1037{
1038 struct rtl_priv *rtlpriv = rtl_priv(hw);
1039 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1040 struct rtl8192_tx_ring *ring;
1041 struct rtl_tx_desc *pdesc;
1042 u8 own;
1043 unsigned long flags;
1044 struct sk_buff *pskb = NULL;
1045
1046 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1047
1048 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1049
1050 pskb = __skb_dequeue(&ring->queue);
1051 if (pskb)
1052 kfree_skb(pskb);
1053
1054 pdesc = &ring->desc[0];
1055 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc, true, HW_DESC_OWN);
1056
1057 rtlpriv->cfg->ops->fill_tx_cmddesc(hw, (u8 *) pdesc, 1, 1, skb);
1058
1059 __skb_queue_tail(&ring->queue, skb);
1060
1061 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1062
1063 rtlpriv->cfg->ops->tx_polling(hw, BEACON_QUEUE);
1064
1065 return true;
1066}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h
index 53d0e0a5af5c..803adcc80c96 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/trx.h
@@ -40,470 +40,494 @@
40#define USB_HWDESC_HEADER_LEN 32 40#define USB_HWDESC_HEADER_LEN 32
41#define CRCLENGTH 4 41#define CRCLENGTH 4
42 42
43/* Define a macro that takes a le32 word, converts it to host ordering,
44 * right shifts by a specified count, creates a mask of the specified
45 * bit count, and extracts that number of bits.
46 */
47
48#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
49 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
50 BIT_LEN_MASK_32(__mask))
51
52/* Define a macro that clears a bit field in an le32 word and
53 * sets the specified value into that bit field. The resulting
54 * value remains in le32 ordering; however, it is properly converted
55 * to host ordering for the clear and set operations before conversion
56 * back to le32.
57 */
58
59#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
60 (*(__le32 *)(__pdesc) = \
61 (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
62 (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
63 (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
64
65/* macros to read/write various fields in RX or TX descriptors */
66
43#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \ 67#define SET_TX_DESC_PKT_SIZE(__pdesc, __val) \
44 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 16, __val) 68 SET_BITS_OFFSET_LE(__pdesc, 0, 16, __val)
45#define SET_TX_DESC_OFFSET(__pdesc, __val) \ 69#define SET_TX_DESC_OFFSET(__pdesc, __val) \
46 SET_BITS_TO_LE_4BYTE(__pdesc, 16, 8, __val) 70 SET_BITS_OFFSET_LE(__pdesc, 16, 8, __val)
47#define SET_TX_DESC_BMC(__pdesc, __val) \ 71#define SET_TX_DESC_BMC(__pdesc, __val) \
48 SET_BITS_TO_LE_4BYTE(__pdesc, 24, 1, __val) 72 SET_BITS_OFFSET_LE(__pdesc, 24, 1, __val)
49#define SET_TX_DESC_HTC(__pdesc, __val) \ 73#define SET_TX_DESC_HTC(__pdesc, __val) \
50 SET_BITS_TO_LE_4BYTE(__pdesc, 25, 1, __val) 74 SET_BITS_OFFSET_LE(__pdesc, 25, 1, __val)
51#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \ 75#define SET_TX_DESC_LAST_SEG(__pdesc, __val) \
52 SET_BITS_TO_LE_4BYTE(__pdesc, 26, 1, __val) 76 SET_BITS_OFFSET_LE(__pdesc, 26, 1, __val)
53#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \ 77#define SET_TX_DESC_FIRST_SEG(__pdesc, __val) \
54 SET_BITS_TO_LE_4BYTE(__pdesc, 27, 1, __val) 78 SET_BITS_OFFSET_LE(__pdesc, 27, 1, __val)
55#define SET_TX_DESC_LINIP(__pdesc, __val) \ 79#define SET_TX_DESC_LINIP(__pdesc, __val) \
56 SET_BITS_TO_LE_4BYTE(__pdesc, 28, 1, __val) 80 SET_BITS_OFFSET_LE(__pdesc, 28, 1, __val)
57#define SET_TX_DESC_NO_ACM(__pdesc, __val) \ 81#define SET_TX_DESC_NO_ACM(__pdesc, __val) \
58 SET_BITS_TO_LE_4BYTE(__pdesc, 29, 1, __val) 82 SET_BITS_OFFSET_LE(__pdesc, 29, 1, __val)
59#define SET_TX_DESC_GF(__pdesc, __val) \ 83#define SET_TX_DESC_GF(__pdesc, __val) \
60 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val) 84 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
61#define SET_TX_DESC_OWN(__pdesc, __val) \ 85#define SET_TX_DESC_OWN(__pdesc, __val) \
62 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val) 86 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
63 87
64#define GET_TX_DESC_PKT_SIZE(__pdesc) \ 88#define GET_TX_DESC_PKT_SIZE(__pdesc) \
65 LE_BITS_TO_4BYTE(__pdesc, 0, 16) 89 SHIFT_AND_MASK_LE(__pdesc, 0, 16)
66#define GET_TX_DESC_OFFSET(__pdesc) \ 90#define GET_TX_DESC_OFFSET(__pdesc) \
67 LE_BITS_TO_4BYTE(__pdesc, 16, 8) 91 SHIFT_AND_MASK_LE(__pdesc, 16, 8)
68#define GET_TX_DESC_BMC(__pdesc) \ 92#define GET_TX_DESC_BMC(__pdesc) \
69 LE_BITS_TO_4BYTE(__pdesc, 24, 1) 93 SHIFT_AND_MASK_LE(__pdesc, 24, 1)
70#define GET_TX_DESC_HTC(__pdesc) \ 94#define GET_TX_DESC_HTC(__pdesc) \
71 LE_BITS_TO_4BYTE(__pdesc, 25, 1) 95 SHIFT_AND_MASK_LE(__pdesc, 25, 1)
72#define GET_TX_DESC_LAST_SEG(__pdesc) \ 96#define GET_TX_DESC_LAST_SEG(__pdesc) \
73 LE_BITS_TO_4BYTE(__pdesc, 26, 1) 97 SHIFT_AND_MASK_LE(__pdesc, 26, 1)
74#define GET_TX_DESC_FIRST_SEG(__pdesc) \ 98#define GET_TX_DESC_FIRST_SEG(__pdesc) \
75 LE_BITS_TO_4BYTE(__pdesc, 27, 1) 99 SHIFT_AND_MASK_LE(__pdesc, 27, 1)
76#define GET_TX_DESC_LINIP(__pdesc) \ 100#define GET_TX_DESC_LINIP(__pdesc) \
77 LE_BITS_TO_4BYTE(__pdesc, 28, 1) 101 SHIFT_AND_MASK_LE(__pdesc, 28, 1)
78#define GET_TX_DESC_NO_ACM(__pdesc) \ 102#define GET_TX_DESC_NO_ACM(__pdesc) \
79 LE_BITS_TO_4BYTE(__pdesc, 29, 1) 103 SHIFT_AND_MASK_LE(__pdesc, 29, 1)
80#define GET_TX_DESC_GF(__pdesc) \ 104#define GET_TX_DESC_GF(__pdesc) \
81 LE_BITS_TO_4BYTE(__pdesc, 30, 1) 105 SHIFT_AND_MASK_LE(__pdesc, 30, 1)
82#define GET_TX_DESC_OWN(__pdesc) \ 106#define GET_TX_DESC_OWN(__pdesc) \
83 LE_BITS_TO_4BYTE(__pdesc, 31, 1) 107 SHIFT_AND_MASK_LE(__pdesc, 31, 1)
84 108
85#define SET_TX_DESC_MACID(__pdesc, __val) \ 109#define SET_TX_DESC_MACID(__pdesc, __val) \
86 SET_BITS_TO_LE_4BYTE(__pdesc+4, 0, 5, __val) 110 SET_BITS_OFFSET_LE(__pdesc+4, 0, 5, __val)
87#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \ 111#define SET_TX_DESC_AGG_BREAK(__pdesc, __val) \
88 SET_BITS_TO_LE_4BYTE(__pdesc+4, 5, 1, __val) 112 SET_BITS_OFFSET_LE(__pdesc+4, 5, 1, __val)
89#define SET_TX_DESC_BK(__pdesc, __val) \ 113#define SET_TX_DESC_BK(__pdesc, __val) \
90 SET_BITS_TO_LE_4BYTE(__pdesc+4, 6, 1, __val) 114 SET_BITS_OFFSET_LE(__pdesc+4, 6, 1, __val)
91#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \ 115#define SET_TX_DESC_RDG_ENABLE(__pdesc, __val) \
92 SET_BITS_TO_LE_4BYTE(__pdesc+4, 7, 1, __val) 116 SET_BITS_OFFSET_LE(__pdesc+4, 7, 1, __val)
93#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \ 117#define SET_TX_DESC_QUEUE_SEL(__pdesc, __val) \
94 SET_BITS_TO_LE_4BYTE(__pdesc+4, 8, 5, __val) 118 SET_BITS_OFFSET_LE(__pdesc+4, 8, 5, __val)
95#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \ 119#define SET_TX_DESC_RDG_NAV_EXT(__pdesc, __val) \
96 SET_BITS_TO_LE_4BYTE(__pdesc+4, 13, 1, __val) 120 SET_BITS_OFFSET_LE(__pdesc+4, 13, 1, __val)
97#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \ 121#define SET_TX_DESC_LSIG_TXOP_EN(__pdesc, __val) \
98 SET_BITS_TO_LE_4BYTE(__pdesc+4, 14, 1, __val) 122 SET_BITS_OFFSET_LE(__pdesc+4, 14, 1, __val)
99#define SET_TX_DESC_PIFS(__pdesc, __val) \ 123#define SET_TX_DESC_PIFS(__pdesc, __val) \
100 SET_BITS_TO_LE_4BYTE(__pdesc+4, 15, 1, __val) 124 SET_BITS_OFFSET_LE(__pdesc+4, 15, 1, __val)
101#define SET_TX_DESC_RATE_ID(__pdesc, __val) \ 125#define SET_TX_DESC_RATE_ID(__pdesc, __val) \
102 SET_BITS_TO_LE_4BYTE(__pdesc+4, 16, 4, __val) 126 SET_BITS_OFFSET_LE(__pdesc+4, 16, 4, __val)
103#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \ 127#define SET_TX_DESC_NAV_USE_HDR(__pdesc, __val) \
104 SET_BITS_TO_LE_4BYTE(__pdesc+4, 20, 1, __val) 128 SET_BITS_OFFSET_LE(__pdesc+4, 20, 1, __val)
105#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \ 129#define SET_TX_DESC_EN_DESC_ID(__pdesc, __val) \
106 SET_BITS_TO_LE_4BYTE(__pdesc+4, 21, 1, __val) 130 SET_BITS_OFFSET_LE(__pdesc+4, 21, 1, __val)
107#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \ 131#define SET_TX_DESC_SEC_TYPE(__pdesc, __val) \
108 SET_BITS_TO_LE_4BYTE(__pdesc+4, 22, 2, __val) 132 SET_BITS_OFFSET_LE(__pdesc+4, 22, 2, __val)
109#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \ 133#define SET_TX_DESC_PKT_OFFSET(__pdesc, __val) \
110 SET_BITS_TO_LE_4BYTE(__pdesc+4, 24, 8, __val) 134 SET_BITS_OFFSET_LE(__pdesc+4, 24, 8, __val)
111 135
112#define GET_TX_DESC_MACID(__pdesc) \ 136#define GET_TX_DESC_MACID(__pdesc) \
113 LE_BITS_TO_4BYTE(__pdesc+4, 0, 5) 137 SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
114#define GET_TX_DESC_AGG_ENABLE(__pdesc) \ 138#define GET_TX_DESC_AGG_ENABLE(__pdesc) \
115 LE_BITS_TO_4BYTE(__pdesc+4, 5, 1) 139 SHIFT_AND_MASK_LE(__pdesc+4, 5, 1)
116#define GET_TX_DESC_AGG_BREAK(__pdesc) \ 140#define GET_TX_DESC_AGG_BREAK(__pdesc) \
117 LE_BITS_TO_4BYTE(__pdesc+4, 6, 1) 141 SHIFT_AND_MASK_LE(__pdesc+4, 6, 1)
118#define GET_TX_DESC_RDG_ENABLE(__pdesc) \ 142#define GET_TX_DESC_RDG_ENABLE(__pdesc) \
119 LE_BITS_TO_4BYTE(__pdesc+4, 7, 1) 143 SHIFT_AND_MASK_LE(__pdesc+4, 7, 1)
120#define GET_TX_DESC_QUEUE_SEL(__pdesc) \ 144#define GET_TX_DESC_QUEUE_SEL(__pdesc) \
121 LE_BITS_TO_4BYTE(__pdesc+4, 8, 5) 145 SHIFT_AND_MASK_LE(__pdesc+4, 8, 5)
122#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \ 146#define GET_TX_DESC_RDG_NAV_EXT(__pdesc) \
123 LE_BITS_TO_4BYTE(__pdesc+4, 13, 1) 147 SHIFT_AND_MASK_LE(__pdesc+4, 13, 1)
124#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \ 148#define GET_TX_DESC_LSIG_TXOP_EN(__pdesc) \
125 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1) 149 SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
126#define GET_TX_DESC_PIFS(__pdesc) \ 150#define GET_TX_DESC_PIFS(__pdesc) \
127 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1) 151 SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
128#define GET_TX_DESC_RATE_ID(__pdesc) \ 152#define GET_TX_DESC_RATE_ID(__pdesc) \
129 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4) 153 SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
130#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \ 154#define GET_TX_DESC_NAV_USE_HDR(__pdesc) \
131 LE_BITS_TO_4BYTE(__pdesc+4, 20, 1) 155 SHIFT_AND_MASK_LE(__pdesc+4, 20, 1)
132#define GET_TX_DESC_EN_DESC_ID(__pdesc) \ 156#define GET_TX_DESC_EN_DESC_ID(__pdesc) \
133 LE_BITS_TO_4BYTE(__pdesc+4, 21, 1) 157 SHIFT_AND_MASK_LE(__pdesc+4, 21, 1)
134#define GET_TX_DESC_SEC_TYPE(__pdesc) \ 158#define GET_TX_DESC_SEC_TYPE(__pdesc) \
135 LE_BITS_TO_4BYTE(__pdesc+4, 22, 2) 159 SHIFT_AND_MASK_LE(__pdesc+4, 22, 2)
136#define GET_TX_DESC_PKT_OFFSET(__pdesc) \ 160#define GET_TX_DESC_PKT_OFFSET(__pdesc) \
137 LE_BITS_TO_4BYTE(__pdesc+4, 24, 8) 161 SHIFT_AND_MASK_LE(__pdesc+4, 24, 8)
138 162
139#define SET_TX_DESC_RTS_RC(__pdesc, __val) \ 163#define SET_TX_DESC_RTS_RC(__pdesc, __val) \
140 SET_BITS_TO_LE_4BYTE(__pdesc+8, 0, 6, __val) 164 SET_BITS_OFFSET_LE(__pdesc+8, 0, 6, __val)
141#define SET_TX_DESC_DATA_RC(__pdesc, __val) \ 165#define SET_TX_DESC_DATA_RC(__pdesc, __val) \
142 SET_BITS_TO_LE_4BYTE(__pdesc+8, 6, 6, __val) 166 SET_BITS_OFFSET_LE(__pdesc+8, 6, 6, __val)
143#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \ 167#define SET_TX_DESC_BAR_RTY_TH(__pdesc, __val) \
144 SET_BITS_TO_LE_4BYTE(__pdesc+8, 14, 2, __val) 168 SET_BITS_OFFSET_LE(__pdesc+8, 14, 2, __val)
145#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \ 169#define SET_TX_DESC_MORE_FRAG(__pdesc, __val) \
146 SET_BITS_TO_LE_4BYTE(__pdesc+8, 17, 1, __val) 170 SET_BITS_OFFSET_LE(__pdesc+8, 17, 1, __val)
147#define SET_TX_DESC_RAW(__pdesc, __val) \ 171#define SET_TX_DESC_RAW(__pdesc, __val) \
148 SET_BITS_TO_LE_4BYTE(__pdesc+8, 18, 1, __val) 172 SET_BITS_OFFSET_LE(__pdesc+8, 18, 1, __val)
149#define SET_TX_DESC_CCX(__pdesc, __val) \ 173#define SET_TX_DESC_CCX(__pdesc, __val) \
150 SET_BITS_TO_LE_4BYTE(__pdesc+8, 19, 1, __val) 174 SET_BITS_OFFSET_LE(__pdesc+8, 19, 1, __val)
151#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \ 175#define SET_TX_DESC_AMPDU_DENSITY(__pdesc, __val) \
152 SET_BITS_TO_LE_4BYTE(__pdesc+8, 20, 3, __val) 176 SET_BITS_OFFSET_LE(__pdesc+8, 20, 3, __val)
153#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \ 177#define SET_TX_DESC_ANTSEL_A(__pdesc, __val) \
154 SET_BITS_TO_LE_4BYTE(__pdesc+8, 24, 1, __val) 178 SET_BITS_OFFSET_LE(__pdesc+8, 24, 1, __val)
155#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \ 179#define SET_TX_DESC_ANTSEL_B(__pdesc, __val) \
156 SET_BITS_TO_LE_4BYTE(__pdesc+8, 25, 1, __val) 180 SET_BITS_OFFSET_LE(__pdesc+8, 25, 1, __val)
157#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \ 181#define SET_TX_DESC_TX_ANT_CCK(__pdesc, __val) \
158 SET_BITS_TO_LE_4BYTE(__pdesc+8, 26, 2, __val) 182 SET_BITS_OFFSET_LE(__pdesc+8, 26, 2, __val)
159#define SET_TX_DESC_TX_ANTL(__pdesc, __val) \ 183#define SET_TX_DESC_TX_ANTL(__pdesc, __val) \
160 SET_BITS_TO_LE_4BYTE(__pdesc+8, 28, 2, __val) 184 SET_BITS_OFFSET_LE(__pdesc+8, 28, 2, __val)
161#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \ 185#define SET_TX_DESC_TX_ANT_HT(__pdesc, __val) \
162 SET_BITS_TO_LE_4BYTE(__pdesc+8, 30, 2, __val) 186 SET_BITS_OFFSET_LE(__pdesc+8, 30, 2, __val)
163 187
164#define GET_TX_DESC_RTS_RC(__pdesc) \ 188#define GET_TX_DESC_RTS_RC(__pdesc) \
165 LE_BITS_TO_4BYTE(__pdesc+8, 0, 6) 189 SHIFT_AND_MASK_LE(__pdesc+8, 0, 6)
166#define GET_TX_DESC_DATA_RC(__pdesc) \ 190#define GET_TX_DESC_DATA_RC(__pdesc) \
167 LE_BITS_TO_4BYTE(__pdesc+8, 6, 6) 191 SHIFT_AND_MASK_LE(__pdesc+8, 6, 6)
168#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \ 192#define GET_TX_DESC_BAR_RTY_TH(__pdesc) \
169 LE_BITS_TO_4BYTE(__pdesc+8, 14, 2) 193 SHIFT_AND_MASK_LE(__pdesc+8, 14, 2)
170#define GET_TX_DESC_MORE_FRAG(__pdesc) \ 194#define GET_TX_DESC_MORE_FRAG(__pdesc) \
171 LE_BITS_TO_4BYTE(__pdesc+8, 17, 1) 195 SHIFT_AND_MASK_LE(__pdesc+8, 17, 1)
172#define GET_TX_DESC_RAW(__pdesc) \ 196#define GET_TX_DESC_RAW(__pdesc) \
173 LE_BITS_TO_4BYTE(__pdesc+8, 18, 1) 197 SHIFT_AND_MASK_LE(__pdesc+8, 18, 1)
174#define GET_TX_DESC_CCX(__pdesc) \ 198#define GET_TX_DESC_CCX(__pdesc) \
175 LE_BITS_TO_4BYTE(__pdesc+8, 19, 1) 199 SHIFT_AND_MASK_LE(__pdesc+8, 19, 1)
176#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \ 200#define GET_TX_DESC_AMPDU_DENSITY(__pdesc) \
177 LE_BITS_TO_4BYTE(__pdesc+8, 20, 3) 201 SHIFT_AND_MASK_LE(__pdesc+8, 20, 3)
178#define GET_TX_DESC_ANTSEL_A(__pdesc) \ 202#define GET_TX_DESC_ANTSEL_A(__pdesc) \
179 LE_BITS_TO_4BYTE(__pdesc+8, 24, 1) 203 SHIFT_AND_MASK_LE(__pdesc+8, 24, 1)
180#define GET_TX_DESC_ANTSEL_B(__pdesc) \ 204#define GET_TX_DESC_ANTSEL_B(__pdesc) \
181 LE_BITS_TO_4BYTE(__pdesc+8, 25, 1) 205 SHIFT_AND_MASK_LE(__pdesc+8, 25, 1)
182#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \ 206#define GET_TX_DESC_TX_ANT_CCK(__pdesc) \
183 LE_BITS_TO_4BYTE(__pdesc+8, 26, 2) 207 SHIFT_AND_MASK_LE(__pdesc+8, 26, 2)
184#define GET_TX_DESC_TX_ANTL(__pdesc) \ 208#define GET_TX_DESC_TX_ANTL(__pdesc) \
185 LE_BITS_TO_4BYTE(__pdesc+8, 28, 2) 209 SHIFT_AND_MASK_LE(__pdesc+8, 28, 2)
186#define GET_TX_DESC_TX_ANT_HT(__pdesc) \ 210#define GET_TX_DESC_TX_ANT_HT(__pdesc) \
187 LE_BITS_TO_4BYTE(__pdesc+8, 30, 2) 211 SHIFT_AND_MASK_LE(__pdesc+8, 30, 2)
188 212
189#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \ 213#define SET_TX_DESC_NEXT_HEAP_PAGE(__pdesc, __val) \
190 SET_BITS_TO_LE_4BYTE(__pdesc+12, 0, 8, __val) 214 SET_BITS_OFFSET_LE(__pdesc+12, 0, 8, __val)
191#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \ 215#define SET_TX_DESC_TAIL_PAGE(__pdesc, __val) \
192 SET_BITS_TO_LE_4BYTE(__pdesc+12, 8, 8, __val) 216 SET_BITS_OFFSET_LE(__pdesc+12, 8, 8, __val)
193#define SET_TX_DESC_SEQ(__pdesc, __val) \ 217#define SET_TX_DESC_SEQ(__pdesc, __val) \
194 SET_BITS_TO_LE_4BYTE(__pdesc+12, 16, 12, __val) 218 SET_BITS_OFFSET_LE(__pdesc+12, 16, 12, __val)
195#define SET_TX_DESC_PKT_ID(__pdesc, __val) \ 219#define SET_TX_DESC_PKT_ID(__pdesc, __val) \
196 SET_BITS_TO_LE_4BYTE(__pdesc+12, 28, 4, __val) 220 SET_BITS_OFFSET_LE(__pdesc+12, 28, 4, __val)
197 221
198#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \ 222#define GET_TX_DESC_NEXT_HEAP_PAGE(__pdesc) \
199 LE_BITS_TO_4BYTE(__pdesc+12, 0, 8) 223 SHIFT_AND_MASK_LE(__pdesc+12, 0, 8)
200#define GET_TX_DESC_TAIL_PAGE(__pdesc) \ 224#define GET_TX_DESC_TAIL_PAGE(__pdesc) \
201 LE_BITS_TO_4BYTE(__pdesc+12, 8, 8) 225 SHIFT_AND_MASK_LE(__pdesc+12, 8, 8)
202#define GET_TX_DESC_SEQ(__pdesc) \ 226#define GET_TX_DESC_SEQ(__pdesc) \
203 LE_BITS_TO_4BYTE(__pdesc+12, 16, 12) 227 SHIFT_AND_MASK_LE(__pdesc+12, 16, 12)
204#define GET_TX_DESC_PKT_ID(__pdesc) \ 228#define GET_TX_DESC_PKT_ID(__pdesc) \
205 LE_BITS_TO_4BYTE(__pdesc+12, 28, 4) 229 SHIFT_AND_MASK_LE(__pdesc+12, 28, 4)
206 230
207#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \ 231#define SET_TX_DESC_RTS_RATE(__pdesc, __val) \
208 SET_BITS_TO_LE_4BYTE(__pdesc+16, 0, 5, __val) 232 SET_BITS_OFFSET_LE(__pdesc+16, 0, 5, __val)
209#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \ 233#define SET_TX_DESC_AP_DCFE(__pdesc, __val) \
210 SET_BITS_TO_LE_4BYTE(__pdesc+16, 5, 1, __val) 234 SET_BITS_OFFSET_LE(__pdesc+16, 5, 1, __val)
211#define SET_TX_DESC_QOS(__pdesc, __val) \ 235#define SET_TX_DESC_QOS(__pdesc, __val) \
212 SET_BITS_TO_LE_4BYTE(__pdesc+16, 6, 1, __val) 236 SET_BITS_OFFSET_LE(__pdesc+16, 6, 1, __val)
213#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \ 237#define SET_TX_DESC_HWSEQ_EN(__pdesc, __val) \
214 SET_BITS_TO_LE_4BYTE(__pdesc+16, 7, 1, __val) 238 SET_BITS_OFFSET_LE(__pdesc+16, 7, 1, __val)
215#define SET_TX_DESC_USE_RATE(__pdesc, __val) \ 239#define SET_TX_DESC_USE_RATE(__pdesc, __val) \
216 SET_BITS_TO_LE_4BYTE(__pdesc+16, 8, 1, __val) 240 SET_BITS_OFFSET_LE(__pdesc+16, 8, 1, __val)
217#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \ 241#define SET_TX_DESC_DISABLE_RTS_FB(__pdesc, __val) \
218 SET_BITS_TO_LE_4BYTE(__pdesc+16, 9, 1, __val) 242 SET_BITS_OFFSET_LE(__pdesc+16, 9, 1, __val)
219#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \ 243#define SET_TX_DESC_DISABLE_FB(__pdesc, __val) \
220 SET_BITS_TO_LE_4BYTE(__pdesc+16, 10, 1, __val) 244 SET_BITS_OFFSET_LE(__pdesc+16, 10, 1, __val)
221#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \ 245#define SET_TX_DESC_CTS2SELF(__pdesc, __val) \
222 SET_BITS_TO_LE_4BYTE(__pdesc+16, 11, 1, __val) 246 SET_BITS_OFFSET_LE(__pdesc+16, 11, 1, __val)
223#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \ 247#define SET_TX_DESC_RTS_ENABLE(__pdesc, __val) \
224 SET_BITS_TO_LE_4BYTE(__pdesc+16, 12, 1, __val) 248 SET_BITS_OFFSET_LE(__pdesc+16, 12, 1, __val)
225#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \ 249#define SET_TX_DESC_HW_RTS_ENABLE(__pdesc, __val) \
226 SET_BITS_TO_LE_4BYTE(__pdesc+16, 13, 1, __val) 250 SET_BITS_OFFSET_LE(__pdesc+16, 13, 1, __val)
227#define SET_TX_DESC_PORT_ID(__pdesc, __val) \ 251#define SET_TX_DESC_PORT_ID(__pdesc, __val) \
228 SET_BITS_TO_LE_4BYTE(__pdesc+16, 14, 1, __val) 252 SET_BITS_OFFSET_LE(__pdesc+16, 14, 1, __val)
229#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \ 253#define SET_TX_DESC_WAIT_DCTS(__pdesc, __val) \
230 SET_BITS_TO_LE_4BYTE(__pdesc+16, 18, 1, __val) 254 SET_BITS_OFFSET_LE(__pdesc+16, 18, 1, __val)
231#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \ 255#define SET_TX_DESC_CTS2AP_EN(__pdesc, __val) \
232 SET_BITS_TO_LE_4BYTE(__pdesc+16, 19, 1, __val) 256 SET_BITS_OFFSET_LE(__pdesc+16, 19, 1, __val)
233#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \ 257#define SET_TX_DESC_TX_SUB_CARRIER(__pdesc, __val) \
234 SET_BITS_TO_LE_4BYTE(__pdesc+16, 20, 2, __val) 258 SET_BITS_OFFSET_LE(__pdesc+16, 20, 2, __val)
235#define SET_TX_DESC_TX_STBC(__pdesc, __val) \ 259#define SET_TX_DESC_TX_STBC(__pdesc, __val) \
236 SET_BITS_TO_LE_4BYTE(__pdesc+16, 22, 2, __val) 260 SET_BITS_OFFSET_LE(__pdesc+16, 22, 2, __val)
237#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \ 261#define SET_TX_DESC_DATA_SHORT(__pdesc, __val) \
238 SET_BITS_TO_LE_4BYTE(__pdesc+16, 24, 1, __val) 262 SET_BITS_OFFSET_LE(__pdesc+16, 24, 1, __val)
239#define SET_TX_DESC_DATA_BW(__pdesc, __val) \ 263#define SET_TX_DESC_DATA_BW(__pdesc, __val) \
240 SET_BITS_TO_LE_4BYTE(__pdesc+16, 25, 1, __val) 264 SET_BITS_OFFSET_LE(__pdesc+16, 25, 1, __val)
241#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \ 265#define SET_TX_DESC_RTS_SHORT(__pdesc, __val) \
242 SET_BITS_TO_LE_4BYTE(__pdesc+16, 26, 1, __val) 266 SET_BITS_OFFSET_LE(__pdesc+16, 26, 1, __val)
243#define SET_TX_DESC_RTS_BW(__pdesc, __val) \ 267#define SET_TX_DESC_RTS_BW(__pdesc, __val) \
244 SET_BITS_TO_LE_4BYTE(__pdesc+16, 27, 1, __val) 268 SET_BITS_OFFSET_LE(__pdesc+16, 27, 1, __val)
245#define SET_TX_DESC_RTS_SC(__pdesc, __val) \ 269#define SET_TX_DESC_RTS_SC(__pdesc, __val) \
246 SET_BITS_TO_LE_4BYTE(__pdesc+16, 28, 2, __val) 270 SET_BITS_OFFSET_LE(__pdesc+16, 28, 2, __val)
247#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \ 271#define SET_TX_DESC_RTS_STBC(__pdesc, __val) \
248 SET_BITS_TO_LE_4BYTE(__pdesc+16, 30, 2, __val) 272 SET_BITS_OFFSET_LE(__pdesc+16, 30, 2, __val)
249 273
250#define GET_TX_DESC_RTS_RATE(__pdesc) \ 274#define GET_TX_DESC_RTS_RATE(__pdesc) \
251 LE_BITS_TO_4BYTE(__pdesc+16, 0, 5) 275 SHIFT_AND_MASK_LE(__pdesc+16, 0, 5)
252#define GET_TX_DESC_AP_DCFE(__pdesc) \ 276#define GET_TX_DESC_AP_DCFE(__pdesc) \
253 LE_BITS_TO_4BYTE(__pdesc+16, 5, 1) 277 SHIFT_AND_MASK_LE(__pdesc+16, 5, 1)
254#define GET_TX_DESC_QOS(__pdesc) \ 278#define GET_TX_DESC_QOS(__pdesc) \
255 LE_BITS_TO_4BYTE(__pdesc+16, 6, 1) 279 SHIFT_AND_MASK_LE(__pdesc+16, 6, 1)
256#define GET_TX_DESC_HWSEQ_EN(__pdesc) \ 280#define GET_TX_DESC_HWSEQ_EN(__pdesc) \
257 LE_BITS_TO_4BYTE(__pdesc+16, 7, 1) 281 SHIFT_AND_MASK_LE(__pdesc+16, 7, 1)
258#define GET_TX_DESC_USE_RATE(__pdesc) \ 282#define GET_TX_DESC_USE_RATE(__pdesc) \
259 LE_BITS_TO_4BYTE(__pdesc+16, 8, 1) 283 SHIFT_AND_MASK_LE(__pdesc+16, 8, 1)
260#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \ 284#define GET_TX_DESC_DISABLE_RTS_FB(__pdesc) \
261 LE_BITS_TO_4BYTE(__pdesc+16, 9, 1) 285 SHIFT_AND_MASK_LE(__pdesc+16, 9, 1)
262#define GET_TX_DESC_DISABLE_FB(__pdesc) \ 286#define GET_TX_DESC_DISABLE_FB(__pdesc) \
263 LE_BITS_TO_4BYTE(__pdesc+16, 10, 1) 287 SHIFT_AND_MASK_LE(__pdesc+16, 10, 1)
264#define GET_TX_DESC_CTS2SELF(__pdesc) \ 288#define GET_TX_DESC_CTS2SELF(__pdesc) \
265 LE_BITS_TO_4BYTE(__pdesc+16, 11, 1) 289 SHIFT_AND_MASK_LE(__pdesc+16, 11, 1)
266#define GET_TX_DESC_RTS_ENABLE(__pdesc) \ 290#define GET_TX_DESC_RTS_ENABLE(__pdesc) \
267 LE_BITS_TO_4BYTE(__pdesc+16, 12, 1) 291 SHIFT_AND_MASK_LE(__pdesc+16, 12, 1)
268#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \ 292#define GET_TX_DESC_HW_RTS_ENABLE(__pdesc) \
269 LE_BITS_TO_4BYTE(__pdesc+16, 13, 1) 293 SHIFT_AND_MASK_LE(__pdesc+16, 13, 1)
270#define GET_TX_DESC_PORT_ID(__pdesc) \ 294#define GET_TX_DESC_PORT_ID(__pdesc) \
271 LE_BITS_TO_4BYTE(__pdesc+16, 14, 1) 295 SHIFT_AND_MASK_LE(__pdesc+16, 14, 1)
272#define GET_TX_DESC_WAIT_DCTS(__pdesc) \ 296#define GET_TX_DESC_WAIT_DCTS(__pdesc) \
273 LE_BITS_TO_4BYTE(__pdesc+16, 18, 1) 297 SHIFT_AND_MASK_LE(__pdesc+16, 18, 1)
274#define GET_TX_DESC_CTS2AP_EN(__pdesc) \ 298#define GET_TX_DESC_CTS2AP_EN(__pdesc) \
275 LE_BITS_TO_4BYTE(__pdesc+16, 19, 1) 299 SHIFT_AND_MASK_LE(__pdesc+16, 19, 1)
276#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \ 300#define GET_TX_DESC_TX_SUB_CARRIER(__pdesc) \
277 LE_BITS_TO_4BYTE(__pdesc+16, 20, 2) 301 SHIFT_AND_MASK_LE(__pdesc+16, 20, 2)
278#define GET_TX_DESC_TX_STBC(__pdesc) \ 302#define GET_TX_DESC_TX_STBC(__pdesc) \
279 LE_BITS_TO_4BYTE(__pdesc+16, 22, 2) 303 SHIFT_AND_MASK_LE(__pdesc+16, 22, 2)
280#define GET_TX_DESC_DATA_SHORT(__pdesc) \ 304#define GET_TX_DESC_DATA_SHORT(__pdesc) \
281 LE_BITS_TO_4BYTE(__pdesc+16, 24, 1) 305 SHIFT_AND_MASK_LE(__pdesc+16, 24, 1)
282#define GET_TX_DESC_DATA_BW(__pdesc) \ 306#define GET_TX_DESC_DATA_BW(__pdesc) \
283 LE_BITS_TO_4BYTE(__pdesc+16, 25, 1) 307 SHIFT_AND_MASK_LE(__pdesc+16, 25, 1)
284#define GET_TX_DESC_RTS_SHORT(__pdesc) \ 308#define GET_TX_DESC_RTS_SHORT(__pdesc) \
285 LE_BITS_TO_4BYTE(__pdesc+16, 26, 1) 309 SHIFT_AND_MASK_LE(__pdesc+16, 26, 1)
286#define GET_TX_DESC_RTS_BW(__pdesc) \ 310#define GET_TX_DESC_RTS_BW(__pdesc) \
287 LE_BITS_TO_4BYTE(__pdesc+16, 27, 1) 311 SHIFT_AND_MASK_LE(__pdesc+16, 27, 1)
288#define GET_TX_DESC_RTS_SC(__pdesc) \ 312#define GET_TX_DESC_RTS_SC(__pdesc) \
289 LE_BITS_TO_4BYTE(__pdesc+16, 28, 2) 313 SHIFT_AND_MASK_LE(__pdesc+16, 28, 2)
290#define GET_TX_DESC_RTS_STBC(__pdesc) \ 314#define GET_TX_DESC_RTS_STBC(__pdesc) \
291 LE_BITS_TO_4BYTE(__pdesc+16, 30, 2) 315 SHIFT_AND_MASK_LE(__pdesc+16, 30, 2)
292 316
293#define SET_TX_DESC_TX_RATE(__pdesc, __val) \ 317#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
294 SET_BITS_TO_LE_4BYTE(__pdesc+20, 0, 6, __val) 318 SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
295#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \ 319#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
296 SET_BITS_TO_LE_4BYTE(__pdesc+20, 6, 1, __val) 320 SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
297#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \ 321#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
298 SET_BITS_TO_LE_4BYTE(__pdesc+20, 7, 1, __val) 322 SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
299#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \ 323#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc, __val) \
300 SET_BITS_TO_LE_4BYTE(__pdesc+20, 8, 5, __val) 324 SET_BITS_OFFSET_LE(__pdesc+20, 8, 5, __val)
301#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \ 325#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc, __val) \
302 SET_BITS_TO_LE_4BYTE(__pdesc+20, 13, 4, __val) 326 SET_BITS_OFFSET_LE(__pdesc+20, 13, 4, __val)
303#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \ 327#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc, __val) \
304 SET_BITS_TO_LE_4BYTE(__pdesc+20, 17, 1, __val) 328 SET_BITS_OFFSET_LE(__pdesc+20, 17, 1, __val)
305#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \ 329#define SET_TX_DESC_DATA_RETRY_LIMIT(__pdesc, __val) \
306 SET_BITS_TO_LE_4BYTE(__pdesc+20, 18, 6, __val) 330 SET_BITS_OFFSET_LE(__pdesc+20, 18, 6, __val)
307#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \ 331#define SET_TX_DESC_USB_TXAGG_NUM(__pdesc, __val) \
308 SET_BITS_TO_LE_4BYTE(__pdesc+20, 24, 8, __val) 332 SET_BITS_OFFSET_LE(__pdesc+20, 24, 8, __val)
309 333
310#define GET_TX_DESC_TX_RATE(__pdesc) \ 334#define GET_TX_DESC_TX_RATE(__pdesc) \
311 LE_BITS_TO_4BYTE(__pdesc+20, 0, 6) 335 SHIFT_AND_MASK_LE(__pdesc+20, 0, 6)
312#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \ 336#define GET_TX_DESC_DATA_SHORTGI(__pdesc) \
313 LE_BITS_TO_4BYTE(__pdesc+20, 6, 1) 337 SHIFT_AND_MASK_LE(__pdesc+20, 6, 1)
314#define GET_TX_DESC_CCX_TAG(__pdesc) \ 338#define GET_TX_DESC_CCX_TAG(__pdesc) \
315 LE_BITS_TO_4BYTE(__pdesc+20, 7, 1) 339 SHIFT_AND_MASK_LE(__pdesc+20, 7, 1)
316#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \ 340#define GET_TX_DESC_DATA_RATE_FB_LIMIT(__pdesc) \
317 LE_BITS_TO_4BYTE(__pdesc+20, 8, 5) 341 SHIFT_AND_MASK_LE(__pdesc+20, 8, 5)
318#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \ 342#define GET_TX_DESC_RTS_RATE_FB_LIMIT(__pdesc) \
319 LE_BITS_TO_4BYTE(__pdesc+20, 13, 4) 343 SHIFT_AND_MASK_LE(__pdesc+20, 13, 4)
320#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \ 344#define GET_TX_DESC_RETRY_LIMIT_ENABLE(__pdesc) \
321 LE_BITS_TO_4BYTE(__pdesc+20, 17, 1) 345 SHIFT_AND_MASK_LE(__pdesc+20, 17, 1)
322#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \ 346#define GET_TX_DESC_DATA_RETRY_LIMIT(__pdesc) \
323 LE_BITS_TO_4BYTE(__pdesc+20, 18, 6) 347 SHIFT_AND_MASK_LE(__pdesc+20, 18, 6)
324#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \ 348#define GET_TX_DESC_USB_TXAGG_NUM(__pdesc) \
325 LE_BITS_TO_4BYTE(__pdesc+20, 24, 8) 349 SHIFT_AND_MASK_LE(__pdesc+20, 24, 8)
326 350
327#define SET_TX_DESC_TXAGC_A(__pdesc, __val) \ 351#define SET_TX_DESC_TXAGC_A(__pdesc, __val) \
328 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 5, __val) 352 SET_BITS_OFFSET_LE(__pdesc+24, 0, 5, __val)
329#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \ 353#define SET_TX_DESC_TXAGC_B(__pdesc, __val) \
330 SET_BITS_TO_LE_4BYTE(__pdesc+24, 5, 5, __val) 354 SET_BITS_OFFSET_LE(__pdesc+24, 5, 5, __val)
331#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \ 355#define SET_TX_DESC_USE_MAX_LEN(__pdesc, __val) \
332 SET_BITS_TO_LE_4BYTE(__pdesc+24, 10, 1, __val) 356 SET_BITS_OFFSET_LE(__pdesc+24, 10, 1, __val)
333#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \ 357#define SET_TX_DESC_MAX_AGG_NUM(__pdesc, __val) \
334 SET_BITS_TO_LE_4BYTE(__pdesc+24, 11, 5, __val) 358 SET_BITS_OFFSET_LE(__pdesc+24, 11, 5, __val)
335#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \ 359#define SET_TX_DESC_MCSG1_MAX_LEN(__pdesc, __val) \
336 SET_BITS_TO_LE_4BYTE(__pdesc+24, 16, 4, __val) 360 SET_BITS_OFFSET_LE(__pdesc+24, 16, 4, __val)
337#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \ 361#define SET_TX_DESC_MCSG2_MAX_LEN(__pdesc, __val) \
338 SET_BITS_TO_LE_4BYTE(__pdesc+24, 20, 4, __val) 362 SET_BITS_OFFSET_LE(__pdesc+24, 20, 4, __val)
339#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \ 363#define SET_TX_DESC_MCSG3_MAX_LEN(__pdesc, __val) \
340 SET_BITS_TO_LE_4BYTE(__pdesc+24, 24, 4, __val) 364 SET_BITS_OFFSET_LE(__pdesc+24, 24, 4, __val)
341#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \ 365#define SET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc, __val) \
342 SET_BITS_TO_LE_4BYTE(__pdesc+24, 28, 4, __val) 366 SET_BITS_OFFSET_LE(__pdesc+24, 28, 4, __val)
343 367
344#define GET_TX_DESC_TXAGC_A(__pdesc) \ 368#define GET_TX_DESC_TXAGC_A(__pdesc) \
345 LE_BITS_TO_4BYTE(__pdesc+24, 0, 5) 369 SHIFT_AND_MASK_LE(__pdesc+24, 0, 5)
346#define GET_TX_DESC_TXAGC_B(__pdesc) \ 370#define GET_TX_DESC_TXAGC_B(__pdesc) \
347 LE_BITS_TO_4BYTE(__pdesc+24, 5, 5) 371 SHIFT_AND_MASK_LE(__pdesc+24, 5, 5)
348#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \ 372#define GET_TX_DESC_USE_MAX_LEN(__pdesc) \
349 LE_BITS_TO_4BYTE(__pdesc+24, 10, 1) 373 SHIFT_AND_MASK_LE(__pdesc+24, 10, 1)
350#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \ 374#define GET_TX_DESC_MAX_AGG_NUM(__pdesc) \
351 LE_BITS_TO_4BYTE(__pdesc+24, 11, 5) 375 SHIFT_AND_MASK_LE(__pdesc+24, 11, 5)
352#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \ 376#define GET_TX_DESC_MCSG1_MAX_LEN(__pdesc) \
353 LE_BITS_TO_4BYTE(__pdesc+24, 16, 4) 377 SHIFT_AND_MASK_LE(__pdesc+24, 16, 4)
354#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \ 378#define GET_TX_DESC_MCSG2_MAX_LEN(__pdesc) \
355 LE_BITS_TO_4BYTE(__pdesc+24, 20, 4) 379 SHIFT_AND_MASK_LE(__pdesc+24, 20, 4)
356#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \ 380#define GET_TX_DESC_MCSG3_MAX_LEN(__pdesc) \
357 LE_BITS_TO_4BYTE(__pdesc+24, 24, 4) 381 SHIFT_AND_MASK_LE(__pdesc+24, 24, 4)
358#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \ 382#define GET_TX_DESC_MCS7_SGI_MAX_LEN(__pdesc) \
359 LE_BITS_TO_4BYTE(__pdesc+24, 28, 4) 383 SHIFT_AND_MASK_LE(__pdesc+24, 28, 4)
360 384
361#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \ 385#define SET_TX_DESC_TX_BUFFER_SIZE(__pdesc, __val) \
362 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 16, __val) 386 SET_BITS_OFFSET_LE(__pdesc+28, 0, 16, __val)
363#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \ 387#define SET_TX_DESC_MCSG4_MAX_LEN(__pdesc, __val) \
364 SET_BITS_TO_LE_4BYTE(__pdesc+28, 16, 4, __val) 388 SET_BITS_OFFSET_LE(__pdesc+28, 16, 4, __val)
365#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \ 389#define SET_TX_DESC_MCSG5_MAX_LEN(__pdesc, __val) \
366 SET_BITS_TO_LE_4BYTE(__pdesc+28, 20, 4, __val) 390 SET_BITS_OFFSET_LE(__pdesc+28, 20, 4, __val)
367#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \ 391#define SET_TX_DESC_MCSG6_MAX_LEN(__pdesc, __val) \
368 SET_BITS_TO_LE_4BYTE(__pdesc+28, 24, 4, __val) 392 SET_BITS_OFFSET_LE(__pdesc+28, 24, 4, __val)
369#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \ 393#define SET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc, __val) \
370 SET_BITS_TO_LE_4BYTE(__pdesc+28, 28, 4, __val) 394 SET_BITS_OFFSET_LE(__pdesc+28, 28, 4, __val)
371 395
372#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \ 396#define GET_TX_DESC_TX_BUFFER_SIZE(__pdesc) \
373 LE_BITS_TO_4BYTE(__pdesc+28, 0, 16) 397 SHIFT_AND_MASK_LE(__pdesc+28, 0, 16)
374#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \ 398#define GET_TX_DESC_MCSG4_MAX_LEN(__pdesc) \
375 LE_BITS_TO_4BYTE(__pdesc+28, 16, 4) 399 SHIFT_AND_MASK_LE(__pdesc+28, 16, 4)
376#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \ 400#define GET_TX_DESC_MCSG5_MAX_LEN(__pdesc) \
377 LE_BITS_TO_4BYTE(__pdesc+28, 20, 4) 401 SHIFT_AND_MASK_LE(__pdesc+28, 20, 4)
378#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \ 402#define GET_TX_DESC_MCSG6_MAX_LEN(__pdesc) \
379 LE_BITS_TO_4BYTE(__pdesc+28, 24, 4) 403 SHIFT_AND_MASK_LE(__pdesc+28, 24, 4)
380#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \ 404#define GET_TX_DESC_MCS15_SGI_MAX_LEN(__pdesc) \
381 LE_BITS_TO_4BYTE(__pdesc+28, 28, 4) 405 SHIFT_AND_MASK_LE(__pdesc+28, 28, 4)
382 406
383#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \ 407#define SET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc, __val) \
384 SET_BITS_TO_LE_4BYTE(__pdesc+32, 0, 32, __val) 408 SET_BITS_OFFSET_LE(__pdesc+32, 0, 32, __val)
385#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \ 409#define SET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc, __val) \
386 SET_BITS_TO_LE_4BYTE(__pdesc+36, 0, 32, __val) 410 SET_BITS_OFFSET_LE(__pdesc+36, 0, 32, __val)
387 411
388#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \ 412#define GET_TX_DESC_TX_BUFFER_ADDRESS(__pdesc) \
389 LE_BITS_TO_4BYTE(__pdesc+32, 0, 32) 413 SHIFT_AND_MASK_LE(__pdesc+32, 0, 32)
390#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \ 414#define GET_TX_DESC_TX_BUFFER_ADDRESS64(__pdesc) \
391 LE_BITS_TO_4BYTE(__pdesc+36, 0, 32) 415 SHIFT_AND_MASK_LE(__pdesc+36, 0, 32)
392 416
393#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \ 417#define SET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc, __val) \
394 SET_BITS_TO_LE_4BYTE(__pdesc+40, 0, 32, __val) 418 SET_BITS_OFFSET_LE(__pdesc+40, 0, 32, __val)
395#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \ 419#define SET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc, __val) \
396 SET_BITS_TO_LE_4BYTE(__pdesc+44, 0, 32, __val) 420 SET_BITS_OFFSET_LE(__pdesc+44, 0, 32, __val)
397 421
398#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \ 422#define GET_TX_DESC_NEXT_DESC_ADDRESS(__pdesc) \
399 LE_BITS_TO_4BYTE(__pdesc+40, 0, 32) 423 SHIFT_AND_MASK_LE(__pdesc+40, 0, 32)
400#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \ 424#define GET_TX_DESC_NEXT_DESC_ADDRESS64(__pdesc) \
401 LE_BITS_TO_4BYTE(__pdesc+44, 0, 32) 425 SHIFT_AND_MASK_LE(__pdesc+44, 0, 32)
402 426
403#define GET_RX_DESC_PKT_LEN(__pdesc) \ 427#define GET_RX_DESC_PKT_LEN(__pdesc) \
404 LE_BITS_TO_4BYTE(__pdesc, 0, 14) 428 SHIFT_AND_MASK_LE(__pdesc, 0, 14)
405#define GET_RX_DESC_CRC32(__pdesc) \ 429#define GET_RX_DESC_CRC32(__pdesc) \
406 LE_BITS_TO_4BYTE(__pdesc, 14, 1) 430 SHIFT_AND_MASK_LE(__pdesc, 14, 1)
407#define GET_RX_DESC_ICV(__pdesc) \ 431#define GET_RX_DESC_ICV(__pdesc) \
408 LE_BITS_TO_4BYTE(__pdesc, 15, 1) 432 SHIFT_AND_MASK_LE(__pdesc, 15, 1)
409#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \ 433#define GET_RX_DESC_DRV_INFO_SIZE(__pdesc) \
410 LE_BITS_TO_4BYTE(__pdesc, 16, 4) 434 SHIFT_AND_MASK_LE(__pdesc, 16, 4)
411#define GET_RX_DESC_SECURITY(__pdesc) \ 435#define GET_RX_DESC_SECURITY(__pdesc) \
412 LE_BITS_TO_4BYTE(__pdesc, 20, 3) 436 SHIFT_AND_MASK_LE(__pdesc, 20, 3)
413#define GET_RX_DESC_QOS(__pdesc) \ 437#define GET_RX_DESC_QOS(__pdesc) \
414 LE_BITS_TO_4BYTE(__pdesc, 23, 1) 438 SHIFT_AND_MASK_LE(__pdesc, 23, 1)
415#define GET_RX_DESC_SHIFT(__pdesc) \ 439#define GET_RX_DESC_SHIFT(__pdesc) \
416 LE_BITS_TO_4BYTE(__pdesc, 24, 2) 440 SHIFT_AND_MASK_LE(__pdesc, 24, 2)
417#define GET_RX_DESC_PHYST(__pdesc) \ 441#define GET_RX_DESC_PHYST(__pdesc) \
418 LE_BITS_TO_4BYTE(__pdesc, 26, 1) 442 SHIFT_AND_MASK_LE(__pdesc, 26, 1)
419#define GET_RX_DESC_SWDEC(__pdesc) \ 443#define GET_RX_DESC_SWDEC(__pdesc) \
420 LE_BITS_TO_4BYTE(__pdesc, 27, 1) 444 SHIFT_AND_MASK_LE(__pdesc, 27, 1)
421#define GET_RX_DESC_LS(__pdesc) \ 445#define GET_RX_DESC_LS(__pdesc) \
422 LE_BITS_TO_4BYTE(__pdesc, 28, 1) 446 SHIFT_AND_MASK_LE(__pdesc, 28, 1)
423#define GET_RX_DESC_FS(__pdesc) \ 447#define GET_RX_DESC_FS(__pdesc) \
424 LE_BITS_TO_4BYTE(__pdesc, 29, 1) 448 SHIFT_AND_MASK_LE(__pdesc, 29, 1)
425#define GET_RX_DESC_EOR(__pdesc) \ 449#define GET_RX_DESC_EOR(__pdesc) \
426 LE_BITS_TO_4BYTE(__pdesc, 30, 1) 450 SHIFT_AND_MASK_LE(__pdesc, 30, 1)
427#define GET_RX_DESC_OWN(__pdesc) \ 451#define GET_RX_DESC_OWN(__pdesc) \
428 LE_BITS_TO_4BYTE(__pdesc, 31, 1) 452 SHIFT_AND_MASK_LE(__pdesc, 31, 1)
429 453
430#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \ 454#define SET_RX_DESC_PKT_LEN(__pdesc, __val) \
431 SET_BITS_TO_LE_4BYTE(__pdesc, 0, 14, __val) 455 SET_BITS_OFFSET_LE(__pdesc, 0, 14, __val)
432#define SET_RX_DESC_EOR(__pdesc, __val) \ 456#define SET_RX_DESC_EOR(__pdesc, __val) \
433 SET_BITS_TO_LE_4BYTE(__pdesc, 30, 1, __val) 457 SET_BITS_OFFSET_LE(__pdesc, 30, 1, __val)
434#define SET_RX_DESC_OWN(__pdesc, __val) \ 458#define SET_RX_DESC_OWN(__pdesc, __val) \
435 SET_BITS_TO_LE_4BYTE(__pdesc, 31, 1, __val) 459 SET_BITS_OFFSET_LE(__pdesc, 31, 1, __val)
436 460
437#define GET_RX_DESC_MACID(__pdesc) \ 461#define GET_RX_DESC_MACID(__pdesc) \
438 LE_BITS_TO_4BYTE(__pdesc+4, 0, 5) 462 SHIFT_AND_MASK_LE(__pdesc+4, 0, 5)
439#define GET_RX_DESC_TID(__pdesc) \ 463#define GET_RX_DESC_TID(__pdesc) \
440 LE_BITS_TO_4BYTE(__pdesc+4, 5, 4) 464 SHIFT_AND_MASK_LE(__pdesc+4, 5, 4)
441#define GET_RX_DESC_HWRSVD(__pdesc) \ 465#define GET_RX_DESC_HWRSVD(__pdesc) \
442 LE_BITS_TO_4BYTE(__pdesc+4, 9, 5) 466 SHIFT_AND_MASK_LE(__pdesc+4, 9, 5)
443#define GET_RX_DESC_PAGGR(__pdesc) \ 467#define GET_RX_DESC_PAGGR(__pdesc) \
444 LE_BITS_TO_4BYTE(__pdesc+4, 14, 1) 468 SHIFT_AND_MASK_LE(__pdesc+4, 14, 1)
445#define GET_RX_DESC_FAGGR(__pdesc) \ 469#define GET_RX_DESC_FAGGR(__pdesc) \
446 LE_BITS_TO_4BYTE(__pdesc+4, 15, 1) 470 SHIFT_AND_MASK_LE(__pdesc+4, 15, 1)
447#define GET_RX_DESC_A1_FIT(__pdesc) \ 471#define GET_RX_DESC_A1_FIT(__pdesc) \
448 LE_BITS_TO_4BYTE(__pdesc+4, 16, 4) 472 SHIFT_AND_MASK_LE(__pdesc+4, 16, 4)
449#define GET_RX_DESC_A2_FIT(__pdesc) \ 473#define GET_RX_DESC_A2_FIT(__pdesc) \
450 LE_BITS_TO_4BYTE(__pdesc+4, 20, 4) 474 SHIFT_AND_MASK_LE(__pdesc+4, 20, 4)
451#define GET_RX_DESC_PAM(__pdesc) \ 475#define GET_RX_DESC_PAM(__pdesc) \
452 LE_BITS_TO_4BYTE(__pdesc+4, 24, 1) 476 SHIFT_AND_MASK_LE(__pdesc+4, 24, 1)
453#define GET_RX_DESC_PWR(__pdesc) \ 477#define GET_RX_DESC_PWR(__pdesc) \
454 LE_BITS_TO_4BYTE(__pdesc+4, 25, 1) 478 SHIFT_AND_MASK_LE(__pdesc+4, 25, 1)
455#define GET_RX_DESC_MD(__pdesc) \ 479#define GET_RX_DESC_MD(__pdesc) \
456 LE_BITS_TO_4BYTE(__pdesc+4, 26, 1) 480 SHIFT_AND_MASK_LE(__pdesc+4, 26, 1)
457#define GET_RX_DESC_MF(__pdesc) \ 481#define GET_RX_DESC_MF(__pdesc) \
458 LE_BITS_TO_4BYTE(__pdesc+4, 27, 1) 482 SHIFT_AND_MASK_LE(__pdesc+4, 27, 1)
459#define GET_RX_DESC_TYPE(__pdesc) \ 483#define GET_RX_DESC_TYPE(__pdesc) \
460 LE_BITS_TO_4BYTE(__pdesc+4, 28, 2) 484 SHIFT_AND_MASK_LE(__pdesc+4, 28, 2)
461#define GET_RX_DESC_MC(__pdesc) \ 485#define GET_RX_DESC_MC(__pdesc) \
462 LE_BITS_TO_4BYTE(__pdesc+4, 30, 1) 486 SHIFT_AND_MASK_LE(__pdesc+4, 30, 1)
463#define GET_RX_DESC_BC(__pdesc) \ 487#define GET_RX_DESC_BC(__pdesc) \
464 LE_BITS_TO_4BYTE(__pdesc+4, 31, 1) 488 SHIFT_AND_MASK_LE(__pdesc+4, 31, 1)
465#define GET_RX_DESC_SEQ(__pdesc) \ 489#define GET_RX_DESC_SEQ(__pdesc) \
466 LE_BITS_TO_4BYTE(__pdesc+8, 0, 12) 490 SHIFT_AND_MASK_LE(__pdesc+8, 0, 12)
467#define GET_RX_DESC_FRAG(__pdesc) \ 491#define GET_RX_DESC_FRAG(__pdesc) \
468 LE_BITS_TO_4BYTE(__pdesc+8, 12, 4) 492 SHIFT_AND_MASK_LE(__pdesc+8, 12, 4)
469#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \ 493#define GET_RX_DESC_NEXT_PKT_LEN(__pdesc) \
470 LE_BITS_TO_4BYTE(__pdesc+8, 16, 14) 494 SHIFT_AND_MASK_LE(__pdesc+8, 16, 14)
471#define GET_RX_DESC_NEXT_IND(__pdesc) \ 495#define GET_RX_DESC_NEXT_IND(__pdesc) \
472 LE_BITS_TO_4BYTE(__pdesc+8, 30, 1) 496 SHIFT_AND_MASK_LE(__pdesc+8, 30, 1)
473#define GET_RX_DESC_RSVD(__pdesc) \ 497#define GET_RX_DESC_RSVD(__pdesc) \
474 LE_BITS_TO_4BYTE(__pdesc+8, 31, 1) 498 SHIFT_AND_MASK_LE(__pdesc+8, 31, 1)
475 499
476#define GET_RX_DESC_RXMCS(__pdesc) \ 500#define GET_RX_DESC_RXMCS(__pdesc) \
477 LE_BITS_TO_4BYTE(__pdesc+12, 0, 6) 501 SHIFT_AND_MASK_LE(__pdesc+12, 0, 6)
478#define GET_RX_DESC_RXHT(__pdesc) \ 502#define GET_RX_DESC_RXHT(__pdesc) \
479 LE_BITS_TO_4BYTE(__pdesc+12, 6, 1) 503 SHIFT_AND_MASK_LE(__pdesc+12, 6, 1)
480#define GET_RX_DESC_SPLCP(__pdesc) \ 504#define GET_RX_DESC_SPLCP(__pdesc) \
481 LE_BITS_TO_4BYTE(__pdesc+12, 8, 1) 505 SHIFT_AND_MASK_LE(__pdesc+12, 8, 1)
482#define GET_RX_DESC_BW(__pdesc) \ 506#define GET_RX_DESC_BW(__pdesc) \
483 LE_BITS_TO_4BYTE(__pdesc+12, 9, 1) 507 SHIFT_AND_MASK_LE(__pdesc+12, 9, 1)
484#define GET_RX_DESC_HTC(__pdesc) \ 508#define GET_RX_DESC_HTC(__pdesc) \
485 LE_BITS_TO_4BYTE(__pdesc+12, 10, 1) 509 SHIFT_AND_MASK_LE(__pdesc+12, 10, 1)
486#define GET_RX_DESC_HWPC_ERR(__pdesc) \ 510#define GET_RX_DESC_HWPC_ERR(__pdesc) \
487 LE_BITS_TO_4BYTE(__pdesc+12, 14, 1) 511 SHIFT_AND_MASK_LE(__pdesc+12, 14, 1)
488#define GET_RX_DESC_HWPC_IND(__pdesc) \ 512#define GET_RX_DESC_HWPC_IND(__pdesc) \
489 LE_BITS_TO_4BYTE(__pdesc+12, 15, 1) 513 SHIFT_AND_MASK_LE(__pdesc+12, 15, 1)
490#define GET_RX_DESC_IV0(__pdesc) \ 514#define GET_RX_DESC_IV0(__pdesc) \
491 LE_BITS_TO_4BYTE(__pdesc+12, 16, 16) 515 SHIFT_AND_MASK_LE(__pdesc+12, 16, 16)
492 516
493#define GET_RX_DESC_IV1(__pdesc) \ 517#define GET_RX_DESC_IV1(__pdesc) \
494 LE_BITS_TO_4BYTE(__pdesc+16, 0, 32) 518 SHIFT_AND_MASK_LE(__pdesc+16, 0, 32)
495#define GET_RX_DESC_TSFL(__pdesc) \ 519#define GET_RX_DESC_TSFL(__pdesc) \
496 LE_BITS_TO_4BYTE(__pdesc+20, 0, 32) 520 SHIFT_AND_MASK_LE(__pdesc+20, 0, 32)
497 521
498#define GET_RX_DESC_BUFF_ADDR(__pdesc) \ 522#define GET_RX_DESC_BUFF_ADDR(__pdesc) \
499 LE_BITS_TO_4BYTE(__pdesc+24, 0, 32) 523 SHIFT_AND_MASK_LE(__pdesc+24, 0, 32)
500#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \ 524#define GET_RX_DESC_BUFF_ADDR64(__pdesc) \
501 LE_BITS_TO_4BYTE(__pdesc+28, 0, 32) 525 SHIFT_AND_MASK_LE(__pdesc+28, 0, 32)
502 526
503#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \ 527#define SET_RX_DESC_BUFF_ADDR(__pdesc, __val) \
504 SET_BITS_TO_LE_4BYTE(__pdesc+24, 0, 32, __val) 528 SET_BITS_OFFSET_LE(__pdesc+24, 0, 32, __val)
505#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \ 529#define SET_RX_DESC_BUFF_ADDR64(__pdesc, __val) \
506 SET_BITS_TO_LE_4BYTE(__pdesc+28, 0, 32, __val) 530 SET_BITS_OFFSET_LE(__pdesc+28, 0, 32, __val)
507 531
508#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \ 532#define CLEAR_PCI_TX_DESC_CONTENT(__pdesc, _size) \
509do { \ 533do { \
@@ -711,4 +735,6 @@ void rtl92ce_tx_polling(struct ieee80211_hw *hw, unsigned int hw_queue);
711void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc, 735void rtl92ce_tx_fill_cmddesc(struct ieee80211_hw *hw, u8 *pdesc,
712 bool b_firstseg, bool b_lastseg, 736 bool b_firstseg, bool b_lastseg,
713 struct sk_buff *skb); 737 struct sk_buff *skb);
738bool _rtl92c_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb);
739
714#endif 740#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/Makefile b/drivers/net/wireless/rtlwifi/rtl8192cu/Makefile
new file mode 100644
index 000000000000..ad2de6b839ef
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/Makefile
@@ -0,0 +1,14 @@
1rtl8192cu-objs := \
2 dm.o \
3 hw.o \
4 led.o \
5 mac.o \
6 phy.o \
7 rf.o \
8 sw.o \
9 table.o \
10 trx.o
11
12obj-$(CONFIG_RTL8192CU) += rtl8192cu.o
13
14ccflags-y += -D__CHECK_ENDIAN__
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/def.h b/drivers/net/wireless/rtlwifi/rtl8192cu/def.h
new file mode 100644
index 000000000000..c54940ea72fe
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/def.h
@@ -0,0 +1,62 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../rtl8192ce/def.h"
31
32/*-------------------------------------------------------------------------
33 * Chip specific
34 *-------------------------------------------------------------------------*/
35#define CHIP_8723 BIT(2) /* RTL8723 With BT feature */
36#define CHIP_8723_DRV_REV BIT(3) /* RTL8723 Driver Revised */
37#define NORMAL_CHIP BIT(4)
38#define CHIP_VENDOR_UMC BIT(5)
39#define CHIP_VENDOR_UMC_B_CUT BIT(6)
40
41#define IS_NORMAL_CHIP(version) \
42 (((version) & NORMAL_CHIP) ? true : false)
43
44#define IS_8723_SERIES(version) \
45 (((version) & CHIP_8723) ? true : false)
46
47#define IS_92C_1T2R(version) \
48 (((version) & CHIP_92C) && ((version) & CHIP_92C_1T2R))
49
50#define IS_VENDOR_UMC(version) \
51 (((version) & CHIP_VENDOR_UMC) ? true : false)
52
53#define IS_VENDOR_UMC_A_CUT(version) \
54 (((version) & CHIP_VENDOR_UMC) ? (((version) & (BIT(6) | BIT(7))) ? \
55 false : true) : false)
56
57#define IS_VENDOR_8723_A_CUT(version) \
58 (((version) & CHIP_VENDOR_UMC) ? (((version) & (BIT(6))) ? \
59 false : true) : false)
60
61#define CHIP_BONDING_92C_1T2R 0x1
62#define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/dm.c b/drivers/net/wireless/rtlwifi/rtl8192cu/dm.c
new file mode 100644
index 000000000000..f311baee668d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/dm.c
@@ -0,0 +1,113 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../base.h"
32#include "reg.h"
33#include "def.h"
34#include "phy.h"
35#include "dm.h"
36
37void rtl92cu_dm_dynamic_txpower(struct ieee80211_hw *hw)
38{
39 struct rtl_priv *rtlpriv = rtl_priv(hw);
40 struct rtl_phy *rtlphy = &(rtlpriv->phy);
41 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
42 long undecorated_smoothed_pwdb;
43
44 if (!rtlpriv->dm.dynamic_txpower_enable)
45 return;
46
47 if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
48 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
49 return;
50 }
51
52 if ((mac->link_state < MAC80211_LINKED) &&
53 (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
54 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
55 ("Not connected to any\n"));
56
57 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
58
59 rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
60 return;
61 }
62
63 if (mac->link_state >= MAC80211_LINKED) {
64 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
65 undecorated_smoothed_pwdb =
66 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
67 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
68 ("AP Client PWDB = 0x%lx\n",
69 undecorated_smoothed_pwdb));
70 } else {
71 undecorated_smoothed_pwdb =
72 rtlpriv->dm.undecorated_smoothed_pwdb;
73 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
74 ("STA Default Port PWDB = 0x%lx\n",
75 undecorated_smoothed_pwdb));
76 }
77 } else {
78 undecorated_smoothed_pwdb =
79 rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
80
81 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
82 ("AP Ext Port PWDB = 0x%lx\n",
83 undecorated_smoothed_pwdb));
84 }
85
86 if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
87 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
88 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
89 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n"));
90 } else if ((undecorated_smoothed_pwdb <
91 (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
92 (undecorated_smoothed_pwdb >=
93 TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
94
95 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
96 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
97 ("TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n"));
98 } else if (undecorated_smoothed_pwdb <
99 (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
100 rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
101 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
102 ("TXHIGHPWRLEVEL_NORMAL\n"));
103 }
104
105 if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
106 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
107 ("PHY_SetTxPowerLevel8192S() Channel = %d\n",
108 rtlphy->current_channel));
109 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
110 }
111
112 rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
113}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/dm.h b/drivers/net/wireless/rtlwifi/rtl8192cu/dm.h
new file mode 100644
index 000000000000..7f966c666b5a
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/dm.h
@@ -0,0 +1,32 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../rtl8192ce/dm.h"
31
32void rtl92cu_dm_dynamic_txpower(struct ieee80211_hw *hw);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
new file mode 100644
index 000000000000..9444e76838cf
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
@@ -0,0 +1,2504 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../efuse.h"
32#include "../base.h"
33#include "../cam.h"
34#include "../ps.h"
35#include "../usb.h"
36#include "reg.h"
37#include "def.h"
38#include "phy.h"
39#include "mac.h"
40#include "dm.h"
41#include "hw.h"
42#include "trx.h"
43#include "led.h"
44#include "table.h"
45
46static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
47{
48 struct rtl_priv *rtlpriv = rtl_priv(hw);
49 struct rtl_phy *rtlphy = &(rtlpriv->phy);
50 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
51
52 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
53 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
54 if (IS_HIGHT_PA(rtlefuse->board_type)) {
55 rtlphy->hwparam_tables[PHY_REG_PG].length =
56 RTL8192CUPHY_REG_Array_PG_HPLength;
57 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
58 RTL8192CUPHY_REG_Array_PG_HP;
59 } else {
60 rtlphy->hwparam_tables[PHY_REG_PG].length =
61 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
62 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
63 RTL8192CUPHY_REG_ARRAY_PG;
64 }
65 /* 2T */
66 rtlphy->hwparam_tables[PHY_REG_2T].length =
67 RTL8192CUPHY_REG_2TARRAY_LENGTH;
68 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
69 RTL8192CUPHY_REG_2TARRAY;
70 rtlphy->hwparam_tables[RADIOA_2T].length =
71 RTL8192CURADIOA_2TARRAYLENGTH;
72 rtlphy->hwparam_tables[RADIOA_2T].pdata =
73 RTL8192CURADIOA_2TARRAY;
74 rtlphy->hwparam_tables[RADIOB_2T].length =
75 RTL8192CURADIOB_2TARRAYLENGTH;
76 rtlphy->hwparam_tables[RADIOB_2T].pdata =
77 RTL8192CU_RADIOB_2TARRAY;
78 rtlphy->hwparam_tables[AGCTAB_2T].length =
79 RTL8192CUAGCTAB_2TARRAYLENGTH;
80 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
81 RTL8192CUAGCTAB_2TARRAY;
82 /* 1T */
83 if (IS_HIGHT_PA(rtlefuse->board_type)) {
84 rtlphy->hwparam_tables[PHY_REG_1T].length =
85 RTL8192CUPHY_REG_1T_HPArrayLength;
86 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
87 RTL8192CUPHY_REG_1T_HPArray;
88 rtlphy->hwparam_tables[RADIOA_1T].length =
89 RTL8192CURadioA_1T_HPArrayLength;
90 rtlphy->hwparam_tables[RADIOA_1T].pdata =
91 RTL8192CURadioA_1T_HPArray;
92 rtlphy->hwparam_tables[RADIOB_1T].length =
93 RTL8192CURADIOB_1TARRAYLENGTH;
94 rtlphy->hwparam_tables[RADIOB_1T].pdata =
95 RTL8192CU_RADIOB_1TARRAY;
96 rtlphy->hwparam_tables[AGCTAB_1T].length =
97 RTL8192CUAGCTAB_1T_HPArrayLength;
98 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
99 Rtl8192CUAGCTAB_1T_HPArray;
100 } else {
101 rtlphy->hwparam_tables[PHY_REG_1T].length =
102 RTL8192CUPHY_REG_1TARRAY_LENGTH;
103 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
104 RTL8192CUPHY_REG_1TARRAY;
105 rtlphy->hwparam_tables[RADIOA_1T].length =
106 RTL8192CURADIOA_1TARRAYLENGTH;
107 rtlphy->hwparam_tables[RADIOA_1T].pdata =
108 RTL8192CU_RADIOA_1TARRAY;
109 rtlphy->hwparam_tables[RADIOB_1T].length =
110 RTL8192CURADIOB_1TARRAYLENGTH;
111 rtlphy->hwparam_tables[RADIOB_1T].pdata =
112 RTL8192CU_RADIOB_1TARRAY;
113 rtlphy->hwparam_tables[AGCTAB_1T].length =
114 RTL8192CUAGCTAB_1TARRAYLENGTH;
115 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
116 RTL8192CUAGCTAB_1TARRAY;
117 }
118}
119
120static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
121 bool autoload_fail,
122 u8 *hwinfo)
123{
124 struct rtl_priv *rtlpriv = rtl_priv(hw);
125 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
126 u8 rf_path, index, tempval;
127 u16 i;
128
129 for (rf_path = 0; rf_path < 2; rf_path++) {
130 for (i = 0; i < 3; i++) {
131 if (!autoload_fail) {
132 rtlefuse->
133 eeprom_chnlarea_txpwr_cck[rf_path][i] =
134 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
135 rtlefuse->
136 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
137 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
138 i];
139 } else {
140 rtlefuse->
141 eeprom_chnlarea_txpwr_cck[rf_path][i] =
142 EEPROM_DEFAULT_TXPOWERLEVEL;
143 rtlefuse->
144 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
145 EEPROM_DEFAULT_TXPOWERLEVEL;
146 }
147 }
148 }
149 for (i = 0; i < 3; i++) {
150 if (!autoload_fail)
151 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
152 else
153 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
154 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
155 (tempval & 0xf);
156 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
157 ((tempval & 0xf0) >> 4);
158 }
159 for (rf_path = 0; rf_path < 2; rf_path++)
160 for (i = 0; i < 3; i++)
161 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
162 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
163 i, rtlefuse->
164 eeprom_chnlarea_txpwr_cck[rf_path][i]));
165 for (rf_path = 0; rf_path < 2; rf_path++)
166 for (i = 0; i < 3; i++)
167 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
168 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
169 rf_path, i,
170 rtlefuse->
171 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
172 for (rf_path = 0; rf_path < 2; rf_path++)
173 for (i = 0; i < 3; i++)
174 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
175 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
176 rf_path, i,
177 rtlefuse->
178 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
179 [i]));
180 for (rf_path = 0; rf_path < 2; rf_path++) {
181 for (i = 0; i < 14; i++) {
182 index = _rtl92c_get_chnl_group((u8) i);
183 rtlefuse->txpwrlevel_cck[rf_path][i] =
184 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
185 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
186 rtlefuse->
187 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
188 if ((rtlefuse->
189 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
190 rtlefuse->
191 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
192 > 0) {
193 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
194 rtlefuse->
195 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
196 [index] - rtlefuse->
197 eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
198 [index];
199 } else {
200 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
201 }
202 }
203 for (i = 0; i < 14; i++) {
204 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
205 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
206 "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
207 rtlefuse->txpwrlevel_cck[rf_path][i],
208 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
209 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
210 }
211 }
212 for (i = 0; i < 3; i++) {
213 if (!autoload_fail) {
214 rtlefuse->eeprom_pwrlimit_ht40[i] =
215 hwinfo[EEPROM_TXPWR_GROUP + i];
216 rtlefuse->eeprom_pwrlimit_ht20[i] =
217 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
218 } else {
219 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
220 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
221 }
222 }
223 for (rf_path = 0; rf_path < 2; rf_path++) {
224 for (i = 0; i < 14; i++) {
225 index = _rtl92c_get_chnl_group((u8) i);
226 if (rf_path == RF90_PATH_A) {
227 rtlefuse->pwrgroup_ht20[rf_path][i] =
228 (rtlefuse->eeprom_pwrlimit_ht20[index]
229 & 0xf);
230 rtlefuse->pwrgroup_ht40[rf_path][i] =
231 (rtlefuse->eeprom_pwrlimit_ht40[index]
232 & 0xf);
233 } else if (rf_path == RF90_PATH_B) {
234 rtlefuse->pwrgroup_ht20[rf_path][i] =
235 ((rtlefuse->eeprom_pwrlimit_ht20[index]
236 & 0xf0) >> 4);
237 rtlefuse->pwrgroup_ht40[rf_path][i] =
238 ((rtlefuse->eeprom_pwrlimit_ht40[index]
239 & 0xf0) >> 4);
240 }
241 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
242 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
243 rf_path, i,
244 rtlefuse->pwrgroup_ht20[rf_path][i]));
245 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
246 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
247 rf_path, i,
248 rtlefuse->pwrgroup_ht40[rf_path][i]));
249 }
250 }
251 for (i = 0; i < 14; i++) {
252 index = _rtl92c_get_chnl_group((u8) i);
253 if (!autoload_fail)
254 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
255 else
256 tempval = EEPROM_DEFAULT_HT20_DIFF;
257 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
258 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
259 ((tempval >> 4) & 0xF);
260 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
261 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
262 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
263 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
264 index = _rtl92c_get_chnl_group((u8) i);
265 if (!autoload_fail)
266 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
267 else
268 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
269 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
270 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
271 ((tempval >> 4) & 0xF);
272 }
273 rtlefuse->legacy_ht_txpowerdiff =
274 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
275 for (i = 0; i < 14; i++)
276 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
277 ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
278 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
279 for (i = 0; i < 14; i++)
280 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
281 ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
282 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
283 for (i = 0; i < 14; i++)
284 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
285 ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
286 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
287 for (i = 0; i < 14; i++)
288 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
289 ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
290 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
291 if (!autoload_fail)
292 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
293 else
294 rtlefuse->eeprom_regulatory = 0;
295 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
296 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
297 if (!autoload_fail) {
298 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
299 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
300 } else {
301 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
302 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
303 }
304 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
305 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
306 rtlefuse->eeprom_tssi[RF90_PATH_A],
307 rtlefuse->eeprom_tssi[RF90_PATH_B]));
308 if (!autoload_fail)
309 tempval = hwinfo[EEPROM_THERMAL_METER];
310 else
311 tempval = EEPROM_DEFAULT_THERMALMETER;
312 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
313 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
314 rtlefuse->eeprom_thermalmeter > 0x1c)
315 rtlefuse->eeprom_thermalmeter = 0x12;
316 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
317 rtlefuse->apk_thermalmeterignore = true;
318 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
319 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
320 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
321}
322
323static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
324{
325 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
326 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
327 u8 boardType;
328
329 if (IS_NORMAL_CHIP(rtlhal->version)) {
330 boardType = ((contents[EEPROM_RF_OPT1]) &
331 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
332 } else {
333 boardType = contents[EEPROM_RF_OPT4];
334 boardType &= BOARD_TYPE_TEST_MASK;
335 }
336 rtlefuse->board_type = boardType;
337 if (IS_HIGHT_PA(rtlefuse->board_type))
338 rtlefuse->external_pa = 1;
339 printk(KERN_INFO "rtl8192cu: Board Type %x\n", rtlefuse->board_type);
340
341#ifdef CONFIG_ANTENNA_DIVERSITY
342 /* Antenna Diversity setting. */
343 if (registry_par->antdiv_cfg == 2) /* 2: From Efuse */
344 rtl_efuse->antenna_cfg = (contents[EEPROM_RF_OPT1]&0x18)>>3;
345 else
346 rtl_efuse->antenna_cfg = registry_par->antdiv_cfg; /* 0:OFF, */
347
348 printk(KERN_INFO "rtl8192cu: Antenna Config %x\n",
349 rtl_efuse->antenna_cfg);
350#endif
351}
352
353#ifdef CONFIG_BT_COEXIST
354static void _update_bt_param(_adapter *padapter)
355{
356 struct btcoexist_priv *pbtpriv = &(padapter->halpriv.bt_coexist);
357 struct registry_priv *registry_par = &padapter->registrypriv;
358 if (2 != registry_par->bt_iso) {
359 /* 0:Low, 1:High, 2:From Efuse */
360 pbtpriv->BT_Ant_isolation = registry_par->bt_iso;
361 }
362 if (registry_par->bt_sco == 1) {
363 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy,
364 * 5.OtherBusy */
365 pbtpriv->BT_Service = BT_OtherAction;
366 } else if (registry_par->bt_sco == 2) {
367 pbtpriv->BT_Service = BT_SCO;
368 } else if (registry_par->bt_sco == 4) {
369 pbtpriv->BT_Service = BT_Busy;
370 } else if (registry_par->bt_sco == 5) {
371 pbtpriv->BT_Service = BT_OtherBusy;
372 } else {
373 pbtpriv->BT_Service = BT_Idle;
374 }
375 pbtpriv->BT_Ampdu = registry_par->bt_ampdu;
376 pbtpriv->bCOBT = _TRUE;
377 pbtpriv->BtEdcaUL = 0;
378 pbtpriv->BtEdcaDL = 0;
379 pbtpriv->BtRssiState = 0xff;
380 pbtpriv->bInitSet = _FALSE;
381 pbtpriv->bBTBusyTraffic = _FALSE;
382 pbtpriv->bBTTrafficModeSet = _FALSE;
383 pbtpriv->bBTNonTrafficModeSet = _FALSE;
384 pbtpriv->CurrentState = 0;
385 pbtpriv->PreviousState = 0;
386 printk(KERN_INFO "rtl8192cu: BT Coexistance = %s\n",
387 (pbtpriv->BT_Coexist == _TRUE) ? "enable" : "disable");
388 if (pbtpriv->BT_Coexist) {
389 if (pbtpriv->BT_Ant_Num == Ant_x2)
390 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
391 "Ant_Num = Antx2\n");
392 else if (pbtpriv->BT_Ant_Num == Ant_x1)
393 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
394 "Ant_Num = Antx1\n");
395 switch (pbtpriv->BT_CoexistType) {
396 case BT_2Wire:
397 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
398 "CoexistType = BT_2Wire\n");
399 break;
400 case BT_ISSC_3Wire:
401 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
402 "CoexistType = BT_ISSC_3Wire\n");
403 break;
404 case BT_Accel:
405 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
406 "CoexistType = BT_Accel\n");
407 break;
408 case BT_CSR_BC4:
409 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
410 "CoexistType = BT_CSR_BC4\n");
411 break;
412 case BT_CSR_BC8:
413 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
414 "CoexistType = BT_CSR_BC8\n");
415 break;
416 case BT_RTL8756:
417 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
418 "CoexistType = BT_RTL8756\n");
419 break;
420 default:
421 printk(KERN_INFO "rtl8192cu: BlueTooth BT_"
422 "CoexistType = Unknown\n");
423 break;
424 }
425 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Ant_isolation = %d\n",
426 pbtpriv->BT_Ant_isolation);
427 switch (pbtpriv->BT_Service) {
428 case BT_OtherAction:
429 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
430 "BT_OtherAction\n");
431 break;
432 case BT_SCO:
433 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
434 "BT_SCO\n");
435 break;
436 case BT_Busy:
437 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
438 "BT_Busy\n");
439 break;
440 case BT_OtherBusy:
441 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
442 "BT_OtherBusy\n");
443 break;
444 default:
445 printk(KERN_INFO "rtl8192cu: BlueTooth BT_Service = "
446 "BT_Idle\n");
447 break;
448 }
449 printk(KERN_INFO "rtl8192cu: BT_RadioSharedType = 0x%x\n",
450 pbtpriv->BT_RadioSharedType);
451 }
452}
453
454#define GET_BT_COEXIST(priv) (&priv->bt_coexist)
455
456static void _rtl92cu_read_bluetooth_coexistInfo(struct ieee80211_hw *hw,
457 u8 *contents,
458 bool bautoloadfailed);
459{
460 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
461 bool isNormal = IS_NORMAL_CHIP(pHalData->VersionID);
462 struct btcoexist_priv *pbtpriv = &pHalData->bt_coexist;
463 u8 rf_opt4;
464
465 _rtw_memset(pbtpriv, 0, sizeof(struct btcoexist_priv));
466 if (AutoloadFail) {
467 pbtpriv->BT_Coexist = _FALSE;
468 pbtpriv->BT_CoexistType = BT_2Wire;
469 pbtpriv->BT_Ant_Num = Ant_x2;
470 pbtpriv->BT_Ant_isolation = 0;
471 pbtpriv->BT_RadioSharedType = BT_Radio_Shared;
472 return;
473 }
474 if (isNormal) {
475 if (pHalData->BoardType == BOARD_USB_COMBO)
476 pbtpriv->BT_Coexist = _TRUE;
477 else
478 pbtpriv->BT_Coexist = ((PROMContent[EEPROM_RF_OPT3] &
479 0x20) >> 5); /* bit[5] */
480 rf_opt4 = PROMContent[EEPROM_RF_OPT4];
481 pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); /* bit [3:1] */
482 pbtpriv->BT_Ant_Num = (rf_opt4&0x1); /* bit [0] */
483 pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); /* bit [4] */
484 pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); /* bit [5] */
485 } else {
486 pbtpriv->BT_Coexist = (PROMContent[EEPROM_RF_OPT4] >> 4) ?
487 _TRUE : _FALSE;
488 }
489 _update_bt_param(Adapter);
490}
491#endif
492
493static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
494{
495 struct rtl_priv *rtlpriv = rtl_priv(hw);
496 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
497 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
498 u16 i, usvalue;
499 u8 hwinfo[HWSET_MAX_SIZE] = {0};
500 u16 eeprom_id;
501
502 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
503 rtl_efuse_shadow_map_update(hw);
504 memcpy((void *)hwinfo,
505 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
506 HWSET_MAX_SIZE);
507 } else if (rtlefuse->epromtype == EEPROM_93C46) {
508 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
509 ("RTL819X Not boot from eeprom, check it !!"));
510 }
511 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
512 hwinfo, HWSET_MAX_SIZE);
513 eeprom_id = *((u16 *)&hwinfo[0]);
514 if (eeprom_id != RTL8190_EEPROM_ID) {
515 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
516 ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
517 rtlefuse->autoload_failflag = true;
518 } else {
519 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
520 rtlefuse->autoload_failflag = false;
521 }
522 if (rtlefuse->autoload_failflag == true)
523 return;
524 for (i = 0; i < 6; i += 2) {
525 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
526 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
527 }
528 printk(KERN_INFO "rtl8192cu: MAC address: %pM\n", rtlefuse->dev_addr);
529 _rtl92cu_read_txpower_info_from_hwpg(hw,
530 rtlefuse->autoload_failflag, hwinfo);
531 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
532 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
533 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
534 (" VID = 0x%02x PID = 0x%02x\n",
535 rtlefuse->eeprom_vid, rtlefuse->eeprom_did));
536 rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
537 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
538 rtlefuse->txpwr_fromeprom = true;
539 rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
540 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
541 ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
542 if (rtlhal->oem_id == RT_CID_DEFAULT) {
543 switch (rtlefuse->eeprom_oemid) {
544 case EEPROM_CID_DEFAULT:
545 if (rtlefuse->eeprom_did == 0x8176) {
546 if ((rtlefuse->eeprom_svid == 0x103C &&
547 rtlefuse->eeprom_smid == 0x1629))
548 rtlhal->oem_id = RT_CID_819x_HP;
549 else
550 rtlhal->oem_id = RT_CID_DEFAULT;
551 } else {
552 rtlhal->oem_id = RT_CID_DEFAULT;
553 }
554 break;
555 case EEPROM_CID_TOSHIBA:
556 rtlhal->oem_id = RT_CID_TOSHIBA;
557 break;
558 case EEPROM_CID_QMI:
559 rtlhal->oem_id = RT_CID_819x_QMI;
560 break;
561 case EEPROM_CID_WHQL:
562 default:
563 rtlhal->oem_id = RT_CID_DEFAULT;
564 break;
565 }
566 }
567 _rtl92cu_read_board_type(hw, hwinfo);
568#ifdef CONFIG_BT_COEXIST
569 _rtl92cu_read_bluetooth_coexistInfo(hw, hwinfo,
570 rtlefuse->autoload_failflag);
571#endif
572}
573
574static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
575{
576 struct rtl_priv *rtlpriv = rtl_priv(hw);
577 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
578 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
579
580 switch (rtlhal->oem_id) {
581 case RT_CID_819x_HP:
582 usb_priv->ledctl.led_opendrain = true;
583 break;
584 case RT_CID_819x_Lenovo:
585 case RT_CID_DEFAULT:
586 case RT_CID_TOSHIBA:
587 case RT_CID_CCX:
588 case RT_CID_819x_Acer:
589 case RT_CID_WHQL:
590 default:
591 break;
592 }
593 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
594 ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
595}
596
597void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
598{
599
600 struct rtl_priv *rtlpriv = rtl_priv(hw);
601 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
602 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
603 u8 tmp_u1b;
604
605 if (!IS_NORMAL_CHIP(rtlhal->version))
606 return;
607 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
608 rtlefuse->epromtype = (tmp_u1b & EEPROMSEL) ?
609 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
610 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from %s\n",
611 (tmp_u1b & EEPROMSEL) ? "EERROM" : "EFUSE"));
612 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
613 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload %s\n",
614 (tmp_u1b & EEPROM_EN) ? "OK!!" : "ERR!!"));
615 _rtl92cu_read_adapter_info(hw);
616 _rtl92cu_hal_customized_behavior(hw);
617 return;
618}
619
620static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
621{
622 struct rtl_priv *rtlpriv = rtl_priv(hw);
623 int status = 0;
624 u16 value16;
625 u8 value8;
626 /* polling autoload done. */
627 u32 pollingCount = 0;
628
629 do {
630 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
631 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
632 ("Autoload Done!\n"));
633 break;
634 }
635 if (pollingCount++ > 100) {
636 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
637 ("Failed to polling REG_APS_FSMCO[PFM_ALDN]"
638 " done!\n"));
639 return -ENODEV;
640 }
641 } while (true);
642 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
643 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
644 /* Power on when re-enter from IPS/Radio off/card disable */
645 /* enable SPS into PWM mode */
646 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
647 udelay(100);
648 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
649 if (0 == (value8 & LDV12_EN)) {
650 value8 |= LDV12_EN;
651 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
652 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
653 (" power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",
654 value8));
655 udelay(100);
656 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
657 value8 &= ~ISO_MD2PP;
658 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
659 }
660 /* auto enable WLAN */
661 pollingCount = 0;
662 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
663 value16 |= APFM_ONMAC;
664 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
665 do {
666 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
667 printk(KERN_INFO "rtl8192cu: MAC auto ON okay!\n");
668 break;
669 }
670 if (pollingCount++ > 100) {
671 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
672 ("Failed to polling REG_APS_FSMCO[APFM_ONMAC]"
673 " done!\n"));
674 return -ENODEV;
675 }
676 } while (true);
677 /* Enable Radio ,GPIO ,and LED function */
678 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
679 /* release RF digital isolation */
680 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
681 value16 &= ~ISO_DIOR;
682 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
683 /* Reconsider when to do this operation after asking HWSD. */
684 pollingCount = 0;
685 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
686 REG_APSD_CTRL) & ~BIT(6)));
687 do {
688 pollingCount++;
689 } while ((pollingCount < 200) &&
690 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
691 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
692 value16 = rtl_read_word(rtlpriv, REG_CR);
693 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
694 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
695 rtl_write_word(rtlpriv, REG_CR, value16);
696 return status;
697}
698
699static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
700 bool wmm_enable,
701 u8 out_ep_num,
702 u8 queue_sel)
703{
704 struct rtl_priv *rtlpriv = rtl_priv(hw);
705 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
706 bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
707 u32 outEPNum = (u32)out_ep_num;
708 u32 numHQ = 0;
709 u32 numLQ = 0;
710 u32 numNQ = 0;
711 u32 numPubQ;
712 u32 value32;
713 u8 value8;
714 u32 txQPageNum, txQPageUnit, txQRemainPage;
715
716 if (!wmm_enable) {
717 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
718 CHIP_A_PAGE_NUM_PUBQ;
719 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
720
721 txQPageUnit = txQPageNum/outEPNum;
722 txQRemainPage = txQPageNum % outEPNum;
723 if (queue_sel & TX_SELE_HQ)
724 numHQ = txQPageUnit;
725 if (queue_sel & TX_SELE_LQ)
726 numLQ = txQPageUnit;
727 /* HIGH priority queue always present in the configuration of
728 * 2 out-ep. Remainder pages have assigned to High queue */
729 if ((outEPNum > 1) && (txQRemainPage))
730 numHQ += txQRemainPage;
731 /* NOTE: This step done before writting REG_RQPN. */
732 if (isChipN) {
733 if (queue_sel & TX_SELE_NQ)
734 numNQ = txQPageUnit;
735 value8 = (u8)_NPQ(numNQ);
736 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
737 }
738 } else {
739 /* for WMM ,number of out-ep must more than or equal to 2! */
740 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
741 WMM_CHIP_A_PAGE_NUM_PUBQ;
742 if (queue_sel & TX_SELE_HQ) {
743 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
744 WMM_CHIP_A_PAGE_NUM_HPQ;
745 }
746 if (queue_sel & TX_SELE_LQ) {
747 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
748 WMM_CHIP_A_PAGE_NUM_LPQ;
749 }
750 /* NOTE: This step done before writting REG_RQPN. */
751 if (isChipN) {
752 if (queue_sel & TX_SELE_NQ)
753 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
754 value8 = (u8)_NPQ(numNQ);
755 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
756 }
757 }
758 /* TX DMA */
759 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
760 rtl_write_dword(rtlpriv, REG_RQPN, value32);
761}
762
763static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
764{
765 struct rtl_priv *rtlpriv = rtl_priv(hw);
766 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
767 u8 txpktbuf_bndy;
768 u8 value8;
769
770 if (!wmm_enable)
771 txpktbuf_bndy = TX_PAGE_BOUNDARY;
772 else /* for WMM */
773 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
774 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
775 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
776 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
777 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
778 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
779 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
780 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
781 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
782 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
783 rtl_write_byte(rtlpriv, REG_PBP, value8);
784}
785
786static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
787 u16 bkQ, u16 viQ, u16 voQ,
788 u16 mgtQ, u16 hiQ)
789{
790 struct rtl_priv *rtlpriv = rtl_priv(hw);
791 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
792
793 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
794 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
795 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
796 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
797}
798
799static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
800 bool wmm_enable,
801 u8 queue_sel)
802{
803 u16 uninitialized_var(value);
804
805 switch (queue_sel) {
806 case TX_SELE_HQ:
807 value = QUEUE_HIGH;
808 break;
809 case TX_SELE_LQ:
810 value = QUEUE_LOW;
811 break;
812 case TX_SELE_NQ:
813 value = QUEUE_NORMAL;
814 break;
815 default:
816 WARN_ON(1); /* Shall not reach here! */
817 break;
818 }
819 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
820 value, value);
821 printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel);
822}
823
824static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
825 bool wmm_enable,
826 u8 queue_sel)
827{
828 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
829 u16 uninitialized_var(valueHi);
830 u16 uninitialized_var(valueLow);
831
832 switch (queue_sel) {
833 case (TX_SELE_HQ | TX_SELE_LQ):
834 valueHi = QUEUE_HIGH;
835 valueLow = QUEUE_LOW;
836 break;
837 case (TX_SELE_NQ | TX_SELE_LQ):
838 valueHi = QUEUE_NORMAL;
839 valueLow = QUEUE_LOW;
840 break;
841 case (TX_SELE_HQ | TX_SELE_NQ):
842 valueHi = QUEUE_HIGH;
843 valueLow = QUEUE_NORMAL;
844 break;
845 default:
846 WARN_ON(1);
847 break;
848 }
849 if (!wmm_enable) {
850 beQ = valueLow;
851 bkQ = valueLow;
852 viQ = valueHi;
853 voQ = valueHi;
854 mgtQ = valueHi;
855 hiQ = valueHi;
856 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
857 beQ = valueHi;
858 bkQ = valueLow;
859 viQ = valueLow;
860 voQ = valueHi;
861 mgtQ = valueHi;
862 hiQ = valueHi;
863 }
864 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
865 printk(KERN_INFO "rtl8192cu: Tx queue select: 0x%02x\n", queue_sel);
866}
867
868static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
869 bool wmm_enable,
870 u8 queue_sel)
871{
872 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
873 struct rtl_priv *rtlpriv = rtl_priv(hw);
874
875 if (!wmm_enable) { /* typical setting */
876 beQ = QUEUE_LOW;
877 bkQ = QUEUE_LOW;
878 viQ = QUEUE_NORMAL;
879 voQ = QUEUE_HIGH;
880 mgtQ = QUEUE_HIGH;
881 hiQ = QUEUE_HIGH;
882 } else { /* for WMM */
883 beQ = QUEUE_LOW;
884 bkQ = QUEUE_NORMAL;
885 viQ = QUEUE_NORMAL;
886 voQ = QUEUE_HIGH;
887 mgtQ = QUEUE_HIGH;
888 hiQ = QUEUE_HIGH;
889 }
890 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
891 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
892 ("Tx queue select :0x%02x..\n", queue_sel));
893}
894
895static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
896 bool wmm_enable,
897 u8 out_ep_num,
898 u8 queue_sel)
899{
900 switch (out_ep_num) {
901 case 1:
902 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
903 queue_sel);
904 break;
905 case 2:
906 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
907 queue_sel);
908 break;
909 case 3:
910 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
911 queue_sel);
912 break;
913 default:
914 WARN_ON(1); /* Shall not reach here! */
915 break;
916 }
917}
918
919static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
920 bool wmm_enable,
921 u8 out_ep_num,
922 u8 queue_sel)
923{
924 u8 hq_sele;
925 struct rtl_priv *rtlpriv = rtl_priv(hw);
926
927 switch (out_ep_num) {
928 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
929 if (!wmm_enable) /* typical setting */
930 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
931 HQSEL_HIQ;
932 else /* for WMM */
933 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
934 HQSEL_HIQ;
935 break;
936 case 1:
937 if (TX_SELE_LQ == queue_sel) {
938 /* map all endpoint to Low queue */
939 hq_sele = 0;
940 } else if (TX_SELE_HQ == queue_sel) {
941 /* map all endpoint to High queue */
942 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
943 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
944 }
945 break;
946 default:
947 WARN_ON(1); /* Shall not reach here! */
948 break;
949 }
950 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
951 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
952 ("Tx queue select :0x%02x..\n", hq_sele));
953}
954
955static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
956 bool wmm_enable,
957 u8 out_ep_num,
958 u8 queue_sel)
959{
960 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
961 if (IS_NORMAL_CHIP(rtlhal->version))
962 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
963 queue_sel);
964 else
965 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
966 queue_sel);
967}
968
969static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
970{
971}
972
973static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
974{
975 u16 value16;
976
977 struct rtl_priv *rtlpriv = rtl_priv(hw);
978 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
979
980 mac->rx_conf = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APP_FCS |
981 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
982 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
983 rtl_write_dword(rtlpriv, REG_RCR, mac->rx_conf);
984 /* Accept all multicast address */
985 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
986 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
987 /* Accept all management frames */
988 value16 = 0xFFFF;
989 rtl92c_set_mgt_filter(hw, value16);
990 /* Reject all control frame - default value is 0 */
991 rtl92c_set_ctrl_filter(hw, 0x0);
992 /* Accept all data frames */
993 value16 = 0xFFFF;
994 rtl92c_set_data_filter(hw, value16);
995}
996
997static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
998{
999 struct rtl_priv *rtlpriv = rtl_priv(hw);
1000 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1001 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
1002 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
1003 int err = 0;
1004 u32 boundary = 0;
1005 u8 wmm_enable = false; /* TODO */
1006 u8 out_ep_nums = rtlusb->out_ep_nums;
1007 u8 queue_sel = rtlusb->out_queue_sel;
1008 err = _rtl92cu_init_power_on(hw);
1009
1010 if (err) {
1011 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1012 ("Failed to init power on!\n"));
1013 return err;
1014 }
1015 if (!wmm_enable) {
1016 boundary = TX_PAGE_BOUNDARY;
1017 } else { /* for WMM */
1018 boundary = (IS_NORMAL_CHIP(rtlhal->version))
1019 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
1020 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
1021 }
1022 if (false == rtl92c_init_llt_table(hw, boundary)) {
1023 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1024 ("Failed to init LLT Table!\n"));
1025 return -EINVAL;
1026 }
1027 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
1028 queue_sel);
1029 _rtl92c_init_trx_buffer(hw, wmm_enable);
1030 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
1031 queue_sel);
1032 /* Get Rx PHY status in order to report RSSI and others. */
1033 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
1034 rtl92c_init_interrupt(hw);
1035 rtl92c_init_network_type(hw);
1036 _rtl92cu_init_wmac_setting(hw);
1037 rtl92c_init_adaptive_ctrl(hw);
1038 rtl92c_init_edca(hw);
1039 rtl92c_init_rate_fallback(hw);
1040 rtl92c_init_retry_function(hw);
1041 _rtl92cu_init_usb_aggregation(hw);
1042 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
1043 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
1044 rtl92c_init_beacon_parameters(hw, rtlhal->version);
1045 rtl92c_init_ampdu_aggregation(hw);
1046 rtl92c_init_beacon_max_error(hw, true);
1047 return err;
1048}
1049
1050void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
1051{
1052 struct rtl_priv *rtlpriv = rtl_priv(hw);
1053 u8 sec_reg_value = 0x0;
1054 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1055
1056 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1057 ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1058 rtlpriv->sec.pairwise_enc_algorithm,
1059 rtlpriv->sec.group_enc_algorithm));
1060 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1061 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1062 ("not open sw encryption\n"));
1063 return;
1064 }
1065 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
1066 if (rtlpriv->sec.use_defaultkey) {
1067 sec_reg_value |= SCR_TxUseDK;
1068 sec_reg_value |= SCR_RxUseDK;
1069 }
1070 if (IS_NORMAL_CHIP(rtlhal->version))
1071 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1072 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1073 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
1074 ("The SECR-value %x\n", sec_reg_value));
1075 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1076}
1077
1078static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
1079{
1080 struct rtl_priv *rtlpriv = rtl_priv(hw);
1081 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1082
1083 /* To Fix MAC loopback mode fail. */
1084 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
1085 rtl_write_byte(rtlpriv, 0x15, 0xe9);
1086 /* HW SEQ CTRL */
1087 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
1088 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
1089 /* fixed USB interface interference issue */
1090 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
1091 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
1092 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
1093 rtlusb->reg_bcn_ctrl_val = 0x18;
1094 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1095}
1096
1097static void _InitPABias(struct ieee80211_hw *hw)
1098{
1099 struct rtl_priv *rtlpriv = rtl_priv(hw);
1100 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1101 u8 pa_setting;
1102
1103 /* FIXED PA current issue */
1104 pa_setting = efuse_read_1byte(hw, 0x1FA);
1105 if (!(pa_setting & BIT(0))) {
1106 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
1107 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
1108 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
1109 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
1110 }
1111 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
1112 IS_92C_SERIAL(rtlhal->version)) {
1113 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
1114 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
1115 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
1116 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
1117 }
1118 if (!(pa_setting & BIT(4))) {
1119 pa_setting = rtl_read_byte(rtlpriv, 0x16);
1120 pa_setting &= 0x0F;
1121 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
1122 }
1123}
1124
1125static void _InitAntenna_Selection(struct ieee80211_hw *hw)
1126{
1127#ifdef CONFIG_ANTENNA_DIVERSITY
1128 struct rtl_priv *rtlpriv = rtl_priv(hw);
1129 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1130 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1131
1132 if (pHalData->AntDivCfg == 0)
1133 return;
1134
1135 if (rtlphy->rf_type == RF_1T1R) {
1136 rtl_write_dword(rtlpriv, REG_LEDCFG0,
1137 rtl_read_dword(rtlpriv,
1138 REG_LEDCFG0)|BIT(23));
1139 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1140 if (rtl_get_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300) ==
1141 Antenna_A)
1142 pHalData->CurAntenna = Antenna_A;
1143 else
1144 pHalData->CurAntenna = Antenna_B;
1145 }
1146#endif
1147}
1148
1149static void _dump_registers(struct ieee80211_hw *hw)
1150{
1151}
1152
1153static void _update_mac_setting(struct ieee80211_hw *hw)
1154{
1155 struct rtl_priv *rtlpriv = rtl_priv(hw);
1156 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1157
1158 mac->rx_conf = rtl_read_dword(rtlpriv, REG_RCR);
1159 mac->rx_mgt_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1160 mac->rx_ctrl_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1161 mac->rx_data_filter = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1162}
1163
1164int rtl92cu_hw_init(struct ieee80211_hw *hw)
1165{
1166 struct rtl_priv *rtlpriv = rtl_priv(hw);
1167 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1168 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1169 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1170 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1171 int err = 0;
1172 static bool iqk_initialized;
1173
1174 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1175 err = _rtl92cu_init_mac(hw);
1176 if (err) {
1177 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("init mac failed!\n"));
1178 return err;
1179 }
1180 err = rtl92c_download_fw(hw);
1181 if (err) {
1182 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1183 ("Failed to download FW. Init HW without FW now..\n"));
1184 err = 1;
1185 rtlhal->fw_ready = false;
1186 return err;
1187 } else {
1188 rtlhal->fw_ready = true;
1189 }
1190 rtlhal->last_hmeboxnum = 0; /* h2c */
1191 _rtl92cu_phy_param_tab_init(hw);
1192 rtl92cu_phy_mac_config(hw);
1193 rtl92cu_phy_bb_config(hw);
1194 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1195 rtl92c_phy_rf_config(hw);
1196 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1197 !IS_92C_SERIAL(rtlhal->version)) {
1198 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1199 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1200 }
1201 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1202 RF_CHNLBW, RFREG_OFFSET_MASK);
1203 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1204 RF_CHNLBW, RFREG_OFFSET_MASK);
1205 rtl92cu_bb_block_on(hw);
1206 rtl_cam_reset_all_entry(hw);
1207 rtl92cu_enable_hw_security_config(hw);
1208 ppsc->rfpwr_state = ERFON;
1209 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1210 if (ppsc->rfpwr_state == ERFON) {
1211 rtl92c_phy_set_rfpath_switch(hw, 1);
1212 if (iqk_initialized) {
1213 rtl92c_phy_iq_calibrate(hw, false);
1214 } else {
1215 rtl92c_phy_iq_calibrate(hw, false);
1216 iqk_initialized = true;
1217 }
1218 rtl92c_dm_check_txpower_tracking(hw);
1219 rtl92c_phy_lc_calibrate(hw);
1220 }
1221 _rtl92cu_hw_configure(hw);
1222 _InitPABias(hw);
1223 _InitAntenna_Selection(hw);
1224 _update_mac_setting(hw);
1225 rtl92c_dm_init(hw);
1226 _dump_registers(hw);
1227 return err;
1228}
1229
1230static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1231{
1232 struct rtl_priv *rtlpriv = rtl_priv(hw);
1233/**************************************
1234a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1235b. RF path 0 offset 0x00 = 0x00 disable RF
1236c. APSD_CTRL 0x600[7:0] = 0x40
1237d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1238e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1239***************************************/
1240 u8 eRFPath = 0, value8 = 0;
1241 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1242 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1243
1244 value8 |= APSDOFF;
1245 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1246 value8 = 0;
1247 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1248 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1249 value8 &= (~FEN_BB_GLB_RSTn);
1250 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1251}
1252
1253static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1254{
1255 struct rtl_priv *rtlpriv = rtl_priv(hw);
1256 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1257
1258 if (rtlhal->fw_version <= 0x20) {
1259 /*****************************
1260 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1261 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)
1262 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE
1263 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)
1264 ******************************/
1265 u16 valu16 = 0;
1266
1267 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1268 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1269 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1270 (~FEN_CPUEN))); /* reset MCU ,8051 */
1271 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1272 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1273 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1274 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1275 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1276 FEN_CPUEN)); /* enable MCU ,8051 */
1277 } else {
1278 u8 retry_cnts = 0;
1279
1280 /* IF fw in RAM code, do reset */
1281 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1282 /* reset MCU ready status */
1283 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1284 if (rtlhal->fw_ready) {
1285 /* 8051 reset by self */
1286 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1287 while ((retry_cnts++ < 100) &&
1288 (FEN_CPUEN & rtl_read_word(rtlpriv,
1289 REG_SYS_FUNC_EN))) {
1290 udelay(50);
1291 }
1292 if (retry_cnts >= 100) {
1293 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1294 ("#####=> 8051 reset failed!.."
1295 ".......................\n"););
1296 /* if 8051 reset fail, reset MAC. */
1297 rtl_write_byte(rtlpriv,
1298 REG_SYS_FUNC_EN + 1,
1299 0x50);
1300 udelay(100);
1301 }
1302 }
1303 }
1304 /* Reset MAC and Enable 8051 */
1305 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1306 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1307 }
1308 if (bWithoutHWSM) {
1309 /*****************************
1310 Without HW auto state machine
1311 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1312 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1313 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1314 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1315 ******************************/
1316 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1317 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1318 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1319 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1320 }
1321}
1322
1323static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1324{
1325 struct rtl_priv *rtlpriv = rtl_priv(hw);
1326/*****************************
1327k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1328l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1329m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1330******************************/
1331 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1332 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1333}
1334
1335static void _DisableGPIO(struct ieee80211_hw *hw)
1336{
1337 struct rtl_priv *rtlpriv = rtl_priv(hw);
1338/***************************************
1339j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1340k. Value = GPIO_PIN_CTRL[7:0]
1341l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1342m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1343n. LEDCFG 0x4C[15:0] = 0x8080
1344***************************************/
1345 u8 value8;
1346 u16 value16;
1347 u32 value32;
1348
1349 /* 1. Disable GPIO[7:0] */
1350 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1351 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1352 value8 = (u8) (value32&0x000000FF);
1353 value32 |= ((value8<<8) | 0x00FF0000);
1354 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1355 /* 2. Disable GPIO[10:8] */
1356 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1357 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1358 value8 = (u8) (value16&0x000F);
1359 value16 |= ((value8<<4) | 0x0780);
1360 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1361 /* 3. Disable LED0 & 1 */
1362 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1363}
1364
1365static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1366{
1367 struct rtl_priv *rtlpriv = rtl_priv(hw);
1368 u16 value16 = 0;
1369 u8 value8 = 0;
1370
1371 if (bWithoutHWSM) {
1372 /*****************************
1373 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1374 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1375 r. When driver call disable, the ASIC will turn off remaining
1376 clock automatically
1377 ******************************/
1378 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1379 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1380 value8 &= (~LDV12_EN);
1381 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1382 }
1383
1384/*****************************
1385h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1386i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1387******************************/
1388 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1389 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1390 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1391 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1392}
1393
1394static void _CardDisableHWSM(struct ieee80211_hw *hw)
1395{
1396 /* ==== RF Off Sequence ==== */
1397 _DisableRFAFEAndResetBB(hw);
1398 /* ==== Reset digital sequence ====== */
1399 _ResetDigitalProcedure1(hw, false);
1400 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1401 _DisableGPIO(hw);
1402 /* ==== Disable analog sequence === */
1403 _DisableAnalog(hw, false);
1404}
1405
1406static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1407{
1408 /*==== RF Off Sequence ==== */
1409 _DisableRFAFEAndResetBB(hw);
1410 /* ==== Reset digital sequence ====== */
1411 _ResetDigitalProcedure1(hw, true);
1412 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1413 _DisableGPIO(hw);
1414 /* ==== Reset digital sequence ====== */
1415 _ResetDigitalProcedure2(hw);
1416 /* ==== Disable analog sequence === */
1417 _DisableAnalog(hw, true);
1418}
1419
1420static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1421 u8 set_bits, u8 clear_bits)
1422{
1423 struct rtl_priv *rtlpriv = rtl_priv(hw);
1424 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1425
1426 rtlusb->reg_bcn_ctrl_val |= set_bits;
1427 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1428 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlusb->reg_bcn_ctrl_val);
1429}
1430
1431static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1432{
1433 struct rtl_priv *rtlpriv = rtl_priv(hw);
1434 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1435 u8 tmp1byte = 0;
1436 if (IS_NORMAL_CHIP(rtlhal->version)) {
1437 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1438 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1439 tmp1byte & (~BIT(6)));
1440 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1441 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1442 tmp1byte &= ~(BIT(0));
1443 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1444 } else {
1445 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1446 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1447 }
1448}
1449
1450static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1451{
1452 struct rtl_priv *rtlpriv = rtl_priv(hw);
1453 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1454 u8 tmp1byte = 0;
1455
1456 if (IS_NORMAL_CHIP(rtlhal->version)) {
1457 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1458 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1459 tmp1byte | BIT(6));
1460 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1461 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1462 tmp1byte |= BIT(0);
1463 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1464 } else {
1465 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1466 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1467 }
1468}
1469
1470static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1471{
1472 struct rtl_priv *rtlpriv = rtl_priv(hw);
1473 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1474
1475 if (IS_NORMAL_CHIP(rtlhal->version))
1476 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1477 else
1478 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1479}
1480
1481static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1482{
1483 struct rtl_priv *rtlpriv = rtl_priv(hw);
1484 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1485
1486 if (IS_NORMAL_CHIP(rtlhal->version))
1487 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1488 else
1489 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1490}
1491
1492static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1493 enum nl80211_iftype type)
1494{
1495 struct rtl_priv *rtlpriv = rtl_priv(hw);
1496 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1497 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1498
1499 bt_msr &= 0xfc;
1500 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
1501 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1502 NL80211_IFTYPE_STATION) {
1503 _rtl92cu_stop_tx_beacon(hw);
1504 _rtl92cu_enable_bcn_sub_func(hw);
1505 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1506 _rtl92cu_resume_tx_beacon(hw);
1507 _rtl92cu_disable_bcn_sub_func(hw);
1508 } else {
1509 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, ("Set HW_VAR_MEDIA_"
1510 "STATUS:No such media status(%x).\n", type));
1511 }
1512 switch (type) {
1513 case NL80211_IFTYPE_UNSPECIFIED:
1514 bt_msr |= MSR_NOLINK;
1515 ledaction = LED_CTL_LINK;
1516 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1517 ("Set Network type to NO LINK!\n"));
1518 break;
1519 case NL80211_IFTYPE_ADHOC:
1520 bt_msr |= MSR_ADHOC;
1521 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1522 ("Set Network type to Ad Hoc!\n"));
1523 break;
1524 case NL80211_IFTYPE_STATION:
1525 bt_msr |= MSR_INFRA;
1526 ledaction = LED_CTL_LINK;
1527 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1528 ("Set Network type to STA!\n"));
1529 break;
1530 case NL80211_IFTYPE_AP:
1531 bt_msr |= MSR_AP;
1532 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1533 ("Set Network type to AP!\n"));
1534 break;
1535 default:
1536 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1537 ("Network type %d not support!\n", type));
1538 goto error_out;
1539 }
1540 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1541 rtlpriv->cfg->ops->led_control(hw, ledaction);
1542 if ((bt_msr & 0xfc) == MSR_AP)
1543 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1544 else
1545 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1546 return 0;
1547error_out:
1548 return 1;
1549}
1550
1551void rtl92cu_card_disable(struct ieee80211_hw *hw)
1552{
1553 struct rtl_priv *rtlpriv = rtl_priv(hw);
1554 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1555 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1556 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1557 enum nl80211_iftype opmode;
1558
1559 mac->link_state = MAC80211_NOLINK;
1560 opmode = NL80211_IFTYPE_UNSPECIFIED;
1561 _rtl92cu_set_media_status(hw, opmode);
1562 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1563 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1564 if (rtlusb->disableHWSM)
1565 _CardDisableHWSM(hw);
1566 else
1567 _CardDisableWithoutHWSM(hw);
1568}
1569
1570void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1571{
1572 /* dummy routine needed for callback from rtl_op_configure_filter() */
1573}
1574
1575/*========================================================================== */
1576
1577static void _rtl92cu_set_check_bssid(struct ieee80211_hw *hw,
1578 enum nl80211_iftype type)
1579{
1580 struct rtl_priv *rtlpriv = rtl_priv(hw);
1581 u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1582 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1583 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1584 u8 filterout_non_associated_bssid = false;
1585
1586 switch (type) {
1587 case NL80211_IFTYPE_ADHOC:
1588 case NL80211_IFTYPE_STATION:
1589 filterout_non_associated_bssid = true;
1590 break;
1591 case NL80211_IFTYPE_UNSPECIFIED:
1592 case NL80211_IFTYPE_AP:
1593 default:
1594 break;
1595 }
1596 if (filterout_non_associated_bssid == true) {
1597 if (IS_NORMAL_CHIP(rtlhal->version)) {
1598 switch (rtlphy->current_io_type) {
1599 case IO_CMD_RESUME_DM_BY_SCAN:
1600 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1601 rtlpriv->cfg->ops->set_hw_reg(hw,
1602 HW_VAR_RCR, (u8 *)(&reg_rcr));
1603 /* enable update TSF */
1604 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1605 break;
1606 case IO_CMD_PAUSE_DM_BY_SCAN:
1607 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1608 rtlpriv->cfg->ops->set_hw_reg(hw,
1609 HW_VAR_RCR, (u8 *)(&reg_rcr));
1610 /* disable update TSF */
1611 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1612 break;
1613 }
1614 } else {
1615 reg_rcr |= (RCR_CBSSID);
1616 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1617 (u8 *)(&reg_rcr));
1618 _rtl92cu_set_bcn_ctrl_reg(hw, 0, (BIT(4)|BIT(5)));
1619 }
1620 } else if (filterout_non_associated_bssid == false) {
1621 if (IS_NORMAL_CHIP(rtlhal->version)) {
1622 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1623 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1624 (u8 *)(&reg_rcr));
1625 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1626 } else {
1627 reg_rcr &= (~RCR_CBSSID);
1628 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1629 (u8 *)(&reg_rcr));
1630 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4)|BIT(5)), 0);
1631 }
1632 }
1633}
1634
1635int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1636{
1637 if (_rtl92cu_set_media_status(hw, type))
1638 return -EOPNOTSUPP;
1639 _rtl92cu_set_check_bssid(hw, type);
1640 return 0;
1641}
1642
1643static void _InitBeaconParameters(struct ieee80211_hw *hw)
1644{
1645 struct rtl_priv *rtlpriv = rtl_priv(hw);
1646 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1647
1648 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
1649
1650 /* TODO: Remove these magic number */
1651 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
1652 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
1653 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
1654 /* Change beacon AIFS to the largest number
1655 * beacause test chip does not contension before sending beacon. */
1656 if (IS_NORMAL_CHIP(rtlhal->version))
1657 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
1658 else
1659 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
1660}
1661
1662static void _beacon_function_enable(struct ieee80211_hw *hw, bool Enable,
1663 bool Linked)
1664{
1665 struct rtl_priv *rtlpriv = rtl_priv(hw);
1666
1667 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1668 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1669}
1670
1671void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1672{
1673
1674 struct rtl_priv *rtlpriv = rtl_priv(hw);
1675 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1676 u16 bcn_interval, atim_window;
1677 u32 value32;
1678
1679 bcn_interval = mac->beacon_interval;
1680 atim_window = 2; /*FIX MERGE */
1681 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1682 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1683 _InitBeaconParameters(hw);
1684 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1685 /*
1686 * Force beacon frame transmission even after receiving beacon frame
1687 * from other ad hoc STA
1688 *
1689 *
1690 * Reset TSF Timer to zero, added by Roger. 2008.06.24
1691 */
1692 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1693 value32 &= ~TSFRST;
1694 rtl_write_dword(rtlpriv, REG_TCR, value32);
1695 value32 |= TSFRST;
1696 rtl_write_dword(rtlpriv, REG_TCR, value32);
1697 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1698 ("SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1699 value32));
1700 /* TODO: Modify later (Find the right parameters)
1701 * NOTE: Fix test chip's bug (about contention windows's randomness) */
1702 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1703 (mac->opmode == NL80211_IFTYPE_AP)) {
1704 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1705 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1706 }
1707 _beacon_function_enable(hw, true, true);
1708}
1709
1710void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1711{
1712 struct rtl_priv *rtlpriv = rtl_priv(hw);
1713 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1714 u16 bcn_interval = mac->beacon_interval;
1715
1716 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1717 ("beacon_interval:%d\n", bcn_interval));
1718 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1719}
1720
1721void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1722 u32 add_msr, u32 rm_msr)
1723{
1724}
1725
1726void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1727{
1728 struct rtl_priv *rtlpriv = rtl_priv(hw);
1729 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1730 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1731
1732 switch (variable) {
1733 case HW_VAR_RCR:
1734 *((u32 *)(val)) = mac->rx_conf;
1735 break;
1736 case HW_VAR_RF_STATE:
1737 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1738 break;
1739 case HW_VAR_FWLPS_RF_ON:{
1740 enum rf_pwrstate rfState;
1741 u32 val_rcr;
1742
1743 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1744 (u8 *)(&rfState));
1745 if (rfState == ERFOFF) {
1746 *((bool *) (val)) = true;
1747 } else {
1748 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1749 val_rcr &= 0x00070000;
1750 if (val_rcr)
1751 *((bool *) (val)) = false;
1752 else
1753 *((bool *) (val)) = true;
1754 }
1755 break;
1756 }
1757 case HW_VAR_FW_PSMODE_STATUS:
1758 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1759 break;
1760 case HW_VAR_CORRECT_TSF:{
1761 u64 tsf;
1762 u32 *ptsf_low = (u32 *)&tsf;
1763 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1764
1765 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1766 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1767 *((u64 *)(val)) = tsf;
1768 break;
1769 }
1770 case HW_VAR_MGT_FILTER:
1771 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1772 break;
1773 case HW_VAR_CTRL_FILTER:
1774 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1775 break;
1776 case HW_VAR_DATA_FILTER:
1777 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1778 break;
1779 default:
1780 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1781 ("switch case not process\n"));
1782 break;
1783 }
1784}
1785
1786void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1787{
1788 struct rtl_priv *rtlpriv = rtl_priv(hw);
1789 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1790 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1791 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1792 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1793 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1794 enum wireless_mode wirelessmode = mac->mode;
1795 u8 idx = 0;
1796
1797 switch (variable) {
1798 case HW_VAR_ETHER_ADDR:{
1799 for (idx = 0; idx < ETH_ALEN; idx++) {
1800 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1801 val[idx]);
1802 }
1803 break;
1804 }
1805 case HW_VAR_BASIC_RATE:{
1806 u16 rate_cfg = ((u16 *) val)[0];
1807 u8 rate_index = 0;
1808
1809 rate_cfg &= 0x15f;
1810 /* TODO */
1811 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1812 * && ((rate_cfg & 0x150) == 0)) {
1813 * rate_cfg |= 0x010;
1814 * } */
1815 rate_cfg |= 0x01;
1816 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1817 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1818 (rate_cfg >> 8) & 0xff);
1819 while (rate_cfg > 0x1) {
1820 rate_cfg >>= 1;
1821 rate_index++;
1822 }
1823 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1824 rate_index);
1825 break;
1826 }
1827 case HW_VAR_BSSID:{
1828 for (idx = 0; idx < ETH_ALEN; idx++) {
1829 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1830 val[idx]);
1831 }
1832 break;
1833 }
1834 case HW_VAR_SIFS:{
1835 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1836 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1837 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1838 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1839 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1840 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1841 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1842 ("HW_VAR_SIFS\n"));
1843 break;
1844 }
1845 case HW_VAR_SLOT_TIME:{
1846 u8 e_aci;
1847 u8 QOS_MODE = 1;
1848
1849 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1850 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1851 ("HW_VAR_SLOT_TIME %x\n", val[0]));
1852 if (QOS_MODE) {
1853 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1854 rtlpriv->cfg->ops->set_hw_reg(hw,
1855 HW_VAR_AC_PARAM,
1856 (u8 *)(&e_aci));
1857 } else {
1858 u8 sifstime = 0;
1859 u8 u1bAIFS;
1860
1861 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1862 IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1863 IS_WIRELESS_MODE_N_5G(wirelessmode))
1864 sifstime = 16;
1865 else
1866 sifstime = 10;
1867 u1bAIFS = sifstime + (2 * val[0]);
1868 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1869 u1bAIFS);
1870 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1871 u1bAIFS);
1872 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1873 u1bAIFS);
1874 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1875 u1bAIFS);
1876 }
1877 break;
1878 }
1879 case HW_VAR_ACK_PREAMBLE:{
1880 u8 reg_tmp;
1881 u8 short_preamble = (bool) (*(u8 *) val);
1882 reg_tmp = 0;
1883 if (short_preamble)
1884 reg_tmp |= 0x80;
1885 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1886 break;
1887 }
1888 case HW_VAR_AMPDU_MIN_SPACE:{
1889 u8 min_spacing_to_set;
1890 u8 sec_min_space;
1891
1892 min_spacing_to_set = *((u8 *) val);
1893 if (min_spacing_to_set <= 7) {
1894 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1895 case NO_ENCRYPTION:
1896 case AESCCMP_ENCRYPTION:
1897 sec_min_space = 0;
1898 break;
1899 case WEP40_ENCRYPTION:
1900 case WEP104_ENCRYPTION:
1901 case TKIP_ENCRYPTION:
1902 sec_min_space = 6;
1903 break;
1904 default:
1905 sec_min_space = 7;
1906 break;
1907 }
1908 if (min_spacing_to_set < sec_min_space)
1909 min_spacing_to_set = sec_min_space;
1910 mac->min_space_cfg = ((mac->min_space_cfg &
1911 0xf8) |
1912 min_spacing_to_set);
1913 *val = min_spacing_to_set;
1914 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1915 ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1916 mac->min_space_cfg));
1917 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1918 mac->min_space_cfg);
1919 }
1920 break;
1921 }
1922 case HW_VAR_SHORTGI_DENSITY:{
1923 u8 density_to_set;
1924
1925 density_to_set = *((u8 *) val);
1926 density_to_set &= 0x1f;
1927 mac->min_space_cfg &= 0x07;
1928 mac->min_space_cfg |= (density_to_set << 3);
1929 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1930 ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1931 mac->min_space_cfg));
1932 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1933 mac->min_space_cfg);
1934 break;
1935 }
1936 case HW_VAR_AMPDU_FACTOR:{
1937 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1938 u8 factor_toset;
1939 u8 *p_regtoset = NULL;
1940 u8 index = 0;
1941
1942 p_regtoset = regtoset_normal;
1943 factor_toset = *((u8 *) val);
1944 if (factor_toset <= 3) {
1945 factor_toset = (1 << (factor_toset + 2));
1946 if (factor_toset > 0xf)
1947 factor_toset = 0xf;
1948 for (index = 0; index < 4; index++) {
1949 if ((p_regtoset[index] & 0xf0) >
1950 (factor_toset << 4))
1951 p_regtoset[index] =
1952 (p_regtoset[index] & 0x0f)
1953 | (factor_toset << 4);
1954 if ((p_regtoset[index] & 0x0f) >
1955 factor_toset)
1956 p_regtoset[index] =
1957 (p_regtoset[index] & 0xf0)
1958 | (factor_toset);
1959 rtl_write_byte(rtlpriv,
1960 (REG_AGGLEN_LMT + index),
1961 p_regtoset[index]);
1962 }
1963 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1964 ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
1965 factor_toset));
1966 }
1967 break;
1968 }
1969 case HW_VAR_AC_PARAM:{
1970 u8 e_aci = *((u8 *) val);
1971 u32 u4b_ac_param;
1972 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1973 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1974 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1975
1976 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1977 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1978 AC_PARAM_ECW_MIN_OFFSET);
1979 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1980 AC_PARAM_ECW_MAX_OFFSET);
1981 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1982 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1983 ("queue:%x, ac_param:%x\n", e_aci,
1984 u4b_ac_param));
1985 switch (e_aci) {
1986 case AC1_BK:
1987 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1988 u4b_ac_param);
1989 break;
1990 case AC0_BE:
1991 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1992 u4b_ac_param);
1993 break;
1994 case AC2_VI:
1995 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1996 u4b_ac_param);
1997 break;
1998 case AC3_VO:
1999 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
2000 u4b_ac_param);
2001 break;
2002 default:
2003 RT_ASSERT(false, ("SetHwReg8185(): invalid"
2004 " aci: %d !\n", e_aci));
2005 break;
2006 }
2007 if (rtlusb->acm_method != eAcmWay2_SW)
2008 rtlpriv->cfg->ops->set_hw_reg(hw,
2009 HW_VAR_ACM_CTRL, (u8 *)(&e_aci));
2010 break;
2011 }
2012 case HW_VAR_ACM_CTRL:{
2013 u8 e_aci = *((u8 *) val);
2014 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)
2015 (&(mac->ac[0].aifs));
2016 u8 acm = p_aci_aifsn->f.acm;
2017 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
2018
2019 acm_ctrl =
2020 acm_ctrl | ((rtlusb->acm_method == 2) ? 0x0 : 0x1);
2021 if (acm) {
2022 switch (e_aci) {
2023 case AC0_BE:
2024 acm_ctrl |= AcmHw_BeqEn;
2025 break;
2026 case AC2_VI:
2027 acm_ctrl |= AcmHw_ViqEn;
2028 break;
2029 case AC3_VO:
2030 acm_ctrl |= AcmHw_VoqEn;
2031 break;
2032 default:
2033 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
2034 ("HW_VAR_ACM_CTRL acm set "
2035 "failed: eACI is %d\n", acm));
2036 break;
2037 }
2038 } else {
2039 switch (e_aci) {
2040 case AC0_BE:
2041 acm_ctrl &= (~AcmHw_BeqEn);
2042 break;
2043 case AC2_VI:
2044 acm_ctrl &= (~AcmHw_ViqEn);
2045 break;
2046 case AC3_VO:
2047 acm_ctrl &= (~AcmHw_BeqEn);
2048 break;
2049 default:
2050 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2051 ("switch case not process\n"));
2052 break;
2053 }
2054 }
2055 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
2056 ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
2057 "Write 0x%X\n", acm_ctrl));
2058 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
2059 break;
2060 }
2061 case HW_VAR_RCR:{
2062 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
2063 mac->rx_conf = ((u32 *) (val))[0];
2064 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
2065 ("### Set RCR(0x%08x) ###\n", mac->rx_conf));
2066 break;
2067 }
2068 case HW_VAR_RETRY_LIMIT:{
2069 u8 retry_limit = ((u8 *) (val))[0];
2070
2071 rtl_write_word(rtlpriv, REG_RL,
2072 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
2073 retry_limit << RETRY_LIMIT_LONG_SHIFT);
2074 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG, ("Set HW_VAR_R"
2075 "ETRY_LIMIT(0x%08x)\n", retry_limit));
2076 break;
2077 }
2078 case HW_VAR_DUAL_TSF_RST:
2079 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
2080 break;
2081 case HW_VAR_EFUSE_BYTES:
2082 rtlefuse->efuse_usedbytes = *((u16 *) val);
2083 break;
2084 case HW_VAR_EFUSE_USAGE:
2085 rtlefuse->efuse_usedpercentage = *((u8 *) val);
2086 break;
2087 case HW_VAR_IO_CMD:
2088 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
2089 break;
2090 case HW_VAR_WPA_CONFIG:
2091 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
2092 break;
2093 case HW_VAR_SET_RPWM:{
2094 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
2095
2096 if (rpwm_val & BIT(7))
2097 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2098 (*(u8 *)val));
2099 else
2100 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
2101 ((*(u8 *)val) | BIT(7)));
2102 break;
2103 }
2104 case HW_VAR_H2C_FW_PWRMODE:{
2105 u8 psmode = (*(u8 *) val);
2106
2107 if ((psmode != FW_PS_ACTIVE_MODE) &&
2108 (!IS_92C_SERIAL(rtlhal->version)))
2109 rtl92c_dm_rf_saving(hw, true);
2110 rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
2111 break;
2112 }
2113 case HW_VAR_FW_PSMODE_STATUS:
2114 ppsc->fw_current_inpsmode = *((bool *) val);
2115 break;
2116 case HW_VAR_H2C_FW_JOINBSSRPT:{
2117 u8 mstatus = (*(u8 *) val);
2118 u8 tmp_reg422;
2119 bool recover = false;
2120
2121 if (mstatus == RT_MEDIA_CONNECT) {
2122 rtlpriv->cfg->ops->set_hw_reg(hw,
2123 HW_VAR_AID, NULL);
2124 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
2125 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2126 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
2127 tmp_reg422 = rtl_read_byte(rtlpriv,
2128 REG_FWHW_TXQ_CTRL + 2);
2129 if (tmp_reg422 & BIT(6))
2130 recover = true;
2131 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
2132 tmp_reg422 & (~BIT(6)));
2133 rtl92c_set_fw_rsvdpagepkt(hw, 0);
2134 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2135 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
2136 if (recover)
2137 rtl_write_byte(rtlpriv,
2138 REG_FWHW_TXQ_CTRL + 2,
2139 tmp_reg422 | BIT(6));
2140 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
2141 }
2142 rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
2143 break;
2144 }
2145 case HW_VAR_AID:{
2146 u16 u2btmp;
2147
2148 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
2149 u2btmp &= 0xC000;
2150 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
2151 (u2btmp | mac->assoc_id));
2152 break;
2153 }
2154 case HW_VAR_CORRECT_TSF:{
2155 u8 btype_ibss = ((u8 *) (val))[0];
2156
2157 if (btype_ibss == true)
2158 _rtl92cu_stop_tx_beacon(hw);
2159 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
2160 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
2161 0xffffffff));
2162 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
2163 (u32)((mac->tsf >> 32) & 0xffffffff));
2164 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
2165 if (btype_ibss == true)
2166 _rtl92cu_resume_tx_beacon(hw);
2167 break;
2168 }
2169 case HW_VAR_MGT_FILTER:
2170 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
2171 break;
2172 case HW_VAR_CTRL_FILTER:
2173 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
2174 break;
2175 case HW_VAR_DATA_FILTER:
2176 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
2177 break;
2178 default:
2179 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2180 "not process\n"));
2181 break;
2182 }
2183}
2184
2185void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw)
2186{
2187 struct rtl_priv *rtlpriv = rtl_priv(hw);
2188 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2189 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2190 u32 ratr_value = (u32) mac->basic_rates;
2191 u8 *mcsrate = mac->mcs;
2192 u8 ratr_index = 0;
2193 u8 nmode = mac->ht_enable;
2194 u8 mimo_ps = 1;
2195 u16 shortgi_rate = 0;
2196 u32 tmp_ratr_value = 0;
2197 u8 curtxbw_40mhz = mac->bw_40;
2198 u8 curshortgi_40mhz = mac->sgi_40;
2199 u8 curshortgi_20mhz = mac->sgi_20;
2200 enum wireless_mode wirelessmode = mac->mode;
2201
2202 ratr_value |= ((*(u16 *) (mcsrate))) << 12;
2203 switch (wirelessmode) {
2204 case WIRELESS_MODE_B:
2205 if (ratr_value & 0x0000000c)
2206 ratr_value &= 0x0000000d;
2207 else
2208 ratr_value &= 0x0000000f;
2209 break;
2210 case WIRELESS_MODE_G:
2211 ratr_value &= 0x00000FF5;
2212 break;
2213 case WIRELESS_MODE_N_24G:
2214 case WIRELESS_MODE_N_5G:
2215 nmode = 1;
2216 if (mimo_ps == 0) {
2217 ratr_value &= 0x0007F005;
2218 } else {
2219 u32 ratr_mask;
2220
2221 if (get_rf_type(rtlphy) == RF_1T2R ||
2222 get_rf_type(rtlphy) == RF_1T1R)
2223 ratr_mask = 0x000ff005;
2224 else
2225 ratr_mask = 0x0f0ff005;
2226 if (curtxbw_40mhz)
2227 ratr_mask |= 0x00000010;
2228 ratr_value &= ratr_mask;
2229 }
2230 break;
2231 default:
2232 if (rtlphy->rf_type == RF_1T2R)
2233 ratr_value &= 0x000ff0ff;
2234 else
2235 ratr_value &= 0x0f0ff0ff;
2236 break;
2237 }
2238 ratr_value &= 0x0FFFFFFF;
2239 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
2240 (!curtxbw_40mhz && curshortgi_20mhz))) {
2241 ratr_value |= 0x10000000;
2242 tmp_ratr_value = (ratr_value >> 12);
2243 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2244 if ((1 << shortgi_rate) & tmp_ratr_value)
2245 break;
2246 }
2247 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2248 (shortgi_rate << 4) | (shortgi_rate);
2249 }
2250 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2251 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("%x\n", rtl_read_dword(rtlpriv,
2252 REG_ARFR0)));
2253}
2254
2255void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
2256{
2257 struct rtl_priv *rtlpriv = rtl_priv(hw);
2258 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2259 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2260 u32 ratr_bitmap = (u32) mac->basic_rates;
2261 u8 *p_mcsrate = mac->mcs;
2262 u8 ratr_index = 0;
2263 u8 curtxbw_40mhz = mac->bw_40;
2264 u8 curshortgi_40mhz = mac->sgi_40;
2265 u8 curshortgi_20mhz = mac->sgi_20;
2266 enum wireless_mode wirelessmode = mac->mode;
2267 bool shortgi = false;
2268 u8 rate_mask[5];
2269 u8 macid = 0;
2270 u8 mimops = 1;
2271
2272 ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
2273 switch (wirelessmode) {
2274 case WIRELESS_MODE_B:
2275 ratr_index = RATR_INX_WIRELESS_B;
2276 if (ratr_bitmap & 0x0000000c)
2277 ratr_bitmap &= 0x0000000d;
2278 else
2279 ratr_bitmap &= 0x0000000f;
2280 break;
2281 case WIRELESS_MODE_G:
2282 ratr_index = RATR_INX_WIRELESS_GB;
2283 if (rssi_level == 1)
2284 ratr_bitmap &= 0x00000f00;
2285 else if (rssi_level == 2)
2286 ratr_bitmap &= 0x00000ff0;
2287 else
2288 ratr_bitmap &= 0x00000ff5;
2289 break;
2290 case WIRELESS_MODE_A:
2291 ratr_index = RATR_INX_WIRELESS_A;
2292 ratr_bitmap &= 0x00000ff0;
2293 break;
2294 case WIRELESS_MODE_N_24G:
2295 case WIRELESS_MODE_N_5G:
2296 ratr_index = RATR_INX_WIRELESS_NGB;
2297 if (mimops == 0) {
2298 if (rssi_level == 1)
2299 ratr_bitmap &= 0x00070000;
2300 else if (rssi_level == 2)
2301 ratr_bitmap &= 0x0007f000;
2302 else
2303 ratr_bitmap &= 0x0007f005;
2304 } else {
2305 if (rtlphy->rf_type == RF_1T2R ||
2306 rtlphy->rf_type == RF_1T1R) {
2307 if (curtxbw_40mhz) {
2308 if (rssi_level == 1)
2309 ratr_bitmap &= 0x000f0000;
2310 else if (rssi_level == 2)
2311 ratr_bitmap &= 0x000ff000;
2312 else
2313 ratr_bitmap &= 0x000ff015;
2314 } else {
2315 if (rssi_level == 1)
2316 ratr_bitmap &= 0x000f0000;
2317 else if (rssi_level == 2)
2318 ratr_bitmap &= 0x000ff000;
2319 else
2320 ratr_bitmap &= 0x000ff005;
2321 }
2322 } else {
2323 if (curtxbw_40mhz) {
2324 if (rssi_level == 1)
2325 ratr_bitmap &= 0x0f0f0000;
2326 else if (rssi_level == 2)
2327 ratr_bitmap &= 0x0f0ff000;
2328 else
2329 ratr_bitmap &= 0x0f0ff015;
2330 } else {
2331 if (rssi_level == 1)
2332 ratr_bitmap &= 0x0f0f0000;
2333 else if (rssi_level == 2)
2334 ratr_bitmap &= 0x0f0ff000;
2335 else
2336 ratr_bitmap &= 0x0f0ff005;
2337 }
2338 }
2339 }
2340 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2341 (!curtxbw_40mhz && curshortgi_20mhz)) {
2342 if (macid == 0)
2343 shortgi = true;
2344 else if (macid == 1)
2345 shortgi = false;
2346 }
2347 break;
2348 default:
2349 ratr_index = RATR_INX_WIRELESS_NGB;
2350 if (rtlphy->rf_type == RF_1T2R)
2351 ratr_bitmap &= 0x000ff0ff;
2352 else
2353 ratr_bitmap &= 0x0f0ff0ff;
2354 break;
2355 }
2356 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("ratr_bitmap :%x\n",
2357 ratr_bitmap));
2358 *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
2359 ratr_index << 28);
2360 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2361 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
2362 "ratr_val:%x, %x:%x:%x:%x:%x\n",
2363 ratr_index, ratr_bitmap,
2364 rate_mask[0], rate_mask[1],
2365 rate_mask[2], rate_mask[3],
2366 rate_mask[4]));
2367 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2368}
2369
2370void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2371{
2372 struct rtl_priv *rtlpriv = rtl_priv(hw);
2373 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2374 u16 sifs_timer;
2375
2376 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2377 (u8 *)&mac->slot_time);
2378 if (!mac->ht_enable)
2379 sifs_timer = 0x0a0a;
2380 else
2381 sifs_timer = 0x0e0e;
2382 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2383}
2384
2385bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2386{
2387 struct rtl_priv *rtlpriv = rtl_priv(hw);
2388 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2389 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2390 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2391 u8 u1tmp = 0;
2392 bool actuallyset = false;
2393 unsigned long flag = 0;
2394 /* to do - usb autosuspend */
2395 u8 usb_autosuspend = 0;
2396
2397 if (ppsc->swrf_processing)
2398 return false;
2399 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2400 if (ppsc->rfchange_inprogress) {
2401 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2402 return false;
2403 } else {
2404 ppsc->rfchange_inprogress = true;
2405 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2406 }
2407 cur_rfstate = ppsc->rfpwr_state;
2408 if (usb_autosuspend) {
2409 /* to do................... */
2410 } else {
2411 if (ppsc->pwrdown_mode) {
2412 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2413 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2414 ERFOFF : ERFON;
2415 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2416 ("pwrdown, 0x5c(BIT7)=%02x\n", u1tmp));
2417 } else {
2418 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2419 rtl_read_byte(rtlpriv,
2420 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2421 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2422 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2423 ERFON : ERFOFF;
2424 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2425 ("GPIO_IN=%02x\n", u1tmp));
2426 }
2427 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("N-SS RF =%x\n",
2428 e_rfpowerstate_toset));
2429 }
2430 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2431 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF - HW "
2432 "Radio ON, RF ON\n"));
2433 ppsc->hwradiooff = false;
2434 actuallyset = true;
2435 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2436 ERFOFF)) {
2437 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, ("GPIOChangeRF - HW"
2438 " Radio OFF\n"));
2439 ppsc->hwradiooff = true;
2440 actuallyset = true;
2441 } else {
2442 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD ,
2443 ("pHalData->bHwRadioOff and eRfPowerStateToSet do not"
2444 " match: pHalData->bHwRadioOff %x, eRfPowerStateToSet "
2445 "%x\n", ppsc->hwradiooff, e_rfpowerstate_toset));
2446 }
2447 if (actuallyset) {
2448 ppsc->hwradiooff = 1;
2449 if (e_rfpowerstate_toset == ERFON) {
2450 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2451 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2452 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2453 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2454 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2455 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2456 }
2457 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2458 ppsc->rfchange_inprogress = false;
2459 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2460 /* For power down module, we need to enable register block
2461 * contrl reg at 0x1c. Then enable power down control bit
2462 * of register 0x04 BIT4 and BIT15 as 1.
2463 */
2464 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2465 /* Enable register area 0x0-0xc. */
2466 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2467 if (IS_HARDWARE_TYPE_8723U(rtlhal)) {
2468 /*
2469 * We should configure HW PDn source for WiFi
2470 * ONLY, and then our HW will be set in
2471 * power-down mode if PDn source from all
2472 * functions are configured.
2473 */
2474 u1tmp = rtl_read_byte(rtlpriv,
2475 REG_MULTI_FUNC_CTRL);
2476 rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL,
2477 (u1tmp|WL_HWPDN_EN));
2478 } else {
2479 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2480 }
2481 }
2482 if (e_rfpowerstate_toset == ERFOFF) {
2483 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2484 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2485 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2486 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2487 }
2488 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2489 /* Enter D3 or ASPM after GPIO had been done. */
2490 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2491 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2492 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2493 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2494 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2495 ppsc->rfchange_inprogress = false;
2496 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2497 } else {
2498 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2499 ppsc->rfchange_inprogress = false;
2500 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2501 }
2502 *valid = 1;
2503 return !ppsc->hwradiooff;
2504}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
new file mode 100644
index 000000000000..62af555bb61c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
@@ -0,0 +1,116 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CU_HW_H__
31#define __RTL92CU_HW_H__
32
33#define H2C_RA_MASK 6
34
35#define LLT_POLLING_LLT_THRESHOLD 20
36#define LLT_POLLING_READY_TIMEOUT_COUNT 100
37#define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
38
39#define RX_PAGE_SIZE_REG_VALUE PBP_128
40/* Note: We will divide number of page equally for each queue
41 * other than public queue! */
42#define TX_TOTAL_PAGE_NUMBER 0xF8
43#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1)
44
45
46#define CHIP_B_PAGE_NUM_PUBQ 0xE7
47
48/* For Test Chip Setting
49 * (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER */
50#define CHIP_A_PAGE_NUM_PUBQ 0x7E
51
52
53/* For Chip A Setting */
54#define WMM_CHIP_A_TX_TOTAL_PAGE_NUMBER 0xF5
55#define WMM_CHIP_A_TX_PAGE_BOUNDARY \
56 (WMM_CHIP_A_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
57
58#define WMM_CHIP_A_PAGE_NUM_PUBQ 0xA3
59#define WMM_CHIP_A_PAGE_NUM_HPQ 0x29
60#define WMM_CHIP_A_PAGE_NUM_LPQ 0x29
61
62
63
64/* Note: For Chip B Setting ,modify later */
65#define WMM_CHIP_B_TX_TOTAL_PAGE_NUMBER 0xF5
66#define WMM_CHIP_B_TX_PAGE_BOUNDARY \
67 (WMM_CHIP_B_TX_TOTAL_PAGE_NUMBER + 1) /* F6 */
68
69#define WMM_CHIP_B_PAGE_NUM_PUBQ 0xB0
70#define WMM_CHIP_B_PAGE_NUM_HPQ 0x29
71#define WMM_CHIP_B_PAGE_NUM_LPQ 0x1C
72#define WMM_CHIP_B_PAGE_NUM_NPQ 0x1C
73
74#define BOARD_TYPE_NORMAL_MASK 0xE0
75#define BOARD_TYPE_TEST_MASK 0x0F
76
77/* should be renamed and moved to another file */
78enum _BOARD_TYPE_8192CUSB {
79 BOARD_USB_DONGLE = 0, /* USB dongle */
80 BOARD_USB_High_PA = 1, /* USB dongle - high power PA */
81 BOARD_MINICARD = 2, /* Minicard */
82 BOARD_USB_SOLO = 3, /* USB solo-Slim module */
83 BOARD_USB_COMBO = 4, /* USB Combo-Slim module */
84};
85
86#define IS_HIGHT_PA(boardtype) \
87 ((boardtype == BOARD_USB_High_PA) ? true : false)
88
89#define RTL92C_DRIVER_INFO_SIZE 4
90void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw);
91void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw);
92int rtl92cu_hw_init(struct ieee80211_hw *hw);
93void rtl92cu_card_disable(struct ieee80211_hw *hw);
94int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
95void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw);
96void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw);
97void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
98 u32 add_msr, u32 rm_msr);
99void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
100void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
101void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw);
102void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level);
103
104void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw);
105bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid);
106void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid);
107u8 _rtl92c_get_chnl_group(u8 chnl);
108int rtl92c_download_fw(struct ieee80211_hw *hw);
109void rtl92c_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode);
110void rtl92c_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool dl_finished);
111void rtl92c_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
112void rtl92c_fill_h2c_cmd(struct ieee80211_hw *hw,
113 u8 element_id, u32 cmd_len, u8 *p_cmdbuffer);
114bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw);
115
116#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/led.c b/drivers/net/wireless/rtlwifi/rtl8192cu/led.c
new file mode 100644
index 000000000000..332c74348a69
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/led.c
@@ -0,0 +1,142 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 *****************************************************************************/
27
28#include "../wifi.h"
29#include "../usb.h"
30#include "reg.h"
31#include "led.h"
32
33static void _rtl92cu_init_led(struct ieee80211_hw *hw,
34 struct rtl_led *pled, enum rtl_led_pin ledpin)
35{
36 pled->hw = hw;
37 pled->ledpin = ledpin;
38 pled->ledon = false;
39}
40
41static void _rtl92cu_deInit_led(struct rtl_led *pled)
42{
43}
44
45void rtl92cu_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled)
46{
47 u8 ledcfg;
48 struct rtl_priv *rtlpriv = rtl_priv(hw);
49
50 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
51 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
52 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
53 switch (pled->ledpin) {
54 case LED_PIN_GPIO0:
55 break;
56 case LED_PIN_LED0:
57 rtl_write_byte(rtlpriv,
58 REG_LEDCFG2, (ledcfg & 0xf0) | BIT(5) | BIT(6));
59 break;
60 case LED_PIN_LED1:
61 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg & 0x0f) | BIT(5));
62 break;
63 default:
64 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
65 ("switch case not process\n"));
66 break;
67 }
68 pled->ledon = true;
69}
70
71void rtl92cu_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled)
72{
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw);
75 u8 ledcfg;
76
77 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD,
78 ("LedAddr:%X ledpin=%d\n", REG_LEDCFG2, pled->ledpin));
79 ledcfg = rtl_read_byte(rtlpriv, REG_LEDCFG2);
80 switch (pled->ledpin) {
81 case LED_PIN_GPIO0:
82 break;
83 case LED_PIN_LED0:
84 ledcfg &= 0xf0;
85 if (usbpriv->ledctl.led_opendrain == true)
86 rtl_write_byte(rtlpriv, REG_LEDCFG2,
87 (ledcfg | BIT(1) | BIT(5) | BIT(6)));
88 else
89 rtl_write_byte(rtlpriv, REG_LEDCFG2,
90 (ledcfg | BIT(3) | BIT(5) | BIT(6)));
91 break;
92 case LED_PIN_LED1:
93 ledcfg &= 0x0f;
94 rtl_write_byte(rtlpriv, REG_LEDCFG2, (ledcfg | BIT(3)));
95 break;
96 default:
97 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
98 ("switch case not process\n"));
99 break;
100 }
101 pled->ledon = false;
102}
103
104void rtl92cu_init_sw_leds(struct ieee80211_hw *hw)
105{
106 struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw);
107 _rtl92cu_init_led(hw, &(usbpriv->ledctl.sw_led0), LED_PIN_LED0);
108 _rtl92cu_init_led(hw, &(usbpriv->ledctl.sw_led1), LED_PIN_LED1);
109}
110
111void rtl92cu_deinit_sw_leds(struct ieee80211_hw *hw)
112{
113 struct rtl_usb_priv *usbpriv = rtl_usbpriv(hw);
114 _rtl92cu_deInit_led(&(usbpriv->ledctl.sw_led0));
115 _rtl92cu_deInit_led(&(usbpriv->ledctl.sw_led1));
116}
117
118static void _rtl92cu_sw_led_control(struct ieee80211_hw *hw,
119 enum led_ctl_mode ledaction)
120{
121}
122
123void rtl92cu_led_control(struct ieee80211_hw *hw,
124 enum led_ctl_mode ledaction)
125{
126 struct rtl_priv *rtlpriv = rtl_priv(hw);
127 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
128
129 if ((ppsc->rfoff_reason > RF_CHANGE_BY_PS) &&
130 (ledaction == LED_CTL_TX ||
131 ledaction == LED_CTL_RX ||
132 ledaction == LED_CTL_SITE_SURVEY ||
133 ledaction == LED_CTL_LINK ||
134 ledaction == LED_CTL_NO_LINK ||
135 ledaction == LED_CTL_START_TO_LINK ||
136 ledaction == LED_CTL_POWER_ON)) {
137 return;
138 }
139 RT_TRACE(rtlpriv, COMP_LED, DBG_LOUD, ("ledaction %d,\n",
140 ledaction));
141 _rtl92cu_sw_led_control(hw, ledaction);
142}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/led.h b/drivers/net/wireless/rtlwifi/rtl8192cu/led.h
new file mode 100644
index 000000000000..decaee4d1eb1
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/led.h
@@ -0,0 +1,37 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 *****************************************************************************/
27
28#ifndef __RTL92CU_LED_H__
29#define __RTL92CU_LED_H__
30
31void rtl92cu_init_sw_leds(struct ieee80211_hw *hw);
32void rtl92cu_deinit_sw_leds(struct ieee80211_hw *hw);
33void rtl92cu_sw_led_on(struct ieee80211_hw *hw, struct rtl_led *pled);
34void rtl92cu_sw_led_off(struct ieee80211_hw *hw, struct rtl_led *pled);
35void rtl92cu_led_control(struct ieee80211_hw *hw, enum led_ctl_mode ledaction);
36
37#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
new file mode 100644
index 000000000000..f8514cba17b6
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
@@ -0,0 +1,1144 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28****************************************************************************/
29#include <linux/module.h>
30
31#include "../wifi.h"
32#include "../pci.h"
33#include "../usb.h"
34#include "../ps.h"
35#include "../cam.h"
36#include "reg.h"
37#include "def.h"
38#include "phy.h"
39#include "rf.h"
40#include "dm.h"
41#include "mac.h"
42#include "trx.h"
43
44/* macro to shorten lines */
45
46#define LINK_Q ui_link_quality
47#define RX_EVM rx_evm_percentage
48#define RX_SIGQ rx_mimo_signalquality
49
50
51void rtl92c_read_chip_version(struct ieee80211_hw *hw)
52{
53 struct rtl_priv *rtlpriv = rtl_priv(hw);
54 struct rtl_phy *rtlphy = &(rtlpriv->phy);
55 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
56 enum version_8192c chip_version = VERSION_UNKNOWN;
57 u32 value32;
58
59 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
60 if (value32 & TRP_VAUX_EN) {
61 chip_version = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C :
62 VERSION_TEST_CHIP_88C;
63 } else {
64 /* Normal mass production chip. */
65 chip_version = NORMAL_CHIP;
66 chip_version |= ((value32 & TYPE_ID) ? CHIP_92C : 0);
67 chip_version |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0);
68 /* RTL8723 with BT function. */
69 chip_version |= ((value32 & BT_FUNC) ? CHIP_8723 : 0);
70 if (IS_VENDOR_UMC(chip_version))
71 chip_version |= ((value32 & CHIP_VER_RTL_MASK) ?
72 CHIP_VENDOR_UMC_B_CUT : 0);
73 if (IS_92C_SERIAL(chip_version)) {
74 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
75 chip_version |= ((CHIP_BONDING_IDENTIFIER(value32) ==
76 CHIP_BONDING_92C_1T2R) ? CHIP_92C_1T2R : 0);
77 } else if (IS_8723_SERIES(chip_version)) {
78 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
79 chip_version |= ((value32 & RF_RL_ID) ?
80 CHIP_8723_DRV_REV : 0);
81 }
82 }
83 rtlhal->version = (enum version_8192c)chip_version;
84 switch (rtlhal->version) {
85 case VERSION_NORMAL_TSMC_CHIP_92C_1T2R:
86 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
87 ("Chip Version ID: VERSION_B_CHIP_92C.\n"));
88 break;
89 case VERSION_NORMAL_TSMC_CHIP_92C:
90 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
91 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_92C.\n"));
92 break;
93 case VERSION_NORMAL_TSMC_CHIP_88C:
94 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
95 ("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_88C.\n"));
96 break;
97 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
98 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
99 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP_i"
100 "92C_1T2R_A_CUT.\n"));
101 break;
102 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
103 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
104 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP_"
105 "92C_A_CUT.\n"));
106 break;
107 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
108 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
109 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP"
110 "_88C_A_CUT.\n"));
111 break;
112 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
113 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
114 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP"
115 "_92C_1T2R_B_CUT.\n"));
116 break;
117 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
118 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
119 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP"
120 "_92C_B_CUT.\n"));
121 break;
122 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
123 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
124 ("Chip Version ID: VERSION_NORMAL_UMC_CHIP"
125 "_88C_B_CUT.\n"));
126 break;
127 case VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT:
128 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
129 ("Chip Version ID: VERSION_NORMA_UMC_CHIP"
130 "_8723_1T1R_A_CUT.\n"));
131 break;
132 case VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT:
133 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
134 ("Chip Version ID: VERSION_NORMA_UMC_CHIP"
135 "_8723_1T1R_B_CUT.\n"));
136 break;
137 case VERSION_TEST_CHIP_92C:
138 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
139 ("Chip Version ID: VERSION_TEST_CHIP_92C.\n"));
140 break;
141 case VERSION_TEST_CHIP_88C:
142 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
143 ("Chip Version ID: VERSION_TEST_CHIP_88C.\n"));
144 break;
145 default:
146 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
147 ("Chip Version ID: ???????????????.\n"));
148 break;
149 }
150 if (IS_92C_SERIAL(rtlhal->version))
151 rtlphy->rf_type =
152 (IS_92C_1T2R(rtlhal->version)) ? RF_1T2R : RF_2T2R;
153 else
154 rtlphy->rf_type = RF_1T1R;
155 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
156 ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
157 "RF_2T2R" : "RF_1T1R"));
158 if (get_rf_type(rtlphy) == RF_1T1R)
159 rtlpriv->dm.rfpath_rxenable[0] = true;
160 else
161 rtlpriv->dm.rfpath_rxenable[0] =
162 rtlpriv->dm.rfpath_rxenable[1] = true;
163 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
164 rtlhal->version));
165}
166
167/**
168 * writeLLT - LLT table write access
169 * @io: io callback
170 * @address: LLT logical address.
171 * @data: LLT data content
172 *
173 * Realtek hardware access function.
174 *
175 */
176bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
177{
178 struct rtl_priv *rtlpriv = rtl_priv(hw);
179 bool status = true;
180 long count = 0;
181 u32 value = _LLT_INIT_ADDR(address) |
182 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
183
184 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
185 do {
186 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
187 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
188 break;
189 if (count > POLLING_LLT_THRESHOLD) {
190 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
191 ("Failed to polling write LLT done at"
192 " address %d! _LLT_OP_VALUE(%x)\n",
193 address, _LLT_OP_VALUE(value)));
194 status = false;
195 break;
196 }
197 } while (++count);
198 return status;
199}
200/**
201 * rtl92c_init_LLT_table - Init LLT table
202 * @io: io callback
203 * @boundary:
204 *
205 * Realtek hardware access function.
206 *
207 */
208bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary)
209{
210 bool rst = true;
211 u32 i;
212
213 for (i = 0; i < (boundary - 1); i++) {
214 rst = rtl92c_llt_write(hw, i , i + 1);
215 if (true != rst) {
216 printk(KERN_ERR "===> %s #1 fail\n", __func__);
217 return rst;
218 }
219 }
220 /* end of list */
221 rst = rtl92c_llt_write(hw, (boundary - 1), 0xFF);
222 if (true != rst) {
223 printk(KERN_ERR "===> %s #2 fail\n", __func__);
224 return rst;
225 }
226 /* Make the other pages as ring buffer
227 * This ring buffer is used as beacon buffer if we config this MAC
228 * as two MAC transfer.
229 * Otherwise used as local loopback buffer.
230 */
231 for (i = boundary; i < LLT_LAST_ENTRY_OF_TX_PKT_BUFFER; i++) {
232 rst = rtl92c_llt_write(hw, i, (i + 1));
233 if (true != rst) {
234 printk(KERN_ERR "===> %s #3 fail\n", __func__);
235 return rst;
236 }
237 }
238 /* Let last entry point to the start entry of ring buffer */
239 rst = rtl92c_llt_write(hw, LLT_LAST_ENTRY_OF_TX_PKT_BUFFER, boundary);
240 if (true != rst) {
241 printk(KERN_ERR "===> %s #4 fail\n", __func__);
242 return rst;
243 }
244 return rst;
245}
246void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
247 u8 *p_macaddr, bool is_group, u8 enc_algo,
248 bool is_wepkey, bool clear_all)
249{
250 struct rtl_priv *rtlpriv = rtl_priv(hw);
251 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
252 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
253 u8 *macaddr = p_macaddr;
254 u32 entry_id = 0;
255 bool is_pairwise = false;
256 static u8 cam_const_addr[4][6] = {
257 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
258 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
259 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
260 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
261 };
262 static u8 cam_const_broad[] = {
263 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
264 };
265
266 if (clear_all) {
267 u8 idx = 0;
268 u8 cam_offset = 0;
269 u8 clear_number = 5;
270
271 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
272 for (idx = 0; idx < clear_number; idx++) {
273 rtl_cam_mark_invalid(hw, cam_offset + idx);
274 rtl_cam_empty_entry(hw, cam_offset + idx);
275 if (idx < 5) {
276 memset(rtlpriv->sec.key_buf[idx], 0,
277 MAX_KEY_LEN);
278 rtlpriv->sec.key_len[idx] = 0;
279 }
280 }
281 } else {
282 switch (enc_algo) {
283 case WEP40_ENCRYPTION:
284 enc_algo = CAM_WEP40;
285 break;
286 case WEP104_ENCRYPTION:
287 enc_algo = CAM_WEP104;
288 break;
289 case TKIP_ENCRYPTION:
290 enc_algo = CAM_TKIP;
291 break;
292 case AESCCMP_ENCRYPTION:
293 enc_algo = CAM_AES;
294 break;
295 default:
296 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
297 ("iillegal switch case\n"));
298 enc_algo = CAM_TKIP;
299 break;
300 }
301 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
302 macaddr = cam_const_addr[key_index];
303 entry_id = key_index;
304 } else {
305 if (is_group) {
306 macaddr = cam_const_broad;
307 entry_id = key_index;
308 } else {
309 key_index = PAIRWISE_KEYIDX;
310 entry_id = CAM_PAIRWISE_KEY_POSITION;
311 is_pairwise = true;
312 }
313 }
314 if (rtlpriv->sec.key_len[key_index] == 0) {
315 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
316 ("delete one entry\n"));
317 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
318 } else {
319 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
320 ("The insert KEY length is %d\n",
321 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
322 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
323 ("The insert KEY is %x %x\n",
324 rtlpriv->sec.key_buf[0][0],
325 rtlpriv->sec.key_buf[0][1]));
326 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
327 ("add one entry\n"));
328 if (is_pairwise) {
329 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
330 "Pairwiase Key content :",
331 rtlpriv->sec.pairwise_key,
332 rtlpriv->sec.
333 key_len[PAIRWISE_KEYIDX]);
334 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
335 ("set Pairwiase key\n"));
336
337 rtl_cam_add_one_entry(hw, macaddr, key_index,
338 entry_id, enc_algo,
339 CAM_CONFIG_NO_USEDK,
340 rtlpriv->sec.
341 key_buf[key_index]);
342 } else {
343 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
344 ("set group key\n"));
345 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
346 rtl_cam_add_one_entry(hw,
347 rtlefuse->dev_addr,
348 PAIRWISE_KEYIDX,
349 CAM_PAIRWISE_KEY_POSITION,
350 enc_algo,
351 CAM_CONFIG_NO_USEDK,
352 rtlpriv->sec.key_buf
353 [entry_id]);
354 }
355 rtl_cam_add_one_entry(hw, macaddr, key_index,
356 entry_id, enc_algo,
357 CAM_CONFIG_NO_USEDK,
358 rtlpriv->sec.key_buf[entry_id]);
359 }
360 }
361 }
362}
363
364u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw)
365{
366 struct rtl_priv *rtlpriv = rtl_priv(hw);
367
368 return rtl_read_dword(rtlpriv, REG_TXDMA_STATUS);
369}
370
371void rtl92c_enable_interrupt(struct ieee80211_hw *hw)
372{
373 struct rtl_priv *rtlpriv = rtl_priv(hw);
374 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
375 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
376 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
377
378 if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
379 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] &
380 0xFFFFFFFF);
381 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] &
382 0xFFFFFFFF);
383 rtlpci->irq_enabled = true;
384 } else {
385 rtl_write_dword(rtlpriv, REG_HIMR, rtlusb->irq_mask[0] &
386 0xFFFFFFFF);
387 rtl_write_dword(rtlpriv, REG_HIMRE, rtlusb->irq_mask[1] &
388 0xFFFFFFFF);
389 rtlusb->irq_enabled = true;
390 }
391}
392
393void rtl92c_init_interrupt(struct ieee80211_hw *hw)
394{
395 rtl92c_enable_interrupt(hw);
396}
397
398void rtl92c_disable_interrupt(struct ieee80211_hw *hw)
399{
400 struct rtl_priv *rtlpriv = rtl_priv(hw);
401 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
402 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
403 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
404
405 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
406 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
407 if (IS_HARDWARE_TYPE_8192CE(rtlhal))
408 rtlpci->irq_enabled = false;
409 else if (IS_HARDWARE_TYPE_8192CU(rtlhal))
410 rtlusb->irq_enabled = false;
411}
412
413void rtl92c_set_qos(struct ieee80211_hw *hw, int aci)
414{
415 struct rtl_priv *rtlpriv = rtl_priv(hw);
416 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
417 u32 u4b_ac_param;
418
419 rtl92c_dm_init_edca_turbo(hw);
420 u4b_ac_param = (u32) mac->ac[aci].aifs;
421 u4b_ac_param |=
422 ((u32) le16_to_cpu(mac->ac[aci].cw_min) & 0xF) <<
423 AC_PARAM_ECW_MIN_OFFSET;
424 u4b_ac_param |=
425 ((u32) le16_to_cpu(mac->ac[aci].cw_max) & 0xF) <<
426 AC_PARAM_ECW_MAX_OFFSET;
427 u4b_ac_param |= (u32) le16_to_cpu(mac->ac[aci].tx_op) <<
428 AC_PARAM_TXOP_OFFSET;
429 RT_TRACE(rtlpriv, COMP_QOS, DBG_LOUD,
430 ("queue:%x, ac_param:%x\n", aci, u4b_ac_param));
431 switch (aci) {
432 case AC1_BK:
433 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, u4b_ac_param);
434 break;
435 case AC0_BE:
436 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param);
437 break;
438 case AC2_VI:
439 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, u4b_ac_param);
440 break;
441 case AC3_VO:
442 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, u4b_ac_param);
443 break;
444 default:
445 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
446 break;
447 }
448}
449
450/*-------------------------------------------------------------------------
451 * HW MAC Address
452 *-------------------------------------------------------------------------*/
453void rtl92c_set_mac_addr(struct ieee80211_hw *hw, const u8 *addr)
454{
455 u32 i;
456 struct rtl_priv *rtlpriv = rtl_priv(hw);
457
458 for (i = 0 ; i < ETH_ALEN ; i++)
459 rtl_write_byte(rtlpriv, (REG_MACID + i), *(addr+i));
460
461 RT_TRACE(rtlpriv, COMP_CMD, DBG_DMESG, ("MAC Address: %02X-%02X-%02X-"
462 "%02X-%02X-%02X\n",
463 rtl_read_byte(rtlpriv, REG_MACID),
464 rtl_read_byte(rtlpriv, REG_MACID+1),
465 rtl_read_byte(rtlpriv, REG_MACID+2),
466 rtl_read_byte(rtlpriv, REG_MACID+3),
467 rtl_read_byte(rtlpriv, REG_MACID+4),
468 rtl_read_byte(rtlpriv, REG_MACID+5)));
469}
470
471void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size)
472{
473 struct rtl_priv *rtlpriv = rtl_priv(hw);
474 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, size);
475}
476
477int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
478{
479 u8 value;
480 struct rtl_priv *rtlpriv = rtl_priv(hw);
481
482 switch (type) {
483 case NL80211_IFTYPE_UNSPECIFIED:
484 value = NT_NO_LINK;
485 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
486 ("Set Network type to NO LINK!\n"));
487 break;
488 case NL80211_IFTYPE_ADHOC:
489 value = NT_LINK_AD_HOC;
490 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
491 ("Set Network type to Ad Hoc!\n"));
492 break;
493 case NL80211_IFTYPE_STATION:
494 value = NT_LINK_AP;
495 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
496 ("Set Network type to STA!\n"));
497 break;
498 case NL80211_IFTYPE_AP:
499 value = NT_AS_AP;
500 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
501 ("Set Network type to AP!\n"));
502 break;
503 default:
504 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
505 ("Network type %d not support!\n", type));
506 return -EOPNOTSUPP;
507 }
508 rtl_write_byte(rtlpriv, (REG_CR + 2), value);
509 return 0;
510}
511
512void rtl92c_init_network_type(struct ieee80211_hw *hw)
513{
514 rtl92c_set_network_type(hw, NL80211_IFTYPE_UNSPECIFIED);
515}
516
517void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw)
518{
519 u16 value16;
520 u32 value32;
521 struct rtl_priv *rtlpriv = rtl_priv(hw);
522
523 /* Response Rate Set */
524 value32 = rtl_read_dword(rtlpriv, REG_RRSR);
525 value32 &= ~RATE_BITMAP_ALL;
526 value32 |= RATE_RRSR_CCK_ONLY_1M;
527 rtl_write_dword(rtlpriv, REG_RRSR, value32);
528 /* SIFS (used in NAV) */
529 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
530 rtl_write_word(rtlpriv, REG_SPEC_SIFS, value16);
531 /* Retry Limit */
532 value16 = _LRL(0x30) | _SRL(0x30);
533 rtl_write_dword(rtlpriv, REG_RL, value16);
534}
535
536void rtl92c_init_rate_fallback(struct ieee80211_hw *hw)
537{
538 struct rtl_priv *rtlpriv = rtl_priv(hw);
539
540 /* Set Data Auto Rate Fallback Retry Count register. */
541 rtl_write_dword(rtlpriv, REG_DARFRC, 0x00000000);
542 rtl_write_dword(rtlpriv, REG_DARFRC+4, 0x10080404);
543 rtl_write_dword(rtlpriv, REG_RARFRC, 0x04030201);
544 rtl_write_dword(rtlpriv, REG_RARFRC+4, 0x08070605);
545}
546
547static void rtl92c_set_cck_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
548 u8 ctx_sifs)
549{
550 struct rtl_priv *rtlpriv = rtl_priv(hw);
551
552 rtl_write_byte(rtlpriv, REG_SIFS_CCK, trx_sifs);
553 rtl_write_byte(rtlpriv, (REG_SIFS_CCK + 1), ctx_sifs);
554}
555
556static void rtl92c_set_ofdm_sifs(struct ieee80211_hw *hw, u8 trx_sifs,
557 u8 ctx_sifs)
558{
559 struct rtl_priv *rtlpriv = rtl_priv(hw);
560
561 rtl_write_byte(rtlpriv, REG_SIFS_OFDM, trx_sifs);
562 rtl_write_byte(rtlpriv, (REG_SIFS_OFDM + 1), ctx_sifs);
563}
564
565void rtl92c_init_edca_param(struct ieee80211_hw *hw,
566 u16 queue, u16 txop, u8 cw_min, u8 cw_max, u8 aifs)
567{
568 /* sequence: VO, VI, BE, BK ==> the same as 92C hardware design.
569 * referenc : enum nl80211_txq_q or ieee80211_set_wmm_default function.
570 */
571 u32 value;
572 struct rtl_priv *rtlpriv = rtl_priv(hw);
573
574 value = (u32)aifs;
575 value |= ((u32)cw_min & 0xF) << 8;
576 value |= ((u32)cw_max & 0xF) << 12;
577 value |= (u32)txop << 16;
578 /* 92C hardware register sequence is the same as queue number. */
579 rtl_write_dword(rtlpriv, (REG_EDCA_VO_PARAM + (queue * 4)), value);
580}
581
582void rtl92c_init_edca(struct ieee80211_hw *hw)
583{
584 u16 value16;
585 struct rtl_priv *rtlpriv = rtl_priv(hw);
586
587 /* disable EDCCA count down, to reduce collison and retry */
588 value16 = rtl_read_word(rtlpriv, REG_RD_CTRL);
589 value16 |= DIS_EDCA_CNT_DWN;
590 rtl_write_word(rtlpriv, REG_RD_CTRL, value16);
591 /* Update SIFS timing. ??????????
592 * pHalData->SifsTime = 0x0e0e0a0a; */
593 rtl92c_set_cck_sifs(hw, 0xa, 0xa);
594 rtl92c_set_ofdm_sifs(hw, 0xe, 0xe);
595 /* Set CCK/OFDM SIFS to be 10us. */
596 rtl_write_word(rtlpriv, REG_SIFS_CCK, 0x0a0a);
597 rtl_write_word(rtlpriv, REG_SIFS_OFDM, 0x1010);
598 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0204);
599 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x014004);
600 /* TXOP */
601 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, 0x005EA42B);
602 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0x0000A44F);
603 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x005EA324);
604 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x002FA226);
605 /* PIFS */
606 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
607 /* AGGR BREAK TIME Register */
608 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
609 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
610 rtl_write_byte(rtlpriv, REG_BCNDMATIM, 0x02);
611 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x02);
612}
613
614void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw)
615{
616 struct rtl_priv *rtlpriv = rtl_priv(hw);
617
618 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x99997631);
619 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
620 /* init AMPDU aggregation number, tuning for Tx's TP, */
621 rtl_write_word(rtlpriv, 0x4CA, 0x0708);
622}
623
624void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw, bool infra_mode)
625{
626 struct rtl_priv *rtlpriv = rtl_priv(hw);
627
628 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xFF);
629}
630
631void rtl92c_init_rdg_setting(struct ieee80211_hw *hw)
632{
633 struct rtl_priv *rtlpriv = rtl_priv(hw);
634
635 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xFF);
636 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
637 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
638}
639
640void rtl92c_init_retry_function(struct ieee80211_hw *hw)
641{
642 u8 value8;
643 struct rtl_priv *rtlpriv = rtl_priv(hw);
644
645 value8 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL);
646 value8 |= EN_AMPDU_RTY_NEW;
647 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL, value8);
648 /* Set ACK timeout */
649 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
650}
651
652void rtl92c_init_beacon_parameters(struct ieee80211_hw *hw,
653 enum version_8192c version)
654{
655 struct rtl_priv *rtlpriv = rtl_priv(hw);
656 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
657
658 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);/* ms */
659 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);/*ms*/
660 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
661 if (IS_NORMAL_CHIP(rtlhal->version))
662 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
663 else
664 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
665}
666
667void rtl92c_disable_fast_edca(struct ieee80211_hw *hw)
668{
669 struct rtl_priv *rtlpriv = rtl_priv(hw);
670
671 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0);
672}
673
674void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T)
675{
676 struct rtl_priv *rtlpriv = rtl_priv(hw);
677 u8 value = is2T ? MAX_MSS_DENSITY_2T : MAX_MSS_DENSITY_1T;
678
679 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, value);
680}
681
682u16 rtl92c_get_mgt_filter(struct ieee80211_hw *hw)
683{
684 struct rtl_priv *rtlpriv = rtl_priv(hw);
685
686 return rtl_read_word(rtlpriv, REG_RXFLTMAP0);
687}
688
689void rtl92c_set_mgt_filter(struct ieee80211_hw *hw, u16 filter)
690{
691 struct rtl_priv *rtlpriv = rtl_priv(hw);
692
693 rtl_write_word(rtlpriv, REG_RXFLTMAP0, filter);
694}
695
696u16 rtl92c_get_ctrl_filter(struct ieee80211_hw *hw)
697{
698 struct rtl_priv *rtlpriv = rtl_priv(hw);
699
700 return rtl_read_word(rtlpriv, REG_RXFLTMAP1);
701}
702
703void rtl92c_set_ctrl_filter(struct ieee80211_hw *hw, u16 filter)
704{
705 struct rtl_priv *rtlpriv = rtl_priv(hw);
706
707 rtl_write_word(rtlpriv, REG_RXFLTMAP1, filter);
708}
709
710u16 rtl92c_get_data_filter(struct ieee80211_hw *hw)
711{
712 struct rtl_priv *rtlpriv = rtl_priv(hw);
713
714 return rtl_read_word(rtlpriv, REG_RXFLTMAP2);
715}
716
717void rtl92c_set_data_filter(struct ieee80211_hw *hw, u16 filter)
718{
719 struct rtl_priv *rtlpriv = rtl_priv(hw);
720
721 rtl_write_word(rtlpriv, REG_RXFLTMAP2, filter);
722}
723/*==============================================================*/
724
725static u8 _rtl92c_query_rxpwrpercentage(char antpower)
726{
727 if ((antpower <= -100) || (antpower >= 20))
728 return 0;
729 else if (antpower >= 0)
730 return 100;
731 else
732 return 100 + antpower;
733}
734
735static u8 _rtl92c_evm_db_to_percentage(char value)
736{
737 char ret_val;
738
739 ret_val = value;
740 if (ret_val >= 0)
741 ret_val = 0;
742 if (ret_val <= -33)
743 ret_val = -33;
744 ret_val = 0 - ret_val;
745 ret_val *= 3;
746 if (ret_val == 99)
747 ret_val = 100;
748 return ret_val;
749}
750
751static long _rtl92c_translate_todbm(struct ieee80211_hw *hw,
752 u8 signal_strength_index)
753{
754 long signal_power;
755
756 signal_power = (long)((signal_strength_index + 1) >> 1);
757 signal_power -= 95;
758 return signal_power;
759}
760
761static long _rtl92c_signal_scale_mapping(struct ieee80211_hw *hw,
762 long currsig)
763{
764 long retsig;
765
766 if (currsig >= 61 && currsig <= 100)
767 retsig = 90 + ((currsig - 60) / 4);
768 else if (currsig >= 41 && currsig <= 60)
769 retsig = 78 + ((currsig - 40) / 2);
770 else if (currsig >= 31 && currsig <= 40)
771 retsig = 66 + (currsig - 30);
772 else if (currsig >= 21 && currsig <= 30)
773 retsig = 54 + (currsig - 20);
774 else if (currsig >= 5 && currsig <= 20)
775 retsig = 42 + (((currsig - 5) * 2) / 3);
776 else if (currsig == 4)
777 retsig = 36;
778 else if (currsig == 3)
779 retsig = 27;
780 else if (currsig == 2)
781 retsig = 18;
782 else if (currsig == 1)
783 retsig = 9;
784 else
785 retsig = currsig;
786 return retsig;
787}
788
789static void _rtl92c_query_rxphystatus(struct ieee80211_hw *hw,
790 struct rtl_stats *pstats,
791 struct rx_desc_92c *pdesc,
792 struct rx_fwinfo_92c *p_drvinfo,
793 bool packet_match_bssid,
794 bool packet_toself,
795 bool packet_beacon)
796{
797 struct rtl_priv *rtlpriv = rtl_priv(hw);
798 struct rtl_phy *rtlphy = &(rtlpriv->phy);
799 struct phy_sts_cck_8192s_t *cck_buf;
800 s8 rx_pwr_all = 0, rx_pwr[4];
801 u8 rf_rx_num = 0, evm, pwdb_all;
802 u8 i, max_spatial_stream;
803 u32 rssi, total_rssi = 0;
804 bool in_powersavemode = false;
805 bool is_cck_rate;
806
807 is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc);
808 pstats->packet_matchbssid = packet_match_bssid;
809 pstats->packet_toself = packet_toself;
810 pstats->is_cck = is_cck_rate;
811 pstats->packet_beacon = packet_beacon;
812 pstats->is_cck = is_cck_rate;
813 pstats->RX_SIGQ[0] = -1;
814 pstats->RX_SIGQ[1] = -1;
815 if (is_cck_rate) {
816 u8 report, cck_highpwr;
817 cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
818 if (!in_powersavemode)
819 cck_highpwr = rtlphy->cck_high_power;
820 else
821 cck_highpwr = false;
822 if (!cck_highpwr) {
823 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
824 report = cck_buf->cck_agc_rpt & 0xc0;
825 report = report >> 6;
826 switch (report) {
827 case 0x3:
828 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
829 break;
830 case 0x2:
831 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
832 break;
833 case 0x1:
834 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
835 break;
836 case 0x0:
837 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
838 break;
839 }
840 } else {
841 u8 cck_agc_rpt = cck_buf->cck_agc_rpt;
842 report = p_drvinfo->cfosho[0] & 0x60;
843 report = report >> 5;
844 switch (report) {
845 case 0x3:
846 rx_pwr_all = -46 - ((cck_agc_rpt & 0x1f) << 1);
847 break;
848 case 0x2:
849 rx_pwr_all = -26 - ((cck_agc_rpt & 0x1f) << 1);
850 break;
851 case 0x1:
852 rx_pwr_all = -12 - ((cck_agc_rpt & 0x1f) << 1);
853 break;
854 case 0x0:
855 rx_pwr_all = 16 - ((cck_agc_rpt & 0x1f) << 1);
856 break;
857 }
858 }
859 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
860 pstats->rx_pwdb_all = pwdb_all;
861 pstats->recvsignalpower = rx_pwr_all;
862 if (packet_match_bssid) {
863 u8 sq;
864 if (pstats->rx_pwdb_all > 40)
865 sq = 100;
866 else {
867 sq = cck_buf->sq_rpt;
868 if (sq > 64)
869 sq = 0;
870 else if (sq < 20)
871 sq = 100;
872 else
873 sq = ((64 - sq) * 100) / 44;
874 }
875 pstats->signalquality = sq;
876 pstats->RX_SIGQ[0] = sq;
877 pstats->RX_SIGQ[1] = -1;
878 }
879 } else {
880 rtlpriv->dm.rfpath_rxenable[0] =
881 rtlpriv->dm.rfpath_rxenable[1] = true;
882 for (i = RF90_PATH_A; i < RF90_PATH_MAX; i++) {
883 if (rtlpriv->dm.rfpath_rxenable[i])
884 rf_rx_num++;
885 rx_pwr[i] =
886 ((p_drvinfo->gain_trsw[i] & 0x3f) * 2) - 110;
887 rssi = _rtl92c_query_rxpwrpercentage(rx_pwr[i]);
888 total_rssi += rssi;
889 rtlpriv->stats.rx_snr_db[i] =
890 (long)(p_drvinfo->rxsnr[i] / 2);
891
892 if (packet_match_bssid)
893 pstats->rx_mimo_signalstrength[i] = (u8) rssi;
894 }
895 rx_pwr_all = ((p_drvinfo->pwdb_all >> 1) & 0x7f) - 110;
896 pwdb_all = _rtl92c_query_rxpwrpercentage(rx_pwr_all);
897 pstats->rx_pwdb_all = pwdb_all;
898 pstats->rxpower = rx_pwr_all;
899 pstats->recvsignalpower = rx_pwr_all;
900 if (GET_RX_DESC_RX_MCS(pdesc) &&
901 GET_RX_DESC_RX_MCS(pdesc) >= DESC92C_RATEMCS8 &&
902 GET_RX_DESC_RX_MCS(pdesc) <= DESC92C_RATEMCS15)
903 max_spatial_stream = 2;
904 else
905 max_spatial_stream = 1;
906 for (i = 0; i < max_spatial_stream; i++) {
907 evm = _rtl92c_evm_db_to_percentage(p_drvinfo->rxevm[i]);
908 if (packet_match_bssid) {
909 if (i == 0)
910 pstats->signalquality =
911 (u8) (evm & 0xff);
912 pstats->RX_SIGQ[i] =
913 (u8) (evm & 0xff);
914 }
915 }
916 }
917 if (is_cck_rate)
918 pstats->signalstrength =
919 (u8) (_rtl92c_signal_scale_mapping(hw, pwdb_all));
920 else if (rf_rx_num != 0)
921 pstats->signalstrength =
922 (u8) (_rtl92c_signal_scale_mapping
923 (hw, total_rssi /= rf_rx_num));
924}
925
926static void _rtl92c_process_ui_rssi(struct ieee80211_hw *hw,
927 struct rtl_stats *pstats)
928{
929 struct rtl_priv *rtlpriv = rtl_priv(hw);
930 struct rtl_phy *rtlphy = &(rtlpriv->phy);
931 u8 rfpath;
932 u32 last_rssi, tmpval;
933
934 if (pstats->packet_toself || pstats->packet_beacon) {
935 rtlpriv->stats.rssi_calculate_cnt++;
936 if (rtlpriv->stats.ui_rssi.total_num++ >=
937 PHY_RSSI_SLID_WIN_MAX) {
938 rtlpriv->stats.ui_rssi.total_num =
939 PHY_RSSI_SLID_WIN_MAX;
940 last_rssi =
941 rtlpriv->stats.ui_rssi.elements[rtlpriv->
942 stats.ui_rssi.index];
943 rtlpriv->stats.ui_rssi.total_val -= last_rssi;
944 }
945 rtlpriv->stats.ui_rssi.total_val += pstats->signalstrength;
946 rtlpriv->stats.ui_rssi.elements[rtlpriv->stats.ui_rssi.
947 index++] = pstats->signalstrength;
948 if (rtlpriv->stats.ui_rssi.index >= PHY_RSSI_SLID_WIN_MAX)
949 rtlpriv->stats.ui_rssi.index = 0;
950 tmpval = rtlpriv->stats.ui_rssi.total_val /
951 rtlpriv->stats.ui_rssi.total_num;
952 rtlpriv->stats.signal_strength =
953 _rtl92c_translate_todbm(hw, (u8) tmpval);
954 pstats->rssi = rtlpriv->stats.signal_strength;
955 }
956 if (!pstats->is_cck && pstats->packet_toself) {
957 for (rfpath = RF90_PATH_A; rfpath < rtlphy->num_total_rfpath;
958 rfpath++) {
959 if (!rtl8192_phy_check_is_legal_rfpath(hw, rfpath))
960 continue;
961 if (rtlpriv->stats.rx_rssi_percentage[rfpath] == 0) {
962 rtlpriv->stats.rx_rssi_percentage[rfpath] =
963 pstats->rx_mimo_signalstrength[rfpath];
964 }
965 if (pstats->rx_mimo_signalstrength[rfpath] >
966 rtlpriv->stats.rx_rssi_percentage[rfpath]) {
967 rtlpriv->stats.rx_rssi_percentage[rfpath] =
968 ((rtlpriv->stats.
969 rx_rssi_percentage[rfpath] *
970 (RX_SMOOTH_FACTOR - 1)) +
971 (pstats->rx_mimo_signalstrength[rfpath])) /
972 (RX_SMOOTH_FACTOR);
973
974 rtlpriv->stats.rx_rssi_percentage[rfpath] =
975 rtlpriv->stats.rx_rssi_percentage[rfpath] +
976 1;
977 } else {
978 rtlpriv->stats.rx_rssi_percentage[rfpath] =
979 ((rtlpriv->stats.
980 rx_rssi_percentage[rfpath] *
981 (RX_SMOOTH_FACTOR - 1)) +
982 (pstats->rx_mimo_signalstrength[rfpath])) /
983 (RX_SMOOTH_FACTOR);
984 }
985 }
986 }
987}
988
989static void _rtl92c_update_rxsignalstatistics(struct ieee80211_hw *hw,
990 struct rtl_stats *pstats)
991{
992 struct rtl_priv *rtlpriv = rtl_priv(hw);
993 int weighting = 0;
994
995 if (rtlpriv->stats.recv_signal_power == 0)
996 rtlpriv->stats.recv_signal_power = pstats->recvsignalpower;
997 if (pstats->recvsignalpower > rtlpriv->stats.recv_signal_power)
998 weighting = 5;
999 else if (pstats->recvsignalpower < rtlpriv->stats.recv_signal_power)
1000 weighting = (-5);
1001 rtlpriv->stats.recv_signal_power =
1002 (rtlpriv->stats.recv_signal_power * 5 +
1003 pstats->recvsignalpower + weighting) / 6;
1004}
1005
1006static void _rtl92c_process_pwdb(struct ieee80211_hw *hw,
1007 struct rtl_stats *pstats)
1008{
1009 struct rtl_priv *rtlpriv = rtl_priv(hw);
1010 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1011 long undecorated_smoothed_pwdb = 0;
1012
1013 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
1014 return;
1015 } else {
1016 undecorated_smoothed_pwdb =
1017 rtlpriv->dm.undecorated_smoothed_pwdb;
1018 }
1019 if (pstats->packet_toself || pstats->packet_beacon) {
1020 if (undecorated_smoothed_pwdb < 0)
1021 undecorated_smoothed_pwdb = pstats->rx_pwdb_all;
1022 if (pstats->rx_pwdb_all > (u32) undecorated_smoothed_pwdb) {
1023 undecorated_smoothed_pwdb =
1024 (((undecorated_smoothed_pwdb) *
1025 (RX_SMOOTH_FACTOR - 1)) +
1026 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
1027 undecorated_smoothed_pwdb = undecorated_smoothed_pwdb
1028 + 1;
1029 } else {
1030 undecorated_smoothed_pwdb =
1031 (((undecorated_smoothed_pwdb) *
1032 (RX_SMOOTH_FACTOR - 1)) +
1033 (pstats->rx_pwdb_all)) / (RX_SMOOTH_FACTOR);
1034 }
1035 rtlpriv->dm.undecorated_smoothed_pwdb =
1036 undecorated_smoothed_pwdb;
1037 _rtl92c_update_rxsignalstatistics(hw, pstats);
1038 }
1039}
1040
1041static void _rtl92c_process_LINK_Q(struct ieee80211_hw *hw,
1042 struct rtl_stats *pstats)
1043{
1044 struct rtl_priv *rtlpriv = rtl_priv(hw);
1045 u32 last_evm = 0, n_stream, tmpval;
1046
1047 if (pstats->signalquality != 0) {
1048 if (pstats->packet_toself || pstats->packet_beacon) {
1049 if (rtlpriv->stats.LINK_Q.total_num++ >=
1050 PHY_LINKQUALITY_SLID_WIN_MAX) {
1051 rtlpriv->stats.LINK_Q.total_num =
1052 PHY_LINKQUALITY_SLID_WIN_MAX;
1053 last_evm =
1054 rtlpriv->stats.LINK_Q.elements
1055 [rtlpriv->stats.LINK_Q.index];
1056 rtlpriv->stats.LINK_Q.total_val -=
1057 last_evm;
1058 }
1059 rtlpriv->stats.LINK_Q.total_val +=
1060 pstats->signalquality;
1061 rtlpriv->stats.LINK_Q.elements
1062 [rtlpriv->stats.LINK_Q.index++] =
1063 pstats->signalquality;
1064 if (rtlpriv->stats.LINK_Q.index >=
1065 PHY_LINKQUALITY_SLID_WIN_MAX)
1066 rtlpriv->stats.LINK_Q.index = 0;
1067 tmpval = rtlpriv->stats.LINK_Q.total_val /
1068 rtlpriv->stats.LINK_Q.total_num;
1069 rtlpriv->stats.signal_quality = tmpval;
1070 rtlpriv->stats.last_sigstrength_inpercent = tmpval;
1071 for (n_stream = 0; n_stream < 2;
1072 n_stream++) {
1073 if (pstats->RX_SIGQ[n_stream] != -1) {
1074 if (!rtlpriv->stats.RX_EVM[n_stream]) {
1075 rtlpriv->stats.RX_EVM[n_stream]
1076 = pstats->RX_SIGQ[n_stream];
1077 }
1078 rtlpriv->stats.RX_EVM[n_stream] =
1079 ((rtlpriv->stats.RX_EVM
1080 [n_stream] *
1081 (RX_SMOOTH_FACTOR - 1)) +
1082 (pstats->RX_SIGQ
1083 [n_stream] * 1)) /
1084 (RX_SMOOTH_FACTOR);
1085 }
1086 }
1087 }
1088 } else {
1089 ;
1090 }
1091}
1092
1093static void _rtl92c_process_phyinfo(struct ieee80211_hw *hw,
1094 u8 *buffer,
1095 struct rtl_stats *pcurrent_stats)
1096{
1097 if (!pcurrent_stats->packet_matchbssid &&
1098 !pcurrent_stats->packet_beacon)
1099 return;
1100 _rtl92c_process_ui_rssi(hw, pcurrent_stats);
1101 _rtl92c_process_pwdb(hw, pcurrent_stats);
1102 _rtl92c_process_LINK_Q(hw, pcurrent_stats);
1103}
1104
1105void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
1106 struct sk_buff *skb,
1107 struct rtl_stats *pstats,
1108 struct rx_desc_92c *pdesc,
1109 struct rx_fwinfo_92c *p_drvinfo)
1110{
1111 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1112 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1113 struct ieee80211_hdr *hdr;
1114 u8 *tmp_buf;
1115 u8 *praddr;
1116 u8 *psaddr;
1117 __le16 fc;
1118 u16 type, cpu_fc;
1119 bool packet_matchbssid, packet_toself, packet_beacon;
1120
1121 tmp_buf = skb->data + pstats->rx_drvinfo_size + pstats->rx_bufshift;
1122 hdr = (struct ieee80211_hdr *)tmp_buf;
1123 fc = hdr->frame_control;
1124 cpu_fc = le16_to_cpu(fc);
1125 type = WLAN_FC_GET_TYPE(fc);
1126 praddr = hdr->addr1;
1127 psaddr = hdr->addr2;
1128 packet_matchbssid =
1129 ((IEEE80211_FTYPE_CTL != type) &&
1130 (!compare_ether_addr(mac->bssid,
1131 (cpu_fc & IEEE80211_FCTL_TODS) ?
1132 hdr->addr1 : (cpu_fc & IEEE80211_FCTL_FROMDS) ?
1133 hdr->addr2 : hdr->addr3)) &&
1134 (!pstats->hwerror) && (!pstats->crc) && (!pstats->icv));
1135
1136 packet_toself = packet_matchbssid &&
1137 (!compare_ether_addr(praddr, rtlefuse->dev_addr));
1138 if (ieee80211_is_beacon(fc))
1139 packet_beacon = true;
1140 _rtl92c_query_rxphystatus(hw, pstats, pdesc, p_drvinfo,
1141 packet_matchbssid, packet_toself,
1142 packet_beacon);
1143 _rtl92c_process_phyinfo(hw, tmp_buf, pstats);
1144}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.h b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.h
new file mode 100644
index 000000000000..298fdb724aa5
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.h
@@ -0,0 +1,180 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92C_MAC_H__
31#define __RTL92C_MAC_H__
32
33#define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
34#define DRIVER_EARLY_INT_TIME 0x05
35#define BCN_DMA_ATIME_INT_TIME 0x02
36
37void rtl92c_read_chip_version(struct ieee80211_hw *hw);
38bool rtl92c_llt_write(struct ieee80211_hw *hw, u32 address, u32 data);
39bool rtl92c_init_llt_table(struct ieee80211_hw *hw, u32 boundary);
40void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
41 u8 *p_macaddr, bool is_group, u8 enc_algo,
42 bool is_wepkey, bool clear_all);
43void rtl92c_enable_interrupt(struct ieee80211_hw *hw);
44void rtl92c_disable_interrupt(struct ieee80211_hw *hw);
45void rtl92c_set_qos(struct ieee80211_hw *hw, int aci);
46
47
48/*---------------------------------------------------------------
49 * Hardware init functions
50 *---------------------------------------------------------------*/
51void rtl92c_set_mac_addr(struct ieee80211_hw *hw, const u8 *addr);
52void rtl92c_init_interrupt(struct ieee80211_hw *hw);
53void rtl92c_init_driver_info_size(struct ieee80211_hw *hw, u8 size);
54
55int rtl92c_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type);
56void rtl92c_init_network_type(struct ieee80211_hw *hw);
57void rtl92c_init_adaptive_ctrl(struct ieee80211_hw *hw);
58void rtl92c_init_rate_fallback(struct ieee80211_hw *hw);
59
60void rtl92c_init_edca_param(struct ieee80211_hw *hw,
61 u16 queue,
62 u16 txop,
63 u8 ecwmax,
64 u8 ecwmin,
65 u8 aifs);
66
67void rtl92c_init_edca(struct ieee80211_hw *hw);
68void rtl92c_init_ampdu_aggregation(struct ieee80211_hw *hw);
69void rtl92c_init_beacon_max_error(struct ieee80211_hw *hw, bool infra_mode);
70void rtl92c_init_rdg_setting(struct ieee80211_hw *hw);
71void rtl92c_init_retry_function(struct ieee80211_hw *hw);
72
73void rtl92c_init_beacon_parameters(struct ieee80211_hw *hw,
74 enum version_8192c version);
75
76void rtl92c_disable_fast_edca(struct ieee80211_hw *hw);
77void rtl92c_set_min_space(struct ieee80211_hw *hw, bool is2T);
78
79/* For filter */
80u16 rtl92c_get_mgt_filter(struct ieee80211_hw *hw);
81void rtl92c_set_mgt_filter(struct ieee80211_hw *hw, u16 filter);
82u16 rtl92c_get_ctrl_filter(struct ieee80211_hw *hw);
83void rtl92c_set_ctrl_filter(struct ieee80211_hw *hw, u16 filter);
84u16 rtl92c_get_data_filter(struct ieee80211_hw *hw);
85void rtl92c_set_data_filter(struct ieee80211_hw *hw, u16 filter);
86
87
88u32 rtl92c_get_txdma_status(struct ieee80211_hw *hw);
89
90#define RX_HAL_IS_CCK_RATE(_pdesc)\
91 (GET_RX_DESC_RX_MCS(_pdesc) == DESC92C_RATE1M ||\
92 GET_RX_DESC_RX_MCS(_pdesc) == DESC92C_RATE2M ||\
93 GET_RX_DESC_RX_MCS(_pdesc) == DESC92C_RATE5_5M ||\
94 GET_RX_DESC_RX_MCS(_pdesc) == DESC92C_RATE11M)
95
96struct rx_fwinfo_92c {
97 u8 gain_trsw[4];
98 u8 pwdb_all;
99 u8 cfosho[4];
100 u8 cfotail[4];
101 char rxevm[2];
102 char rxsnr[4];
103 u8 pdsnr[2];
104 u8 csi_current[2];
105 u8 csi_target[2];
106 u8 sigevm;
107 u8 max_ex_pwr;
108 u8 ex_intf_flag:1;
109 u8 sgi_en:1;
110 u8 rxsc:2;
111 u8 reserve:4;
112} __packed;
113
114struct rx_desc_92c {
115 u32 length:14;
116 u32 crc32:1;
117 u32 icverror:1;
118 u32 drv_infosize:4;
119 u32 security:3;
120 u32 qos:1;
121 u32 shift:2;
122 u32 phystatus:1;
123 u32 swdec:1;
124 u32 lastseg:1;
125 u32 firstseg:1;
126 u32 eor:1;
127 u32 own:1;
128 u32 macid:5; /* word 1 */
129 u32 tid:4;
130 u32 hwrsvd:5;
131 u32 paggr:1;
132 u32 faggr:1;
133 u32 a1_fit:4;
134 u32 a2_fit:4;
135 u32 pam:1;
136 u32 pwr:1;
137 u32 moredata:1;
138 u32 morefrag:1;
139 u32 type:2;
140 u32 mc:1;
141 u32 bc:1;
142 u32 seq:12; /* word 2 */
143 u32 frag:4;
144 u32 nextpktlen:14;
145 u32 nextind:1;
146 u32 rsvd:1;
147 u32 rxmcs:6; /* word 3 */
148 u32 rxht:1;
149 u32 amsdu:1;
150 u32 splcp:1;
151 u32 bandwidth:1;
152 u32 htc:1;
153 u32 tcpchk_rpt:1;
154 u32 ipcchk_rpt:1;
155 u32 tcpchk_valid:1;
156 u32 hwpcerr:1;
157 u32 hwpcind:1;
158 u32 iv0:16;
159 u32 iv1; /* word 4 */
160 u32 tsfl; /* word 5 */
161 u32 bufferaddress; /* word 6 */
162 u32 bufferaddress64; /* word 7 */
163} __packed;
164
165enum rtl_desc_qsel rtl92c_map_hwqueue_to_fwqueue(u16 fc,
166 unsigned int
167 skb_queue);
168void rtl92c_translate_rx_signal_stuff(struct ieee80211_hw *hw,
169 struct sk_buff *skb,
170 struct rtl_stats *pstats,
171 struct rx_desc_92c *pdesc,
172 struct rx_fwinfo_92c *p_drvinfo);
173
174/*---------------------------------------------------------------
175 * Card disable functions
176 *---------------------------------------------------------------*/
177
178
179
180#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
new file mode 100644
index 000000000000..4e020e654e6b
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.c
@@ -0,0 +1,607 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../pci.h"
32#include "../ps.h"
33#include "reg.h"
34#include "def.h"
35#include "phy.h"
36#include "rf.h"
37#include "dm.h"
38#include "table.h"
39
40u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
41 enum radio_path rfpath, u32 regaddr, u32 bitmask)
42{
43 struct rtl_priv *rtlpriv = rtl_priv(hw);
44 u32 original_value, readback_value, bitshift;
45 struct rtl_phy *rtlphy = &(rtlpriv->phy);
46
47 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
48 "rfpath(%#x), bitmask(%#x)\n",
49 regaddr, rfpath, bitmask));
50 if (rtlphy->rf_mode != RF_OP_BY_FW) {
51 original_value = _rtl92c_phy_rf_serial_read(hw,
52 rfpath, regaddr);
53 } else {
54 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
55 rfpath, regaddr);
56 }
57 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
58 readback_value = (original_value & bitmask) >> bitshift;
59 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
60 ("regaddr(%#x), rfpath(%#x), "
61 "bitmask(%#x), original_value(%#x)\n",
62 regaddr, rfpath, bitmask, original_value));
63 return readback_value;
64}
65
66void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw,
67 enum radio_path rfpath,
68 u32 regaddr, u32 bitmask, u32 data)
69{
70 struct rtl_priv *rtlpriv = rtl_priv(hw);
71 struct rtl_phy *rtlphy = &(rtlpriv->phy);
72 u32 original_value, bitshift;
73
74 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
75 ("regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
76 regaddr, bitmask, data, rfpath));
77 if (rtlphy->rf_mode != RF_OP_BY_FW) {
78 if (bitmask != RFREG_OFFSET_MASK) {
79 original_value = _rtl92c_phy_rf_serial_read(hw,
80 rfpath,
81 regaddr);
82 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
83 data =
84 ((original_value & (~bitmask)) |
85 (data << bitshift));
86 }
87 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
88 } else {
89 if (bitmask != RFREG_OFFSET_MASK) {
90 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
91 rfpath,
92 regaddr);
93 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
94 data =
95 ((original_value & (~bitmask)) |
96 (data << bitshift));
97 }
98 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
99 }
100 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, ("regaddr(%#x), "
101 "bitmask(%#x), data(%#x), rfpath(%#x)\n",
102 regaddr, bitmask, data, rfpath));
103}
104
105bool rtl92cu_phy_mac_config(struct ieee80211_hw *hw)
106{
107 bool rtstatus;
108 struct rtl_priv *rtlpriv = rtl_priv(hw);
109 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
110 bool is92c = IS_92C_SERIAL(rtlhal->version);
111
112 rtstatus = _rtl92cu_phy_config_mac_with_headerfile(hw);
113 if (is92c && IS_HARDWARE_TYPE_8192CE(rtlhal))
114 rtl_write_byte(rtlpriv, 0x14, 0x71);
115 return rtstatus;
116}
117
118bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw)
119{
120 bool rtstatus = true;
121 struct rtl_priv *rtlpriv = rtl_priv(hw);
122 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
123 u16 regval;
124 u8 b_reg_hwparafile = 1;
125
126 _rtl92c_phy_init_bb_rf_register_definition(hw);
127 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
128 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, regval | BIT(13) |
129 BIT(0) | BIT(1));
130 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
131 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
132 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
133 if (IS_HARDWARE_TYPE_8192CE(rtlhal)) {
134 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_PPLL | FEN_PCIEA |
135 FEN_DIO_PCIE | FEN_BB_GLB_RSTn | FEN_BBRSTB);
136 } else if (IS_HARDWARE_TYPE_8192CU(rtlhal)) {
137 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD |
138 FEN_BB_GLB_RSTn | FEN_BBRSTB);
139 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
140 }
141 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
142 if (b_reg_hwparafile == 1)
143 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
144 return rtstatus;
145}
146
147bool _rtl92cu_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
148{
149 struct rtl_priv *rtlpriv = rtl_priv(hw);
150 struct rtl_phy *rtlphy = &(rtlpriv->phy);
151 u32 i;
152 u32 arraylength;
153 u32 *ptrarray;
154
155 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Read Rtl819XMACPHY_Array\n"));
156 arraylength = rtlphy->hwparam_tables[MAC_REG].length ;
157 ptrarray = rtlphy->hwparam_tables[MAC_REG].pdata;
158 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
159 ("Img:RTL8192CEMAC_2T_ARRAY\n"));
160 for (i = 0; i < arraylength; i = i + 2)
161 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
162 return true;
163}
164
165bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
166 u8 configtype)
167{
168 int i;
169 u32 *phy_regarray_table;
170 u32 *agctab_array_table;
171 u16 phy_reg_arraylen, agctab_arraylen;
172 struct rtl_priv *rtlpriv = rtl_priv(hw);
173 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
174 struct rtl_phy *rtlphy = &(rtlpriv->phy);
175
176 if (IS_92C_SERIAL(rtlhal->version)) {
177 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_2T].length;
178 agctab_array_table = rtlphy->hwparam_tables[AGCTAB_2T].pdata;
179 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_2T].length;
180 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_2T].pdata;
181 } else {
182 agctab_arraylen = rtlphy->hwparam_tables[AGCTAB_1T].length;
183 agctab_array_table = rtlphy->hwparam_tables[AGCTAB_1T].pdata;
184 phy_reg_arraylen = rtlphy->hwparam_tables[PHY_REG_1T].length;
185 phy_regarray_table = rtlphy->hwparam_tables[PHY_REG_1T].pdata;
186 }
187 if (configtype == BASEBAND_CONFIG_PHY_REG) {
188 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
189 if (phy_regarray_table[i] == 0xfe)
190 mdelay(50);
191 else if (phy_regarray_table[i] == 0xfd)
192 mdelay(5);
193 else if (phy_regarray_table[i] == 0xfc)
194 mdelay(1);
195 else if (phy_regarray_table[i] == 0xfb)
196 udelay(50);
197 else if (phy_regarray_table[i] == 0xfa)
198 udelay(5);
199 else if (phy_regarray_table[i] == 0xf9)
200 udelay(1);
201 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
202 phy_regarray_table[i + 1]);
203 udelay(1);
204 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
205 ("The phy_regarray_table[0] is %x"
206 " Rtl819XPHY_REGArray[1] is %x\n",
207 phy_regarray_table[i],
208 phy_regarray_table[i + 1]));
209 }
210 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
211 for (i = 0; i < agctab_arraylen; i = i + 2) {
212 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
213 agctab_array_table[i + 1]);
214 udelay(1);
215 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
216 ("The agctab_array_table[0] is "
217 "%x Rtl819XPHY_REGArray[1] is %x\n",
218 agctab_array_table[i],
219 agctab_array_table[i + 1]));
220 }
221 }
222 return true;
223}
224
225bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
226 u8 configtype)
227{
228 struct rtl_priv *rtlpriv = rtl_priv(hw);
229 struct rtl_phy *rtlphy = &(rtlpriv->phy);
230 int i;
231 u32 *phy_regarray_table_pg;
232 u16 phy_regarray_pg_len;
233
234 rtlphy->pwrgroup_cnt = 0;
235 phy_regarray_pg_len = rtlphy->hwparam_tables[PHY_REG_PG].length;
236 phy_regarray_table_pg = rtlphy->hwparam_tables[PHY_REG_PG].pdata;
237 if (configtype == BASEBAND_CONFIG_PHY_REG) {
238 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
239 if (phy_regarray_table_pg[i] == 0xfe)
240 mdelay(50);
241 else if (phy_regarray_table_pg[i] == 0xfd)
242 mdelay(5);
243 else if (phy_regarray_table_pg[i] == 0xfc)
244 mdelay(1);
245 else if (phy_regarray_table_pg[i] == 0xfb)
246 udelay(50);
247 else if (phy_regarray_table_pg[i] == 0xfa)
248 udelay(5);
249 else if (phy_regarray_table_pg[i] == 0xf9)
250 udelay(1);
251 _rtl92c_store_pwrIndex_diffrate_offset(hw,
252 phy_regarray_table_pg[i],
253 phy_regarray_table_pg[i + 1],
254 phy_regarray_table_pg[i + 2]);
255 }
256 } else {
257 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
258 ("configtype != BaseBand_Config_PHY_REG\n"));
259 }
260 return true;
261}
262
263bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
264 enum radio_path rfpath)
265{
266 int i;
267 u32 *radioa_array_table;
268 u32 *radiob_array_table;
269 u16 radioa_arraylen, radiob_arraylen;
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
272 struct rtl_phy *rtlphy = &(rtlpriv->phy);
273
274 if (IS_92C_SERIAL(rtlhal->version)) {
275 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_2T].length;
276 radioa_array_table = rtlphy->hwparam_tables[RADIOA_2T].pdata;
277 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_2T].length;
278 radiob_array_table = rtlphy->hwparam_tables[RADIOB_2T].pdata;
279 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
280 ("Radio_A:RTL8192CERADIOA_2TARRAY\n"));
281 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
282 ("Radio_B:RTL8192CE_RADIOB_2TARRAY\n"));
283 } else {
284 radioa_arraylen = rtlphy->hwparam_tables[RADIOA_1T].length;
285 radioa_array_table = rtlphy->hwparam_tables[RADIOA_1T].pdata;
286 radiob_arraylen = rtlphy->hwparam_tables[RADIOB_1T].length;
287 radiob_array_table = rtlphy->hwparam_tables[RADIOB_1T].pdata;
288 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
289 ("Radio_A:RTL8192CE_RADIOA_1TARRAY\n"));
290 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
291 ("Radio_B:RTL8192CE_RADIOB_1TARRAY\n"));
292 }
293 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("Radio No %x\n", rfpath));
294 switch (rfpath) {
295 case RF90_PATH_A:
296 for (i = 0; i < radioa_arraylen; i = i + 2) {
297 if (radioa_array_table[i] == 0xfe)
298 mdelay(50);
299 else if (radioa_array_table[i] == 0xfd)
300 mdelay(5);
301 else if (radioa_array_table[i] == 0xfc)
302 mdelay(1);
303 else if (radioa_array_table[i] == 0xfb)
304 udelay(50);
305 else if (radioa_array_table[i] == 0xfa)
306 udelay(5);
307 else if (radioa_array_table[i] == 0xf9)
308 udelay(1);
309 else {
310 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
311 RFREG_OFFSET_MASK,
312 radioa_array_table[i + 1]);
313 udelay(1);
314 }
315 }
316 break;
317 case RF90_PATH_B:
318 for (i = 0; i < radiob_arraylen; i = i + 2) {
319 if (radiob_array_table[i] == 0xfe) {
320 mdelay(50);
321 } else if (radiob_array_table[i] == 0xfd)
322 mdelay(5);
323 else if (radiob_array_table[i] == 0xfc)
324 mdelay(1);
325 else if (radiob_array_table[i] == 0xfb)
326 udelay(50);
327 else if (radiob_array_table[i] == 0xfa)
328 udelay(5);
329 else if (radiob_array_table[i] == 0xf9)
330 udelay(1);
331 else {
332 rtl_set_rfreg(hw, rfpath, radiob_array_table[i],
333 RFREG_OFFSET_MASK,
334 radiob_array_table[i + 1]);
335 udelay(1);
336 }
337 }
338 break;
339 case RF90_PATH_C:
340 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
341 ("switch case not process\n"));
342 break;
343 case RF90_PATH_D:
344 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
345 ("switch case not process\n"));
346 break;
347 }
348 return true;
349}
350
351void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
352{
353 struct rtl_priv *rtlpriv = rtl_priv(hw);
354 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
355 struct rtl_phy *rtlphy = &(rtlpriv->phy);
356 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
357 u8 reg_bw_opmode;
358 u8 reg_prsr_rsc;
359
360 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
361 ("Switch to %s bandwidth\n",
362 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
363 "20MHz" : "40MHz"))
364 if (is_hal_stop(rtlhal)) {
365 rtlphy->set_bwmode_inprogress = false;
366 return;
367 }
368 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
369 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
370 switch (rtlphy->current_chan_bw) {
371 case HT_CHANNEL_WIDTH_20:
372 reg_bw_opmode |= BW_OPMODE_20MHZ;
373 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
374 break;
375 case HT_CHANNEL_WIDTH_20_40:
376 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
377 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
378 reg_prsr_rsc =
379 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
380 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
381 break;
382 default:
383 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
384 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
385 break;
386 }
387 switch (rtlphy->current_chan_bw) {
388 case HT_CHANNEL_WIDTH_20:
389 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
390 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
391 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
392 break;
393 case HT_CHANNEL_WIDTH_20_40:
394 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
395 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
396 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
397 (mac->cur_40_prime_sc >> 1));
398 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
399 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
400 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
401 (mac->cur_40_prime_sc ==
402 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
403 break;
404 default:
405 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
406 ("unknown bandwidth: %#X\n", rtlphy->current_chan_bw));
407 break;
408 }
409 rtl92cu_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
410 rtlphy->set_bwmode_inprogress = false;
411 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, ("<==\n"));
412}
413
414void rtl92cu_bb_block_on(struct ieee80211_hw *hw)
415{
416 struct rtl_priv *rtlpriv = rtl_priv(hw);
417
418 mutex_lock(&rtlpriv->io.bb_mutex);
419 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
420 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
421 mutex_unlock(&rtlpriv->io.bb_mutex);
422}
423
424void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
425{
426 u8 tmpreg;
427 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
428 struct rtl_priv *rtlpriv = rtl_priv(hw);
429
430 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
431
432 if ((tmpreg & 0x70) != 0)
433 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
434 else
435 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
436
437 if ((tmpreg & 0x70) != 0) {
438 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
439 if (is2t)
440 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
441 MASK12BITS);
442 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
443 (rf_a_mode & 0x8FFFF) | 0x10000);
444 if (is2t)
445 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
446 (rf_b_mode & 0x8FFFF) | 0x10000);
447 }
448 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
449 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
450 mdelay(100);
451 if ((tmpreg & 0x70) != 0) {
452 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
453 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
454 if (is2t)
455 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
456 rf_b_mode);
457 } else {
458 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
459 }
460}
461
462bool _rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
463 enum rf_pwrstate rfpwr_state)
464{
465 struct rtl_priv *rtlpriv = rtl_priv(hw);
466 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
467 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
468 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
469 bool bresult = true;
470 u8 i, queue_id;
471 struct rtl8192_tx_ring *ring = NULL;
472
473 ppsc->set_rfpowerstate_inprogress = true;
474 switch (rfpwr_state) {
475 case ERFON:
476 if ((ppsc->rfpwr_state == ERFOFF) &&
477 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
478 bool rtstatus;
479 u32 InitializeCount = 0;
480
481 do {
482 InitializeCount++;
483 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
484 ("IPS Set eRf nic enable\n"));
485 rtstatus = rtl_ps_enable_nic(hw);
486 } while ((rtstatus != true)
487 && (InitializeCount < 10));
488 RT_CLEAR_PS_LEVEL(ppsc,
489 RT_RF_OFF_LEVL_HALT_NIC);
490 } else {
491 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
492 ("Set ERFON sleeped:%d ms\n",
493 jiffies_to_msecs(jiffies -
494 ppsc->
495 last_sleep_jiffies)));
496 ppsc->last_awake_jiffies = jiffies;
497 rtl92ce_phy_set_rf_on(hw);
498 }
499 if (mac->link_state == MAC80211_LINKED) {
500 rtlpriv->cfg->ops->led_control(hw,
501 LED_CTL_LINK);
502 } else {
503 rtlpriv->cfg->ops->led_control(hw,
504 LED_CTL_NO_LINK);
505 }
506 break;
507 case ERFOFF:
508 for (queue_id = 0, i = 0;
509 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
510 ring = &pcipriv->dev.tx_ring[queue_id];
511 if (skb_queue_len(&ring->queue) == 0 ||
512 queue_id == BEACON_QUEUE) {
513 queue_id++;
514 continue;
515 } else {
516 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
517 ("eRf Off/Sleep: %d times "
518 "TcbBusyQueue[%d] "
519 "=%d before doze!\n", (i + 1),
520 queue_id,
521 skb_queue_len(&ring->queue)));
522 udelay(10);
523 i++;
524 }
525 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
526 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
527 ("\nERFOFF: %d times "
528 "TcbBusyQueue[%d] = %d !\n",
529 MAX_DOZE_WAITING_TIMES_9x,
530 queue_id,
531 skb_queue_len(&ring->queue)));
532 break;
533 }
534 }
535 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
536 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
537 ("IPS Set eRf nic disable\n"));
538 rtl_ps_disable_nic(hw);
539 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
540 } else {
541 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
542 rtlpriv->cfg->ops->led_control(hw,
543 LED_CTL_NO_LINK);
544 } else {
545 rtlpriv->cfg->ops->led_control(hw,
546 LED_CTL_POWER_OFF);
547 }
548 }
549 break;
550 case ERFSLEEP:
551 if (ppsc->rfpwr_state == ERFOFF)
552 break;
553 for (queue_id = 0, i = 0;
554 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
555 ring = &pcipriv->dev.tx_ring[queue_id];
556 if (skb_queue_len(&ring->queue) == 0) {
557 queue_id++;
558 continue;
559 } else {
560 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
561 ("eRf Off/Sleep: %d times "
562 "TcbBusyQueue[%d] =%d before "
563 "doze!\n", (i + 1), queue_id,
564 skb_queue_len(&ring->queue)));
565 udelay(10);
566 i++;
567 }
568 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
569 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
570 ("\n ERFSLEEP: %d times "
571 "TcbBusyQueue[%d] = %d !\n",
572 MAX_DOZE_WAITING_TIMES_9x,
573 queue_id,
574 skb_queue_len(&ring->queue)));
575 break;
576 }
577 }
578 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
579 ("Set ERFSLEEP awaked:%d ms\n",
580 jiffies_to_msecs(jiffies -
581 ppsc->last_awake_jiffies)));
582 ppsc->last_sleep_jiffies = jiffies;
583 _rtl92c_phy_set_rf_sleep(hw);
584 break;
585 default:
586 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
587 ("switch case not process\n"));
588 bresult = false;
589 break;
590 }
591 if (bresult)
592 ppsc->rfpwr_state = rfpwr_state;
593 ppsc->set_rfpowerstate_inprogress = false;
594 return bresult;
595}
596
597bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
598 enum rf_pwrstate rfpwr_state)
599{
600 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
601 bool bresult = false;
602
603 if (rfpwr_state == ppsc->rfpwr_state)
604 return bresult;
605 bresult = _rtl92cu_phy_set_rf_power_state(hw, rfpwr_state);
606 return bresult;
607}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/phy.h b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.h
new file mode 100644
index 000000000000..06299559ab68
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/phy.h
@@ -0,0 +1,36 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../rtl8192ce/phy.h"
31
32void rtl92cu_bb_block_on(struct ieee80211_hw *hw);
33bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath);
34void rtl92c_phy_set_io(struct ieee80211_hw *hw);
35bool _rtl92cu_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
36bool rtl92cu_phy_bb_config(struct ieee80211_hw *hw);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/reg.h b/drivers/net/wireless/rtlwifi/rtl8192cu/reg.h
new file mode 100644
index 000000000000..7f1be614c998
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/reg.h
@@ -0,0 +1,30 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../rtl8192ce/reg.h"
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c
new file mode 100644
index 000000000000..1c79c226f145
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.c
@@ -0,0 +1,493 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "reg.h"
32#include "def.h"
33#include "phy.h"
34#include "rf.h"
35#include "dm.h"
36
37static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
38
39void rtl92cu_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
40{
41 struct rtl_priv *rtlpriv = rtl_priv(hw);
42 struct rtl_phy *rtlphy = &(rtlpriv->phy);
43
44 switch (bandwidth) {
45 case HT_CHANNEL_WIDTH_20:
46 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
47 0xfffff3ff) | 0x0400);
48 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
49 rtlphy->rfreg_chnlval[0]);
50 break;
51 case HT_CHANNEL_WIDTH_20_40:
52 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
53 0xfffff3ff));
54 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
55 rtlphy->rfreg_chnlval[0]);
56 break;
57 default:
58 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
59 ("unknown bandwidth: %#X\n", bandwidth));
60 break;
61 }
62}
63
64void rtl92cu_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
65 u8 *ppowerlevel)
66{
67 struct rtl_priv *rtlpriv = rtl_priv(hw);
68 struct rtl_phy *rtlphy = &(rtlpriv->phy);
69 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
70 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
71 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
72 u32 tx_agc[2] = { 0, 0 }, tmpval = 0;
73 bool turbo_scanoff = false;
74 u8 idx1, idx2;
75 u8 *ptr;
76
77 if (rtlhal->interface == INTF_PCI) {
78 if (rtlefuse->eeprom_regulatory != 0)
79 turbo_scanoff = true;
80 } else {
81 if ((rtlefuse->eeprom_regulatory != 0) ||
82 (rtlefuse->external_pa))
83 turbo_scanoff = true;
84 }
85 if (mac->act_scanning == true) {
86 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
87 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
88 if (turbo_scanoff) {
89 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
90 tx_agc[idx1] = ppowerlevel[idx1] |
91 (ppowerlevel[idx1] << 8) |
92 (ppowerlevel[idx1] << 16) |
93 (ppowerlevel[idx1] << 24);
94 if (rtlhal->interface == INTF_USB) {
95 if (tx_agc[idx1] > 0x20 &&
96 rtlefuse->external_pa)
97 tx_agc[idx1] = 0x20;
98 }
99 }
100 }
101 } else {
102 if (rtlpriv->dm.dynamic_txhighpower_lvl ==
103 TXHIGHPWRLEVEL_LEVEL1) {
104 tx_agc[RF90_PATH_A] = 0x10101010;
105 tx_agc[RF90_PATH_B] = 0x10101010;
106 } else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
107 TXHIGHPWRLEVEL_LEVEL1) {
108 tx_agc[RF90_PATH_A] = 0x00000000;
109 tx_agc[RF90_PATH_B] = 0x00000000;
110 } else{
111 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
112 tx_agc[idx1] = ppowerlevel[idx1] |
113 (ppowerlevel[idx1] << 8) |
114 (ppowerlevel[idx1] << 16) |
115 (ppowerlevel[idx1] << 24);
116 }
117 if (rtlefuse->eeprom_regulatory == 0) {
118 tmpval = (rtlphy->mcs_txpwrlevel_origoffset
119 [0][6]) +
120 (rtlphy->mcs_txpwrlevel_origoffset
121 [0][7] << 8);
122 tx_agc[RF90_PATH_A] += tmpval;
123 tmpval = (rtlphy->mcs_txpwrlevel_origoffset
124 [0][14]) +
125 (rtlphy->mcs_txpwrlevel_origoffset
126 [0][15] << 24);
127 tx_agc[RF90_PATH_B] += tmpval;
128 }
129 }
130 }
131 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
132 ptr = (u8 *) (&(tx_agc[idx1]));
133 for (idx2 = 0; idx2 < 4; idx2++) {
134 if (*ptr > RF6052_MAX_TX_PWR)
135 *ptr = RF6052_MAX_TX_PWR;
136 ptr++;
137 }
138 }
139 tmpval = tx_agc[RF90_PATH_A] & 0xff;
140 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
141
142 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
143 ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
144 RTXAGC_A_CCK1_MCS32));
145
146 tmpval = tx_agc[RF90_PATH_A] >> 8;
147 if (mac->mode == WIRELESS_MODE_B)
148 tmpval = tmpval & 0xff00ffff;
149 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
150 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
151 ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval,
152 RTXAGC_B_CCK11_A_CCK2_11));
153 tmpval = tx_agc[RF90_PATH_B] >> 24;
154 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
155 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
156 ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
157 RTXAGC_B_CCK11_A_CCK2_11));
158 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
159 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
160 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
161 ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", tmpval,
162 RTXAGC_B_CCK1_55_MCS32));
163}
164
165static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
166 u8 *ppowerlevel, u8 channel,
167 u32 *ofdmbase, u32 *mcsbase)
168{
169 struct rtl_priv *rtlpriv = rtl_priv(hw);
170 struct rtl_phy *rtlphy = &(rtlpriv->phy);
171 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
172 u32 powerBase0, powerBase1;
173 u8 legacy_pwrdiff = 0, ht20_pwrdiff = 0;
174 u8 i, powerlevel[2];
175
176 for (i = 0; i < 2; i++) {
177 powerlevel[i] = ppowerlevel[i];
178 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
179 powerBase0 = powerlevel[i] + legacy_pwrdiff;
180 powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
181 (powerBase0 << 8) | powerBase0;
182 *(ofdmbase + i) = powerBase0;
183 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
184 (" [OFDM power base index rf(%c) = 0x%x]\n",
185 ((i == 0) ? 'A' : 'B'), *(ofdmbase + i)));
186 }
187 for (i = 0; i < 2; i++) {
188 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
189 ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
190 powerlevel[i] += ht20_pwrdiff;
191 }
192 powerBase1 = powerlevel[i];
193 powerBase1 = (powerBase1 << 24) |
194 (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
195 *(mcsbase + i) = powerBase1;
196 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
197 (" [MCS power base index rf(%c) = 0x%x]\n",
198 ((i == 0) ? 'A' : 'B'), *(mcsbase + i)));
199 }
200}
201
202static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
203 u8 channel, u8 index,
204 u32 *powerBase0,
205 u32 *powerBase1,
206 u32 *p_outwriteval)
207{
208 struct rtl_priv *rtlpriv = rtl_priv(hw);
209 struct rtl_phy *rtlphy = &(rtlpriv->phy);
210 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
211 u8 i, chnlgroup = 0, pwr_diff_limit[4];
212 u32 writeVal, customer_limit, rf;
213
214 for (rf = 0; rf < 2; rf++) {
215 switch (rtlefuse->eeprom_regulatory) {
216 case 0:
217 chnlgroup = 0;
218 writeVal = rtlphy->mcs_txpwrlevel_origoffset
219 [chnlgroup][index + (rf ? 8 : 0)]
220 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
221 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
222 ("RTK better performance,writeVal(%c) = 0x%x\n",
223 ((rf == 0) ? 'A' : 'B'), writeVal));
224 break;
225 case 1:
226 if (rtlphy->pwrgroup_cnt == 1)
227 chnlgroup = 0;
228 if (rtlphy->pwrgroup_cnt >= 3) {
229 if (channel <= 3)
230 chnlgroup = 0;
231 else if (channel >= 4 && channel <= 9)
232 chnlgroup = 1;
233 else if (channel > 9)
234 chnlgroup = 2;
235 if (rtlphy->current_chan_bw ==
236 HT_CHANNEL_WIDTH_20)
237 chnlgroup++;
238 else
239 chnlgroup += 4;
240 }
241 writeVal = rtlphy->mcs_txpwrlevel_origoffset
242 [chnlgroup][index +
243 (rf ? 8 : 0)] +
244 ((index < 2) ? powerBase0[rf] :
245 powerBase1[rf]);
246 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
247 ("Realtek regulatory, 20MHz, "
248 "writeVal(%c) = 0x%x\n",
249 ((rf == 0) ? 'A' : 'B'), writeVal));
250 break;
251 case 2:
252 writeVal = ((index < 2) ? powerBase0[rf] :
253 powerBase1[rf]);
254 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
255 ("Better regulatory,writeVal(%c) = 0x%x\n",
256 ((rf == 0) ? 'A' : 'B'), writeVal));
257 break;
258 case 3:
259 chnlgroup = 0;
260 if (rtlphy->current_chan_bw ==
261 HT_CHANNEL_WIDTH_20_40) {
262 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
263 ("customer's limit, 40MHzrf(%c) = "
264 "0x%x\n", ((rf == 0) ? 'A' : 'B'),
265 rtlefuse->pwrgroup_ht40[rf]
266 [channel - 1]));
267 } else {
268 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
269 ("customer's limit, 20MHz rf(%c) = "
270 "0x%x\n", ((rf == 0) ? 'A' : 'B'),
271 rtlefuse->pwrgroup_ht20[rf]
272 [channel - 1]));
273 }
274 for (i = 0; i < 4; i++) {
275 pwr_diff_limit[i] =
276 (u8) ((rtlphy->mcs_txpwrlevel_origoffset
277 [chnlgroup][index + (rf ? 8 : 0)]
278 & (0x7f << (i * 8))) >> (i * 8));
279 if (rtlphy->current_chan_bw ==
280 HT_CHANNEL_WIDTH_20_40) {
281 if (pwr_diff_limit[i] >
282 rtlefuse->pwrgroup_ht40[rf]
283 [channel - 1])
284 pwr_diff_limit[i] = rtlefuse->
285 pwrgroup_ht40[rf]
286 [channel - 1];
287 } else {
288 if (pwr_diff_limit[i] >
289 rtlefuse->pwrgroup_ht20[rf]
290 [channel - 1])
291 pwr_diff_limit[i] =
292 rtlefuse->pwrgroup_ht20[rf]
293 [channel - 1];
294 }
295 }
296 customer_limit = (pwr_diff_limit[3] << 24) |
297 (pwr_diff_limit[2] << 16) |
298 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
299 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
300 ("Customer's limit rf(%c) = 0x%x\n",
301 ((rf == 0) ? 'A' : 'B'), customer_limit));
302 writeVal = customer_limit + ((index < 2) ?
303 powerBase0[rf] : powerBase1[rf]);
304 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
305 ("Customer, writeVal rf(%c)= 0x%x\n",
306 ((rf == 0) ? 'A' : 'B'), writeVal));
307 break;
308 default:
309 chnlgroup = 0;
310 writeVal = rtlphy->mcs_txpwrlevel_origoffset[chnlgroup]
311 [index + (rf ? 8 : 0)] + ((index < 2) ?
312 powerBase0[rf] : powerBase1[rf]);
313 RTPRINT(rtlpriv, FPHY, PHY_TXPWR, ("RTK better "
314 "performance, writeValrf(%c) = 0x%x\n",
315 ((rf == 0) ? 'A' : 'B'), writeVal));
316 break;
317 }
318 if (rtlpriv->dm.dynamic_txhighpower_lvl ==
319 TXHIGHPWRLEVEL_LEVEL1)
320 writeVal = 0x14141414;
321 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
322 TXHIGHPWRLEVEL_LEVEL2)
323 writeVal = 0x00000000;
324 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
325 writeVal = writeVal - 0x06060606;
326 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
327 TXHIGHPWRLEVEL_BT2)
328 writeVal = writeVal;
329 *(p_outwriteval + rf) = writeVal;
330 }
331}
332
333static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw,
334 u8 index, u32 *pValue)
335{
336 struct rtl_priv *rtlpriv = rtl_priv(hw);
337 struct rtl_phy *rtlphy = &(rtlpriv->phy);
338 u16 regoffset_a[6] = {
339 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
340 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
341 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
342 };
343 u16 regoffset_b[6] = {
344 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
345 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
346 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
347 };
348 u8 i, rf, pwr_val[4];
349 u32 writeVal;
350 u16 regoffset;
351
352 for (rf = 0; rf < 2; rf++) {
353 writeVal = pValue[rf];
354 for (i = 0; i < 4; i++) {
355 pwr_val[i] = (u8)((writeVal & (0x7f << (i * 8))) >>
356 (i * 8));
357 if (pwr_val[i] > RF6052_MAX_TX_PWR)
358 pwr_val[i] = RF6052_MAX_TX_PWR;
359 }
360 writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
361 (pwr_val[1] << 8) | pwr_val[0];
362 if (rf == 0)
363 regoffset = regoffset_a[index];
364 else
365 regoffset = regoffset_b[index];
366 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
367 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
368 ("Set 0x%x = %08x\n", regoffset, writeVal));
369 if (((get_rf_type(rtlphy) == RF_2T2R) &&
370 (regoffset == RTXAGC_A_MCS15_MCS12 ||
371 regoffset == RTXAGC_B_MCS15_MCS12)) ||
372 ((get_rf_type(rtlphy) != RF_2T2R) &&
373 (regoffset == RTXAGC_A_MCS07_MCS04 ||
374 regoffset == RTXAGC_B_MCS07_MCS04))) {
375 writeVal = pwr_val[3];
376 if (regoffset == RTXAGC_A_MCS15_MCS12 ||
377 regoffset == RTXAGC_A_MCS07_MCS04)
378 regoffset = 0xc90;
379 if (regoffset == RTXAGC_B_MCS15_MCS12 ||
380 regoffset == RTXAGC_B_MCS07_MCS04)
381 regoffset = 0xc98;
382 for (i = 0; i < 3; i++) {
383 writeVal = (writeVal > 6) ? (writeVal - 6) : 0;
384 rtl_write_byte(rtlpriv, (u32)(regoffset + i),
385 (u8)writeVal);
386 }
387 }
388 }
389}
390
391void rtl92cu_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
392 u8 *ppowerlevel, u8 channel)
393{
394 u32 writeVal[2], powerBase0[2], powerBase1[2];
395 u8 index = 0;
396
397 rtl92c_phy_get_power_base(hw, ppowerlevel,
398 channel, &powerBase0[0], &powerBase1[0]);
399 for (index = 0; index < 6; index++) {
400 _rtl92c_get_txpower_writeval_by_regulatory(hw,
401 channel, index,
402 &powerBase0[0],
403 &powerBase1[0],
404 &writeVal[0]);
405 _rtl92c_write_ofdm_power_reg(hw, index, &writeVal[0]);
406 }
407}
408
409bool rtl92cu_phy_rf6052_config(struct ieee80211_hw *hw)
410{
411 struct rtl_priv *rtlpriv = rtl_priv(hw);
412 struct rtl_phy *rtlphy = &(rtlpriv->phy);
413 bool rtstatus = true;
414 u8 b_reg_hwparafile = 1;
415
416 if (rtlphy->rf_type == RF_1T1R)
417 rtlphy->num_total_rfpath = 1;
418 else
419 rtlphy->num_total_rfpath = 2;
420 if (b_reg_hwparafile == 1)
421 rtstatus = _rtl92c_phy_rf6052_config_parafile(hw);
422 return rtstatus;
423}
424
425static bool _rtl92c_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
426{
427 struct rtl_priv *rtlpriv = rtl_priv(hw);
428 struct rtl_phy *rtlphy = &(rtlpriv->phy);
429 u32 u4_regvalue = 0;
430 u8 rfpath;
431 bool rtstatus = true;
432 struct bb_reg_def *pphyreg;
433
434 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
435 pphyreg = &rtlphy->phyreg_def[rfpath];
436 switch (rfpath) {
437 case RF90_PATH_A:
438 case RF90_PATH_C:
439 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
440 BRFSI_RFENV);
441 break;
442 case RF90_PATH_B:
443 case RF90_PATH_D:
444 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
445 BRFSI_RFENV << 16);
446 break;
447 }
448 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
449 udelay(1);
450 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
451 udelay(1);
452 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
453 B3WIREADDREAALENGTH, 0x0);
454 udelay(1);
455 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
456 udelay(1);
457 switch (rfpath) {
458 case RF90_PATH_A:
459 rtstatus = rtl92cu_phy_config_rf_with_headerfile(hw,
460 (enum radio_path) rfpath);
461 break;
462 case RF90_PATH_B:
463 rtstatus = rtl92cu_phy_config_rf_with_headerfile(hw,
464 (enum radio_path) rfpath);
465 break;
466 case RF90_PATH_C:
467 break;
468 case RF90_PATH_D:
469 break;
470 }
471 switch (rfpath) {
472 case RF90_PATH_A:
473 case RF90_PATH_C:
474 rtl_set_bbreg(hw, pphyreg->rfintfs,
475 BRFSI_RFENV, u4_regvalue);
476 break;
477 case RF90_PATH_B:
478 case RF90_PATH_D:
479 rtl_set_bbreg(hw, pphyreg->rfintfs,
480 BRFSI_RFENV << 16, u4_regvalue);
481 break;
482 }
483 if (rtstatus != true) {
484 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
485 ("Radio[%d] Fail!!", rfpath));
486 goto phy_rf_cfg_fail;
487 }
488 }
489 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("<---\n"));
490 return rtstatus;
491phy_rf_cfg_fail:
492 return rtstatus;
493}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/rf.h b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.h
new file mode 100644
index 000000000000..86c2728cfa00
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/rf.h
@@ -0,0 +1,47 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CU_RF_H__
31#define __RTL92CU_RF_H__
32
33#define RF6052_MAX_TX_PWR 0x3F
34#define RF6052_MAX_REG 0x3F
35#define RF6052_MAX_PATH 2
36
37extern void rtl92cu_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw,
38 u8 bandwidth);
39extern void rtl92c_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
40 u8 *ppowerlevel);
41extern void rtl92c_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
42 u8 *ppowerlevel, u8 channel);
43bool rtl92cu_phy_rf6052_config(struct ieee80211_hw *hw);
44bool rtl92cu_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
45 enum radio_path rfpath);
46
47#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
new file mode 100644
index 000000000000..71244a38d49e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
@@ -0,0 +1,336 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../core.h"
32#include "../usb.h"
33#include "../efuse.h"
34#include "reg.h"
35#include "def.h"
36#include "phy.h"
37#include "mac.h"
38#include "dm.h"
39#include "rf.h"
40#include "sw.h"
41#include "trx.h"
42#include "led.h"
43#include "hw.h"
44#include <linux/vmalloc.h>
45
46MODULE_AUTHOR("Georgia <georgia@realtek.com>");
47MODULE_AUTHOR("Ziv Huang <ziv_huang@realtek.com>");
48MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
49MODULE_LICENSE("GPL");
50MODULE_DESCRIPTION("Realtek 8192C/8188C 802.11n USB wireless");
51MODULE_FIRMWARE("rtlwifi/rtl8192cufw.bin");
52
53static int rtl92cu_init_sw_vars(struct ieee80211_hw *hw)
54{
55 struct rtl_priv *rtlpriv = rtl_priv(hw);
56
57 rtlpriv->dm.dm_initialgain_enable = 1;
58 rtlpriv->dm.dm_flag = 0;
59 rtlpriv->dm.disable_framebursting = 0;
60 rtlpriv->dm.thermalvalue = 0;
61 rtlpriv->rtlhal.pfirmware = vmalloc(0x4000);
62 if (!rtlpriv->rtlhal.pfirmware) {
63 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
64 ("Can't alloc buffer for fw.\n"));
65 return 1;
66 }
67 return 0;
68}
69
70static void rtl92cu_deinit_sw_vars(struct ieee80211_hw *hw)
71{
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
73
74 if (rtlpriv->rtlhal.pfirmware) {
75 vfree(rtlpriv->rtlhal.pfirmware);
76 rtlpriv->rtlhal.pfirmware = NULL;
77 }
78}
79
80static struct rtl_hal_ops rtl8192cu_hal_ops = {
81 .init_sw_vars = rtl92cu_init_sw_vars,
82 .deinit_sw_vars = rtl92cu_deinit_sw_vars,
83 .read_chip_version = rtl92c_read_chip_version,
84 .read_eeprom_info = rtl92cu_read_eeprom_info,
85 .enable_interrupt = rtl92c_enable_interrupt,
86 .disable_interrupt = rtl92c_disable_interrupt,
87 .hw_init = rtl92cu_hw_init,
88 .hw_disable = rtl92cu_card_disable,
89 .set_network_type = rtl92cu_set_network_type,
90 .set_chk_bssid = rtl92cu_set_check_bssid,
91 .set_qos = rtl92c_set_qos,
92 .set_bcn_reg = rtl92cu_set_beacon_related_registers,
93 .set_bcn_intv = rtl92cu_set_beacon_interval,
94 .update_interrupt_mask = rtl92cu_update_interrupt_mask,
95 .get_hw_reg = rtl92cu_get_hw_reg,
96 .set_hw_reg = rtl92cu_set_hw_reg,
97 .update_rate_table = rtl92cu_update_hal_rate_table,
98 .update_rate_mask = rtl92cu_update_hal_rate_mask,
99 .fill_tx_desc = rtl92cu_tx_fill_desc,
100 .fill_fake_txdesc = rtl92cu_fill_fake_txdesc,
101 .fill_tx_cmddesc = rtl92cu_tx_fill_cmddesc,
102 .cmd_send_packet = rtl92cu_cmd_send_packet,
103 .query_rx_desc = rtl92cu_rx_query_desc,
104 .set_channel_access = rtl92cu_update_channel_access_setting,
105 .radio_onoff_checking = rtl92cu_gpio_radio_on_off_checking,
106 .set_bw_mode = rtl92c_phy_set_bw_mode,
107 .switch_channel = rtl92c_phy_sw_chnl,
108 .dm_watchdog = rtl92c_dm_watchdog,
109 .scan_operation_backup = rtl92c_phy_scan_operation_backup,
110 .set_rf_power_state = rtl92cu_phy_set_rf_power_state,
111 .led_control = rtl92cu_led_control,
112 .enable_hw_sec = rtl92cu_enable_hw_security_config,
113 .set_key = rtl92c_set_key,
114 .init_sw_leds = rtl92cu_init_sw_leds,
115 .deinit_sw_leds = rtl92cu_deinit_sw_leds,
116 .get_bbreg = rtl92c_phy_query_bb_reg,
117 .set_bbreg = rtl92c_phy_set_bb_reg,
118 .get_rfreg = rtl92cu_phy_query_rf_reg,
119 .set_rfreg = rtl92cu_phy_set_rf_reg,
120 .phy_rf6052_config = rtl92cu_phy_rf6052_config,
121 .phy_rf6052_set_cck_txpower = rtl92cu_phy_rf6052_set_cck_txpower,
122 .phy_rf6052_set_ofdm_txpower = rtl92cu_phy_rf6052_set_ofdm_txpower,
123 .config_bb_with_headerfile = _rtl92cu_phy_config_bb_with_headerfile,
124 .config_bb_with_pgheaderfile = _rtl92cu_phy_config_bb_with_pgheaderfile,
125 .phy_lc_calibrate = _rtl92cu_phy_lc_calibrate,
126 .phy_set_bw_mode_callback = rtl92cu_phy_set_bw_mode_callback,
127 .dm_dynamic_txpower = rtl92cu_dm_dynamic_txpower,
128};
129
130static struct rtl_mod_params rtl92cu_mod_params = {
131 .sw_crypto = 0,
132};
133
134static struct rtl_hal_usbint_cfg rtl92cu_interface_cfg = {
135 /* rx */
136 .in_ep_num = RTL92C_USB_BULK_IN_NUM,
137 .rx_urb_num = RTL92C_NUM_RX_URBS,
138 .rx_max_size = RTL92C_SIZE_MAX_RX_BUFFER,
139 .usb_rx_hdl = rtl8192cu_rx_hdl,
140 .usb_rx_segregate_hdl = NULL, /* rtl8192c_rx_segregate_hdl; */
141 /* tx */
142 .usb_tx_cleanup = rtl8192c_tx_cleanup,
143 .usb_tx_post_hdl = rtl8192c_tx_post_hdl,
144 .usb_tx_aggregate_hdl = rtl8192c_tx_aggregate_hdl,
145 /* endpoint mapping */
146 .usb_endpoint_mapping = rtl8192cu_endpoint_mapping,
147 .usb_mq_to_hwq = rtl8192cu_mq_to_hwq,
148};
149
150static struct rtl_hal_cfg rtl92cu_hal_cfg = {
151 .name = "rtl92c_usb",
152 .fw_name = "rtlwifi/rtl8192cufw.bin",
153 .ops = &rtl8192cu_hal_ops,
154 .mod_params = &rtl92cu_mod_params,
155 .usb_interface_cfg = &rtl92cu_interface_cfg,
156
157 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
158 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
159 .maps[SYS_CLK] = REG_SYS_CLKR,
160 .maps[MAC_RCR_AM] = AM,
161 .maps[MAC_RCR_AB] = AB,
162 .maps[MAC_RCR_ACRC32] = ACRC32,
163 .maps[MAC_RCR_ACF] = ACF,
164 .maps[MAC_RCR_AAP] = AAP,
165
166 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
167 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
168 .maps[EFUSE_CLK] = 0,
169 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
170 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
171 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
172 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
173 .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
174 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
175 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
176 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
177
178 .maps[RWCAM] = REG_CAMCMD,
179 .maps[WCAMI] = REG_CAMWRITE,
180 .maps[RCAMO] = REG_CAMREAD,
181 .maps[CAMDBG] = REG_CAMDBG,
182 .maps[SECR] = REG_SECCFG,
183 .maps[SEC_CAM_NONE] = CAM_NONE,
184 .maps[SEC_CAM_WEP40] = CAM_WEP40,
185 .maps[SEC_CAM_TKIP] = CAM_TKIP,
186 .maps[SEC_CAM_AES] = CAM_AES,
187 .maps[SEC_CAM_WEP104] = CAM_WEP104,
188
189 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
190 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
191 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
192 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
193 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
194 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
195 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
196 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
197 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
198 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
199 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
200 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
201 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
202 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
203 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
204 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
205
206 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
207 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
208 .maps[RTL_IMR_BcnInt] = IMR_BCNINT,
209 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
210 .maps[RTL_IMR_RDU] = IMR_RDU,
211 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
212 .maps[RTL_IMR_BDOK] = IMR_BDOK,
213 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
214 .maps[RTL_IMR_TBDER] = IMR_TBDER,
215 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
216 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
217 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
218 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
219 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
220 .maps[RTL_IMR_VODOK] = IMR_VODOK,
221 .maps[RTL_IMR_ROK] = IMR_ROK,
222 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
223
224 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
225 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
226 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
227 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
228 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
229 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
230 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
231 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
232 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
233 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
234 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
235 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
236 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
237 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
238};
239
240#define USB_VENDER_ID_REALTEK 0x0bda
241
242/* 2010-10-19 DID_USB_V3.4 */
243static struct usb_device_id rtl8192c_usb_ids[] = {
244
245 /*=== Realtek demoboard ===*/
246 /* Default ID */
247 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8191, rtl92cu_hal_cfg)},
248
249 /****** 8188CU ********/
250 /* 8188CE-VAU USB minCard */
251 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8170, rtl92cu_hal_cfg)},
252 /* 8188cu 1*1 dongle */
253 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8176, rtl92cu_hal_cfg)},
254 /* 8188cu 1*1 dongle, (b/g mode only) */
255 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8177, rtl92cu_hal_cfg)},
256 /* 8188cu Slim Solo */
257 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817a, rtl92cu_hal_cfg)},
258 /* 8188cu Slim Combo */
259 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817b, rtl92cu_hal_cfg)},
260 /* 8188RU High-power USB Dongle */
261 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817d, rtl92cu_hal_cfg)},
262 /* 8188CE-VAU USB minCard (b/g mode only) */
263 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817e, rtl92cu_hal_cfg)},
264 /* 8188 Combo for BC4 */
265 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8754, rtl92cu_hal_cfg)},
266
267 /****** 8192CU ********/
268 /* 8191cu 1*2 */
269 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8177, rtl92cu_hal_cfg)},
270 /* 8192cu 2*2 */
271 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817b, rtl92cu_hal_cfg)},
272 /* 8192CE-VAU USB minCard */
273 {RTL_USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817c, rtl92cu_hal_cfg)},
274
275 /*=== Customer ID ===*/
276 /****** 8188CU ********/
277 {RTL_USB_DEVICE(0x050d, 0x1102, rtl92cu_hal_cfg)}, /*Belkin - Edimax*/
278 {RTL_USB_DEVICE(0x06f8, 0xe033, rtl92cu_hal_cfg)}, /*Hercules - Edimax*/
279 {RTL_USB_DEVICE(0x07b8, 0x8188, rtl92cu_hal_cfg)}, /*Abocom - Abocom*/
280 {RTL_USB_DEVICE(0x07b8, 0x8189, rtl92cu_hal_cfg)}, /*Funai - Abocom*/
281 {RTL_USB_DEVICE(0x0Df6, 0x0052, rtl92cu_hal_cfg)}, /*Sitecom - Edimax*/
282 {RTL_USB_DEVICE(0x0eb0, 0x9071, rtl92cu_hal_cfg)}, /*NO Brand - Etop*/
283 /* HP - Lite-On ,8188CUS Slim Combo */
284 {RTL_USB_DEVICE(0x103c, 0x1629, rtl92cu_hal_cfg)},
285 {RTL_USB_DEVICE(0x2001, 0x3308, rtl92cu_hal_cfg)}, /*D-Link - Alpha*/
286 {RTL_USB_DEVICE(0x2019, 0xab2a, rtl92cu_hal_cfg)}, /*Planex - Abocom*/
287 {RTL_USB_DEVICE(0x2019, 0xed17, rtl92cu_hal_cfg)}, /*PCI - Edimax*/
288 {RTL_USB_DEVICE(0x20f4, 0x648b, rtl92cu_hal_cfg)}, /*TRENDnet - Cameo*/
289 {RTL_USB_DEVICE(0x7392, 0x7811, rtl92cu_hal_cfg)}, /*Edimax - Edimax*/
290 {RTL_USB_DEVICE(0x3358, 0x13d3, rtl92cu_hal_cfg)}, /*Azwave 8188CE-VAU*/
291 /* Russian customer -Azwave (8188CE-VAU b/g mode only) */
292 {RTL_USB_DEVICE(0x3359, 0x13d3, rtl92cu_hal_cfg)},
293
294 /****** 8192CU ********/
295 {RTL_USB_DEVICE(0x0586, 0x341f, rtl92cu_hal_cfg)}, /*Zyxel -Abocom*/
296 {RTL_USB_DEVICE(0x07aa, 0x0056, rtl92cu_hal_cfg)}, /*ATKK-Gemtek*/
297 {RTL_USB_DEVICE(0x07b8, 0x8178, rtl92cu_hal_cfg)}, /*Funai -Abocom*/
298 {RTL_USB_DEVICE(0x07b8, 0x8178, rtl92cu_hal_cfg)}, /*Abocom -Abocom*/
299 {RTL_USB_DEVICE(0x2001, 0x3307, rtl92cu_hal_cfg)}, /*D-Link-Cameo*/
300 {RTL_USB_DEVICE(0x2001, 0x3309, rtl92cu_hal_cfg)}, /*D-Link-Alpha*/
301 {RTL_USB_DEVICE(0x2001, 0x330a, rtl92cu_hal_cfg)}, /*D-Link-Alpha*/
302 {RTL_USB_DEVICE(0x2019, 0xab2b, rtl92cu_hal_cfg)}, /*Planex -Abocom*/
303 {RTL_USB_DEVICE(0x7392, 0x7822, rtl92cu_hal_cfg)}, /*Edimax -Edimax*/
304 {}
305};
306
307MODULE_DEVICE_TABLE(usb, rtl8192c_usb_ids);
308
309static struct usb_driver rtl8192cu_driver = {
310 .name = "rtl8192cu",
311 .probe = rtl_usb_probe,
312 .disconnect = rtl_usb_disconnect,
313 .id_table = rtl8192c_usb_ids,
314
315#ifdef CONFIG_PM
316 /* .suspend = rtl_usb_suspend, */
317 /* .resume = rtl_usb_resume, */
318 /* .reset_resume = rtl8192c_resume, */
319#endif /* CONFIG_PM */
320#ifdef CONFIG_AUTOSUSPEND
321 .supports_autosuspend = 1,
322#endif
323};
324
325static int __init rtl8192cu_init(void)
326{
327 return usb_register(&rtl8192cu_driver);
328}
329
330static void __exit rtl8192cu_exit(void)
331{
332 usb_deregister(&rtl8192cu_driver);
333}
334
335module_init(rtl8192cu_init);
336module_exit(rtl8192cu_exit);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
new file mode 100644
index 000000000000..43b1177924ab
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
@@ -0,0 +1,53 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CU_SW_H__
31#define __RTL92CU_SW_H__
32
33#define EFUSE_MAX_SECTION 16
34
35void rtl92cu_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
36 u8 *powerlevel);
37void rtl92cu_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
38 u8 *ppowerlevel, u8 channel);
39bool _rtl92cu_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
40 u8 configtype);
41bool _rtl92cu_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
42 u8 configtype);
43void _rtl92cu_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t);
44void rtl92cu_phy_set_rf_reg(struct ieee80211_hw *hw,
45 enum radio_path rfpath,
46 u32 regaddr, u32 bitmask, u32 data);
47bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
48 enum rf_pwrstate rfpwr_state);
49u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
50 enum radio_path rfpath, u32 regaddr, u32 bitmask);
51void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
52
53#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/table.c b/drivers/net/wireless/rtlwifi/rtl8192cu/table.c
new file mode 100644
index 000000000000..d57ef5e88a9e
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/table.c
@@ -0,0 +1,1888 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "table.h"
31
32u32 RTL8192CUPHY_REG_2TARRAY[RTL8192CUPHY_REG_2TARRAY_LENGTH] = {
33 0x024, 0x0011800f,
34 0x028, 0x00ffdb83,
35 0x800, 0x80040002,
36 0x804, 0x00000003,
37 0x808, 0x0000fc00,
38 0x80c, 0x0000000a,
39 0x810, 0x10005388,
40 0x814, 0x020c3d10,
41 0x818, 0x02200385,
42 0x81c, 0x00000000,
43 0x820, 0x01000100,
44 0x824, 0x00390004,
45 0x828, 0x01000100,
46 0x82c, 0x00390004,
47 0x830, 0x27272727,
48 0x834, 0x27272727,
49 0x838, 0x27272727,
50 0x83c, 0x27272727,
51 0x840, 0x00010000,
52 0x844, 0x00010000,
53 0x848, 0x27272727,
54 0x84c, 0x27272727,
55 0x850, 0x00000000,
56 0x854, 0x00000000,
57 0x858, 0x569a569a,
58 0x85c, 0x0c1b25a4,
59 0x860, 0x66e60230,
60 0x864, 0x061f0130,
61 0x868, 0x27272727,
62 0x86c, 0x2b2b2b27,
63 0x870, 0x07000700,
64 0x874, 0x22184000,
65 0x878, 0x08080808,
66 0x87c, 0x00000000,
67 0x880, 0xc0083070,
68 0x884, 0x000004d5,
69 0x888, 0x00000000,
70 0x88c, 0xcc0000c0,
71 0x890, 0x00000800,
72 0x894, 0xfffffffe,
73 0x898, 0x40302010,
74 0x89c, 0x00706050,
75 0x900, 0x00000000,
76 0x904, 0x00000023,
77 0x908, 0x00000000,
78 0x90c, 0x81121313,
79 0xa00, 0x00d047c8,
80 0xa04, 0x80ff000c,
81 0xa08, 0x8c838300,
82 0xa0c, 0x2e68120f,
83 0xa10, 0x9500bb78,
84 0xa14, 0x11144028,
85 0xa18, 0x00881117,
86 0xa1c, 0x89140f00,
87 0xa20, 0x1a1b0000,
88 0xa24, 0x090e1317,
89 0xa28, 0x00000204,
90 0xa2c, 0x00d30000,
91 0xa70, 0x101fbf00,
92 0xa74, 0x00000007,
93 0xc00, 0x48071d40,
94 0xc04, 0x03a05633,
95 0xc08, 0x000000e4,
96 0xc0c, 0x6c6c6c6c,
97 0xc10, 0x08800000,
98 0xc14, 0x40000100,
99 0xc18, 0x08800000,
100 0xc1c, 0x40000100,
101 0xc20, 0x00000000,
102 0xc24, 0x00000000,
103 0xc28, 0x00000000,
104 0xc2c, 0x00000000,
105 0xc30, 0x69e9ac44,
106 0xc34, 0x469652cf,
107 0xc38, 0x49795994,
108 0xc3c, 0x0a97971c,
109 0xc40, 0x1f7c403f,
110 0xc44, 0x000100b7,
111 0xc48, 0xec020107,
112 0xc4c, 0x007f037f,
113 0xc50, 0x6954341e,
114 0xc54, 0x43bc0094,
115 0xc58, 0x6954341e,
116 0xc5c, 0x433c0094,
117 0xc60, 0x00000000,
118 0xc64, 0x5116848b,
119 0xc68, 0x47c00bff,
120 0xc6c, 0x00000036,
121 0xc70, 0x2c7f000d,
122 0xc74, 0x0186115b,
123 0xc78, 0x0000001f,
124 0xc7c, 0x00b99612,
125 0xc80, 0x40000100,
126 0xc84, 0x20f60000,
127 0xc88, 0x40000100,
128 0xc8c, 0x20200000,
129 0xc90, 0x00121820,
130 0xc94, 0x00000000,
131 0xc98, 0x00121820,
132 0xc9c, 0x00007f7f,
133 0xca0, 0x00000000,
134 0xca4, 0x00000080,
135 0xca8, 0x00000000,
136 0xcac, 0x00000000,
137 0xcb0, 0x00000000,
138 0xcb4, 0x00000000,
139 0xcb8, 0x00000000,
140 0xcbc, 0x28000000,
141 0xcc0, 0x00000000,
142 0xcc4, 0x00000000,
143 0xcc8, 0x00000000,
144 0xccc, 0x00000000,
145 0xcd0, 0x00000000,
146 0xcd4, 0x00000000,
147 0xcd8, 0x64b22427,
148 0xcdc, 0x00766932,
149 0xce0, 0x00222222,
150 0xce4, 0x00000000,
151 0xce8, 0x37644302,
152 0xcec, 0x2f97d40c,
153 0xd00, 0x00080740,
154 0xd04, 0x00020403,
155 0xd08, 0x0000907f,
156 0xd0c, 0x20010201,
157 0xd10, 0xa0633333,
158 0xd14, 0x3333bc43,
159 0xd18, 0x7a8f5b6b,
160 0xd2c, 0xcc979975,
161 0xd30, 0x00000000,
162 0xd34, 0x80608000,
163 0xd38, 0x00000000,
164 0xd3c, 0x00027293,
165 0xd40, 0x00000000,
166 0xd44, 0x00000000,
167 0xd48, 0x00000000,
168 0xd4c, 0x00000000,
169 0xd50, 0x6437140a,
170 0xd54, 0x00000000,
171 0xd58, 0x00000000,
172 0xd5c, 0x30032064,
173 0xd60, 0x4653de68,
174 0xd64, 0x04518a3c,
175 0xd68, 0x00002101,
176 0xd6c, 0x2a201c16,
177 0xd70, 0x1812362e,
178 0xd74, 0x322c2220,
179 0xd78, 0x000e3c24,
180 0xe00, 0x2a2a2a2a,
181 0xe04, 0x2a2a2a2a,
182 0xe08, 0x03902a2a,
183 0xe10, 0x2a2a2a2a,
184 0xe14, 0x2a2a2a2a,
185 0xe18, 0x2a2a2a2a,
186 0xe1c, 0x2a2a2a2a,
187 0xe28, 0x00000000,
188 0xe30, 0x1000dc1f,
189 0xe34, 0x10008c1f,
190 0xe38, 0x02140102,
191 0xe3c, 0x681604c2,
192 0xe40, 0x01007c00,
193 0xe44, 0x01004800,
194 0xe48, 0xfb000000,
195 0xe4c, 0x000028d1,
196 0xe50, 0x1000dc1f,
197 0xe54, 0x10008c1f,
198 0xe58, 0x02140102,
199 0xe5c, 0x28160d05,
200 0xe60, 0x00000010,
201 0xe68, 0x001b25a4,
202 0xe6c, 0x63db25a4,
203 0xe70, 0x63db25a4,
204 0xe74, 0x0c1b25a4,
205 0xe78, 0x0c1b25a4,
206 0xe7c, 0x0c1b25a4,
207 0xe80, 0x0c1b25a4,
208 0xe84, 0x63db25a4,
209 0xe88, 0x0c1b25a4,
210 0xe8c, 0x63db25a4,
211 0xed0, 0x63db25a4,
212 0xed4, 0x63db25a4,
213 0xed8, 0x63db25a4,
214 0xedc, 0x001b25a4,
215 0xee0, 0x001b25a4,
216 0xeec, 0x6fdb25a4,
217 0xf14, 0x00000003,
218 0xf4c, 0x00000000,
219 0xf00, 0x00000300,
220};
221
222u32 RTL8192CUPHY_REG_1TARRAY[RTL8192CUPHY_REG_1TARRAY_LENGTH] = {
223 0x024, 0x0011800f,
224 0x028, 0x00ffdb83,
225 0x800, 0x80040000,
226 0x804, 0x00000001,
227 0x808, 0x0000fc00,
228 0x80c, 0x0000000a,
229 0x810, 0x10005388,
230 0x814, 0x020c3d10,
231 0x818, 0x02200385,
232 0x81c, 0x00000000,
233 0x820, 0x01000100,
234 0x824, 0x00390004,
235 0x828, 0x00000000,
236 0x82c, 0x00000000,
237 0x830, 0x00000000,
238 0x834, 0x00000000,
239 0x838, 0x00000000,
240 0x83c, 0x00000000,
241 0x840, 0x00010000,
242 0x844, 0x00000000,
243 0x848, 0x00000000,
244 0x84c, 0x00000000,
245 0x850, 0x00000000,
246 0x854, 0x00000000,
247 0x858, 0x569a569a,
248 0x85c, 0x001b25a4,
249 0x860, 0x66e60230,
250 0x864, 0x061f0130,
251 0x868, 0x00000000,
252 0x86c, 0x32323200,
253 0x870, 0x07000700,
254 0x874, 0x22004000,
255 0x878, 0x00000808,
256 0x87c, 0x00000000,
257 0x880, 0xc0083070,
258 0x884, 0x000004d5,
259 0x888, 0x00000000,
260 0x88c, 0xccc000c0,
261 0x890, 0x00000800,
262 0x894, 0xfffffffe,
263 0x898, 0x40302010,
264 0x89c, 0x00706050,
265 0x900, 0x00000000,
266 0x904, 0x00000023,
267 0x908, 0x00000000,
268 0x90c, 0x81121111,
269 0xa00, 0x00d047c8,
270 0xa04, 0x80ff000c,
271 0xa08, 0x8c838300,
272 0xa0c, 0x2e68120f,
273 0xa10, 0x9500bb78,
274 0xa14, 0x11144028,
275 0xa18, 0x00881117,
276 0xa1c, 0x89140f00,
277 0xa20, 0x1a1b0000,
278 0xa24, 0x090e1317,
279 0xa28, 0x00000204,
280 0xa2c, 0x00d30000,
281 0xa70, 0x101fbf00,
282 0xa74, 0x00000007,
283 0xc00, 0x48071d40,
284 0xc04, 0x03a05611,
285 0xc08, 0x000000e4,
286 0xc0c, 0x6c6c6c6c,
287 0xc10, 0x08800000,
288 0xc14, 0x40000100,
289 0xc18, 0x08800000,
290 0xc1c, 0x40000100,
291 0xc20, 0x00000000,
292 0xc24, 0x00000000,
293 0xc28, 0x00000000,
294 0xc2c, 0x00000000,
295 0xc30, 0x69e9ac44,
296 0xc34, 0x469652cf,
297 0xc38, 0x49795994,
298 0xc3c, 0x0a97971c,
299 0xc40, 0x1f7c403f,
300 0xc44, 0x000100b7,
301 0xc48, 0xec020107,
302 0xc4c, 0x007f037f,
303 0xc50, 0x6954341e,
304 0xc54, 0x43bc0094,
305 0xc58, 0x6954341e,
306 0xc5c, 0x433c0094,
307 0xc60, 0x00000000,
308 0xc64, 0x5116848b,
309 0xc68, 0x47c00bff,
310 0xc6c, 0x00000036,
311 0xc70, 0x2c7f000d,
312 0xc74, 0x018610db,
313 0xc78, 0x0000001f,
314 0xc7c, 0x00b91612,
315 0xc80, 0x40000100,
316 0xc84, 0x20f60000,
317 0xc88, 0x40000100,
318 0xc8c, 0x20200000,
319 0xc90, 0x00121820,
320 0xc94, 0x00000000,
321 0xc98, 0x00121820,
322 0xc9c, 0x00007f7f,
323 0xca0, 0x00000000,
324 0xca4, 0x00000080,
325 0xca8, 0x00000000,
326 0xcac, 0x00000000,
327 0xcb0, 0x00000000,
328 0xcb4, 0x00000000,
329 0xcb8, 0x00000000,
330 0xcbc, 0x28000000,
331 0xcc0, 0x00000000,
332 0xcc4, 0x00000000,
333 0xcc8, 0x00000000,
334 0xccc, 0x00000000,
335 0xcd0, 0x00000000,
336 0xcd4, 0x00000000,
337 0xcd8, 0x64b22427,
338 0xcdc, 0x00766932,
339 0xce0, 0x00222222,
340 0xce4, 0x00000000,
341 0xce8, 0x37644302,
342 0xcec, 0x2f97d40c,
343 0xd00, 0x00080740,
344 0xd04, 0x00020401,
345 0xd08, 0x0000907f,
346 0xd0c, 0x20010201,
347 0xd10, 0xa0633333,
348 0xd14, 0x3333bc43,
349 0xd18, 0x7a8f5b6b,
350 0xd2c, 0xcc979975,
351 0xd30, 0x00000000,
352 0xd34, 0x80608000,
353 0xd38, 0x00000000,
354 0xd3c, 0x00027293,
355 0xd40, 0x00000000,
356 0xd44, 0x00000000,
357 0xd48, 0x00000000,
358 0xd4c, 0x00000000,
359 0xd50, 0x6437140a,
360 0xd54, 0x00000000,
361 0xd58, 0x00000000,
362 0xd5c, 0x30032064,
363 0xd60, 0x4653de68,
364 0xd64, 0x04518a3c,
365 0xd68, 0x00002101,
366 0xd6c, 0x2a201c16,
367 0xd70, 0x1812362e,
368 0xd74, 0x322c2220,
369 0xd78, 0x000e3c24,
370 0xe00, 0x2a2a2a2a,
371 0xe04, 0x2a2a2a2a,
372 0xe08, 0x03902a2a,
373 0xe10, 0x2a2a2a2a,
374 0xe14, 0x2a2a2a2a,
375 0xe18, 0x2a2a2a2a,
376 0xe1c, 0x2a2a2a2a,
377 0xe28, 0x00000000,
378 0xe30, 0x1000dc1f,
379 0xe34, 0x10008c1f,
380 0xe38, 0x02140102,
381 0xe3c, 0x681604c2,
382 0xe40, 0x01007c00,
383 0xe44, 0x01004800,
384 0xe48, 0xfb000000,
385 0xe4c, 0x000028d1,
386 0xe50, 0x1000dc1f,
387 0xe54, 0x10008c1f,
388 0xe58, 0x02140102,
389 0xe5c, 0x28160d05,
390 0xe60, 0x00000008,
391 0xe68, 0x001b25a4,
392 0xe6c, 0x631b25a0,
393 0xe70, 0x631b25a0,
394 0xe74, 0x081b25a0,
395 0xe78, 0x081b25a0,
396 0xe7c, 0x081b25a0,
397 0xe80, 0x081b25a0,
398 0xe84, 0x631b25a0,
399 0xe88, 0x081b25a0,
400 0xe8c, 0x631b25a0,
401 0xed0, 0x631b25a0,
402 0xed4, 0x631b25a0,
403 0xed8, 0x631b25a0,
404 0xedc, 0x001b25a0,
405 0xee0, 0x001b25a0,
406 0xeec, 0x6b1b25a0,
407 0xf14, 0x00000003,
408 0xf4c, 0x00000000,
409 0xf00, 0x00000300,
410};
411
412u32 RTL8192CUPHY_REG_ARRAY_PG[RTL8192CUPHY_REG_ARRAY_PGLENGTH] = {
413 0xe00, 0xffffffff, 0x07090c0c,
414 0xe04, 0xffffffff, 0x01020405,
415 0xe08, 0x0000ff00, 0x00000000,
416 0x86c, 0xffffff00, 0x00000000,
417 0xe10, 0xffffffff, 0x0b0c0c0e,
418 0xe14, 0xffffffff, 0x01030506,
419 0xe18, 0xffffffff, 0x0b0c0d0e,
420 0xe1c, 0xffffffff, 0x01030509,
421 0x830, 0xffffffff, 0x07090c0c,
422 0x834, 0xffffffff, 0x01020405,
423 0x838, 0xffffff00, 0x00000000,
424 0x86c, 0x000000ff, 0x00000000,
425 0x83c, 0xffffffff, 0x0b0c0d0e,
426 0x848, 0xffffffff, 0x01030509,
427 0x84c, 0xffffffff, 0x0b0c0d0e,
428 0x868, 0xffffffff, 0x01030509,
429 0xe00, 0xffffffff, 0x00000000,
430 0xe04, 0xffffffff, 0x00000000,
431 0xe08, 0x0000ff00, 0x00000000,
432 0x86c, 0xffffff00, 0x00000000,
433 0xe10, 0xffffffff, 0x00000000,
434 0xe14, 0xffffffff, 0x00000000,
435 0xe18, 0xffffffff, 0x00000000,
436 0xe1c, 0xffffffff, 0x00000000,
437 0x830, 0xffffffff, 0x00000000,
438 0x834, 0xffffffff, 0x00000000,
439 0x838, 0xffffff00, 0x00000000,
440 0x86c, 0x000000ff, 0x00000000,
441 0x83c, 0xffffffff, 0x00000000,
442 0x848, 0xffffffff, 0x00000000,
443 0x84c, 0xffffffff, 0x00000000,
444 0x868, 0xffffffff, 0x00000000,
445 0xe00, 0xffffffff, 0x04040404,
446 0xe04, 0xffffffff, 0x00020204,
447 0xe08, 0x0000ff00, 0x00000000,
448 0x86c, 0xffffff00, 0x00000000,
449 0xe10, 0xffffffff, 0x06060606,
450 0xe14, 0xffffffff, 0x00020406,
451 0xe18, 0xffffffff, 0x00000000,
452 0xe1c, 0xffffffff, 0x00000000,
453 0x830, 0xffffffff, 0x04040404,
454 0x834, 0xffffffff, 0x00020204,
455 0x838, 0xffffff00, 0x00000000,
456 0x86c, 0x000000ff, 0x00000000,
457 0x83c, 0xffffffff, 0x06060606,
458 0x848, 0xffffffff, 0x00020406,
459 0x84c, 0xffffffff, 0x00000000,
460 0x868, 0xffffffff, 0x00000000,
461 0xe00, 0xffffffff, 0x00000000,
462 0xe04, 0xffffffff, 0x00000000,
463 0xe08, 0x0000ff00, 0x00000000,
464 0x86c, 0xffffff00, 0x00000000,
465 0xe10, 0xffffffff, 0x00000000,
466 0xe14, 0xffffffff, 0x00000000,
467 0xe18, 0xffffffff, 0x00000000,
468 0xe1c, 0xffffffff, 0x00000000,
469 0x830, 0xffffffff, 0x00000000,
470 0x834, 0xffffffff, 0x00000000,
471 0x838, 0xffffff00, 0x00000000,
472 0x86c, 0x000000ff, 0x00000000,
473 0x83c, 0xffffffff, 0x00000000,
474 0x848, 0xffffffff, 0x00000000,
475 0x84c, 0xffffffff, 0x00000000,
476 0x868, 0xffffffff, 0x00000000,
477 0xe00, 0xffffffff, 0x00000000,
478 0xe04, 0xffffffff, 0x00000000,
479 0xe08, 0x0000ff00, 0x00000000,
480 0x86c, 0xffffff00, 0x00000000,
481 0xe10, 0xffffffff, 0x00000000,
482 0xe14, 0xffffffff, 0x00000000,
483 0xe18, 0xffffffff, 0x00000000,
484 0xe1c, 0xffffffff, 0x00000000,
485 0x830, 0xffffffff, 0x00000000,
486 0x834, 0xffffffff, 0x00000000,
487 0x838, 0xffffff00, 0x00000000,
488 0x86c, 0x000000ff, 0x00000000,
489 0x83c, 0xffffffff, 0x00000000,
490 0x848, 0xffffffff, 0x00000000,
491 0x84c, 0xffffffff, 0x00000000,
492 0x868, 0xffffffff, 0x00000000,
493 0xe00, 0xffffffff, 0x04040404,
494 0xe04, 0xffffffff, 0x00020204,
495 0xe08, 0x0000ff00, 0x00000000,
496 0x86c, 0xffffff00, 0x00000000,
497 0xe10, 0xffffffff, 0x00000000,
498 0xe14, 0xffffffff, 0x00000000,
499 0xe18, 0xffffffff, 0x00000000,
500 0xe1c, 0xffffffff, 0x00000000,
501 0x830, 0xffffffff, 0x04040404,
502 0x834, 0xffffffff, 0x00020204,
503 0x838, 0xffffff00, 0x00000000,
504 0x86c, 0x000000ff, 0x00000000,
505 0x83c, 0xffffffff, 0x00000000,
506 0x848, 0xffffffff, 0x00000000,
507 0x84c, 0xffffffff, 0x00000000,
508 0x868, 0xffffffff, 0x00000000,
509 0xe00, 0xffffffff, 0x00000000,
510 0xe04, 0xffffffff, 0x00000000,
511 0xe08, 0x0000ff00, 0x00000000,
512 0x86c, 0xffffff00, 0x00000000,
513 0xe10, 0xffffffff, 0x00000000,
514 0xe14, 0xffffffff, 0x00000000,
515 0xe18, 0xffffffff, 0x00000000,
516 0xe1c, 0xffffffff, 0x00000000,
517 0x830, 0xffffffff, 0x00000000,
518 0x834, 0xffffffff, 0x00000000,
519 0x838, 0xffffff00, 0x00000000,
520 0x86c, 0x000000ff, 0x00000000,
521 0x83c, 0xffffffff, 0x00000000,
522 0x848, 0xffffffff, 0x00000000,
523 0x84c, 0xffffffff, 0x00000000,
524 0x868, 0xffffffff, 0x00000000,
525};
526
527u32 RTL8192CURADIOA_2TARRAY[RTL8192CURADIOA_2TARRAYLENGTH] = {
528 0x000, 0x00030159,
529 0x001, 0x00031284,
530 0x002, 0x00098000,
531 0x003, 0x00018c63,
532 0x004, 0x000210e7,
533 0x009, 0x0002044f,
534 0x00a, 0x0001adb1,
535 0x00b, 0x00054867,
536 0x00c, 0x0008992e,
537 0x00d, 0x0000e52c,
538 0x00e, 0x00039ce7,
539 0x00f, 0x00000451,
540 0x019, 0x00000000,
541 0x01a, 0x00010255,
542 0x01b, 0x00060a00,
543 0x01c, 0x000fc378,
544 0x01d, 0x000a1250,
545 0x01e, 0x0004445f,
546 0x01f, 0x00080001,
547 0x020, 0x0000b614,
548 0x021, 0x0006c000,
549 0x022, 0x00000000,
550 0x023, 0x00001558,
551 0x024, 0x00000060,
552 0x025, 0x00000483,
553 0x026, 0x0004f000,
554 0x027, 0x000ec7d9,
555 0x028, 0x000577c0,
556 0x029, 0x00004783,
557 0x02a, 0x00000001,
558 0x02b, 0x00021334,
559 0x02a, 0x00000000,
560 0x02b, 0x00000054,
561 0x02a, 0x00000001,
562 0x02b, 0x00000808,
563 0x02b, 0x00053333,
564 0x02c, 0x0000000c,
565 0x02a, 0x00000002,
566 0x02b, 0x00000808,
567 0x02b, 0x0005b333,
568 0x02c, 0x0000000d,
569 0x02a, 0x00000003,
570 0x02b, 0x00000808,
571 0x02b, 0x00063333,
572 0x02c, 0x0000000d,
573 0x02a, 0x00000004,
574 0x02b, 0x00000808,
575 0x02b, 0x0006b333,
576 0x02c, 0x0000000d,
577 0x02a, 0x00000005,
578 0x02b, 0x00000808,
579 0x02b, 0x00073333,
580 0x02c, 0x0000000d,
581 0x02a, 0x00000006,
582 0x02b, 0x00000709,
583 0x02b, 0x0005b333,
584 0x02c, 0x0000000d,
585 0x02a, 0x00000007,
586 0x02b, 0x00000709,
587 0x02b, 0x00063333,
588 0x02c, 0x0000000d,
589 0x02a, 0x00000008,
590 0x02b, 0x0000060a,
591 0x02b, 0x0004b333,
592 0x02c, 0x0000000d,
593 0x02a, 0x00000009,
594 0x02b, 0x0000060a,
595 0x02b, 0x00053333,
596 0x02c, 0x0000000d,
597 0x02a, 0x0000000a,
598 0x02b, 0x0000060a,
599 0x02b, 0x0005b333,
600 0x02c, 0x0000000d,
601 0x02a, 0x0000000b,
602 0x02b, 0x0000060a,
603 0x02b, 0x00063333,
604 0x02c, 0x0000000d,
605 0x02a, 0x0000000c,
606 0x02b, 0x0000060a,
607 0x02b, 0x0006b333,
608 0x02c, 0x0000000d,
609 0x02a, 0x0000000d,
610 0x02b, 0x0000060a,
611 0x02b, 0x00073333,
612 0x02c, 0x0000000d,
613 0x02a, 0x0000000e,
614 0x02b, 0x0000050b,
615 0x02b, 0x00066666,
616 0x02c, 0x0000001a,
617 0x02a, 0x000e0000,
618 0x010, 0x0004000f,
619 0x011, 0x000e31fc,
620 0x010, 0x0006000f,
621 0x011, 0x000ff9f8,
622 0x010, 0x0002000f,
623 0x011, 0x000203f9,
624 0x010, 0x0003000f,
625 0x011, 0x000ff500,
626 0x010, 0x00000000,
627 0x011, 0x00000000,
628 0x010, 0x0008000f,
629 0x011, 0x0003f100,
630 0x010, 0x0009000f,
631 0x011, 0x00023100,
632 0x012, 0x00032000,
633 0x012, 0x00071000,
634 0x012, 0x000b0000,
635 0x012, 0x000fc000,
636 0x013, 0x000287af,
637 0x013, 0x000244b7,
638 0x013, 0x000204ab,
639 0x013, 0x0001c49f,
640 0x013, 0x00018493,
641 0x013, 0x00014297,
642 0x013, 0x00010295,
643 0x013, 0x0000c298,
644 0x013, 0x0000819c,
645 0x013, 0x000040a8,
646 0x013, 0x0000001c,
647 0x014, 0x0001944c,
648 0x014, 0x00059444,
649 0x014, 0x0009944c,
650 0x014, 0x000d9444,
651 0x015, 0x0000f424,
652 0x015, 0x0004f424,
653 0x015, 0x0008f424,
654 0x015, 0x000cf424,
655 0x016, 0x000e0330,
656 0x016, 0x000a0330,
657 0x016, 0x00060330,
658 0x016, 0x00020330,
659 0x000, 0x00010159,
660 0x018, 0x0000f401,
661 0x0fe, 0x00000000,
662 0x0fe, 0x00000000,
663 0x01f, 0x00080003,
664 0x0fe, 0x00000000,
665 0x0fe, 0x00000000,
666 0x01e, 0x00044457,
667 0x01f, 0x00080000,
668 0x000, 0x00030159,
669};
670
671u32 RTL8192CU_RADIOB_2TARRAY[RTL8192CURADIOB_2TARRAYLENGTH] = {
672 0x000, 0x00030159,
673 0x001, 0x00031284,
674 0x002, 0x00098000,
675 0x003, 0x00018c63,
676 0x004, 0x000210e7,
677 0x009, 0x0002044f,
678 0x00a, 0x0001adb1,
679 0x00b, 0x00054867,
680 0x00c, 0x0008992e,
681 0x00d, 0x0000e52c,
682 0x00e, 0x00039ce7,
683 0x00f, 0x00000451,
684 0x012, 0x00032000,
685 0x012, 0x00071000,
686 0x012, 0x000b0000,
687 0x012, 0x000fc000,
688 0x013, 0x000287af,
689 0x013, 0x000244b7,
690 0x013, 0x000204ab,
691 0x013, 0x0001c49f,
692 0x013, 0x00018493,
693 0x013, 0x00014297,
694 0x013, 0x00010295,
695 0x013, 0x0000c298,
696 0x013, 0x0000819c,
697 0x013, 0x000040a8,
698 0x013, 0x0000001c,
699 0x014, 0x0001944c,
700 0x014, 0x00059444,
701 0x014, 0x0009944c,
702 0x014, 0x000d9444,
703 0x015, 0x0000f424,
704 0x015, 0x0004f424,
705 0x015, 0x0008f424,
706 0x015, 0x000cf424,
707 0x016, 0x000e0330,
708 0x016, 0x000a0330,
709 0x016, 0x00060330,
710 0x016, 0x00020330,
711};
712
713u32 RTL8192CU_RADIOA_1TARRAY[RTL8192CURADIOA_1TARRAYLENGTH] = {
714 0x000, 0x00030159,
715 0x001, 0x00031284,
716 0x002, 0x00098000,
717 0x003, 0x00018c63,
718 0x004, 0x000210e7,
719 0x009, 0x0002044f,
720 0x00a, 0x0001adb1,
721 0x00b, 0x00054867,
722 0x00c, 0x0008992e,
723 0x00d, 0x0000e52c,
724 0x00e, 0x00039ce7,
725 0x00f, 0x00000451,
726 0x019, 0x00000000,
727 0x01a, 0x00010255,
728 0x01b, 0x00060a00,
729 0x01c, 0x000fc378,
730 0x01d, 0x000a1250,
731 0x01e, 0x0004445f,
732 0x01f, 0x00080001,
733 0x020, 0x0000b614,
734 0x021, 0x0006c000,
735 0x022, 0x00000000,
736 0x023, 0x00001558,
737 0x024, 0x00000060,
738 0x025, 0x00000483,
739 0x026, 0x0004f000,
740 0x027, 0x000ec7d9,
741 0x028, 0x000577c0,
742 0x029, 0x00004783,
743 0x02a, 0x00000001,
744 0x02b, 0x00021334,
745 0x02a, 0x00000000,
746 0x02b, 0x00000054,
747 0x02a, 0x00000001,
748 0x02b, 0x00000808,
749 0x02b, 0x00053333,
750 0x02c, 0x0000000c,
751 0x02a, 0x00000002,
752 0x02b, 0x00000808,
753 0x02b, 0x0005b333,
754 0x02c, 0x0000000d,
755 0x02a, 0x00000003,
756 0x02b, 0x00000808,
757 0x02b, 0x00063333,
758 0x02c, 0x0000000d,
759 0x02a, 0x00000004,
760 0x02b, 0x00000808,
761 0x02b, 0x0006b333,
762 0x02c, 0x0000000d,
763 0x02a, 0x00000005,
764 0x02b, 0x00000808,
765 0x02b, 0x00073333,
766 0x02c, 0x0000000d,
767 0x02a, 0x00000006,
768 0x02b, 0x00000709,
769 0x02b, 0x0005b333,
770 0x02c, 0x0000000d,
771 0x02a, 0x00000007,
772 0x02b, 0x00000709,
773 0x02b, 0x00063333,
774 0x02c, 0x0000000d,
775 0x02a, 0x00000008,
776 0x02b, 0x0000060a,
777 0x02b, 0x0004b333,
778 0x02c, 0x0000000d,
779 0x02a, 0x00000009,
780 0x02b, 0x0000060a,
781 0x02b, 0x00053333,
782 0x02c, 0x0000000d,
783 0x02a, 0x0000000a,
784 0x02b, 0x0000060a,
785 0x02b, 0x0005b333,
786 0x02c, 0x0000000d,
787 0x02a, 0x0000000b,
788 0x02b, 0x0000060a,
789 0x02b, 0x00063333,
790 0x02c, 0x0000000d,
791 0x02a, 0x0000000c,
792 0x02b, 0x0000060a,
793 0x02b, 0x0006b333,
794 0x02c, 0x0000000d,
795 0x02a, 0x0000000d,
796 0x02b, 0x0000060a,
797 0x02b, 0x00073333,
798 0x02c, 0x0000000d,
799 0x02a, 0x0000000e,
800 0x02b, 0x0000050b,
801 0x02b, 0x00066666,
802 0x02c, 0x0000001a,
803 0x02a, 0x000e0000,
804 0x010, 0x0004000f,
805 0x011, 0x000e31fc,
806 0x010, 0x0006000f,
807 0x011, 0x000ff9f8,
808 0x010, 0x0002000f,
809 0x011, 0x000203f9,
810 0x010, 0x0003000f,
811 0x011, 0x000ff500,
812 0x010, 0x00000000,
813 0x011, 0x00000000,
814 0x010, 0x0008000f,
815 0x011, 0x0003f100,
816 0x010, 0x0009000f,
817 0x011, 0x00023100,
818 0x012, 0x00032000,
819 0x012, 0x00071000,
820 0x012, 0x000b0000,
821 0x012, 0x000fc000,
822 0x013, 0x000287b3,
823 0x013, 0x000244b7,
824 0x013, 0x000204ab,
825 0x013, 0x0001c49f,
826 0x013, 0x00018493,
827 0x013, 0x0001429b,
828 0x013, 0x00010299,
829 0x013, 0x0000c29c,
830 0x013, 0x000081a0,
831 0x013, 0x000040ac,
832 0x013, 0x00000020,
833 0x014, 0x0001944c,
834 0x014, 0x00059444,
835 0x014, 0x0009944c,
836 0x014, 0x000d9444,
837 0x015, 0x0000f405,
838 0x015, 0x0004f405,
839 0x015, 0x0008f405,
840 0x015, 0x000cf405,
841 0x016, 0x000e0330,
842 0x016, 0x000a0330,
843 0x016, 0x00060330,
844 0x016, 0x00020330,
845 0x000, 0x00010159,
846 0x018, 0x0000f401,
847 0x0fe, 0x00000000,
848 0x0fe, 0x00000000,
849 0x01f, 0x00080003,
850 0x0fe, 0x00000000,
851 0x0fe, 0x00000000,
852 0x01e, 0x00044457,
853 0x01f, 0x00080000,
854 0x000, 0x00030159,
855};
856
857u32 RTL8192CU_RADIOB_1TARRAY[RTL8192CURADIOB_1TARRAYLENGTH] = {
858 0x0,
859};
860
861u32 RTL8192CUMAC_2T_ARRAY[RTL8192CUMAC_2T_ARRAYLENGTH] = {
862 0x420, 0x00000080,
863 0x423, 0x00000000,
864 0x430, 0x00000000,
865 0x431, 0x00000000,
866 0x432, 0x00000000,
867 0x433, 0x00000001,
868 0x434, 0x00000004,
869 0x435, 0x00000005,
870 0x436, 0x00000006,
871 0x437, 0x00000007,
872 0x438, 0x00000000,
873 0x439, 0x00000000,
874 0x43a, 0x00000000,
875 0x43b, 0x00000001,
876 0x43c, 0x00000004,
877 0x43d, 0x00000005,
878 0x43e, 0x00000006,
879 0x43f, 0x00000007,
880 0x440, 0x0000005d,
881 0x441, 0x00000001,
882 0x442, 0x00000000,
883 0x444, 0x00000015,
884 0x445, 0x000000f0,
885 0x446, 0x0000000f,
886 0x447, 0x00000000,
887 0x458, 0x00000041,
888 0x459, 0x000000a8,
889 0x45a, 0x00000072,
890 0x45b, 0x000000b9,
891 0x460, 0x00000066,
892 0x461, 0x00000066,
893 0x462, 0x00000008,
894 0x463, 0x00000003,
895 0x4c8, 0x000000ff,
896 0x4c9, 0x00000008,
897 0x4cc, 0x000000ff,
898 0x4cd, 0x000000ff,
899 0x4ce, 0x00000001,
900 0x500, 0x00000026,
901 0x501, 0x000000a2,
902 0x502, 0x0000002f,
903 0x503, 0x00000000,
904 0x504, 0x00000028,
905 0x505, 0x000000a3,
906 0x506, 0x0000005e,
907 0x507, 0x00000000,
908 0x508, 0x0000002b,
909 0x509, 0x000000a4,
910 0x50a, 0x0000005e,
911 0x50b, 0x00000000,
912 0x50c, 0x0000004f,
913 0x50d, 0x000000a4,
914 0x50e, 0x00000000,
915 0x50f, 0x00000000,
916 0x512, 0x0000001c,
917 0x514, 0x0000000a,
918 0x515, 0x00000010,
919 0x516, 0x0000000a,
920 0x517, 0x00000010,
921 0x51a, 0x00000016,
922 0x524, 0x0000000f,
923 0x525, 0x0000004f,
924 0x546, 0x00000040,
925 0x547, 0x00000000,
926 0x550, 0x00000010,
927 0x551, 0x00000010,
928 0x559, 0x00000002,
929 0x55a, 0x00000002,
930 0x55d, 0x000000ff,
931 0x605, 0x00000030,
932 0x608, 0x0000000e,
933 0x609, 0x0000002a,
934 0x652, 0x00000020,
935 0x63c, 0x0000000a,
936 0x63d, 0x0000000e,
937 0x63e, 0x0000000a,
938 0x63f, 0x0000000e,
939 0x66e, 0x00000005,
940 0x700, 0x00000021,
941 0x701, 0x00000043,
942 0x702, 0x00000065,
943 0x703, 0x00000087,
944 0x708, 0x00000021,
945 0x709, 0x00000043,
946 0x70a, 0x00000065,
947 0x70b, 0x00000087,
948};
949
950u32 RTL8192CUAGCTAB_2TARRAY[RTL8192CUAGCTAB_2TARRAYLENGTH] = {
951 0xc78, 0x7b000001,
952 0xc78, 0x7b010001,
953 0xc78, 0x7b020001,
954 0xc78, 0x7b030001,
955 0xc78, 0x7b040001,
956 0xc78, 0x7b050001,
957 0xc78, 0x7a060001,
958 0xc78, 0x79070001,
959 0xc78, 0x78080001,
960 0xc78, 0x77090001,
961 0xc78, 0x760a0001,
962 0xc78, 0x750b0001,
963 0xc78, 0x740c0001,
964 0xc78, 0x730d0001,
965 0xc78, 0x720e0001,
966 0xc78, 0x710f0001,
967 0xc78, 0x70100001,
968 0xc78, 0x6f110001,
969 0xc78, 0x6e120001,
970 0xc78, 0x6d130001,
971 0xc78, 0x6c140001,
972 0xc78, 0x6b150001,
973 0xc78, 0x6a160001,
974 0xc78, 0x69170001,
975 0xc78, 0x68180001,
976 0xc78, 0x67190001,
977 0xc78, 0x661a0001,
978 0xc78, 0x651b0001,
979 0xc78, 0x641c0001,
980 0xc78, 0x631d0001,
981 0xc78, 0x621e0001,
982 0xc78, 0x611f0001,
983 0xc78, 0x60200001,
984 0xc78, 0x49210001,
985 0xc78, 0x48220001,
986 0xc78, 0x47230001,
987 0xc78, 0x46240001,
988 0xc78, 0x45250001,
989 0xc78, 0x44260001,
990 0xc78, 0x43270001,
991 0xc78, 0x42280001,
992 0xc78, 0x41290001,
993 0xc78, 0x402a0001,
994 0xc78, 0x262b0001,
995 0xc78, 0x252c0001,
996 0xc78, 0x242d0001,
997 0xc78, 0x232e0001,
998 0xc78, 0x222f0001,
999 0xc78, 0x21300001,
1000 0xc78, 0x20310001,
1001 0xc78, 0x06320001,
1002 0xc78, 0x05330001,
1003 0xc78, 0x04340001,
1004 0xc78, 0x03350001,
1005 0xc78, 0x02360001,
1006 0xc78, 0x01370001,
1007 0xc78, 0x00380001,
1008 0xc78, 0x00390001,
1009 0xc78, 0x003a0001,
1010 0xc78, 0x003b0001,
1011 0xc78, 0x003c0001,
1012 0xc78, 0x003d0001,
1013 0xc78, 0x003e0001,
1014 0xc78, 0x003f0001,
1015 0xc78, 0x7b400001,
1016 0xc78, 0x7b410001,
1017 0xc78, 0x7b420001,
1018 0xc78, 0x7b430001,
1019 0xc78, 0x7b440001,
1020 0xc78, 0x7b450001,
1021 0xc78, 0x7a460001,
1022 0xc78, 0x79470001,
1023 0xc78, 0x78480001,
1024 0xc78, 0x77490001,
1025 0xc78, 0x764a0001,
1026 0xc78, 0x754b0001,
1027 0xc78, 0x744c0001,
1028 0xc78, 0x734d0001,
1029 0xc78, 0x724e0001,
1030 0xc78, 0x714f0001,
1031 0xc78, 0x70500001,
1032 0xc78, 0x6f510001,
1033 0xc78, 0x6e520001,
1034 0xc78, 0x6d530001,
1035 0xc78, 0x6c540001,
1036 0xc78, 0x6b550001,
1037 0xc78, 0x6a560001,
1038 0xc78, 0x69570001,
1039 0xc78, 0x68580001,
1040 0xc78, 0x67590001,
1041 0xc78, 0x665a0001,
1042 0xc78, 0x655b0001,
1043 0xc78, 0x645c0001,
1044 0xc78, 0x635d0001,
1045 0xc78, 0x625e0001,
1046 0xc78, 0x615f0001,
1047 0xc78, 0x60600001,
1048 0xc78, 0x49610001,
1049 0xc78, 0x48620001,
1050 0xc78, 0x47630001,
1051 0xc78, 0x46640001,
1052 0xc78, 0x45650001,
1053 0xc78, 0x44660001,
1054 0xc78, 0x43670001,
1055 0xc78, 0x42680001,
1056 0xc78, 0x41690001,
1057 0xc78, 0x406a0001,
1058 0xc78, 0x266b0001,
1059 0xc78, 0x256c0001,
1060 0xc78, 0x246d0001,
1061 0xc78, 0x236e0001,
1062 0xc78, 0x226f0001,
1063 0xc78, 0x21700001,
1064 0xc78, 0x20710001,
1065 0xc78, 0x06720001,
1066 0xc78, 0x05730001,
1067 0xc78, 0x04740001,
1068 0xc78, 0x03750001,
1069 0xc78, 0x02760001,
1070 0xc78, 0x01770001,
1071 0xc78, 0x00780001,
1072 0xc78, 0x00790001,
1073 0xc78, 0x007a0001,
1074 0xc78, 0x007b0001,
1075 0xc78, 0x007c0001,
1076 0xc78, 0x007d0001,
1077 0xc78, 0x007e0001,
1078 0xc78, 0x007f0001,
1079 0xc78, 0x3800001e,
1080 0xc78, 0x3801001e,
1081 0xc78, 0x3802001e,
1082 0xc78, 0x3803001e,
1083 0xc78, 0x3804001e,
1084 0xc78, 0x3805001e,
1085 0xc78, 0x3806001e,
1086 0xc78, 0x3807001e,
1087 0xc78, 0x3808001e,
1088 0xc78, 0x3c09001e,
1089 0xc78, 0x3e0a001e,
1090 0xc78, 0x400b001e,
1091 0xc78, 0x440c001e,
1092 0xc78, 0x480d001e,
1093 0xc78, 0x4c0e001e,
1094 0xc78, 0x500f001e,
1095 0xc78, 0x5210001e,
1096 0xc78, 0x5611001e,
1097 0xc78, 0x5a12001e,
1098 0xc78, 0x5e13001e,
1099 0xc78, 0x6014001e,
1100 0xc78, 0x6015001e,
1101 0xc78, 0x6016001e,
1102 0xc78, 0x6217001e,
1103 0xc78, 0x6218001e,
1104 0xc78, 0x6219001e,
1105 0xc78, 0x621a001e,
1106 0xc78, 0x621b001e,
1107 0xc78, 0x621c001e,
1108 0xc78, 0x621d001e,
1109 0xc78, 0x621e001e,
1110 0xc78, 0x621f001e,
1111};
1112
1113u32 RTL8192CUAGCTAB_1TARRAY[RTL8192CUAGCTAB_1TARRAYLENGTH] = {
1114 0xc78, 0x7b000001,
1115 0xc78, 0x7b010001,
1116 0xc78, 0x7b020001,
1117 0xc78, 0x7b030001,
1118 0xc78, 0x7b040001,
1119 0xc78, 0x7b050001,
1120 0xc78, 0x7a060001,
1121 0xc78, 0x79070001,
1122 0xc78, 0x78080001,
1123 0xc78, 0x77090001,
1124 0xc78, 0x760a0001,
1125 0xc78, 0x750b0001,
1126 0xc78, 0x740c0001,
1127 0xc78, 0x730d0001,
1128 0xc78, 0x720e0001,
1129 0xc78, 0x710f0001,
1130 0xc78, 0x70100001,
1131 0xc78, 0x6f110001,
1132 0xc78, 0x6e120001,
1133 0xc78, 0x6d130001,
1134 0xc78, 0x6c140001,
1135 0xc78, 0x6b150001,
1136 0xc78, 0x6a160001,
1137 0xc78, 0x69170001,
1138 0xc78, 0x68180001,
1139 0xc78, 0x67190001,
1140 0xc78, 0x661a0001,
1141 0xc78, 0x651b0001,
1142 0xc78, 0x641c0001,
1143 0xc78, 0x631d0001,
1144 0xc78, 0x621e0001,
1145 0xc78, 0x611f0001,
1146 0xc78, 0x60200001,
1147 0xc78, 0x49210001,
1148 0xc78, 0x48220001,
1149 0xc78, 0x47230001,
1150 0xc78, 0x46240001,
1151 0xc78, 0x45250001,
1152 0xc78, 0x44260001,
1153 0xc78, 0x43270001,
1154 0xc78, 0x42280001,
1155 0xc78, 0x41290001,
1156 0xc78, 0x402a0001,
1157 0xc78, 0x262b0001,
1158 0xc78, 0x252c0001,
1159 0xc78, 0x242d0001,
1160 0xc78, 0x232e0001,
1161 0xc78, 0x222f0001,
1162 0xc78, 0x21300001,
1163 0xc78, 0x20310001,
1164 0xc78, 0x06320001,
1165 0xc78, 0x05330001,
1166 0xc78, 0x04340001,
1167 0xc78, 0x03350001,
1168 0xc78, 0x02360001,
1169 0xc78, 0x01370001,
1170 0xc78, 0x00380001,
1171 0xc78, 0x00390001,
1172 0xc78, 0x003a0001,
1173 0xc78, 0x003b0001,
1174 0xc78, 0x003c0001,
1175 0xc78, 0x003d0001,
1176 0xc78, 0x003e0001,
1177 0xc78, 0x003f0001,
1178 0xc78, 0x7b400001,
1179 0xc78, 0x7b410001,
1180 0xc78, 0x7b420001,
1181 0xc78, 0x7b430001,
1182 0xc78, 0x7b440001,
1183 0xc78, 0x7b450001,
1184 0xc78, 0x7a460001,
1185 0xc78, 0x79470001,
1186 0xc78, 0x78480001,
1187 0xc78, 0x77490001,
1188 0xc78, 0x764a0001,
1189 0xc78, 0x754b0001,
1190 0xc78, 0x744c0001,
1191 0xc78, 0x734d0001,
1192 0xc78, 0x724e0001,
1193 0xc78, 0x714f0001,
1194 0xc78, 0x70500001,
1195 0xc78, 0x6f510001,
1196 0xc78, 0x6e520001,
1197 0xc78, 0x6d530001,
1198 0xc78, 0x6c540001,
1199 0xc78, 0x6b550001,
1200 0xc78, 0x6a560001,
1201 0xc78, 0x69570001,
1202 0xc78, 0x68580001,
1203 0xc78, 0x67590001,
1204 0xc78, 0x665a0001,
1205 0xc78, 0x655b0001,
1206 0xc78, 0x645c0001,
1207 0xc78, 0x635d0001,
1208 0xc78, 0x625e0001,
1209 0xc78, 0x615f0001,
1210 0xc78, 0x60600001,
1211 0xc78, 0x49610001,
1212 0xc78, 0x48620001,
1213 0xc78, 0x47630001,
1214 0xc78, 0x46640001,
1215 0xc78, 0x45650001,
1216 0xc78, 0x44660001,
1217 0xc78, 0x43670001,
1218 0xc78, 0x42680001,
1219 0xc78, 0x41690001,
1220 0xc78, 0x406a0001,
1221 0xc78, 0x266b0001,
1222 0xc78, 0x256c0001,
1223 0xc78, 0x246d0001,
1224 0xc78, 0x236e0001,
1225 0xc78, 0x226f0001,
1226 0xc78, 0x21700001,
1227 0xc78, 0x20710001,
1228 0xc78, 0x06720001,
1229 0xc78, 0x05730001,
1230 0xc78, 0x04740001,
1231 0xc78, 0x03750001,
1232 0xc78, 0x02760001,
1233 0xc78, 0x01770001,
1234 0xc78, 0x00780001,
1235 0xc78, 0x00790001,
1236 0xc78, 0x007a0001,
1237 0xc78, 0x007b0001,
1238 0xc78, 0x007c0001,
1239 0xc78, 0x007d0001,
1240 0xc78, 0x007e0001,
1241 0xc78, 0x007f0001,
1242 0xc78, 0x3800001e,
1243 0xc78, 0x3801001e,
1244 0xc78, 0x3802001e,
1245 0xc78, 0x3803001e,
1246 0xc78, 0x3804001e,
1247 0xc78, 0x3805001e,
1248 0xc78, 0x3806001e,
1249 0xc78, 0x3807001e,
1250 0xc78, 0x3808001e,
1251 0xc78, 0x3c09001e,
1252 0xc78, 0x3e0a001e,
1253 0xc78, 0x400b001e,
1254 0xc78, 0x440c001e,
1255 0xc78, 0x480d001e,
1256 0xc78, 0x4c0e001e,
1257 0xc78, 0x500f001e,
1258 0xc78, 0x5210001e,
1259 0xc78, 0x5611001e,
1260 0xc78, 0x5a12001e,
1261 0xc78, 0x5e13001e,
1262 0xc78, 0x6014001e,
1263 0xc78, 0x6015001e,
1264 0xc78, 0x6016001e,
1265 0xc78, 0x6217001e,
1266 0xc78, 0x6218001e,
1267 0xc78, 0x6219001e,
1268 0xc78, 0x621a001e,
1269 0xc78, 0x621b001e,
1270 0xc78, 0x621c001e,
1271 0xc78, 0x621d001e,
1272 0xc78, 0x621e001e,
1273 0xc78, 0x621f001e,
1274};
1275
1276u32 RTL8192CUPHY_REG_1T_HPArray[RTL8192CUPHY_REG_1T_HPArrayLength] = {
1277 0x024, 0x0011800f,
1278 0x028, 0x00ffdb83,
1279 0x040, 0x000c0004,
1280 0x800, 0x80040000,
1281 0x804, 0x00000001,
1282 0x808, 0x0000fc00,
1283 0x80c, 0x0000000a,
1284 0x810, 0x10005388,
1285 0x814, 0x020c3d10,
1286 0x818, 0x02200385,
1287 0x81c, 0x00000000,
1288 0x820, 0x01000100,
1289 0x824, 0x00390204,
1290 0x828, 0x00000000,
1291 0x82c, 0x00000000,
1292 0x830, 0x00000000,
1293 0x834, 0x00000000,
1294 0x838, 0x00000000,
1295 0x83c, 0x00000000,
1296 0x840, 0x00010000,
1297 0x844, 0x00000000,
1298 0x848, 0x00000000,
1299 0x84c, 0x00000000,
1300 0x850, 0x00000000,
1301 0x854, 0x00000000,
1302 0x858, 0x569a569a,
1303 0x85c, 0x001b25a4,
1304 0x860, 0x66e60230,
1305 0x864, 0x061f0130,
1306 0x868, 0x00000000,
1307 0x86c, 0x20202000,
1308 0x870, 0x03000300,
1309 0x874, 0x22004000,
1310 0x878, 0x00000808,
1311 0x87c, 0x00ffc3f1,
1312 0x880, 0xc0083070,
1313 0x884, 0x000004d5,
1314 0x888, 0x00000000,
1315 0x88c, 0xccc000c0,
1316 0x890, 0x00000800,
1317 0x894, 0xfffffffe,
1318 0x898, 0x40302010,
1319 0x89c, 0x00706050,
1320 0x900, 0x00000000,
1321 0x904, 0x00000023,
1322 0x908, 0x00000000,
1323 0x90c, 0x81121111,
1324 0xa00, 0x00d047c8,
1325 0xa04, 0x80ff000c,
1326 0xa08, 0x8c838300,
1327 0xa0c, 0x2e68120f,
1328 0xa10, 0x9500bb78,
1329 0xa14, 0x11144028,
1330 0xa18, 0x00881117,
1331 0xa1c, 0x89140f00,
1332 0xa20, 0x15160000,
1333 0xa24, 0x070b0f12,
1334 0xa28, 0x00000104,
1335 0xa2c, 0x00d30000,
1336 0xa70, 0x101fbf00,
1337 0xa74, 0x00000007,
1338 0xc00, 0x48071d40,
1339 0xc04, 0x03a05611,
1340 0xc08, 0x000000e4,
1341 0xc0c, 0x6c6c6c6c,
1342 0xc10, 0x08800000,
1343 0xc14, 0x40000100,
1344 0xc18, 0x08800000,
1345 0xc1c, 0x40000100,
1346 0xc20, 0x00000000,
1347 0xc24, 0x00000000,
1348 0xc28, 0x00000000,
1349 0xc2c, 0x00000000,
1350 0xc30, 0x69e9ac44,
1351 0xc34, 0x469652cf,
1352 0xc38, 0x49795994,
1353 0xc3c, 0x0a97971c,
1354 0xc40, 0x1f7c403f,
1355 0xc44, 0x000100b7,
1356 0xc48, 0xec020107,
1357 0xc4c, 0x007f037f,
1358 0xc50, 0x6954342e,
1359 0xc54, 0x43bc0094,
1360 0xc58, 0x6954342f,
1361 0xc5c, 0x433c0094,
1362 0xc60, 0x00000000,
1363 0xc64, 0x5116848b,
1364 0xc68, 0x47c00bff,
1365 0xc6c, 0x00000036,
1366 0xc70, 0x2c46000d,
1367 0xc74, 0x018610db,
1368 0xc78, 0x0000001f,
1369 0xc7c, 0x00b91612,
1370 0xc80, 0x24000090,
1371 0xc84, 0x20f60000,
1372 0xc88, 0x24000090,
1373 0xc8c, 0x20200000,
1374 0xc90, 0x00121820,
1375 0xc94, 0x00000000,
1376 0xc98, 0x00121820,
1377 0xc9c, 0x00007f7f,
1378 0xca0, 0x00000000,
1379 0xca4, 0x00000080,
1380 0xca8, 0x00000000,
1381 0xcac, 0x00000000,
1382 0xcb0, 0x00000000,
1383 0xcb4, 0x00000000,
1384 0xcb8, 0x00000000,
1385 0xcbc, 0x28000000,
1386 0xcc0, 0x00000000,
1387 0xcc4, 0x00000000,
1388 0xcc8, 0x00000000,
1389 0xccc, 0x00000000,
1390 0xcd0, 0x00000000,
1391 0xcd4, 0x00000000,
1392 0xcd8, 0x64b22427,
1393 0xcdc, 0x00766932,
1394 0xce0, 0x00222222,
1395 0xce4, 0x00000000,
1396 0xce8, 0x37644302,
1397 0xcec, 0x2f97d40c,
1398 0xd00, 0x00080740,
1399 0xd04, 0x00020401,
1400 0xd08, 0x0000907f,
1401 0xd0c, 0x20010201,
1402 0xd10, 0xa0633333,
1403 0xd14, 0x3333bc43,
1404 0xd18, 0x7a8f5b6b,
1405 0xd2c, 0xcc979975,
1406 0xd30, 0x00000000,
1407 0xd34, 0x80608000,
1408 0xd38, 0x00000000,
1409 0xd3c, 0x00027293,
1410 0xd40, 0x00000000,
1411 0xd44, 0x00000000,
1412 0xd48, 0x00000000,
1413 0xd4c, 0x00000000,
1414 0xd50, 0x6437140a,
1415 0xd54, 0x00000000,
1416 0xd58, 0x00000000,
1417 0xd5c, 0x30032064,
1418 0xd60, 0x4653de68,
1419 0xd64, 0x04518a3c,
1420 0xd68, 0x00002101,
1421 0xd6c, 0x2a201c16,
1422 0xd70, 0x1812362e,
1423 0xd74, 0x322c2220,
1424 0xd78, 0x000e3c24,
1425 0xe00, 0x24242424,
1426 0xe04, 0x24242424,
1427 0xe08, 0x03902024,
1428 0xe10, 0x24242424,
1429 0xe14, 0x24242424,
1430 0xe18, 0x24242424,
1431 0xe1c, 0x24242424,
1432 0xe28, 0x00000000,
1433 0xe30, 0x1000dc1f,
1434 0xe34, 0x10008c1f,
1435 0xe38, 0x02140102,
1436 0xe3c, 0x681604c2,
1437 0xe40, 0x01007c00,
1438 0xe44, 0x01004800,
1439 0xe48, 0xfb000000,
1440 0xe4c, 0x000028d1,
1441 0xe50, 0x1000dc1f,
1442 0xe54, 0x10008c1f,
1443 0xe58, 0x02140102,
1444 0xe5c, 0x28160d05,
1445 0xe60, 0x00000008,
1446 0xe68, 0x001b25a4,
1447 0xe6c, 0x631b25a0,
1448 0xe70, 0x631b25a0,
1449 0xe74, 0x081b25a0,
1450 0xe78, 0x081b25a0,
1451 0xe7c, 0x081b25a0,
1452 0xe80, 0x081b25a0,
1453 0xe84, 0x631b25a0,
1454 0xe88, 0x081b25a0,
1455 0xe8c, 0x631b25a0,
1456 0xed0, 0x631b25a0,
1457 0xed4, 0x631b25a0,
1458 0xed8, 0x631b25a0,
1459 0xedc, 0x001b25a0,
1460 0xee0, 0x001b25a0,
1461 0xeec, 0x6b1b25a0,
1462 0xee8, 0x31555448,
1463 0xf14, 0x00000003,
1464 0xf4c, 0x00000000,
1465 0xf00, 0x00000300,
1466};
1467
1468u32 RTL8192CUPHY_REG_Array_PG_HP[RTL8192CUPHY_REG_Array_PG_HPLength] = {
1469 0xe00, 0xffffffff, 0x06080808,
1470 0xe04, 0xffffffff, 0x00040406,
1471 0xe08, 0x0000ff00, 0x00000000,
1472 0x86c, 0xffffff00, 0x00000000,
1473 0xe10, 0xffffffff, 0x04060608,
1474 0xe14, 0xffffffff, 0x00020204,
1475 0xe18, 0xffffffff, 0x04060608,
1476 0xe1c, 0xffffffff, 0x00020204,
1477 0x830, 0xffffffff, 0x06080808,
1478 0x834, 0xffffffff, 0x00040406,
1479 0x838, 0xffffff00, 0x00000000,
1480 0x86c, 0x000000ff, 0x00000000,
1481 0x83c, 0xffffffff, 0x04060608,
1482 0x848, 0xffffffff, 0x00020204,
1483 0x84c, 0xffffffff, 0x04060608,
1484 0x868, 0xffffffff, 0x00020204,
1485 0xe00, 0xffffffff, 0x00000000,
1486 0xe04, 0xffffffff, 0x00000000,
1487 0xe08, 0x0000ff00, 0x00000000,
1488 0x86c, 0xffffff00, 0x00000000,
1489 0xe10, 0xffffffff, 0x00000000,
1490 0xe14, 0xffffffff, 0x00000000,
1491 0xe18, 0xffffffff, 0x00000000,
1492 0xe1c, 0xffffffff, 0x00000000,
1493 0x830, 0xffffffff, 0x00000000,
1494 0x834, 0xffffffff, 0x00000000,
1495 0x838, 0xffffff00, 0x00000000,
1496 0x86c, 0x000000ff, 0x00000000,
1497 0x83c, 0xffffffff, 0x00000000,
1498 0x848, 0xffffffff, 0x00000000,
1499 0x84c, 0xffffffff, 0x00000000,
1500 0x868, 0xffffffff, 0x00000000,
1501 0xe00, 0xffffffff, 0x00000000,
1502 0xe04, 0xffffffff, 0x00000000,
1503 0xe08, 0x0000ff00, 0x00000000,
1504 0x86c, 0xffffff00, 0x00000000,
1505 0xe10, 0xffffffff, 0x00000000,
1506 0xe14, 0xffffffff, 0x00000000,
1507 0xe18, 0xffffffff, 0x00000000,
1508 0xe1c, 0xffffffff, 0x00000000,
1509 0x830, 0xffffffff, 0x00000000,
1510 0x834, 0xffffffff, 0x00000000,
1511 0x838, 0xffffff00, 0x00000000,
1512 0x86c, 0x000000ff, 0x00000000,
1513 0x83c, 0xffffffff, 0x00000000,
1514 0x848, 0xffffffff, 0x00000000,
1515 0x84c, 0xffffffff, 0x00000000,
1516 0x868, 0xffffffff, 0x00000000,
1517 0xe00, 0xffffffff, 0x00000000,
1518 0xe04, 0xffffffff, 0x00000000,
1519 0xe08, 0x0000ff00, 0x00000000,
1520 0x86c, 0xffffff00, 0x00000000,
1521 0xe10, 0xffffffff, 0x00000000,
1522 0xe14, 0xffffffff, 0x00000000,
1523 0xe18, 0xffffffff, 0x00000000,
1524 0xe1c, 0xffffffff, 0x00000000,
1525 0x830, 0xffffffff, 0x00000000,
1526 0x834, 0xffffffff, 0x00000000,
1527 0x838, 0xffffff00, 0x00000000,
1528 0x86c, 0x000000ff, 0x00000000,
1529 0x83c, 0xffffffff, 0x00000000,
1530 0x848, 0xffffffff, 0x00000000,
1531 0x84c, 0xffffffff, 0x00000000,
1532 0x868, 0xffffffff, 0x00000000,
1533 0xe00, 0xffffffff, 0x00000000,
1534 0xe04, 0xffffffff, 0x00000000,
1535 0xe08, 0x0000ff00, 0x00000000,
1536 0x86c, 0xffffff00, 0x00000000,
1537 0xe10, 0xffffffff, 0x00000000,
1538 0xe14, 0xffffffff, 0x00000000,
1539 0xe18, 0xffffffff, 0x00000000,
1540 0xe1c, 0xffffffff, 0x00000000,
1541 0x830, 0xffffffff, 0x00000000,
1542 0x834, 0xffffffff, 0x00000000,
1543 0x838, 0xffffff00, 0x00000000,
1544 0x86c, 0x000000ff, 0x00000000,
1545 0x83c, 0xffffffff, 0x00000000,
1546 0x848, 0xffffffff, 0x00000000,
1547 0x84c, 0xffffffff, 0x00000000,
1548 0x868, 0xffffffff, 0x00000000,
1549 0xe00, 0xffffffff, 0x00000000,
1550 0xe04, 0xffffffff, 0x00000000,
1551 0xe08, 0x0000ff00, 0x00000000,
1552 0x86c, 0xffffff00, 0x00000000,
1553 0xe10, 0xffffffff, 0x00000000,
1554 0xe14, 0xffffffff, 0x00000000,
1555 0xe18, 0xffffffff, 0x00000000,
1556 0xe1c, 0xffffffff, 0x00000000,
1557 0x830, 0xffffffff, 0x00000000,
1558 0x834, 0xffffffff, 0x00000000,
1559 0x838, 0xffffff00, 0x00000000,
1560 0x86c, 0x000000ff, 0x00000000,
1561 0x83c, 0xffffffff, 0x00000000,
1562 0x848, 0xffffffff, 0x00000000,
1563 0x84c, 0xffffffff, 0x00000000,
1564 0x868, 0xffffffff, 0x00000000,
1565 0xe00, 0xffffffff, 0x00000000,
1566 0xe04, 0xffffffff, 0x00000000,
1567 0xe08, 0x0000ff00, 0x00000000,
1568 0x86c, 0xffffff00, 0x00000000,
1569 0xe10, 0xffffffff, 0x00000000,
1570 0xe14, 0xffffffff, 0x00000000,
1571 0xe18, 0xffffffff, 0x00000000,
1572 0xe1c, 0xffffffff, 0x00000000,
1573 0x830, 0xffffffff, 0x00000000,
1574 0x834, 0xffffffff, 0x00000000,
1575 0x838, 0xffffff00, 0x00000000,
1576 0x86c, 0x000000ff, 0x00000000,
1577 0x83c, 0xffffffff, 0x00000000,
1578 0x848, 0xffffffff, 0x00000000,
1579 0x84c, 0xffffffff, 0x00000000,
1580 0x868, 0xffffffff, 0x00000000,
1581};
1582
1583u32 RTL8192CURadioA_1T_HPArray[RTL8192CURadioA_1T_HPArrayLength] = {
1584 0x000, 0x00030159,
1585 0x001, 0x00031284,
1586 0x002, 0x00098000,
1587 0x003, 0x00018c63,
1588 0x004, 0x000210e7,
1589 0x009, 0x0002044f,
1590 0x00a, 0x0001adb0,
1591 0x00b, 0x00054867,
1592 0x00c, 0x0008992e,
1593 0x00d, 0x0000e529,
1594 0x00e, 0x00039ce7,
1595 0x00f, 0x00000451,
1596 0x019, 0x00000000,
1597 0x01a, 0x00000255,
1598 0x01b, 0x00060a00,
1599 0x01c, 0x000fc378,
1600 0x01d, 0x000a1250,
1601 0x01e, 0x0004445f,
1602 0x01f, 0x00080001,
1603 0x020, 0x0000b614,
1604 0x021, 0x0006c000,
1605 0x022, 0x0000083c,
1606 0x023, 0x00001558,
1607 0x024, 0x00000060,
1608 0x025, 0x00000483,
1609 0x026, 0x0004f000,
1610 0x027, 0x000ec7d9,
1611 0x028, 0x000977c0,
1612 0x029, 0x00004783,
1613 0x02a, 0x00000001,
1614 0x02b, 0x00021334,
1615 0x02a, 0x00000000,
1616 0x02b, 0x00000054,
1617 0x02a, 0x00000001,
1618 0x02b, 0x00000808,
1619 0x02b, 0x00053333,
1620 0x02c, 0x0000000c,
1621 0x02a, 0x00000002,
1622 0x02b, 0x00000808,
1623 0x02b, 0x0005b333,
1624 0x02c, 0x0000000d,
1625 0x02a, 0x00000003,
1626 0x02b, 0x00000808,
1627 0x02b, 0x00063333,
1628 0x02c, 0x0000000d,
1629 0x02a, 0x00000004,
1630 0x02b, 0x00000808,
1631 0x02b, 0x0006b333,
1632 0x02c, 0x0000000d,
1633 0x02a, 0x00000005,
1634 0x02b, 0x00000808,
1635 0x02b, 0x00073333,
1636 0x02c, 0x0000000d,
1637 0x02a, 0x00000006,
1638 0x02b, 0x00000709,
1639 0x02b, 0x0005b333,
1640 0x02c, 0x0000000d,
1641 0x02a, 0x00000007,
1642 0x02b, 0x00000709,
1643 0x02b, 0x00063333,
1644 0x02c, 0x0000000d,
1645 0x02a, 0x00000008,
1646 0x02b, 0x0000060a,
1647 0x02b, 0x0004b333,
1648 0x02c, 0x0000000d,
1649 0x02a, 0x00000009,
1650 0x02b, 0x0000060a,
1651 0x02b, 0x00053333,
1652 0x02c, 0x0000000d,
1653 0x02a, 0x0000000a,
1654 0x02b, 0x0000060a,
1655 0x02b, 0x0005b333,
1656 0x02c, 0x0000000d,
1657 0x02a, 0x0000000b,
1658 0x02b, 0x0000060a,
1659 0x02b, 0x00063333,
1660 0x02c, 0x0000000d,
1661 0x02a, 0x0000000c,
1662 0x02b, 0x0000060a,
1663 0x02b, 0x0006b333,
1664 0x02c, 0x0000000d,
1665 0x02a, 0x0000000d,
1666 0x02b, 0x0000060a,
1667 0x02b, 0x00073333,
1668 0x02c, 0x0000000d,
1669 0x02a, 0x0000000e,
1670 0x02b, 0x0000050b,
1671 0x02b, 0x00066666,
1672 0x02c, 0x0000001a,
1673 0x02a, 0x000e0000,
1674 0x010, 0x0004000f,
1675 0x011, 0x000e31fc,
1676 0x010, 0x0006000f,
1677 0x011, 0x000ff9f8,
1678 0x010, 0x0002000f,
1679 0x011, 0x000203f9,
1680 0x010, 0x0003000f,
1681 0x011, 0x000ff500,
1682 0x010, 0x00000000,
1683 0x011, 0x00000000,
1684 0x010, 0x0008000f,
1685 0x011, 0x0003f100,
1686 0x010, 0x0009000f,
1687 0x011, 0x00023100,
1688 0x012, 0x000d8000,
1689 0x012, 0x00090000,
1690 0x012, 0x00051000,
1691 0x012, 0x00012000,
1692 0x013, 0x00028fb4,
1693 0x013, 0x00024fa8,
1694 0x013, 0x000207a4,
1695 0x013, 0x0001c798,
1696 0x013, 0x000183a4,
1697 0x013, 0x00014398,
1698 0x013, 0x000101a4,
1699 0x013, 0x0000c198,
1700 0x013, 0x000080a4,
1701 0x013, 0x00004098,
1702 0x013, 0x00000000,
1703 0x014, 0x0001944c,
1704 0x014, 0x00059444,
1705 0x014, 0x0009944c,
1706 0x014, 0x000d9444,
1707 0x015, 0x0000f405,
1708 0x015, 0x0004f405,
1709 0x015, 0x0008f405,
1710 0x015, 0x000cf405,
1711 0x016, 0x000e0330,
1712 0x016, 0x000a0330,
1713 0x016, 0x00060330,
1714 0x016, 0x00020330,
1715 0x000, 0x00010159,
1716 0x018, 0x0000f401,
1717 0x0fe, 0x00000000,
1718 0x0fe, 0x00000000,
1719 0x01f, 0x00080003,
1720 0x0fe, 0x00000000,
1721 0x0fe, 0x00000000,
1722 0x01e, 0x00044457,
1723 0x01f, 0x00080000,
1724 0x000, 0x00030159,
1725};
1726
1727u32 Rtl8192CUAGCTAB_1T_HPArray[RTL8192CUAGCTAB_1T_HPArrayLength] = {
1728 0xc78, 0x7b000001,
1729 0xc78, 0x7b010001,
1730 0xc78, 0x7b020001,
1731 0xc78, 0x7b030001,
1732 0xc78, 0x7b040001,
1733 0xc78, 0x7b050001,
1734 0xc78, 0x7b060001,
1735 0xc78, 0x7b070001,
1736 0xc78, 0x7b080001,
1737 0xc78, 0x7a090001,
1738 0xc78, 0x790a0001,
1739 0xc78, 0x780b0001,
1740 0xc78, 0x770c0001,
1741 0xc78, 0x760d0001,
1742 0xc78, 0x750e0001,
1743 0xc78, 0x740f0001,
1744 0xc78, 0x73100001,
1745 0xc78, 0x72110001,
1746 0xc78, 0x71120001,
1747 0xc78, 0x70130001,
1748 0xc78, 0x6f140001,
1749 0xc78, 0x6e150001,
1750 0xc78, 0x6d160001,
1751 0xc78, 0x6c170001,
1752 0xc78, 0x6b180001,
1753 0xc78, 0x6a190001,
1754 0xc78, 0x691a0001,
1755 0xc78, 0x681b0001,
1756 0xc78, 0x671c0001,
1757 0xc78, 0x661d0001,
1758 0xc78, 0x651e0001,
1759 0xc78, 0x641f0001,
1760 0xc78, 0x63200001,
1761 0xc78, 0x62210001,
1762 0xc78, 0x61220001,
1763 0xc78, 0x60230001,
1764 0xc78, 0x46240001,
1765 0xc78, 0x45250001,
1766 0xc78, 0x44260001,
1767 0xc78, 0x43270001,
1768 0xc78, 0x42280001,
1769 0xc78, 0x41290001,
1770 0xc78, 0x402a0001,
1771 0xc78, 0x262b0001,
1772 0xc78, 0x252c0001,
1773 0xc78, 0x242d0001,
1774 0xc78, 0x232e0001,
1775 0xc78, 0x222f0001,
1776 0xc78, 0x21300001,
1777 0xc78, 0x20310001,
1778 0xc78, 0x06320001,
1779 0xc78, 0x05330001,
1780 0xc78, 0x04340001,
1781 0xc78, 0x03350001,
1782 0xc78, 0x02360001,
1783 0xc78, 0x01370001,
1784 0xc78, 0x00380001,
1785 0xc78, 0x00390001,
1786 0xc78, 0x003a0001,
1787 0xc78, 0x003b0001,
1788 0xc78, 0x003c0001,
1789 0xc78, 0x003d0001,
1790 0xc78, 0x003e0001,
1791 0xc78, 0x003f0001,
1792 0xc78, 0x7b400001,
1793 0xc78, 0x7b410001,
1794 0xc78, 0x7b420001,
1795 0xc78, 0x7b430001,
1796 0xc78, 0x7b440001,
1797 0xc78, 0x7b450001,
1798 0xc78, 0x7b460001,
1799 0xc78, 0x7b470001,
1800 0xc78, 0x7b480001,
1801 0xc78, 0x7a490001,
1802 0xc78, 0x794a0001,
1803 0xc78, 0x784b0001,
1804 0xc78, 0x774c0001,
1805 0xc78, 0x764d0001,
1806 0xc78, 0x754e0001,
1807 0xc78, 0x744f0001,
1808 0xc78, 0x73500001,
1809 0xc78, 0x72510001,
1810 0xc78, 0x71520001,
1811 0xc78, 0x70530001,
1812 0xc78, 0x6f540001,
1813 0xc78, 0x6e550001,
1814 0xc78, 0x6d560001,
1815 0xc78, 0x6c570001,
1816 0xc78, 0x6b580001,
1817 0xc78, 0x6a590001,
1818 0xc78, 0x695a0001,
1819 0xc78, 0x685b0001,
1820 0xc78, 0x675c0001,
1821 0xc78, 0x665d0001,
1822 0xc78, 0x655e0001,
1823 0xc78, 0x645f0001,
1824 0xc78, 0x63600001,
1825 0xc78, 0x62610001,
1826 0xc78, 0x61620001,
1827 0xc78, 0x60630001,
1828 0xc78, 0x46640001,
1829 0xc78, 0x45650001,
1830 0xc78, 0x44660001,
1831 0xc78, 0x43670001,
1832 0xc78, 0x42680001,
1833 0xc78, 0x41690001,
1834 0xc78, 0x406a0001,
1835 0xc78, 0x266b0001,
1836 0xc78, 0x256c0001,
1837 0xc78, 0x246d0001,
1838 0xc78, 0x236e0001,
1839 0xc78, 0x226f0001,
1840 0xc78, 0x21700001,
1841 0xc78, 0x20710001,
1842 0xc78, 0x06720001,
1843 0xc78, 0x05730001,
1844 0xc78, 0x04740001,
1845 0xc78, 0x03750001,
1846 0xc78, 0x02760001,
1847 0xc78, 0x01770001,
1848 0xc78, 0x00780001,
1849 0xc78, 0x00790001,
1850 0xc78, 0x007a0001,
1851 0xc78, 0x007b0001,
1852 0xc78, 0x007c0001,
1853 0xc78, 0x007d0001,
1854 0xc78, 0x007e0001,
1855 0xc78, 0x007f0001,
1856 0xc78, 0x3800001e,
1857 0xc78, 0x3801001e,
1858 0xc78, 0x3802001e,
1859 0xc78, 0x3803001e,
1860 0xc78, 0x3804001e,
1861 0xc78, 0x3805001e,
1862 0xc78, 0x3806001e,
1863 0xc78, 0x3807001e,
1864 0xc78, 0x3808001e,
1865 0xc78, 0x3c09001e,
1866 0xc78, 0x3e0a001e,
1867 0xc78, 0x400b001e,
1868 0xc78, 0x440c001e,
1869 0xc78, 0x480d001e,
1870 0xc78, 0x4c0e001e,
1871 0xc78, 0x500f001e,
1872 0xc78, 0x5210001e,
1873 0xc78, 0x5611001e,
1874 0xc78, 0x5a12001e,
1875 0xc78, 0x5e13001e,
1876 0xc78, 0x6014001e,
1877 0xc78, 0x6015001e,
1878 0xc78, 0x6016001e,
1879 0xc78, 0x6217001e,
1880 0xc78, 0x6218001e,
1881 0xc78, 0x6219001e,
1882 0xc78, 0x621a001e,
1883 0xc78, 0x621b001e,
1884 0xc78, 0x621c001e,
1885 0xc78, 0x621d001e,
1886 0xc78, 0x621e001e,
1887 0xc78, 0x621f001e,
1888};
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/table.h b/drivers/net/wireless/rtlwifi/rtl8192cu/table.h
new file mode 100644
index 000000000000..c3d5cd826cfa
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/table.h
@@ -0,0 +1,71 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CU_TABLE__H_
31#define __RTL92CU_TABLE__H_
32
33#include <linux/types.h>
34
35#define RTL8192CUPHY_REG_2TARRAY_LENGTH 374
36extern u32 RTL8192CUPHY_REG_2TARRAY[RTL8192CUPHY_REG_2TARRAY_LENGTH];
37#define RTL8192CUPHY_REG_1TARRAY_LENGTH 374
38extern u32 RTL8192CUPHY_REG_1TARRAY[RTL8192CUPHY_REG_1TARRAY_LENGTH];
39
40#define RTL8192CUPHY_REG_ARRAY_PGLENGTH 336
41extern u32 RTL8192CUPHY_REG_ARRAY_PG[RTL8192CUPHY_REG_ARRAY_PGLENGTH];
42
43#define RTL8192CURADIOA_2TARRAYLENGTH 282
44extern u32 RTL8192CURADIOA_2TARRAY[RTL8192CURADIOA_2TARRAYLENGTH];
45#define RTL8192CURADIOB_2TARRAYLENGTH 78
46extern u32 RTL8192CU_RADIOB_2TARRAY[RTL8192CURADIOB_2TARRAYLENGTH];
47#define RTL8192CURADIOA_1TARRAYLENGTH 282
48extern u32 RTL8192CU_RADIOA_1TARRAY[RTL8192CURADIOA_1TARRAYLENGTH];
49#define RTL8192CURADIOB_1TARRAYLENGTH 1
50extern u32 RTL8192CU_RADIOB_1TARRAY[RTL8192CURADIOB_1TARRAYLENGTH];
51
52#define RTL8192CUMAC_2T_ARRAYLENGTH 172
53extern u32 RTL8192CUMAC_2T_ARRAY[RTL8192CUMAC_2T_ARRAYLENGTH];
54
55#define RTL8192CUAGCTAB_2TARRAYLENGTH 320
56extern u32 RTL8192CUAGCTAB_2TARRAY[RTL8192CUAGCTAB_2TARRAYLENGTH];
57#define RTL8192CUAGCTAB_1TARRAYLENGTH 320
58extern u32 RTL8192CUAGCTAB_1TARRAY[RTL8192CUAGCTAB_1TARRAYLENGTH];
59
60#define RTL8192CUPHY_REG_1T_HPArrayLength 378
61extern u32 RTL8192CUPHY_REG_1T_HPArray[RTL8192CUPHY_REG_1T_HPArrayLength];
62
63#define RTL8192CUPHY_REG_Array_PG_HPLength 336
64extern u32 RTL8192CUPHY_REG_Array_PG_HP[RTL8192CUPHY_REG_Array_PG_HPLength];
65
66#define RTL8192CURadioA_1T_HPArrayLength 282
67extern u32 RTL8192CURadioA_1T_HPArray[RTL8192CURadioA_1T_HPArrayLength];
68#define RTL8192CUAGCTAB_1T_HPArrayLength 320
69extern u32 Rtl8192CUAGCTAB_1T_HPArray[RTL8192CUAGCTAB_1T_HPArrayLength];
70
71#endif
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c
new file mode 100644
index 000000000000..d0b0d43b9a6d
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.c
@@ -0,0 +1,687 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#include "../wifi.h"
31#include "../usb.h"
32#include "../ps.h"
33#include "../base.h"
34#include "reg.h"
35#include "def.h"
36#include "phy.h"
37#include "rf.h"
38#include "dm.h"
39#include "mac.h"
40#include "trx.h"
41
42static int _ConfigVerTOutEP(struct ieee80211_hw *hw)
43{
44 u8 ep_cfg, txqsele;
45 u8 ep_nums = 0;
46
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
49 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
50
51 rtlusb->out_queue_sel = 0;
52 ep_cfg = rtl_read_byte(rtlpriv, REG_TEST_SIE_OPTIONAL);
53 ep_cfg = (ep_cfg & USB_TEST_EP_MASK) >> USB_TEST_EP_SHIFT;
54 switch (ep_cfg) {
55 case 0: /* 2 bulk OUT, 1 bulk IN */
56 case 3:
57 rtlusb->out_queue_sel = TX_SELE_HQ | TX_SELE_LQ;
58 ep_nums = 2;
59 break;
60 case 1: /* 1 bulk IN/OUT => map all endpoint to Low queue */
61 case 2: /* 1 bulk IN, 1 bulk OUT => map all endpoint to High queue */
62 txqsele = rtl_read_byte(rtlpriv, REG_TEST_USB_TXQS);
63 if (txqsele & 0x0F) /* /map all endpoint to High queue */
64 rtlusb->out_queue_sel = TX_SELE_HQ;
65 else if (txqsele&0xF0) /* map all endpoint to Low queue */
66 rtlusb->out_queue_sel = TX_SELE_LQ;
67 ep_nums = 1;
68 break;
69 default:
70 break;
71 }
72 return (rtlusb->out_ep_nums == ep_nums) ? 0 : -EINVAL;
73}
74
75static int _ConfigVerNOutEP(struct ieee80211_hw *hw)
76{
77 u8 ep_cfg;
78 u8 ep_nums = 0;
79
80 struct rtl_priv *rtlpriv = rtl_priv(hw);
81 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
82 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
83
84 rtlusb->out_queue_sel = 0;
85 /* Normal and High queue */
86 ep_cfg = rtl_read_byte(rtlpriv, (REG_NORMAL_SIE_EP + 1));
87 if (ep_cfg & USB_NORMAL_SIE_EP_MASK) {
88 rtlusb->out_queue_sel |= TX_SELE_HQ;
89 ep_nums++;
90 }
91 if ((ep_cfg >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK) {
92 rtlusb->out_queue_sel |= TX_SELE_NQ;
93 ep_nums++;
94 }
95 /* Low queue */
96 ep_cfg = rtl_read_byte(rtlpriv, (REG_NORMAL_SIE_EP + 2));
97 if (ep_cfg & USB_NORMAL_SIE_EP_MASK) {
98 rtlusb->out_queue_sel |= TX_SELE_LQ;
99 ep_nums++;
100 }
101 return (rtlusb->out_ep_nums == ep_nums) ? 0 : -EINVAL;
102}
103
104static void _TwoOutEpMapping(struct ieee80211_hw *hw, bool bIsChipB,
105 bool bwificfg, struct rtl_ep_map *ep_map)
106{
107 struct rtl_priv *rtlpriv = rtl_priv(hw);
108
109 if (bwificfg) { /* for WMM */
110 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
111 ("USB Chip-B & WMM Setting.....\n"));
112 ep_map->ep_mapping[RTL_TXQ_BE] = 2;
113 ep_map->ep_mapping[RTL_TXQ_BK] = 3;
114 ep_map->ep_mapping[RTL_TXQ_VI] = 3;
115 ep_map->ep_mapping[RTL_TXQ_VO] = 2;
116 ep_map->ep_mapping[RTL_TXQ_MGT] = 2;
117 ep_map->ep_mapping[RTL_TXQ_BCN] = 2;
118 ep_map->ep_mapping[RTL_TXQ_HI] = 2;
119 } else { /* typical setting */
120 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
121 ("USB typical Setting.....\n"));
122 ep_map->ep_mapping[RTL_TXQ_BE] = 3;
123 ep_map->ep_mapping[RTL_TXQ_BK] = 3;
124 ep_map->ep_mapping[RTL_TXQ_VI] = 2;
125 ep_map->ep_mapping[RTL_TXQ_VO] = 2;
126 ep_map->ep_mapping[RTL_TXQ_MGT] = 2;
127 ep_map->ep_mapping[RTL_TXQ_BCN] = 2;
128 ep_map->ep_mapping[RTL_TXQ_HI] = 2;
129 }
130}
131
132static void _ThreeOutEpMapping(struct ieee80211_hw *hw, bool bwificfg,
133 struct rtl_ep_map *ep_map)
134{
135 struct rtl_priv *rtlpriv = rtl_priv(hw);
136 if (bwificfg) { /* for WMM */
137 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
138 ("USB 3EP Setting for WMM.....\n"));
139 ep_map->ep_mapping[RTL_TXQ_BE] = 5;
140 ep_map->ep_mapping[RTL_TXQ_BK] = 3;
141 ep_map->ep_mapping[RTL_TXQ_VI] = 3;
142 ep_map->ep_mapping[RTL_TXQ_VO] = 2;
143 ep_map->ep_mapping[RTL_TXQ_MGT] = 2;
144 ep_map->ep_mapping[RTL_TXQ_BCN] = 2;
145 ep_map->ep_mapping[RTL_TXQ_HI] = 2;
146 } else { /* typical setting */
147 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
148 ("USB 3EP Setting for typical.....\n"));
149 ep_map->ep_mapping[RTL_TXQ_BE] = 5;
150 ep_map->ep_mapping[RTL_TXQ_BK] = 5;
151 ep_map->ep_mapping[RTL_TXQ_VI] = 3;
152 ep_map->ep_mapping[RTL_TXQ_VO] = 2;
153 ep_map->ep_mapping[RTL_TXQ_MGT] = 2;
154 ep_map->ep_mapping[RTL_TXQ_BCN] = 2;
155 ep_map->ep_mapping[RTL_TXQ_HI] = 2;
156 }
157}
158
159static void _OneOutEpMapping(struct ieee80211_hw *hw, struct rtl_ep_map *ep_map)
160{
161 ep_map->ep_mapping[RTL_TXQ_BE] = 2;
162 ep_map->ep_mapping[RTL_TXQ_BK] = 2;
163 ep_map->ep_mapping[RTL_TXQ_VI] = 2;
164 ep_map->ep_mapping[RTL_TXQ_VO] = 2;
165 ep_map->ep_mapping[RTL_TXQ_MGT] = 2;
166 ep_map->ep_mapping[RTL_TXQ_BCN] = 2;
167 ep_map->ep_mapping[RTL_TXQ_HI] = 2;
168}
169static int _out_ep_mapping(struct ieee80211_hw *hw)
170{
171 int err = 0;
172 bool bIsChipN, bwificfg = false;
173 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
174 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
175 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
176 struct rtl_ep_map *ep_map = &(rtlusb->ep_map);
177
178 bIsChipN = IS_NORMAL_CHIP(rtlhal->version);
179 switch (rtlusb->out_ep_nums) {
180 case 2:
181 _TwoOutEpMapping(hw, bIsChipN, bwificfg, ep_map);
182 break;
183 case 3:
184 /* Test chip doesn't support three out EPs. */
185 if (!bIsChipN) {
186 err = -EINVAL;
187 goto err_out;
188 }
189 _ThreeOutEpMapping(hw, bIsChipN, ep_map);
190 break;
191 case 1:
192 _OneOutEpMapping(hw, ep_map);
193 break;
194 default:
195 err = -EINVAL;
196 break;
197 }
198err_out:
199 return err;
200
201}
202/* endpoint mapping */
203int rtl8192cu_endpoint_mapping(struct ieee80211_hw *hw)
204{
205 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
206 int error = 0;
207 if (likely(IS_NORMAL_CHIP(rtlhal->version)))
208 error = _ConfigVerNOutEP(hw);
209 else
210 error = _ConfigVerTOutEP(hw);
211 if (error)
212 goto err_out;
213 error = _out_ep_mapping(hw);
214 if (error)
215 goto err_out;
216err_out:
217 return error;
218}
219
220u16 rtl8192cu_mq_to_hwq(__le16 fc, u16 mac80211_queue_index)
221{
222 u16 hw_queue_index;
223
224 if (unlikely(ieee80211_is_beacon(fc))) {
225 hw_queue_index = RTL_TXQ_BCN;
226 goto out;
227 }
228 if (ieee80211_is_mgmt(fc)) {
229 hw_queue_index = RTL_TXQ_MGT;
230 goto out;
231 }
232 switch (mac80211_queue_index) {
233 case 0:
234 hw_queue_index = RTL_TXQ_VO;
235 break;
236 case 1:
237 hw_queue_index = RTL_TXQ_VI;
238 break;
239 case 2:
240 hw_queue_index = RTL_TXQ_BE;
241 break;
242 case 3:
243 hw_queue_index = RTL_TXQ_BK;
244 break;
245 default:
246 hw_queue_index = RTL_TXQ_BE;
247 RT_ASSERT(false, ("QSLT_BE queue, skb_queue:%d\n",
248 mac80211_queue_index));
249 break;
250 }
251out:
252 return hw_queue_index;
253}
254
255static enum rtl_desc_qsel _rtl8192cu_mq_to_descq(struct ieee80211_hw *hw,
256 __le16 fc, u16 mac80211_queue_index)
257{
258 enum rtl_desc_qsel qsel;
259 struct rtl_priv *rtlpriv = rtl_priv(hw);
260
261 if (unlikely(ieee80211_is_beacon(fc))) {
262 qsel = QSLT_BEACON;
263 goto out;
264 }
265 if (ieee80211_is_mgmt(fc)) {
266 qsel = QSLT_MGNT;
267 goto out;
268 }
269 switch (mac80211_queue_index) {
270 case 0: /* VO */
271 qsel = QSLT_VO;
272 RT_TRACE(rtlpriv, COMP_USB, DBG_DMESG,
273 ("VO queue, set qsel = 0x%x\n", QSLT_VO));
274 break;
275 case 1: /* VI */
276 qsel = QSLT_VI;
277 RT_TRACE(rtlpriv, COMP_USB, DBG_DMESG,
278 ("VI queue, set qsel = 0x%x\n", QSLT_VI));
279 break;
280 case 3: /* BK */
281 qsel = QSLT_BK;
282 RT_TRACE(rtlpriv, COMP_USB, DBG_DMESG,
283 ("BK queue, set qsel = 0x%x\n", QSLT_BK));
284 break;
285 case 2: /* BE */
286 default:
287 qsel = QSLT_BE;
288 RT_TRACE(rtlpriv, COMP_USB, DBG_DMESG,
289 ("BE queue, set qsel = 0x%x\n", QSLT_BE));
290 break;
291 }
292out:
293 return qsel;
294}
295
296/* =============================================================== */
297
298/*----------------------------------------------------------------------
299 *
300 * Rx handler
301 *
302 *---------------------------------------------------------------------- */
303bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw,
304 struct rtl_stats *stats,
305 struct ieee80211_rx_status *rx_status,
306 u8 *p_desc, struct sk_buff *skb)
307{
308 struct rx_fwinfo_92c *p_drvinfo;
309 struct rx_desc_92c *pdesc = (struct rx_desc_92c *)p_desc;
310 u32 phystatus = GET_RX_DESC_PHY_STATUS(pdesc);
311
312 stats->length = (u16) GET_RX_DESC_PKT_LEN(pdesc);
313 stats->rx_drvinfo_size = (u8)GET_RX_DESC_DRVINFO_SIZE(pdesc) *
314 RX_DRV_INFO_SIZE_UNIT;
315 stats->rx_bufshift = (u8) (GET_RX_DESC_SHIFT(pdesc) & 0x03);
316 stats->icv = (u16) GET_RX_DESC_ICV(pdesc);
317 stats->crc = (u16) GET_RX_DESC_CRC32(pdesc);
318 stats->hwerror = (stats->crc | stats->icv);
319 stats->decrypted = !GET_RX_DESC_SWDEC(pdesc);
320 stats->rate = (u8) GET_RX_DESC_RX_MCS(pdesc);
321 stats->shortpreamble = (u16) GET_RX_DESC_SPLCP(pdesc);
322 stats->isampdu = (bool) (GET_RX_DESC_PAGGR(pdesc) == 1);
323 stats->isampdu = (bool) ((GET_RX_DESC_PAGGR(pdesc) == 1)
324 && (GET_RX_DESC_FAGGR(pdesc) == 1));
325 stats->timestamp_low = GET_RX_DESC_TSFL(pdesc);
326 stats->rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(pdesc);
327 rx_status->freq = hw->conf.channel->center_freq;
328 rx_status->band = hw->conf.channel->band;
329 if (GET_RX_DESC_CRC32(pdesc))
330 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
331 if (!GET_RX_DESC_SWDEC(pdesc))
332 rx_status->flag |= RX_FLAG_DECRYPTED;
333 if (GET_RX_DESC_BW(pdesc))
334 rx_status->flag |= RX_FLAG_40MHZ;
335 if (GET_RX_DESC_RX_HT(pdesc))
336 rx_status->flag |= RX_FLAG_HT;
337 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
338 if (stats->decrypted)
339 rx_status->flag |= RX_FLAG_DECRYPTED;
340 rx_status->rate_idx = _rtl92c_rate_mapping(hw,
341 (bool)GET_RX_DESC_RX_HT(pdesc),
342 (u8)GET_RX_DESC_RX_MCS(pdesc),
343 (bool)GET_RX_DESC_PAGGR(pdesc));
344 rx_status->mactime = GET_RX_DESC_TSFL(pdesc);
345 if (phystatus == true) {
346 p_drvinfo = (struct rx_fwinfo_92c *)(pdesc + RTL_RX_DESC_SIZE);
347 rtl92c_translate_rx_signal_stuff(hw, skb, stats, pdesc,
348 p_drvinfo);
349 }
350 /*rx_status->qual = stats->signal; */
351 rx_status->signal = stats->rssi + 10;
352 /*rx_status->noise = -stats->noise; */
353 return true;
354}
355
356#define RTL_RX_DRV_INFO_UNIT 8
357
358static void _rtl_rx_process(struct ieee80211_hw *hw, struct sk_buff *skb)
359{
360 struct ieee80211_rx_status *rx_status =
361 (struct ieee80211_rx_status *)IEEE80211_SKB_RXCB(skb);
362 u32 skb_len, pkt_len, drvinfo_len;
363 struct rtl_priv *rtlpriv = rtl_priv(hw);
364 u8 *rxdesc;
365 struct rtl_stats stats = {
366 .signal = 0,
367 .noise = -98,
368 .rate = 0,
369 };
370 struct rx_fwinfo_92c *p_drvinfo;
371 bool bv;
372 __le16 fc;
373 struct ieee80211_hdr *hdr;
374
375 memset(rx_status, 0, sizeof(rx_status));
376 rxdesc = skb->data;
377 skb_len = skb->len;
378 drvinfo_len = (GET_RX_DESC_DRVINFO_SIZE(rxdesc) * RTL_RX_DRV_INFO_UNIT);
379 pkt_len = GET_RX_DESC_PKT_LEN(rxdesc);
380 /* TODO: Error recovery. drop this skb or something. */
381 WARN_ON(skb_len < (pkt_len + RTL_RX_DESC_SIZE + drvinfo_len));
382 stats.length = (u16) GET_RX_DESC_PKT_LEN(rxdesc);
383 stats.rx_drvinfo_size = (u8)GET_RX_DESC_DRVINFO_SIZE(rxdesc) *
384 RX_DRV_INFO_SIZE_UNIT;
385 stats.rx_bufshift = (u8) (GET_RX_DESC_SHIFT(rxdesc) & 0x03);
386 stats.icv = (u16) GET_RX_DESC_ICV(rxdesc);
387 stats.crc = (u16) GET_RX_DESC_CRC32(rxdesc);
388 stats.hwerror = (stats.crc | stats.icv);
389 stats.decrypted = !GET_RX_DESC_SWDEC(rxdesc);
390 stats.rate = (u8) GET_RX_DESC_RX_MCS(rxdesc);
391 stats.shortpreamble = (u16) GET_RX_DESC_SPLCP(rxdesc);
392 stats.isampdu = (bool) ((GET_RX_DESC_PAGGR(rxdesc) == 1)
393 && (GET_RX_DESC_FAGGR(rxdesc) == 1));
394 stats.timestamp_low = GET_RX_DESC_TSFL(rxdesc);
395 stats.rx_is40Mhzpacket = (bool) GET_RX_DESC_BW(rxdesc);
396 /* TODO: is center_freq changed when doing scan? */
397 /* TODO: Shall we add protection or just skip those two step? */
398 rx_status->freq = hw->conf.channel->center_freq;
399 rx_status->band = hw->conf.channel->band;
400 if (GET_RX_DESC_CRC32(rxdesc))
401 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
402 if (!GET_RX_DESC_SWDEC(rxdesc))
403 rx_status->flag |= RX_FLAG_DECRYPTED;
404 if (GET_RX_DESC_BW(rxdesc))
405 rx_status->flag |= RX_FLAG_40MHZ;
406 if (GET_RX_DESC_RX_HT(rxdesc))
407 rx_status->flag |= RX_FLAG_HT;
408 /* Data rate */
409 rx_status->rate_idx = _rtl92c_rate_mapping(hw,
410 (bool)GET_RX_DESC_RX_HT(rxdesc),
411 (u8)GET_RX_DESC_RX_MCS(rxdesc),
412 (bool)GET_RX_DESC_PAGGR(rxdesc)
413 );
414 /* There is a phy status after this rx descriptor. */
415 if (GET_RX_DESC_PHY_STATUS(rxdesc)) {
416 p_drvinfo = (struct rx_fwinfo_92c *)(rxdesc + RTL_RX_DESC_SIZE);
417 rtl92c_translate_rx_signal_stuff(hw, skb, &stats,
418 (struct rx_desc_92c *)rxdesc, p_drvinfo);
419 }
420 skb_pull(skb, (drvinfo_len + RTL_RX_DESC_SIZE));
421 hdr = (struct ieee80211_hdr *)(skb->data);
422 fc = hdr->frame_control;
423 bv = ieee80211_is_probe_resp(fc);
424 if (bv)
425 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
426 ("Got probe response frame.\n"));
427 if (ieee80211_is_beacon(fc))
428 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
429 ("Got beacon frame.\n"));
430 if (ieee80211_is_data(fc))
431 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Got data frame.\n"));
432 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
433 ("Fram: fc = 0x%X addr1 = 0x%02X:0x%02X:0x%02X:0x%02X:0x%02X:"
434 "0x%02X\n", fc, (u32)hdr->addr1[0], (u32)hdr->addr1[1],
435 (u32)hdr->addr1[2], (u32)hdr->addr1[3], (u32)hdr->addr1[4],
436 (u32)hdr->addr1[5]));
437 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
438 ieee80211_rx_irqsafe(hw, skb);
439}
440
441void rtl8192cu_rx_hdl(struct ieee80211_hw *hw, struct sk_buff * skb)
442{
443 _rtl_rx_process(hw, skb);
444}
445
446void rtl8192c_rx_segregate_hdl(
447 struct ieee80211_hw *hw,
448 struct sk_buff *skb,
449 struct sk_buff_head *skb_list)
450{
451}
452
453/*----------------------------------------------------------------------
454 *
455 * Tx handler
456 *
457 *---------------------------------------------------------------------- */
458void rtl8192c_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb)
459{
460}
461
462int rtl8192c_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb,
463 struct sk_buff *skb)
464{
465 return 0;
466}
467
468struct sk_buff *rtl8192c_tx_aggregate_hdl(struct ieee80211_hw *hw,
469 struct sk_buff_head *list)
470{
471 return skb_dequeue(list);
472}
473
474/*======================================== trx ===============================*/
475
476static void _rtl_fill_usb_tx_desc(u8 *txdesc)
477{
478 SET_TX_DESC_OWN(txdesc, 1);
479 SET_TX_DESC_LAST_SEG(txdesc, 1);
480 SET_TX_DESC_FIRST_SEG(txdesc, 1);
481}
482/**
483 * For HW recovery information
484 */
485static void _rtl_tx_desc_checksum(u8 *txdesc)
486{
487 u16 *ptr = (u16 *)txdesc;
488 u16 checksum = 0;
489 u32 index;
490
491 /* Clear first */
492 SET_TX_DESC_TX_DESC_CHECKSUM(txdesc, 0);
493 for (index = 0; index < 16; index++)
494 checksum = checksum ^ (*(ptr + index));
495 SET_TX_DESC_TX_DESC_CHECKSUM(txdesc, checksum);
496}
497
498void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw,
499 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
500 struct ieee80211_tx_info *info, struct sk_buff *skb,
501 unsigned int queue_index)
502{
503 struct rtl_priv *rtlpriv = rtl_priv(hw);
504 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
505 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
506 bool defaultadapter = true;
507 struct ieee80211_sta *sta;
508 struct rtl_tcb_desc tcb_desc;
509 u8 *qc = ieee80211_get_qos_ctl(hdr);
510 u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
511 u16 seq_number;
512 __le16 fc = hdr->frame_control;
513 u8 rate_flag = info->control.rates[0].flags;
514 u16 pktlen = skb->len;
515 enum rtl_desc_qsel fw_qsel = _rtl8192cu_mq_to_descq(hw, fc,
516 skb_get_queue_mapping(skb));
517 u8 *txdesc;
518
519 seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
520 rtl_get_tcb_desc(hw, info, skb, &tcb_desc);
521 txdesc = (u8 *)skb_push(skb, RTL_TX_HEADER_SIZE);
522 memset(txdesc, 0, RTL_TX_HEADER_SIZE);
523 SET_TX_DESC_PKT_SIZE(txdesc, pktlen);
524 SET_TX_DESC_LINIP(txdesc, 0);
525 SET_TX_DESC_PKT_OFFSET(txdesc, RTL_DUMMY_OFFSET);
526 SET_TX_DESC_OFFSET(txdesc, RTL_TX_HEADER_SIZE);
527 SET_TX_DESC_TX_RATE(txdesc, tcb_desc.hw_rate);
528 if (tcb_desc.use_shortgi || tcb_desc.use_shortpreamble)
529 SET_TX_DESC_DATA_SHORTGI(txdesc, 1);
530 if (mac->tids[tid].agg.agg_state == RTL_AGG_ON &&
531 info->flags & IEEE80211_TX_CTL_AMPDU) {
532 SET_TX_DESC_AGG_ENABLE(txdesc, 1);
533 SET_TX_DESC_MAX_AGG_NUM(txdesc, 0x14);
534 } else {
535 SET_TX_DESC_AGG_BREAK(txdesc, 1);
536 }
537 SET_TX_DESC_SEQ(txdesc, seq_number);
538 SET_TX_DESC_RTS_ENABLE(txdesc, ((tcb_desc.rts_enable &&
539 !tcb_desc.cts_enable) ? 1 : 0));
540 SET_TX_DESC_HW_RTS_ENABLE(txdesc, ((tcb_desc.rts_enable ||
541 tcb_desc.cts_enable) ? 1 : 0));
542 SET_TX_DESC_CTS2SELF(txdesc, ((tcb_desc.cts_enable) ? 1 : 0));
543 SET_TX_DESC_RTS_STBC(txdesc, ((tcb_desc.rts_stbc) ? 1 : 0));
544 SET_TX_DESC_RTS_RATE(txdesc, tcb_desc.rts_rate);
545 SET_TX_DESC_RTS_BW(txdesc, 0);
546 SET_TX_DESC_RTS_SC(txdesc, tcb_desc.rts_sc);
547 SET_TX_DESC_RTS_SHORT(txdesc,
548 ((tcb_desc.rts_rate <= DESC92C_RATE54M) ?
549 (tcb_desc.rts_use_shortpreamble ? 1 : 0)
550 : (tcb_desc.rts_use_shortgi ? 1 : 0)));
551 if (mac->bw_40) {
552 if (tcb_desc.packet_bw) {
553 SET_TX_DESC_DATA_BW(txdesc, 1);
554 SET_TX_DESC_DATA_SC(txdesc, 3);
555 } else {
556 SET_TX_DESC_DATA_BW(txdesc, 0);
557 if (rate_flag & IEEE80211_TX_RC_DUP_DATA)
558 SET_TX_DESC_DATA_SC(txdesc,
559 mac->cur_40_prime_sc);
560 }
561 } else {
562 SET_TX_DESC_DATA_BW(txdesc, 0);
563 SET_TX_DESC_DATA_SC(txdesc, 0);
564 }
565 rcu_read_lock();
566 sta = ieee80211_find_sta(mac->vif, mac->bssid);
567 if (sta) {
568 u8 ampdu_density = sta->ht_cap.ampdu_density;
569 SET_TX_DESC_AMPDU_DENSITY(txdesc, ampdu_density);
570 }
571 rcu_read_unlock();
572 if (info->control.hw_key) {
573 struct ieee80211_key_conf *keyconf = info->control.hw_key;
574 switch (keyconf->cipher) {
575 case WLAN_CIPHER_SUITE_WEP40:
576 case WLAN_CIPHER_SUITE_WEP104:
577 case WLAN_CIPHER_SUITE_TKIP:
578 SET_TX_DESC_SEC_TYPE(txdesc, 0x1);
579 break;
580 case WLAN_CIPHER_SUITE_CCMP:
581 SET_TX_DESC_SEC_TYPE(txdesc, 0x3);
582 break;
583 default:
584 SET_TX_DESC_SEC_TYPE(txdesc, 0x0);
585 break;
586 }
587 }
588 SET_TX_DESC_PKT_ID(txdesc, 0);
589 SET_TX_DESC_QUEUE_SEL(txdesc, fw_qsel);
590 SET_TX_DESC_DATA_RATE_FB_LIMIT(txdesc, 0x1F);
591 SET_TX_DESC_RTS_RATE_FB_LIMIT(txdesc, 0xF);
592 SET_TX_DESC_DISABLE_FB(txdesc, 0);
593 SET_TX_DESC_USE_RATE(txdesc, tcb_desc.use_driver_rate ? 1 : 0);
594 if (ieee80211_is_data_qos(fc)) {
595 if (mac->rdg_en) {
596 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
597 ("Enable RDG function.\n"));
598 SET_TX_DESC_RDG_ENABLE(txdesc, 1);
599 SET_TX_DESC_HTC(txdesc, 1);
600 }
601 }
602 if (rtlpriv->dm.useramask) {
603 SET_TX_DESC_RATE_ID(txdesc, tcb_desc.ratr_index);
604 SET_TX_DESC_MACID(txdesc, tcb_desc.mac_id);
605 } else {
606 SET_TX_DESC_RATE_ID(txdesc, 0xC + tcb_desc.ratr_index);
607 SET_TX_DESC_MACID(txdesc, tcb_desc.ratr_index);
608 }
609 if ((!ieee80211_is_data_qos(fc)) && ppsc->leisure_ps &&
610 ppsc->fwctrl_lps) {
611 SET_TX_DESC_HWSEQ_EN(txdesc, 1);
612 SET_TX_DESC_PKT_ID(txdesc, 8);
613 if (!defaultadapter)
614 SET_TX_DESC_QOS(txdesc, 1);
615 }
616 if (ieee80211_has_morefrags(fc))
617 SET_TX_DESC_MORE_FRAG(txdesc, 1);
618 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
619 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
620 SET_TX_DESC_BMC(txdesc, 1);
621 _rtl_fill_usb_tx_desc(txdesc);
622 _rtl_tx_desc_checksum(txdesc);
623 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, (" %s ==>\n", __func__));
624}
625
626void rtl92cu_fill_fake_txdesc(struct ieee80211_hw *hw, u8 * pDesc,
627 u32 buffer_len, bool bIsPsPoll)
628{
629 /* Clear all status */
630 memset(pDesc, 0, RTL_TX_HEADER_SIZE);
631 SET_TX_DESC_FIRST_SEG(pDesc, 1); /* bFirstSeg; */
632 SET_TX_DESC_LAST_SEG(pDesc, 1); /* bLastSeg; */
633 SET_TX_DESC_OFFSET(pDesc, RTL_TX_HEADER_SIZE); /* Offset = 32 */
634 SET_TX_DESC_PKT_SIZE(pDesc, buffer_len); /* Buffer size + command hdr */
635 SET_TX_DESC_QUEUE_SEL(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */
636 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error
637 * vlaue by Hw. */
638 if (bIsPsPoll) {
639 SET_TX_DESC_NAV_USE_HDR(pDesc, 1);
640 } else {
641 SET_TX_DESC_HWSEQ_EN(pDesc, 1); /* Hw set sequence number */
642 SET_TX_DESC_PKT_ID(pDesc, 0x100); /* set bit3 to 1. */
643 }
644 SET_TX_DESC_USE_RATE(pDesc, 1); /* use data rate which is set by Sw */
645 SET_TX_DESC_OWN(pDesc, 1);
646 SET_TX_DESC_TX_RATE(pDesc, DESC92C_RATE1M);
647 _rtl_tx_desc_checksum(pDesc);
648}
649
650void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw,
651 u8 *pdesc, bool firstseg,
652 bool lastseg, struct sk_buff *skb)
653{
654 struct rtl_priv *rtlpriv = rtl_priv(hw);
655 u8 fw_queue = QSLT_BEACON;
656 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
657 __le16 fc = hdr->frame_control;
658
659 memset((void *)pdesc, 0, RTL_TX_HEADER_SIZE);
660 if (firstseg)
661 SET_TX_DESC_OFFSET(pdesc, RTL_TX_HEADER_SIZE);
662 SET_TX_DESC_TX_RATE(pdesc, DESC92C_RATE1M);
663 SET_TX_DESC_SEQ(pdesc, 0);
664 SET_TX_DESC_LINIP(pdesc, 0);
665 SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
666 SET_TX_DESC_FIRST_SEG(pdesc, 1);
667 SET_TX_DESC_LAST_SEG(pdesc, 1);
668 SET_TX_DESC_RATE_ID(pdesc, 7);
669 SET_TX_DESC_MACID(pdesc, 0);
670 SET_TX_DESC_OWN(pdesc, 1);
671 SET_TX_DESC_PKT_SIZE((u8 *) pdesc, (u16) (skb->len));
672 SET_TX_DESC_FIRST_SEG(pdesc, 1);
673 SET_TX_DESC_LAST_SEG(pdesc, 1);
674 SET_TX_DESC_OFFSET(pdesc, 0x20);
675 SET_TX_DESC_USE_RATE(pdesc, 1);
676 if (!ieee80211_is_data_qos(fc)) {
677 SET_TX_DESC_HWSEQ_EN(pdesc, 1);
678 SET_TX_DESC_PKT_ID(pdesc, 8);
679 }
680 RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD, "H2C Tx Cmd Content\n",
681 pdesc, RTL_TX_DESC_SIZE);
682}
683
684bool rtl92cu_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)
685{
686 return true;
687}
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/trx.h b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.h
new file mode 100644
index 000000000000..b396d46edbb7
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/trx.h
@@ -0,0 +1,430 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2010 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30#ifndef __RTL92CU_TRX_H__
31#define __RTL92CU_TRX_H__
32
33#define RTL92C_USB_BULK_IN_NUM 1
34#define RTL92C_NUM_RX_URBS 8
35#define RTL92C_NUM_TX_URBS 32
36
37#define RTL92C_SIZE_MAX_RX_BUFFER 15360 /* 8192 */
38#define RX_DRV_INFO_SIZE_UNIT 8
39
40enum usb_rx_agg_mode {
41 USB_RX_AGG_DISABLE,
42 USB_RX_AGG_DMA,
43 USB_RX_AGG_USB,
44 USB_RX_AGG_DMA_USB
45};
46
47#define TX_SELE_HQ BIT(0) /* High Queue */
48#define TX_SELE_LQ BIT(1) /* Low Queue */
49#define TX_SELE_NQ BIT(2) /* Normal Queue */
50
51#define RTL_USB_TX_AGG_NUM_DESC 5
52
53#define RTL_USB_RX_AGG_PAGE_NUM 4
54#define RTL_USB_RX_AGG_PAGE_TIMEOUT 3
55
56#define RTL_USB_RX_AGG_BLOCK_NUM 5
57#define RTL_USB_RX_AGG_BLOCK_TIMEOUT 3
58
59/*======================== rx status =========================================*/
60
61struct rx_drv_info_92c {
62 /*
63 * Driver info contain PHY status and other variabel size info
64 * PHY Status content as below
65 */
66
67 /* DWORD 0 */
68 u8 gain_trsw[4];
69
70 /* DWORD 1 */
71 u8 pwdb_all;
72 u8 cfosho[4];
73
74 /* DWORD 2 */
75 u8 cfotail[4];
76
77 /* DWORD 3 */
78 s8 rxevm[2];
79 s8 rxsnr[4];
80
81 /* DWORD 4 */
82 u8 pdsnr[2];
83
84 /* DWORD 5 */
85 u8 csi_current[2];
86 u8 csi_target[2];
87
88 /* DWORD 6 */
89 u8 sigevm;
90 u8 max_ex_pwr;
91 u8 ex_intf_flag:1;
92 u8 sgi_en:1;
93 u8 rxsc:2;
94 u8 reserve:4;
95} __packed;
96
97/* Define a macro that takes a le32 word, converts it to host ordering,
98 * right shifts by a specified count, creates a mask of the specified
99 * bit count, and extracts that number of bits.
100 */
101
102#define SHIFT_AND_MASK_LE(__pdesc, __shift, __bits) \
103 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
104 BIT_LEN_MASK_32(__bits))
105
106/* Define a macro that clears a bit field in an le32 word and
107 * sets the specified value into that bit field. The resulting
108 * value remains in le32 ordering; however, it is properly converted
109 * to host ordering for the clear and set operations before conversion
110 * back to le32.
111 */
112
113#define SET_BITS_OFFSET_LE(__pdesc, __shift, __len, __val) \
114 (*(__le32 *)(__pdesc) = \
115 (cpu_to_le32((le32_to_cpu(*((__le32 *)(__pdesc))) & \
116 (~(BIT_OFFSET_LEN_MASK_32((__shift), __len)))) | \
117 (((u32)(__val) & BIT_LEN_MASK_32(__len)) << (__shift)))));
118
119/* macros to read various fields in RX descriptor */
120
121/* DWORD 0 */
122#define GET_RX_DESC_PKT_LEN(__rxdesc) \
123 SHIFT_AND_MASK_LE((__rxdesc), 0, 14)
124#define GET_RX_DESC_CRC32(__rxdesc) \
125 SHIFT_AND_MASK_LE(__rxdesc, 14, 1)
126#define GET_RX_DESC_ICV(__rxdesc) \
127 SHIFT_AND_MASK_LE(__rxdesc, 15, 1)
128#define GET_RX_DESC_DRVINFO_SIZE(__rxdesc) \
129 SHIFT_AND_MASK_LE(__rxdesc, 16, 4)
130#define GET_RX_DESC_SECURITY(__rxdesc) \
131 SHIFT_AND_MASK_LE(__rxdesc, 20, 3)
132#define GET_RX_DESC_QOS(__rxdesc) \
133 SHIFT_AND_MASK_LE(__rxdesc, 23, 1)
134#define GET_RX_DESC_SHIFT(__rxdesc) \
135 SHIFT_AND_MASK_LE(__rxdesc, 24, 2)
136#define GET_RX_DESC_PHY_STATUS(__rxdesc) \
137 SHIFT_AND_MASK_LE(__rxdesc, 26, 1)
138#define GET_RX_DESC_SWDEC(__rxdesc) \
139 SHIFT_AND_MASK_LE(__rxdesc, 27, 1)
140#define GET_RX_DESC_LAST_SEG(__rxdesc) \
141 SHIFT_AND_MASK_LE(__rxdesc, 28, 1)
142#define GET_RX_DESC_FIRST_SEG(__rxdesc) \
143 SHIFT_AND_MASK_LE(__rxdesc, 29, 1)
144#define GET_RX_DESC_EOR(__rxdesc) \
145 SHIFT_AND_MASK_LE(__rxdesc, 30, 1)
146#define GET_RX_DESC_OWN(__rxdesc) \
147 SHIFT_AND_MASK_LE(__rxdesc, 31, 1)
148
149/* DWORD 1 */
150#define GET_RX_DESC_MACID(__rxdesc) \
151 SHIFT_AND_MASK_LE(__rxdesc+4, 0, 5)
152#define GET_RX_DESC_TID(__rxdesc) \
153 SHIFT_AND_MASK_LE(__rxdesc+4, 5, 4)
154#define GET_RX_DESC_PAGGR(__rxdesc) \
155 SHIFT_AND_MASK_LE(__rxdesc+4, 14, 1)
156#define GET_RX_DESC_FAGGR(__rxdesc) \
157 SHIFT_AND_MASK_LE(__rxdesc+4, 15, 1)
158#define GET_RX_DESC_A1_FIT(__rxdesc) \
159 SHIFT_AND_MASK_LE(__rxdesc+4, 16, 4)
160#define GET_RX_DESC_A2_FIT(__rxdesc) \
161 SHIFT_AND_MASK_LE(__rxdesc+4, 20, 4)
162#define GET_RX_DESC_PAM(__rxdesc) \
163 SHIFT_AND_MASK_LE(__rxdesc+4, 24, 1)
164#define GET_RX_DESC_PWR(__rxdesc) \
165 SHIFT_AND_MASK_LE(__rxdesc+4, 25, 1)
166#define GET_RX_DESC_MORE_DATA(__rxdesc) \
167 SHIFT_AND_MASK_LE(__rxdesc+4, 26, 1)
168#define GET_RX_DESC_MORE_FRAG(__rxdesc) \
169 SHIFT_AND_MASK_LE(__rxdesc+4, 27, 1)
170#define GET_RX_DESC_TYPE(__rxdesc) \
171 SHIFT_AND_MASK_LE(__rxdesc+4, 28, 2)
172#define GET_RX_DESC_MC(__rxdesc) \
173 SHIFT_AND_MASK_LE(__rxdesc+4, 30, 1)
174#define GET_RX_DESC_BC(__rxdesc) \
175 SHIFT_AND_MASK_LE(__rxdesc+4, 31, 1)
176
177/* DWORD 2 */
178#define GET_RX_DESC_SEQ(__rxdesc) \
179 SHIFT_AND_MASK_LE(__rxdesc+8, 0, 12)
180#define GET_RX_DESC_FRAG(__rxdesc) \
181 SHIFT_AND_MASK_LE(__rxdesc+8, 12, 4)
182#define GET_RX_DESC_USB_AGG_PKTNUM(__rxdesc) \
183 SHIFT_AND_MASK_LE(__rxdesc+8, 16, 8)
184#define GET_RX_DESC_NEXT_IND(__rxdesc) \
185 SHIFT_AND_MASK_LE(__rxdesc+8, 30, 1)
186
187/* DWORD 3 */
188#define GET_RX_DESC_RX_MCS(__rxdesc) \
189 SHIFT_AND_MASK_LE(__rxdesc+12, 0, 6)
190#define GET_RX_DESC_RX_HT(__rxdesc) \
191 SHIFT_AND_MASK_LE(__rxdesc+12, 6, 1)
192#define GET_RX_DESC_AMSDU(__rxdesc) \
193 SHIFT_AND_MASK_LE(__rxdesc+12, 7, 1)
194#define GET_RX_DESC_SPLCP(__rxdesc) \
195 SHIFT_AND_MASK_LE(__rxdesc+12, 8, 1)
196#define GET_RX_DESC_BW(__rxdesc) \
197 SHIFT_AND_MASK_LE(__rxdesc+12, 9, 1)
198#define GET_RX_DESC_HTC(__rxdesc) \
199 SHIFT_AND_MASK_LE(__rxdesc+12, 10, 1)
200#define GET_RX_DESC_TCP_CHK_RPT(__rxdesc) \
201 SHIFT_AND_MASK_LE(__rxdesc+12, 11, 1)
202#define GET_RX_DESC_IP_CHK_RPT(__rxdesc) \
203 SHIFT_AND_MASK_LE(__rxdesc+12, 12, 1)
204#define GET_RX_DESC_TCP_CHK_VALID(__rxdesc) \
205 SHIFT_AND_MASK_LE(__rxdesc+12, 13, 1)
206#define GET_RX_DESC_HWPC_ERR(__rxdesc) \
207 SHIFT_AND_MASK_LE(__rxdesc+12, 14, 1)
208#define GET_RX_DESC_HWPC_IND(__rxdesc) \
209 SHIFT_AND_MASK_LE(__rxdesc+12, 15, 1)
210#define GET_RX_DESC_IV0(__rxdesc) \
211 SHIFT_AND_MASK_LE(__rxdesc+12, 16, 16)
212
213/* DWORD 4 */
214#define GET_RX_DESC_IV1(__rxdesc) \
215 SHIFT_AND_MASK_LE(__rxdesc+16, 0, 32)
216
217/* DWORD 5 */
218#define GET_RX_DESC_TSFL(__rxdesc) \
219 SHIFT_AND_MASK_LE(__rxdesc+20, 0, 32)
220
221/*======================= tx desc ============================================*/
222
223/* macros to set various fields in TX descriptor */
224
225/* Dword 0 */
226#define SET_TX_DESC_PKT_SIZE(__txdesc, __value) \
227 SET_BITS_OFFSET_LE(__txdesc, 0, 16, __value)
228#define SET_TX_DESC_OFFSET(__txdesc, __value) \
229 SET_BITS_OFFSET_LE(__txdesc, 16, 8, __value)
230#define SET_TX_DESC_BMC(__txdesc, __value) \
231 SET_BITS_OFFSET_LE(__txdesc, 24, 1, __value)
232#define SET_TX_DESC_HTC(__txdesc, __value) \
233 SET_BITS_OFFSET_LE(__txdesc, 25, 1, __value)
234#define SET_TX_DESC_LAST_SEG(__txdesc, __value) \
235 SET_BITS_OFFSET_LE(__txdesc, 26, 1, __value)
236#define SET_TX_DESC_FIRST_SEG(__txdesc, __value) \
237 SET_BITS_OFFSET_LE(__txdesc, 27, 1, __value)
238#define SET_TX_DESC_LINIP(__txdesc, __value) \
239 SET_BITS_OFFSET_LE(__txdesc, 28, 1, __value)
240#define SET_TX_DESC_NO_ACM(__txdesc, __value) \
241 SET_BITS_OFFSET_LE(__txdesc, 29, 1, __value)
242#define SET_TX_DESC_GF(__txdesc, __value) \
243 SET_BITS_OFFSET_LE(__txdesc, 30, 1, __value)
244#define SET_TX_DESC_OWN(__txdesc, __value) \
245 SET_BITS_OFFSET_LE(__txdesc, 31, 1, __value)
246
247
248/* Dword 1 */
249#define SET_TX_DESC_MACID(__txdesc, __value) \
250 SET_BITS_OFFSET_LE(__txdesc+4, 0, 5, __value)
251#define SET_TX_DESC_AGG_ENABLE(__txdesc, __value) \
252 SET_BITS_OFFSET_LE(__txdesc+4, 5, 1, __value)
253#define SET_TX_DESC_AGG_BREAK(__txdesc, __value) \
254 SET_BITS_OFFSET_LE(__txdesc+4, 6, 1, __value)
255#define SET_TX_DESC_RDG_ENABLE(__txdesc, __value) \
256 SET_BITS_OFFSET_LE(__txdesc+4, 7, 1, __value)
257#define SET_TX_DESC_QUEUE_SEL(__txdesc, __value) \
258 SET_BITS_OFFSET_LE(__txdesc+4, 8, 5, __value)
259#define SET_TX_DESC_RDG_NAV_EXT(__txdesc, __value) \
260 SET_BITS_OFFSET_LE(__txdesc+4, 13, 1, __value)
261#define SET_TX_DESC_LSIG_TXOP_EN(__txdesc, __value) \
262 SET_BITS_OFFSET_LE(__txdesc+4, 14, 1, __value)
263#define SET_TX_DESC_PIFS(__txdesc, __value) \
264 SET_BITS_OFFSET_LE(__txdesc+4, 15, 1, __value)
265#define SET_TX_DESC_RATE_ID(__txdesc, __value) \
266 SET_BITS_OFFSET_LE(__txdesc+4, 16, 4, __value)
267#define SET_TX_DESC_RA_BRSR_ID(__txdesc, __value) \
268 SET_BITS_OFFSET_LE(__txdesc+4, 16, 4, __value)
269#define SET_TX_DESC_NAV_USE_HDR(__txdesc, __value) \
270 SET_BITS_OFFSET_LE(__txdesc+4, 20, 1, __value)
271#define SET_TX_DESC_EN_DESC_ID(__txdesc, __value) \
272 SET_BITS_OFFSET_LE(__txdesc+4, 21, 1, __value)
273#define SET_TX_DESC_SEC_TYPE(__txdesc, __value) \
274 SET_BITS_OFFSET_LE(__txdesc+4, 22, 2, __value)
275#define SET_TX_DESC_PKT_OFFSET(__txdesc, __value) \
276 SET_BITS_OFFSET_LE(__txdesc+4, 26, 5, __value)
277
278/* Dword 2 */
279#define SET_TX_DESC_RTS_RC(__txdesc, __value) \
280 SET_BITS_OFFSET_LE(__txdesc+8, 0, 6, __value)
281#define SET_TX_DESC_DATA_RC(__txdesc, __value) \
282 SET_BITS_OFFSET_LE(__txdesc+8, 6, 6, __value)
283#define SET_TX_DESC_BAR_RTY_TH(__txdesc, __value) \
284 SET_BITS_OFFSET_LE(__txdesc+8, 14, 2, __value)
285#define SET_TX_DESC_MORE_FRAG(__txdesc, __value) \
286 SET_BITS_OFFSET_LE(__txdesc+8, 17, 1, __value)
287#define SET_TX_DESC_RAW(__txdesc, __value) \
288 SET_BITS_OFFSET_LE(__txdesc+8, 18, 1, __value)
289#define SET_TX_DESC_CCX(__txdesc, __value) \
290 SET_BITS_OFFSET_LE(__txdesc+8, 19, 1, __value)
291#define SET_TX_DESC_AMPDU_DENSITY(__txdesc, __value) \
292 SET_BITS_OFFSET_LE(__txdesc+8, 20, 3, __value)
293#define SET_TX_DESC_ANTSEL_A(__txdesc, __value) \
294 SET_BITS_OFFSET_LE(__txdesc+8, 24, 1, __value)
295#define SET_TX_DESC_ANTSEL_B(__txdesc, __value) \
296 SET_BITS_OFFSET_LE(__txdesc+8, 25, 1, __value)
297#define SET_TX_DESC_TX_ANT_CCK(__txdesc, __value) \
298 SET_BITS_OFFSET_LE(__txdesc+8, 26, 2, __value)
299#define SET_TX_DESC_TX_ANTL(__txdesc, __value) \
300 SET_BITS_OFFSET_LE(__txdesc+8, 28, 2, __value)
301#define SET_TX_DESC_TX_ANT_HT(__txdesc, __value) \
302 SET_BITS_OFFSET_LE(__txdesc+8, 30, 2, __value)
303
304/* Dword 3 */
305#define SET_TX_DESC_NEXT_HEAP_PAGE(__txdesc, __value) \
306 SET_BITS_OFFSET_LE(__txdesc+12, 0, 8, __value)
307#define SET_TX_DESC_TAIL_PAGE(__txdesc, __value) \
308 SET_BITS_OFFSET_LE(__txdesc+12, 8, 8, __value)
309#define SET_TX_DESC_SEQ(__txdesc, __value) \
310 SET_BITS_OFFSET_LE(__txdesc+12, 16, 12, __value)
311#define SET_TX_DESC_PKT_ID(__txdesc, __value) \
312 SET_BITS_OFFSET_LE(__txdesc+12, 28, 4, __value)
313
314/* Dword 4 */
315#define SET_TX_DESC_RTS_RATE(__txdesc, __value) \
316 SET_BITS_OFFSET_LE(__txdesc+16, 0, 5, __value)
317#define SET_TX_DESC_AP_DCFE(__txdesc, __value) \
318 SET_BITS_OFFSET_LE(__txdesc+16, 5, 1, __value)
319#define SET_TX_DESC_QOS(__txdesc, __value) \
320 SET_BITS_OFFSET_LE(__txdesc+16, 6, 1, __value)
321#define SET_TX_DESC_HWSEQ_EN(__txdesc, __value) \
322 SET_BITS_OFFSET_LE(__txdesc+16, 7, 1, __value)
323#define SET_TX_DESC_USE_RATE(__txdesc, __value) \
324 SET_BITS_OFFSET_LE(__txdesc+16, 8, 1, __value)
325#define SET_TX_DESC_DISABLE_RTS_FB(__txdesc, __value) \
326 SET_BITS_OFFSET_LE(__txdesc+16, 9, 1, __value)
327#define SET_TX_DESC_DISABLE_FB(__txdesc, __value) \
328 SET_BITS_OFFSET_LE(__txdesc+16, 10, 1, __value)
329#define SET_TX_DESC_CTS2SELF(__txdesc, __value) \
330 SET_BITS_OFFSET_LE(__txdesc+16, 11, 1, __value)
331#define SET_TX_DESC_RTS_ENABLE(__txdesc, __value) \
332 SET_BITS_OFFSET_LE(__txdesc+16, 12, 1, __value)
333#define SET_TX_DESC_HW_RTS_ENABLE(__txdesc, __value) \
334 SET_BITS_OFFSET_LE(__txdesc+16, 13, 1, __value)
335#define SET_TX_DESC_WAIT_DCTS(__txdesc, __value) \
336 SET_BITS_OFFSET_LE(__txdesc+16, 18, 1, __value)
337#define SET_TX_DESC_CTS2AP_EN(__txdesc, __value) \
338 SET_BITS_OFFSET_LE(__txdesc+16, 19, 1, __value)
339#define SET_TX_DESC_DATA_SC(__txdesc, __value) \
340 SET_BITS_OFFSET_LE(__txdesc+16, 20, 2, __value)
341#define SET_TX_DESC_DATA_STBC(__txdesc, __value) \
342 SET_BITS_OFFSET_LE(__txdesc+16, 22, 2, __value)
343#define SET_TX_DESC_DATA_SHORT(__txdesc, __value) \
344 SET_BITS_OFFSET_LE(__txdesc+16, 24, 1, __value)
345#define SET_TX_DESC_DATA_BW(__txdesc, __value) \
346 SET_BITS_OFFSET_LE(__txdesc+16, 25, 1, __value)
347#define SET_TX_DESC_RTS_SHORT(__txdesc, __value) \
348 SET_BITS_OFFSET_LE(__txdesc+16, 26, 1, __value)
349#define SET_TX_DESC_RTS_BW(__txdesc, __value) \
350 SET_BITS_OFFSET_LE(__txdesc+16, 27, 1, __value)
351#define SET_TX_DESC_RTS_SC(__txdesc, __value) \
352 SET_BITS_OFFSET_LE(__txdesc+16, 28, 2, __value)
353#define SET_TX_DESC_RTS_STBC(__txdesc, __value) \
354 SET_BITS_OFFSET_LE(__txdesc+16, 30, 2, __value)
355
356/* Dword 5 */
357#define SET_TX_DESC_TX_RATE(__pdesc, __val) \
358 SET_BITS_OFFSET_LE(__pdesc+20, 0, 6, __val)
359#define SET_TX_DESC_DATA_SHORTGI(__pdesc, __val) \
360 SET_BITS_OFFSET_LE(__pdesc+20, 6, 1, __val)
361#define SET_TX_DESC_CCX_TAG(__pdesc, __val) \
362 SET_BITS_OFFSET_LE(__pdesc+20, 7, 1, __val)
363#define SET_TX_DESC_DATA_RATE_FB_LIMIT(__txdesc, __value) \
364 SET_BITS_OFFSET_LE(__txdesc+20, 8, 5, __value)
365#define SET_TX_DESC_RTS_RATE_FB_LIMIT(__txdesc, __value) \
366 SET_BITS_OFFSET_LE(__txdesc+20, 13, 4, __value)
367#define SET_TX_DESC_RETRY_LIMIT_ENABLE(__txdesc, __value) \
368 SET_BITS_OFFSET_LE(__txdesc+20, 17, 1, __value)
369#define SET_TX_DESC_DATA_RETRY_LIMIT(__txdesc, __value) \
370 SET_BITS_OFFSET_LE(__txdesc+20, 18, 6, __value)
371#define SET_TX_DESC_USB_TXAGG_NUM(__txdesc, __value) \
372 SET_BITS_OFFSET_LE(__txdesc+20, 24, 8, __value)
373
374/* Dword 6 */
375#define SET_TX_DESC_TXAGC_A(__txdesc, __value) \
376 SET_BITS_OFFSET_LE(__txdesc+24, 0, 5, __value)
377#define SET_TX_DESC_TXAGC_B(__txdesc, __value) \
378 SET_BITS_OFFSET_LE(__txdesc+24, 5, 5, __value)
379#define SET_TX_DESC_USB_MAX_LEN(__txdesc, __value) \
380 SET_BITS_OFFSET_LE(__txdesc+24, 10, 1, __value)
381#define SET_TX_DESC_MAX_AGG_NUM(__txdesc, __value) \
382 SET_BITS_OFFSET_LE(__txdesc+24, 11, 5, __value)
383#define SET_TX_DESC_MCSG1_MAX_LEN(__txdesc, __value) \
384 SET_BITS_OFFSET_LE(__txdesc+24, 16, 4, __value)
385#define SET_TX_DESC_MCSG2_MAX_LEN(__txdesc, __value) \
386 SET_BITS_OFFSET_LE(__txdesc+24, 20, 4, __value)
387#define SET_TX_DESC_MCSG3_MAX_LEN(__txdesc, __value) \
388 SET_BITS_OFFSET_LE(__txdesc+24, 24, 4, __value)
389#define SET_TX_DESC_MCSG7_MAX_LEN(__txdesc, __value) \
390 SET_BITS_OFFSET_LE(__txdesc+24, 28, 4, __value)
391
392/* Dword 7 */
393#define SET_TX_DESC_TX_DESC_CHECKSUM(__txdesc, __value) \
394 SET_BITS_OFFSET_LE(__txdesc+28, 0, 16, __value)
395#define SET_TX_DESC_MCSG4_MAX_LEN(__txdesc, __value) \
396 SET_BITS_OFFSET_LE(__txdesc+28, 16, 4, __value)
397#define SET_TX_DESC_MCSG5_MAX_LEN(__txdesc, __value) \
398 SET_BITS_OFFSET_LE(__txdesc+28, 20, 4, __value)
399#define SET_TX_DESC_MCSG6_MAX_LEN(__txdesc, __value) \
400 SET_BITS_OFFSET_LE(__txdesc+28, 24, 4, __value)
401#define SET_TX_DESC_MCSG15_MAX_LEN(__txdesc, __value) \
402 SET_BITS_OFFSET_LE(__txdesc+28, 28, 4, __value)
403
404
405int rtl8192cu_endpoint_mapping(struct ieee80211_hw *hw);
406u16 rtl8192cu_mq_to_hwq(__le16 fc, u16 mac80211_queue_index);
407bool rtl92cu_rx_query_desc(struct ieee80211_hw *hw,
408 struct rtl_stats *stats,
409 struct ieee80211_rx_status *rx_status,
410 u8 *p_desc, struct sk_buff *skb);
411void rtl8192cu_rx_hdl(struct ieee80211_hw *hw, struct sk_buff * skb);
412void rtl8192c_rx_segregate_hdl(struct ieee80211_hw *, struct sk_buff *,
413 struct sk_buff_head *);
414void rtl8192c_tx_cleanup(struct ieee80211_hw *hw, struct sk_buff *skb);
415int rtl8192c_tx_post_hdl(struct ieee80211_hw *hw, struct urb *urb,
416 struct sk_buff *skb);
417struct sk_buff *rtl8192c_tx_aggregate_hdl(struct ieee80211_hw *,
418 struct sk_buff_head *);
419void rtl92cu_tx_fill_desc(struct ieee80211_hw *hw,
420 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
421 struct ieee80211_tx_info *info, struct sk_buff *skb,
422 unsigned int queue_index);
423void rtl92cu_fill_fake_txdesc(struct ieee80211_hw *hw, u8 * pDesc,
424 u32 buffer_len, bool bIsPsPoll);
425void rtl92cu_tx_fill_cmddesc(struct ieee80211_hw *hw,
426 u8 *pdesc, bool b_firstseg,
427 bool b_lastseg, struct sk_buff *skb);
428bool rtl92cu_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb);
429
430#endif
diff --git a/drivers/net/wireless/rtlwifi/usb.c b/drivers/net/wireless/rtlwifi/usb.c
new file mode 100644
index 000000000000..a4b2613d6a8c
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/usb.c
@@ -0,0 +1,1035 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 *****************************************************************************/
27#include <linux/usb.h>
28#include "core.h"
29#include "wifi.h"
30#include "usb.h"
31#include "base.h"
32#include "ps.h"
33
34#define REALTEK_USB_VENQT_READ 0xC0
35#define REALTEK_USB_VENQT_WRITE 0x40
36#define REALTEK_USB_VENQT_CMD_REQ 0x05
37#define REALTEK_USB_VENQT_CMD_IDX 0x00
38
39#define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
40
41static void usbctrl_async_callback(struct urb *urb)
42{
43 if (urb)
44 kfree(urb->context);
45}
46
47static int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request,
48 u16 value, u16 index, void *pdata,
49 u16 len)
50{
51 int rc;
52 unsigned int pipe;
53 u8 reqtype;
54 struct usb_ctrlrequest *dr;
55 struct urb *urb;
56 struct rtl819x_async_write_data {
57 u8 data[REALTEK_USB_VENQT_MAX_BUF_SIZE];
58 struct usb_ctrlrequest dr;
59 } *buf;
60
61 pipe = usb_sndctrlpipe(udev, 0); /* write_out */
62 reqtype = REALTEK_USB_VENQT_WRITE;
63
64 buf = kmalloc(sizeof(*buf), GFP_ATOMIC);
65 if (!buf)
66 return -ENOMEM;
67
68 urb = usb_alloc_urb(0, GFP_ATOMIC);
69 if (!urb) {
70 kfree(buf);
71 return -ENOMEM;
72 }
73
74 dr = &buf->dr;
75
76 dr->bRequestType = reqtype;
77 dr->bRequest = request;
78 dr->wValue = cpu_to_le16(value);
79 dr->wIndex = cpu_to_le16(index);
80 dr->wLength = cpu_to_le16(len);
81 memcpy(buf, pdata, len);
82 usb_fill_control_urb(urb, udev, pipe,
83 (unsigned char *)dr, buf, len,
84 usbctrl_async_callback, buf);
85 rc = usb_submit_urb(urb, GFP_ATOMIC);
86 if (rc < 0)
87 kfree(buf);
88 usb_free_urb(urb);
89 return rc;
90}
91
92static int _usbctrl_vendorreq_sync_read(struct usb_device *udev, u8 request,
93 u16 value, u16 index, void *pdata,
94 u16 len)
95{
96 unsigned int pipe;
97 int status;
98 u8 reqtype;
99
100 pipe = usb_rcvctrlpipe(udev, 0); /* read_in */
101 reqtype = REALTEK_USB_VENQT_READ;
102
103 status = usb_control_msg(udev, pipe, request, reqtype, value, index,
104 pdata, len, 0); /* max. timeout */
105
106 if (status < 0)
107 printk(KERN_ERR "reg 0x%x, usbctrl_vendorreq TimeOut! "
108 "status:0x%x value=0x%x\n", value, status,
109 *(u32 *)pdata);
110 return status;
111}
112
113static u32 _usb_read_sync(struct usb_device *udev, u32 addr, u16 len)
114{
115 u8 request;
116 u16 wvalue;
117 u16 index;
118 u32 *data;
119 u32 ret;
120
121 data = kmalloc(sizeof(u32), GFP_KERNEL);
122 if (!data)
123 return -ENOMEM;
124 request = REALTEK_USB_VENQT_CMD_REQ;
125 index = REALTEK_USB_VENQT_CMD_IDX; /* n/a */
126
127 wvalue = (u16)addr;
128 _usbctrl_vendorreq_sync_read(udev, request, wvalue, index, data, len);
129 ret = *data;
130 kfree(data);
131 return ret;
132}
133
134static u8 _usb_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
135{
136 struct device *dev = rtlpriv->io.dev;
137
138 return (u8)_usb_read_sync(to_usb_device(dev), addr, 1);
139}
140
141static u16 _usb_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
142{
143 struct device *dev = rtlpriv->io.dev;
144
145 return (u16)_usb_read_sync(to_usb_device(dev), addr, 2);
146}
147
148static u32 _usb_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
149{
150 struct device *dev = rtlpriv->io.dev;
151
152 return _usb_read_sync(to_usb_device(dev), addr, 4);
153}
154
155static void _usb_write_async(struct usb_device *udev, u32 addr, u32 val,
156 u16 len)
157{
158 u8 request;
159 u16 wvalue;
160 u16 index;
161 u32 data;
162
163 request = REALTEK_USB_VENQT_CMD_REQ;
164 index = REALTEK_USB_VENQT_CMD_IDX; /* n/a */
165 wvalue = (u16)(addr&0x0000ffff);
166 data = val;
167 _usbctrl_vendorreq_async_write(udev, request, wvalue, index, &data,
168 len);
169}
170
171static void _usb_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
172{
173 struct device *dev = rtlpriv->io.dev;
174
175 _usb_write_async(to_usb_device(dev), addr, val, 1);
176}
177
178static void _usb_write16_async(struct rtl_priv *rtlpriv, u32 addr, u16 val)
179{
180 struct device *dev = rtlpriv->io.dev;
181
182 _usb_write_async(to_usb_device(dev), addr, val, 2);
183}
184
185static void _usb_write32_async(struct rtl_priv *rtlpriv, u32 addr, u32 val)
186{
187 struct device *dev = rtlpriv->io.dev;
188
189 _usb_write_async(to_usb_device(dev), addr, val, 4);
190}
191
192static int _usb_nbytes_read_write(struct usb_device *udev, bool read, u32 addr,
193 u16 len, u8 *pdata)
194{
195 int status;
196 u8 request;
197 u16 wvalue;
198 u16 index;
199
200 request = REALTEK_USB_VENQT_CMD_REQ;
201 index = REALTEK_USB_VENQT_CMD_IDX; /* n/a */
202 wvalue = (u16)addr;
203 if (read)
204 status = _usbctrl_vendorreq_sync_read(udev, request, wvalue,
205 index, pdata, len);
206 else
207 status = _usbctrl_vendorreq_async_write(udev, request, wvalue,
208 index, pdata, len);
209 return status;
210}
211
212static int _usb_readN_sync(struct rtl_priv *rtlpriv, u32 addr, u16 len,
213 u8 *pdata)
214{
215 struct device *dev = rtlpriv->io.dev;
216
217 return _usb_nbytes_read_write(to_usb_device(dev), true, addr, len,
218 pdata);
219}
220
221static int _usb_writeN_async(struct rtl_priv *rtlpriv, u32 addr, u16 len,
222 u8 *pdata)
223{
224 struct device *dev = rtlpriv->io.dev;
225
226 return _usb_nbytes_read_write(to_usb_device(dev), false, addr, len,
227 pdata);
228}
229
230static void _rtl_usb_io_handler_init(struct device *dev,
231 struct ieee80211_hw *hw)
232{
233 struct rtl_priv *rtlpriv = rtl_priv(hw);
234
235 rtlpriv->io.dev = dev;
236 mutex_init(&rtlpriv->io.bb_mutex);
237 rtlpriv->io.write8_async = _usb_write8_async;
238 rtlpriv->io.write16_async = _usb_write16_async;
239 rtlpriv->io.write32_async = _usb_write32_async;
240 rtlpriv->io.writeN_async = _usb_writeN_async;
241 rtlpriv->io.read8_sync = _usb_read8_sync;
242 rtlpriv->io.read16_sync = _usb_read16_sync;
243 rtlpriv->io.read32_sync = _usb_read32_sync;
244 rtlpriv->io.readN_sync = _usb_readN_sync;
245}
246
247static void _rtl_usb_io_handler_release(struct ieee80211_hw *hw)
248{
249 struct rtl_priv *rtlpriv = rtl_priv(hw);
250
251 mutex_destroy(&rtlpriv->io.bb_mutex);
252}
253
254/**
255 *
256 * Default aggregation handler. Do nothing and just return the oldest skb.
257 */
258static struct sk_buff *_none_usb_tx_aggregate_hdl(struct ieee80211_hw *hw,
259 struct sk_buff_head *list)
260{
261 return skb_dequeue(list);
262}
263
264#define IS_HIGH_SPEED_USB(udev) \
265 ((USB_SPEED_HIGH == (udev)->speed) ? true : false)
266
267static int _rtl_usb_init_tx(struct ieee80211_hw *hw)
268{
269 u32 i;
270 struct rtl_priv *rtlpriv = rtl_priv(hw);
271 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
272
273 rtlusb->max_bulk_out_size = IS_HIGH_SPEED_USB(rtlusb->udev)
274 ? USB_HIGH_SPEED_BULK_SIZE
275 : USB_FULL_SPEED_BULK_SIZE;
276
277 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("USB Max Bulk-out Size=%d\n",
278 rtlusb->max_bulk_out_size));
279
280 for (i = 0; i < __RTL_TXQ_NUM; i++) {
281 u32 ep_num = rtlusb->ep_map.ep_mapping[i];
282 if (!ep_num) {
283 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
284 ("Invalid endpoint map setting!\n"));
285 return -EINVAL;
286 }
287 }
288
289 rtlusb->usb_tx_post_hdl =
290 rtlpriv->cfg->usb_interface_cfg->usb_tx_post_hdl;
291 rtlusb->usb_tx_cleanup =
292 rtlpriv->cfg->usb_interface_cfg->usb_tx_cleanup;
293 rtlusb->usb_tx_aggregate_hdl =
294 (rtlpriv->cfg->usb_interface_cfg->usb_tx_aggregate_hdl)
295 ? rtlpriv->cfg->usb_interface_cfg->usb_tx_aggregate_hdl
296 : &_none_usb_tx_aggregate_hdl;
297
298 init_usb_anchor(&rtlusb->tx_submitted);
299 for (i = 0; i < RTL_USB_MAX_EP_NUM; i++) {
300 skb_queue_head_init(&rtlusb->tx_skb_queue[i]);
301 init_usb_anchor(&rtlusb->tx_pending[i]);
302 }
303 return 0;
304}
305
306static int _rtl_usb_init_rx(struct ieee80211_hw *hw)
307{
308 struct rtl_priv *rtlpriv = rtl_priv(hw);
309 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
310 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
311
312 rtlusb->rx_max_size = rtlpriv->cfg->usb_interface_cfg->rx_max_size;
313 rtlusb->rx_urb_num = rtlpriv->cfg->usb_interface_cfg->rx_urb_num;
314 rtlusb->in_ep = rtlpriv->cfg->usb_interface_cfg->in_ep_num;
315 rtlusb->usb_rx_hdl = rtlpriv->cfg->usb_interface_cfg->usb_rx_hdl;
316 rtlusb->usb_rx_segregate_hdl =
317 rtlpriv->cfg->usb_interface_cfg->usb_rx_segregate_hdl;
318
319 printk(KERN_INFO "rtl8192cu: rx_max_size %d, rx_urb_num %d, in_ep %d\n",
320 rtlusb->rx_max_size, rtlusb->rx_urb_num, rtlusb->in_ep);
321 init_usb_anchor(&rtlusb->rx_submitted);
322 return 0;
323}
324
325static int _rtl_usb_init(struct ieee80211_hw *hw)
326{
327 struct rtl_priv *rtlpriv = rtl_priv(hw);
328 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
329 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
330 int err;
331 u8 epidx;
332 struct usb_interface *usb_intf = rtlusb->intf;
333 u8 epnums = usb_intf->cur_altsetting->desc.bNumEndpoints;
334
335 rtlusb->out_ep_nums = rtlusb->in_ep_nums = 0;
336 for (epidx = 0; epidx < epnums; epidx++) {
337 struct usb_endpoint_descriptor *pep_desc;
338 pep_desc = &usb_intf->cur_altsetting->endpoint[epidx].desc;
339
340 if (usb_endpoint_dir_in(pep_desc))
341 rtlusb->in_ep_nums++;
342 else if (usb_endpoint_dir_out(pep_desc))
343 rtlusb->out_ep_nums++;
344
345 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
346 ("USB EP(0x%02x), MaxPacketSize=%d ,Interval=%d.\n",
347 pep_desc->bEndpointAddress, pep_desc->wMaxPacketSize,
348 pep_desc->bInterval));
349 }
350 if (rtlusb->in_ep_nums < rtlpriv->cfg->usb_interface_cfg->in_ep_num)
351 return -EINVAL ;
352
353 /* usb endpoint mapping */
354 err = rtlpriv->cfg->usb_interface_cfg->usb_endpoint_mapping(hw);
355 rtlusb->usb_mq_to_hwq = rtlpriv->cfg->usb_interface_cfg->usb_mq_to_hwq;
356 _rtl_usb_init_tx(hw);
357 _rtl_usb_init_rx(hw);
358 return err;
359}
360
361static int _rtl_usb_init_sw(struct ieee80211_hw *hw)
362{
363 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
364 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
365 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
366 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
367
368 rtlhal->hw = hw;
369 ppsc->inactiveps = false;
370 ppsc->leisure_ps = false;
371 ppsc->fwctrl_lps = false;
372 ppsc->reg_fwctrl_lps = 3;
373 ppsc->reg_max_lps_awakeintvl = 5;
374 ppsc->fwctrl_psmode = FW_PS_DTIM_MODE;
375
376 /* IBSS */
377 mac->beacon_interval = 100;
378
379 /* AMPDU */
380 mac->min_space_cfg = 0;
381 mac->max_mss_density = 0;
382
383 /* set sane AMPDU defaults */
384 mac->current_ampdu_density = 7;
385 mac->current_ampdu_factor = 3;
386
387 /* QOS */
388 rtlusb->acm_method = eAcmWay2_SW;
389
390 /* IRQ */
391 /* HIMR - turn all on */
392 rtlusb->irq_mask[0] = 0xFFFFFFFF;
393 /* HIMR_EX - turn all on */
394 rtlusb->irq_mask[1] = 0xFFFFFFFF;
395 rtlusb->disableHWSM = true;
396 return 0;
397}
398
399#define __RADIO_TAP_SIZE_RSV 32
400
401static void _rtl_rx_completed(struct urb *urb);
402
403static struct sk_buff *_rtl_prep_rx_urb(struct ieee80211_hw *hw,
404 struct rtl_usb *rtlusb,
405 struct urb *urb,
406 gfp_t gfp_mask)
407{
408 struct sk_buff *skb;
409 struct rtl_priv *rtlpriv = rtl_priv(hw);
410
411 skb = __dev_alloc_skb((rtlusb->rx_max_size + __RADIO_TAP_SIZE_RSV),
412 gfp_mask);
413 if (!skb) {
414 RT_TRACE(rtlpriv, COMP_USB, DBG_EMERG,
415 ("Failed to __dev_alloc_skb!!\n"))
416 return ERR_PTR(-ENOMEM);
417 }
418
419 /* reserve some space for mac80211's radiotap */
420 skb_reserve(skb, __RADIO_TAP_SIZE_RSV);
421 usb_fill_bulk_urb(urb, rtlusb->udev,
422 usb_rcvbulkpipe(rtlusb->udev, rtlusb->in_ep),
423 skb->data, min(skb_tailroom(skb),
424 (int)rtlusb->rx_max_size),
425 _rtl_rx_completed, skb);
426
427 _rtl_install_trx_info(rtlusb, skb, rtlusb->in_ep);
428 return skb;
429}
430
431#undef __RADIO_TAP_SIZE_RSV
432
433static void _rtl_usb_rx_process_agg(struct ieee80211_hw *hw,
434 struct sk_buff *skb)
435{
436 struct rtl_priv *rtlpriv = rtl_priv(hw);
437 u8 *rxdesc = skb->data;
438 struct ieee80211_hdr *hdr;
439 bool unicast = false;
440 __le16 fc;
441 struct ieee80211_rx_status rx_status = {0};
442 struct rtl_stats stats = {
443 .signal = 0,
444 .noise = -98,
445 .rate = 0,
446 };
447
448 skb_pull(skb, RTL_RX_DESC_SIZE);
449 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, &rx_status, rxdesc, skb);
450 skb_pull(skb, (stats.rx_drvinfo_size + stats.rx_bufshift));
451 hdr = (struct ieee80211_hdr *)(skb->data);
452 fc = hdr->frame_control;
453 if (!stats.crc) {
454 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
455
456 if (is_broadcast_ether_addr(hdr->addr1)) {
457 /*TODO*/;
458 } else if (is_multicast_ether_addr(hdr->addr1)) {
459 /*TODO*/
460 } else {
461 unicast = true;
462 rtlpriv->stats.rxbytesunicast += skb->len;
463 }
464
465 rtl_is_special_data(hw, skb, false);
466
467 if (ieee80211_is_data(fc)) {
468 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
469
470 if (unicast)
471 rtlpriv->link_info.num_rx_inperiod++;
472 }
473 }
474}
475
476static void _rtl_usb_rx_process_noagg(struct ieee80211_hw *hw,
477 struct sk_buff *skb)
478{
479 struct rtl_priv *rtlpriv = rtl_priv(hw);
480 u8 *rxdesc = skb->data;
481 struct ieee80211_hdr *hdr;
482 bool unicast = false;
483 __le16 fc;
484 struct ieee80211_rx_status rx_status = {0};
485 struct rtl_stats stats = {
486 .signal = 0,
487 .noise = -98,
488 .rate = 0,
489 };
490
491 skb_pull(skb, RTL_RX_DESC_SIZE);
492 rtlpriv->cfg->ops->query_rx_desc(hw, &stats, &rx_status, rxdesc, skb);
493 skb_pull(skb, (stats.rx_drvinfo_size + stats.rx_bufshift));
494 hdr = (struct ieee80211_hdr *)(skb->data);
495 fc = hdr->frame_control;
496 if (!stats.crc) {
497 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
498
499 if (is_broadcast_ether_addr(hdr->addr1)) {
500 /*TODO*/;
501 } else if (is_multicast_ether_addr(hdr->addr1)) {
502 /*TODO*/
503 } else {
504 unicast = true;
505 rtlpriv->stats.rxbytesunicast += skb->len;
506 }
507
508 rtl_is_special_data(hw, skb, false);
509
510 if (ieee80211_is_data(fc)) {
511 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
512
513 if (unicast)
514 rtlpriv->link_info.num_rx_inperiod++;
515 }
516 if (likely(rtl_action_proc(hw, skb, false))) {
517 struct sk_buff *uskb = NULL;
518 u8 *pdata;
519
520 uskb = dev_alloc_skb(skb->len + 128);
521 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
522 sizeof(rx_status));
523 pdata = (u8 *)skb_put(uskb, skb->len);
524 memcpy(pdata, skb->data, skb->len);
525 dev_kfree_skb_any(skb);
526 ieee80211_rx_irqsafe(hw, uskb);
527 } else {
528 dev_kfree_skb_any(skb);
529 }
530 }
531}
532
533static void _rtl_rx_pre_process(struct ieee80211_hw *hw, struct sk_buff *skb)
534{
535 struct sk_buff *_skb;
536 struct sk_buff_head rx_queue;
537 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
538
539 skb_queue_head_init(&rx_queue);
540 if (rtlusb->usb_rx_segregate_hdl)
541 rtlusb->usb_rx_segregate_hdl(hw, skb, &rx_queue);
542 WARN_ON(skb_queue_empty(&rx_queue));
543 while (!skb_queue_empty(&rx_queue)) {
544 _skb = skb_dequeue(&rx_queue);
545 _rtl_usb_rx_process_agg(hw, skb);
546 ieee80211_rx_irqsafe(hw, skb);
547 }
548}
549
550static void _rtl_rx_completed(struct urb *_urb)
551{
552 struct sk_buff *skb = (struct sk_buff *)_urb->context;
553 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
554 struct rtl_usb *rtlusb = (struct rtl_usb *)info->rate_driver_data[0];
555 struct ieee80211_hw *hw = usb_get_intfdata(rtlusb->intf);
556 struct rtl_priv *rtlpriv = rtl_priv(hw);
557 int err = 0;
558
559 if (unlikely(IS_USB_STOP(rtlusb)))
560 goto free;
561
562 if (likely(0 == _urb->status)) {
563 /* If this code were moved to work queue, would CPU
564 * utilization be improved? NOTE: We shall allocate another skb
565 * and reuse the original one.
566 */
567 skb_put(skb, _urb->actual_length);
568
569 if (likely(!rtlusb->usb_rx_segregate_hdl)) {
570 struct sk_buff *_skb;
571 _rtl_usb_rx_process_noagg(hw, skb);
572 _skb = _rtl_prep_rx_urb(hw, rtlusb, _urb, GFP_ATOMIC);
573 if (IS_ERR(_skb)) {
574 err = PTR_ERR(_skb);
575 RT_TRACE(rtlpriv, COMP_USB, DBG_EMERG,
576 ("Can't allocate skb for bulk IN!\n"));
577 return;
578 }
579 skb = _skb;
580 } else{
581 /* TO DO */
582 _rtl_rx_pre_process(hw, skb);
583 printk(KERN_ERR "rtlwifi: rx agg not supported\n");
584 }
585 goto resubmit;
586 }
587
588 switch (_urb->status) {
589 /* disconnect */
590 case -ENOENT:
591 case -ECONNRESET:
592 case -ENODEV:
593 case -ESHUTDOWN:
594 goto free;
595 default:
596 break;
597 }
598
599resubmit:
600 skb_reset_tail_pointer(skb);
601 skb_trim(skb, 0);
602
603 usb_anchor_urb(_urb, &rtlusb->rx_submitted);
604 err = usb_submit_urb(_urb, GFP_ATOMIC);
605 if (unlikely(err)) {
606 usb_unanchor_urb(_urb);
607 goto free;
608 }
609 return;
610
611free:
612 dev_kfree_skb_irq(skb);
613}
614
615static int _rtl_usb_receive(struct ieee80211_hw *hw)
616{
617 struct urb *urb;
618 struct sk_buff *skb;
619 int err;
620 int i;
621 struct rtl_priv *rtlpriv = rtl_priv(hw);
622 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
623
624 WARN_ON(0 == rtlusb->rx_urb_num);
625 /* 1600 == 1514 + max WLAN header + rtk info */
626 WARN_ON(rtlusb->rx_max_size < 1600);
627
628 for (i = 0; i < rtlusb->rx_urb_num; i++) {
629 err = -ENOMEM;
630 urb = usb_alloc_urb(0, GFP_KERNEL);
631 if (!urb) {
632 RT_TRACE(rtlpriv, COMP_USB, DBG_EMERG,
633 ("Failed to alloc URB!!\n"))
634 goto err_out;
635 }
636
637 skb = _rtl_prep_rx_urb(hw, rtlusb, urb, GFP_KERNEL);
638 if (IS_ERR(skb)) {
639 RT_TRACE(rtlpriv, COMP_USB, DBG_EMERG,
640 ("Failed to prep_rx_urb!!\n"))
641 err = PTR_ERR(skb);
642 goto err_out;
643 }
644
645 usb_anchor_urb(urb, &rtlusb->rx_submitted);
646 err = usb_submit_urb(urb, GFP_KERNEL);
647 if (err)
648 goto err_out;
649 usb_free_urb(urb);
650 }
651 return 0;
652
653err_out:
654 usb_kill_anchored_urbs(&rtlusb->rx_submitted);
655 return err;
656}
657
658static int rtl_usb_start(struct ieee80211_hw *hw)
659{
660 int err;
661 struct rtl_priv *rtlpriv = rtl_priv(hw);
662 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
663 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
664
665 err = rtlpriv->cfg->ops->hw_init(hw);
666 rtl_init_rx_config(hw);
667
668 /* Enable software */
669 SET_USB_START(rtlusb);
670 /* should after adapter start and interrupt enable. */
671 set_hal_start(rtlhal);
672
673 /* Start bulk IN */
674 _rtl_usb_receive(hw);
675
676 return err;
677}
678/**
679 *
680 *
681 */
682
683/*======================= tx =========================================*/
684static void rtl_usb_cleanup(struct ieee80211_hw *hw)
685{
686 u32 i;
687 struct sk_buff *_skb;
688 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
689 struct ieee80211_tx_info *txinfo;
690
691 SET_USB_STOP(rtlusb);
692
693 /* clean up rx stuff. */
694 usb_kill_anchored_urbs(&rtlusb->rx_submitted);
695
696 /* clean up tx stuff */
697 for (i = 0; i < RTL_USB_MAX_EP_NUM; i++) {
698 while ((_skb = skb_dequeue(&rtlusb->tx_skb_queue[i]))) {
699 rtlusb->usb_tx_cleanup(hw, _skb);
700 txinfo = IEEE80211_SKB_CB(_skb);
701 ieee80211_tx_info_clear_status(txinfo);
702 txinfo->flags |= IEEE80211_TX_STAT_ACK;
703 ieee80211_tx_status_irqsafe(hw, _skb);
704 }
705 usb_kill_anchored_urbs(&rtlusb->tx_pending[i]);
706 }
707 usb_kill_anchored_urbs(&rtlusb->tx_submitted);
708}
709
710/**
711 *
712 * We may add some struct into struct rtl_usb later. Do deinit here.
713 *
714 */
715static void rtl_usb_deinit(struct ieee80211_hw *hw)
716{
717 rtl_usb_cleanup(hw);
718}
719
720static void rtl_usb_stop(struct ieee80211_hw *hw)
721{
722 struct rtl_priv *rtlpriv = rtl_priv(hw);
723 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
724 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
725
726 /* should after adapter start and interrupt enable. */
727 set_hal_stop(rtlhal);
728 /* Enable software */
729 SET_USB_STOP(rtlusb);
730 rtl_usb_deinit(hw);
731 rtlpriv->cfg->ops->hw_disable(hw);
732}
733
734static void _rtl_submit_tx_urb(struct ieee80211_hw *hw, struct urb *_urb)
735{
736 int err;
737 struct rtl_priv *rtlpriv = rtl_priv(hw);
738 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
739
740 usb_anchor_urb(_urb, &rtlusb->tx_submitted);
741 err = usb_submit_urb(_urb, GFP_ATOMIC);
742 if (err < 0) {
743 struct sk_buff *skb;
744
745 RT_TRACE(rtlpriv, COMP_USB, DBG_EMERG,
746 ("Failed to submit urb.\n"));
747 usb_unanchor_urb(_urb);
748 skb = (struct sk_buff *)_urb->context;
749 kfree_skb(skb);
750 }
751 usb_free_urb(_urb);
752}
753
754static int _usb_tx_post(struct ieee80211_hw *hw, struct urb *urb,
755 struct sk_buff *skb)
756{
757 struct rtl_priv *rtlpriv = rtl_priv(hw);
758 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
759 struct ieee80211_tx_info *txinfo;
760
761 rtlusb->usb_tx_post_hdl(hw, urb, skb);
762 skb_pull(skb, RTL_TX_HEADER_SIZE);
763 txinfo = IEEE80211_SKB_CB(skb);
764 ieee80211_tx_info_clear_status(txinfo);
765 txinfo->flags |= IEEE80211_TX_STAT_ACK;
766
767 if (urb->status) {
768 RT_TRACE(rtlpriv, COMP_USB, DBG_EMERG,
769 ("Urb has error status 0x%X\n", urb->status));
770 goto out;
771 }
772 /* TODO: statistics */
773out:
774 ieee80211_tx_status_irqsafe(hw, skb);
775 return urb->status;
776}
777
778static void _rtl_tx_complete(struct urb *urb)
779{
780 struct sk_buff *skb = (struct sk_buff *)urb->context;
781 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
782 struct rtl_usb *rtlusb = (struct rtl_usb *)info->rate_driver_data[0];
783 struct ieee80211_hw *hw = usb_get_intfdata(rtlusb->intf);
784 int err;
785
786 if (unlikely(IS_USB_STOP(rtlusb)))
787 return;
788 err = _usb_tx_post(hw, urb, skb);
789 if (err) {
790 /* Ignore error and keep issuiing other urbs */
791 return;
792 }
793}
794
795static struct urb *_rtl_usb_tx_urb_setup(struct ieee80211_hw *hw,
796 struct sk_buff *skb, u32 ep_num)
797{
798 struct rtl_priv *rtlpriv = rtl_priv(hw);
799 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
800 struct urb *_urb;
801
802 WARN_ON(NULL == skb);
803 _urb = usb_alloc_urb(0, GFP_ATOMIC);
804 if (!_urb) {
805 RT_TRACE(rtlpriv, COMP_USB, DBG_EMERG,
806 ("Can't allocate URB for bulk out!\n"));
807 kfree_skb(skb);
808 return NULL;
809 }
810 _rtl_install_trx_info(rtlusb, skb, ep_num);
811 usb_fill_bulk_urb(_urb, rtlusb->udev, usb_sndbulkpipe(rtlusb->udev,
812 ep_num), skb->data, skb->len, _rtl_tx_complete, skb);
813 _urb->transfer_flags |= URB_ZERO_PACKET;
814 return _urb;
815}
816
817static void _rtl_usb_transmit(struct ieee80211_hw *hw, struct sk_buff *skb,
818 enum rtl_txq qnum)
819{
820 struct rtl_priv *rtlpriv = rtl_priv(hw);
821 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
822 u32 ep_num;
823 struct urb *_urb = NULL;
824 struct sk_buff *_skb = NULL;
825 struct sk_buff_head *skb_list;
826 struct usb_anchor *urb_list;
827
828 WARN_ON(NULL == rtlusb->usb_tx_aggregate_hdl);
829 if (unlikely(IS_USB_STOP(rtlusb))) {
830 RT_TRACE(rtlpriv, COMP_USB, DBG_EMERG,
831 ("USB device is stopping...\n"));
832 kfree_skb(skb);
833 return;
834 }
835 ep_num = rtlusb->ep_map.ep_mapping[qnum];
836 skb_list = &rtlusb->tx_skb_queue[ep_num];
837 _skb = skb;
838 _urb = _rtl_usb_tx_urb_setup(hw, _skb, ep_num);
839 if (unlikely(!_urb)) {
840 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
841 ("Can't allocate urb. Drop skb!\n"));
842 return;
843 }
844 urb_list = &rtlusb->tx_pending[ep_num];
845 _rtl_submit_tx_urb(hw, _urb);
846}
847
848static void _rtl_usb_tx_preprocess(struct ieee80211_hw *hw, struct sk_buff *skb,
849 u16 hw_queue)
850{
851 struct rtl_priv *rtlpriv = rtl_priv(hw);
852 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
853 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
854 struct rtl_tx_desc *pdesc = NULL;
855 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
856 __le16 fc = hdr->frame_control;
857 u8 *pda_addr = hdr->addr1;
858 /* ssn */
859 u8 *qc = NULL;
860 u8 tid = 0;
861 u16 seq_number = 0;
862
863 if (ieee80211_is_mgmt(fc))
864 rtl_tx_mgmt_proc(hw, skb);
865 rtl_action_proc(hw, skb, true);
866 if (is_multicast_ether_addr(pda_addr))
867 rtlpriv->stats.txbytesmulticast += skb->len;
868 else if (is_broadcast_ether_addr(pda_addr))
869 rtlpriv->stats.txbytesbroadcast += skb->len;
870 else
871 rtlpriv->stats.txbytesunicast += skb->len;
872 if (ieee80211_is_data_qos(fc)) {
873 qc = ieee80211_get_qos_ctl(hdr);
874 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
875 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
876 IEEE80211_SCTL_SEQ) >> 4;
877 seq_number += 1;
878 seq_number <<= 4;
879 }
880 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc, info, skb,
881 hw_queue);
882 if (!ieee80211_has_morefrags(hdr->frame_control)) {
883 if (qc)
884 mac->tids[tid].seq_number = seq_number;
885 }
886 if (ieee80211_is_data(fc))
887 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
888}
889
890static int rtl_usb_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
891{
892 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
893 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
894 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)(skb->data);
895 __le16 fc = hdr->frame_control;
896 u16 hw_queue;
897
898 if (unlikely(is_hal_stop(rtlhal)))
899 goto err_free;
900 hw_queue = rtlusb->usb_mq_to_hwq(fc, skb_get_queue_mapping(skb));
901 _rtl_usb_tx_preprocess(hw, skb, hw_queue);
902 _rtl_usb_transmit(hw, skb, hw_queue);
903 return NETDEV_TX_OK;
904
905err_free:
906 dev_kfree_skb_any(skb);
907 return NETDEV_TX_OK;
908}
909
910static bool rtl_usb_tx_chk_waitq_insert(struct ieee80211_hw *hw,
911 struct sk_buff *skb)
912{
913 return false;
914}
915
916static struct rtl_intf_ops rtl_usb_ops = {
917 .adapter_start = rtl_usb_start,
918 .adapter_stop = rtl_usb_stop,
919 .adapter_tx = rtl_usb_tx,
920 .waitq_insert = rtl_usb_tx_chk_waitq_insert,
921};
922
923int __devinit rtl_usb_probe(struct usb_interface *intf,
924 const struct usb_device_id *id)
925{
926 int err;
927 struct ieee80211_hw *hw = NULL;
928 struct rtl_priv *rtlpriv = NULL;
929 struct usb_device *udev;
930 struct rtl_usb_priv *usb_priv;
931
932 hw = ieee80211_alloc_hw(sizeof(struct rtl_priv) +
933 sizeof(struct rtl_usb_priv), &rtl_ops);
934 if (!hw) {
935 RT_ASSERT(false, ("%s : ieee80211 alloc failed\n", __func__));
936 return -ENOMEM;
937 }
938 rtlpriv = hw->priv;
939 SET_IEEE80211_DEV(hw, &intf->dev);
940 udev = interface_to_usbdev(intf);
941 usb_get_dev(udev);
942 usb_priv = rtl_usbpriv(hw);
943 memset(usb_priv, 0, sizeof(*usb_priv));
944 usb_priv->dev.intf = intf;
945 usb_priv->dev.udev = udev;
946 usb_set_intfdata(intf, hw);
947 /* init cfg & intf_ops */
948 rtlpriv->rtlhal.interface = INTF_USB;
949 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_info);
950 rtlpriv->intf_ops = &rtl_usb_ops;
951 rtl_dbgp_flag_init(hw);
952 /* Init IO handler */
953 _rtl_usb_io_handler_init(&udev->dev, hw);
954 rtlpriv->cfg->ops->read_chip_version(hw);
955 /*like read eeprom and so on */
956 rtlpriv->cfg->ops->read_eeprom_info(hw);
957 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
958 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
959 ("Can't init_sw_vars.\n"));
960 goto error_out;
961 }
962 rtlpriv->cfg->ops->init_sw_leds(hw);
963 err = _rtl_usb_init(hw);
964 err = _rtl_usb_init_sw(hw);
965 /* Init mac80211 sw */
966 err = rtl_init_core(hw);
967 if (err) {
968 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
969 ("Can't allocate sw for mac80211.\n"));
970 goto error_out;
971 }
972
973 /*init rfkill */
974 /* rtl_init_rfkill(hw); */
975
976 err = ieee80211_register_hw(hw);
977 if (err) {
978 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
979 ("Can't register mac80211 hw.\n"));
980 goto error_out;
981 } else {
982 rtlpriv->mac80211.mac80211_registered = 1;
983 }
984 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
985 return 0;
986error_out:
987 rtl_deinit_core(hw);
988 _rtl_usb_io_handler_release(hw);
989 ieee80211_free_hw(hw);
990 usb_put_dev(udev);
991 return -ENODEV;
992}
993EXPORT_SYMBOL(rtl_usb_probe);
994
995void rtl_usb_disconnect(struct usb_interface *intf)
996{
997 struct ieee80211_hw *hw = usb_get_intfdata(intf);
998 struct rtl_priv *rtlpriv = rtl_priv(hw);
999 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1000 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1001
1002 if (unlikely(!rtlpriv))
1003 return;
1004 /*ieee80211_unregister_hw will call ops_stop */
1005 if (rtlmac->mac80211_registered == 1) {
1006 ieee80211_unregister_hw(hw);
1007 rtlmac->mac80211_registered = 0;
1008 } else {
1009 rtl_deinit_deferred_work(hw);
1010 rtlpriv->intf_ops->adapter_stop(hw);
1011 }
1012 /*deinit rfkill */
1013 /* rtl_deinit_rfkill(hw); */
1014 rtl_usb_deinit(hw);
1015 rtl_deinit_core(hw);
1016 rtlpriv->cfg->ops->deinit_sw_leds(hw);
1017 rtlpriv->cfg->ops->deinit_sw_vars(hw);
1018 _rtl_usb_io_handler_release(hw);
1019 usb_put_dev(rtlusb->udev);
1020 usb_set_intfdata(intf, NULL);
1021 ieee80211_free_hw(hw);
1022}
1023EXPORT_SYMBOL(rtl_usb_disconnect);
1024
1025int rtl_usb_suspend(struct usb_interface *pusb_intf, pm_message_t message)
1026{
1027 return 0;
1028}
1029EXPORT_SYMBOL(rtl_usb_suspend);
1030
1031int rtl_usb_resume(struct usb_interface *pusb_intf)
1032{
1033 return 0;
1034}
1035EXPORT_SYMBOL(rtl_usb_resume);
diff --git a/drivers/net/wireless/rtlwifi/usb.h b/drivers/net/wireless/rtlwifi/usb.h
new file mode 100644
index 000000000000..abadfe918d30
--- /dev/null
+++ b/drivers/net/wireless/rtlwifi/usb.h
@@ -0,0 +1,164 @@
1/******************************************************************************
2 *
3 * Copyright(c) 2009-2011 Realtek Corporation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 *****************************************************************************/
27
28#ifndef __RTL_USB_H__
29#define __RTL_USB_H__
30
31#include <linux/usb.h>
32#include <linux/skbuff.h>
33
34#define RTL_USB_DEVICE(vend, prod, cfg) \
35 .match_flags = USB_DEVICE_ID_MATCH_DEVICE, \
36 .idVendor = (vend), \
37 .idProduct = (prod), \
38 .driver_info = (kernel_ulong_t)&(cfg)
39
40#define USB_HIGH_SPEED_BULK_SIZE 512
41#define USB_FULL_SPEED_BULK_SIZE 64
42
43
44#define RTL_USB_MAX_TXQ_NUM 4 /* max tx queue */
45#define RTL_USB_MAX_EP_NUM 6 /* max ep number */
46#define RTL_USB_MAX_TX_URBS_NUM 8
47
48enum rtl_txq {
49 /* These definitions shall be consistent with value
50 * returned by skb_get_queue_mapping
51 *------------------------------------*/
52 RTL_TXQ_BK,
53 RTL_TXQ_BE,
54 RTL_TXQ_VI,
55 RTL_TXQ_VO,
56 /*------------------------------------*/
57 RTL_TXQ_BCN,
58 RTL_TXQ_MGT,
59 RTL_TXQ_HI,
60
61 /* Must be last */
62 __RTL_TXQ_NUM,
63};
64
65struct rtl_ep_map {
66 u32 ep_mapping[__RTL_TXQ_NUM];
67};
68
69struct _trx_info {
70 struct rtl_usb *rtlusb;
71 u32 ep_num;
72};
73
74static inline void _rtl_install_trx_info(struct rtl_usb *rtlusb,
75 struct sk_buff *skb,
76 u32 ep_num)
77{
78 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
79 info->rate_driver_data[0] = rtlusb;
80 info->rate_driver_data[1] = (void *)(__kernel_size_t)ep_num;
81}
82
83
84/* Add suspend/resume later */
85enum rtl_usb_state {
86 USB_STATE_STOP = 0,
87 USB_STATE_START = 1,
88};
89
90#define IS_USB_STOP(rtlusb_ptr) (USB_STATE_STOP == (rtlusb_ptr)->state)
91#define IS_USB_START(rtlusb_ptr) (USB_STATE_START == (rtlusb_ptr)->state)
92#define SET_USB_STOP(rtlusb_ptr) \
93 do { \
94 (rtlusb_ptr)->state = USB_STATE_STOP; \
95 } while (0)
96
97#define SET_USB_START(rtlusb_ptr) \
98 do { \
99 (rtlusb_ptr)->state = USB_STATE_START; \
100 } while (0)
101
102struct rtl_usb {
103 struct usb_device *udev;
104 struct usb_interface *intf;
105 enum rtl_usb_state state;
106
107 /* Bcn control register setting */
108 u32 reg_bcn_ctrl_val;
109 /* for 88/92cu card disable */
110 u8 disableHWSM;
111 /*QOS & EDCA */
112 enum acm_method acm_method;
113 /* irq . HIMR,HIMR_EX */
114 u32 irq_mask[2];
115 bool irq_enabled;
116
117 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
118
119 /* Tx */
120 u8 out_ep_nums ;
121 u8 out_queue_sel;
122 struct rtl_ep_map ep_map;
123
124 u32 max_bulk_out_size;
125 u32 tx_submitted_urbs;
126 struct sk_buff_head tx_skb_queue[RTL_USB_MAX_EP_NUM];
127
128 struct usb_anchor tx_pending[RTL_USB_MAX_EP_NUM];
129 struct usb_anchor tx_submitted;
130
131 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
132 struct sk_buff_head *);
133 int (*usb_tx_post_hdl)(struct ieee80211_hw *,
134 struct urb *, struct sk_buff *);
135 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
136
137 /* Rx */
138 u8 in_ep_nums ;
139 u32 in_ep; /* Bulk IN endpoint number */
140 u32 rx_max_size; /* Bulk IN max buffer size */
141 u32 rx_urb_num; /* How many Bulk INs are submitted to host. */
142 struct usb_anchor rx_submitted;
143 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
144 struct sk_buff_head *);
145 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
146};
147
148struct rtl_usb_priv {
149 struct rtl_usb dev;
150 struct rtl_led_ctl ledctl;
151};
152
153#define rtl_usbpriv(hw) (((struct rtl_usb_priv *)(rtl_priv(hw))->priv))
154#define rtl_usbdev(usbpriv) (&((usbpriv)->dev))
155
156
157
158int __devinit rtl_usb_probe(struct usb_interface *intf,
159 const struct usb_device_id *id);
160void rtl_usb_disconnect(struct usb_interface *intf);
161int rtl_usb_suspend(struct usb_interface *pusb_intf, pm_message_t message);
162int rtl_usb_resume(struct usb_interface *pusb_intf);
163
164#endif
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
index d44d79613d2d..01226f8e70f9 100644
--- a/drivers/net/wireless/rtlwifi/wifi.h
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -34,6 +34,8 @@
34#include <linux/firmware.h> 34#include <linux/firmware.h>
35#include <linux/version.h> 35#include <linux/version.h>
36#include <linux/etherdevice.h> 36#include <linux/etherdevice.h>
37#include <linux/vmalloc.h>
38#include <linux/usb.h>
37#include <net/mac80211.h> 39#include <net/mac80211.h>
38#include "debug.h" 40#include "debug.h"
39 41
@@ -82,6 +84,19 @@
82#define MAC80211_3ADDR_LEN 24 84#define MAC80211_3ADDR_LEN 24
83#define MAC80211_4ADDR_LEN 30 85#define MAC80211_4ADDR_LEN 30
84 86
87#define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
88#define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
89#define MAX_PG_GROUP 13
90#define CHANNEL_GROUP_MAX_2G 3
91#define CHANNEL_GROUP_IDX_5GL 3
92#define CHANNEL_GROUP_IDX_5GM 6
93#define CHANNEL_GROUP_IDX_5GH 9
94#define CHANNEL_GROUP_MAX_5G 9
95#define CHANNEL_MAX_NUMBER_2G 14
96#define AVG_THERMAL_NUM 8
97
98/* for early mode */
99#define EM_HDR_LEN 8
85enum intf_type { 100enum intf_type {
86 INTF_PCI = 0, 101 INTF_PCI = 0,
87 INTF_USB = 1, 102 INTF_USB = 1,
@@ -113,11 +128,38 @@ enum hardware_type {
113 HARDWARE_TYPE_RTL8192CU, 128 HARDWARE_TYPE_RTL8192CU,
114 HARDWARE_TYPE_RTL8192DE, 129 HARDWARE_TYPE_RTL8192DE,
115 HARDWARE_TYPE_RTL8192DU, 130 HARDWARE_TYPE_RTL8192DU,
131 HARDWARE_TYPE_RTL8723E,
132 HARDWARE_TYPE_RTL8723U,
116 133
117 /*keep it last*/ 134 /* keep it last */
118 HARDWARE_TYPE_NUM 135 HARDWARE_TYPE_NUM
119}; 136};
120 137
138#define IS_HARDWARE_TYPE_8192SU(rtlhal) \
139 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
140#define IS_HARDWARE_TYPE_8192SE(rtlhal) \
141 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
142#define IS_HARDWARE_TYPE_8192CE(rtlhal) \
143 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
144#define IS_HARDWARE_TYPE_8192CU(rtlhal) \
145 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
146#define IS_HARDWARE_TYPE_8192DE(rtlhal) \
147 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
148#define IS_HARDWARE_TYPE_8192DU(rtlhal) \
149 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
150#define IS_HARDWARE_TYPE_8723E(rtlhal) \
151 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
152#define IS_HARDWARE_TYPE_8723U(rtlhal) \
153 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
154#define IS_HARDWARE_TYPE_8192S(rtlhal) \
155(IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
156#define IS_HARDWARE_TYPE_8192C(rtlhal) \
157(IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
158#define IS_HARDWARE_TYPE_8192D(rtlhal) \
159(IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
160#define IS_HARDWARE_TYPE_8723(rtlhal) \
161(IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
162
121enum scan_operation_backup_opt { 163enum scan_operation_backup_opt {
122 SCAN_OPT_BACKUP = 0, 164 SCAN_OPT_BACKUP = 0,
123 SCAN_OPT_RESTORE, 165 SCAN_OPT_RESTORE,
@@ -315,6 +357,7 @@ enum rf_type {
315 RF_1T1R = 0, 357 RF_1T1R = 0,
316 RF_1T2R = 1, 358 RF_1T2R = 1,
317 RF_2T2R = 2, 359 RF_2T2R = 2,
360 RF_2T2R_GREEN = 3,
318}; 361};
319 362
320enum ht_channel_width { 363enum ht_channel_width {
@@ -359,6 +402,8 @@ enum rtl_var_map {
359 EFUSE_LOADER_CLK_EN, 402 EFUSE_LOADER_CLK_EN,
360 EFUSE_ANA8M, 403 EFUSE_ANA8M,
361 EFUSE_HWSET_MAX_SIZE, 404 EFUSE_HWSET_MAX_SIZE,
405 EFUSE_MAX_SECTION_MAP,
406 EFUSE_REAL_CONTENT_SIZE,
362 407
363 /*CAM map */ 408 /*CAM map */
364 RWCAM, 409 RWCAM,
@@ -397,6 +442,7 @@ enum rtl_var_map {
397 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */ 442 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
398 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */ 443 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
399 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */ 444 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
445 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
400 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */ 446 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
401 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */ 447 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
402 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */ 448 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
@@ -405,7 +451,8 @@ enum rtl_var_map {
405 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */ 451 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
406 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */ 452 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
407 RTL_IMR_ROK, /*Receive DMA OK Interrupt */ 453 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
408 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt|RTL_IMR_TBDOK|RTL_IMR_TBDER)*/ 454 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BcnInt | RTL_IMR_TBDOK |
455 * RTL_IMR_TBDER) */
409 456
410 /*CCK Rates, TxHT = 0 */ 457 /*CCK Rates, TxHT = 0 */
411 RTL_RC_CCK_RATE1M, 458 RTL_RC_CCK_RATE1M,
@@ -481,6 +528,19 @@ enum acm_method {
481 eAcmWay2_SW = 2, 528 eAcmWay2_SW = 2,
482}; 529};
483 530
531enum macphy_mode {
532 SINGLEMAC_SINGLEPHY = 0,
533 DUALMAC_DUALPHY,
534 DUALMAC_SINGLEPHY,
535};
536
537enum band_type {
538 BAND_ON_2_4G = 0,
539 BAND_ON_5G,
540 BAND_ON_BOTH,
541 BANDMAX
542};
543
484/*aci/aifsn Field. 544/*aci/aifsn Field.
485Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/ 545Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
486union aci_aifsn { 546union aci_aifsn {
@@ -505,6 +565,17 @@ enum wireless_mode {
505 WIRELESS_MODE_N_5G = 0x20 565 WIRELESS_MODE_N_5G = 0x20
506}; 566};
507 567
568#define IS_WIRELESS_MODE_A(wirelessmode) \
569 (wirelessmode == WIRELESS_MODE_A)
570#define IS_WIRELESS_MODE_B(wirelessmode) \
571 (wirelessmode == WIRELESS_MODE_B)
572#define IS_WIRELESS_MODE_G(wirelessmode) \
573 (wirelessmode == WIRELESS_MODE_G)
574#define IS_WIRELESS_MODE_N_24G(wirelessmode) \
575 (wirelessmode == WIRELESS_MODE_N_24G)
576#define IS_WIRELESS_MODE_N_5G(wirelessmode) \
577 (wirelessmode == WIRELESS_MODE_N_5G)
578
508enum ratr_table_mode { 579enum ratr_table_mode {
509 RATR_INX_WIRELESS_NGB = 0, 580 RATR_INX_WIRELESS_NGB = 0,
510 RATR_INX_WIRELESS_NG = 1, 581 RATR_INX_WIRELESS_NG = 1,
@@ -574,11 +645,11 @@ struct rtl_probe_rsp {
574struct rtl_led { 645struct rtl_led {
575 void *hw; 646 void *hw;
576 enum rtl_led_pin ledpin; 647 enum rtl_led_pin ledpin;
577 bool b_ledon; 648 bool ledon;
578}; 649};
579 650
580struct rtl_led_ctl { 651struct rtl_led_ctl {
581 bool bled_opendrain; 652 bool led_opendrain;
582 struct rtl_led sw_led0; 653 struct rtl_led sw_led0;
583 struct rtl_led sw_led1; 654 struct rtl_led sw_led1;
584}; 655};
@@ -603,6 +674,8 @@ struct false_alarm_statistics {
603 u32 cnt_rate_illegal; 674 u32 cnt_rate_illegal;
604 u32 cnt_crc8_fail; 675 u32 cnt_crc8_fail;
605 u32 cnt_mcs_fail; 676 u32 cnt_mcs_fail;
677 u32 cnt_fast_fsync_fail;
678 u32 cnt_sb_search_fail;
606 u32 cnt_ofdm_fail; 679 u32 cnt_ofdm_fail;
607 u32 cnt_cck_fail; 680 u32 cnt_cck_fail;
608 u32 cnt_all; 681 u32 cnt_all;
@@ -690,6 +763,32 @@ struct rtl_rfkill {
690 bool rfkill_state; /*0 is off, 1 is on */ 763 bool rfkill_state; /*0 is off, 1 is on */
691}; 764};
692 765
766#define IQK_MATRIX_REG_NUM 8
767#define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
768struct iqk_matrix_regs {
769 bool b_iqk_done;
770 long value[1][IQK_MATRIX_REG_NUM];
771};
772
773struct phy_parameters {
774 u16 length;
775 u32 *pdata;
776};
777
778enum hw_param_tab_index {
779 PHY_REG_2T,
780 PHY_REG_1T,
781 PHY_REG_PG,
782 RADIOA_2T,
783 RADIOB_2T,
784 RADIOA_1T,
785 RADIOB_1T,
786 MAC_REG,
787 AGCTAB_2T,
788 AGCTAB_1T,
789 MAX_TAB
790};
791
693struct rtl_phy { 792struct rtl_phy {
694 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */ 793 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
695 struct init_gain initgain_backup; 794 struct init_gain initgain_backup;
@@ -705,8 +804,9 @@ struct rtl_phy {
705 u8 current_channel; 804 u8 current_channel;
706 u8 h2c_box_num; 805 u8 h2c_box_num;
707 u8 set_io_inprogress; 806 u8 set_io_inprogress;
807 u8 lck_inprogress;
708 808
709 /*record for power tracking*/ 809 /* record for power tracking */
710 s32 reg_e94; 810 s32 reg_e94;
711 s32 reg_e9c; 811 s32 reg_e9c;
712 s32 reg_ea4; 812 s32 reg_ea4;
@@ -723,26 +823,32 @@ struct rtl_phy {
723 u32 iqk_mac_backup[IQK_MAC_REG_NUM]; 823 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
724 u32 iqk_bb_backup[10]; 824 u32 iqk_bb_backup[10];
725 825
726 bool b_rfpi_enable; 826 /* Dual mac */
827 bool need_iqk;
828 struct iqk_matrix_regs iqk_matrix_regsetting[IQK_MATRIX_SETTINGS_NUM];
829
830 bool rfpi_enable;
727 831
728 u8 pwrgroup_cnt; 832 u8 pwrgroup_cnt;
729 u8 bcck_high_power; 833 u8 cck_high_power;
730 /* 3 groups of pwr diff by rates*/ 834 /* MAX_PG_GROUP groups of pwr diff by rates */
731 u32 mcs_txpwrlevel_origoffset[4][16]; 835 u32 mcs_txpwrlevel_origoffset[MAX_PG_GROUP][16];
732 u8 default_initialgain[4]; 836 u8 default_initialgain[4];
733 837
734 /*the current Tx power level*/ 838 /* the current Tx power level */
735 u8 cur_cck_txpwridx; 839 u8 cur_cck_txpwridx;
736 u8 cur_ofdm24g_txpwridx; 840 u8 cur_ofdm24g_txpwridx;
737 841
738 u32 rfreg_chnlval[2]; 842 u32 rfreg_chnlval[2];
739 bool b_apk_done; 843 bool apk_done;
844 u32 reg_rf3c[2]; /* pathA / pathB */
740 845
741 /*fsync*/
742 u8 framesync; 846 u8 framesync;
743 u32 framesync_c34; 847 u32 framesync_c34;
744 848
745 u8 num_total_rfpath; 849 u8 num_total_rfpath;
850 struct phy_parameters hwparam_tables[MAX_TAB];
851 u16 rf_pathmap;
746}; 852};
747 853
748#define MAX_TID_COUNT 9 854#define MAX_TID_COUNT 9
@@ -768,6 +874,7 @@ struct rtl_tid_data {
768struct rtl_priv; 874struct rtl_priv;
769struct rtl_io { 875struct rtl_io {
770 struct device *dev; 876 struct device *dev;
877 struct mutex bb_mutex;
771 878
772 /*PCI MEM map */ 879 /*PCI MEM map */
773 unsigned long pci_mem_end; /*shared mem end */ 880 unsigned long pci_mem_end; /*shared mem end */
@@ -779,11 +886,14 @@ struct rtl_io {
779 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val); 886 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
780 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val); 887 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
781 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val); 888 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
782 889 int (*writeN_async) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
783 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr); 890 u8 *pdata);
784 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr); 891
785 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr); 892 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
786 893 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
894 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
895 int (*readN_sync) (struct rtl_priv *rtlpriv, u32 addr, u16 len,
896 u8 *pdata);
787}; 897};
788 898
789struct rtl_mac { 899struct rtl_mac {
@@ -815,16 +925,24 @@ struct rtl_mac {
815 bool act_scanning; 925 bool act_scanning;
816 u8 cnt_after_linked; 926 u8 cnt_after_linked;
817 927
818 /*RDG*/ bool rdg_en; 928 /* early mode */
929 /* skb wait queue */
930 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
931 u8 earlymode_threshold;
932
933 /*RDG*/
934 bool rdg_en;
819 935
820 /*AP*/ u8 bssid[6]; 936 /*AP*/
821 u8 mcs[16]; /*16 bytes mcs for HT rates.*/ 937 u8 bssid[6];
822 u32 basic_rates; /*b/g rates*/ 938 u32 vendor;
939 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
940 u32 basic_rates; /* b/g rates */
823 u8 ht_enable; 941 u8 ht_enable;
824 u8 sgi_40; 942 u8 sgi_40;
825 u8 sgi_20; 943 u8 sgi_20;
826 u8 bw_40; 944 u8 bw_40;
827 u8 mode; /*wireless mode*/ 945 u8 mode; /* wireless mode */
828 u8 slot_time; 946 u8 slot_time;
829 u8 short_preamble; 947 u8 short_preamble;
830 u8 use_cts_protect; 948 u8 use_cts_protect;
@@ -835,9 +953,11 @@ struct rtl_mac {
835 u8 retry_long; 953 u8 retry_long;
836 u16 assoc_id; 954 u16 assoc_id;
837 955
838 /*IBSS*/ int beacon_interval; 956 /*IBSS*/
957 int beacon_interval;
839 958
840 /*AMPDU*/ u8 min_space_cfg; /*For Min spacing configurations */ 959 /*AMPDU*/
960 u8 min_space_cfg; /*For Min spacing configurations */
841 u8 max_mss_density; 961 u8 max_mss_density;
842 u8 current_ampdu_factor; 962 u8 current_ampdu_factor;
843 u8 current_ampdu_density; 963 u8 current_ampdu_density;
@@ -852,17 +972,54 @@ struct rtl_hal {
852 972
853 enum intf_type interface; 973 enum intf_type interface;
854 u16 hw_type; /*92c or 92d or 92s and so on */ 974 u16 hw_type; /*92c or 92d or 92s and so on */
975 u8 ic_class;
855 u8 oem_id; 976 u8 oem_id;
856 u8 version; /*version of chip */ 977 u32 version; /*version of chip */
857 u8 state; /*stop 0, start 1 */ 978 u8 state; /*stop 0, start 1 */
858 979
859 /*firmware */ 980 /*firmware */
981 u32 fwsize;
860 u8 *pfirmware; 982 u8 *pfirmware;
861 bool b_h2c_setinprogress; 983 u16 fw_version;
984 u16 fw_subversion;
985 bool h2c_setinprogress;
862 u8 last_hmeboxnum; 986 u8 last_hmeboxnum;
863 bool bfw_ready; 987 bool fw_ready;
864 /*Reserve page start offset except beacon in TxQ. */ 988 /*Reserve page start offset except beacon in TxQ. */
865 u8 fw_rsvdpage_startoffset; 989 u8 fw_rsvdpage_startoffset;
990 u8 h2c_txcmd_seq;
991
992 /* FW Cmd IO related */
993 u16 fwcmd_iomap;
994 u32 fwcmd_ioparam;
995 bool set_fwcmd_inprogress;
996 u8 current_fwcmd_io;
997
998 /**/
999 bool driver_going2unload;
1000
1001 /*AMPDU init min space*/
1002 u8 minspace_cfg; /*For Min spacing configurations */
1003
1004 /* Dual mac */
1005 enum macphy_mode macphymode;
1006 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1007 enum band_type current_bandtypebackup;
1008 enum band_type bandset;
1009 /* dual MAC 0--Mac0 1--Mac1 */
1010 u32 interfaceindex;
1011 /* just for DualMac S3S4 */
1012 u8 macphyctl_reg;
1013 bool earlymode_enable;
1014 /* Dual mac*/
1015 bool during_mac0init_radiob;
1016 bool during_mac1init_radioa;
1017 bool reloadtxpowerindex;
1018 /* True if IMR or IQK have done
1019 for 2.4G in scan progress */
1020 bool load_imrandiqk_setting_for2g;
1021
1022 bool disable_amsdu_8k;
866}; 1023};
867 1024
868struct rtl_security { 1025struct rtl_security {
@@ -887,48 +1044,61 @@ struct rtl_security {
887}; 1044};
888 1045
889struct rtl_dm { 1046struct rtl_dm {
890 /*PHY status for DM */ 1047 /*PHY status for Dynamic Management */
891 long entry_min_undecoratedsmoothed_pwdb; 1048 long entry_min_undecoratedsmoothed_pwdb;
892 long undecorated_smoothed_pwdb; /*out dm */ 1049 long undecorated_smoothed_pwdb; /*out dm */
893 long entry_max_undecoratedsmoothed_pwdb; 1050 long entry_max_undecoratedsmoothed_pwdb;
894 bool b_dm_initialgain_enable; 1051 bool dm_initialgain_enable;
895 bool bdynamic_txpower_enable; 1052 bool dynamic_txpower_enable;
896 bool bcurrent_turbo_edca; 1053 bool current_turbo_edca;
897 bool bis_any_nonbepkts; /*out dm */ 1054 bool is_any_nonbepkts; /*out dm */
898 bool bis_cur_rdlstate; 1055 bool is_cur_rdlstate;
899 bool btxpower_trackingInit; 1056 bool txpower_trackingInit;
900 bool b_disable_framebursting; 1057 bool disable_framebursting;
901 bool b_cck_inch14; 1058 bool cck_inch14;
902 bool btxpower_tracking; 1059 bool txpower_tracking;
903 bool b_useramask; 1060 bool useramask;
904 bool brfpath_rxenable[4]; 1061 bool rfpath_rxenable[4];
905 1062 bool inform_fw_driverctrldm;
1063 bool current_mrc_switch;
1064 u8 txpowercount;
1065
1066 u8 thermalvalue_rxgain;
906 u8 thermalvalue_iqk; 1067 u8 thermalvalue_iqk;
907 u8 thermalvalue_lck; 1068 u8 thermalvalue_lck;
908 u8 thermalvalue; 1069 u8 thermalvalue;
909 u8 last_dtp_lvl; 1070 u8 last_dtp_lvl;
1071 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1072 u8 thermalvalue_avg_index;
1073 bool done_txpower;
910 u8 dynamic_txhighpower_lvl; /*Tx high power level */ 1074 u8 dynamic_txhighpower_lvl; /*Tx high power level */
911 u8 dm_flag; /*Indicate if each dynamic mechanism's status. */ 1075 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
912 u8 dm_type; 1076 u8 dm_type;
913 u8 txpower_track_control; 1077 u8 txpower_track_control;
914 1078 bool interrupt_migration;
1079 bool disable_tx_int;
915 char ofdm_index[2]; 1080 char ofdm_index[2];
916 char cck_index; 1081 char cck_index;
1082 u8 power_index_backup[6];
917}; 1083};
918 1084
919#define EFUSE_MAX_LOGICAL_SIZE 128 1085#define EFUSE_MAX_LOGICAL_SIZE 256
920 1086
921struct rtl_efuse { 1087struct rtl_efuse {
922 bool bautoLoad_ok; 1088 bool autoLoad_ok;
923 bool bootfromefuse; 1089 bool bootfromefuse;
924 u16 max_physical_size; 1090 u16 max_physical_size;
925 u8 contents[EFUSE_MAX_LOGICAL_SIZE];
926 1091
927 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE]; 1092 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
928 u16 efuse_usedbytes; 1093 u16 efuse_usedbytes;
929 u8 efuse_usedpercentage; 1094 u8 efuse_usedpercentage;
1095#ifdef EFUSE_REPG_WORKAROUND
1096 bool efuse_re_pg_sec1flag;
1097 u8 efuse_re_pg_data[8];
1098#endif
930 1099
931 u8 autoload_failflag; 1100 u8 autoload_failflag;
1101 u8 autoload_status;
932 1102
933 short epromtype; 1103 short epromtype;
934 u16 eeprom_vid; 1104 u16 eeprom_vid;
@@ -938,69 +1108,90 @@ struct rtl_efuse {
938 u8 eeprom_oemid; 1108 u8 eeprom_oemid;
939 u16 eeprom_channelplan; 1109 u16 eeprom_channelplan;
940 u8 eeprom_version; 1110 u8 eeprom_version;
1111 u8 board_type;
1112 u8 external_pa;
941 1113
942 u8 dev_addr[6]; 1114 u8 dev_addr[6];
943 1115
944 bool b_txpwr_fromeprom; 1116 bool txpwr_fromeprom;
1117 u8 eeprom_crystalcap;
945 u8 eeprom_tssi[2]; 1118 u8 eeprom_tssi[2];
946 u8 eeprom_pwrlimit_ht20[3]; 1119 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
947 u8 eeprom_pwrlimit_ht40[3]; 1120 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
948 u8 eeprom_chnlarea_txpwr_cck[2][3]; 1121 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
949 u8 eeprom_chnlarea_txpwr_ht40_1s[2][3]; 1122 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
950 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][3]; 1123 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
951 u8 txpwrlevel_cck[2][14]; 1124 u8 eeprom_chnlarea_txpwr_ht40_2sdiif[2][CHANNEL_GROUP_MAX];
952 u8 txpwrlevel_ht40_1s[2][14]; /*For HT 40MHZ pwr */ 1125 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
953 u8 txpwrlevel_ht40_2s[2][14]; /*For HT 40MHZ pwr */ 1126 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1127 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1128
1129 u8 internal_pa_5g[2]; /* pathA / pathB */
1130 u8 eeprom_c9;
1131 u8 eeprom_cc;
954 1132
955 /*For power group */ 1133 /*For power group */
956 u8 pwrgroup_ht20[2][14]; 1134 u8 eeprom_pwrgroup[2][3];
957 u8 pwrgroup_ht40[2][14]; 1135 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
958 1136 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
959 char txpwr_ht20diff[2][14]; /*HT 20<->40 Pwr diff */ 1137
960 u8 txpwr_legacyhtdiff[2][14]; /*For HT<->legacy pwr diff */ 1138 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1139 /*For HT<->legacy pwr diff*/
1140 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1141 u8 txpwr_safetyflag; /* Band edge enable flag */
1142 u16 eeprom_txpowerdiff;
1143 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1144 u8 antenna_txpwdiff[3];
961 1145
962 u8 eeprom_regulatory; 1146 u8 eeprom_regulatory;
963 u8 eeprom_thermalmeter; 1147 u8 eeprom_thermalmeter;
964 /*ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 1148 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
965 u8 thermalmeter[2]; 1149 u16 tssi_13dbm;
1150 u8 crystalcap; /* CrystalCap. */
1151 u8 delta_iqk;
1152 u8 delta_lck;
966 1153
967 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */ 1154 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
968 bool b_apk_thermalmeterignore; 1155 bool apk_thermalmeterignore;
1156
1157 bool b1x1_recvcombine;
1158 bool b1ss_support;
1159
1160 /*channel plan */
1161 u8 channel_plan;
969}; 1162};
970 1163
971struct rtl_ps_ctl { 1164struct rtl_ps_ctl {
1165 bool pwrdomain_protect;
972 bool set_rfpowerstate_inprogress; 1166 bool set_rfpowerstate_inprogress;
973 bool b_in_powersavemode; 1167 bool in_powersavemode;
974 bool rfchange_inprogress; 1168 bool rfchange_inprogress;
975 bool b_swrf_processing; 1169 bool swrf_processing;
976 bool b_hwradiooff; 1170 bool hwradiooff;
977
978 u32 last_sleep_jiffies;
979 u32 last_awake_jiffies;
980 u32 last_delaylps_stamp_jiffies;
981 1171
982 /* 1172 /*
983 * just for PCIE ASPM 1173 * just for PCIE ASPM
984 * If it supports ASPM, Offset[560h] = 0x40, 1174 * If it supports ASPM, Offset[560h] = 0x40,
985 * otherwise Offset[560h] = 0x00. 1175 * otherwise Offset[560h] = 0x00.
986 * */ 1176 * */
987 bool b_support_aspm; 1177 bool support_aspm;
988 bool b_support_backdoor; 1178 bool support_backdoor;
989 1179
990 /*for LPS */ 1180 /*for LPS */
991 enum rt_psmode dot11_psmode; /*Power save mode configured. */ 1181 enum rt_psmode dot11_psmode; /*Power save mode configured. */
992 bool b_leisure_ps; 1182 bool swctrl_lps;
993 bool b_fwctrl_lps; 1183 bool leisure_ps;
1184 bool fwctrl_lps;
994 u8 fwctrl_psmode; 1185 u8 fwctrl_psmode;
995 /*For Fw control LPS mode */ 1186 /*For Fw control LPS mode */
996 u8 b_reg_fwctrl_lps; 1187 u8 reg_fwctrl_lps;
997 /*Record Fw PS mode status. */ 1188 /*Record Fw PS mode status. */
998 bool b_fw_current_inpsmode; 1189 bool fw_current_inpsmode;
999 u8 reg_max_lps_awakeintvl; 1190 u8 reg_max_lps_awakeintvl;
1000 bool report_linked; 1191 bool report_linked;
1001 1192
1002 /*for IPS */ 1193 /*for IPS */
1003 bool b_inactiveps; 1194 bool inactiveps;
1004 1195
1005 u32 rfoff_reason; 1196 u32 rfoff_reason;
1006 1197
@@ -1011,8 +1202,26 @@ struct rtl_ps_ctl {
1011 /*just for PCIE ASPM */ 1202 /*just for PCIE ASPM */
1012 u8 const_amdpci_aspm; 1203 u8 const_amdpci_aspm;
1013 1204
1205 bool pwrdown_mode;
1206
1014 enum rf_pwrstate inactive_pwrstate; 1207 enum rf_pwrstate inactive_pwrstate;
1015 enum rf_pwrstate rfpwr_state; /*cur power state */ 1208 enum rf_pwrstate rfpwr_state; /*cur power state */
1209
1210 /* for SW LPS*/
1211 bool sw_ps_enabled;
1212 bool state;
1213 bool state_inap;
1214 bool multi_buffered;
1215 u16 nullfunc_seq;
1216 unsigned int dtim_counter;
1217 unsigned int sleep_ms;
1218 unsigned long last_sleep_jiffies;
1219 unsigned long last_awake_jiffies;
1220 unsigned long last_delaylps_stamp_jiffies;
1221 unsigned long last_dtim;
1222 unsigned long last_beacon;
1223 unsigned long last_action;
1224 unsigned long last_slept;
1016}; 1225};
1017 1226
1018struct rtl_stats { 1227struct rtl_stats {
@@ -1038,10 +1247,10 @@ struct rtl_stats {
1038 s32 recvsignalpower; 1247 s32 recvsignalpower;
1039 s8 rxpower; /*in dBm Translate from PWdB */ 1248 s8 rxpower; /*in dBm Translate from PWdB */
1040 u8 signalstrength; /*in 0-100 index. */ 1249 u8 signalstrength; /*in 0-100 index. */
1041 u16 b_hwerror:1; 1250 u16 hwerror:1;
1042 u16 b_crc:1; 1251 u16 crc:1;
1043 u16 b_icv:1; 1252 u16 icv:1;
1044 u16 b_shortpreamble:1; 1253 u16 shortpreamble:1;
1045 u16 antenna:1; 1254 u16 antenna:1;
1046 u16 decrypted:1; 1255 u16 decrypted:1;
1047 u16 wakeup:1; 1256 u16 wakeup:1;
@@ -1050,15 +1259,16 @@ struct rtl_stats {
1050 1259
1051 u8 rx_drvinfo_size; 1260 u8 rx_drvinfo_size;
1052 u8 rx_bufshift; 1261 u8 rx_bufshift;
1053 bool b_isampdu; 1262 bool isampdu;
1263 bool isfirst_ampdu;
1054 bool rx_is40Mhzpacket; 1264 bool rx_is40Mhzpacket;
1055 u32 rx_pwdb_all; 1265 u32 rx_pwdb_all;
1056 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */ 1266 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1057 s8 rx_mimo_signalquality[2]; 1267 s8 rx_mimo_signalquality[2];
1058 bool b_packet_matchbssid; 1268 bool packet_matchbssid;
1059 bool b_is_cck; 1269 bool is_cck;
1060 bool b_packet_toself; 1270 bool packet_toself;
1061 bool b_packet_beacon; /*for rssi */ 1271 bool packet_beacon; /*for rssi */
1062 char cck_adc_pwdb[4]; /*for rx path selection */ 1272 char cck_adc_pwdb[4]; /*for rx path selection */
1063}; 1273};
1064 1274
@@ -1069,23 +1279,23 @@ struct rt_link_detect {
1069 u32 num_tx_inperiod; 1279 u32 num_tx_inperiod;
1070 u32 num_rx_inperiod; 1280 u32 num_rx_inperiod;
1071 1281
1072 bool b_busytraffic; 1282 bool busytraffic;
1073 bool b_higher_busytraffic; 1283 bool higher_busytraffic;
1074 bool b_higher_busyrxtraffic; 1284 bool higher_busyrxtraffic;
1075}; 1285};
1076 1286
1077struct rtl_tcb_desc { 1287struct rtl_tcb_desc {
1078 u8 b_packet_bw:1; 1288 u8 packet_bw:1;
1079 u8 b_multicast:1; 1289 u8 multicast:1;
1080 u8 b_broadcast:1; 1290 u8 broadcast:1;
1081 1291
1082 u8 b_rts_stbc:1; 1292 u8 rts_stbc:1;
1083 u8 b_rts_enable:1; 1293 u8 rts_enable:1;
1084 u8 b_cts_enable:1; 1294 u8 cts_enable:1;
1085 u8 b_rts_use_shortpreamble:1; 1295 u8 rts_use_shortpreamble:1;
1086 u8 b_rts_use_shortgi:1; 1296 u8 rts_use_shortgi:1;
1087 u8 rts_sc:1; 1297 u8 rts_sc:1;
1088 u8 b_rts_bw:1; 1298 u8 rts_bw:1;
1089 u8 rts_rate; 1299 u8 rts_rate;
1090 1300
1091 u8 use_shortgi:1; 1301 u8 use_shortgi:1;
@@ -1096,20 +1306,34 @@ struct rtl_tcb_desc {
1096 u8 ratr_index; 1306 u8 ratr_index;
1097 u8 mac_id; 1307 u8 mac_id;
1098 u8 hw_rate; 1308 u8 hw_rate;
1309
1310 u8 last_inipkt:1;
1311 u8 cmd_or_init:1;
1312 u8 queue_index;
1313
1314 /* early mode */
1315 u8 empkt_num;
1316 /* The max value by HW */
1317 u32 empkt_len[5];
1099}; 1318};
1100 1319
1101struct rtl_hal_ops { 1320struct rtl_hal_ops {
1102 int (*init_sw_vars) (struct ieee80211_hw *hw); 1321 int (*init_sw_vars) (struct ieee80211_hw *hw);
1103 void (*deinit_sw_vars) (struct ieee80211_hw *hw); 1322 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1323 void (*read_chip_version)(struct ieee80211_hw *hw);
1104 void (*read_eeprom_info) (struct ieee80211_hw *hw); 1324 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1105 void (*interrupt_recognized) (struct ieee80211_hw *hw, 1325 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1106 u32 *p_inta, u32 *p_intb); 1326 u32 *p_inta, u32 *p_intb);
1107 int (*hw_init) (struct ieee80211_hw *hw); 1327 int (*hw_init) (struct ieee80211_hw *hw);
1108 void (*hw_disable) (struct ieee80211_hw *hw); 1328 void (*hw_disable) (struct ieee80211_hw *hw);
1329 void (*hw_suspend) (struct ieee80211_hw *hw);
1330 void (*hw_resume) (struct ieee80211_hw *hw);
1109 void (*enable_interrupt) (struct ieee80211_hw *hw); 1331 void (*enable_interrupt) (struct ieee80211_hw *hw);
1110 void (*disable_interrupt) (struct ieee80211_hw *hw); 1332 void (*disable_interrupt) (struct ieee80211_hw *hw);
1111 int (*set_network_type) (struct ieee80211_hw *hw, 1333 int (*set_network_type) (struct ieee80211_hw *hw,
1112 enum nl80211_iftype type); 1334 enum nl80211_iftype type);
1335 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1336 bool check_bssid);
1113 void (*set_bw_mode) (struct ieee80211_hw *hw, 1337 void (*set_bw_mode) (struct ieee80211_hw *hw,
1114 enum nl80211_channel_type ch_type); 1338 enum nl80211_channel_type ch_type);
1115 u8(*switch_channel) (struct ieee80211_hw *hw); 1339 u8(*switch_channel) (struct ieee80211_hw *hw);
@@ -1126,23 +1350,26 @@ struct rtl_hal_ops {
1126 struct ieee80211_hdr *hdr, u8 *pdesc_tx, 1350 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1127 struct ieee80211_tx_info *info, 1351 struct ieee80211_tx_info *info,
1128 struct sk_buff *skb, unsigned int queue_index); 1352 struct sk_buff *skb, unsigned int queue_index);
1353 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 * pDesc,
1354 u32 buffer_len, bool bIsPsPoll);
1129 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc, 1355 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1130 bool b_firstseg, bool b_lastseg, 1356 bool firstseg, bool lastseg,
1131 struct sk_buff *skb); 1357 struct sk_buff *skb);
1132 bool(*query_rx_desc) (struct ieee80211_hw *hw, 1358 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1359 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1133 struct rtl_stats *stats, 1360 struct rtl_stats *stats,
1134 struct ieee80211_rx_status *rx_status, 1361 struct ieee80211_rx_status *rx_status,
1135 u8 *pdesc, struct sk_buff *skb); 1362 u8 *pdesc, struct sk_buff *skb);
1136 void (*set_channel_access) (struct ieee80211_hw *hw); 1363 void (*set_channel_access) (struct ieee80211_hw *hw);
1137 bool(*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid); 1364 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1138 void (*dm_watchdog) (struct ieee80211_hw *hw); 1365 void (*dm_watchdog) (struct ieee80211_hw *hw);
1139 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation); 1366 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1140 bool(*set_rf_power_state) (struct ieee80211_hw *hw, 1367 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1141 enum rf_pwrstate rfpwr_state); 1368 enum rf_pwrstate rfpwr_state);
1142 void (*led_control) (struct ieee80211_hw *hw, 1369 void (*led_control) (struct ieee80211_hw *hw,
1143 enum led_ctl_mode ledaction); 1370 enum led_ctl_mode ledaction);
1144 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val); 1371 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1145 u32(*get_desc) (u8 *pdesc, bool istx, u8 desc_name); 1372 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1146 void (*tx_polling) (struct ieee80211_hw *hw, unsigned int hw_queue); 1373 void (*tx_polling) (struct ieee80211_hw *hw, unsigned int hw_queue);
1147 void (*enable_hw_sec) (struct ieee80211_hw *hw); 1374 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1148 void (*set_key) (struct ieee80211_hw *hw, u32 key_index, 1375 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
@@ -1150,22 +1377,36 @@ struct rtl_hal_ops {
1150 bool is_wepkey, bool clear_all); 1377 bool is_wepkey, bool clear_all);
1151 void (*init_sw_leds) (struct ieee80211_hw *hw); 1378 void (*init_sw_leds) (struct ieee80211_hw *hw);
1152 void (*deinit_sw_leds) (struct ieee80211_hw *hw); 1379 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1153 u32(*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask); 1380 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1154 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask, 1381 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1155 u32 data); 1382 u32 data);
1156 u32(*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 1383 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1157 u32 regaddr, u32 bitmask); 1384 u32 regaddr, u32 bitmask);
1158 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath, 1385 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1159 u32 regaddr, u32 bitmask, u32 data); 1386 u32 regaddr, u32 bitmask, u32 data);
1387 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1388 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1389 u8 *powerlevel);
1390 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1391 u8 *ppowerlevel, u8 channel);
1392 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1393 u8 configtype);
1394 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1395 u8 configtype);
1396 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1397 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1398 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1160}; 1399};
1161 1400
1162struct rtl_intf_ops { 1401struct rtl_intf_ops {
1163 /*com */ 1402 /*com */
1403 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1164 int (*adapter_start) (struct ieee80211_hw *hw); 1404 int (*adapter_start) (struct ieee80211_hw *hw);
1165 void (*adapter_stop) (struct ieee80211_hw *hw); 1405 void (*adapter_stop) (struct ieee80211_hw *hw);
1166 1406
1167 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb); 1407 int (*adapter_tx) (struct ieee80211_hw *hw, struct sk_buff *skb);
1168 int (*reset_trx_ring) (struct ieee80211_hw *hw); 1408 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1409 bool (*waitq_insert) (struct ieee80211_hw *hw, struct sk_buff *skb);
1169 1410
1170 /*pci */ 1411 /*pci */
1171 void (*disable_aspm) (struct ieee80211_hw *hw); 1412 void (*disable_aspm) (struct ieee80211_hw *hw);
@@ -1179,11 +1420,36 @@ struct rtl_mod_params {
1179 int sw_crypto; 1420 int sw_crypto;
1180}; 1421};
1181 1422
1423struct rtl_hal_usbint_cfg {
1424 /* data - rx */
1425 u32 in_ep_num;
1426 u32 rx_urb_num;
1427 u32 rx_max_size;
1428
1429 /* op - rx */
1430 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1431 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1432 struct sk_buff_head *);
1433
1434 /* tx */
1435 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1436 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1437 struct sk_buff *);
1438 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1439 struct sk_buff_head *);
1440
1441 /* endpoint mapping */
1442 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1443 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1444};
1445
1182struct rtl_hal_cfg { 1446struct rtl_hal_cfg {
1447 u8 bar_id;
1183 char *name; 1448 char *name;
1184 char *fw_name; 1449 char *fw_name;
1185 struct rtl_hal_ops *ops; 1450 struct rtl_hal_ops *ops;
1186 struct rtl_mod_params *mod_params; 1451 struct rtl_mod_params *mod_params;
1452 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1187 1453
1188 /*this map used for some registers or vars 1454 /*this map used for some registers or vars
1189 defined int HAL but used in MAIN */ 1455 defined int HAL but used in MAIN */
@@ -1202,6 +1468,11 @@ struct rtl_locks {
1202 spinlock_t rf_ps_lock; 1468 spinlock_t rf_ps_lock;
1203 spinlock_t rf_lock; 1469 spinlock_t rf_lock;
1204 spinlock_t lps_lock; 1470 spinlock_t lps_lock;
1471 spinlock_t waitq_lock;
1472 spinlock_t tx_urb_lock;
1473
1474 /*Dual mac*/
1475 spinlock_t cck_and_rw_pagea_lock;
1205}; 1476};
1206 1477
1207struct rtl_works { 1478struct rtl_works {
@@ -1218,12 +1489,20 @@ struct rtl_works {
1218 struct workqueue_struct *rtl_wq; 1489 struct workqueue_struct *rtl_wq;
1219 struct delayed_work watchdog_wq; 1490 struct delayed_work watchdog_wq;
1220 struct delayed_work ips_nic_off_wq; 1491 struct delayed_work ips_nic_off_wq;
1492
1493 /* For SW LPS */
1494 struct delayed_work ps_work;
1495 struct delayed_work ps_rfon_wq;
1221}; 1496};
1222 1497
1223struct rtl_debug { 1498struct rtl_debug {
1224 u32 dbgp_type[DBGP_TYPE_MAX]; 1499 u32 dbgp_type[DBGP_TYPE_MAX];
1225 u32 global_debuglevel; 1500 u32 global_debuglevel;
1226 u64 global_debugcomponents; 1501 u64 global_debugcomponents;
1502
1503 /* add for proc debug */
1504 struct proc_dir_entry *proc_dir;
1505 char proc_name[20];
1227}; 1506};
1228 1507
1229struct rtl_priv { 1508struct rtl_priv {
@@ -1274,6 +1553,91 @@ struct rtl_priv {
1274#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse)) 1553#define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
1275#define rtl_psc(rtlpriv) (&((rtlpriv)->psc)) 1554#define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
1276 1555
1556
1557/***************************************
1558 Bluetooth Co-existance Related
1559****************************************/
1560
1561enum bt_ant_num {
1562 ANT_X2 = 0,
1563 ANT_X1 = 1,
1564};
1565
1566enum bt_co_type {
1567 BT_2WIRE = 0,
1568 BT_ISSC_3WIRE = 1,
1569 BT_ACCEL = 2,
1570 BT_CSR_BC4 = 3,
1571 BT_CSR_BC8 = 4,
1572 BT_RTL8756 = 5,
1573};
1574
1575enum bt_cur_state {
1576 BT_OFF = 0,
1577 BT_ON = 1,
1578};
1579
1580enum bt_service_type {
1581 BT_SCO = 0,
1582 BT_A2DP = 1,
1583 BT_HID = 2,
1584 BT_HID_IDLE = 3,
1585 BT_SCAN = 4,
1586 BT_IDLE = 5,
1587 BT_OTHER_ACTION = 6,
1588 BT_BUSY = 7,
1589 BT_OTHERBUSY = 8,
1590 BT_PAN = 9,
1591};
1592
1593enum bt_radio_shared {
1594 BT_RADIO_SHARED = 0,
1595 BT_RADIO_INDIVIDUAL = 1,
1596};
1597
1598struct bt_coexist_info {
1599
1600 /* EEPROM BT info. */
1601 u8 eeprom_bt_coexist;
1602 u8 eeprom_bt_type;
1603 u8 eeprom_bt_ant_num;
1604 u8 eeprom_bt_ant_isolation;
1605 u8 eeprom_bt_radio_shared;
1606
1607 u8 bt_coexistence;
1608 u8 bt_ant_num;
1609 u8 bt_coexist_type;
1610 u8 bt_state;
1611 u8 bt_cur_state; /* 0:on, 1:off */
1612 u8 bt_ant_isolation; /* 0:good, 1:bad */
1613 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
1614 u8 bt_service;
1615 u8 bt_radio_shared_type;
1616 u8 bt_rfreg_origin_1e;
1617 u8 bt_rfreg_origin_1f;
1618 u8 bt_rssi_state;
1619 u32 ratio_tx;
1620 u32 ratio_pri;
1621 u32 bt_edca_ul;
1622 u32 bt_edca_dl;
1623
1624 bool b_init_set;
1625 bool b_bt_busy_traffic;
1626 bool b_bt_traffic_mode_set;
1627 bool b_bt_non_traffic_mode_set;
1628
1629 bool b_fw_coexist_all_off;
1630 bool b_sw_coexist_all_off;
1631 u32 current_state;
1632 u32 previous_state;
1633 u8 bt_pre_rssi_state;
1634
1635 u8 b_reg_bt_iso;
1636 u8 b_reg_bt_sco;
1637
1638};
1639
1640
1277/**************************************** 1641/****************************************
1278 mem access macro define start 1642 mem access macro define start
1279 Call endian free function when 1643 Call endian free function when
@@ -1281,7 +1645,7 @@ struct rtl_priv {
1281 2. Before write integer to IO. 1645 2. Before write integer to IO.
1282 3. After read integer from IO. 1646 3. After read integer from IO.
1283****************************************/ 1647****************************************/
1284/* Convert little data endian to host */ 1648/* Convert little data endian to host ordering */
1285#define EF1BYTE(_val) \ 1649#define EF1BYTE(_val) \
1286 ((u8)(_val)) 1650 ((u8)(_val))
1287#define EF2BYTE(_val) \ 1651#define EF2BYTE(_val) \
@@ -1289,27 +1653,21 @@ struct rtl_priv {
1289#define EF4BYTE(_val) \ 1653#define EF4BYTE(_val) \
1290 (le32_to_cpu(_val)) 1654 (le32_to_cpu(_val))
1291 1655
1292/* Read data from memory */ 1656/* Read le16 data from memory and convert to host ordering */
1293#define READEF1BYTE(_ptr) \
1294 EF1BYTE(*((u8 *)(_ptr)))
1295#define READEF2BYTE(_ptr) \ 1657#define READEF2BYTE(_ptr) \
1296 EF2BYTE(*((u16 *)(_ptr))) 1658 EF2BYTE(*((u16 *)(_ptr)))
1297#define READEF4BYTE(_ptr) \
1298 EF4BYTE(*((u32 *)(_ptr)))
1299 1659
1300/* Write data to memory */ 1660/* Write le16 data to memory in host ordering */
1301#define WRITEEF1BYTE(_ptr, _val) \
1302 (*((u8 *)(_ptr))) = EF1BYTE(_val)
1303#define WRITEEF2BYTE(_ptr, _val) \ 1661#define WRITEEF2BYTE(_ptr, _val) \
1304 (*((u16 *)(_ptr))) = EF2BYTE(_val) 1662 (*((u16 *)(_ptr))) = EF2BYTE(_val)
1305#define WRITEEF4BYTE(_ptr, _val) \ 1663
1306 (*((u32 *)(_ptr))) = EF4BYTE(_val) 1664/* Create a bit mask
1307 1665 * Examples:
1308/*Example: 1666 * BIT_LEN_MASK_32(0) => 0x00000000
1309BIT_LEN_MASK_32(0) => 0x00000000 1667 * BIT_LEN_MASK_32(1) => 0x00000001
1310BIT_LEN_MASK_32(1) => 0x00000001 1668 * BIT_LEN_MASK_32(2) => 0x00000003
1311BIT_LEN_MASK_32(2) => 0x00000003 1669 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
1312BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/ 1670 */
1313#define BIT_LEN_MASK_32(__bitlen) \ 1671#define BIT_LEN_MASK_32(__bitlen) \
1314 (0xFFFFFFFF >> (32 - (__bitlen))) 1672 (0xFFFFFFFF >> (32 - (__bitlen)))
1315#define BIT_LEN_MASK_16(__bitlen) \ 1673#define BIT_LEN_MASK_16(__bitlen) \
@@ -1317,9 +1675,11 @@ BIT_LEN_MASK_32(32) => 0xFFFFFFFF*/
1317#define BIT_LEN_MASK_8(__bitlen) \ 1675#define BIT_LEN_MASK_8(__bitlen) \
1318 (0xFF >> (8 - (__bitlen))) 1676 (0xFF >> (8 - (__bitlen)))
1319 1677
1320/*Example: 1678/* Create an offset bit mask
1321BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 1679 * Examples:
1322BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000*/ 1680 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
1681 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
1682 */
1323#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \ 1683#define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
1324 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset)) 1684 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
1325#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \ 1685#define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
@@ -1328,8 +1688,9 @@ BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000*/
1328 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset)) 1688 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
1329 1689
1330/*Description: 1690/*Description:
1331Return 4-byte value in host byte ordering from 1691 * Return 4-byte value in host byte ordering from
13324-byte pointer in little-endian system.*/ 1692 * 4-byte pointer in little-endian system.
1693 */
1333#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \ 1694#define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
1334 (EF4BYTE(*((u32 *)(__pstart)))) 1695 (EF4BYTE(*((u32 *)(__pstart))))
1335#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \ 1696#define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
@@ -1337,28 +1698,10 @@ Return 4-byte value in host byte ordering from
1337#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \ 1698#define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
1338 (EF1BYTE(*((u8 *)(__pstart)))) 1699 (EF1BYTE(*((u8 *)(__pstart))))
1339 1700
1340/*Description: 1701/* Description:
1341Translate subfield (continuous bits in little-endian) of 4-byte 1702 * Mask subfield (continuous bits in little-endian) of 4-byte value
1342value to host byte ordering.*/ 1703 * and return the result in 4-byte value in host byte ordering.
1343#define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 1704 */
1344 ( \
1345 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
1346 BIT_LEN_MASK_32(__bitlen) \
1347 )
1348#define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
1349 ( \
1350 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
1351 BIT_LEN_MASK_16(__bitlen) \
1352 )
1353#define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
1354 ( \
1355 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
1356 BIT_LEN_MASK_8(__bitlen) \
1357 )
1358
1359/*Description:
1360Mask subfield (continuous bits in little-endian) of 4-byte value
1361and return the result in 4-byte value in host byte ordering.*/
1362#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \ 1705#define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
1363 ( \ 1706 ( \
1364 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \ 1707 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
@@ -1375,20 +1718,9 @@ and return the result in 4-byte value in host byte ordering.*/
1375 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \ 1718 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
1376 ) 1719 )
1377 1720
1378/*Description: 1721/* Description:
1379Set subfield of little-endian 4-byte value to specified value. */ 1722 * Set subfield of little-endian 4-byte value to specified value.
1380#define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \ 1723 */
1381 *((u32 *)(__pstart)) = EF4BYTE \
1382 ( \
1383 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
1384 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
1385 );
1386#define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
1387 *((u16 *)(__pstart)) = EF2BYTE \
1388 ( \
1389 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
1390 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
1391 );
1392#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \ 1724#define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
1393 *((u8 *)(__pstart)) = EF1BYTE \ 1725 *((u8 *)(__pstart)) = EF1BYTE \
1394 ( \ 1726 ( \
@@ -1400,13 +1732,14 @@ Set subfield of little-endian 4-byte value to specified value. */
1400 mem access macro define end 1732 mem access macro define end
1401****************************************/ 1733****************************************/
1402 1734
1403#define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC) 1735#define byte(x, n) ((x >> (8 * n)) & 0xff)
1736
1404#define RTL_WATCH_DOG_TIME 2000 1737#define RTL_WATCH_DOG_TIME 2000
1405#define MSECS(t) msecs_to_jiffies(t) 1738#define MSECS(t) msecs_to_jiffies(t)
1406#define WLAN_FC_GET_VERS(fc) ((fc) & IEEE80211_FCTL_VERS) 1739#define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
1407#define WLAN_FC_GET_TYPE(fc) ((fc) & IEEE80211_FCTL_FTYPE) 1740#define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
1408#define WLAN_FC_GET_STYPE(fc) ((fc) & IEEE80211_FCTL_STYPE) 1741#define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
1409#define WLAN_FC_MORE_DATA(fc) ((fc) & IEEE80211_FCTL_MOREDATA) 1742#define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
1410#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4) 1743#define SEQ_TO_SN(seq) (((seq) & IEEE80211_SCTL_SEQ) >> 4)
1411#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ) 1744#define SN_TO_SEQ(ssn) (((ssn) << 4) & IEEE80211_SCTL_SEQ)
1412#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4) 1745#define MAX_SN ((IEEE80211_SCTL_SEQ) >> 4)
@@ -1420,6 +1753,8 @@ Set subfield of little-endian 4-byte value to specified value. */
1420#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */ 1753#define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
1421/*Always enable ASPM and Clock Req in initialization.*/ 1754/*Always enable ASPM and Clock Req in initialization.*/
1422#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) 1755#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
1756/* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
1757#define RT_PS_LEVEL_ASPM BIT(7)
1423/*When LPS is on, disable 2R if no packet is received or transmittd.*/ 1758/*When LPS is on, disable 2R if no packet is received or transmittd.*/
1424#define RT_RF_LPS_DISALBE_2R BIT(30) 1759#define RT_RF_LPS_DISALBE_2R BIT(30)
1425#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */ 1760#define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
@@ -1433,15 +1768,6 @@ Set subfield of little-endian 4-byte value to specified value. */
1433#define container_of_dwork_rtl(x, y, z) \ 1768#define container_of_dwork_rtl(x, y, z) \
1434 container_of(container_of(x, struct delayed_work, work), y, z) 1769 container_of(container_of(x, struct delayed_work, work), y, z)
1435 1770
1436#define FILL_OCTET_STRING(_os, _octet, _len) \
1437 (_os).octet = (u8 *)(_octet); \
1438 (_os).length = (_len);
1439
1440#define CP_MACADDR(des, src) \
1441 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
1442 (des)[2] = (src)[2], (des)[3] = (src)[3],\
1443 (des)[4] = (src)[4], (des)[5] = (src)[5])
1444
1445static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr) 1771static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
1446{ 1772{
1447 return rtlpriv->io.read8_sync(rtlpriv, addr); 1773 return rtlpriv->io.read8_sync(rtlpriv, addr);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-31 11:11:25 -0500