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authorLarry Finger <Larry.Finger@lwfinger.net>2014-02-28 16:16:47 -0500
committerJohn W. Linville <linville@tuxdriver.com>2014-03-04 13:19:37 -0500
commit0a168b48cdf7c22cf0250f62df4dde20adebf74b (patch)
treedb687ec89af8dcbb25438fa4ce73e599191575e1 /drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
parent2cddad3c737a35118151ec930fb43a710b3646d2 (diff)
rtlwifi: rtl8723ae: rtl8723-common: Create new driver for common code
The drivers for RTL8723AE and RTL8723BE have some code in common. This commit creates a driver for this code that will be shared, and copies those common routines from rtl8723ae's phy code. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8723ae/phy.c')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8723ae/phy.c482
1 files changed, 46 insertions, 436 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c b/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
index 5d318a85eda4..4f8189d3bb44 100644
--- a/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8723ae/phy.c
@@ -36,6 +36,7 @@
36#include "rf.h" 36#include "rf.h"
37#include "dm.h" 37#include "dm.h"
38#include "table.h" 38#include "table.h"
39#include "../rtl8723com/phy_common.h"
39 40
40/* static forward definitions */ 41/* static forward definitions */
41static u32 _phy_fw_rf_serial_read(struct ieee80211_hw *hw, 42static u32 _phy_fw_rf_serial_read(struct ieee80211_hw *hw,
@@ -43,72 +44,17 @@ static u32 _phy_fw_rf_serial_read(struct ieee80211_hw *hw,
43static void _phy_fw_rf_serial_write(struct ieee80211_hw *hw, 44static void _phy_fw_rf_serial_write(struct ieee80211_hw *hw,
44 enum radio_path rfpath, 45 enum radio_path rfpath,
45 u32 offset, u32 data); 46 u32 offset, u32 data);
46static u32 _phy_rf_serial_read(struct ieee80211_hw *hw,
47 enum radio_path rfpath, u32 offset);
48static void _phy_rf_serial_write(struct ieee80211_hw *hw,
49 enum radio_path rfpath, u32 offset, u32 data);
50static u32 _phy_calculate_bit_shift(u32 bitmask);
51static bool _phy_bb8192c_config_parafile(struct ieee80211_hw *hw); 47static bool _phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
52static bool _phy_cfg_mac_w_header(struct ieee80211_hw *hw); 48static bool _phy_cfg_mac_w_header(struct ieee80211_hw *hw);
53static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype); 49static bool _phy_cfg_bb_w_header(struct ieee80211_hw *hw, u8 configtype);
54static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype); 50static bool _phy_cfg_bb_w_pgheader(struct ieee80211_hw *hw, u8 configtype);
55static void _phy_init_bb_rf_reg_def(struct ieee80211_hw *hw);
56static bool _phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
57 u32 cmdtableidx, u32 cmdtablesz,
58 enum swchnlcmd_id cmdid,
59 u32 para1, u32 para2,
60 u32 msdelay);
61static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel, 51static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
62 u8 *stage, u8 *step, u32 *delay); 52 u8 *stage, u8 *step, u32 *delay);
63static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw, 53static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
64 enum wireless_mode wirelessmode, 54 enum wireless_mode wirelessmode,
65 long power_indbm); 55 long power_indbm);
66static long _phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
67 enum wireless_mode wirelessmode, u8 txpwridx);
68static void rtl8723ae_phy_set_io(struct ieee80211_hw *hw); 56static void rtl8723ae_phy_set_io(struct ieee80211_hw *hw);
69 57
70u32 rtl8723ae_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr,
71 u32 bitmask)
72{
73 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 u32 returnvalue, originalvalue, bitshift;
75
76 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
77 "regaddr(%#x), bitmask(%#x)\n", regaddr, bitmask);
78 originalvalue = rtl_read_dword(rtlpriv, regaddr);
79 bitshift = _phy_calculate_bit_shift(bitmask);
80 returnvalue = (originalvalue & bitmask) >> bitshift;
81
82 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
83 "BBR MASK=0x%x Addr[0x%x]=0x%x\n", bitmask, regaddr,
84 originalvalue);
85
86 return returnvalue;
87}
88
89void rtl8723ae_phy_set_bb_reg(struct ieee80211_hw *hw,
90 u32 regaddr, u32 bitmask, u32 data)
91{
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93 u32 originalvalue, bitshift;
94
95 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
96 "regaddr(%#x), bitmask(%#x), data(%#x)\n", regaddr,
97 bitmask, data);
98
99 if (bitmask != MASKDWORD) {
100 originalvalue = rtl_read_dword(rtlpriv, regaddr);
101 bitshift = _phy_calculate_bit_shift(bitmask);
102 data = ((originalvalue & (~bitmask)) | (data << bitshift));
103 }
104
105 rtl_write_dword(rtlpriv, regaddr, data);
106
107 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
108 "regaddr(%#x), bitmask(%#x), data(%#x)\n",
109 regaddr, bitmask, data);
110}
111
112u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw, 58u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw,
113 enum radio_path rfpath, u32 regaddr, u32 bitmask) 59 enum radio_path rfpath, u32 regaddr, u32 bitmask)
114{ 60{
@@ -124,11 +70,11 @@ u32 rtl8723ae_phy_query_rf_reg(struct ieee80211_hw *hw,
124 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags); 70 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
125 71
126 if (rtlphy->rf_mode != RF_OP_BY_FW) 72 if (rtlphy->rf_mode != RF_OP_BY_FW)
127 original_value = _phy_rf_serial_read(hw, rfpath, regaddr); 73 original_value = rtl8723_phy_rf_serial_read(hw, rfpath, regaddr);
128 else 74 else
129 original_value = _phy_fw_rf_serial_read(hw, rfpath, regaddr); 75 original_value = _phy_fw_rf_serial_read(hw, rfpath, regaddr);
130 76
131 bitshift = _phy_calculate_bit_shift(bitmask); 77 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
132 readback_value = (original_value & bitmask) >> bitshift; 78 readback_value = (original_value & bitmask) >> bitshift;
133 79
134 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags); 80 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
@@ -157,19 +103,19 @@ void rtl8723ae_phy_set_rf_reg(struct ieee80211_hw *hw,
157 103
158 if (rtlphy->rf_mode != RF_OP_BY_FW) { 104 if (rtlphy->rf_mode != RF_OP_BY_FW) {
159 if (bitmask != RFREG_OFFSET_MASK) { 105 if (bitmask != RFREG_OFFSET_MASK) {
160 original_value = _phy_rf_serial_read(hw, rfpath, 106 original_value = rtl8723_phy_rf_serial_read(hw, rfpath,
161 regaddr); 107 regaddr);
162 bitshift = _phy_calculate_bit_shift(bitmask); 108 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
163 data = ((original_value & (~bitmask)) | 109 data = ((original_value & (~bitmask)) |
164 (data << bitshift)); 110 (data << bitshift));
165 } 111 }
166 112
167 _phy_rf_serial_write(hw, rfpath, regaddr, data); 113 rtl8723_phy_rf_serial_write(hw, rfpath, regaddr, data);
168 } else { 114 } else {
169 if (bitmask != RFREG_OFFSET_MASK) { 115 if (bitmask != RFREG_OFFSET_MASK) {
170 original_value = _phy_fw_rf_serial_read(hw, rfpath, 116 original_value = _phy_fw_rf_serial_read(hw, rfpath,
171 regaddr); 117 regaddr);
172 bitshift = _phy_calculate_bit_shift(bitmask); 118 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
173 data = ((original_value & (~bitmask)) | 119 data = ((original_value & (~bitmask)) |
174 (data << bitshift)); 120 (data << bitshift));
175 } 121 }
@@ -197,87 +143,6 @@ static void _phy_fw_rf_serial_write(struct ieee80211_hw *hw,
197 RT_ASSERT(false, "deprecated!\n"); 143 RT_ASSERT(false, "deprecated!\n");
198} 144}
199 145
200static u32 _phy_rf_serial_read(struct ieee80211_hw *hw,
201 enum radio_path rfpath, u32 offset)
202{
203 struct rtl_priv *rtlpriv = rtl_priv(hw);
204 struct rtl_phy *rtlphy = &(rtlpriv->phy);
205 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
206 u32 newoffset;
207 u32 tmplong, tmplong2;
208 u8 rfpi_enable = 0;
209 u32 retvalue;
210
211 offset &= 0x3f;
212 newoffset = offset;
213 if (RT_CANNOT_IO(hw)) {
214 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
215 return 0xFFFFFFFF;
216 }
217 tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
218 if (rfpath == RF90_PATH_A)
219 tmplong2 = tmplong;
220 else
221 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
222 tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
223 (newoffset << 23) | BLSSIREADEDGE;
224 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
225 tmplong & (~BLSSIREADEDGE));
226 mdelay(1);
227 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
228 mdelay(1);
229 rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
230 tmplong | BLSSIREADEDGE);
231 mdelay(1);
232 if (rfpath == RF90_PATH_A)
233 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
234 BIT(8));
235 else if (rfpath == RF90_PATH_B)
236 rfpi_enable = (u8) rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
237 BIT(8));
238 if (rfpi_enable)
239 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
240 BLSSIREADBACKDATA);
241 else
242 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
243 BLSSIREADBACKDATA);
244 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
245 rfpath, pphyreg->rf_rb, retvalue);
246 return retvalue;
247}
248
249static void _phy_rf_serial_write(struct ieee80211_hw *hw,
250 enum radio_path rfpath, u32 offset, u32 data)
251{
252 u32 data_and_addr;
253 u32 newoffset;
254 struct rtl_priv *rtlpriv = rtl_priv(hw);
255 struct rtl_phy *rtlphy = &(rtlpriv->phy);
256 struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
257
258 if (RT_CANNOT_IO(hw)) {
259 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
260 return;
261 }
262 offset &= 0x3f;
263 newoffset = offset;
264 data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
265 rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
266 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
267 rfpath, pphyreg->rf3wire_offset, data_and_addr);
268}
269
270static u32 _phy_calculate_bit_shift(u32 bitmask)
271{
272 u32 i;
273
274 for (i = 0; i <= 31; i++) {
275 if (((bitmask >> i) & 0x1) == 1)
276 break;
277 }
278 return i;
279}
280
281static void _rtl8723ae_phy_bb_config_1t(struct ieee80211_hw *hw) 146static void _rtl8723ae_phy_bb_config_1t(struct ieee80211_hw *hw)
282{ 147{
283 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2); 148 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
@@ -307,7 +172,7 @@ bool rtl8723ae_phy_bb_config(struct ieee80211_hw *hw)
307 u8 tmpu1b; 172 u8 tmpu1b;
308 u8 reg_hwparafile = 1; 173 u8 reg_hwparafile = 1;
309 174
310 _phy_init_bb_rf_reg_def(hw); 175 rtl8723_phy_init_bb_rf_reg_def(hw);
311 176
312 /* 1. 0x28[1] = 1 */ 177 /* 1. 0x28[1] = 1 */
313 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_PLL_CTRL); 178 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_PLL_CTRL);
@@ -690,92 +555,6 @@ void rtl8723ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
690 ROFDM0_RXDETECTOR3, rtlphy->framesync); 555 ROFDM0_RXDETECTOR3, rtlphy->framesync);
691} 556}
692 557
693static void _phy_init_bb_rf_reg_def(struct ieee80211_hw *hw)
694{
695 struct rtl_priv *rtlpriv = rtl_priv(hw);
696 struct rtl_phy *rtlphy = &(rtlpriv->phy);
697
698 rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
699 rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
700 rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
701 rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
702
703 rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
704 rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
705 rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
706 rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
707
708 rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
709 rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
710
711 rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
712 rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
713
714 rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
715 RFPGA0_XA_LSSIPARAMETER;
716 rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
717 RFPGA0_XB_LSSIPARAMETER;
718
719 rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
720 rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
721 rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
722 rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
723
724 rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
725 rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
726 rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
727 rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
728
729 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
730 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
731
732 rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
733 rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
734
735 rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
736 rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
737 rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
738 rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
739
740 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
741 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
742 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
743 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
744
745 rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
746 rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
747 rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
748 rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
749
750 rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
751 rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
752 rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
753 rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
754
755 rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
756 rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
757 rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
758 rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
759
760 rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
761 rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
762 rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
763 rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
764
765 rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
766 rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
767 rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
768 rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
769
770 rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
771 rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
772 rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
773 rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
774
775 rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
776 rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
777}
778
779void rtl8723ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel) 558void rtl8723ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
780{ 559{
781 struct rtl_priv *rtlpriv = rtl_priv(hw); 560 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -785,17 +564,17 @@ void rtl8723ae_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
785 long txpwr_dbm; 564 long txpwr_dbm;
786 565
787 txpwr_level = rtlphy->cur_cck_txpwridx; 566 txpwr_level = rtlphy->cur_cck_txpwridx;
788 txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B, txpwr_level); 567 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B, txpwr_level);
789 txpwr_level = rtlphy->cur_ofdm24g_txpwridx + 568 txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
790 rtlefuse->legacy_ht_txpowerdiff; 569 rtlefuse->legacy_ht_txpowerdiff;
791 if (_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) > txpwr_dbm) 570 if (rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, txpwr_level) > txpwr_dbm)
792 txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G, 571 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
793 txpwr_level); 572 txpwr_level);
794 txpwr_level = rtlphy->cur_ofdm24g_txpwridx; 573 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
795 if (_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, txpwr_level) > 574 if (rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, txpwr_level) >
796 txpwr_dbm) 575 txpwr_dbm)
797 txpwr_dbm = _phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G, 576 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
798 txpwr_level); 577 txpwr_level);
799 *powerlevel = txpwr_dbm; 578 *powerlevel = txpwr_dbm;
800} 579}
801 580
@@ -912,28 +691,6 @@ static u8 _phy_dbm_to_txpwr_Idx(struct ieee80211_hw *hw,
912 return txpwridx; 691 return txpwridx;
913} 692}
914 693
915static long _phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
916 enum wireless_mode wirelessmode, u8 txpwridx)
917{
918 long offset;
919 long pwrout_dbm;
920
921 switch (wirelessmode) {
922 case WIRELESS_MODE_B:
923 offset = -7;
924 break;
925 case WIRELESS_MODE_G:
926 case WIRELESS_MODE_N_24G:
927 offset = -8;
928 break;
929 default:
930 offset = -8;
931 break;
932 }
933 pwrout_dbm = txpwridx / 2 + offset;
934 return pwrout_dbm;
935}
936
937void rtl8723ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw) 694void rtl8723ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
938{ 695{
939 struct rtl_priv *rtlpriv = rtl_priv(hw); 696 struct rtl_priv *rtlpriv = rtl_priv(hw);
@@ -1117,26 +874,26 @@ static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
1117 u8 num_total_rfpath = rtlphy->num_total_rfpath; 874 u8 num_total_rfpath = rtlphy->num_total_rfpath;
1118 875
1119 precommoncmdcnt = 0; 876 precommoncmdcnt = 0;
1120 _phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 877 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1121 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 878 MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL,
1122 0, 0, 0); 879 0, 0, 0);
1123 _phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, 880 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
1124 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0); 881 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
1125 postcommoncmdcnt = 0; 882 postcommoncmdcnt = 0;
1126 883
1127 _phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, 884 rtl8723_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
1128 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0); 885 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
1129 rfdependcmdcnt = 0; 886 rfdependcmdcnt = 0;
1130 887
1131 RT_ASSERT((channel >= 1 && channel <= 14), 888 RT_ASSERT((channel >= 1 && channel <= 14),
1132 "illegal channel for Zebra: %d\n", channel); 889 "illegal channel for Zebra: %d\n", channel);
1133 890
1134 _phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 891 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1135 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, 892 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
1136 RF_CHNLBW, channel, 10); 893 RF_CHNLBW, channel, 10);
1137 894
1138 _phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, 895 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
1139 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0); 896 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
1140 897
1141 do { 898 do {
1142 switch (*stage) { 899 switch (*stage) {
@@ -1204,29 +961,6 @@ static bool _phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel,
1204 return false; 961 return false;
1205} 962}
1206 963
1207static bool _phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
1208 u32 cmdtableidx, u32 cmdtablesz,
1209 enum swchnlcmd_id cmdid, u32 para1,
1210 u32 para2, u32 msdelay)
1211{
1212 struct swchnlcmd *pcmd;
1213
1214 if (cmdtable == NULL) {
1215 RT_ASSERT(false, "cmdtable cannot be NULL.\n");
1216 return false;
1217 }
1218
1219 if (cmdtableidx >= cmdtablesz)
1220 return false;
1221
1222 pcmd = cmdtable + cmdtableidx;
1223 pcmd->cmdid = cmdid;
1224 pcmd->para1 = para1;
1225 pcmd->para2 = para2;
1226 pcmd->msdelay = msdelay;
1227 return true;
1228}
1229
1230static u8 _rtl8723ae_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb) 964static u8 _rtl8723ae_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1231{ 965{
1232 u32 reg_eac, reg_e94, reg_e9c, reg_ea4; 966 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
@@ -1297,136 +1031,6 @@ static u8 _rtl8723ae_phy_path_b_iqk(struct ieee80211_hw *hw)
1297 return result; 1031 return result;
1298} 1032}
1299 1033
1300static void phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw, bool iqk_ok,
1301 long result[][8], u8 final_candidate,
1302 bool btxonly)
1303{
1304 u32 oldval_0, x, tx0_a, reg;
1305 long y, tx0_c;
1306
1307 if (final_candidate == 0xFF) {
1308 return;
1309 } else if (iqk_ok) {
1310 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1311 MASKDWORD) >> 22) & 0x3FF;
1312 x = result[final_candidate][0];
1313 if ((x & 0x00000200) != 0)
1314 x = x | 0xFFFFFC00;
1315 tx0_a = (x * oldval_0) >> 8;
1316 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1317 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1318 ((x * oldval_0 >> 7) & 0x1));
1319 y = result[final_candidate][1];
1320 if ((y & 0x00000200) != 0)
1321 y = y | 0xFFFFFC00;
1322 tx0_c = (y * oldval_0) >> 8;
1323 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1324 ((tx0_c & 0x3C0) >> 6));
1325 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1326 (tx0_c & 0x3F));
1327 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1328 ((y * oldval_0 >> 7) & 0x1));
1329 if (btxonly)
1330 return;
1331 reg = result[final_candidate][2];
1332 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1333 reg = result[final_candidate][3] & 0x3F;
1334 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1335 reg = (result[final_candidate][3] >> 6) & 0xF;
1336 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1337 }
1338}
1339
1340static void phy_save_adda_regs(struct ieee80211_hw *hw,
1341 u32 *addareg, u32 *addabackup,
1342 u32 registernum)
1343{
1344 u32 i;
1345
1346 for (i = 0; i < registernum; i++)
1347 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1348}
1349
1350static void phy_save_mac_regs(struct ieee80211_hw *hw, u32 *macreg,
1351 u32 *macbackup)
1352{
1353 struct rtl_priv *rtlpriv = rtl_priv(hw);
1354 u32 i;
1355
1356 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1357 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1358 macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1359}
1360
1361static void phy_reload_adda_regs(struct ieee80211_hw *hw, u32 *addareg,
1362 u32 *addabackup, u32 regiesternum)
1363{
1364 u32 i;
1365
1366 for (i = 0; i < regiesternum; i++)
1367 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1368}
1369
1370static void phy_reload_mac_regs(struct ieee80211_hw *hw, u32 *macreg,
1371 u32 *macbackup)
1372{
1373 struct rtl_priv *rtlpriv = rtl_priv(hw);
1374 u32 i;
1375
1376 for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1377 rtl_write_byte(rtlpriv, macreg[i], (u8) macbackup[i]);
1378 rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1379}
1380
1381static void _rtl8723ae_phy_path_adda_on(struct ieee80211_hw *hw,
1382 u32 *addareg, bool is_patha_on,
1383 bool is2t)
1384{
1385 u32 pathOn;
1386 u32 i;
1387
1388 pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1389 if (false == is2t) {
1390 pathOn = 0x0bdb25a0;
1391 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1392 } else {
1393 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1394 }
1395
1396 for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1397 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1398}
1399
1400static void _rtl8723ae_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1401 u32 *macreg, u32 *macbackup)
1402{
1403 struct rtl_priv *rtlpriv = rtl_priv(hw);
1404 u32 i = 0;
1405
1406 rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1407
1408 for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1409 rtl_write_byte(rtlpriv, macreg[i],
1410 (u8) (macbackup[i] & (~BIT(3))));
1411 rtl_write_byte(rtlpriv, macreg[i], (u8) (macbackup[i] & (~BIT(5))));
1412}
1413
1414static void _rtl8723ae_phy_path_a_standby(struct ieee80211_hw *hw)
1415{
1416 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1417 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1418 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1419}
1420
1421static void _rtl8723ae_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1422{
1423 u32 mode;
1424
1425 mode = pi_mode ? 0x01000100 : 0x01000000;
1426 rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1427 rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1428}
1429
1430static bool phy_simularity_comp(struct ieee80211_hw *hw, long result[][8], 1034static bool phy_simularity_comp(struct ieee80211_hw *hw, long result[][8],
1431 u8 c1, u8 c2) 1035 u8 c1, u8 c2)
1432{ 1036{
@@ -1498,10 +1102,12 @@ static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1498 const u32 retrycount = 2; 1102 const u32 retrycount = 2;
1499 1103
1500 if (t == 0) { 1104 if (t == 0) {
1501 phy_save_adda_regs(hw, adda_reg, rtlphy->adda_backup, 16); 1105 rtl8723_save_adda_registers(hw, adda_reg, rtlphy->adda_backup,
1502 phy_save_mac_regs(hw, iqk_mac_reg, rtlphy->iqk_mac_backup); 1106 16);
1107 rtl8723_phy_save_mac_registers(hw, iqk_mac_reg,
1108 rtlphy->iqk_mac_backup);
1503 } 1109 }
1504 _rtl8723ae_phy_path_adda_on(hw, adda_reg, true, is2t); 1110 rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t);
1505 if (t == 0) { 1111 if (t == 0) {
1506 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw, 1112 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1507 RFPGA0_XA_HSSIPARAMETER1, 1113 RFPGA0_XA_HSSIPARAMETER1,
@@ -1509,7 +1115,7 @@ static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1509 } 1115 }
1510 1116
1511 if (!rtlphy->rfpi_enable) 1117 if (!rtlphy->rfpi_enable)
1512 _rtl8723ae_phy_pi_mode_switch(hw, true); 1118 rtl8723_phy_pi_mode_switch(hw, true);
1513 if (t == 0) { 1119 if (t == 0) {
1514 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD); 1120 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1515 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD); 1121 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
@@ -1522,7 +1128,7 @@ static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1522 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000); 1128 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1523 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000); 1129 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1524 } 1130 }
1525 _rtl8723ae_phy_mac_setting_calibration(hw, iqk_mac_reg, 1131 rtl8723_phy_mac_setting_calibration(hw, iqk_mac_reg,
1526 rtlphy->iqk_mac_backup); 1132 rtlphy->iqk_mac_backup);
1527 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000); 1133 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1528 if (is2t) 1134 if (is2t)
@@ -1552,8 +1158,8 @@ static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1552 } 1158 }
1553 1159
1554 if (is2t) { 1160 if (is2t) {
1555 _rtl8723ae_phy_path_a_standby(hw); 1161 rtl8723_phy_path_a_standby(hw);
1556 _rtl8723ae_phy_path_adda_on(hw, adda_reg, false, is2t); 1162 rtl8723_phy_path_adda_on(hw, adda_reg, false, is2t);
1557 for (i = 0; i < retrycount; i++) { 1163 for (i = 0; i < retrycount; i++) {
1558 pathb_ok = _rtl8723ae_phy_path_b_iqk(hw); 1164 pathb_ok = _rtl8723ae_phy_path_b_iqk(hw);
1559 if (pathb_ok == 0x03) { 1165 if (pathb_ok == 0x03) {
@@ -1588,9 +1194,11 @@ static void _rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw,
1588 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3); 1194 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1589 if (t != 0) { 1195 if (t != 0) {
1590 if (!rtlphy->rfpi_enable) 1196 if (!rtlphy->rfpi_enable)
1591 _rtl8723ae_phy_pi_mode_switch(hw, false); 1197 rtl8723_phy_pi_mode_switch(hw, false);
1592 phy_reload_adda_regs(hw, adda_reg, rtlphy->adda_backup, 16); 1198 rtl8723_phy_reload_adda_registers(hw, adda_reg,
1593 phy_reload_mac_regs(hw, iqk_mac_reg, rtlphy->iqk_mac_backup); 1199 rtlphy->adda_backup, 16);
1200 rtl8723_phy_reload_mac_registers(hw, iqk_mac_reg,
1201 rtlphy->iqk_mac_backup);
1594 } 1202 }
1595} 1203}
1596 1204
@@ -1691,7 +1299,8 @@ void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1691 }; 1299 };
1692 1300
1693 if (recovery) { 1301 if (recovery) {
1694 phy_reload_adda_regs(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 10); 1302 rtl8723_phy_reload_adda_registers(hw, iqk_bb_reg,
1303 rtlphy->iqk_bb_backup, 10);
1695 return; 1304 return;
1696 } 1305 }
1697 if (start_conttx || singletone) 1306 if (start_conttx || singletone)
@@ -1756,9 +1365,10 @@ void rtl8723ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery)
1756 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0; 1365 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1757 } 1366 }
1758 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */ 1367 if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1759 phy_path_a_fill_iqk_matrix(hw, patha_ok, result, 1368 rtl8723_phy_path_a_fill_iqk_matrix(hw, patha_ok, result,
1760 final_candidate, (reg_ea4 == 0)); 1369 final_candidate,
1761 phy_save_adda_regs(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 10); 1370 (reg_ea4 == 0));
1371 rtl8723_save_adda_registers(hw, iqk_bb_reg, rtlphy->iqk_bb_backup, 10);
1762} 1372}
1763 1373
1764void rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw) 1374void rtl8723ae_phy_lc_calibrate(struct ieee80211_hw *hw)
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-13 22:20:34 -0400