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authorMike McCormack <mikem@ring3k.org>2011-06-19 21:47:51 -0400
committerJohn W. Linville <linville@tuxdriver.com>2011-06-20 15:47:43 -0400
commite10542c447abf7c840931ff12f7d0dee976ca2ea (patch)
treeae254d633339b2617e4062fe070d2f4bc274cfb2 /drivers/net/wireless/rtlwifi/rtl8192se/phy.c
parent4b9d8d67b44aae18e1c4b71281f5cfc0f2105cf6 (diff)
rtlwifi: rtl8192{c,ce,cu,se}: Remove comparisons of booleans with true
These are a potential source of confusion, as most C code treats all non-zero values as true. Signed-off-by: Mike McCormack <mikem@ring3k.org> Acked-by: Larry Finger <Larry.Finger@lwfinger.net> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rtlwifi/rtl8192se/phy.c')
-rw-r--r--drivers/net/wireless/rtlwifi/rtl8192se/phy.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/net/wireless/rtlwifi/rtl8192se/phy.c b/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
index 7ee2daccd7d5..81a5aa4370cf 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192se/phy.c
@@ -1416,7 +1416,7 @@ static void _rtl92s_phy_set_fwcmd_io(struct ieee80211_hw *hw)
1416 break; 1416 break;
1417 case FW_CMD_HIGH_PWR_ENABLE: 1417 case FW_CMD_HIGH_PWR_ENABLE:
1418 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1418 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1419 (rtlpriv->dm.dynamic_txpower_enable == true)) 1419 rtlpriv->dm.dynamic_txpower_enable)
1420 break; 1420 break;
1421 1421
1422 /* CCA threshold */ 1422 /* CCA threshold */
@@ -1608,7 +1608,7 @@ bool rtl92s_phy_set_fw_cmd(struct ieee80211_hw *hw, enum fwcmd_iotype fw_cmdio)
1608 fw_cmdmap &= ~FW_DIG_ENABLE_CTL; 1608 fw_cmdmap &= ~FW_DIG_ENABLE_CTL;
1609 1609
1610 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) || 1610 if ((rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) ||
1611 (rtlpriv->dm.dynamic_txpower_enable == true)) 1611 rtlpriv->dm.dynamic_txpower_enable)
1612 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL; 1612 fw_cmdmap &= ~FW_HIGH_PWR_ENABLE_CTL;
1613 1613
1614 if ((digtable.dig_ext_port_stage == 1614 if ((digtable.dig_ext_port_stage ==