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authorLinus Torvalds <torvalds@linux-foundation.org>2010-05-21 00:04:44 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-05-21 00:04:44 -0400
commitf8965467f366fd18f01feafb5db10512d7b4422c (patch)
tree3706a9cd779859271ca61b85c63a1bc3f82d626e /drivers/net/wireless/rt2x00
parenta26272e5200765691e67d6780e52b32498fdb659 (diff)
parent2ec8c6bb5d8f3a62a79f463525054bae1e3d4487 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1674 commits) qlcnic: adding co maintainer ixgbe: add support for active DA cables ixgbe: dcb, do not tag tc_prio_control frames ixgbe: fix ixgbe_tx_is_paused logic ixgbe: always enable vlan strip/insert when DCB is enabled ixgbe: remove some redundant code in setting FCoE FIP filter ixgbe: fix wrong offset to fc_frame_header in ixgbe_fcoe_ddp ixgbe: fix header len when unsplit packet overflows to data buffer ipv6: Never schedule DAD timer on dead address ipv6: Use POSTDAD state ipv6: Use state_lock to protect ifa state ipv6: Replace inet6_ifaddr->dead with state cxgb4: notify upper drivers if the device is already up when they load cxgb4: keep interrupts available when the ports are brought down cxgb4: fix initial addition of MAC address cnic: Return SPQ credit to bnx2x after ring setup and shutdown. cnic: Convert cnic_local_flags to atomic ops. can: Fix SJA1000 command register writes on SMP systems bridge: fix build for CONFIG_SYSFS disabled ARCNET: Limit com20020 PCI ID matches for SOHARD cards ... Fix up various conflicts with pcmcia tree drivers/net/ {pcmcia/3c589_cs.c, wireless/orinoco/orinoco_cs.c and wireless/orinoco/spectrum_cs.c} and feature removal (Documentation/feature-removal-schedule.txt). Also fix a non-content conflict due to pm_qos_requirement getting renamed in the PM tree (now pm_qos_request) in net/mac80211/scan.c
Diffstat (limited to 'drivers/net/wireless/rt2x00')
-rw-r--r--drivers/net/wireless/rt2x00/Kconfig4
-rw-r--r--drivers/net/wireless/rt2x00/rt2400pci.c56
-rw-r--r--drivers/net/wireless/rt2x00/rt2500pci.c54
-rw-r--r--drivers/net/wireless/rt2x00/rt2500usb.c130
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h119
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c676
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.h3
-rw-r--r--drivers/net/wireless/rt2x00/rt2800pci.c318
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.c297
-rw-r--r--drivers/net/wireless/rt2x00/rt2800usb.h40
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h35
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00crypto.c1
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00debug.c23
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00dev.c1
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00dump.h3
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00firmware.c2
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00ht.c17
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.c12
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00pci.h3
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.c47
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00queue.h11
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00reg.h10
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.c11
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00usb.h3
-rw-r--r--drivers/net/wireless/rt2x00/rt61pci.c95
-rw-r--r--drivers/net/wireless/rt2x00/rt73usb.c128
26 files changed, 1243 insertions, 856 deletions
diff --git a/drivers/net/wireless/rt2x00/Kconfig b/drivers/net/wireless/rt2x00/Kconfig
index 5239e082cd0f..eea1ef2f502b 100644
--- a/drivers/net/wireless/rt2x00/Kconfig
+++ b/drivers/net/wireless/rt2x00/Kconfig
@@ -87,7 +87,7 @@ if RT2800PCI
87 87
88config RT2800PCI_RT30XX 88config RT2800PCI_RT30XX
89 bool "rt2800pci - Include support for rt30xx (PCI/PCIe/PCMCIA) devices" 89 bool "rt2800pci - Include support for rt30xx (PCI/PCIe/PCMCIA) devices"
90 default n 90 default y
91 ---help--- 91 ---help---
92 This adds support for rt30xx wireless chipset family to the 92 This adds support for rt30xx wireless chipset family to the
93 rt2800pci driver. 93 rt2800pci driver.
@@ -156,7 +156,7 @@ if RT2800USB
156 156
157config RT2800USB_RT30XX 157config RT2800USB_RT30XX
158 bool "rt2800usb - Include support for rt30xx (USB) devices" 158 bool "rt2800usb - Include support for rt30xx (USB) devices"
159 default n 159 default y
160 ---help--- 160 ---help---
161 This adds support for rt30xx wireless chipset family to the 161 This adds support for rt30xx wireless chipset family to the
162 rt2800usb driver. 162 rt2800usb driver.
diff --git a/drivers/net/wireless/rt2x00/rt2400pci.c b/drivers/net/wireless/rt2x00/rt2400pci.c
index 5f5204b82891..4ba7b038928f 100644
--- a/drivers/net/wireless/rt2x00/rt2400pci.c
+++ b/drivers/net/wireless/rt2x00/rt2400pci.c
@@ -526,6 +526,10 @@ static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
526 526
527 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1); 527 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
528 rt2x00pci_register_write(rt2x00dev, CSR20, reg); 528 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
529 } else {
530 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
531 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
532 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
529 } 533 }
530 534
531 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 535 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
@@ -1003,19 +1007,19 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1003{ 1007{
1004 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1008 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1005 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; 1009 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1006 __le32 *txd = skbdesc->desc; 1010 __le32 *txd = entry_priv->desc;
1007 u32 word; 1011 u32 word;
1008 1012
1009 /* 1013 /*
1010 * Start writing the descriptor words. 1014 * Start writing the descriptor words.
1011 */ 1015 */
1012 rt2x00_desc_read(entry_priv->desc, 1, &word); 1016 rt2x00_desc_read(txd, 1, &word);
1013 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); 1017 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1014 rt2x00_desc_write(entry_priv->desc, 1, word); 1018 rt2x00_desc_write(txd, 1, word);
1015 1019
1016 rt2x00_desc_read(txd, 2, &word); 1020 rt2x00_desc_read(txd, 2, &word);
1017 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skb->len); 1021 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
1018 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skb->len); 1022 rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1019 rt2x00_desc_write(txd, 2, word); 1023 rt2x00_desc_write(txd, 2, word);
1020 1024
1021 rt2x00_desc_read(txd, 3, &word); 1025 rt2x00_desc_read(txd, 3, &word);
@@ -1036,6 +1040,11 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1036 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1); 1040 rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1037 rt2x00_desc_write(txd, 4, word); 1041 rt2x00_desc_write(txd, 4, word);
1038 1042
1043 /*
1044 * Writing TXD word 0 must the last to prevent a race condition with
1045 * the device, whereby the device may take hold of the TXD before we
1046 * finished updating it.
1047 */
1039 rt2x00_desc_read(txd, 0, &word); 1048 rt2x00_desc_read(txd, 0, &word);
1040 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); 1049 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1041 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1050 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
@@ -1051,12 +1060,19 @@ static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1051 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1060 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1052 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1061 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1053 rt2x00_desc_write(txd, 0, word); 1062 rt2x00_desc_write(txd, 0, word);
1063
1064 /*
1065 * Register descriptor details in skb frame descriptor.
1066 */
1067 skbdesc->desc = txd;
1068 skbdesc->desc_len = TXD_DESC_SIZE;
1054} 1069}
1055 1070
1056/* 1071/*
1057 * TX data initialization 1072 * TX data initialization
1058 */ 1073 */
1059static void rt2400pci_write_beacon(struct queue_entry *entry) 1074static void rt2400pci_write_beacon(struct queue_entry *entry,
1075 struct txentry_desc *txdesc)
1060{ 1076{
1061 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1077 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1062 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1078 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
@@ -1072,20 +1088,19 @@ static void rt2400pci_write_beacon(struct queue_entry *entry)
1072 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 1088 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1073 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1089 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1074 1090
1075 /*
1076 * Replace rt2x00lib allocated descriptor with the
1077 * pointer to the _real_ hardware descriptor.
1078 * After that, map the beacon to DMA and update the
1079 * descriptor.
1080 */
1081 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1082 skbdesc->desc = entry_priv->desc;
1083
1084 rt2x00queue_map_txskb(rt2x00dev, entry->skb); 1091 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1085 1092
1086 rt2x00_desc_read(entry_priv->desc, 1, &word); 1093 rt2x00_desc_read(entry_priv->desc, 1, &word);
1087 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); 1094 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1088 rt2x00_desc_write(entry_priv->desc, 1, word); 1095 rt2x00_desc_write(entry_priv->desc, 1, word);
1096
1097 /*
1098 * Enable beaconing again.
1099 */
1100 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1101 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1102 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1103 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1089} 1104}
1090 1105
1091static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1106static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
@@ -1093,17 +1108,6 @@ static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1093{ 1108{
1094 u32 reg; 1109 u32 reg;
1095 1110
1096 if (queue == QID_BEACON) {
1097 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1098 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1099 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1100 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1101 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1102 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1103 }
1104 return;
1105 }
1106
1107 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 1111 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1108 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE)); 1112 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1109 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK)); 1113 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
diff --git a/drivers/net/wireless/rt2x00/rt2500pci.c b/drivers/net/wireless/rt2x00/rt2500pci.c
index 2a73f593aab0..89d132d4af12 100644
--- a/drivers/net/wireless/rt2x00/rt2500pci.c
+++ b/drivers/net/wireless/rt2x00/rt2500pci.c
@@ -574,6 +574,10 @@ static void rt2500pci_config_ps(struct rt2x00_dev *rt2x00dev,
574 574
575 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1); 575 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
576 rt2x00pci_register_write(rt2x00dev, CSR20, reg); 576 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
577 } else {
578 rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
579 rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
580 rt2x00pci_register_write(rt2x00dev, CSR20, reg);
577 } 581 }
578 582
579 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 583 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
@@ -1161,15 +1165,15 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1161{ 1165{
1162 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1166 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1163 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data; 1167 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1164 __le32 *txd = skbdesc->desc; 1168 __le32 *txd = entry_priv->desc;
1165 u32 word; 1169 u32 word;
1166 1170
1167 /* 1171 /*
1168 * Start writing the descriptor words. 1172 * Start writing the descriptor words.
1169 */ 1173 */
1170 rt2x00_desc_read(entry_priv->desc, 1, &word); 1174 rt2x00_desc_read(txd, 1, &word);
1171 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); 1175 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1172 rt2x00_desc_write(entry_priv->desc, 1, word); 1176 rt2x00_desc_write(txd, 1, word);
1173 1177
1174 rt2x00_desc_read(txd, 2, &word); 1178 rt2x00_desc_read(txd, 2, &word);
1175 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER); 1179 rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
@@ -1190,6 +1194,11 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1190 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags)); 1194 test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1191 rt2x00_desc_write(txd, 10, word); 1195 rt2x00_desc_write(txd, 10, word);
1192 1196
1197 /*
1198 * Writing TXD word 0 must the last to prevent a race condition with
1199 * the device, whereby the device may take hold of the TXD before we
1200 * finished updating it.
1201 */
1193 rt2x00_desc_read(txd, 0, &word); 1202 rt2x00_desc_read(txd, 0, &word);
1194 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); 1203 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1195 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1204 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
@@ -1205,15 +1214,22 @@ static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1205 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs); 1214 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1206 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE, 1215 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1207 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags)); 1216 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1208 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len); 1217 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1209 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE); 1218 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1210 rt2x00_desc_write(txd, 0, word); 1219 rt2x00_desc_write(txd, 0, word);
1220
1221 /*
1222 * Register descriptor details in skb frame descriptor.
1223 */
1224 skbdesc->desc = txd;
1225 skbdesc->desc_len = TXD_DESC_SIZE;
1211} 1226}
1212 1227
1213/* 1228/*
1214 * TX data initialization 1229 * TX data initialization
1215 */ 1230 */
1216static void rt2500pci_write_beacon(struct queue_entry *entry) 1231static void rt2500pci_write_beacon(struct queue_entry *entry,
1232 struct txentry_desc *txdesc)
1217{ 1233{
1218 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1234 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1219 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 1235 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
@@ -1229,20 +1245,19 @@ static void rt2500pci_write_beacon(struct queue_entry *entry)
1229 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0); 1245 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1230 rt2x00pci_register_write(rt2x00dev, CSR14, reg); 1246 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1231 1247
1232 /*
1233 * Replace rt2x00lib allocated descriptor with the
1234 * pointer to the _real_ hardware descriptor.
1235 * After that, map the beacon to DMA and update the
1236 * descriptor.
1237 */
1238 memcpy(entry_priv->desc, skbdesc->desc, skbdesc->desc_len);
1239 skbdesc->desc = entry_priv->desc;
1240
1241 rt2x00queue_map_txskb(rt2x00dev, entry->skb); 1248 rt2x00queue_map_txskb(rt2x00dev, entry->skb);
1242 1249
1243 rt2x00_desc_read(entry_priv->desc, 1, &word); 1250 rt2x00_desc_read(entry_priv->desc, 1, &word);
1244 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma); 1251 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1245 rt2x00_desc_write(entry_priv->desc, 1, word); 1252 rt2x00_desc_write(entry_priv->desc, 1, word);
1253
1254 /*
1255 * Enable beaconing again.
1256 */
1257 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1258 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1259 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1260 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1246} 1261}
1247 1262
1248static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev, 1263static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
@@ -1250,17 +1265,6 @@ static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1250{ 1265{
1251 u32 reg; 1266 u32 reg;
1252 1267
1253 if (queue == QID_BEACON) {
1254 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1255 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1256 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1257 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1258 rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1259 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1260 }
1261 return;
1262 }
1263
1264 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg); 1268 rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1265 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE)); 1269 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1266 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK)); 1270 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
diff --git a/drivers/net/wireless/rt2x00/rt2500usb.c b/drivers/net/wireless/rt2x00/rt2500usb.c
index 8ebb705fe106..9ae96a626e6d 100644
--- a/drivers/net/wireless/rt2x00/rt2500usb.c
+++ b/drivers/net/wireless/rt2x00/rt2500usb.c
@@ -649,6 +649,10 @@ static void rt2500usb_config_ps(struct rt2x00_dev *rt2x00dev,
649 649
650 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 1); 650 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 1);
651 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg); 651 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
652 } else {
653 rt2500usb_register_read(rt2x00dev, MAC_CSR18, &reg);
654 rt2x00_set_field16(&reg, MAC_CSR18_AUTO_WAKE, 0);
655 rt2500usb_register_write(rt2x00dev, MAC_CSR18, reg);
652 } 656 }
653 657
654 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 658 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
@@ -1030,12 +1034,30 @@ static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1030 struct txentry_desc *txdesc) 1034 struct txentry_desc *txdesc)
1031{ 1035{
1032 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1036 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1033 __le32 *txd = skbdesc->desc; 1037 __le32 *txd = (__le32 *)(skb->data - TXD_DESC_SIZE);
1034 u32 word; 1038 u32 word;
1035 1039
1036 /* 1040 /*
1037 * Start writing the descriptor words. 1041 * Start writing the descriptor words.
1038 */ 1042 */
1043 rt2x00_desc_read(txd, 0, &word);
1044 rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit);
1045 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1046 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1047 rt2x00_set_field32(&word, TXD_W0_ACK,
1048 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1049 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1050 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1051 rt2x00_set_field32(&word, TXD_W0_OFDM,
1052 (txdesc->rate_mode == RATE_MODE_OFDM));
1053 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
1054 test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
1055 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1056 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1057 rt2x00_set_field32(&word, TXD_W0_CIPHER, !!txdesc->cipher);
1058 rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx);
1059 rt2x00_desc_write(txd, 0, word);
1060
1039 rt2x00_desc_read(txd, 1, &word); 1061 rt2x00_desc_read(txd, 1, &word);
1040 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset); 1062 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, txdesc->iv_offset);
1041 rt2x00_set_field32(&word, TXD_W1_AIFS, txdesc->aifs); 1063 rt2x00_set_field32(&word, TXD_W1_AIFS, txdesc->aifs);
@@ -1055,23 +1077,11 @@ static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1055 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]); 1077 _rt2x00_desc_write(txd, 4, skbdesc->iv[1]);
1056 } 1078 }
1057 1079
1058 rt2x00_desc_read(txd, 0, &word); 1080 /*
1059 rt2x00_set_field32(&word, TXD_W0_RETRY_LIMIT, txdesc->retry_limit); 1081 * Register descriptor details in skb frame descriptor.
1060 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, 1082 */
1061 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 1083 skbdesc->desc = txd;
1062 rt2x00_set_field32(&word, TXD_W0_ACK, 1084 skbdesc->desc_len = TXD_DESC_SIZE;
1063 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1064 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1065 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1066 rt2x00_set_field32(&word, TXD_W0_OFDM,
1067 (txdesc->rate_mode == RATE_MODE_OFDM));
1068 rt2x00_set_field32(&word, TXD_W0_NEW_SEQ,
1069 test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags));
1070 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1071 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1072 rt2x00_set_field32(&word, TXD_W0_CIPHER, !!txdesc->cipher);
1073 rt2x00_set_field32(&word, TXD_W0_KEY_ID, txdesc->key_idx);
1074 rt2x00_desc_write(txd, 0, word);
1075} 1085}
1076 1086
1077/* 1087/*
@@ -1079,22 +1089,15 @@ static void rt2500usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1079 */ 1089 */
1080static void rt2500usb_beacondone(struct urb *urb); 1090static void rt2500usb_beacondone(struct urb *urb);
1081 1091
1082static void rt2500usb_write_beacon(struct queue_entry *entry) 1092static void rt2500usb_write_beacon(struct queue_entry *entry,
1093 struct txentry_desc *txdesc)
1083{ 1094{
1084 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1095 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1085 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev); 1096 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
1086 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data; 1097 struct queue_entry_priv_usb_bcn *bcn_priv = entry->priv_data;
1087 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1088 int pipe = usb_sndbulkpipe(usb_dev, entry->queue->usb_endpoint); 1098 int pipe = usb_sndbulkpipe(usb_dev, entry->queue->usb_endpoint);
1089 int length; 1099 int length;
1090 u16 reg; 1100 u16 reg, reg0;
1091
1092 /*
1093 * Add the descriptor in front of the skb.
1094 */
1095 skb_push(entry->skb, entry->queue->desc_size);
1096 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1097 skbdesc->desc = entry->skb->data;
1098 1101
1099 /* 1102 /*
1100 * Disable beaconing while we are reloading the beacon data, 1103 * Disable beaconing while we are reloading the beacon data,
@@ -1105,6 +1108,11 @@ static void rt2500usb_write_beacon(struct queue_entry *entry)
1105 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg); 1108 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1106 1109
1107 /* 1110 /*
1111 * Take the descriptor in front of the skb into account.
1112 */
1113 skb_push(entry->skb, TXD_DESC_SIZE);
1114
1115 /*
1108 * USB devices cannot blindly pass the skb->len as the 1116 * USB devices cannot blindly pass the skb->len as the
1109 * length of the data to usb_fill_bulk_urb. Pass the skb 1117 * length of the data to usb_fill_bulk_urb. Pass the skb
1110 * to the driver to determine what the length should be. 1118 * to the driver to determine what the length should be.
@@ -1129,6 +1137,26 @@ static void rt2500usb_write_beacon(struct queue_entry *entry)
1129 * Send out the guardian byte. 1137 * Send out the guardian byte.
1130 */ 1138 */
1131 usb_submit_urb(bcn_priv->guardian_urb, GFP_ATOMIC); 1139 usb_submit_urb(bcn_priv->guardian_urb, GFP_ATOMIC);
1140
1141 /*
1142 * Enable beaconing again.
1143 */
1144 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
1145 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
1146 reg0 = reg;
1147 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
1148 /*
1149 * Beacon generation will fail initially.
1150 * To prevent this we need to change the TXRX_CSR19
1151 * register several times (reg0 is the same as reg
1152 * except for TXRX_CSR19_BEACON_GEN, which is 0 in reg0
1153 * and 1 in reg).
1154 */
1155 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1156 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
1157 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1158 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
1159 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1132} 1160}
1133 1161
1134static int rt2500usb_get_tx_data_len(struct queue_entry *entry) 1162static int rt2500usb_get_tx_data_len(struct queue_entry *entry)
@@ -1145,37 +1173,6 @@ static int rt2500usb_get_tx_data_len(struct queue_entry *entry)
1145 return length; 1173 return length;
1146} 1174}
1147 1175
1148static void rt2500usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1149 const enum data_queue_qid queue)
1150{
1151 u16 reg, reg0;
1152
1153 if (queue != QID_BEACON) {
1154 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1155 return;
1156 }
1157
1158 rt2500usb_register_read(rt2x00dev, TXRX_CSR19, &reg);
1159 if (!rt2x00_get_field16(reg, TXRX_CSR19_BEACON_GEN)) {
1160 rt2x00_set_field16(&reg, TXRX_CSR19_TSF_COUNT, 1);
1161 rt2x00_set_field16(&reg, TXRX_CSR19_TBCN, 1);
1162 reg0 = reg;
1163 rt2x00_set_field16(&reg, TXRX_CSR19_BEACON_GEN, 1);
1164 /*
1165 * Beacon generation will fail initially.
1166 * To prevent this we need to change the TXRX_CSR19
1167 * register several times (reg0 is the same as reg
1168 * except for TXRX_CSR19_BEACON_GEN, which is 0 in reg0
1169 * and 1 in reg).
1170 */
1171 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1172 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
1173 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1174 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg0);
1175 rt2500usb_register_write(rt2x00dev, TXRX_CSR19, reg);
1176 }
1177}
1178
1179/* 1176/*
1180 * RX control handlers 1177 * RX control handlers
1181 */ 1178 */
@@ -1210,11 +1207,9 @@ static void rt2500usb_fill_rxdone(struct queue_entry *entry,
1210 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR)) 1207 if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1211 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC; 1208 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1212 1209
1213 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) { 1210 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER);
1214 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER); 1211 if (rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR))
1215 if (rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR)) 1212 rxdesc->cipher_status = RX_CRYPTO_FAIL_KEY;
1216 rxdesc->cipher_status = RX_CRYPTO_FAIL_KEY;
1217 }
1218 1213
1219 if (rxdesc->cipher != CIPHER_NONE) { 1214 if (rxdesc->cipher != CIPHER_NONE) {
1220 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]); 1215 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
@@ -1644,11 +1639,6 @@ static int rt2500usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1644 unsigned int i; 1639 unsigned int i;
1645 1640
1646 /* 1641 /*
1647 * Disable powersaving as default.
1648 */
1649 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
1650
1651 /*
1652 * Initialize all hw fields. 1642 * Initialize all hw fields.
1653 */ 1643 */
1654 rt2x00dev->hw->flags = 1644 rt2x00dev->hw->flags =
@@ -1781,7 +1771,7 @@ static const struct rt2x00lib_ops rt2500usb_rt2x00_ops = {
1781 .write_tx_data = rt2x00usb_write_tx_data, 1771 .write_tx_data = rt2x00usb_write_tx_data,
1782 .write_beacon = rt2500usb_write_beacon, 1772 .write_beacon = rt2500usb_write_beacon,
1783 .get_tx_data_len = rt2500usb_get_tx_data_len, 1773 .get_tx_data_len = rt2500usb_get_tx_data_len,
1784 .kick_tx_queue = rt2500usb_kick_tx_queue, 1774 .kick_tx_queue = rt2x00usb_kick_tx_queue,
1785 .kill_tx_queue = rt2x00usb_kill_tx_queue, 1775 .kill_tx_queue = rt2x00usb_kill_tx_queue,
1786 .fill_rxdone = rt2500usb_fill_rxdone, 1776 .fill_rxdone = rt2500usb_fill_rxdone,
1787 .config_shared_key = rt2500usb_config_key, 1777 .config_shared_key = rt2500usb_config_key,
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index 74c0433dba37..2aa03751c341 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -56,15 +56,20 @@
56#define RF3021 0x0007 56#define RF3021 0x0007
57#define RF3022 0x0008 57#define RF3022 0x0008
58#define RF3052 0x0009 58#define RF3052 0x0009
59#define RF3320 0x000b
59 60
60/* 61/*
61 * Chipset version. 62 * Chipset revisions.
62 */ 63 */
63#define RT2860C_VERSION 0x0100 64#define REV_RT2860C 0x0100
64#define RT2860D_VERSION 0x0101 65#define REV_RT2860D 0x0101
65#define RT2880E_VERSION 0x0200 66#define REV_RT2870D 0x0101
66#define RT2883_VERSION 0x0300 67#define REV_RT2872E 0x0200
67#define RT3070_VERSION 0x0200 68#define REV_RT3070E 0x0200
69#define REV_RT3070F 0x0201
70#define REV_RT3071E 0x0211
71#define REV_RT3090E 0x0211
72#define REV_RT3390E 0x0211
68 73
69/* 74/*
70 * Signal information. 75 * Signal information.
@@ -90,13 +95,19 @@
90#define NUM_TX_QUEUES 4 95#define NUM_TX_QUEUES 4
91 96
92/* 97/*
93 * USB registers. 98 * Registers.
94 */ 99 */
95 100
96/* 101/*
102 * OPT_14: Unknown register used by rt3xxx devices.
103 */
104#define OPT_14_CSR 0x0114
105#define OPT_14_CSR_BIT0 FIELD32(0x00000001)
106
107/*
97 * INT_SOURCE_CSR: Interrupt source register. 108 * INT_SOURCE_CSR: Interrupt source register.
98 * Write one to clear corresponding bit. 109 * Write one to clear corresponding bit.
99 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c 110 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
100 */ 111 */
101#define INT_SOURCE_CSR 0x0200 112#define INT_SOURCE_CSR 0x0200
102#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001) 113#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
@@ -398,6 +409,31 @@
398#define EFUSE_DATA3 0x059c 409#define EFUSE_DATA3 0x059c
399 410
400/* 411/*
412 * LDO_CFG0
413 */
414#define LDO_CFG0 0x05d4
415#define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
416#define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
417#define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
418#define LDO_CFG0_BGSEL FIELD32(0x03000000)
419#define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
420#define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
421#define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
422
423/*
424 * GPIO_SWITCH
425 */
426#define GPIO_SWITCH 0x05dc
427#define GPIO_SWITCH_0 FIELD32(0x00000001)
428#define GPIO_SWITCH_1 FIELD32(0x00000002)
429#define GPIO_SWITCH_2 FIELD32(0x00000004)
430#define GPIO_SWITCH_3 FIELD32(0x00000008)
431#define GPIO_SWITCH_4 FIELD32(0x00000010)
432#define GPIO_SWITCH_5 FIELD32(0x00000020)
433#define GPIO_SWITCH_6 FIELD32(0x00000040)
434#define GPIO_SWITCH_7 FIELD32(0x00000080)
435
436/*
401 * MAC Control/Status Registers(CSR). 437 * MAC Control/Status Registers(CSR).
402 * Some values are set in TU, whereas 1 TU == 1024 us. 438 * Some values are set in TU, whereas 1 TU == 1024 us.
403 */ 439 */
@@ -809,7 +845,7 @@
809 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz 845 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
810 */ 846 */
811#define TX_BAND_CFG 0x132c 847#define TX_BAND_CFG 0x132c
812#define TX_BAND_CFG_HT40_PLUS FIELD32(0x00000001) 848#define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
813#define TX_BAND_CFG_A FIELD32(0x00000002) 849#define TX_BAND_CFG_A FIELD32(0x00000002)
814#define TX_BAND_CFG_BG FIELD32(0x00000004) 850#define TX_BAND_CFG_BG FIELD32(0x00000004)
815 851
@@ -1483,7 +1519,7 @@ struct mac_iveiv_entry {
1483 * BBP 3: RX Antenna 1519 * BBP 3: RX Antenna
1484 */ 1520 */
1485#define BBP3_RX_ANTENNA FIELD8(0x18) 1521#define BBP3_RX_ANTENNA FIELD8(0x18)
1486#define BBP3_HT40_PLUS FIELD8(0x20) 1522#define BBP3_HT40_MINUS FIELD8(0x20)
1487 1523
1488/* 1524/*
1489 * BBP 4: Bandwidth 1525 * BBP 4: Bandwidth
@@ -1492,14 +1528,32 @@ struct mac_iveiv_entry {
1492#define BBP4_BANDWIDTH FIELD8(0x18) 1528#define BBP4_BANDWIDTH FIELD8(0x18)
1493 1529
1494/* 1530/*
1531 * BBP 138: Unknown
1532 */
1533#define BBP138_RX_ADC1 FIELD8(0x02)
1534#define BBP138_RX_ADC2 FIELD8(0x04)
1535#define BBP138_TX_DAC1 FIELD8(0x20)
1536#define BBP138_TX_DAC2 FIELD8(0x40)
1537
1538/*
1495 * RFCSR registers 1539 * RFCSR registers
1496 * The wordsize of the RFCSR is 8 bits. 1540 * The wordsize of the RFCSR is 8 bits.
1497 */ 1541 */
1498 1542
1499/* 1543/*
1544 * RFCSR 1:
1545 */
1546#define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1547#define RFCSR1_RX0_PD FIELD8(0x04)
1548#define RFCSR1_TX0_PD FIELD8(0x08)
1549#define RFCSR1_RX1_PD FIELD8(0x10)
1550#define RFCSR1_TX1_PD FIELD8(0x20)
1551
1552/*
1500 * RFCSR 6: 1553 * RFCSR 6:
1501 */ 1554 */
1502#define RFCSR6_R FIELD8(0x03) 1555#define RFCSR6_R1 FIELD8(0x03)
1556#define RFCSR6_R2 FIELD8(0x40)
1503 1557
1504/* 1558/*
1505 * RFCSR 7: 1559 * RFCSR 7:
@@ -1512,6 +1566,33 @@ struct mac_iveiv_entry {
1512#define RFCSR12_TX_POWER FIELD8(0x1f) 1566#define RFCSR12_TX_POWER FIELD8(0x1f)
1513 1567
1514/* 1568/*
1569 * RFCSR 13:
1570 */
1571#define RFCSR13_TX_POWER FIELD8(0x1f)
1572
1573/*
1574 * RFCSR 15:
1575 */
1576#define RFCSR15_TX_LO2_EN FIELD8(0x08)
1577
1578/*
1579 * RFCSR 17:
1580 */
1581#define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1582#define RFCSR17_TX_LO1_EN FIELD8(0x08)
1583#define RFCSR17_R FIELD8(0x20)
1584
1585/*
1586 * RFCSR 20:
1587 */
1588#define RFCSR20_RX_LO1_EN FIELD8(0x08)
1589
1590/*
1591 * RFCSR 21:
1592 */
1593#define RFCSR21_RX_LO2_EN FIELD8(0x08)
1594
1595/*
1515 * RFCSR 22: 1596 * RFCSR 22:
1516 */ 1597 */
1517#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01) 1598#define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
@@ -1522,6 +1603,14 @@ struct mac_iveiv_entry {
1522#define RFCSR23_FREQ_OFFSET FIELD8(0x7f) 1603#define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1523 1604
1524/* 1605/*
1606 * RFCSR 27:
1607 */
1608#define RFCSR27_R1 FIELD8(0x03)
1609#define RFCSR27_R2 FIELD8(0x04)
1610#define RFCSR27_R3 FIELD8(0x30)
1611#define RFCSR27_R4 FIELD8(0x40)
1612
1613/*
1525 * RFCSR 30: 1614 * RFCSR 30:
1526 */ 1615 */
1527#define RFCSR30_RF_CALIBRATION FIELD8(0x80) 1616#define RFCSR30_RF_CALIBRATION FIELD8(0x80)
@@ -1603,6 +1692,8 @@ struct mac_iveiv_entry {
1603#define EEPROM_NIC_WPS_PBC FIELD16(0x0080) 1692#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1604#define EEPROM_NIC_BW40M_BG FIELD16(0x0100) 1693#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1605#define EEPROM_NIC_BW40M_A FIELD16(0x0200) 1694#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1695#define EEPROM_NIC_ANT_DIVERSITY FIELD16(0x0800)
1696#define EEPROM_NIC_DAC_TEST FIELD16(0x8000)
1606 1697
1607/* 1698/*
1608 * EEPROM frequency 1699 * EEPROM frequency
@@ -1659,6 +1750,12 @@ struct mac_iveiv_entry {
1659#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00) 1750#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1660 1751
1661/* 1752/*
1753 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
1754 */
1755#define EEPROM_TXMIXER_GAIN_BG 0x0024
1756#define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
1757
1758/*
1662 * EEPROM RSSI A offset 1759 * EEPROM RSSI A offset
1663 */ 1760 */
1664#define EEPROM_RSSI_A 0x0025 1761#define EEPROM_RSSI_A 0x0025
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index c015ce9fdd09..db4250d1c8b3 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -41,9 +41,6 @@
41#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE) 41#if defined(CONFIG_RT2X00_LIB_USB) || defined(CONFIG_RT2X00_LIB_USB_MODULE)
42#include "rt2x00usb.h" 42#include "rt2x00usb.h"
43#endif 43#endif
44#if defined(CONFIG_RT2X00_LIB_PCI) || defined(CONFIG_RT2X00_LIB_PCI_MODULE)
45#include "rt2x00pci.h"
46#endif
47#include "rt2800lib.h" 44#include "rt2800lib.h"
48#include "rt2800.h" 45#include "rt2800.h"
49#include "rt2800usb.h" 46#include "rt2800usb.h"
@@ -76,6 +73,23 @@ MODULE_LICENSE("GPL");
76 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \ 73 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
77 H2M_MAILBOX_CSR_OWNER, (__reg)) 74 H2M_MAILBOX_CSR_OWNER, (__reg))
78 75
76static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
77{
78 /* check for rt2872 on SoC */
79 if (!rt2x00_is_soc(rt2x00dev) ||
80 !rt2x00_rt(rt2x00dev, RT2872))
81 return false;
82
83 /* we know for sure that these rf chipsets are used on rt305x boards */
84 if (rt2x00_rf(rt2x00dev, RF3020) ||
85 rt2x00_rf(rt2x00dev, RF3021) ||
86 rt2x00_rf(rt2x00dev, RF3022))
87 return true;
88
89 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
90 return false;
91}
92
79static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev, 93static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
80 const unsigned int word, const u8 value) 94 const unsigned int word, const u8 value)
81{ 95{
@@ -268,6 +282,104 @@ int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
268} 282}
269EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready); 283EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
270 284
285void rt2800_write_txwi(struct sk_buff *skb, struct txentry_desc *txdesc)
286{
287 __le32 *txwi = (__le32 *)(skb->data - TXWI_DESC_SIZE);
288 u32 word;
289
290 /*
291 * Initialize TX Info descriptor
292 */
293 rt2x00_desc_read(txwi, 0, &word);
294 rt2x00_set_field32(&word, TXWI_W0_FRAG,
295 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
296 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
297 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
298 rt2x00_set_field32(&word, TXWI_W0_TS,
299 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
300 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
301 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
302 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
303 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->txop);
304 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
305 rt2x00_set_field32(&word, TXWI_W0_BW,
306 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
307 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
308 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
309 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
310 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
311 rt2x00_desc_write(txwi, 0, word);
312
313 rt2x00_desc_read(txwi, 1, &word);
314 rt2x00_set_field32(&word, TXWI_W1_ACK,
315 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
316 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
317 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
318 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
319 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
320 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
321 txdesc->key_idx : 0xff);
322 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
323 txdesc->length);
324 rt2x00_set_field32(&word, TXWI_W1_PACKETID, txdesc->queue + 1);
325 rt2x00_desc_write(txwi, 1, word);
326
327 /*
328 * Always write 0 to IV/EIV fields, hardware will insert the IV
329 * from the IVEIV register when TXD_W3_WIV is set to 0.
330 * When TXD_W3_WIV is set to 1 it will use the IV data
331 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
332 * crypto entry in the registers should be used to encrypt the frame.
333 */
334 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
335 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
336}
337EXPORT_SYMBOL_GPL(rt2800_write_txwi);
338
339void rt2800_process_rxwi(struct sk_buff *skb, struct rxdone_entry_desc *rxdesc)
340{
341 __le32 *rxwi = (__le32 *) skb->data;
342 u32 word;
343
344 rt2x00_desc_read(rxwi, 0, &word);
345
346 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
347 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
348
349 rt2x00_desc_read(rxwi, 1, &word);
350
351 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
352 rxdesc->flags |= RX_FLAG_SHORT_GI;
353
354 if (rt2x00_get_field32(word, RXWI_W1_BW))
355 rxdesc->flags |= RX_FLAG_40MHZ;
356
357 /*
358 * Detect RX rate, always use MCS as signal type.
359 */
360 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
361 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
362 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
363
364 /*
365 * Mask of 0x8 bit to remove the short preamble flag.
366 */
367 if (rxdesc->rate_mode == RATE_MODE_CCK)
368 rxdesc->signal &= ~0x8;
369
370 rt2x00_desc_read(rxwi, 2, &word);
371
372 rxdesc->rssi =
373 (rt2x00_get_field32(word, RXWI_W2_RSSI0) +
374 rt2x00_get_field32(word, RXWI_W2_RSSI1)) / 2;
375
376 /*
377 * Remove RXWI descriptor from start of buffer.
378 */
379 skb_pull(skb, RXWI_DESC_SIZE);
380}
381EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
382
271#ifdef CONFIG_RT2X00_LIB_DEBUGFS 383#ifdef CONFIG_RT2X00_LIB_DEBUGFS
272const struct rt2x00debug rt2800_rt2x00debug = { 384const struct rt2x00debug rt2800_rt2x00debug = {
273 .owner = THIS_MODULE, 385 .owner = THIS_MODULE,
@@ -360,11 +472,6 @@ static int rt2800_blink_set(struct led_classdev *led_cdev,
360 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg); 472 rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
361 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on); 473 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
362 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off); 474 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
363 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
364 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
365 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
366 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
367 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
368 rt2800_register_write(led->rt2x00dev, LED_CFG, reg); 475 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
369 476
370 return 0; 477 return 0;
@@ -610,10 +717,6 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
610{ 717{
611 u32 reg; 718 u32 reg;
612 719
613 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
614 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
615 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
616
617 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); 720 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
618 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 721 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
619 !!erp->short_preamble); 722 !!erp->short_preamble);
@@ -632,15 +735,10 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp)
632 735
633 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg); 736 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
634 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time); 737 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
635 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
636 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg); 738 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
637 739
638 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg); 740 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
639 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
640 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
641 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
642 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs); 741 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
643 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
644 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg); 742 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
645 743
646 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg); 744 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
@@ -718,10 +816,10 @@ static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
718 rt2x00dev->lna_gain = lna_gain; 816 rt2x00dev->lna_gain = lna_gain;
719} 817}
720 818
721static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev, 819static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
722 struct ieee80211_conf *conf, 820 struct ieee80211_conf *conf,
723 struct rf_channel *rf, 821 struct rf_channel *rf,
724 struct channel_info *info) 822 struct channel_info *info)
725{ 823{
726 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); 824 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
727 825
@@ -787,10 +885,10 @@ static void rt2800_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
787 rt2800_rf_write(rt2x00dev, 4, rf->rf4); 885 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
788} 886}
789 887
790static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev, 888static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
791 struct ieee80211_conf *conf, 889 struct ieee80211_conf *conf,
792 struct rf_channel *rf, 890 struct rf_channel *rf,
793 struct channel_info *info) 891 struct channel_info *info)
794{ 892{
795 u8 rfcsr; 893 u8 rfcsr;
796 894
@@ -798,7 +896,7 @@ static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
798 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); 896 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
799 897
800 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); 898 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
801 rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2); 899 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
802 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); 900 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
803 901
804 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); 902 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
@@ -806,6 +904,11 @@ static void rt2800_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
806 TXPOWER_G_TO_DEV(info->tx_power1)); 904 TXPOWER_G_TO_DEV(info->tx_power1));
807 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); 905 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
808 906
907 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
908 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
909 TXPOWER_G_TO_DEV(info->tx_power2));
910 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
911
809 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); 912 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
810 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); 913 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
811 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); 914 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
@@ -827,15 +930,13 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
827 unsigned int tx_pin; 930 unsigned int tx_pin;
828 u8 bbp; 931 u8 bbp;
829 932
830 if ((rt2x00_rt(rt2x00dev, RT3070) || 933 if (rt2x00_rf(rt2x00dev, RF2020) ||
831 rt2x00_rt(rt2x00dev, RT3090)) && 934 rt2x00_rf(rt2x00dev, RF3020) ||
832 (rt2x00_rf(rt2x00dev, RF2020) || 935 rt2x00_rf(rt2x00dev, RF3021) ||
833 rt2x00_rf(rt2x00dev, RF3020) || 936 rt2x00_rf(rt2x00dev, RF3022))
834 rt2x00_rf(rt2x00dev, RF3021) || 937 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
835 rt2x00_rf(rt2x00dev, RF3022)))
836 rt2800_config_channel_rt3x(rt2x00dev, conf, rf, info);
837 else 938 else
838 rt2800_config_channel_rt2x(rt2x00dev, conf, rf, info); 939 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
839 940
840 /* 941 /*
841 * Change BBP settings 942 * Change BBP settings
@@ -863,7 +964,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
863 } 964 }
864 965
865 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg); 966 rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
866 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf)); 967 rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
867 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14); 968 rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
868 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14); 969 rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
869 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); 970 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
@@ -896,11 +997,10 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
896 rt2800_bbp_write(rt2x00dev, 4, bbp); 997 rt2800_bbp_write(rt2x00dev, 4, bbp);
897 998
898 rt2800_bbp_read(rt2x00dev, 3, &bbp); 999 rt2800_bbp_read(rt2x00dev, 3, &bbp);
899 rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf)); 1000 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
900 rt2800_bbp_write(rt2x00dev, 3, bbp); 1001 rt2800_bbp_write(rt2x00dev, 3, bbp);
901 1002
902 if (rt2x00_rt(rt2x00dev, RT2860) && 1003 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
903 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) {
904 if (conf_is_ht40(conf)) { 1004 if (conf_is_ht40(conf)) {
905 rt2800_bbp_write(rt2x00dev, 69, 0x1a); 1005 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
906 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 1006 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
@@ -988,10 +1088,6 @@ static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
988 libconf->conf->short_frame_max_tx_count); 1088 libconf->conf->short_frame_max_tx_count);
989 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 1089 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
990 libconf->conf->long_frame_max_tx_count); 1090 libconf->conf->long_frame_max_tx_count);
991 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
992 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
993 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
994 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
995 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg); 1091 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
996} 1092}
997 1093
@@ -1015,13 +1111,13 @@ static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
1015 1111
1016 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state); 1112 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1017 } else { 1113 } else {
1018 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1019
1020 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg); 1114 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1021 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0); 1115 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1022 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0); 1116 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1023 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0); 1117 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1024 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg); 1118 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1119
1120 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1025 } 1121 }
1026} 1122}
1027 1123
@@ -1062,9 +1158,10 @@ EXPORT_SYMBOL_GPL(rt2800_link_stats);
1062static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev) 1158static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1063{ 1159{
1064 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) { 1160 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
1065 if (rt2x00_is_usb(rt2x00dev) && 1161 if (rt2x00_rt(rt2x00dev, RT3070) ||
1066 rt2x00_rt(rt2x00dev, RT3070) && 1162 rt2x00_rt(rt2x00dev, RT3071) ||
1067 (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) 1163 rt2x00_rt(rt2x00dev, RT3090) ||
1164 rt2x00_rt(rt2x00dev, RT3390))
1068 return 0x1c + (2 * rt2x00dev->lna_gain); 1165 return 0x1c + (2 * rt2x00dev->lna_gain);
1069 else 1166 else
1070 return 0x2e + rt2x00dev->lna_gain; 1167 return 0x2e + rt2x00dev->lna_gain;
@@ -1095,8 +1192,7 @@ EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
1095void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual, 1192void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
1096 const u32 count) 1193 const u32 count)
1097{ 1194{
1098 if (rt2x00_rt(rt2x00dev, RT2860) && 1195 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
1099 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION))
1100 return; 1196 return;
1101 1197
1102 /* 1198 /*
@@ -1114,8 +1210,17 @@ EXPORT_SYMBOL_GPL(rt2800_link_tuner);
1114int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) 1210int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1115{ 1211{
1116 u32 reg; 1212 u32 reg;
1213 u16 eeprom;
1117 unsigned int i; 1214 unsigned int i;
1118 1215
1216 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1217 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1218 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1219 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1220 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1221 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1222 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1223
1119 if (rt2x00_is_usb(rt2x00dev)) { 1224 if (rt2x00_is_usb(rt2x00dev)) {
1120 /* 1225 /*
1121 * Wait until BBP and RF are ready. 1226 * Wait until BBP and RF are ready.
@@ -1135,8 +1240,25 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1135 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg); 1240 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1136 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 1241 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL,
1137 reg & ~0x00002000); 1242 reg & ~0x00002000);
1138 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) 1243 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1244 /*
1245 * Reset DMA indexes
1246 */
1247 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1248 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1249 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1250 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1251 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1252 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1253 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1254 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1255 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1256
1257 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1258 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1259
1139 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 1260 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1261 }
1140 1262
1141 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg); 1263 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1142 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1); 1264 rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
@@ -1181,12 +1303,42 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1181 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0); 1303 rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1182 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 1304 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1183 1305
1184 if (rt2x00_is_usb(rt2x00dev) && 1306 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
1185 rt2x00_rt(rt2x00dev, RT3070) && 1307
1186 (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) { 1308 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
1309 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
1310 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
1311 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1312
1313 if (rt2x00_rt(rt2x00dev, RT3071) ||
1314 rt2x00_rt(rt2x00dev, RT3090) ||
1315 rt2x00_rt(rt2x00dev, RT3390)) {
1187 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 1316 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1188 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 1317 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1189 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); 1318 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1319 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
1320 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
1321 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1322 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1323 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1324 0x0000002c);
1325 else
1326 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
1327 0x0000000f);
1328 } else {
1329 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1330 }
1331 rt2800_register_write(rt2x00dev, TX_SW_CFG2, reg);
1332 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
1333 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
1334
1335 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1336 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
1337 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
1338 } else {
1339 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1340 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
1341 }
1190 } else { 1342 } else {
1191 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000); 1343 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1192 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 1344 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -1205,19 +1357,15 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1205 1357
1206 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg); 1358 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1207 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9); 1359 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1360 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
1208 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10); 1361 rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1209 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg); 1362 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1210 1363
1211 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg); 1364 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1212 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE); 1365 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1213 if ((rt2x00_rt(rt2x00dev, RT2872) && 1366 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
1214 (rt2x00_rev(rt2x00dev) >= RT2880E_VERSION)) ||
1215 rt2x00_rt(rt2x00dev, RT2880) ||
1216 rt2x00_rt(rt2x00dev, RT2883) || 1367 rt2x00_rt(rt2x00dev, RT2883) ||
1217 rt2x00_rt(rt2x00dev, RT2890) || 1368 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
1218 rt2x00_rt(rt2x00dev, RT3052) ||
1219 (rt2x00_rt(rt2x00dev, RT3070) &&
1220 (rt2x00_rev(rt2x00dev) < RT3070_VERSION)))
1221 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2); 1369 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1222 else 1370 else
1223 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1); 1371 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
@@ -1225,38 +1373,61 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1225 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0); 1373 rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1226 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg); 1374 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1227 1375
1376 rt2800_register_read(rt2x00dev, LED_CFG, &reg);
1377 rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
1378 rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
1379 rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
1380 rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
1381 rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
1382 rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
1383 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
1384 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1385
1228 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f); 1386 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1229 1387
1388 rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1389 rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
1390 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
1391 rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1392 rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1393 rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1394 rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1395 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1396
1230 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg); 1397 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1231 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1); 1398 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1399 rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
1232 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0); 1400 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1233 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0); 1401 rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1402 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 1);
1234 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0); 1403 rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1235 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0); 1404 rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1236 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg); 1405 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1237 1406
1238 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg); 1407 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1239 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8); 1408 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1240 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0); 1409 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1241 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1); 1410 rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1242 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1411 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1243 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1412 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1244 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1413 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1245 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1414 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1246 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1415 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1247 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1416 rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1417 rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
1248 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg); 1418 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1249 1419
1250 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg); 1420 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1251 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8); 1421 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1252 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0); 1422 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1253 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1); 1423 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1254 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1424 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1255 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1425 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1256 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1); 1426 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1257 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1427 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1258 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1428 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1259 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1429 rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1430 rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
1260 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg); 1431 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1261 1432
1262 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg); 1433 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
@@ -1269,11 +1440,13 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1269 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1440 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1270 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1441 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1271 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1442 rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1443 rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
1272 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg); 1444 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1273 1445
1274 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg); 1446 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1275 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084); 1447 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1276 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0); 1448 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL,
1449 !rt2x00_is_usb(rt2x00dev));
1277 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1); 1450 rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1278 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1); 1451 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1279 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1); 1452 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
@@ -1281,6 +1454,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1281 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1454 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1282 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1455 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1283 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1456 rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1457 rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
1284 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg); 1458 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1285 1459
1286 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg); 1460 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
@@ -1293,6 +1467,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1293 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0); 1467 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1294 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1468 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1295 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0); 1469 rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1470 rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
1296 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg); 1471 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1297 1472
1298 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg); 1473 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
@@ -1305,6 +1480,7 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1305 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1); 1480 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1306 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1); 1481 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1307 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1); 1482 rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1483 rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
1308 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg); 1484 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1309 1485
1310 if (rt2x00_is_usb(rt2x00dev)) { 1486 if (rt2x00_is_usb(rt2x00dev)) {
@@ -1334,6 +1510,22 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
1334 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg); 1510 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1335 1511
1336 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca); 1512 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1513
1514 /*
1515 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
1516 * time should be set to 16. However, the original Ralink driver uses
1517 * 16 for both and indeed using a value of 10 for CCK SIFS results in
1518 * connection problems with 11g + CTS protection. Hence, use the same
1519 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
1520 */
1521 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
1522 rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
1523 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
1524 rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
1525 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
1526 rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
1527 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1528
1337 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003); 1529 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1338 1530
1339 /* 1531 /*
@@ -1481,45 +1673,79 @@ int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
1481 rt2800_wait_bbp_ready(rt2x00dev))) 1673 rt2800_wait_bbp_ready(rt2x00dev)))
1482 return -EACCES; 1674 return -EACCES;
1483 1675
1676 if (rt2800_is_305x_soc(rt2x00dev))
1677 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1678
1484 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 1679 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1485 rt2800_bbp_write(rt2x00dev, 66, 0x38); 1680 rt2800_bbp_write(rt2x00dev, 66, 0x38);
1486 rt2800_bbp_write(rt2x00dev, 69, 0x12); 1681
1682 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
1683 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1684 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1685 } else {
1686 rt2800_bbp_write(rt2x00dev, 69, 0x12);
1687 rt2800_bbp_write(rt2x00dev, 73, 0x10);
1688 }
1689
1487 rt2800_bbp_write(rt2x00dev, 70, 0x0a); 1690 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1488 rt2800_bbp_write(rt2x00dev, 73, 0x10); 1691
1489 rt2800_bbp_write(rt2x00dev, 81, 0x37); 1692 if (rt2x00_rt(rt2x00dev, RT3070) ||
1693 rt2x00_rt(rt2x00dev, RT3071) ||
1694 rt2x00_rt(rt2x00dev, RT3090) ||
1695 rt2x00_rt(rt2x00dev, RT3390)) {
1696 rt2800_bbp_write(rt2x00dev, 79, 0x13);
1697 rt2800_bbp_write(rt2x00dev, 80, 0x05);
1698 rt2800_bbp_write(rt2x00dev, 81, 0x33);
1699 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1700 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1701 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1702 } else {
1703 rt2800_bbp_write(rt2x00dev, 81, 0x37);
1704 }
1705
1490 rt2800_bbp_write(rt2x00dev, 82, 0x62); 1706 rt2800_bbp_write(rt2x00dev, 82, 0x62);
1491 rt2800_bbp_write(rt2x00dev, 83, 0x6a); 1707 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1492 rt2800_bbp_write(rt2x00dev, 84, 0x99); 1708
1709 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D) ||
1710 rt2x00_rt_rev(rt2x00dev, RT2870, REV_RT2870D))
1711 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1712 else
1713 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1714
1493 rt2800_bbp_write(rt2x00dev, 86, 0x00); 1715 rt2800_bbp_write(rt2x00dev, 86, 0x00);
1494 rt2800_bbp_write(rt2x00dev, 91, 0x04); 1716 rt2800_bbp_write(rt2x00dev, 91, 0x04);
1495 rt2800_bbp_write(rt2x00dev, 92, 0x00); 1717 rt2800_bbp_write(rt2x00dev, 92, 0x00);
1496 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1497 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1498 1718
1499 if (rt2x00_rt(rt2x00dev, RT2860) && 1719 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
1500 (rt2x00_rev(rt2x00dev) == RT2860C_VERSION)) { 1720 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
1501 rt2800_bbp_write(rt2x00dev, 69, 0x16); 1721 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
1502 rt2800_bbp_write(rt2x00dev, 73, 0x12); 1722 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
1503 } 1723 rt2800_is_305x_soc(rt2x00dev))
1504 1724 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
1505 if (rt2x00_rt(rt2x00dev, RT2860) && 1725 else
1506 (rt2x00_rev(rt2x00dev) > RT2860D_VERSION)) 1726 rt2800_bbp_write(rt2x00dev, 103, 0x00);
1507 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1508 1727
1509 if (rt2x00_is_usb(rt2x00dev) && 1728 if (rt2800_is_305x_soc(rt2x00dev))
1510 rt2x00_rt(rt2x00dev, RT3070) && 1729 rt2800_bbp_write(rt2x00dev, 105, 0x01);
1511 (rt2x00_rev(rt2x00dev) == RT3070_VERSION)) { 1730 else
1512 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1513 rt2800_bbp_write(rt2x00dev, 84, 0x99);
1514 rt2800_bbp_write(rt2x00dev, 105, 0x05); 1731 rt2800_bbp_write(rt2x00dev, 105, 0x05);
1515 } 1732 rt2800_bbp_write(rt2x00dev, 106, 0x35);
1516 1733
1517 if (rt2x00_rt(rt2x00dev, RT3052)) { 1734 if (rt2x00_rt(rt2x00dev, RT3071) ||
1518 rt2800_bbp_write(rt2x00dev, 31, 0x08); 1735 rt2x00_rt(rt2x00dev, RT3090) ||
1519 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 1736 rt2x00_rt(rt2x00dev, RT3390)) {
1520 rt2800_bbp_write(rt2x00dev, 80, 0x08); 1737 rt2800_bbp_read(rt2x00dev, 138, &value);
1738
1739 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1740 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
1741 value |= 0x20;
1742 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
1743 value &= ~0x02;
1744
1745 rt2800_bbp_write(rt2x00dev, 138, value);
1521 } 1746 }
1522 1747
1748
1523 for (i = 0; i < EEPROM_BBP_SIZE; i++) { 1749 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1524 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom); 1750 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1525 1751
@@ -1598,19 +1824,16 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1598{ 1824{
1599 u8 rfcsr; 1825 u8 rfcsr;
1600 u8 bbp; 1826 u8 bbp;
1827 u32 reg;
1828 u16 eeprom;
1601 1829
1602 if (rt2x00_is_usb(rt2x00dev) && 1830 if (!rt2x00_rt(rt2x00dev, RT3070) &&
1603 rt2x00_rt(rt2x00dev, RT3070) && 1831 !rt2x00_rt(rt2x00dev, RT3071) &&
1604 (rt2x00_rev(rt2x00dev) != RT3070_VERSION)) 1832 !rt2x00_rt(rt2x00dev, RT3090) &&
1833 !rt2x00_rt(rt2x00dev, RT3390) &&
1834 !rt2800_is_305x_soc(rt2x00dev))
1605 return 0; 1835 return 0;
1606 1836
1607 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) {
1608 if (!rt2x00_rf(rt2x00dev, RF3020) &&
1609 !rt2x00_rf(rt2x00dev, RF3021) &&
1610 !rt2x00_rf(rt2x00dev, RF3022))
1611 return 0;
1612 }
1613
1614 /* 1837 /*
1615 * Init RF calibration. 1838 * Init RF calibration.
1616 */ 1839 */
@@ -1621,13 +1844,15 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1621 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0); 1844 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1622 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); 1845 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1623 1846
1624 if (rt2x00_is_usb(rt2x00dev)) { 1847 if (rt2x00_rt(rt2x00dev, RT3070) ||
1848 rt2x00_rt(rt2x00dev, RT3071) ||
1849 rt2x00_rt(rt2x00dev, RT3090)) {
1625 rt2800_rfcsr_write(rt2x00dev, 4, 0x40); 1850 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1626 rt2800_rfcsr_write(rt2x00dev, 5, 0x03); 1851 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1627 rt2800_rfcsr_write(rt2x00dev, 6, 0x02); 1852 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1628 rt2800_rfcsr_write(rt2x00dev, 7, 0x70); 1853 rt2800_rfcsr_write(rt2x00dev, 7, 0x70);
1629 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); 1854 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1630 rt2800_rfcsr_write(rt2x00dev, 10, 0x71); 1855 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
1631 rt2800_rfcsr_write(rt2x00dev, 11, 0x21); 1856 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1632 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); 1857 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
1633 rt2800_rfcsr_write(rt2x00dev, 14, 0x90); 1858 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
@@ -1640,9 +1865,41 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1640 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); 1865 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1641 rt2800_rfcsr_write(rt2x00dev, 24, 0x16); 1866 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
1642 rt2800_rfcsr_write(rt2x00dev, 25, 0x01); 1867 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1643 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
1644 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); 1868 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
1645 } else if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev)) { 1869 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1870 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
1871 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
1872 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
1873 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
1874 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1875 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
1876 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
1877 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
1878 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
1879 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1880 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
1881 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1882 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
1883 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
1884 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1885 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1886 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
1887 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
1888 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
1889 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
1890 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
1891 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
1892 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1893 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
1894 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1895 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1896 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1897 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1898 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
1899 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
1900 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
1901 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
1902 } else if (rt2800_is_305x_soc(rt2x00dev)) {
1646 rt2800_rfcsr_write(rt2x00dev, 0, 0x50); 1903 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1647 rt2800_rfcsr_write(rt2x00dev, 1, 0x01); 1904 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1648 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); 1905 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
@@ -1673,15 +1930,57 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1673 rt2800_rfcsr_write(rt2x00dev, 27, 0x23); 1930 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1674 rt2800_rfcsr_write(rt2x00dev, 28, 0x13); 1931 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1675 rt2800_rfcsr_write(rt2x00dev, 29, 0x83); 1932 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1933 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
1934 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
1935 return 0;
1936 }
1937
1938 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
1939 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1940 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1941 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1942 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1943 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1944 rt2x00_rt(rt2x00dev, RT3090)) {
1945 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1946 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
1947 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1948
1949 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
1950
1951 rt2800_register_read(rt2x00dev, LDO_CFG0, &reg);
1952 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
1953 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
1954 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
1955 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1956 if (rt2x00_get_field16(eeprom, EEPROM_NIC_DAC_TEST))
1957 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
1958 else
1959 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
1960 }
1961 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
1962 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
1963 rt2800_register_read(rt2x00dev, GPIO_SWITCH, &reg);
1964 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
1965 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1676 } 1966 }
1677 1967
1678 /* 1968 /*
1679 * Set RX Filter calibration for 20MHz and 40MHz 1969 * Set RX Filter calibration for 20MHz and 40MHz
1680 */ 1970 */
1681 rt2x00dev->calibration[0] = 1971 if (rt2x00_rt(rt2x00dev, RT3070)) {
1682 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16); 1972 rt2x00dev->calibration[0] =
1683 rt2x00dev->calibration[1] = 1973 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1684 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); 1974 rt2x00dev->calibration[1] =
1975 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1976 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
1977 rt2x00_rt(rt2x00dev, RT3090) ||
1978 rt2x00_rt(rt2x00dev, RT3390)) {
1979 rt2x00dev->calibration[0] =
1980 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
1981 rt2x00dev->calibration[1] =
1982 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
1983 }
1685 1984
1686 /* 1985 /*
1687 * Set back to initial state 1986 * Set back to initial state
@@ -1699,6 +1998,81 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1699 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0); 1998 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1700 rt2800_bbp_write(rt2x00dev, 4, bbp); 1999 rt2800_bbp_write(rt2x00dev, 4, bbp);
1701 2000
2001 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2002 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2003 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2004 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
2005 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
2006
2007 rt2800_register_read(rt2x00dev, OPT_14_CSR, &reg);
2008 rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
2009 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
2010
2011 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2012 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
2013 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2014 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2015 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2016 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2017 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2018 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
2019 }
2020 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &eeprom);
2021 if (rt2x00_get_field16(eeprom, EEPROM_TXMIXER_GAIN_BG_VAL) >= 1)
2022 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
2023 rt2x00_get_field16(eeprom,
2024 EEPROM_TXMIXER_GAIN_BG_VAL));
2025 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2026
2027 if (rt2x00_rt(rt2x00dev, RT3090)) {
2028 rt2800_bbp_read(rt2x00dev, 138, &bbp);
2029
2030 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2031 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1)
2032 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
2033 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1)
2034 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
2035
2036 rt2800_bbp_write(rt2x00dev, 138, bbp);
2037 }
2038
2039 if (rt2x00_rt(rt2x00dev, RT3071) ||
2040 rt2x00_rt(rt2x00dev, RT3090) ||
2041 rt2x00_rt(rt2x00dev, RT3390)) {
2042 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2043 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2044 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2045 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2046 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2047 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2048 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2049
2050 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
2051 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
2052 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
2053
2054 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
2055 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
2056 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
2057
2058 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
2059 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
2060 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
2061 }
2062
2063 if (rt2x00_rt(rt2x00dev, RT3070) || rt2x00_rt(rt2x00dev, RT3071)) {
2064 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
2065 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
2066 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E))
2067 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
2068 else
2069 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
2070 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
2071 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
2072 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
2073 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
2074 }
2075
1702 return 0; 2076 return 0;
1703} 2077}
1704EXPORT_SYMBOL_GPL(rt2800_init_rfcsr); 2078EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
@@ -1774,10 +2148,7 @@ int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1774 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word); 2148 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1775 } else if (rt2x00_rt(rt2x00dev, RT2860) || 2149 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
1776 rt2x00_rt(rt2x00dev, RT2870) || 2150 rt2x00_rt(rt2x00dev, RT2870) ||
1777 rt2x00_rt(rt2x00dev, RT2872) || 2151 rt2x00_rt(rt2x00dev, RT2872)) {
1778 rt2x00_rt(rt2x00dev, RT2880) ||
1779 (rt2x00_rt(rt2x00dev, RT2883) &&
1780 (rt2x00_rev(rt2x00dev) < RT2883_VERSION))) {
1781 /* 2152 /*
1782 * There is a max of 2 RX streams for RT28x0 series 2153 * There is a max of 2 RX streams for RT28x0 series
1783 */ 2154 */
@@ -1882,10 +2253,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1882 if (!rt2x00_rt(rt2x00dev, RT2860) && 2253 if (!rt2x00_rt(rt2x00dev, RT2860) &&
1883 !rt2x00_rt(rt2x00dev, RT2870) && 2254 !rt2x00_rt(rt2x00dev, RT2870) &&
1884 !rt2x00_rt(rt2x00dev, RT2872) && 2255 !rt2x00_rt(rt2x00dev, RT2872) &&
1885 !rt2x00_rt(rt2x00dev, RT2880) &&
1886 !rt2x00_rt(rt2x00dev, RT2883) && 2256 !rt2x00_rt(rt2x00dev, RT2883) &&
1887 !rt2x00_rt(rt2x00dev, RT2890) &&
1888 !rt2x00_rt(rt2x00dev, RT3052) &&
1889 !rt2x00_rt(rt2x00dev, RT3070) && 2257 !rt2x00_rt(rt2x00dev, RT3070) &&
1890 !rt2x00_rt(rt2x00dev, RT3071) && 2258 !rt2x00_rt(rt2x00dev, RT3071) &&
1891 !rt2x00_rt(rt2x00dev, RT3090) && 2259 !rt2x00_rt(rt2x00dev, RT3090) &&
@@ -1954,7 +2322,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
1954EXPORT_SYMBOL_GPL(rt2800_init_eeprom); 2322EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
1955 2323
1956/* 2324/*
1957 * RF value list for rt28x0 2325 * RF value list for rt28xx
1958 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750) 2326 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
1959 */ 2327 */
1960static const struct rf_channel rf_vals[] = { 2328static const struct rf_channel rf_vals[] = {
@@ -2029,10 +2397,10 @@ static const struct rf_channel rf_vals[] = {
2029}; 2397};
2030 2398
2031/* 2399/*
2032 * RF value list for rt3070 2400 * RF value list for rt3xxx
2033 * Supports: 2.4 GHz 2401 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
2034 */ 2402 */
2035static const struct rf_channel rf_vals_302x[] = { 2403static const struct rf_channel rf_vals_3x[] = {
2036 {1, 241, 2, 2 }, 2404 {1, 241, 2, 2 },
2037 {2, 241, 2, 7 }, 2405 {2, 241, 2, 7 },
2038 {3, 242, 2, 2 }, 2406 {3, 242, 2, 2 },
@@ -2047,6 +2415,51 @@ static const struct rf_channel rf_vals_302x[] = {
2047 {12, 246, 2, 7 }, 2415 {12, 246, 2, 7 },
2048 {13, 247, 2, 2 }, 2416 {13, 247, 2, 2 },
2049 {14, 248, 2, 4 }, 2417 {14, 248, 2, 4 },
2418
2419 /* 802.11 UNI / HyperLan 2 */
2420 {36, 0x56, 0, 4},
2421 {38, 0x56, 0, 6},
2422 {40, 0x56, 0, 8},
2423 {44, 0x57, 0, 0},
2424 {46, 0x57, 0, 2},
2425 {48, 0x57, 0, 4},
2426 {52, 0x57, 0, 8},
2427 {54, 0x57, 0, 10},
2428 {56, 0x58, 0, 0},
2429 {60, 0x58, 0, 4},
2430 {62, 0x58, 0, 6},
2431 {64, 0x58, 0, 8},
2432
2433 /* 802.11 HyperLan 2 */
2434 {100, 0x5b, 0, 8},
2435 {102, 0x5b, 0, 10},
2436 {104, 0x5c, 0, 0},
2437 {108, 0x5c, 0, 4},
2438 {110, 0x5c, 0, 6},
2439 {112, 0x5c, 0, 8},
2440 {116, 0x5d, 0, 0},
2441 {118, 0x5d, 0, 2},
2442 {120, 0x5d, 0, 4},
2443 {124, 0x5d, 0, 8},
2444 {126, 0x5d, 0, 10},
2445 {128, 0x5e, 0, 0},
2446 {132, 0x5e, 0, 4},
2447 {134, 0x5e, 0, 6},
2448 {136, 0x5e, 0, 8},
2449 {140, 0x5f, 0, 0},
2450
2451 /* 802.11 UNII */
2452 {149, 0x5f, 0, 9},
2453 {151, 0x5f, 0, 11},
2454 {153, 0x60, 0, 1},
2455 {157, 0x60, 0, 5},
2456 {159, 0x60, 0, 7},
2457 {161, 0x60, 0, 9},
2458 {165, 0x61, 0, 1},
2459 {167, 0x61, 0, 3},
2460 {169, 0x61, 0, 5},
2461 {171, 0x61, 0, 7},
2462 {173, 0x61, 0, 9},
2050}; 2463};
2051 2464
2052int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev) 2465int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
@@ -2087,11 +2500,11 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2087 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM; 2500 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2088 2501
2089 if (rt2x00_rf(rt2x00dev, RF2820) || 2502 if (rt2x00_rf(rt2x00dev, RF2820) ||
2090 rt2x00_rf(rt2x00dev, RF2720) || 2503 rt2x00_rf(rt2x00dev, RF2720)) {
2091 rt2x00_rf(rt2x00dev, RF3052)) {
2092 spec->num_channels = 14; 2504 spec->num_channels = 14;
2093 spec->channels = rf_vals; 2505 spec->channels = rf_vals;
2094 } else if (rt2x00_rf(rt2x00dev, RF2850) || rt2x00_rf(rt2x00dev, RF2750)) { 2506 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
2507 rt2x00_rf(rt2x00dev, RF2750)) {
2095 spec->supported_bands |= SUPPORT_BAND_5GHZ; 2508 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2096 spec->num_channels = ARRAY_SIZE(rf_vals); 2509 spec->num_channels = ARRAY_SIZE(rf_vals);
2097 spec->channels = rf_vals; 2510 spec->channels = rf_vals;
@@ -2099,8 +2512,12 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2099 rt2x00_rf(rt2x00dev, RF2020) || 2512 rt2x00_rf(rt2x00dev, RF2020) ||
2100 rt2x00_rf(rt2x00dev, RF3021) || 2513 rt2x00_rf(rt2x00dev, RF3021) ||
2101 rt2x00_rf(rt2x00dev, RF3022)) { 2514 rt2x00_rf(rt2x00dev, RF3022)) {
2102 spec->num_channels = ARRAY_SIZE(rf_vals_302x); 2515 spec->num_channels = 14;
2103 spec->channels = rf_vals_302x; 2516 spec->channels = rf_vals_3x;
2517 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
2518 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2519 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
2520 spec->channels = rf_vals_3x;
2104 } 2521 }
2105 2522
2106 /* 2523 /*
@@ -2111,8 +2528,11 @@ int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2111 else 2528 else
2112 spec->ht.ht_supported = false; 2529 spec->ht.ht_supported = false;
2113 2530
2531 /*
2532 * Don't set IEEE80211_HT_CAP_SUP_WIDTH_20_40 for now as it causes
2533 * reception problems with HT40 capable 11n APs
2534 */
2114 spec->ht.cap = 2535 spec->ht.cap =
2115 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2116 IEEE80211_HT_CAP_GRN_FLD | 2536 IEEE80211_HT_CAP_GRN_FLD |
2117 IEEE80211_HT_CAP_SGI_20 | 2537 IEEE80211_HT_CAP_SGI_20 |
2118 IEEE80211_HT_CAP_SGI_40 | 2538 IEEE80211_HT_CAP_SGI_40 |
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.h b/drivers/net/wireless/rt2x00/rt2800lib.h
index ebabeae62d1b..94de999e2290 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.h
+++ b/drivers/net/wireless/rt2x00/rt2800lib.h
@@ -111,6 +111,9 @@ void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
111 const u8 command, const u8 token, 111 const u8 command, const u8 token,
112 const u8 arg0, const u8 arg1); 112 const u8 arg0, const u8 arg1);
113 113
114void rt2800_write_txwi(struct sk_buff *skb, struct txentry_desc *txdesc);
115void rt2800_process_rxwi(struct sk_buff *skb, struct rxdone_entry_desc *txdesc);
116
114extern const struct rt2x00debug rt2800_rt2x00debug; 117extern const struct rt2x00debug rt2800_rt2x00debug;
115 118
116int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev); 119int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev);
diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c
index 91cce2d0f6db..b2f23272c3aa 100644
--- a/drivers/net/wireless/rt2x00/rt2800pci.c
+++ b/drivers/net/wireless/rt2x00/rt2800pci.c
@@ -60,6 +60,12 @@ static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
60 unsigned int i; 60 unsigned int i;
61 u32 reg; 61 u32 reg;
62 62
63 /*
64 * SOC devices don't support MCU requests.
65 */
66 if (rt2x00_is_soc(rt2x00dev))
67 return;
68
63 for (i = 0; i < 200; i++) { 69 for (i = 0; i < 200; i++) {
64 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg); 70 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
65 71
@@ -341,19 +347,6 @@ static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
341 struct queue_entry_priv_pci *entry_priv; 347 struct queue_entry_priv_pci *entry_priv;
342 u32 reg; 348 u32 reg;
343 349
344 rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
345 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
346 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
347 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
348 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
349 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
350 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
351 rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
352 rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
353
354 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
355 rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
356
357 /* 350 /*
358 * Initialize registers. 351 * Initialize registers.
359 */ 352 */
@@ -620,64 +613,31 @@ static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
620/* 613/*
621 * TX descriptor initialization 614 * TX descriptor initialization
622 */ 615 */
616static int rt2800pci_write_tx_data(struct queue_entry* entry,
617 struct txentry_desc *txdesc)
618{
619 int ret;
620
621 ret = rt2x00pci_write_tx_data(entry, txdesc);
622 if (ret)
623 return ret;
624
625 rt2800_write_txwi(entry->skb, txdesc);
626
627 return 0;
628}
629
630
623static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev, 631static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
624 struct sk_buff *skb, 632 struct sk_buff *skb,
625 struct txentry_desc *txdesc) 633 struct txentry_desc *txdesc)
626{ 634{
627 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 635 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
628 __le32 *txd = skbdesc->desc; 636 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
629 __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->ops->extra_tx_headroom); 637 __le32 *txd = entry_priv->desc;
630 u32 word; 638 u32 word;
631 639
632 /* 640 /*
633 * Initialize TX Info descriptor
634 */
635 rt2x00_desc_read(txwi, 0, &word);
636 rt2x00_set_field32(&word, TXWI_W0_FRAG,
637 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
638 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
639 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
640 rt2x00_set_field32(&word, TXWI_W0_TS,
641 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
642 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
643 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
644 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
645 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
646 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
647 rt2x00_set_field32(&word, TXWI_W0_BW,
648 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
649 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
650 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
651 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
652 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
653 rt2x00_desc_write(txwi, 0, word);
654
655 rt2x00_desc_read(txwi, 1, &word);
656 rt2x00_set_field32(&word, TXWI_W1_ACK,
657 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
658 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
659 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
660 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
661 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
662 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
663 txdesc->key_idx : 0xff);
664 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
665 skb->len - txdesc->l2pad);
666 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
667 skbdesc->entry->queue->qid + 1);
668 rt2x00_desc_write(txwi, 1, word);
669
670 /*
671 * Always write 0 to IV/EIV fields, hardware will insert the IV
672 * from the IVEIV register when TXD_W3_WIV is set to 0.
673 * When TXD_W3_WIV is set to 1 it will use the IV data
674 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
675 * crypto entry in the registers should be used to encrypt the frame.
676 */
677 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
678 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
679
680 /*
681 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1 641 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
682 * must contains a TXWI structure + 802.11 header + padding + 802.11 642 * must contains a TXWI structure + 802.11 header + padding + 802.11
683 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and 643 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
@@ -698,15 +658,14 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
698 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags)); 658 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
699 rt2x00_set_field32(&word, TXD_W1_BURST, 659 rt2x00_set_field32(&word, TXD_W1_BURST,
700 test_bit(ENTRY_TXD_BURST, &txdesc->flags)); 660 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
701 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, 661 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
702 rt2x00dev->ops->extra_tx_headroom);
703 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0); 662 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
704 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0); 663 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
705 rt2x00_desc_write(txd, 1, word); 664 rt2x00_desc_write(txd, 1, word);
706 665
707 rt2x00_desc_read(txd, 2, &word); 666 rt2x00_desc_read(txd, 2, &word);
708 rt2x00_set_field32(&word, TXD_W2_SD_PTR1, 667 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
709 skbdesc->skb_dma + rt2x00dev->ops->extra_tx_headroom); 668 skbdesc->skb_dma + TXWI_DESC_SIZE);
710 rt2x00_desc_write(txd, 2, word); 669 rt2x00_desc_write(txd, 2, word);
711 670
712 rt2x00_desc_read(txd, 3, &word); 671 rt2x00_desc_read(txd, 3, &word);
@@ -714,15 +673,21 @@ static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
714 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags)); 673 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
715 rt2x00_set_field32(&word, TXD_W3_QSEL, 2); 674 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
716 rt2x00_desc_write(txd, 3, word); 675 rt2x00_desc_write(txd, 3, word);
676
677 /*
678 * Register descriptor details in skb frame descriptor.
679 */
680 skbdesc->desc = txd;
681 skbdesc->desc_len = TXD_DESC_SIZE;
717} 682}
718 683
719/* 684/*
720 * TX data initialization 685 * TX data initialization
721 */ 686 */
722static void rt2800pci_write_beacon(struct queue_entry *entry) 687static void rt2800pci_write_beacon(struct queue_entry *entry,
688 struct txentry_desc *txdesc)
723{ 689{
724 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 690 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
725 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
726 unsigned int beacon_base; 691 unsigned int beacon_base;
727 u32 reg; 692 u32 reg;
728 693
@@ -735,15 +700,25 @@ static void rt2800pci_write_beacon(struct queue_entry *entry)
735 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 700 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
736 701
737 /* 702 /*
738 * Write entire beacon with descriptor to register. 703 * Add the TXWI for the beacon to the skb.
704 */
705 rt2800_write_txwi(entry->skb, txdesc);
706 skb_push(entry->skb, TXWI_DESC_SIZE);
707
708 /*
709 * Write entire beacon with TXWI to register.
739 */ 710 */
740 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 711 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
741 rt2800_register_multiwrite(rt2x00dev, 712 rt2800_register_multiwrite(rt2x00dev, beacon_base,
742 beacon_base, 713 entry->skb->data, entry->skb->len);
743 skbdesc->desc, skbdesc->desc_len); 714
744 rt2800_register_multiwrite(rt2x00dev, 715 /*
745 beacon_base + skbdesc->desc_len, 716 * Enable beaconing again.
746 entry->skb->data, entry->skb->len); 717 */
718 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
719 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
720 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
721 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
747 722
748 /* 723 /*
749 * Clean up beacon skb. 724 * Clean up beacon skb.
@@ -757,18 +732,6 @@ static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
757{ 732{
758 struct data_queue *queue; 733 struct data_queue *queue;
759 unsigned int idx, qidx = 0; 734 unsigned int idx, qidx = 0;
760 u32 reg;
761
762 if (queue_idx == QID_BEACON) {
763 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
764 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
765 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
766 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
767 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
768 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
769 }
770 return;
771 }
772 735
773 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT) 736 if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
774 return; 737 return;
@@ -811,34 +774,21 @@ static void rt2800pci_fill_rxdone(struct queue_entry *entry,
811 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 774 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
812 struct queue_entry_priv_pci *entry_priv = entry->priv_data; 775 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
813 __le32 *rxd = entry_priv->desc; 776 __le32 *rxd = entry_priv->desc;
814 __le32 *rxwi = (__le32 *)entry->skb->data; 777 u32 word;
815 u32 rxd3; 778
816 u32 rxwi0; 779 rt2x00_desc_read(rxd, 3, &word);
817 u32 rxwi1; 780
818 u32 rxwi2; 781 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
819 u32 rxwi3;
820
821 rt2x00_desc_read(rxd, 3, &rxd3);
822 rt2x00_desc_read(rxwi, 0, &rxwi0);
823 rt2x00_desc_read(rxwi, 1, &rxwi1);
824 rt2x00_desc_read(rxwi, 2, &rxwi2);
825 rt2x00_desc_read(rxwi, 3, &rxwi3);
826
827 if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
828 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 782 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
829 783
830 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) { 784 /*
831 /* 785 * Unfortunately we don't know the cipher type used during
832 * Unfortunately we don't know the cipher type used during 786 * decryption. This prevents us from correct providing
833 * decryption. This prevents us from correct providing 787 * correct statistics through debugfs.
834 * correct statistics through debugfs. 788 */
835 */ 789 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
836 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
837 rxdesc->cipher_status =
838 rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
839 }
840 790
841 if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) { 791 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
842 /* 792 /*
843 * Hardware has stripped IV/EIV data from 802.11 frame during 793 * Hardware has stripped IV/EIV data from 802.11 frame during
844 * decryption. Unfortunately the descriptor doesn't contain 794 * decryption. Unfortunately the descriptor doesn't contain
@@ -853,51 +803,22 @@ static void rt2800pci_fill_rxdone(struct queue_entry *entry,
853 rxdesc->flags |= RX_FLAG_MMIC_ERROR; 803 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
854 } 804 }
855 805
856 if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS)) 806 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
857 rxdesc->dev_flags |= RXDONE_MY_BSS; 807 rxdesc->dev_flags |= RXDONE_MY_BSS;
858 808
859 if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) 809 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
860 rxdesc->dev_flags |= RXDONE_L2PAD; 810 rxdesc->dev_flags |= RXDONE_L2PAD;
861 811
862 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
863 rxdesc->flags |= RX_FLAG_SHORT_GI;
864
865 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
866 rxdesc->flags |= RX_FLAG_40MHZ;
867
868 /* 812 /*
869 * Detect RX rate, always use MCS as signal type. 813 * Process the RXWI structure that is at the start of the buffer.
870 */ 814 */
871 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 815 rt2800_process_rxwi(entry->skb, rxdesc);
872 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
873 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
874
875 /*
876 * Mask of 0x8 bit to remove the short preamble flag.
877 */
878 if (rxdesc->rate_mode == RATE_MODE_CCK)
879 rxdesc->signal &= ~0x8;
880
881 rxdesc->rssi =
882 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
883 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
884
885 rxdesc->noise =
886 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
887 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
888
889 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
890 816
891 /* 817 /*
892 * Set RX IDX in register to inform hardware that we have handled 818 * Set RX IDX in register to inform hardware that we have handled
893 * this entry and it is available for reuse again. 819 * this entry and it is available for reuse again.
894 */ 820 */
895 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx); 821 rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
896
897 /*
898 * Remove TXWI descriptor from start of buffer.
899 */
900 skb_pull(entry->skb, RXWI_DESC_SIZE);
901} 822}
902 823
903/* 824/*
@@ -907,14 +828,12 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
907{ 828{
908 struct data_queue *queue; 829 struct data_queue *queue;
909 struct queue_entry *entry; 830 struct queue_entry *entry;
910 struct queue_entry *entry_done; 831 __le32 *txwi;
911 struct queue_entry_priv_pci *entry_priv;
912 struct txdone_entry_desc txdesc; 832 struct txdone_entry_desc txdesc;
913 u32 word; 833 u32 word;
914 u32 reg; 834 u32 reg;
915 u32 old_reg; 835 u32 old_reg;
916 unsigned int type; 836 int wcid, ack, pid, tx_wcid, tx_ack, tx_pid;
917 unsigned int index;
918 u16 mcs, real_mcs; 837 u16 mcs, real_mcs;
919 838
920 /* 839 /*
@@ -936,76 +855,89 @@ static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
936 break; 855 break;
937 old_reg = reg; 856 old_reg = reg;
938 857
858 wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
859 ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED);
860 pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
861
939 /* 862 /*
940 * Skip this entry when it contains an invalid 863 * Skip this entry when it contains an invalid
941 * queue identication number. 864 * queue identication number.
942 */ 865 */
943 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1; 866 if (pid <= 0 || pid > QID_RX)
944 if (type >= QID_RX)
945 continue; 867 continue;
946 868
947 queue = rt2x00queue_get_queue(rt2x00dev, type); 869 queue = rt2x00queue_get_queue(rt2x00dev, pid - 1);
948 if (unlikely(!queue)) 870 if (unlikely(!queue))
949 continue; 871 continue;
950 872
951 /* 873 /*
952 * Skip this entry when it contains an invalid 874 * Inside each queue, we process each entry in a chronological
953 * index number. 875 * order. We first check that the queue is not empty.
954 */ 876 */
955 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1; 877 if (rt2x00queue_empty(queue))
956 if (unlikely(index >= queue->limit))
957 continue; 878 continue;
879 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
958 880
959 entry = &queue->entries[index]; 881 /* Check if we got a match by looking at WCID/ACK/PID
960 entry_priv = entry->priv_data; 882 * fields */
961 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word); 883 txwi = (__le32 *)(entry->skb->data -
884 rt2x00dev->ops->extra_tx_headroom);
962 885
963 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE); 886 rt2x00_desc_read(txwi, 1, &word);
964 while (entry != entry_done) { 887 tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID);
965 /* 888 tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK);
966 * Catch up. 889 tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID);
967 * Just report any entries we missed as failed.
968 */
969 WARNING(rt2x00dev,
970 "TX status report missed for entry %d\n",
971 entry_done->entry_idx);
972 890
973 txdesc.flags = 0; 891 if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid))
974 __set_bit(TXDONE_UNKNOWN, &txdesc.flags); 892 WARNING(rt2x00dev, "invalid TX_STA_FIFO content\n");
975 txdesc.retry = 0;
976
977 rt2x00lib_txdone(entry_done, &txdesc);
978 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
979 }
980 893
981 /* 894 /*
982 * Obtain the status about this packet. 895 * Obtain the status about this packet.
983 */ 896 */
984 txdesc.flags = 0; 897 txdesc.flags = 0;
985 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) 898 rt2x00_desc_read(txwi, 0, &word);
986 __set_bit(TXDONE_SUCCESS, &txdesc.flags); 899 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
987 else 900 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
988 __set_bit(TXDONE_FAILURE, &txdesc.flags);
989 901
990 /* 902 /*
991 * Ralink has a retry mechanism using a global fallback 903 * Ralink has a retry mechanism using a global fallback
992 * table. We setup this fallback table to try immediate 904 * table. We setup this fallback table to try the immediate
993 * lower rate for all rates. In the TX_STA_FIFO, 905 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
994 * the MCS field contains the MCS used for the successfull 906 * always contains the MCS used for the last transmission, be
995 * transmission. If the first transmission succeed, 907 * it successful or not.
996 * we have mcs == tx_mcs. On the second transmission,
997 * we have mcs = tx_mcs - 1. So the number of
998 * retry is (tx_mcs - mcs).
999 */ 908 */
1000 mcs = rt2x00_get_field32(word, TXWI_W0_MCS); 909 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS)) {
1001 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS); 910 /*
911 * Transmission succeeded. The number of retries is
912 * mcs - real_mcs
913 */
914 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
915 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
916 } else {
917 /*
918 * Transmission failed. The number of retries is
919 * always 7 in this case (for a total number of 8
920 * frames sent).
921 */
922 __set_bit(TXDONE_FAILURE, &txdesc.flags);
923 txdesc.retry = 7;
924 }
925
1002 __set_bit(TXDONE_FALLBACK, &txdesc.flags); 926 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1003 txdesc.retry = mcs - min(mcs, real_mcs); 927
1004 928
1005 rt2x00lib_txdone(entry, &txdesc); 929 rt2x00lib_txdone(entry, &txdesc);
1006 } 930 }
1007} 931}
1008 932
933static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
934{
935 struct ieee80211_conf conf = { .flags = 0 };
936 struct rt2x00lib_conf libconf = { .conf = &conf };
937
938 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
939}
940
1009static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance) 941static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1010{ 942{
1011 struct rt2x00_dev *rt2x00dev = dev_instance; 943 struct rt2x00_dev *rt2x00dev = dev_instance;
@@ -1030,6 +962,9 @@ static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
1030 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) 962 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
1031 rt2800pci_txdone(rt2x00dev); 963 rt2800pci_txdone(rt2x00dev);
1032 964
965 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
966 rt2800pci_wakeup(rt2x00dev);
967
1033 return IRQ_HANDLED; 968 return IRQ_HANDLED;
1034} 969}
1035 970
@@ -1128,7 +1063,7 @@ static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1128 .reset_tuner = rt2800_reset_tuner, 1063 .reset_tuner = rt2800_reset_tuner,
1129 .link_tuner = rt2800_link_tuner, 1064 .link_tuner = rt2800_link_tuner,
1130 .write_tx_desc = rt2800pci_write_tx_desc, 1065 .write_tx_desc = rt2800pci_write_tx_desc,
1131 .write_tx_data = rt2x00pci_write_tx_data, 1066 .write_tx_data = rt2800pci_write_tx_data,
1132 .write_beacon = rt2800pci_write_beacon, 1067 .write_beacon = rt2800pci_write_beacon,
1133 .kick_tx_queue = rt2800pci_kick_tx_queue, 1068 .kick_tx_queue = rt2800pci_kick_tx_queue,
1134 .kill_tx_queue = rt2800pci_kill_tx_queue, 1069 .kill_tx_queue = rt2800pci_kill_tx_queue,
@@ -1184,6 +1119,7 @@ static const struct rt2x00_ops rt2800pci_ops = {
1184/* 1119/*
1185 * RT2800pci module information. 1120 * RT2800pci module information.
1186 */ 1121 */
1122#ifdef CONFIG_RT2800PCI_PCI
1187static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = { 1123static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1188 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1124 { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
1189 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1125 { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
@@ -1208,9 +1144,11 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1208 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1144 { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
1209 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1145 { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
1210 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) }, 1146 { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
1147 { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
1211#endif 1148#endif
1212 { 0, } 1149 { 0, }
1213}; 1150};
1151#endif /* CONFIG_RT2800PCI_PCI */
1214 1152
1215MODULE_AUTHOR(DRV_PROJECT); 1153MODULE_AUTHOR(DRV_PROJECT);
1216MODULE_VERSION(DRV_VERSION); 1154MODULE_VERSION(DRV_VERSION);
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.c b/drivers/net/wireless/rt2x00/rt2800usb.c
index d27d7d5d850c..0f8b84b7224c 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.c
+++ b/drivers/net/wireless/rt2x00/rt2800usb.c
@@ -400,60 +400,16 @@ static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
400 struct txentry_desc *txdesc) 400 struct txentry_desc *txdesc)
401{ 401{
402 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 402 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
403 __le32 *txi = skbdesc->desc; 403 __le32 *txi = (__le32 *)(skb->data - TXWI_DESC_SIZE - TXINFO_DESC_SIZE);
404 __le32 *txwi = &txi[TXINFO_DESC_SIZE / sizeof(__le32)];
405 u32 word; 404 u32 word;
406 405
407 /* 406 /*
408 * Initialize TX Info descriptor 407 * Initialize TXWI descriptor
409 */ 408 */
410 rt2x00_desc_read(txwi, 0, &word); 409 rt2800_write_txwi(skb, txdesc);
411 rt2x00_set_field32(&word, TXWI_W0_FRAG,
412 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
413 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
414 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
415 rt2x00_set_field32(&word, TXWI_W0_TS,
416 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
417 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
418 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
419 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
420 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
421 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
422 rt2x00_set_field32(&word, TXWI_W0_BW,
423 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
424 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
425 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
426 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
427 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
428 rt2x00_desc_write(txwi, 0, word);
429
430 rt2x00_desc_read(txwi, 1, &word);
431 rt2x00_set_field32(&word, TXWI_W1_ACK,
432 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
433 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
434 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
435 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
436 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
437 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
438 txdesc->key_idx : 0xff);
439 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
440 skb->len - txdesc->l2pad);
441 rt2x00_set_field32(&word, TXWI_W1_PACKETID,
442 skbdesc->entry->queue->qid + 1);
443 rt2x00_desc_write(txwi, 1, word);
444 410
445 /* 411 /*
446 * Always write 0 to IV/EIV fields, hardware will insert the IV 412 * Initialize TXINFO descriptor
447 * from the IVEIV register when TXINFO_W0_WIV is set to 0.
448 * When TXINFO_W0_WIV is set to 1 it will use the IV data
449 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
450 * crypto entry in the registers should be used to encrypt the frame.
451 */
452 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
453 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
454
455 /*
456 * Initialize TX descriptor
457 */ 413 */
458 rt2x00_desc_read(txi, 0, &word); 414 rt2x00_desc_read(txi, 0, &word);
459 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN, 415 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_PKT_LEN,
@@ -466,26 +422,25 @@ static void rt2800usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
466 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST, 422 rt2x00_set_field32(&word, TXINFO_W0_USB_DMA_TX_BURST,
467 test_bit(ENTRY_TXD_BURST, &txdesc->flags)); 423 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
468 rt2x00_desc_write(txi, 0, word); 424 rt2x00_desc_write(txi, 0, word);
425
426 /*
427 * Register descriptor details in skb frame descriptor.
428 */
429 skbdesc->desc = txi;
430 skbdesc->desc_len = TXINFO_DESC_SIZE + TXWI_DESC_SIZE;
469} 431}
470 432
471/* 433/*
472 * TX data initialization 434 * TX data initialization
473 */ 435 */
474static void rt2800usb_write_beacon(struct queue_entry *entry) 436static void rt2800usb_write_beacon(struct queue_entry *entry,
437 struct txentry_desc *txdesc)
475{ 438{
476 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 439 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
477 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
478 unsigned int beacon_base; 440 unsigned int beacon_base;
479 u32 reg; 441 u32 reg;
480 442
481 /* 443 /*
482 * Add the descriptor in front of the skb.
483 */
484 skb_push(entry->skb, entry->queue->desc_size);
485 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
486 skbdesc->desc = entry->skb->data;
487
488 /*
489 * Disable beaconing while we are reloading the beacon data, 444 * Disable beaconing while we are reloading the beacon data,
490 * otherwise we might be sending out invalid data. 445 * otherwise we might be sending out invalid data.
491 */ 446 */
@@ -494,6 +449,12 @@ static void rt2800usb_write_beacon(struct queue_entry *entry)
494 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg); 449 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
495 450
496 /* 451 /*
452 * Add the TXWI for the beacon to the skb.
453 */
454 rt2800_write_txwi(entry->skb, txdesc);
455 skb_push(entry->skb, TXWI_DESC_SIZE);
456
457 /*
497 * Write entire beacon with descriptor to register. 458 * Write entire beacon with descriptor to register.
498 */ 459 */
499 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 460 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
@@ -503,6 +464,14 @@ static void rt2800usb_write_beacon(struct queue_entry *entry)
503 REGISTER_TIMEOUT32(entry->skb->len)); 464 REGISTER_TIMEOUT32(entry->skb->len));
504 465
505 /* 466 /*
467 * Enable beaconing again.
468 */
469 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
470 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
471 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
472 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
473
474 /*
506 * Clean up the beacon skb. 475 * Clean up the beacon skb.
507 */ 476 */
508 dev_kfree_skb(entry->skb); 477 dev_kfree_skb(entry->skb);
@@ -524,84 +493,53 @@ static int rt2800usb_get_tx_data_len(struct queue_entry *entry)
524 return length; 493 return length;
525} 494}
526 495
527static void rt2800usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
528 const enum data_queue_qid queue)
529{
530 u32 reg;
531
532 if (queue != QID_BEACON) {
533 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
534 return;
535 }
536
537 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
538 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
539 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
540 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
541 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
542 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
543 }
544}
545
546/* 496/*
547 * RX control handlers 497 * RX control handlers
548 */ 498 */
549static void rt2800usb_fill_rxdone(struct queue_entry *entry, 499static void rt2800usb_fill_rxdone(struct queue_entry *entry,
550 struct rxdone_entry_desc *rxdesc) 500 struct rxdone_entry_desc *rxdesc)
551{ 501{
552 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
553 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 502 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
554 __le32 *rxi = (__le32 *)entry->skb->data; 503 __le32 *rxi = (__le32 *)entry->skb->data;
555 __le32 *rxwi;
556 __le32 *rxd; 504 __le32 *rxd;
557 u32 rxi0; 505 u32 word;
558 u32 rxwi0;
559 u32 rxwi1;
560 u32 rxwi2;
561 u32 rxwi3;
562 u32 rxd0;
563 int rx_pkt_len; 506 int rx_pkt_len;
564 507
565 /* 508 /*
509 * Copy descriptor to the skbdesc->desc buffer, making it safe from
510 * moving of frame data in rt2x00usb.
511 */
512 memcpy(skbdesc->desc, rxi, skbdesc->desc_len);
513
514 /*
566 * RX frame format is : 515 * RX frame format is :
567 * | RXINFO | RXWI | header | L2 pad | payload | pad | RXD | USB pad | 516 * | RXINFO | RXWI | header | L2 pad | payload | pad | RXD | USB pad |
568 * |<------------ rx_pkt_len -------------->| 517 * |<------------ rx_pkt_len -------------->|
569 */ 518 */
570 rt2x00_desc_read(rxi, 0, &rxi0); 519 rt2x00_desc_read(rxi, 0, &word);
571 rx_pkt_len = rt2x00_get_field32(rxi0, RXINFO_W0_USB_DMA_RX_PKT_LEN); 520 rx_pkt_len = rt2x00_get_field32(word, RXINFO_W0_USB_DMA_RX_PKT_LEN);
572
573 rxwi = (__le32 *)(entry->skb->data + RXINFO_DESC_SIZE);
574 521
575 /* 522 /*
576 * FIXME : we need to check for rx_pkt_len validity 523 * Remove the RXINFO structure from the sbk.
577 */ 524 */
578 rxd = (__le32 *)(entry->skb->data + RXINFO_DESC_SIZE + rx_pkt_len); 525 skb_pull(entry->skb, RXINFO_DESC_SIZE);
579 526
580 /* 527 /*
581 * Copy descriptor to the skbdesc->desc buffer, making it safe from 528 * FIXME: we need to check for rx_pkt_len validity
582 * moving of frame data in rt2x00usb.
583 */ 529 */
584 memcpy(skbdesc->desc, rxi, skbdesc->desc_len); 530 rxd = (__le32 *)(entry->skb->data + rx_pkt_len);
585 531
586 /* 532 /*
587 * It is now safe to read the descriptor on all architectures. 533 * It is now safe to read the descriptor on all architectures.
588 */ 534 */
589 rt2x00_desc_read(rxwi, 0, &rxwi0); 535 rt2x00_desc_read(rxd, 0, &word);
590 rt2x00_desc_read(rxwi, 1, &rxwi1);
591 rt2x00_desc_read(rxwi, 2, &rxwi2);
592 rt2x00_desc_read(rxwi, 3, &rxwi3);
593 rt2x00_desc_read(rxd, 0, &rxd0);
594 536
595 if (rt2x00_get_field32(rxd0, RXD_W0_CRC_ERROR)) 537 if (rt2x00_get_field32(word, RXD_W0_CRC_ERROR))
596 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 538 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
597 539
598 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) { 540 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W0_CIPHER_ERROR);
599 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
600 rxdesc->cipher_status =
601 rt2x00_get_field32(rxd0, RXD_W0_CIPHER_ERROR);
602 }
603 541
604 if (rt2x00_get_field32(rxd0, RXD_W0_DECRYPTED)) { 542 if (rt2x00_get_field32(word, RXD_W0_DECRYPTED)) {
605 /* 543 /*
606 * Hardware has stripped IV/EIV data from 802.11 frame during 544 * Hardware has stripped IV/EIV data from 802.11 frame during
607 * decryption. Unfortunately the descriptor doesn't contain 545 * decryption. Unfortunately the descriptor doesn't contain
@@ -616,45 +554,21 @@ static void rt2800usb_fill_rxdone(struct queue_entry *entry,
616 rxdesc->flags |= RX_FLAG_MMIC_ERROR; 554 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
617 } 555 }
618 556
619 if (rt2x00_get_field32(rxd0, RXD_W0_MY_BSS)) 557 if (rt2x00_get_field32(word, RXD_W0_MY_BSS))
620 rxdesc->dev_flags |= RXDONE_MY_BSS; 558 rxdesc->dev_flags |= RXDONE_MY_BSS;
621 559
622 if (rt2x00_get_field32(rxd0, RXD_W0_L2PAD)) 560 if (rt2x00_get_field32(word, RXD_W0_L2PAD))
623 rxdesc->dev_flags |= RXDONE_L2PAD; 561 rxdesc->dev_flags |= RXDONE_L2PAD;
624 562
625 if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
626 rxdesc->flags |= RX_FLAG_SHORT_GI;
627
628 if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
629 rxdesc->flags |= RX_FLAG_40MHZ;
630
631 /* 563 /*
632 * Detect RX rate, always use MCS as signal type. 564 * Remove RXD descriptor from end of buffer.
633 */ 565 */
634 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS; 566 skb_trim(entry->skb, rx_pkt_len);
635 rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
636 rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
637 567
638 /* 568 /*
639 * Mask of 0x8 bit to remove the short preamble flag. 569 * Process the RXWI structure.
640 */ 570 */
641 if (rxdesc->rate_mode == RATE_MODE_CCK) 571 rt2800_process_rxwi(entry->skb, rxdesc);
642 rxdesc->signal &= ~0x8;
643
644 rxdesc->rssi =
645 (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
646 rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
647
648 rxdesc->noise =
649 (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
650 rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
651
652 rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
653
654 /*
655 * Remove RXWI descriptor from start of buffer.
656 */
657 skb_pull(entry->skb, skbdesc->desc_len);
658} 572}
659 573
660/* 574/*
@@ -747,7 +661,7 @@ static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
747 .write_tx_data = rt2x00usb_write_tx_data, 661 .write_tx_data = rt2x00usb_write_tx_data,
748 .write_beacon = rt2800usb_write_beacon, 662 .write_beacon = rt2800usb_write_beacon,
749 .get_tx_data_len = rt2800usb_get_tx_data_len, 663 .get_tx_data_len = rt2800usb_get_tx_data_len,
750 .kick_tx_queue = rt2800usb_kick_tx_queue, 664 .kick_tx_queue = rt2x00usb_kick_tx_queue,
751 .kill_tx_queue = rt2x00usb_kill_tx_queue, 665 .kill_tx_queue = rt2x00usb_kill_tx_queue,
752 .fill_rxdone = rt2800usb_fill_rxdone, 666 .fill_rxdone = rt2800usb_fill_rxdone,
753 .config_shared_key = rt2800_config_shared_key, 667 .config_shared_key = rt2800_config_shared_key,
@@ -806,6 +720,10 @@ static struct usb_device_id rt2800usb_device_table[] = {
806 { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) }, 720 { USB_DEVICE(0x07b8, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
807 { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) }, 721 { USB_DEVICE(0x07b8, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
808 { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) }, 722 { USB_DEVICE(0x1482, 0x3c09), USB_DEVICE_DATA(&rt2800usb_ops) },
723 /* Allwin */
724 { USB_DEVICE(0x8516, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
725 { USB_DEVICE(0x8516, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
726 { USB_DEVICE(0x8516, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
809 /* Amit */ 727 /* Amit */
810 { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) }, 728 { USB_DEVICE(0x15c5, 0x0008), USB_DEVICE_DATA(&rt2800usb_ops) },
811 /* Askey */ 729 /* Askey */
@@ -841,13 +759,18 @@ static struct usb_device_id rt2800usb_device_table[] = {
841 { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) }, 759 { USB_DEVICE(0x7392, 0x7717), USB_DEVICE_DATA(&rt2800usb_ops) },
842 { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) }, 760 { USB_DEVICE(0x7392, 0x7718), USB_DEVICE_DATA(&rt2800usb_ops) },
843 /* EnGenius */ 761 /* EnGenius */
844 { USB_DEVICE(0X1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) }, 762 { USB_DEVICE(0x1740, 0x9701), USB_DEVICE_DATA(&rt2800usb_ops) },
845 { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) }, 763 { USB_DEVICE(0x1740, 0x9702), USB_DEVICE_DATA(&rt2800usb_ops) },
846 /* Gigabyte */ 764 /* Gigabyte */
847 { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) }, 765 { USB_DEVICE(0x1044, 0x800b), USB_DEVICE_DATA(&rt2800usb_ops) },
848 /* Hawking */ 766 /* Hawking */
849 { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) }, 767 { USB_DEVICE(0x0e66, 0x0001), USB_DEVICE_DATA(&rt2800usb_ops) },
850 { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) }, 768 { USB_DEVICE(0x0e66, 0x0003), USB_DEVICE_DATA(&rt2800usb_ops) },
769 { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
770 { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
771 { USB_DEVICE(0x0e66, 0x0013), USB_DEVICE_DATA(&rt2800usb_ops) },
772 { USB_DEVICE(0x0e66, 0x0017), USB_DEVICE_DATA(&rt2800usb_ops) },
773 { USB_DEVICE(0x0e66, 0x0018), USB_DEVICE_DATA(&rt2800usb_ops) },
851 /* Linksys */ 774 /* Linksys */
852 { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) }, 775 { USB_DEVICE(0x1737, 0x0070), USB_DEVICE_DATA(&rt2800usb_ops) },
853 { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) }, 776 { USB_DEVICE(0x1737, 0x0071), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -876,6 +799,8 @@ static struct usb_device_id rt2800usb_device_table[] = {
876 { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) }, 799 { USB_DEVICE(0x0df6, 0x002c), USB_DEVICE_DATA(&rt2800usb_ops) },
877 { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) }, 800 { USB_DEVICE(0x0df6, 0x002d), USB_DEVICE_DATA(&rt2800usb_ops) },
878 { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) }, 801 { USB_DEVICE(0x0df6, 0x0039), USB_DEVICE_DATA(&rt2800usb_ops) },
802 { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
803 { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
879 { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) }, 804 { USB_DEVICE(0x0df6, 0x003f), USB_DEVICE_DATA(&rt2800usb_ops) },
880 /* SMC */ 805 /* SMC */
881 { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) }, 806 { USB_DEVICE(0x083a, 0x6618), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -905,8 +830,17 @@ static struct usb_device_id rt2800usb_device_table[] = {
905 { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) }, 830 { USB_DEVICE(0x07b8, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
906 /* AirTies */ 831 /* AirTies */
907 { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) }, 832 { USB_DEVICE(0x1eda, 0x2310), USB_DEVICE_DATA(&rt2800usb_ops) },
833 /* Allwin */
834 { USB_DEVICE(0x8516, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
835 { USB_DEVICE(0x8516, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
836 { USB_DEVICE(0x8516, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
837 /* ASUS */
838 { USB_DEVICE(0x0b05, 0x1784), USB_DEVICE_DATA(&rt2800usb_ops) },
908 /* AzureWave */ 839 /* AzureWave */
909 { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) }, 840 { USB_DEVICE(0x13d3, 0x3273), USB_DEVICE_DATA(&rt2800usb_ops) },
841 { USB_DEVICE(0x13d3, 0x3305), USB_DEVICE_DATA(&rt2800usb_ops) },
842 { USB_DEVICE(0x13d3, 0x3307), USB_DEVICE_DATA(&rt2800usb_ops) },
843 { USB_DEVICE(0x13d3, 0x3321), USB_DEVICE_DATA(&rt2800usb_ops) },
910 /* Conceptronic */ 844 /* Conceptronic */
911 { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) }, 845 { USB_DEVICE(0x14b2, 0x3c12), USB_DEVICE_DATA(&rt2800usb_ops) },
912 /* Corega */ 846 /* Corega */
@@ -916,20 +850,46 @@ static struct usb_device_id rt2800usb_device_table[] = {
916 { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) }, 850 { USB_DEVICE(0x07d1, 0x3c0d), USB_DEVICE_DATA(&rt2800usb_ops) },
917 { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) }, 851 { USB_DEVICE(0x07d1, 0x3c0e), USB_DEVICE_DATA(&rt2800usb_ops) },
918 { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) }, 852 { USB_DEVICE(0x07d1, 0x3c0f), USB_DEVICE_DATA(&rt2800usb_ops) },
853 { USB_DEVICE(0x07d1, 0x3c16), USB_DEVICE_DATA(&rt2800usb_ops) },
854 /* Draytek */
855 { USB_DEVICE(0x07fa, 0x7712), USB_DEVICE_DATA(&rt2800usb_ops) },
919 /* Edimax */ 856 /* Edimax */
920 { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) }, 857 { USB_DEVICE(0x7392, 0x7711), USB_DEVICE_DATA(&rt2800usb_ops) },
921 /* Encore */ 858 /* Encore */
922 { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) }, 859 { USB_DEVICE(0x203d, 0x1480), USB_DEVICE_DATA(&rt2800usb_ops) },
860 { USB_DEVICE(0x203d, 0x14a9), USB_DEVICE_DATA(&rt2800usb_ops) },
923 /* EnGenius */ 861 /* EnGenius */
924 { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) }, 862 { USB_DEVICE(0x1740, 0x9703), USB_DEVICE_DATA(&rt2800usb_ops) },
925 { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) }, 863 { USB_DEVICE(0x1740, 0x9705), USB_DEVICE_DATA(&rt2800usb_ops) },
926 { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) }, 864 { USB_DEVICE(0x1740, 0x9706), USB_DEVICE_DATA(&rt2800usb_ops) },
865 { USB_DEVICE(0x1740, 0x9707), USB_DEVICE_DATA(&rt2800usb_ops) },
866 { USB_DEVICE(0x1740, 0x9708), USB_DEVICE_DATA(&rt2800usb_ops) },
867 { USB_DEVICE(0x1740, 0x9709), USB_DEVICE_DATA(&rt2800usb_ops) },
927 /* Gigabyte */ 868 /* Gigabyte */
928 { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) }, 869 { USB_DEVICE(0x1044, 0x800d), USB_DEVICE_DATA(&rt2800usb_ops) },
929 /* I-O DATA */ 870 /* I-O DATA */
930 { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) }, 871 { USB_DEVICE(0x04bb, 0x0945), USB_DEVICE_DATA(&rt2800usb_ops) },
872 { USB_DEVICE(0x04bb, 0x0947), USB_DEVICE_DATA(&rt2800usb_ops) },
873 { USB_DEVICE(0x04bb, 0x0948), USB_DEVICE_DATA(&rt2800usb_ops) },
874 /* Logitec */
875 { USB_DEVICE(0x0789, 0x0166), USB_DEVICE_DATA(&rt2800usb_ops) },
931 /* MSI */ 876 /* MSI */
932 { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) }, 877 { USB_DEVICE(0x0db0, 0x3820), USB_DEVICE_DATA(&rt2800usb_ops) },
878 { USB_DEVICE(0x0db0, 0x3821), USB_DEVICE_DATA(&rt2800usb_ops) },
879 { USB_DEVICE(0x0db0, 0x3822), USB_DEVICE_DATA(&rt2800usb_ops) },
880 { USB_DEVICE(0x0db0, 0x3870), USB_DEVICE_DATA(&rt2800usb_ops) },
881 { USB_DEVICE(0x0db0, 0x3871), USB_DEVICE_DATA(&rt2800usb_ops) },
882 { USB_DEVICE(0x0db0, 0x821a), USB_DEVICE_DATA(&rt2800usb_ops) },
883 { USB_DEVICE(0x0db0, 0x822a), USB_DEVICE_DATA(&rt2800usb_ops) },
884 { USB_DEVICE(0x0db0, 0x822b), USB_DEVICE_DATA(&rt2800usb_ops) },
885 { USB_DEVICE(0x0db0, 0x822c), USB_DEVICE_DATA(&rt2800usb_ops) },
886 { USB_DEVICE(0x0db0, 0x870a), USB_DEVICE_DATA(&rt2800usb_ops) },
887 { USB_DEVICE(0x0db0, 0x871a), USB_DEVICE_DATA(&rt2800usb_ops) },
888 { USB_DEVICE(0x0db0, 0x871b), USB_DEVICE_DATA(&rt2800usb_ops) },
889 { USB_DEVICE(0x0db0, 0x871c), USB_DEVICE_DATA(&rt2800usb_ops) },
890 { USB_DEVICE(0x0db0, 0x899a), USB_DEVICE_DATA(&rt2800usb_ops) },
891 /* Para */
892 { USB_DEVICE(0x20b8, 0x8888), USB_DEVICE_DATA(&rt2800usb_ops) },
933 /* Pegatron */ 893 /* Pegatron */
934 { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) }, 894 { USB_DEVICE(0x1d4d, 0x000c), USB_DEVICE_DATA(&rt2800usb_ops) },
935 { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) }, 895 { USB_DEVICE(0x1d4d, 0x000e), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -944,14 +904,22 @@ static struct usb_device_id rt2800usb_device_table[] = {
944 { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) }, 904 { USB_DEVICE(0x148f, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
945 /* Sitecom */ 905 /* Sitecom */
946 { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) }, 906 { USB_DEVICE(0x0df6, 0x003e), USB_DEVICE_DATA(&rt2800usb_ops) },
907 { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
947 { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) }, 908 { USB_DEVICE(0x0df6, 0x0042), USB_DEVICE_DATA(&rt2800usb_ops) },
909 { USB_DEVICE(0x0df6, 0x0047), USB_DEVICE_DATA(&rt2800usb_ops) },
910 { USB_DEVICE(0x0df6, 0x0048), USB_DEVICE_DATA(&rt2800usb_ops) },
948 /* SMC */ 911 /* SMC */
949 { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) }, 912 { USB_DEVICE(0x083a, 0x7511), USB_DEVICE_DATA(&rt2800usb_ops) },
913 { USB_DEVICE(0x083a, 0xa701), USB_DEVICE_DATA(&rt2800usb_ops) },
914 { USB_DEVICE(0x083a, 0xa702), USB_DEVICE_DATA(&rt2800usb_ops) },
915 { USB_DEVICE(0x083a, 0xa703), USB_DEVICE_DATA(&rt2800usb_ops) },
950 /* Zinwell */ 916 /* Zinwell */
951 { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) }, 917 { USB_DEVICE(0x5a57, 0x0283), USB_DEVICE_DATA(&rt2800usb_ops) },
952 { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) }, 918 { USB_DEVICE(0x5a57, 0x5257), USB_DEVICE_DATA(&rt2800usb_ops) },
953#endif 919#endif
954#ifdef CONFIG_RT2800USB_RT35XX 920#ifdef CONFIG_RT2800USB_RT35XX
921 /* Allwin */
922 { USB_DEVICE(0x8516, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
955 /* Askey */ 923 /* Askey */
956 { USB_DEVICE(0x1690, 0x0744), USB_DEVICE_DATA(&rt2800usb_ops) }, 924 { USB_DEVICE(0x1690, 0x0744), USB_DEVICE_DATA(&rt2800usb_ops) },
957 /* Cisco */ 925 /* Cisco */
@@ -966,37 +934,27 @@ static struct usb_device_id rt2800usb_device_table[] = {
966 { USB_DEVICE(0x148f, 0x8070), USB_DEVICE_DATA(&rt2800usb_ops) }, 934 { USB_DEVICE(0x148f, 0x8070), USB_DEVICE_DATA(&rt2800usb_ops) },
967 /* Sitecom */ 935 /* Sitecom */
968 { USB_DEVICE(0x0df6, 0x0041), USB_DEVICE_DATA(&rt2800usb_ops) }, 936 { USB_DEVICE(0x0df6, 0x0041), USB_DEVICE_DATA(&rt2800usb_ops) },
937 { USB_DEVICE(0x0df6, 0x0050), USB_DEVICE_DATA(&rt2800usb_ops) },
969 /* Zinwell */ 938 /* Zinwell */
970 { USB_DEVICE(0x5a57, 0x0284), USB_DEVICE_DATA(&rt2800usb_ops) }, 939 { USB_DEVICE(0x5a57, 0x0284), USB_DEVICE_DATA(&rt2800usb_ops) },
971#endif 940#endif
972#ifdef CONFIG_RT2800USB_UNKNOWN 941#ifdef CONFIG_RT2800USB_UNKNOWN
973 /* 942 /*
974 * Unclear what kind of devices these are (they aren't supported by the 943 * Unclear what kind of devices these are (they aren't supported by the
975 * vendor driver). 944 * vendor linux driver).
976 */ 945 */
977 /* Allwin */
978 { USB_DEVICE(0x8516, 0x2070), USB_DEVICE_DATA(&rt2800usb_ops) },
979 { USB_DEVICE(0x8516, 0x2770), USB_DEVICE_DATA(&rt2800usb_ops) },
980 { USB_DEVICE(0x8516, 0x2870), USB_DEVICE_DATA(&rt2800usb_ops) },
981 { USB_DEVICE(0x8516, 0x3070), USB_DEVICE_DATA(&rt2800usb_ops) },
982 { USB_DEVICE(0x8516, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
983 { USB_DEVICE(0x8516, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
984 { USB_DEVICE(0x8516, 0x3572), USB_DEVICE_DATA(&rt2800usb_ops) },
985 /* Amigo */ 946 /* Amigo */
986 { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) }, 947 { USB_DEVICE(0x0e0b, 0x9031), USB_DEVICE_DATA(&rt2800usb_ops) },
987 { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) }, 948 { USB_DEVICE(0x0e0b, 0x9041), USB_DEVICE_DATA(&rt2800usb_ops) },
988 /* Askey */
989 { USB_DEVICE(0x0930, 0x0a07), USB_DEVICE_DATA(&rt2800usb_ops) },
990 /* ASUS */ 949 /* ASUS */
991 { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) }, 950 { USB_DEVICE(0x0b05, 0x1760), USB_DEVICE_DATA(&rt2800usb_ops) },
992 { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) }, 951 { USB_DEVICE(0x0b05, 0x1761), USB_DEVICE_DATA(&rt2800usb_ops) },
993 { USB_DEVICE(0x0b05, 0x1784), USB_DEVICE_DATA(&rt2800usb_ops) },
994 { USB_DEVICE(0x0b05, 0x1790), USB_DEVICE_DATA(&rt2800usb_ops) }, 952 { USB_DEVICE(0x0b05, 0x1790), USB_DEVICE_DATA(&rt2800usb_ops) },
995 { USB_DEVICE(0x1761, 0x0b05), USB_DEVICE_DATA(&rt2800usb_ops) }, 953 { USB_DEVICE(0x1761, 0x0b05), USB_DEVICE_DATA(&rt2800usb_ops) },
996 /* AzureWave */ 954 /* AzureWave */
997 { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) }, 955 { USB_DEVICE(0x13d3, 0x3262), USB_DEVICE_DATA(&rt2800usb_ops) },
998 { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) }, 956 { USB_DEVICE(0x13d3, 0x3284), USB_DEVICE_DATA(&rt2800usb_ops) },
999 { USB_DEVICE(0x13d3, 0x3305), USB_DEVICE_DATA(&rt2800usb_ops) }, 957 { USB_DEVICE(0x13d3, 0x3322), USB_DEVICE_DATA(&rt2800usb_ops) },
1000 /* Belkin */ 958 /* Belkin */
1001 { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) }, 959 { USB_DEVICE(0x050d, 0x825a), USB_DEVICE_DATA(&rt2800usb_ops) },
1002 /* Buffalo */ 960 /* Buffalo */
@@ -1015,24 +973,13 @@ static struct usb_device_id rt2800usb_device_table[] = {
1015 { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) }, 973 { USB_DEVICE(0x07d1, 0x3c0b), USB_DEVICE_DATA(&rt2800usb_ops) },
1016 { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) }, 974 { USB_DEVICE(0x07d1, 0x3c13), USB_DEVICE_DATA(&rt2800usb_ops) },
1017 { USB_DEVICE(0x07d1, 0x3c15), USB_DEVICE_DATA(&rt2800usb_ops) }, 975 { USB_DEVICE(0x07d1, 0x3c15), USB_DEVICE_DATA(&rt2800usb_ops) },
1018 { USB_DEVICE(0x07d1, 0x3c16), USB_DEVICE_DATA(&rt2800usb_ops) }, 976 { USB_DEVICE(0x07d1, 0x3c17), USB_DEVICE_DATA(&rt2800usb_ops) },
1019 /* Encore */ 977 /* Encore */
1020 { USB_DEVICE(0x203d, 0x14a1), USB_DEVICE_DATA(&rt2800usb_ops) }, 978 { USB_DEVICE(0x203d, 0x14a1), USB_DEVICE_DATA(&rt2800usb_ops) },
1021 { USB_DEVICE(0x203d, 0x14a9), USB_DEVICE_DATA(&rt2800usb_ops) },
1022 /* EnGenius */
1023 { USB_DEVICE(0x1740, 0x9707), USB_DEVICE_DATA(&rt2800usb_ops) },
1024 { USB_DEVICE(0x1740, 0x9708), USB_DEVICE_DATA(&rt2800usb_ops) },
1025 { USB_DEVICE(0x1740, 0x9709), USB_DEVICE_DATA(&rt2800usb_ops) },
1026 /* Gemtek */ 979 /* Gemtek */
1027 { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) }, 980 { USB_DEVICE(0x15a9, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
1028 /* Gigabyte */ 981 /* Gigabyte */
1029 { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) }, 982 { USB_DEVICE(0x1044, 0x800c), USB_DEVICE_DATA(&rt2800usb_ops) },
1030 /* Hawking */
1031 { USB_DEVICE(0x0e66, 0x0009), USB_DEVICE_DATA(&rt2800usb_ops) },
1032 { USB_DEVICE(0x0e66, 0x000b), USB_DEVICE_DATA(&rt2800usb_ops) },
1033 /* I-O DATA */
1034 { USB_DEVICE(0x04bb, 0x0947), USB_DEVICE_DATA(&rt2800usb_ops) },
1035 { USB_DEVICE(0x04bb, 0x0948), USB_DEVICE_DATA(&rt2800usb_ops) },
1036 /* LevelOne */ 983 /* LevelOne */
1037 { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) }, 984 { USB_DEVICE(0x1740, 0x0605), USB_DEVICE_DATA(&rt2800usb_ops) },
1038 { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) }, 985 { USB_DEVICE(0x1740, 0x0615), USB_DEVICE_DATA(&rt2800usb_ops) },
@@ -1042,43 +989,23 @@ static struct usb_device_id rt2800usb_device_table[] = {
1042 { USB_DEVICE(0x1737, 0x0079), USB_DEVICE_DATA(&rt2800usb_ops) }, 989 { USB_DEVICE(0x1737, 0x0079), USB_DEVICE_DATA(&rt2800usb_ops) },
1043 /* Motorola */ 990 /* Motorola */
1044 { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) }, 991 { USB_DEVICE(0x100d, 0x9032), USB_DEVICE_DATA(&rt2800usb_ops) },
1045 /* MSI */
1046 { USB_DEVICE(0x0db0, 0x3821), USB_DEVICE_DATA(&rt2800usb_ops) },
1047 { USB_DEVICE(0x0db0, 0x3822), USB_DEVICE_DATA(&rt2800usb_ops) },
1048 { USB_DEVICE(0x0db0, 0x3870), USB_DEVICE_DATA(&rt2800usb_ops) },
1049 { USB_DEVICE(0x0db0, 0x3871), USB_DEVICE_DATA(&rt2800usb_ops) },
1050 { USB_DEVICE(0x0db0, 0x821a), USB_DEVICE_DATA(&rt2800usb_ops) },
1051 { USB_DEVICE(0x0db0, 0x822a), USB_DEVICE_DATA(&rt2800usb_ops) },
1052 { USB_DEVICE(0x0db0, 0x870a), USB_DEVICE_DATA(&rt2800usb_ops) },
1053 { USB_DEVICE(0x0db0, 0x871a), USB_DEVICE_DATA(&rt2800usb_ops) },
1054 { USB_DEVICE(0x0db0, 0x899a), USB_DEVICE_DATA(&rt2800usb_ops) },
1055 /* Ovislink */ 992 /* Ovislink */
993 { USB_DEVICE(0x1b75, 0x3071), USB_DEVICE_DATA(&rt2800usb_ops) },
1056 { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) }, 994 { USB_DEVICE(0x1b75, 0x3072), USB_DEVICE_DATA(&rt2800usb_ops) },
1057 /* Para */
1058 { USB_DEVICE(0x20b8, 0x8888), USB_DEVICE_DATA(&rt2800usb_ops) },
1059 /* Pegatron */ 995 /* Pegatron */
1060 { USB_DEVICE(0x05a6, 0x0101), USB_DEVICE_DATA(&rt2800usb_ops) }, 996 { USB_DEVICE(0x05a6, 0x0101), USB_DEVICE_DATA(&rt2800usb_ops) },
1061 { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) }, 997 { USB_DEVICE(0x1d4d, 0x0002), USB_DEVICE_DATA(&rt2800usb_ops) },
1062 { USB_DEVICE(0x1d4d, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) }, 998 { USB_DEVICE(0x1d4d, 0x0010), USB_DEVICE_DATA(&rt2800usb_ops) },
999 { USB_DEVICE(0x1d4d, 0x0011), USB_DEVICE_DATA(&rt2800usb_ops) },
1063 /* Planex */ 1000 /* Planex */
1064 { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) }, 1001 { USB_DEVICE(0x2019, 0xab24), USB_DEVICE_DATA(&rt2800usb_ops) },
1065 /* Qcom */ 1002 /* Qcom */
1066 { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) }, 1003 { USB_DEVICE(0x18e8, 0x6259), USB_DEVICE_DATA(&rt2800usb_ops) },
1067 /* Sitecom */
1068 { USB_DEVICE(0x0df6, 0x003b), USB_DEVICE_DATA(&rt2800usb_ops) },
1069 { USB_DEVICE(0x0df6, 0x003c), USB_DEVICE_DATA(&rt2800usb_ops) },
1070 { USB_DEVICE(0x0df6, 0x003d), USB_DEVICE_DATA(&rt2800usb_ops) },
1071 { USB_DEVICE(0x0df6, 0x0040), USB_DEVICE_DATA(&rt2800usb_ops) },
1072 { USB_DEVICE(0x0df6, 0x0047), USB_DEVICE_DATA(&rt2800usb_ops) },
1073 { USB_DEVICE(0x0df6, 0x0048), USB_DEVICE_DATA(&rt2800usb_ops) },
1074 { USB_DEVICE(0x0df6, 0x004a), USB_DEVICE_DATA(&rt2800usb_ops) },
1075 { USB_DEVICE(0x0df6, 0x004d), USB_DEVICE_DATA(&rt2800usb_ops) },
1076 /* SMC */ 1004 /* SMC */
1077 { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) }, 1005 { USB_DEVICE(0x083a, 0xa512), USB_DEVICE_DATA(&rt2800usb_ops) },
1078 { USB_DEVICE(0x083a, 0xa701), USB_DEVICE_DATA(&rt2800usb_ops) },
1079 { USB_DEVICE(0x083a, 0xa702), USB_DEVICE_DATA(&rt2800usb_ops) },
1080 { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) }, 1006 { USB_DEVICE(0x083a, 0xc522), USB_DEVICE_DATA(&rt2800usb_ops) },
1081 { USB_DEVICE(0x083a, 0xd522), USB_DEVICE_DATA(&rt2800usb_ops) }, 1007 { USB_DEVICE(0x083a, 0xd522), USB_DEVICE_DATA(&rt2800usb_ops) },
1008 { USB_DEVICE(0x083a, 0xf511), USB_DEVICE_DATA(&rt2800usb_ops) },
1082 /* Sweex */ 1009 /* Sweex */
1083 { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) }, 1010 { USB_DEVICE(0x177f, 0x0153), USB_DEVICE_DATA(&rt2800usb_ops) },
1084 { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) }, 1011 { USB_DEVICE(0x177f, 0x0313), USB_DEVICE_DATA(&rt2800usb_ops) },
diff --git a/drivers/net/wireless/rt2x00/rt2800usb.h b/drivers/net/wireless/rt2x00/rt2800usb.h
index d1d8ae94b4d4..2bca6a71a7f5 100644
--- a/drivers/net/wireless/rt2x00/rt2800usb.h
+++ b/drivers/net/wireless/rt2x00/rt2800usb.h
@@ -79,8 +79,6 @@
79 */ 79 */
80#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) ) 80#define TXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
81#define RXINFO_DESC_SIZE ( 1 * sizeof(__le32) ) 81#define RXINFO_DESC_SIZE ( 1 * sizeof(__le32) )
82#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
83#define RXD_DESC_SIZE ( 1 * sizeof(__le32) )
84 82
85/* 83/*
86 * TX Info structure 84 * TX Info structure
@@ -113,44 +111,6 @@
113#define RXINFO_W0_USB_DMA_RX_PKT_LEN FIELD32(0x0000ffff) 111#define RXINFO_W0_USB_DMA_RX_PKT_LEN FIELD32(0x0000ffff)
114 112
115/* 113/*
116 * RX WI structure
117 */
118
119/*
120 * Word0
121 */
122#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
123#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
124#define RXWI_W0_BSSID FIELD32(0x00001c00)
125#define RXWI_W0_UDF FIELD32(0x0000e000)
126#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
127#define RXWI_W0_TID FIELD32(0xf0000000)
128
129/*
130 * Word1
131 */
132#define RXWI_W1_FRAG FIELD32(0x0000000f)
133#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
134#define RXWI_W1_MCS FIELD32(0x007f0000)
135#define RXWI_W1_BW FIELD32(0x00800000)
136#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
137#define RXWI_W1_STBC FIELD32(0x06000000)
138#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
139
140/*
141 * Word2
142 */
143#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
144#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
145#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
146
147/*
148 * Word3
149 */
150#define RXWI_W3_SNR0 FIELD32(0x000000ff)
151#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
152
153/*
154 * RX descriptor format for RX Ring. 114 * RX descriptor format for RX Ring.
155 */ 115 */
156 116
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index d9daa9c406fa..6c1ff4c15c84 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -177,16 +177,15 @@ struct rt2x00_chip {
177#define RT2573 0x2573 177#define RT2573 0x2573
178#define RT2860 0x2860 /* 2.4GHz PCI/CB */ 178#define RT2860 0x2860 /* 2.4GHz PCI/CB */
179#define RT2870 0x2870 179#define RT2870 0x2870
180#define RT2872 0x2872 180#define RT2872 0x2872 /* WSOC */
181#define RT2880 0x2880 /* WSOC */
182#define RT2883 0x2883 /* WSOC */ 181#define RT2883 0x2883 /* WSOC */
183#define RT2890 0x2890 /* 2.4GHz PCIe */
184#define RT3052 0x3052 /* WSOC */
185#define RT3070 0x3070 182#define RT3070 0x3070
186#define RT3071 0x3071 183#define RT3071 0x3071
187#define RT3090 0x3090 /* 2.4GHz PCIe */ 184#define RT3090 0x3090 /* 2.4GHz PCIe */
188#define RT3390 0x3390 185#define RT3390 0x3390
189#define RT3572 0x3572 186#define RT3572 0x3572
187#define RT3593 0x3593 /* PCIe */
188#define RT3883 0x3883 /* WSOC */
190 189
191 u16 rf; 190 u16 rf;
192 u16 rev; 191 u16 rev;
@@ -550,8 +549,10 @@ struct rt2x00lib_ops {
550 void (*write_tx_desc) (struct rt2x00_dev *rt2x00dev, 549 void (*write_tx_desc) (struct rt2x00_dev *rt2x00dev,
551 struct sk_buff *skb, 550 struct sk_buff *skb,
552 struct txentry_desc *txdesc); 551 struct txentry_desc *txdesc);
553 int (*write_tx_data) (struct queue_entry *entry); 552 int (*write_tx_data) (struct queue_entry *entry,
554 void (*write_beacon) (struct queue_entry *entry); 553 struct txentry_desc *txdesc);
554 void (*write_beacon) (struct queue_entry *entry,
555 struct txentry_desc *txdesc);
555 int (*get_tx_data_len) (struct queue_entry *entry); 556 int (*get_tx_data_len) (struct queue_entry *entry);
556 void (*kick_tx_queue) (struct rt2x00_dev *rt2x00dev, 557 void (*kick_tx_queue) (struct rt2x00_dev *rt2x00dev,
557 const enum data_queue_qid queue); 558 const enum data_queue_qid queue);
@@ -930,12 +931,12 @@ static inline void rt2x00_set_chip(struct rt2x00_dev *rt2x00dev,
930 rt2x00dev->chip.rt, rt2x00dev->chip.rf, rt2x00dev->chip.rev); 931 rt2x00dev->chip.rt, rt2x00dev->chip.rf, rt2x00dev->chip.rev);
931} 932}
932 933
933static inline char rt2x00_rt(struct rt2x00_dev *rt2x00dev, const u16 rt) 934static inline bool rt2x00_rt(struct rt2x00_dev *rt2x00dev, const u16 rt)
934{ 935{
935 return (rt2x00dev->chip.rt == rt); 936 return (rt2x00dev->chip.rt == rt);
936} 937}
937 938
938static inline char rt2x00_rf(struct rt2x00_dev *rt2x00dev, const u16 rf) 939static inline bool rt2x00_rf(struct rt2x00_dev *rt2x00dev, const u16 rf)
939{ 940{
940 return (rt2x00dev->chip.rf == rf); 941 return (rt2x00dev->chip.rf == rf);
941} 942}
@@ -945,6 +946,24 @@ static inline u16 rt2x00_rev(struct rt2x00_dev *rt2x00dev)
945 return rt2x00dev->chip.rev; 946 return rt2x00dev->chip.rev;
946} 947}
947 948
949static inline bool rt2x00_rt_rev(struct rt2x00_dev *rt2x00dev,
950 const u16 rt, const u16 rev)
951{
952 return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) == rev);
953}
954
955static inline bool rt2x00_rt_rev_lt(struct rt2x00_dev *rt2x00dev,
956 const u16 rt, const u16 rev)
957{
958 return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) < rev);
959}
960
961static inline bool rt2x00_rt_rev_gte(struct rt2x00_dev *rt2x00dev,
962 const u16 rt, const u16 rev)
963{
964 return (rt2x00_rt(rt2x00dev, rt) && rt2x00_rev(rt2x00dev) >= rev);
965}
966
948static inline void rt2x00_set_chip_intf(struct rt2x00_dev *rt2x00dev, 967static inline void rt2x00_set_chip_intf(struct rt2x00_dev *rt2x00dev,
949 enum rt2x00_chip_intf intf) 968 enum rt2x00_chip_intf intf)
950{ 969{
diff --git a/drivers/net/wireless/rt2x00/rt2x00crypto.c b/drivers/net/wireless/rt2x00/rt2x00crypto.c
index d291c7862e10..583dacd8d241 100644
--- a/drivers/net/wireless/rt2x00/rt2x00crypto.c
+++ b/drivers/net/wireless/rt2x00/rt2x00crypto.c
@@ -128,6 +128,7 @@ void rt2x00crypto_tx_remove_iv(struct sk_buff *skb, struct txentry_desc *txdesc)
128 128
129 /* Pull buffer to correct size */ 129 /* Pull buffer to correct size */
130 skb_pull(skb, txdesc->iv_len); 130 skb_pull(skb, txdesc->iv_len);
131 txdesc->length -= txdesc->iv_len;
131 132
132 /* IV/EIV data has officially been stripped */ 133 /* IV/EIV data has officially been stripped */
133 skbdesc->flags |= SKBDESC_IV_STRIPPED; 134 skbdesc->flags |= SKBDESC_IV_STRIPPED;
diff --git a/drivers/net/wireless/rt2x00/rt2x00debug.c b/drivers/net/wireless/rt2x00/rt2x00debug.c
index 9569fb4e5bc5..e9fe93fd8042 100644
--- a/drivers/net/wireless/rt2x00/rt2x00debug.c
+++ b/drivers/net/wireless/rt2x00/rt2x00debug.c
@@ -156,10 +156,11 @@ void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
156 enum rt2x00_dump_type type, struct sk_buff *skb) 156 enum rt2x00_dump_type type, struct sk_buff *skb)
157{ 157{
158 struct rt2x00debug_intf *intf = rt2x00dev->debugfs_intf; 158 struct rt2x00debug_intf *intf = rt2x00dev->debugfs_intf;
159 struct skb_frame_desc *desc = get_skb_frame_desc(skb); 159 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
160 struct sk_buff *skbcopy; 160 struct sk_buff *skbcopy;
161 struct rt2x00dump_hdr *dump_hdr; 161 struct rt2x00dump_hdr *dump_hdr;
162 struct timeval timestamp; 162 struct timeval timestamp;
163 u32 data_len;
163 164
164 do_gettimeofday(&timestamp); 165 do_gettimeofday(&timestamp);
165 166
@@ -171,7 +172,11 @@ void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
171 return; 172 return;
172 } 173 }
173 174
174 skbcopy = alloc_skb(sizeof(*dump_hdr) + desc->desc_len + skb->len, 175 data_len = skb->len;
176 if (skbdesc->flags & SKBDESC_DESC_IN_SKB)
177 data_len -= skbdesc->desc_len;
178
179 skbcopy = alloc_skb(sizeof(*dump_hdr) + skbdesc->desc_len + data_len,
175 GFP_ATOMIC); 180 GFP_ATOMIC);
176 if (!skbcopy) { 181 if (!skbcopy) {
177 DEBUG(rt2x00dev, "Failed to copy skb for dump.\n"); 182 DEBUG(rt2x00dev, "Failed to copy skb for dump.\n");
@@ -181,18 +186,20 @@ void rt2x00debug_dump_frame(struct rt2x00_dev *rt2x00dev,
181 dump_hdr = (struct rt2x00dump_hdr *)skb_put(skbcopy, sizeof(*dump_hdr)); 186 dump_hdr = (struct rt2x00dump_hdr *)skb_put(skbcopy, sizeof(*dump_hdr));
182 dump_hdr->version = cpu_to_le32(DUMP_HEADER_VERSION); 187 dump_hdr->version = cpu_to_le32(DUMP_HEADER_VERSION);
183 dump_hdr->header_length = cpu_to_le32(sizeof(*dump_hdr)); 188 dump_hdr->header_length = cpu_to_le32(sizeof(*dump_hdr));
184 dump_hdr->desc_length = cpu_to_le32(desc->desc_len); 189 dump_hdr->desc_length = cpu_to_le32(skbdesc->desc_len);
185 dump_hdr->data_length = cpu_to_le32(skb->len); 190 dump_hdr->data_length = cpu_to_le32(data_len);
186 dump_hdr->chip_rt = cpu_to_le16(rt2x00dev->chip.rt); 191 dump_hdr->chip_rt = cpu_to_le16(rt2x00dev->chip.rt);
187 dump_hdr->chip_rf = cpu_to_le16(rt2x00dev->chip.rf); 192 dump_hdr->chip_rf = cpu_to_le16(rt2x00dev->chip.rf);
188 dump_hdr->chip_rev = cpu_to_le16(rt2x00dev->chip.rev); 193 dump_hdr->chip_rev = cpu_to_le16(rt2x00dev->chip.rev);
189 dump_hdr->type = cpu_to_le16(type); 194 dump_hdr->type = cpu_to_le16(type);
190 dump_hdr->queue_index = desc->entry->queue->qid; 195 dump_hdr->queue_index = skbdesc->entry->queue->qid;
191 dump_hdr->entry_index = desc->entry->entry_idx; 196 dump_hdr->entry_index = skbdesc->entry->entry_idx;
192 dump_hdr->timestamp_sec = cpu_to_le32(timestamp.tv_sec); 197 dump_hdr->timestamp_sec = cpu_to_le32(timestamp.tv_sec);
193 dump_hdr->timestamp_usec = cpu_to_le32(timestamp.tv_usec); 198 dump_hdr->timestamp_usec = cpu_to_le32(timestamp.tv_usec);
194 199
195 memcpy(skb_put(skbcopy, desc->desc_len), desc->desc, desc->desc_len); 200 if (!(skbdesc->flags & SKBDESC_DESC_IN_SKB))
201 memcpy(skb_put(skbcopy, skbdesc->desc_len), skbdesc->desc,
202 skbdesc->desc_len);
196 memcpy(skb_put(skbcopy, skb->len), skb->data, skb->len); 203 memcpy(skb_put(skbcopy, skb->len), skb->data, skb->len);
197 204
198 skb_queue_tail(&intf->frame_dump_skbqueue, skbcopy); 205 skb_queue_tail(&intf->frame_dump_skbqueue, skbcopy);
@@ -700,8 +707,6 @@ void rt2x00debug_register(struct rt2x00_dev *rt2x00dev)
700exit: 707exit:
701 rt2x00debug_deregister(rt2x00dev); 708 rt2x00debug_deregister(rt2x00dev);
702 ERROR(rt2x00dev, "Failed to register debug handler.\n"); 709 ERROR(rt2x00dev, "Failed to register debug handler.\n");
703
704 return;
705} 710}
706 711
707void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev) 712void rt2x00debug_deregister(struct rt2x00_dev *rt2x00dev)
diff --git a/drivers/net/wireless/rt2x00/rt2x00dev.c b/drivers/net/wireless/rt2x00/rt2x00dev.c
index eda73ba735a6..3ae468c4d760 100644
--- a/drivers/net/wireless/rt2x00/rt2x00dev.c
+++ b/drivers/net/wireless/rt2x00/rt2x00dev.c
@@ -435,7 +435,6 @@ void rt2x00lib_rxdone(struct rt2x00_dev *rt2x00dev,
435 rx_status->mactime = rxdesc.timestamp; 435 rx_status->mactime = rxdesc.timestamp;
436 rx_status->rate_idx = rate_idx; 436 rx_status->rate_idx = rate_idx;
437 rx_status->signal = rxdesc.rssi; 437 rx_status->signal = rxdesc.rssi;
438 rx_status->noise = rxdesc.noise;
439 rx_status->flag = rxdesc.flags; 438 rx_status->flag = rxdesc.flags;
440 rx_status->antenna = rt2x00dev->link.ant.active.rx; 439 rx_status->antenna = rt2x00dev->link.ant.active.rx;
441 440
diff --git a/drivers/net/wireless/rt2x00/rt2x00dump.h b/drivers/net/wireless/rt2x00/rt2x00dump.h
index 727019a748e7..ed303b423e41 100644
--- a/drivers/net/wireless/rt2x00/rt2x00dump.h
+++ b/drivers/net/wireless/rt2x00/rt2x00dump.h
@@ -62,11 +62,14 @@
62 * the tx event which has either succeeded or failed. A frame 62 * the tx event which has either succeeded or failed. A frame
63 * with this type should also have been reported with as a 63 * with this type should also have been reported with as a
64 * %DUMP_FRAME_TX frame. 64 * %DUMP_FRAME_TX frame.
65 * @DUMP_FRAME_BEACON: This beacon frame is queued for transmission to the
66 * hardware.
65 */ 67 */
66enum rt2x00_dump_type { 68enum rt2x00_dump_type {
67 DUMP_FRAME_RXDONE = 1, 69 DUMP_FRAME_RXDONE = 1,
68 DUMP_FRAME_TX = 2, 70 DUMP_FRAME_TX = 2,
69 DUMP_FRAME_TXDONE = 3, 71 DUMP_FRAME_TXDONE = 3,
72 DUMP_FRAME_BEACON = 4,
70}; 73};
71 74
72/** 75/**
diff --git a/drivers/net/wireless/rt2x00/rt2x00firmware.c b/drivers/net/wireless/rt2x00/rt2x00firmware.c
index 34beb00c4347..b818a43c4672 100644
--- a/drivers/net/wireless/rt2x00/rt2x00firmware.c
+++ b/drivers/net/wireless/rt2x00/rt2x00firmware.c
@@ -79,7 +79,7 @@ static int rt2x00lib_request_firmware(struct rt2x00_dev *rt2x00dev)
79 ERROR(rt2x00dev, 79 ERROR(rt2x00dev,
80 "Current firmware does not support detected chipset.\n"); 80 "Current firmware does not support detected chipset.\n");
81 goto exit; 81 goto exit;
82 }; 82 }
83 83
84 rt2x00dev->fw = fw; 84 rt2x00dev->fw = fw;
85 85
diff --git a/drivers/net/wireless/rt2x00/rt2x00ht.c b/drivers/net/wireless/rt2x00/rt2x00ht.c
index 1056c92143a8..5a407602ce3e 100644
--- a/drivers/net/wireless/rt2x00/rt2x00ht.c
+++ b/drivers/net/wireless/rt2x00/rt2x00ht.c
@@ -35,6 +35,7 @@ void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
35{ 35{
36 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb); 36 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(entry->skb);
37 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0]; 37 struct ieee80211_tx_rate *txrate = &tx_info->control.rates[0];
38 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)entry->skb->data;
38 39
39 if (tx_info->control.sta) 40 if (tx_info->control.sta)
40 txdesc->mpdu_density = 41 txdesc->mpdu_density =
@@ -66,4 +67,20 @@ void rt2x00ht_create_tx_descriptor(struct queue_entry *entry,
66 __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags); 67 __set_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags);
67 if (txrate->flags & IEEE80211_TX_RC_SHORT_GI) 68 if (txrate->flags & IEEE80211_TX_RC_SHORT_GI)
68 __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags); 69 __set_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags);
70
71 /*
72 * Determine IFS values
73 * - Use TXOP_BACKOFF for management frames
74 * - Use TXOP_SIFS for fragment bursts
75 * - Use TXOP_HTTXOP for everything else
76 *
77 * Note: rt2800 devices won't use CTS protection (if used)
78 * for frames not transmitted with TXOP_HTTXOP
79 */
80 if (ieee80211_is_mgmt(hdr->frame_control))
81 txdesc->txop = TXOP_BACKOFF;
82 else if (!(tx_info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT))
83 txdesc->txop = TXOP_SIFS;
84 else
85 txdesc->txop = TXOP_HTTXOP;
69} 86}
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.c b/drivers/net/wireless/rt2x00/rt2x00pci.c
index cf3f1c0c4382..a016f7ccde29 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.c
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.c
@@ -63,11 +63,10 @@ EXPORT_SYMBOL_GPL(rt2x00pci_regbusy_read);
63/* 63/*
64 * TX data handlers. 64 * TX data handlers.
65 */ 65 */
66int rt2x00pci_write_tx_data(struct queue_entry *entry) 66int rt2x00pci_write_tx_data(struct queue_entry *entry,
67 struct txentry_desc *txdesc)
67{ 68{
68 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 69 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
69 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
70 struct skb_frame_desc *skbdesc;
71 70
72 /* 71 /*
73 * This should not happen, we already checked the entry 72 * This should not happen, we already checked the entry
@@ -82,13 +81,6 @@ int rt2x00pci_write_tx_data(struct queue_entry *entry)
82 return -EINVAL; 81 return -EINVAL;
83 } 82 }
84 83
85 /*
86 * Fill in skb descriptor
87 */
88 skbdesc = get_skb_frame_desc(entry->skb);
89 skbdesc->desc = entry_priv->desc;
90 skbdesc->desc_len = entry->queue->desc_size;
91
92 return 0; 84 return 0;
93} 85}
94EXPORT_SYMBOL_GPL(rt2x00pci_write_tx_data); 86EXPORT_SYMBOL_GPL(rt2x00pci_write_tx_data);
diff --git a/drivers/net/wireless/rt2x00/rt2x00pci.h b/drivers/net/wireless/rt2x00/rt2x00pci.h
index 8149ff68410a..51bcef3839ce 100644
--- a/drivers/net/wireless/rt2x00/rt2x00pci.h
+++ b/drivers/net/wireless/rt2x00/rt2x00pci.h
@@ -92,7 +92,8 @@ int rt2x00pci_regbusy_read(struct rt2x00_dev *rt2x00dev,
92 * This function will initialize the DMA and skb descriptor 92 * This function will initialize the DMA and skb descriptor
93 * to prepare the entry for the actual TX operation. 93 * to prepare the entry for the actual TX operation.
94 */ 94 */
95int rt2x00pci_write_tx_data(struct queue_entry *entry); 95int rt2x00pci_write_tx_data(struct queue_entry *entry,
96 struct txentry_desc *txdesc);
96 97
97/** 98/**
98 * struct queue_entry_priv_pci: Per entry PCI specific information 99 * struct queue_entry_priv_pci: Per entry PCI specific information
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.c b/drivers/net/wireless/rt2x00/rt2x00queue.c
index a0bd36fc4d2e..20dbdd6fb904 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.c
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.c
@@ -334,12 +334,10 @@ static void rt2x00queue_create_tx_descriptor(struct queue_entry *entry,
334 txdesc->aifs = entry->queue->aifs; 334 txdesc->aifs = entry->queue->aifs;
335 335
336 /* 336 /*
337 * Header and alignment information. 337 * Header and frame information.
338 */ 338 */
339 txdesc->length = entry->skb->len;
339 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb); 340 txdesc->header_length = ieee80211_get_hdrlen_from_skb(entry->skb);
340 if (test_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags) &&
341 (entry->skb->len > txdesc->header_length))
342 txdesc->l2pad = L2PAD_SIZE(txdesc->header_length);
343 341
344 /* 342 /*
345 * Check whether this frame is to be acked. 343 * Check whether this frame is to be acked.
@@ -423,6 +421,7 @@ static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
423{ 421{
424 struct data_queue *queue = entry->queue; 422 struct data_queue *queue = entry->queue;
425 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; 423 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
424 enum rt2x00_dump_type dump_type;
426 425
427 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc); 426 rt2x00dev->ops->lib->write_tx_desc(rt2x00dev, entry->skb, txdesc);
428 427
@@ -430,21 +429,26 @@ static void rt2x00queue_write_tx_descriptor(struct queue_entry *entry,
430 * All processing on the frame has been completed, this means 429 * All processing on the frame has been completed, this means
431 * it is now ready to be dumped to userspace through debugfs. 430 * it is now ready to be dumped to userspace through debugfs.
432 */ 431 */
433 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_TX, entry->skb); 432 dump_type = (txdesc->queue == QID_BEACON) ?
433 DUMP_FRAME_BEACON : DUMP_FRAME_TX;
434 rt2x00debug_dump_frame(rt2x00dev, dump_type, entry->skb);
435}
436
437static void rt2x00queue_kick_tx_queue(struct queue_entry *entry,
438 struct txentry_desc *txdesc)
439{
440 struct data_queue *queue = entry->queue;
441 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
434 442
435 /* 443 /*
436 * Check if we need to kick the queue, there are however a few rules 444 * Check if we need to kick the queue, there are however a few rules
437 * 1) Don't kick beacon queue 445 * 1) Don't kick unless this is the last in frame in a burst.
438 * 2) Don't kick unless this is the last in frame in a burst.
439 * When the burst flag is set, this frame is always followed 446 * When the burst flag is set, this frame is always followed
440 * by another frame which in some way are related to eachother. 447 * by another frame which in some way are related to eachother.
441 * This is true for fragments, RTS or CTS-to-self frames. 448 * This is true for fragments, RTS or CTS-to-self frames.
442 * 3) Rule 2 can be broken when the available entries 449 * 2) Rule 1 can be broken when the available entries
443 * in the queue are less then a certain threshold. 450 * in the queue are less then a certain threshold.
444 */ 451 */
445 if (entry->queue->qid == QID_BEACON)
446 return;
447
448 if (rt2x00queue_threshold(queue) || 452 if (rt2x00queue_threshold(queue) ||
449 !test_bit(ENTRY_TXD_BURST, &txdesc->flags)) 453 !test_bit(ENTRY_TXD_BURST, &txdesc->flags))
450 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid); 454 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, queue->qid);
@@ -526,7 +530,8 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
526 * call failed. Since we always return NETDEV_TX_OK to mac80211, 530 * call failed. Since we always return NETDEV_TX_OK to mac80211,
527 * this frame will simply be dropped. 531 * this frame will simply be dropped.
528 */ 532 */
529 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry))) { 533 if (unlikely(queue->rt2x00dev->ops->lib->write_tx_data(entry,
534 &txdesc))) {
530 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags); 535 clear_bit(ENTRY_OWNER_DEVICE_DATA, &entry->flags);
531 entry->skb = NULL; 536 entry->skb = NULL;
532 return -EIO; 537 return -EIO;
@@ -539,6 +544,7 @@ int rt2x00queue_write_tx_frame(struct data_queue *queue, struct sk_buff *skb,
539 544
540 rt2x00queue_index_inc(queue, Q_INDEX); 545 rt2x00queue_index_inc(queue, Q_INDEX);
541 rt2x00queue_write_tx_descriptor(entry, &txdesc); 546 rt2x00queue_write_tx_descriptor(entry, &txdesc);
547 rt2x00queue_kick_tx_queue(entry, &txdesc);
542 548
543 return 0; 549 return 0;
544} 550}
@@ -550,7 +556,6 @@ int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
550 struct rt2x00_intf *intf = vif_to_intf(vif); 556 struct rt2x00_intf *intf = vif_to_intf(vif);
551 struct skb_frame_desc *skbdesc; 557 struct skb_frame_desc *skbdesc;
552 struct txentry_desc txdesc; 558 struct txentry_desc txdesc;
553 __le32 desc[16];
554 559
555 if (unlikely(!intf->beacon)) 560 if (unlikely(!intf->beacon))
556 return -ENOBUFS; 561 return -ENOBUFS;
@@ -583,19 +588,10 @@ int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
583 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc); 588 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
584 589
585 /* 590 /*
586 * For the descriptor we use a local array from where the
587 * driver can move it to the correct location required for
588 * the hardware.
589 */
590 memset(desc, 0, sizeof(desc));
591
592 /*
593 * Fill in skb descriptor 591 * Fill in skb descriptor
594 */ 592 */
595 skbdesc = get_skb_frame_desc(intf->beacon->skb); 593 skbdesc = get_skb_frame_desc(intf->beacon->skb);
596 memset(skbdesc, 0, sizeof(*skbdesc)); 594 memset(skbdesc, 0, sizeof(*skbdesc));
597 skbdesc->desc = desc;
598 skbdesc->desc_len = intf->beacon->queue->desc_size;
599 skbdesc->entry = intf->beacon; 595 skbdesc->entry = intf->beacon;
600 596
601 /* 597 /*
@@ -604,12 +600,9 @@ int rt2x00queue_update_beacon(struct rt2x00_dev *rt2x00dev,
604 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc); 600 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
605 601
606 /* 602 /*
607 * Send beacon to hardware. 603 * Send beacon to hardware and enable beacon genaration..
608 * Also enable beacon generation, which might have been disabled
609 * by the driver during the config_beacon() callback function.
610 */ 604 */
611 rt2x00dev->ops->lib->write_beacon(intf->beacon); 605 rt2x00dev->ops->lib->write_beacon(intf->beacon, &txdesc);
612 rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
613 606
614 mutex_unlock(&intf->beacon_skb_mutex); 607 mutex_unlock(&intf->beacon_skb_mutex);
615 608
diff --git a/drivers/net/wireless/rt2x00/rt2x00queue.h b/drivers/net/wireless/rt2x00/rt2x00queue.h
index c1e482bb37b3..f79170849add 100644
--- a/drivers/net/wireless/rt2x00/rt2x00queue.h
+++ b/drivers/net/wireless/rt2x00/rt2x00queue.h
@@ -94,12 +94,15 @@ enum data_queue_qid {
94 * mac80211 but was stripped for processing by the driver. 94 * mac80211 but was stripped for processing by the driver.
95 * @SKBDESC_NOT_MAC80211: Frame didn't originate from mac80211, 95 * @SKBDESC_NOT_MAC80211: Frame didn't originate from mac80211,
96 * don't try to pass it back. 96 * don't try to pass it back.
97 * @SKBDESC_DESC_IN_SKB: The descriptor is at the start of the
98 * skb, instead of in the desc field.
97 */ 99 */
98enum skb_frame_desc_flags { 100enum skb_frame_desc_flags {
99 SKBDESC_DMA_MAPPED_RX = 1 << 0, 101 SKBDESC_DMA_MAPPED_RX = 1 << 0,
100 SKBDESC_DMA_MAPPED_TX = 1 << 1, 102 SKBDESC_DMA_MAPPED_TX = 1 << 1,
101 SKBDESC_IV_STRIPPED = 1 << 2, 103 SKBDESC_IV_STRIPPED = 1 << 2,
102 SKBDESC_NOT_MAC80211 = 1 << 3, 104 SKBDESC_NOT_MAC80211 = 1 << 3,
105 SKBDESC_DESC_IN_SKB = 1 << 4,
103}; 106};
104 107
105/** 108/**
@@ -183,7 +186,6 @@ enum rxdone_entry_desc_flags {
183 * @timestamp: RX Timestamp 186 * @timestamp: RX Timestamp
184 * @signal: Signal of the received frame. 187 * @signal: Signal of the received frame.
185 * @rssi: RSSI of the received frame. 188 * @rssi: RSSI of the received frame.
186 * @noise: Measured noise during frame reception.
187 * @size: Data size of the received frame. 189 * @size: Data size of the received frame.
188 * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags). 190 * @flags: MAC80211 receive flags (See &enum mac80211_rx_flags).
189 * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags). 191 * @dev_flags: Ralink receive flags (See &enum rxdone_entry_desc_flags).
@@ -197,7 +199,6 @@ struct rxdone_entry_desc {
197 u64 timestamp; 199 u64 timestamp;
198 int signal; 200 int signal;
199 int rssi; 201 int rssi;
200 int noise;
201 int size; 202 int size;
202 int flags; 203 int flags;
203 int dev_flags; 204 int dev_flags;
@@ -287,8 +288,8 @@ enum txentry_desc_flags {
287 * 288 *
288 * @flags: Descriptor flags (See &enum queue_entry_flags). 289 * @flags: Descriptor flags (See &enum queue_entry_flags).
289 * @queue: Queue identification (See &enum data_queue_qid). 290 * @queue: Queue identification (See &enum data_queue_qid).
291 * @length: Length of the entire frame.
290 * @header_length: Length of 802.11 header. 292 * @header_length: Length of 802.11 header.
291 * @l2pad: Amount of padding to align 802.11 payload to 4-byte boundrary.
292 * @length_high: PLCP length high word. 293 * @length_high: PLCP length high word.
293 * @length_low: PLCP length low word. 294 * @length_low: PLCP length low word.
294 * @signal: PLCP signal. 295 * @signal: PLCP signal.
@@ -301,6 +302,7 @@ enum txentry_desc_flags {
301 * @retry_limit: Max number of retries. 302 * @retry_limit: Max number of retries.
302 * @aifs: AIFS value. 303 * @aifs: AIFS value.
303 * @ifs: IFS value. 304 * @ifs: IFS value.
305 * @txop: IFS value for 11n capable chips.
304 * @cw_min: cwmin value. 306 * @cw_min: cwmin value.
305 * @cw_max: cwmax value. 307 * @cw_max: cwmax value.
306 * @cipher: Cipher type used for encryption. 308 * @cipher: Cipher type used for encryption.
@@ -313,8 +315,8 @@ struct txentry_desc {
313 315
314 enum data_queue_qid queue; 316 enum data_queue_qid queue;
315 317
318 u16 length;
316 u16 header_length; 319 u16 header_length;
317 u16 l2pad;
318 320
319 u16 length_high; 321 u16 length_high;
320 u16 length_low; 322 u16 length_low;
@@ -330,6 +332,7 @@ struct txentry_desc {
330 short retry_limit; 332 short retry_limit;
331 short aifs; 333 short aifs;
332 short ifs; 334 short ifs;
335 short txop;
333 short cw_min; 336 short cw_min;
334 short cw_max; 337 short cw_max;
335 338
diff --git a/drivers/net/wireless/rt2x00/rt2x00reg.h b/drivers/net/wireless/rt2x00/rt2x00reg.h
index 603bfc0adaa3..b9fe94873ee0 100644
--- a/drivers/net/wireless/rt2x00/rt2x00reg.h
+++ b/drivers/net/wireless/rt2x00/rt2x00reg.h
@@ -101,6 +101,16 @@ enum ifs {
101}; 101};
102 102
103/* 103/*
104 * IFS backoff values for HT devices
105 */
106enum txop {
107 TXOP_HTTXOP = 0,
108 TXOP_PIFS = 1,
109 TXOP_SIFS = 2,
110 TXOP_BACKOFF = 3,
111};
112
113/*
104 * Cipher types for hardware encryption 114 * Cipher types for hardware encryption
105 */ 115 */
106enum cipher { 116enum cipher {
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.c b/drivers/net/wireless/rt2x00/rt2x00usb.c
index f9a7f8b17411..bd1546ba7ad2 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.c
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.c
@@ -216,12 +216,12 @@ static void rt2x00usb_interrupt_txdone(struct urb *urb)
216 rt2x00lib_txdone(entry, &txdesc); 216 rt2x00lib_txdone(entry, &txdesc);
217} 217}
218 218
219int rt2x00usb_write_tx_data(struct queue_entry *entry) 219int rt2x00usb_write_tx_data(struct queue_entry *entry,
220 struct txentry_desc *txdesc)
220{ 221{
221 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 222 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
222 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev); 223 struct usb_device *usb_dev = to_usb_device_intf(rt2x00dev->dev);
223 struct queue_entry_priv_usb *entry_priv = entry->priv_data; 224 struct queue_entry_priv_usb *entry_priv = entry->priv_data;
224 struct skb_frame_desc *skbdesc;
225 u32 length; 225 u32 length;
226 226
227 /* 227 /*
@@ -231,13 +231,6 @@ int rt2x00usb_write_tx_data(struct queue_entry *entry)
231 memset(entry->skb->data, 0, entry->queue->desc_size); 231 memset(entry->skb->data, 0, entry->queue->desc_size);
232 232
233 /* 233 /*
234 * Fill in skb descriptor
235 */
236 skbdesc = get_skb_frame_desc(entry->skb);
237 skbdesc->desc = entry->skb->data;
238 skbdesc->desc_len = entry->queue->desc_size;
239
240 /*
241 * USB devices cannot blindly pass the skb->len as the 234 * USB devices cannot blindly pass the skb->len as the
242 * length of the data to usb_fill_bulk_urb. Pass the skb 235 * length of the data to usb_fill_bulk_urb. Pass the skb
243 * to the driver to determine what the length should be. 236 * to the driver to determine what the length should be.
diff --git a/drivers/net/wireless/rt2x00/rt2x00usb.h b/drivers/net/wireless/rt2x00/rt2x00usb.h
index 3da6841b5d42..621d0f829251 100644
--- a/drivers/net/wireless/rt2x00/rt2x00usb.h
+++ b/drivers/net/wireless/rt2x00/rt2x00usb.h
@@ -376,7 +376,8 @@ void rt2x00usb_disable_radio(struct rt2x00_dev *rt2x00dev);
376 * This function will initialize the URB and skb descriptor 376 * This function will initialize the URB and skb descriptor
377 * to prepare the entry for the actual TX operation. 377 * to prepare the entry for the actual TX operation.
378 */ 378 */
379int rt2x00usb_write_tx_data(struct queue_entry *entry); 379int rt2x00usb_write_tx_data(struct queue_entry *entry,
380 struct txentry_desc *txdesc);
380 381
381/** 382/**
382 * struct queue_entry_priv_usb: Per entry USB specific information 383 * struct queue_entry_priv_usb: Per entry USB specific information
diff --git a/drivers/net/wireless/rt2x00/rt61pci.c b/drivers/net/wireless/rt2x00/rt61pci.c
index 432e75f960b7..2e3076f67535 100644
--- a/drivers/net/wireless/rt2x00/rt61pci.c
+++ b/drivers/net/wireless/rt2x00/rt61pci.c
@@ -1764,7 +1764,8 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1764 struct txentry_desc *txdesc) 1764 struct txentry_desc *txdesc)
1765{ 1765{
1766 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1766 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1767 __le32 *txd = skbdesc->desc; 1767 struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1768 __le32 *txd = entry_priv->desc;
1768 u32 word; 1769 u32 word;
1769 1770
1770 /* 1771 /*
@@ -1802,17 +1803,23 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1802 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); 1803 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1803 rt2x00_desc_write(txd, 5, word); 1804 rt2x00_desc_write(txd, 5, word);
1804 1805
1805 rt2x00_desc_read(txd, 6, &word); 1806 if (txdesc->queue != QID_BEACON) {
1806 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS, 1807 rt2x00_desc_read(txd, 6, &word);
1807 skbdesc->skb_dma); 1808 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1808 rt2x00_desc_write(txd, 6, word); 1809 skbdesc->skb_dma);
1810 rt2x00_desc_write(txd, 6, word);
1809 1811
1810 if (skbdesc->desc_len > TXINFO_SIZE) {
1811 rt2x00_desc_read(txd, 11, &word); 1812 rt2x00_desc_read(txd, 11, &word);
1812 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skb->len); 1813 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0,
1814 txdesc->length);
1813 rt2x00_desc_write(txd, 11, word); 1815 rt2x00_desc_write(txd, 11, word);
1814 } 1816 }
1815 1817
1818 /*
1819 * Writing TXD word 0 must the last to prevent a race condition with
1820 * the device, whereby the device may take hold of the TXD before we
1821 * finished updating it.
1822 */
1816 rt2x00_desc_read(txd, 0, &word); 1823 rt2x00_desc_read(txd, 0, &word);
1817 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1); 1824 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1818 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1825 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
@@ -1832,20 +1839,28 @@ static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1832 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE, 1839 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1833 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags)); 1840 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1834 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx); 1841 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1835 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len); 1842 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1836 rt2x00_set_field32(&word, TXD_W0_BURST, 1843 rt2x00_set_field32(&word, TXD_W0_BURST,
1837 test_bit(ENTRY_TXD_BURST, &txdesc->flags)); 1844 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1838 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher); 1845 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1839 rt2x00_desc_write(txd, 0, word); 1846 rt2x00_desc_write(txd, 0, word);
1847
1848 /*
1849 * Register descriptor details in skb frame descriptor.
1850 */
1851 skbdesc->desc = txd;
1852 skbdesc->desc_len =
1853 (txdesc->queue == QID_BEACON) ? TXINFO_SIZE : TXD_DESC_SIZE;
1840} 1854}
1841 1855
1842/* 1856/*
1843 * TX data initialization 1857 * TX data initialization
1844 */ 1858 */
1845static void rt61pci_write_beacon(struct queue_entry *entry) 1859static void rt61pci_write_beacon(struct queue_entry *entry,
1860 struct txentry_desc *txdesc)
1846{ 1861{
1847 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1862 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1848 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb); 1863 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1849 unsigned int beacon_base; 1864 unsigned int beacon_base;
1850 u32 reg; 1865 u32 reg;
1851 1866
@@ -1861,14 +1876,25 @@ static void rt61pci_write_beacon(struct queue_entry *entry)
1861 * Write entire beacon with descriptor to register. 1876 * Write entire beacon with descriptor to register.
1862 */ 1877 */
1863 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 1878 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1864 rt2x00pci_register_multiwrite(rt2x00dev, 1879 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
1865 beacon_base, 1880 entry_priv->desc, TXINFO_SIZE);
1866 skbdesc->desc, skbdesc->desc_len); 1881 rt2x00pci_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE,
1867 rt2x00pci_register_multiwrite(rt2x00dev,
1868 beacon_base + skbdesc->desc_len,
1869 entry->skb->data, entry->skb->len); 1882 entry->skb->data, entry->skb->len);
1870 1883
1871 /* 1884 /*
1885 * Enable beaconing again.
1886 *
1887 * For Wi-Fi faily generated beacons between participating
1888 * stations. Set TBTT phase adaptive adjustment step to 8us.
1889 */
1890 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1891
1892 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1893 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1894 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1895 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1896
1897 /*
1872 * Clean up beacon skb. 1898 * Clean up beacon skb.
1873 */ 1899 */
1874 dev_kfree_skb_any(entry->skb); 1900 dev_kfree_skb_any(entry->skb);
@@ -1880,23 +1906,6 @@ static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1880{ 1906{
1881 u32 reg; 1907 u32 reg;
1882 1908
1883 if (queue == QID_BEACON) {
1884 /*
1885 * For Wi-Fi faily generated beacons between participating
1886 * stations. Set TBTT phase adaptive adjustment step to 8us.
1887 */
1888 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1889
1890 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1891 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1892 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1893 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1894 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1895 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1896 }
1897 return;
1898 }
1899
1900 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg); 1909 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1901 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE)); 1910 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1902 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK)); 1911 rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
@@ -1968,12 +1977,8 @@ static void rt61pci_fill_rxdone(struct queue_entry *entry,
1968 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1977 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1969 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1978 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1970 1979
1971 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) { 1980 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1972 rxdesc->cipher = 1981 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1973 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1974 rxdesc->cipher_status =
1975 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1976 }
1977 1982
1978 if (rxdesc->cipher != CIPHER_NONE) { 1983 if (rxdesc->cipher != CIPHER_NONE) {
1979 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]); 1984 _rt2x00_desc_read(entry_priv->desc, 2, &rxdesc->iv[0]);
@@ -2118,6 +2123,14 @@ static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
2118 } 2123 }
2119} 2124}
2120 2125
2126static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev)
2127{
2128 struct ieee80211_conf conf = { .flags = 0 };
2129 struct rt2x00lib_conf libconf = { .conf = &conf };
2130
2131 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
2132}
2133
2121static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance) 2134static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2122{ 2135{
2123 struct rt2x00_dev *rt2x00dev = dev_instance; 2136 struct rt2x00_dev *rt2x00dev = dev_instance;
@@ -2165,6 +2178,12 @@ static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
2165 rt2x00pci_register_write(rt2x00dev, 2178 rt2x00pci_register_write(rt2x00dev,
2166 M2H_CMD_DONE_CSR, 0xffffffff); 2179 M2H_CMD_DONE_CSR, 0xffffffff);
2167 2180
2181 /*
2182 * 4 - MCU Autowakeup interrupt.
2183 */
2184 if (rt2x00_get_field32(reg_mcu, MCU_INT_SOURCE_CSR_TWAKEUP))
2185 rt61pci_wakeup(rt2x00dev);
2186
2168 return IRQ_HANDLED; 2187 return IRQ_HANDLED;
2169} 2188}
2170 2189
diff --git a/drivers/net/wireless/rt2x00/rt73usb.c b/drivers/net/wireless/rt2x00/rt73usb.c
index bb58d797fb72..e35bd19c3c5a 100644
--- a/drivers/net/wireless/rt2x00/rt73usb.c
+++ b/drivers/net/wireless/rt2x00/rt73usb.c
@@ -861,15 +861,15 @@ static void rt73usb_config_ps(struct rt2x00_dev *rt2x00dev,
861 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0, 861 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
862 USB_MODE_SLEEP, REGISTER_TIMEOUT); 862 USB_MODE_SLEEP, REGISTER_TIMEOUT);
863 } else { 863 } else {
864 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
865 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
866
867 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg); 864 rt2x00usb_register_read(rt2x00dev, MAC_CSR11, &reg);
868 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0); 865 rt2x00_set_field32(&reg, MAC_CSR11_DELAY_AFTER_TBCN, 0);
869 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0); 866 rt2x00_set_field32(&reg, MAC_CSR11_TBCN_BEFORE_WAKEUP, 0);
870 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0); 867 rt2x00_set_field32(&reg, MAC_CSR11_AUTOWAKE, 0);
871 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0); 868 rt2x00_set_field32(&reg, MAC_CSR11_WAKEUP_LATENCY, 0);
872 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg); 869 rt2x00usb_register_write(rt2x00dev, MAC_CSR11, reg);
870
871 rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE, 0,
872 USB_MODE_WAKEUP, REGISTER_TIMEOUT);
873 } 873 }
874} 874}
875 875
@@ -1441,12 +1441,38 @@ static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1441 struct txentry_desc *txdesc) 1441 struct txentry_desc *txdesc)
1442{ 1442{
1443 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb); 1443 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1444 __le32 *txd = skbdesc->desc; 1444 __le32 *txd = (__le32 *)(skb->data - TXD_DESC_SIZE);
1445 u32 word; 1445 u32 word;
1446 1446
1447 /* 1447 /*
1448 * Start writing the descriptor words. 1448 * Start writing the descriptor words.
1449 */ 1449 */
1450 rt2x00_desc_read(txd, 0, &word);
1451 rt2x00_set_field32(&word, TXD_W0_BURST,
1452 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1453 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1454 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1455 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1456 rt2x00_set_field32(&word, TXD_W0_ACK,
1457 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1458 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1459 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1460 rt2x00_set_field32(&word, TXD_W0_OFDM,
1461 (txdesc->rate_mode == RATE_MODE_OFDM));
1462 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1463 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1464 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1465 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1466 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1467 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1468 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1469 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1470 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, txdesc->length);
1471 rt2x00_set_field32(&word, TXD_W0_BURST2,
1472 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1473 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1474 rt2x00_desc_write(txd, 0, word);
1475
1450 rt2x00_desc_read(txd, 1, &word); 1476 rt2x00_desc_read(txd, 1, &word);
1451 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue); 1477 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1452 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs); 1478 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
@@ -1475,51 +1501,24 @@ static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1475 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1); 1501 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1476 rt2x00_desc_write(txd, 5, word); 1502 rt2x00_desc_write(txd, 5, word);
1477 1503
1478 rt2x00_desc_read(txd, 0, &word); 1504 /*
1479 rt2x00_set_field32(&word, TXD_W0_BURST, 1505 * Register descriptor details in skb frame descriptor.
1480 test_bit(ENTRY_TXD_BURST, &txdesc->flags)); 1506 */
1481 rt2x00_set_field32(&word, TXD_W0_VALID, 1); 1507 skbdesc->desc = txd;
1482 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG, 1508 skbdesc->desc_len = TXD_DESC_SIZE;
1483 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1484 rt2x00_set_field32(&word, TXD_W0_ACK,
1485 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1486 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1487 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1488 rt2x00_set_field32(&word, TXD_W0_OFDM,
1489 (txdesc->rate_mode == RATE_MODE_OFDM));
1490 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1491 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1492 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1493 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC,
1494 test_bit(ENTRY_TXD_ENCRYPT_MMIC, &txdesc->flags));
1495 rt2x00_set_field32(&word, TXD_W0_KEY_TABLE,
1496 test_bit(ENTRY_TXD_ENCRYPT_PAIRWISE, &txdesc->flags));
1497 rt2x00_set_field32(&word, TXD_W0_KEY_INDEX, txdesc->key_idx);
1498 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skb->len);
1499 rt2x00_set_field32(&word, TXD_W0_BURST2,
1500 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1501 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, txdesc->cipher);
1502 rt2x00_desc_write(txd, 0, word);
1503} 1509}
1504 1510
1505/* 1511/*
1506 * TX data initialization 1512 * TX data initialization
1507 */ 1513 */
1508static void rt73usb_write_beacon(struct queue_entry *entry) 1514static void rt73usb_write_beacon(struct queue_entry *entry,
1515 struct txentry_desc *txdesc)
1509{ 1516{
1510 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; 1517 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1511 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1512 unsigned int beacon_base; 1518 unsigned int beacon_base;
1513 u32 reg; 1519 u32 reg;
1514 1520
1515 /* 1521 /*
1516 * Add the descriptor in front of the skb.
1517 */
1518 skb_push(entry->skb, entry->queue->desc_size);
1519 memcpy(entry->skb->data, skbdesc->desc, skbdesc->desc_len);
1520 skbdesc->desc = entry->skb->data;
1521
1522 /*
1523 * Disable beaconing while we are reloading the beacon data, 1522 * Disable beaconing while we are reloading the beacon data,
1524 * otherwise we might be sending out invalid data. 1523 * otherwise we might be sending out invalid data.
1525 */ 1524 */
@@ -1528,6 +1527,11 @@ static void rt73usb_write_beacon(struct queue_entry *entry)
1528 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg); 1527 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1529 1528
1530 /* 1529 /*
1530 * Take the descriptor in front of the skb into account.
1531 */
1532 skb_push(entry->skb, TXD_DESC_SIZE);
1533
1534 /*
1531 * Write entire beacon with descriptor to register. 1535 * Write entire beacon with descriptor to register.
1532 */ 1536 */
1533 beacon_base = HW_BEACON_OFFSET(entry->entry_idx); 1537 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
@@ -1537,6 +1541,19 @@ static void rt73usb_write_beacon(struct queue_entry *entry)
1537 REGISTER_TIMEOUT32(entry->skb->len)); 1541 REGISTER_TIMEOUT32(entry->skb->len));
1538 1542
1539 /* 1543 /*
1544 * Enable beaconing again.
1545 *
1546 * For Wi-Fi faily generated beacons between participating stations.
1547 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1548 */
1549 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1550
1551 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1552 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1553 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1554 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1555
1556 /*
1540 * Clean up the beacon skb. 1557 * Clean up the beacon skb.
1541 */ 1558 */
1542 dev_kfree_skb(entry->skb); 1559 dev_kfree_skb(entry->skb);
@@ -1557,31 +1574,6 @@ static int rt73usb_get_tx_data_len(struct queue_entry *entry)
1557 return length; 1574 return length;
1558} 1575}
1559 1576
1560static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1561 const enum data_queue_qid queue)
1562{
1563 u32 reg;
1564
1565 if (queue != QID_BEACON) {
1566 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1567 return;
1568 }
1569
1570 /*
1571 * For Wi-Fi faily generated beacons between participating stations.
1572 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1573 */
1574 rt2x00usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1575
1576 rt2x00usb_register_read(rt2x00dev, TXRX_CSR9, &reg);
1577 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1578 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1579 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1580 rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1581 rt2x00usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1582 }
1583}
1584
1585/* 1577/*
1586 * RX control handlers 1578 * RX control handlers
1587 */ 1579 */
@@ -1645,12 +1637,8 @@ static void rt73usb_fill_rxdone(struct queue_entry *entry,
1645 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR)) 1637 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1646 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC; 1638 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1647 1639
1648 if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) { 1640 rxdesc->cipher = rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1649 rxdesc->cipher = 1641 rxdesc->cipher_status = rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1650 rt2x00_get_field32(word0, RXD_W0_CIPHER_ALG);
1651 rxdesc->cipher_status =
1652 rt2x00_get_field32(word0, RXD_W0_CIPHER_ERROR);
1653 }
1654 1642
1655 if (rxdesc->cipher != CIPHER_NONE) { 1643 if (rxdesc->cipher != CIPHER_NONE) {
1656 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]); 1644 _rt2x00_desc_read(rxd, 2, &rxdesc->iv[0]);
@@ -2266,7 +2254,7 @@ static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2266 .write_tx_data = rt2x00usb_write_tx_data, 2254 .write_tx_data = rt2x00usb_write_tx_data,
2267 .write_beacon = rt73usb_write_beacon, 2255 .write_beacon = rt73usb_write_beacon,
2268 .get_tx_data_len = rt73usb_get_tx_data_len, 2256 .get_tx_data_len = rt73usb_get_tx_data_len,
2269 .kick_tx_queue = rt73usb_kick_tx_queue, 2257 .kick_tx_queue = rt2x00usb_kick_tx_queue,
2270 .kill_tx_queue = rt2x00usb_kill_tx_queue, 2258 .kill_tx_queue = rt2x00usb_kill_tx_queue,
2271 .fill_rxdone = rt73usb_fill_rxdone, 2259 .fill_rxdone = rt73usb_fill_rxdone,
2272 .config_shared_key = rt73usb_config_shared_key, 2260 .config_shared_key = rt73usb_config_shared_key,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 17:21:39 -0500