diff options
author | Stanislaw Gruszka <stf_xl@wp.pl> | 2012-12-12 00:30:55 -0500 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2013-01-07 15:16:50 -0500 |
commit | d5374ef13ebda6ec93f0b4af6b30682ea4b14782 (patch) | |
tree | 1e5a4e95b76c91e4cd355932c3320149b6764445 /drivers/net/wireless/rt2x00 | |
parent | 48c6cc04c9ce5c38c76304377f6f7e5b1e98ca47 (diff) |
rt2800: refactor RFCSR initialization
rt2800_init_rfcsr() is too big, split RF initialization into per chip
functions. Code will change, but we should setup the same values onto
RF registers and in the same order as before.
Signed-off-by: Stanislaw Gruszka <stf_xl@wp.pl>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt2800lib.c | 795 |
1 files changed, 423 insertions, 372 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c index 12f93e42e160..0ece3537106d 100644 --- a/drivers/net/wireless/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/rt2x00/rt2800lib.c | |||
@@ -3866,6 +3866,400 @@ static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, | |||
3866 | return rfcsr24; | 3866 | return rfcsr24; |
3867 | } | 3867 | } |
3868 | 3868 | ||
3869 | static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev) | ||
3870 | { | ||
3871 | rt2800_rfcsr_write(rt2x00dev, 0, 0x50); | ||
3872 | rt2800_rfcsr_write(rt2x00dev, 1, 0x01); | ||
3873 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); | ||
3874 | rt2800_rfcsr_write(rt2x00dev, 3, 0x75); | ||
3875 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | ||
3876 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | ||
3877 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | ||
3878 | rt2800_rfcsr_write(rt2x00dev, 7, 0x50); | ||
3879 | rt2800_rfcsr_write(rt2x00dev, 8, 0x39); | ||
3880 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); | ||
3881 | rt2800_rfcsr_write(rt2x00dev, 10, 0x60); | ||
3882 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | ||
3883 | rt2800_rfcsr_write(rt2x00dev, 12, 0x75); | ||
3884 | rt2800_rfcsr_write(rt2x00dev, 13, 0x75); | ||
3885 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | ||
3886 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | ||
3887 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | ||
3888 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | ||
3889 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | ||
3890 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | ||
3891 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | ||
3892 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | ||
3893 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | ||
3894 | rt2800_rfcsr_write(rt2x00dev, 23, 0x31); | ||
3895 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); | ||
3896 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | ||
3897 | rt2800_rfcsr_write(rt2x00dev, 26, 0x25); | ||
3898 | rt2800_rfcsr_write(rt2x00dev, 27, 0x23); | ||
3899 | rt2800_rfcsr_write(rt2x00dev, 28, 0x13); | ||
3900 | rt2800_rfcsr_write(rt2x00dev, 29, 0x83); | ||
3901 | rt2800_rfcsr_write(rt2x00dev, 30, 0x00); | ||
3902 | rt2800_rfcsr_write(rt2x00dev, 31, 0x00); | ||
3903 | } | ||
3904 | |||
3905 | static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev) | ||
3906 | { | ||
3907 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | ||
3908 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | ||
3909 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | ||
3910 | rt2800_rfcsr_write(rt2x00dev, 7, 0x60); | ||
3911 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); | ||
3912 | rt2800_rfcsr_write(rt2x00dev, 10, 0x41); | ||
3913 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | ||
3914 | rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); | ||
3915 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | ||
3916 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | ||
3917 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | ||
3918 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | ||
3919 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | ||
3920 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | ||
3921 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | ||
3922 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | ||
3923 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | ||
3924 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | ||
3925 | rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); | ||
3926 | } | ||
3927 | |||
3928 | static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev) | ||
3929 | { | ||
3930 | rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); | ||
3931 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | ||
3932 | rt2800_rfcsr_write(rt2x00dev, 3, 0x08); | ||
3933 | rt2800_rfcsr_write(rt2x00dev, 4, 0x00); | ||
3934 | rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); | ||
3935 | rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); | ||
3936 | rt2800_rfcsr_write(rt2x00dev, 9, 0x02); | ||
3937 | rt2800_rfcsr_write(rt2x00dev, 10, 0x53); | ||
3938 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); | ||
3939 | rt2800_rfcsr_write(rt2x00dev, 12, 0x46); | ||
3940 | rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); | ||
3941 | rt2800_rfcsr_write(rt2x00dev, 18, 0x02); | ||
3942 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | ||
3943 | rt2800_rfcsr_write(rt2x00dev, 25, 0x83); | ||
3944 | rt2800_rfcsr_write(rt2x00dev, 26, 0x82); | ||
3945 | rt2800_rfcsr_write(rt2x00dev, 27, 0x09); | ||
3946 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | ||
3947 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); | ||
3948 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | ||
3949 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | ||
3950 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | ||
3951 | rt2800_rfcsr_write(rt2x00dev, 34, 0x05); | ||
3952 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | ||
3953 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | ||
3954 | rt2800_rfcsr_write(rt2x00dev, 38, 0x85); | ||
3955 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); | ||
3956 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); | ||
3957 | rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); | ||
3958 | rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); | ||
3959 | rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); | ||
3960 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); | ||
3961 | rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); | ||
3962 | rt2800_rfcsr_write(rt2x00dev, 46, 0x73); | ||
3963 | rt2800_rfcsr_write(rt2x00dev, 47, 0x00); | ||
3964 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | ||
3965 | rt2800_rfcsr_write(rt2x00dev, 49, 0x98); | ||
3966 | rt2800_rfcsr_write(rt2x00dev, 52, 0x38); | ||
3967 | rt2800_rfcsr_write(rt2x00dev, 53, 0x00); | ||
3968 | rt2800_rfcsr_write(rt2x00dev, 54, 0x78); | ||
3969 | rt2800_rfcsr_write(rt2x00dev, 55, 0x43); | ||
3970 | rt2800_rfcsr_write(rt2x00dev, 56, 0x02); | ||
3971 | rt2800_rfcsr_write(rt2x00dev, 57, 0x80); | ||
3972 | rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); | ||
3973 | rt2800_rfcsr_write(rt2x00dev, 59, 0x09); | ||
3974 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | ||
3975 | rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); | ||
3976 | } | ||
3977 | |||
3978 | static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev) | ||
3979 | { | ||
3980 | rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); | ||
3981 | rt2800_rfcsr_write(rt2x00dev, 1, 0x23); | ||
3982 | rt2800_rfcsr_write(rt2x00dev, 2, 0x50); | ||
3983 | rt2800_rfcsr_write(rt2x00dev, 3, 0x18); | ||
3984 | rt2800_rfcsr_write(rt2x00dev, 4, 0x00); | ||
3985 | rt2800_rfcsr_write(rt2x00dev, 5, 0x00); | ||
3986 | rt2800_rfcsr_write(rt2x00dev, 6, 0x33); | ||
3987 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | ||
3988 | rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); | ||
3989 | rt2800_rfcsr_write(rt2x00dev, 9, 0x02); | ||
3990 | rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); | ||
3991 | rt2800_rfcsr_write(rt2x00dev, 11, 0x42); | ||
3992 | rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); | ||
3993 | rt2800_rfcsr_write(rt2x00dev, 13, 0x00); | ||
3994 | rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); | ||
3995 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | ||
3996 | rt2800_rfcsr_write(rt2x00dev, 16, 0x01); | ||
3997 | rt2800_rfcsr_write(rt2x00dev, 18, 0x45); | ||
3998 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | ||
3999 | rt2800_rfcsr_write(rt2x00dev, 20, 0x00); | ||
4000 | rt2800_rfcsr_write(rt2x00dev, 21, 0x00); | ||
4001 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | ||
4002 | rt2800_rfcsr_write(rt2x00dev, 23, 0x00); | ||
4003 | rt2800_rfcsr_write(rt2x00dev, 24, 0x00); | ||
4004 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | ||
4005 | rt2800_rfcsr_write(rt2x00dev, 26, 0x00); | ||
4006 | rt2800_rfcsr_write(rt2x00dev, 27, 0x03); | ||
4007 | rt2800_rfcsr_write(rt2x00dev, 28, 0x03); | ||
4008 | rt2800_rfcsr_write(rt2x00dev, 29, 0x00); | ||
4009 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); | ||
4010 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | ||
4011 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | ||
4012 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | ||
4013 | rt2800_rfcsr_write(rt2x00dev, 34, 0x01); | ||
4014 | rt2800_rfcsr_write(rt2x00dev, 35, 0x03); | ||
4015 | rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); | ||
4016 | rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); | ||
4017 | rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); | ||
4018 | rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); | ||
4019 | rt2800_rfcsr_write(rt2x00dev, 40, 0x33); | ||
4020 | rt2800_rfcsr_write(rt2x00dev, 41, 0x5b); | ||
4021 | rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); | ||
4022 | rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); | ||
4023 | rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); | ||
4024 | rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); | ||
4025 | rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); | ||
4026 | rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); | ||
4027 | rt2800_rfcsr_write(rt2x00dev, 48, 0x14); | ||
4028 | rt2800_rfcsr_write(rt2x00dev, 49, 0x00); | ||
4029 | rt2800_rfcsr_write(rt2x00dev, 50, 0x2d); | ||
4030 | rt2800_rfcsr_write(rt2x00dev, 51, 0x7f); | ||
4031 | rt2800_rfcsr_write(rt2x00dev, 52, 0x00); | ||
4032 | rt2800_rfcsr_write(rt2x00dev, 53, 0x52); | ||
4033 | rt2800_rfcsr_write(rt2x00dev, 54, 0x1b); | ||
4034 | rt2800_rfcsr_write(rt2x00dev, 55, 0x7f); | ||
4035 | rt2800_rfcsr_write(rt2x00dev, 56, 0x00); | ||
4036 | rt2800_rfcsr_write(rt2x00dev, 57, 0x52); | ||
4037 | rt2800_rfcsr_write(rt2x00dev, 58, 0x1b); | ||
4038 | rt2800_rfcsr_write(rt2x00dev, 59, 0x00); | ||
4039 | rt2800_rfcsr_write(rt2x00dev, 60, 0x00); | ||
4040 | rt2800_rfcsr_write(rt2x00dev, 61, 0x00); | ||
4041 | rt2800_rfcsr_write(rt2x00dev, 62, 0x00); | ||
4042 | rt2800_rfcsr_write(rt2x00dev, 63, 0x00); | ||
4043 | } | ||
4044 | |||
4045 | static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev) | ||
4046 | { | ||
4047 | rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); | ||
4048 | rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); | ||
4049 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); | ||
4050 | rt2800_rfcsr_write(rt2x00dev, 3, 0x62); | ||
4051 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | ||
4052 | rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); | ||
4053 | rt2800_rfcsr_write(rt2x00dev, 6, 0x42); | ||
4054 | rt2800_rfcsr_write(rt2x00dev, 7, 0x34); | ||
4055 | rt2800_rfcsr_write(rt2x00dev, 8, 0x00); | ||
4056 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); | ||
4057 | rt2800_rfcsr_write(rt2x00dev, 10, 0x61); | ||
4058 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | ||
4059 | rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); | ||
4060 | rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); | ||
4061 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | ||
4062 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); | ||
4063 | rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); | ||
4064 | rt2800_rfcsr_write(rt2x00dev, 17, 0x94); | ||
4065 | rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); | ||
4066 | rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); | ||
4067 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); | ||
4068 | rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); | ||
4069 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | ||
4070 | rt2800_rfcsr_write(rt2x00dev, 23, 0x14); | ||
4071 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); | ||
4072 | rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); | ||
4073 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | ||
4074 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | ||
4075 | rt2800_rfcsr_write(rt2x00dev, 28, 0x41); | ||
4076 | rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); | ||
4077 | rt2800_rfcsr_write(rt2x00dev, 30, 0x20); | ||
4078 | rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); | ||
4079 | } | ||
4080 | |||
4081 | static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev) | ||
4082 | { | ||
4083 | rt2800_rfcsr_write(rt2x00dev, 0, 0x70); | ||
4084 | rt2800_rfcsr_write(rt2x00dev, 1, 0x81); | ||
4085 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); | ||
4086 | rt2800_rfcsr_write(rt2x00dev, 3, 0x02); | ||
4087 | rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); | ||
4088 | rt2800_rfcsr_write(rt2x00dev, 5, 0x05); | ||
4089 | rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); | ||
4090 | rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); | ||
4091 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); | ||
4092 | rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); | ||
4093 | rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); | ||
4094 | rt2800_rfcsr_write(rt2x00dev, 12, 0x70); | ||
4095 | rt2800_rfcsr_write(rt2x00dev, 13, 0x65); | ||
4096 | rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); | ||
4097 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); | ||
4098 | rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); | ||
4099 | rt2800_rfcsr_write(rt2x00dev, 17, 0x23); | ||
4100 | rt2800_rfcsr_write(rt2x00dev, 18, 0xac); | ||
4101 | rt2800_rfcsr_write(rt2x00dev, 19, 0x93); | ||
4102 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); | ||
4103 | rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); | ||
4104 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | ||
4105 | rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); | ||
4106 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | ||
4107 | rt2800_rfcsr_write(rt2x00dev, 25, 0x15); | ||
4108 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | ||
4109 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | ||
4110 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | ||
4111 | rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); | ||
4112 | rt2800_rfcsr_write(rt2x00dev, 30, 0x09); | ||
4113 | rt2800_rfcsr_write(rt2x00dev, 31, 0x10); | ||
4114 | } | ||
4115 | |||
4116 | static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev) | ||
4117 | { | ||
4118 | rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); | ||
4119 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | ||
4120 | rt2800_rfcsr_write(rt2x00dev, 3, 0x88); | ||
4121 | rt2800_rfcsr_write(rt2x00dev, 5, 0x10); | ||
4122 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4123 | rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); | ||
4124 | else | ||
4125 | rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); | ||
4126 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | ||
4127 | rt2800_rfcsr_write(rt2x00dev, 10, 0x53); | ||
4128 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); | ||
4129 | rt2800_rfcsr_write(rt2x00dev, 12, 0xc6); | ||
4130 | rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); | ||
4131 | rt2800_rfcsr_write(rt2x00dev, 14, 0x00); | ||
4132 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | ||
4133 | rt2800_rfcsr_write(rt2x00dev, 16, 0x00); | ||
4134 | rt2800_rfcsr_write(rt2x00dev, 18, 0x03); | ||
4135 | rt2800_rfcsr_write(rt2x00dev, 19, 0x00); | ||
4136 | |||
4137 | rt2800_rfcsr_write(rt2x00dev, 20, 0x00); | ||
4138 | rt2800_rfcsr_write(rt2x00dev, 21, 0x00); | ||
4139 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | ||
4140 | rt2800_rfcsr_write(rt2x00dev, 23, 0x00); | ||
4141 | rt2800_rfcsr_write(rt2x00dev, 24, 0x00); | ||
4142 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4143 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | ||
4144 | else | ||
4145 | rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); | ||
4146 | rt2800_rfcsr_write(rt2x00dev, 26, 0x00); | ||
4147 | rt2800_rfcsr_write(rt2x00dev, 27, 0x09); | ||
4148 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | ||
4149 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | ||
4150 | |||
4151 | rt2800_rfcsr_write(rt2x00dev, 30, 0x00); | ||
4152 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | ||
4153 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | ||
4154 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | ||
4155 | rt2800_rfcsr_write(rt2x00dev, 34, 0x07); | ||
4156 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | ||
4157 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | ||
4158 | rt2800_rfcsr_write(rt2x00dev, 37, 0x08); | ||
4159 | rt2800_rfcsr_write(rt2x00dev, 38, 0x85); | ||
4160 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); | ||
4161 | |||
4162 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4163 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); | ||
4164 | else | ||
4165 | rt2800_rfcsr_write(rt2x00dev, 40, 0x4b); | ||
4166 | rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); | ||
4167 | rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); | ||
4168 | rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); | ||
4169 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); | ||
4170 | rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); | ||
4171 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4172 | rt2800_rfcsr_write(rt2x00dev, 46, 0x73); | ||
4173 | else | ||
4174 | rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); | ||
4175 | rt2800_rfcsr_write(rt2x00dev, 47, 0x00); | ||
4176 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | ||
4177 | rt2800_rfcsr_write(rt2x00dev, 49, 0x94); | ||
4178 | |||
4179 | rt2800_rfcsr_write(rt2x00dev, 52, 0x38); | ||
4180 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4181 | rt2800_rfcsr_write(rt2x00dev, 53, 0x00); | ||
4182 | else | ||
4183 | rt2800_rfcsr_write(rt2x00dev, 53, 0x84); | ||
4184 | rt2800_rfcsr_write(rt2x00dev, 54, 0x78); | ||
4185 | rt2800_rfcsr_write(rt2x00dev, 55, 0x44); | ||
4186 | rt2800_rfcsr_write(rt2x00dev, 56, 0x22); | ||
4187 | rt2800_rfcsr_write(rt2x00dev, 57, 0x80); | ||
4188 | rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); | ||
4189 | rt2800_rfcsr_write(rt2x00dev, 59, 0x63); | ||
4190 | |||
4191 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | ||
4192 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4193 | rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); | ||
4194 | else | ||
4195 | rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); | ||
4196 | rt2800_rfcsr_write(rt2x00dev, 62, 0x00); | ||
4197 | rt2800_rfcsr_write(rt2x00dev, 63, 0x00); | ||
4198 | } | ||
4199 | |||
4200 | static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev) | ||
4201 | { | ||
4202 | rt2800_rfcsr_write(rt2x00dev, 1, 0x17); | ||
4203 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | ||
4204 | rt2800_rfcsr_write(rt2x00dev, 3, 0x88); | ||
4205 | rt2800_rfcsr_write(rt2x00dev, 5, 0x10); | ||
4206 | rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); | ||
4207 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | ||
4208 | rt2800_rfcsr_write(rt2x00dev, 10, 0x53); | ||
4209 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); | ||
4210 | rt2800_rfcsr_write(rt2x00dev, 12, 0x46); | ||
4211 | rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); | ||
4212 | rt2800_rfcsr_write(rt2x00dev, 14, 0x00); | ||
4213 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | ||
4214 | rt2800_rfcsr_write(rt2x00dev, 16, 0x00); | ||
4215 | rt2800_rfcsr_write(rt2x00dev, 18, 0x03); | ||
4216 | rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); | ||
4217 | rt2800_rfcsr_write(rt2x00dev, 20, 0x00); | ||
4218 | rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); | ||
4219 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | ||
4220 | rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); | ||
4221 | rt2800_rfcsr_write(rt2x00dev, 24, 0x44); | ||
4222 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | ||
4223 | rt2800_rfcsr_write(rt2x00dev, 26, 0x82); | ||
4224 | rt2800_rfcsr_write(rt2x00dev, 27, 0x09); | ||
4225 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | ||
4226 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | ||
4227 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); | ||
4228 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | ||
4229 | rt2800_rfcsr_write(rt2x00dev, 32, 0x20); | ||
4230 | rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); | ||
4231 | rt2800_rfcsr_write(rt2x00dev, 34, 0x07); | ||
4232 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | ||
4233 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | ||
4234 | rt2800_rfcsr_write(rt2x00dev, 37, 0x08); | ||
4235 | rt2800_rfcsr_write(rt2x00dev, 38, 0x89); | ||
4236 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); | ||
4237 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); | ||
4238 | rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); | ||
4239 | rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); | ||
4240 | rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); | ||
4241 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); | ||
4242 | rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); | ||
4243 | rt2800_rfcsr_write(rt2x00dev, 46, 0x73); | ||
4244 | rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); | ||
4245 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | ||
4246 | rt2800_rfcsr_write(rt2x00dev, 49, 0x94); | ||
4247 | rt2800_rfcsr_write(rt2x00dev, 50, 0x94); | ||
4248 | rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); | ||
4249 | rt2800_rfcsr_write(rt2x00dev, 52, 0x48); | ||
4250 | rt2800_rfcsr_write(rt2x00dev, 53, 0x44); | ||
4251 | rt2800_rfcsr_write(rt2x00dev, 54, 0x38); | ||
4252 | rt2800_rfcsr_write(rt2x00dev, 55, 0x43); | ||
4253 | rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); | ||
4254 | rt2800_rfcsr_write(rt2x00dev, 57, 0x00); | ||
4255 | rt2800_rfcsr_write(rt2x00dev, 58, 0x39); | ||
4256 | rt2800_rfcsr_write(rt2x00dev, 59, 0x07); | ||
4257 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | ||
4258 | rt2800_rfcsr_write(rt2x00dev, 61, 0x91); | ||
4259 | rt2800_rfcsr_write(rt2x00dev, 62, 0x39); | ||
4260 | rt2800_rfcsr_write(rt2x00dev, 63, 0x07); | ||
4261 | } | ||
4262 | |||
3869 | static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) | 4263 | static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) |
3870 | { | 4264 | { |
3871 | struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; | 4265 | struct rt2800_drv_data *drv_data = rt2x00dev->drv_data; |
@@ -3889,6 +4283,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) | |||
3889 | /* | 4283 | /* |
3890 | * Init RF calibration. | 4284 | * Init RF calibration. |
3891 | */ | 4285 | */ |
4286 | |||
3892 | if (rt2x00_rt(rt2x00dev, RT3290) || | 4287 | if (rt2x00_rt(rt2x00dev, RT3290) || |
3893 | rt2x00_rt(rt2x00dev, RT5390) || | 4288 | rt2x00_rt(rt2x00dev, RT5390) || |
3894 | rt2x00_rt(rt2x00dev, RT5392)) { | 4289 | rt2x00_rt(rt2x00dev, RT5392)) { |
@@ -3907,379 +4302,35 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) | |||
3907 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); | 4302 | rt2800_rfcsr_write(rt2x00dev, 30, rfcsr); |
3908 | } | 4303 | } |
3909 | 4304 | ||
3910 | if (rt2x00_rt(rt2x00dev, RT3070) || | 4305 | if (rt2800_is_305x_soc(rt2x00dev)) { |
3911 | rt2x00_rt(rt2x00dev, RT3071) || | 4306 | rt2800_init_rfcsr_305x_soc(rt2x00dev); |
3912 | rt2x00_rt(rt2x00dev, RT3090)) { | ||
3913 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | ||
3914 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | ||
3915 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | ||
3916 | rt2800_rfcsr_write(rt2x00dev, 7, 0x60); | ||
3917 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); | ||
3918 | rt2800_rfcsr_write(rt2x00dev, 10, 0x41); | ||
3919 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | ||
3920 | rt2800_rfcsr_write(rt2x00dev, 12, 0x7b); | ||
3921 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | ||
3922 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | ||
3923 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | ||
3924 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | ||
3925 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | ||
3926 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | ||
3927 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | ||
3928 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | ||
3929 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | ||
3930 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | ||
3931 | rt2800_rfcsr_write(rt2x00dev, 29, 0x1f); | ||
3932 | } else if (rt2x00_rt(rt2x00dev, RT3290)) { | ||
3933 | rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); | ||
3934 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | ||
3935 | rt2800_rfcsr_write(rt2x00dev, 3, 0x08); | ||
3936 | rt2800_rfcsr_write(rt2x00dev, 4, 0x00); | ||
3937 | rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); | ||
3938 | rt2800_rfcsr_write(rt2x00dev, 8, 0xf3); | ||
3939 | rt2800_rfcsr_write(rt2x00dev, 9, 0x02); | ||
3940 | rt2800_rfcsr_write(rt2x00dev, 10, 0x53); | ||
3941 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); | ||
3942 | rt2800_rfcsr_write(rt2x00dev, 12, 0x46); | ||
3943 | rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); | ||
3944 | rt2800_rfcsr_write(rt2x00dev, 18, 0x02); | ||
3945 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | ||
3946 | rt2800_rfcsr_write(rt2x00dev, 25, 0x83); | ||
3947 | rt2800_rfcsr_write(rt2x00dev, 26, 0x82); | ||
3948 | rt2800_rfcsr_write(rt2x00dev, 27, 0x09); | ||
3949 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | ||
3950 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); | ||
3951 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | ||
3952 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | ||
3953 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | ||
3954 | rt2800_rfcsr_write(rt2x00dev, 34, 0x05); | ||
3955 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | ||
3956 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | ||
3957 | rt2800_rfcsr_write(rt2x00dev, 38, 0x85); | ||
3958 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); | ||
3959 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); | ||
3960 | rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); | ||
3961 | rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); | ||
3962 | rt2800_rfcsr_write(rt2x00dev, 43, 0x7b); | ||
3963 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); | ||
3964 | rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); | ||
3965 | rt2800_rfcsr_write(rt2x00dev, 46, 0x73); | ||
3966 | rt2800_rfcsr_write(rt2x00dev, 47, 0x00); | ||
3967 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | ||
3968 | rt2800_rfcsr_write(rt2x00dev, 49, 0x98); | ||
3969 | rt2800_rfcsr_write(rt2x00dev, 52, 0x38); | ||
3970 | rt2800_rfcsr_write(rt2x00dev, 53, 0x00); | ||
3971 | rt2800_rfcsr_write(rt2x00dev, 54, 0x78); | ||
3972 | rt2800_rfcsr_write(rt2x00dev, 55, 0x43); | ||
3973 | rt2800_rfcsr_write(rt2x00dev, 56, 0x02); | ||
3974 | rt2800_rfcsr_write(rt2x00dev, 57, 0x80); | ||
3975 | rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); | ||
3976 | rt2800_rfcsr_write(rt2x00dev, 59, 0x09); | ||
3977 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | ||
3978 | rt2800_rfcsr_write(rt2x00dev, 61, 0xc1); | ||
3979 | } else if (rt2x00_rt(rt2x00dev, RT3390)) { | ||
3980 | rt2800_rfcsr_write(rt2x00dev, 0, 0xa0); | ||
3981 | rt2800_rfcsr_write(rt2x00dev, 1, 0xe1); | ||
3982 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); | ||
3983 | rt2800_rfcsr_write(rt2x00dev, 3, 0x62); | ||
3984 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | ||
3985 | rt2800_rfcsr_write(rt2x00dev, 5, 0x8b); | ||
3986 | rt2800_rfcsr_write(rt2x00dev, 6, 0x42); | ||
3987 | rt2800_rfcsr_write(rt2x00dev, 7, 0x34); | ||
3988 | rt2800_rfcsr_write(rt2x00dev, 8, 0x00); | ||
3989 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); | ||
3990 | rt2800_rfcsr_write(rt2x00dev, 10, 0x61); | ||
3991 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | ||
3992 | rt2800_rfcsr_write(rt2x00dev, 12, 0x3b); | ||
3993 | rt2800_rfcsr_write(rt2x00dev, 13, 0xe0); | ||
3994 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | ||
3995 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); | ||
3996 | rt2800_rfcsr_write(rt2x00dev, 16, 0xe0); | ||
3997 | rt2800_rfcsr_write(rt2x00dev, 17, 0x94); | ||
3998 | rt2800_rfcsr_write(rt2x00dev, 18, 0x5c); | ||
3999 | rt2800_rfcsr_write(rt2x00dev, 19, 0x4a); | ||
4000 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb2); | ||
4001 | rt2800_rfcsr_write(rt2x00dev, 21, 0xf6); | ||
4002 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | ||
4003 | rt2800_rfcsr_write(rt2x00dev, 23, 0x14); | ||
4004 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); | ||
4005 | rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); | ||
4006 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | ||
4007 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | ||
4008 | rt2800_rfcsr_write(rt2x00dev, 28, 0x41); | ||
4009 | rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); | ||
4010 | rt2800_rfcsr_write(rt2x00dev, 30, 0x20); | ||
4011 | rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); | ||
4012 | } else if (rt2x00_rt(rt2x00dev, RT3572)) { | ||
4013 | rt2800_rfcsr_write(rt2x00dev, 0, 0x70); | ||
4014 | rt2800_rfcsr_write(rt2x00dev, 1, 0x81); | ||
4015 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); | ||
4016 | rt2800_rfcsr_write(rt2x00dev, 3, 0x02); | ||
4017 | rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); | ||
4018 | rt2800_rfcsr_write(rt2x00dev, 5, 0x05); | ||
4019 | rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); | ||
4020 | rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); | ||
4021 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); | ||
4022 | rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); | ||
4023 | rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); | ||
4024 | rt2800_rfcsr_write(rt2x00dev, 12, 0x70); | ||
4025 | rt2800_rfcsr_write(rt2x00dev, 13, 0x65); | ||
4026 | rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); | ||
4027 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); | ||
4028 | rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); | ||
4029 | rt2800_rfcsr_write(rt2x00dev, 17, 0x23); | ||
4030 | rt2800_rfcsr_write(rt2x00dev, 18, 0xac); | ||
4031 | rt2800_rfcsr_write(rt2x00dev, 19, 0x93); | ||
4032 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); | ||
4033 | rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); | ||
4034 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | ||
4035 | rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); | ||
4036 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | ||
4037 | rt2800_rfcsr_write(rt2x00dev, 25, 0x15); | ||
4038 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | ||
4039 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | ||
4040 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | ||
4041 | rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); | ||
4042 | rt2800_rfcsr_write(rt2x00dev, 30, 0x09); | ||
4043 | rt2800_rfcsr_write(rt2x00dev, 31, 0x10); | ||
4044 | } else if (rt2800_is_305x_soc(rt2x00dev)) { | ||
4045 | rt2800_rfcsr_write(rt2x00dev, 0, 0x50); | ||
4046 | rt2800_rfcsr_write(rt2x00dev, 1, 0x01); | ||
4047 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf7); | ||
4048 | rt2800_rfcsr_write(rt2x00dev, 3, 0x75); | ||
4049 | rt2800_rfcsr_write(rt2x00dev, 4, 0x40); | ||
4050 | rt2800_rfcsr_write(rt2x00dev, 5, 0x03); | ||
4051 | rt2800_rfcsr_write(rt2x00dev, 6, 0x02); | ||
4052 | rt2800_rfcsr_write(rt2x00dev, 7, 0x50); | ||
4053 | rt2800_rfcsr_write(rt2x00dev, 8, 0x39); | ||
4054 | rt2800_rfcsr_write(rt2x00dev, 9, 0x0f); | ||
4055 | rt2800_rfcsr_write(rt2x00dev, 10, 0x60); | ||
4056 | rt2800_rfcsr_write(rt2x00dev, 11, 0x21); | ||
4057 | rt2800_rfcsr_write(rt2x00dev, 12, 0x75); | ||
4058 | rt2800_rfcsr_write(rt2x00dev, 13, 0x75); | ||
4059 | rt2800_rfcsr_write(rt2x00dev, 14, 0x90); | ||
4060 | rt2800_rfcsr_write(rt2x00dev, 15, 0x58); | ||
4061 | rt2800_rfcsr_write(rt2x00dev, 16, 0xb3); | ||
4062 | rt2800_rfcsr_write(rt2x00dev, 17, 0x92); | ||
4063 | rt2800_rfcsr_write(rt2x00dev, 18, 0x2c); | ||
4064 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | ||
4065 | rt2800_rfcsr_write(rt2x00dev, 20, 0xba); | ||
4066 | rt2800_rfcsr_write(rt2x00dev, 21, 0xdb); | ||
4067 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | ||
4068 | rt2800_rfcsr_write(rt2x00dev, 23, 0x31); | ||
4069 | rt2800_rfcsr_write(rt2x00dev, 24, 0x08); | ||
4070 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | ||
4071 | rt2800_rfcsr_write(rt2x00dev, 26, 0x25); | ||
4072 | rt2800_rfcsr_write(rt2x00dev, 27, 0x23); | ||
4073 | rt2800_rfcsr_write(rt2x00dev, 28, 0x13); | ||
4074 | rt2800_rfcsr_write(rt2x00dev, 29, 0x83); | ||
4075 | rt2800_rfcsr_write(rt2x00dev, 30, 0x00); | ||
4076 | rt2800_rfcsr_write(rt2x00dev, 31, 0x00); | ||
4077 | return 0; | 4307 | return 0; |
4078 | } else if (rt2x00_rt(rt2x00dev, RT3352)) { | 4308 | } |
4079 | rt2800_rfcsr_write(rt2x00dev, 0, 0xf0); | 4309 | |
4080 | rt2800_rfcsr_write(rt2x00dev, 1, 0x23); | 4310 | switch (rt2x00dev->chip.rt) { |
4081 | rt2800_rfcsr_write(rt2x00dev, 2, 0x50); | 4311 | case RT3070: |
4082 | rt2800_rfcsr_write(rt2x00dev, 3, 0x18); | 4312 | case RT3071: |
4083 | rt2800_rfcsr_write(rt2x00dev, 4, 0x00); | 4313 | case RT3090: |
4084 | rt2800_rfcsr_write(rt2x00dev, 5, 0x00); | 4314 | rt2800_init_rfcsr_30xx(rt2x00dev); |
4085 | rt2800_rfcsr_write(rt2x00dev, 6, 0x33); | 4315 | break; |
4086 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | 4316 | case RT3290: |
4087 | rt2800_rfcsr_write(rt2x00dev, 8, 0xf1); | 4317 | rt2800_init_rfcsr_3290(rt2x00dev); |
4088 | rt2800_rfcsr_write(rt2x00dev, 9, 0x02); | 4318 | break; |
4089 | rt2800_rfcsr_write(rt2x00dev, 10, 0xd2); | 4319 | case RT3352: |
4090 | rt2800_rfcsr_write(rt2x00dev, 11, 0x42); | 4320 | rt2800_init_rfcsr_3352(rt2x00dev); |
4091 | rt2800_rfcsr_write(rt2x00dev, 12, 0x1c); | 4321 | break; |
4092 | rt2800_rfcsr_write(rt2x00dev, 13, 0x00); | 4322 | case RT3390: |
4093 | rt2800_rfcsr_write(rt2x00dev, 14, 0x5a); | 4323 | rt2800_init_rfcsr_3390(rt2x00dev); |
4094 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | 4324 | break; |
4095 | rt2800_rfcsr_write(rt2x00dev, 16, 0x01); | 4325 | case RT3572: |
4096 | rt2800_rfcsr_write(rt2x00dev, 18, 0x45); | 4326 | rt2800_init_rfcsr_3572(rt2x00dev); |
4097 | rt2800_rfcsr_write(rt2x00dev, 19, 0x02); | 4327 | break; |
4098 | rt2800_rfcsr_write(rt2x00dev, 20, 0x00); | 4328 | case RT5390: |
4099 | rt2800_rfcsr_write(rt2x00dev, 21, 0x00); | 4329 | rt2800_init_rfcsr_5390(rt2x00dev); |
4100 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | 4330 | break; |
4101 | rt2800_rfcsr_write(rt2x00dev, 23, 0x00); | 4331 | case RT5392: |
4102 | rt2800_rfcsr_write(rt2x00dev, 24, 0x00); | 4332 | rt2800_init_rfcsr_5392(rt2x00dev); |
4103 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | 4333 | break; |
4104 | rt2800_rfcsr_write(rt2x00dev, 26, 0x00); | ||
4105 | rt2800_rfcsr_write(rt2x00dev, 27, 0x03); | ||
4106 | rt2800_rfcsr_write(rt2x00dev, 28, 0x03); | ||
4107 | rt2800_rfcsr_write(rt2x00dev, 29, 0x00); | ||
4108 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); | ||
4109 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | ||
4110 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | ||
4111 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | ||
4112 | rt2800_rfcsr_write(rt2x00dev, 34, 0x01); | ||
4113 | rt2800_rfcsr_write(rt2x00dev, 35, 0x03); | ||
4114 | rt2800_rfcsr_write(rt2x00dev, 36, 0xbd); | ||
4115 | rt2800_rfcsr_write(rt2x00dev, 37, 0x3c); | ||
4116 | rt2800_rfcsr_write(rt2x00dev, 38, 0x5f); | ||
4117 | rt2800_rfcsr_write(rt2x00dev, 39, 0xc5); | ||
4118 | rt2800_rfcsr_write(rt2x00dev, 40, 0x33); | ||
4119 | rt2800_rfcsr_write(rt2x00dev, 41, 0x5b); | ||
4120 | rt2800_rfcsr_write(rt2x00dev, 42, 0x5b); | ||
4121 | rt2800_rfcsr_write(rt2x00dev, 43, 0xdb); | ||
4122 | rt2800_rfcsr_write(rt2x00dev, 44, 0xdb); | ||
4123 | rt2800_rfcsr_write(rt2x00dev, 45, 0xdb); | ||
4124 | rt2800_rfcsr_write(rt2x00dev, 46, 0xdd); | ||
4125 | rt2800_rfcsr_write(rt2x00dev, 47, 0x0d); | ||
4126 | rt2800_rfcsr_write(rt2x00dev, 48, 0x14); | ||
4127 | rt2800_rfcsr_write(rt2x00dev, 49, 0x00); | ||
4128 | rt2800_rfcsr_write(rt2x00dev, 50, 0x2d); | ||
4129 | rt2800_rfcsr_write(rt2x00dev, 51, 0x7f); | ||
4130 | rt2800_rfcsr_write(rt2x00dev, 52, 0x00); | ||
4131 | rt2800_rfcsr_write(rt2x00dev, 53, 0x52); | ||
4132 | rt2800_rfcsr_write(rt2x00dev, 54, 0x1b); | ||
4133 | rt2800_rfcsr_write(rt2x00dev, 55, 0x7f); | ||
4134 | rt2800_rfcsr_write(rt2x00dev, 56, 0x00); | ||
4135 | rt2800_rfcsr_write(rt2x00dev, 57, 0x52); | ||
4136 | rt2800_rfcsr_write(rt2x00dev, 58, 0x1b); | ||
4137 | rt2800_rfcsr_write(rt2x00dev, 59, 0x00); | ||
4138 | rt2800_rfcsr_write(rt2x00dev, 60, 0x00); | ||
4139 | rt2800_rfcsr_write(rt2x00dev, 61, 0x00); | ||
4140 | rt2800_rfcsr_write(rt2x00dev, 62, 0x00); | ||
4141 | rt2800_rfcsr_write(rt2x00dev, 63, 0x00); | ||
4142 | } else if (rt2x00_rt(rt2x00dev, RT5390)) { | ||
4143 | rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); | ||
4144 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | ||
4145 | rt2800_rfcsr_write(rt2x00dev, 3, 0x88); | ||
4146 | rt2800_rfcsr_write(rt2x00dev, 5, 0x10); | ||
4147 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4148 | rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); | ||
4149 | else | ||
4150 | rt2800_rfcsr_write(rt2x00dev, 6, 0xa0); | ||
4151 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | ||
4152 | rt2800_rfcsr_write(rt2x00dev, 10, 0x53); | ||
4153 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); | ||
4154 | rt2800_rfcsr_write(rt2x00dev, 12, 0xc6); | ||
4155 | rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); | ||
4156 | rt2800_rfcsr_write(rt2x00dev, 14, 0x00); | ||
4157 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | ||
4158 | rt2800_rfcsr_write(rt2x00dev, 16, 0x00); | ||
4159 | rt2800_rfcsr_write(rt2x00dev, 18, 0x03); | ||
4160 | rt2800_rfcsr_write(rt2x00dev, 19, 0x00); | ||
4161 | |||
4162 | rt2800_rfcsr_write(rt2x00dev, 20, 0x00); | ||
4163 | rt2800_rfcsr_write(rt2x00dev, 21, 0x00); | ||
4164 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | ||
4165 | rt2800_rfcsr_write(rt2x00dev, 23, 0x00); | ||
4166 | rt2800_rfcsr_write(rt2x00dev, 24, 0x00); | ||
4167 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4168 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | ||
4169 | else | ||
4170 | rt2800_rfcsr_write(rt2x00dev, 25, 0xc0); | ||
4171 | rt2800_rfcsr_write(rt2x00dev, 26, 0x00); | ||
4172 | rt2800_rfcsr_write(rt2x00dev, 27, 0x09); | ||
4173 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | ||
4174 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | ||
4175 | |||
4176 | rt2800_rfcsr_write(rt2x00dev, 30, 0x00); | ||
4177 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | ||
4178 | rt2800_rfcsr_write(rt2x00dev, 32, 0x80); | ||
4179 | rt2800_rfcsr_write(rt2x00dev, 33, 0x00); | ||
4180 | rt2800_rfcsr_write(rt2x00dev, 34, 0x07); | ||
4181 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | ||
4182 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | ||
4183 | rt2800_rfcsr_write(rt2x00dev, 37, 0x08); | ||
4184 | rt2800_rfcsr_write(rt2x00dev, 38, 0x85); | ||
4185 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); | ||
4186 | |||
4187 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4188 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0b); | ||
4189 | else | ||
4190 | rt2800_rfcsr_write(rt2x00dev, 40, 0x4b); | ||
4191 | rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); | ||
4192 | rt2800_rfcsr_write(rt2x00dev, 42, 0xd2); | ||
4193 | rt2800_rfcsr_write(rt2x00dev, 43, 0x9a); | ||
4194 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); | ||
4195 | rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); | ||
4196 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4197 | rt2800_rfcsr_write(rt2x00dev, 46, 0x73); | ||
4198 | else | ||
4199 | rt2800_rfcsr_write(rt2x00dev, 46, 0x7b); | ||
4200 | rt2800_rfcsr_write(rt2x00dev, 47, 0x00); | ||
4201 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | ||
4202 | rt2800_rfcsr_write(rt2x00dev, 49, 0x94); | ||
4203 | |||
4204 | rt2800_rfcsr_write(rt2x00dev, 52, 0x38); | ||
4205 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4206 | rt2800_rfcsr_write(rt2x00dev, 53, 0x00); | ||
4207 | else | ||
4208 | rt2800_rfcsr_write(rt2x00dev, 53, 0x84); | ||
4209 | rt2800_rfcsr_write(rt2x00dev, 54, 0x78); | ||
4210 | rt2800_rfcsr_write(rt2x00dev, 55, 0x44); | ||
4211 | rt2800_rfcsr_write(rt2x00dev, 56, 0x22); | ||
4212 | rt2800_rfcsr_write(rt2x00dev, 57, 0x80); | ||
4213 | rt2800_rfcsr_write(rt2x00dev, 58, 0x7f); | ||
4214 | rt2800_rfcsr_write(rt2x00dev, 59, 0x63); | ||
4215 | |||
4216 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | ||
4217 | if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) | ||
4218 | rt2800_rfcsr_write(rt2x00dev, 61, 0xd1); | ||
4219 | else | ||
4220 | rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); | ||
4221 | rt2800_rfcsr_write(rt2x00dev, 62, 0x00); | ||
4222 | rt2800_rfcsr_write(rt2x00dev, 63, 0x00); | ||
4223 | } else if (rt2x00_rt(rt2x00dev, RT5392)) { | ||
4224 | rt2800_rfcsr_write(rt2x00dev, 1, 0x17); | ||
4225 | rt2800_rfcsr_write(rt2x00dev, 2, 0x80); | ||
4226 | rt2800_rfcsr_write(rt2x00dev, 3, 0x88); | ||
4227 | rt2800_rfcsr_write(rt2x00dev, 5, 0x10); | ||
4228 | rt2800_rfcsr_write(rt2x00dev, 6, 0xe0); | ||
4229 | rt2800_rfcsr_write(rt2x00dev, 7, 0x00); | ||
4230 | rt2800_rfcsr_write(rt2x00dev, 10, 0x53); | ||
4231 | rt2800_rfcsr_write(rt2x00dev, 11, 0x4a); | ||
4232 | rt2800_rfcsr_write(rt2x00dev, 12, 0x46); | ||
4233 | rt2800_rfcsr_write(rt2x00dev, 13, 0x9f); | ||
4234 | rt2800_rfcsr_write(rt2x00dev, 14, 0x00); | ||
4235 | rt2800_rfcsr_write(rt2x00dev, 15, 0x00); | ||
4236 | rt2800_rfcsr_write(rt2x00dev, 16, 0x00); | ||
4237 | rt2800_rfcsr_write(rt2x00dev, 18, 0x03); | ||
4238 | rt2800_rfcsr_write(rt2x00dev, 19, 0x4d); | ||
4239 | rt2800_rfcsr_write(rt2x00dev, 20, 0x00); | ||
4240 | rt2800_rfcsr_write(rt2x00dev, 21, 0x8d); | ||
4241 | rt2800_rfcsr_write(rt2x00dev, 22, 0x20); | ||
4242 | rt2800_rfcsr_write(rt2x00dev, 23, 0x0b); | ||
4243 | rt2800_rfcsr_write(rt2x00dev, 24, 0x44); | ||
4244 | rt2800_rfcsr_write(rt2x00dev, 25, 0x80); | ||
4245 | rt2800_rfcsr_write(rt2x00dev, 26, 0x82); | ||
4246 | rt2800_rfcsr_write(rt2x00dev, 27, 0x09); | ||
4247 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | ||
4248 | rt2800_rfcsr_write(rt2x00dev, 29, 0x10); | ||
4249 | rt2800_rfcsr_write(rt2x00dev, 30, 0x10); | ||
4250 | rt2800_rfcsr_write(rt2x00dev, 31, 0x80); | ||
4251 | rt2800_rfcsr_write(rt2x00dev, 32, 0x20); | ||
4252 | rt2800_rfcsr_write(rt2x00dev, 33, 0xC0); | ||
4253 | rt2800_rfcsr_write(rt2x00dev, 34, 0x07); | ||
4254 | rt2800_rfcsr_write(rt2x00dev, 35, 0x12); | ||
4255 | rt2800_rfcsr_write(rt2x00dev, 36, 0x00); | ||
4256 | rt2800_rfcsr_write(rt2x00dev, 37, 0x08); | ||
4257 | rt2800_rfcsr_write(rt2x00dev, 38, 0x89); | ||
4258 | rt2800_rfcsr_write(rt2x00dev, 39, 0x1b); | ||
4259 | rt2800_rfcsr_write(rt2x00dev, 40, 0x0f); | ||
4260 | rt2800_rfcsr_write(rt2x00dev, 41, 0xbb); | ||
4261 | rt2800_rfcsr_write(rt2x00dev, 42, 0xd5); | ||
4262 | rt2800_rfcsr_write(rt2x00dev, 43, 0x9b); | ||
4263 | rt2800_rfcsr_write(rt2x00dev, 44, 0x0e); | ||
4264 | rt2800_rfcsr_write(rt2x00dev, 45, 0xa2); | ||
4265 | rt2800_rfcsr_write(rt2x00dev, 46, 0x73); | ||
4266 | rt2800_rfcsr_write(rt2x00dev, 47, 0x0c); | ||
4267 | rt2800_rfcsr_write(rt2x00dev, 48, 0x10); | ||
4268 | rt2800_rfcsr_write(rt2x00dev, 49, 0x94); | ||
4269 | rt2800_rfcsr_write(rt2x00dev, 50, 0x94); | ||
4270 | rt2800_rfcsr_write(rt2x00dev, 51, 0x3a); | ||
4271 | rt2800_rfcsr_write(rt2x00dev, 52, 0x48); | ||
4272 | rt2800_rfcsr_write(rt2x00dev, 53, 0x44); | ||
4273 | rt2800_rfcsr_write(rt2x00dev, 54, 0x38); | ||
4274 | rt2800_rfcsr_write(rt2x00dev, 55, 0x43); | ||
4275 | rt2800_rfcsr_write(rt2x00dev, 56, 0xa1); | ||
4276 | rt2800_rfcsr_write(rt2x00dev, 57, 0x00); | ||
4277 | rt2800_rfcsr_write(rt2x00dev, 58, 0x39); | ||
4278 | rt2800_rfcsr_write(rt2x00dev, 59, 0x07); | ||
4279 | rt2800_rfcsr_write(rt2x00dev, 60, 0x45); | ||
4280 | rt2800_rfcsr_write(rt2x00dev, 61, 0x91); | ||
4281 | rt2800_rfcsr_write(rt2x00dev, 62, 0x39); | ||
4282 | rt2800_rfcsr_write(rt2x00dev, 63, 0x07); | ||
4283 | } | 4334 | } |
4284 | 4335 | ||
4285 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { | 4336 | if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { |