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authorDaniel Golle <dgolle@allnet.de>2012-09-09 07:24:39 -0400
committerJohn W. Linville <linville@tuxdriver.com>2012-09-11 15:13:50 -0400
commit03839951515b0ea2b21d649b1fe7b63f9817d0c8 (patch)
tree8d02043e2c45dd341370fc4670686cadbe39cac1 /drivers/net/wireless/rt2x00
parentad417a533a5bddedbf6b64c12cc26af7c80866f8 (diff)
rt2x00: add MediaTek/RaLink Rt3352 WiSoC
Support for the RT3352 WiSoC was developed for and tested with the ALL5002 devboard running OpenWrt. For now, this supports only devices with internal TXALC. Corrections were made according to the remarks of Stanislaw Gruszka and Gertjan van Wingerde, thank you guys for reviewing! Signed-off-by: Daniel Golle <dgolle@allnet.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/rt2x00')
-rw-r--r--drivers/net/wireless/rt2x00/rt2800.h5
-rw-r--r--drivers/net/wireless/rt2x00/rt2800lib.c211
-rw-r--r--drivers/net/wireless/rt2x00/rt2x00.h1
3 files changed, 212 insertions, 5 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h
index e13916f18001..6d67c3ede651 100644
--- a/drivers/net/wireless/rt2x00/rt2800.h
+++ b/drivers/net/wireless/rt2x00/rt2800.h
@@ -1943,6 +1943,11 @@ struct mac_iveiv_entry {
1943#define BBP47_TSSI_ADC6 FIELD8(0x80) 1943#define BBP47_TSSI_ADC6 FIELD8(0x80)
1944 1944
1945/* 1945/*
1946 * BBP 49
1947 */
1948#define BBP49_UPDATE_FLAG FIELD8(0x01)
1949
1950/*
1946 * BBP 109 1951 * BBP 109
1947 */ 1952 */
1948#define BBP109_TX0_POWER FIELD8(0x0f) 1953#define BBP109_TX0_POWER FIELD8(0x0f)
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c
index a04e2229b33d..9e09367c9739 100644
--- a/drivers/net/wireless/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/rt2x00/rt2800lib.c
@@ -1615,6 +1615,7 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1615 case 1: 1615 case 1:
1616 if (rt2x00_rt(rt2x00dev, RT3070) || 1616 if (rt2x00_rt(rt2x00dev, RT3070) ||
1617 rt2x00_rt(rt2x00dev, RT3090) || 1617 rt2x00_rt(rt2x00dev, RT3090) ||
1618 rt2x00_rt(rt2x00dev, RT3352) ||
1618 rt2x00_rt(rt2x00dev, RT3390)) { 1619 rt2x00_rt(rt2x00dev, RT3390)) {
1619 rt2x00_eeprom_read(rt2x00dev, 1620 rt2x00_eeprom_read(rt2x00dev,
1620 EEPROM_NIC_CONF1, &eeprom); 1621 EEPROM_NIC_CONF1, &eeprom);
@@ -2053,6 +2054,60 @@ static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2053 } 2054 }
2054} 2055}
2055 2056
2057static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2058 struct ieee80211_conf *conf,
2059 struct rf_channel *rf,
2060 struct channel_info *info)
2061{
2062 u8 rfcsr;
2063
2064 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2065 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2066
2067 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2068 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2069 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2070
2071 if (info->default_power1 > POWER_BOUND)
2072 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2073 else
2074 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2075
2076 if (info->default_power2 > POWER_BOUND)
2077 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2078 else
2079 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2080
2081 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2082 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2083 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2084 else
2085 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2086
2087 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2088
2089 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2090 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2091 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2092
2093 if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2094 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2095 else
2096 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2097
2098 if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2099 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2100 else
2101 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2102
2103 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2104 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2105
2106 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2107
2108 rt2800_rfcsr_write(rt2x00dev, 31, 80);
2109}
2110
2056static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev, 2111static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2057 struct ieee80211_conf *conf, 2112 struct ieee80211_conf *conf,
2058 struct rf_channel *rf, 2113 struct rf_channel *rf,
@@ -2182,6 +2237,9 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2182 case RF3290: 2237 case RF3290:
2183 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info); 2238 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2184 break; 2239 break;
2240 case RF3322:
2241 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
2242 break;
2185 case RF5360: 2243 case RF5360:
2186 case RF5370: 2244 case RF5370:
2187 case RF5372: 2245 case RF5372:
@@ -2194,6 +2252,7 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2194 } 2252 }
2195 2253
2196 if (rt2x00_rf(rt2x00dev, RF3290) || 2254 if (rt2x00_rf(rt2x00dev, RF3290) ||
2255 rt2x00_rf(rt2x00dev, RF3322) ||
2197 rt2x00_rf(rt2x00dev, RF5360) || 2256 rt2x00_rf(rt2x00dev, RF5360) ||
2198 rt2x00_rf(rt2x00dev, RF5370) || 2257 rt2x00_rf(rt2x00dev, RF5370) ||
2199 rt2x00_rf(rt2x00dev, RF5372) || 2258 rt2x00_rf(rt2x00dev, RF5372) ||
@@ -2212,10 +2271,17 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2212 /* 2271 /*
2213 * Change BBP settings 2272 * Change BBP settings
2214 */ 2273 */
2215 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain); 2274 if (rt2x00_rt(rt2x00dev, RT3352)) {
2216 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain); 2275 rt2800_bbp_write(rt2x00dev, 27, 0x0);
2217 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain); 2276 rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
2218 rt2800_bbp_write(rt2x00dev, 86, 0); 2277 rt2800_bbp_write(rt2x00dev, 27, 0x20);
2278 rt2800_bbp_write(rt2x00dev, 62, 0x26 + rt2x00dev->lna_gain);
2279 } else {
2280 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2281 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2282 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2283 rt2800_bbp_write(rt2x00dev, 86, 0);
2284 }
2219 2285
2220 if (rf->channel <= 14) { 2286 if (rf->channel <= 14) {
2221 if (!rt2x00_rt(rt2x00dev, RT5390) && 2287 if (!rt2x00_rt(rt2x00dev, RT5390) &&
@@ -2310,6 +2376,15 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2310 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg); 2376 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &reg);
2311 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg); 2377 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &reg);
2312 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg); 2378 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &reg);
2379
2380 /*
2381 * Clear update flag
2382 */
2383 if (rt2x00_rt(rt2x00dev, RT3352)) {
2384 rt2800_bbp_read(rt2x00dev, 49, &bbp);
2385 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
2386 rt2800_bbp_write(rt2x00dev, 49, bbp);
2387 }
2313} 2388}
2314 2389
2315static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev) 2390static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
@@ -2998,6 +3073,10 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2998 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 3073 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2999 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); 3074 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
3000 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); 3075 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
3076 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3077 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
3078 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
3079 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
3001 } else if (rt2x00_rt(rt2x00dev, RT3572)) { 3080 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3002 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); 3081 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
3003 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); 3082 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
@@ -3378,6 +3457,11 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3378 rt2800_wait_bbp_ready(rt2x00dev))) 3457 rt2800_wait_bbp_ready(rt2x00dev)))
3379 return -EACCES; 3458 return -EACCES;
3380 3459
3460 if (rt2x00_rt(rt2x00dev, RT3352)) {
3461 rt2800_bbp_write(rt2x00dev, 3, 0x00);
3462 rt2800_bbp_write(rt2x00dev, 4, 0x50);
3463 }
3464
3381 if (rt2x00_rt(rt2x00dev, RT3290) || 3465 if (rt2x00_rt(rt2x00dev, RT3290) ||
3382 rt2x00_rt(rt2x00dev, RT5390) || 3466 rt2x00_rt(rt2x00dev, RT5390) ||
3383 rt2x00_rt(rt2x00dev, RT5392)) { 3467 rt2x00_rt(rt2x00dev, RT5392)) {
@@ -3388,15 +3472,20 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3388 3472
3389 if (rt2800_is_305x_soc(rt2x00dev) || 3473 if (rt2800_is_305x_soc(rt2x00dev) ||
3390 rt2x00_rt(rt2x00dev, RT3290) || 3474 rt2x00_rt(rt2x00dev, RT3290) ||
3475 rt2x00_rt(rt2x00dev, RT3352) ||
3391 rt2x00_rt(rt2x00dev, RT3572) || 3476 rt2x00_rt(rt2x00dev, RT3572) ||
3392 rt2x00_rt(rt2x00dev, RT5390) || 3477 rt2x00_rt(rt2x00dev, RT5390) ||
3393 rt2x00_rt(rt2x00dev, RT5392)) 3478 rt2x00_rt(rt2x00dev, RT5392))
3394 rt2800_bbp_write(rt2x00dev, 31, 0x08); 3479 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3395 3480
3481 if (rt2x00_rt(rt2x00dev, RT3352))
3482 rt2800_bbp_write(rt2x00dev, 47, 0x48);
3483
3396 rt2800_bbp_write(rt2x00dev, 65, 0x2c); 3484 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3397 rt2800_bbp_write(rt2x00dev, 66, 0x38); 3485 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3398 3486
3399 if (rt2x00_rt(rt2x00dev, RT3290) || 3487 if (rt2x00_rt(rt2x00dev, RT3290) ||
3488 rt2x00_rt(rt2x00dev, RT3352) ||
3400 rt2x00_rt(rt2x00dev, RT5390) || 3489 rt2x00_rt(rt2x00dev, RT5390) ||
3401 rt2x00_rt(rt2x00dev, RT5392)) 3490 rt2x00_rt(rt2x00dev, RT5392))
3402 rt2800_bbp_write(rt2x00dev, 68, 0x0b); 3491 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
@@ -3405,6 +3494,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3405 rt2800_bbp_write(rt2x00dev, 69, 0x16); 3494 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3406 rt2800_bbp_write(rt2x00dev, 73, 0x12); 3495 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3407 } else if (rt2x00_rt(rt2x00dev, RT3290) || 3496 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3497 rt2x00_rt(rt2x00dev, RT3352) ||
3408 rt2x00_rt(rt2x00dev, RT5390) || 3498 rt2x00_rt(rt2x00dev, RT5390) ||
3409 rt2x00_rt(rt2x00dev, RT5392)) { 3499 rt2x00_rt(rt2x00dev, RT5392)) {
3410 rt2800_bbp_write(rt2x00dev, 69, 0x12); 3500 rt2800_bbp_write(rt2x00dev, 69, 0x12);
@@ -3436,6 +3526,10 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3436 } else if (rt2800_is_305x_soc(rt2x00dev)) { 3526 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3437 rt2800_bbp_write(rt2x00dev, 78, 0x0e); 3527 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3438 rt2800_bbp_write(rt2x00dev, 80, 0x08); 3528 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3529 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
3530 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3531 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3532 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3439 } else { 3533 } else {
3440 rt2800_bbp_write(rt2x00dev, 81, 0x37); 3534 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3441 } 3535 }
@@ -3465,18 +3559,21 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3465 rt2800_bbp_write(rt2x00dev, 84, 0x99); 3559 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3466 3560
3467 if (rt2x00_rt(rt2x00dev, RT3290) || 3561 if (rt2x00_rt(rt2x00dev, RT3290) ||
3562 rt2x00_rt(rt2x00dev, RT3352) ||
3468 rt2x00_rt(rt2x00dev, RT5390) || 3563 rt2x00_rt(rt2x00dev, RT5390) ||
3469 rt2x00_rt(rt2x00dev, RT5392)) 3564 rt2x00_rt(rt2x00dev, RT5392))
3470 rt2800_bbp_write(rt2x00dev, 86, 0x38); 3565 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3471 else 3566 else
3472 rt2800_bbp_write(rt2x00dev, 86, 0x00); 3567 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3473 3568
3474 if (rt2x00_rt(rt2x00dev, RT5392)) 3569 if (rt2x00_rt(rt2x00dev, RT3352) ||
3570 rt2x00_rt(rt2x00dev, RT5392))
3475 rt2800_bbp_write(rt2x00dev, 88, 0x90); 3571 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3476 3572
3477 rt2800_bbp_write(rt2x00dev, 91, 0x04); 3573 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3478 3574
3479 if (rt2x00_rt(rt2x00dev, RT3290) || 3575 if (rt2x00_rt(rt2x00dev, RT3290) ||
3576 rt2x00_rt(rt2x00dev, RT3352) ||
3480 rt2x00_rt(rt2x00dev, RT5390) || 3577 rt2x00_rt(rt2x00dev, RT5390) ||
3481 rt2x00_rt(rt2x00dev, RT5392)) 3578 rt2x00_rt(rt2x00dev, RT5392))
3482 rt2800_bbp_write(rt2x00dev, 92, 0x02); 3579 rt2800_bbp_write(rt2x00dev, 92, 0x02);
@@ -3493,6 +3590,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3493 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || 3590 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3494 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || 3591 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3495 rt2x00_rt(rt2x00dev, RT3290) || 3592 rt2x00_rt(rt2x00dev, RT3290) ||
3593 rt2x00_rt(rt2x00dev, RT3352) ||
3496 rt2x00_rt(rt2x00dev, RT3572) || 3594 rt2x00_rt(rt2x00dev, RT3572) ||
3497 rt2x00_rt(rt2x00dev, RT5390) || 3595 rt2x00_rt(rt2x00dev, RT5390) ||
3498 rt2x00_rt(rt2x00dev, RT5392) || 3596 rt2x00_rt(rt2x00dev, RT5392) ||
@@ -3502,6 +3600,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3502 rt2800_bbp_write(rt2x00dev, 103, 0x00); 3600 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3503 3601
3504 if (rt2x00_rt(rt2x00dev, RT3290) || 3602 if (rt2x00_rt(rt2x00dev, RT3290) ||
3603 rt2x00_rt(rt2x00dev, RT3352) ||
3505 rt2x00_rt(rt2x00dev, RT5390) || 3604 rt2x00_rt(rt2x00dev, RT5390) ||
3506 rt2x00_rt(rt2x00dev, RT5392)) 3605 rt2x00_rt(rt2x00dev, RT5392))
3507 rt2800_bbp_write(rt2x00dev, 104, 0x92); 3606 rt2800_bbp_write(rt2x00dev, 104, 0x92);
@@ -3510,6 +3609,8 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3510 rt2800_bbp_write(rt2x00dev, 105, 0x01); 3609 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3511 else if (rt2x00_rt(rt2x00dev, RT3290)) 3610 else if (rt2x00_rt(rt2x00dev, RT3290))
3512 rt2800_bbp_write(rt2x00dev, 105, 0x1c); 3611 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
3612 else if (rt2x00_rt(rt2x00dev, RT3352))
3613 rt2800_bbp_write(rt2x00dev, 105, 0x34);
3513 else if (rt2x00_rt(rt2x00dev, RT5390) || 3614 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3514 rt2x00_rt(rt2x00dev, RT5392)) 3615 rt2x00_rt(rt2x00dev, RT5392))
3515 rt2800_bbp_write(rt2x00dev, 105, 0x3c); 3616 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
@@ -3519,11 +3620,16 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3519 if (rt2x00_rt(rt2x00dev, RT3290) || 3620 if (rt2x00_rt(rt2x00dev, RT3290) ||
3520 rt2x00_rt(rt2x00dev, RT5390)) 3621 rt2x00_rt(rt2x00dev, RT5390))
3521 rt2800_bbp_write(rt2x00dev, 106, 0x03); 3622 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3623 else if (rt2x00_rt(rt2x00dev, RT3352))
3624 rt2800_bbp_write(rt2x00dev, 106, 0x05);
3522 else if (rt2x00_rt(rt2x00dev, RT5392)) 3625 else if (rt2x00_rt(rt2x00dev, RT5392))
3523 rt2800_bbp_write(rt2x00dev, 106, 0x12); 3626 rt2800_bbp_write(rt2x00dev, 106, 0x12);
3524 else 3627 else
3525 rt2800_bbp_write(rt2x00dev, 106, 0x35); 3628 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3526 3629
3630 if (rt2x00_rt(rt2x00dev, RT3352))
3631 rt2800_bbp_write(rt2x00dev, 120, 0x50);
3632
3527 if (rt2x00_rt(rt2x00dev, RT3290) || 3633 if (rt2x00_rt(rt2x00dev, RT3290) ||
3528 rt2x00_rt(rt2x00dev, RT5390) || 3634 rt2x00_rt(rt2x00dev, RT5390) ||
3529 rt2x00_rt(rt2x00dev, RT5392)) 3635 rt2x00_rt(rt2x00dev, RT5392))
@@ -3534,6 +3640,9 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3534 rt2800_bbp_write(rt2x00dev, 135, 0xf6); 3640 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3535 } 3641 }
3536 3642
3643 if (rt2x00_rt(rt2x00dev, RT3352))
3644 rt2800_bbp_write(rt2x00dev, 137, 0x0f);
3645
3537 if (rt2x00_rt(rt2x00dev, RT3071) || 3646 if (rt2x00_rt(rt2x00dev, RT3071) ||
3538 rt2x00_rt(rt2x00dev, RT3090) || 3647 rt2x00_rt(rt2x00dev, RT3090) ||
3539 rt2x00_rt(rt2x00dev, RT3390) || 3648 rt2x00_rt(rt2x00dev, RT3390) ||
@@ -3574,6 +3683,28 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3574 rt2800_bbp_write(rt2x00dev, 3, value); 3683 rt2800_bbp_write(rt2x00dev, 3, value);
3575 } 3684 }
3576 3685
3686 if (rt2x00_rt(rt2x00dev, RT3352)) {
3687 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
3688 /* Set ITxBF timeout to 0x9c40=1000msec */
3689 rt2800_bbp_write(rt2x00dev, 179, 0x02);
3690 rt2800_bbp_write(rt2x00dev, 180, 0x00);
3691 rt2800_bbp_write(rt2x00dev, 182, 0x40);
3692 rt2800_bbp_write(rt2x00dev, 180, 0x01);
3693 rt2800_bbp_write(rt2x00dev, 182, 0x9c);
3694 rt2800_bbp_write(rt2x00dev, 179, 0x00);
3695 /* Reprogram the inband interface to put right values in RXWI */
3696 rt2800_bbp_write(rt2x00dev, 142, 0x04);
3697 rt2800_bbp_write(rt2x00dev, 143, 0x3b);
3698 rt2800_bbp_write(rt2x00dev, 142, 0x06);
3699 rt2800_bbp_write(rt2x00dev, 143, 0xa0);
3700 rt2800_bbp_write(rt2x00dev, 142, 0x07);
3701 rt2800_bbp_write(rt2x00dev, 143, 0xa1);
3702 rt2800_bbp_write(rt2x00dev, 142, 0x08);
3703 rt2800_bbp_write(rt2x00dev, 143, 0xa2);
3704
3705 rt2800_bbp_write(rt2x00dev, 148, 0xc8);
3706 }
3707
3577 if (rt2x00_rt(rt2x00dev, RT5390) || 3708 if (rt2x00_rt(rt2x00dev, RT5390) ||
3578 rt2x00_rt(rt2x00dev, RT5392)) { 3709 rt2x00_rt(rt2x00dev, RT5392)) {
3579 int ant, div_mode; 3710 int ant, div_mode;
@@ -3707,6 +3838,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3707 !rt2x00_rt(rt2x00dev, RT3071) && 3838 !rt2x00_rt(rt2x00dev, RT3071) &&
3708 !rt2x00_rt(rt2x00dev, RT3090) && 3839 !rt2x00_rt(rt2x00dev, RT3090) &&
3709 !rt2x00_rt(rt2x00dev, RT3290) && 3840 !rt2x00_rt(rt2x00dev, RT3290) &&
3841 !rt2x00_rt(rt2x00dev, RT3352) &&
3710 !rt2x00_rt(rt2x00dev, RT3390) && 3842 !rt2x00_rt(rt2x00dev, RT3390) &&
3711 !rt2x00_rt(rt2x00dev, RT3572) && 3843 !rt2x00_rt(rt2x00dev, RT3572) &&
3712 !rt2x00_rt(rt2x00dev, RT5390) && 3844 !rt2x00_rt(rt2x00dev, RT5390) &&
@@ -3903,6 +4035,70 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3903 rt2800_rfcsr_write(rt2x00dev, 30, 0x00); 4035 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3904 rt2800_rfcsr_write(rt2x00dev, 31, 0x00); 4036 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3905 return 0; 4037 return 0;
4038 } else if (rt2x00_rt(rt2x00dev, RT3352)) {
4039 rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
4040 rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
4041 rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
4042 rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
4043 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
4044 rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
4045 rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
4046 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
4047 rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
4048 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
4049 rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
4050 rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
4051 rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
4052 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
4053 rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
4054 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
4055 rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
4056 rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
4057 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
4058 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
4059 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
4060 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
4061 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
4062 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
4063 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
4064 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
4065 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4066 rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
4067 rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
4068 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
4069 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
4070 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
4071 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
4072 rt2800_rfcsr_write(rt2x00dev, 34, 0x01);
4073 rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
4074 rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
4075 rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
4076 rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
4077 rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
4078 rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
4079 rt2800_rfcsr_write(rt2x00dev, 41, 0x5b);
4080 rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
4081 rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
4082 rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
4083 rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
4084 rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
4085 rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
4086 rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
4087 rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
4088 rt2800_rfcsr_write(rt2x00dev, 50, 0x2d);
4089 rt2800_rfcsr_write(rt2x00dev, 51, 0x7f);
4090 rt2800_rfcsr_write(rt2x00dev, 52, 0x00);
4091 rt2800_rfcsr_write(rt2x00dev, 53, 0x52);
4092 rt2800_rfcsr_write(rt2x00dev, 54, 0x1b);
4093 rt2800_rfcsr_write(rt2x00dev, 55, 0x7f);
4094 rt2800_rfcsr_write(rt2x00dev, 56, 0x00);
4095 rt2800_rfcsr_write(rt2x00dev, 57, 0x52);
4096 rt2800_rfcsr_write(rt2x00dev, 58, 0x1b);
4097 rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
4098 rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
4099 rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
4100 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
4101 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3906 } else if (rt2x00_rt(rt2x00dev, RT5390)) { 4102 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3907 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f); 4103 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3908 rt2800_rfcsr_write(rt2x00dev, 2, 0x80); 4104 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
@@ -4104,6 +4300,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
4104 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); 4300 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4105 } else if (rt2x00_rt(rt2x00dev, RT3071) || 4301 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4106 rt2x00_rt(rt2x00dev, RT3090) || 4302 rt2x00_rt(rt2x00dev, RT3090) ||
4303 rt2x00_rt(rt2x00dev, RT3352) ||
4107 rt2x00_rt(rt2x00dev, RT3390) || 4304 rt2x00_rt(rt2x00dev, RT3390) ||
4108 rt2x00_rt(rt2x00dev, RT3572)) { 4305 rt2x00_rt(rt2x00dev, RT3572)) {
4109 drv_data->calibration_bw20 = 4306 drv_data->calibration_bw20 =
@@ -4566,6 +4763,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4566 case RT3071: 4763 case RT3071:
4567 case RT3090: 4764 case RT3090:
4568 case RT3290: 4765 case RT3290:
4766 case RT3352:
4569 case RT3390: 4767 case RT3390:
4570 case RT3572: 4768 case RT3572:
4571 case RT5390: 4769 case RT5390:
@@ -4588,6 +4786,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4588 case RF3052: 4786 case RF3052:
4589 case RF3290: 4787 case RF3290:
4590 case RF3320: 4788 case RF3320:
4789 case RF3322:
4591 case RF5360: 4790 case RF5360:
4592 case RF5370: 4791 case RF5370:
4593 case RF5372: 4792 case RF5372:
@@ -4612,6 +4811,7 @@ static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4612 4811
4613 if (rt2x00_rt(rt2x00dev, RT3070) || 4812 if (rt2x00_rt(rt2x00dev, RT3070) ||
4614 rt2x00_rt(rt2x00dev, RT3090) || 4813 rt2x00_rt(rt2x00dev, RT3090) ||
4814 rt2x00_rt(rt2x00dev, RT3352) ||
4615 rt2x00_rt(rt2x00dev, RT3390)) { 4815 rt2x00_rt(rt2x00dev, RT3390)) {
4616 value = rt2x00_get_field16(eeprom, 4816 value = rt2x00_get_field16(eeprom,
4617 EEPROM_NIC_CONF1_ANT_DIVERSITY); 4817 EEPROM_NIC_CONF1_ANT_DIVERSITY);
@@ -4904,6 +5104,7 @@ static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4904 rt2x00_rf(rt2x00dev, RF3022) || 5104 rt2x00_rf(rt2x00dev, RF3022) ||
4905 rt2x00_rf(rt2x00dev, RF3290) || 5105 rt2x00_rf(rt2x00dev, RF3290) ||
4906 rt2x00_rf(rt2x00dev, RF3320) || 5106 rt2x00_rf(rt2x00dev, RF3320) ||
5107 rt2x00_rf(rt2x00dev, RF3322) ||
4907 rt2x00_rf(rt2x00dev, RF5360) || 5108 rt2x00_rf(rt2x00dev, RF5360) ||
4908 rt2x00_rf(rt2x00dev, RF5370) || 5109 rt2x00_rf(rt2x00dev, RF5370) ||
4909 rt2x00_rf(rt2x00dev, RF5372) || 5110 rt2x00_rf(rt2x00dev, RF5372) ||
diff --git a/drivers/net/wireless/rt2x00/rt2x00.h b/drivers/net/wireless/rt2x00/rt2x00.h
index f991e8bedc70..49375c86c334 100644
--- a/drivers/net/wireless/rt2x00/rt2x00.h
+++ b/drivers/net/wireless/rt2x00/rt2x00.h
@@ -188,6 +188,7 @@ struct rt2x00_chip {
188#define RT3071 0x3071 188#define RT3071 0x3071
189#define RT3090 0x3090 /* 2.4GHz PCIe */ 189#define RT3090 0x3090 /* 2.4GHz PCIe */
190#define RT3290 0x3290 190#define RT3290 0x3290
191#define RT3352 0x3352 /* WSOC */
191#define RT3390 0x3390 192#define RT3390 0x3390
192#define RT3572 0x3572 193#define RT3572 0x3572
193#define RT3593 0x3593 194#define RT3593 0x3593