diff options
author | John W. Linville <linville@tuxdriver.com> | 2011-06-08 13:44:21 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2011-06-08 13:44:21 -0400 |
commit | c0c33addcba2ce753b4e2746db99feaae2f82a85 (patch) | |
tree | dab480183ac0e64bfe9250e1f294705d1a424c78 /drivers/net/wireless/rt2x00/rt2800lib.c | |
parent | ffbc03bc75b39c7bd412e7cc6d2185c11b0ffedd (diff) | |
parent | 931749bf78b969c54de9bbc67cf29b13a40bb73b (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless-next-2.6 into for-davem
Diffstat (limited to 'drivers/net/wireless/rt2x00/rt2800lib.c')
-rw-r--r-- | drivers/net/wireless/rt2x00/rt2800lib.c | 376 |
1 files changed, 285 insertions, 91 deletions
diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c index 8f92dfcb08df..84ab7d1acb6a 100644 --- a/drivers/net/wireless/rt2x00/rt2800lib.c +++ b/drivers/net/wireless/rt2x00/rt2800lib.c | |||
@@ -401,7 +401,8 @@ int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev, | |||
401 | return -EBUSY; | 401 | return -EBUSY; |
402 | 402 | ||
403 | if (rt2x00_is_pci(rt2x00dev)) { | 403 | if (rt2x00_is_pci(rt2x00dev)) { |
404 | if (rt2x00_rt(rt2x00dev, RT5390)) { | 404 | if (rt2x00_rt(rt2x00dev, RT3572) || |
405 | rt2x00_rt(rt2x00dev, RT5390)) { | ||
405 | rt2800_register_read(rt2x00dev, AUX_CTRL, ®); | 406 | rt2800_register_read(rt2x00dev, AUX_CTRL, ®); |
406 | rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); | 407 | rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); |
407 | rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); | 408 | rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); |
@@ -600,49 +601,6 @@ void rt2800_process_rxwi(struct queue_entry *entry, | |||
600 | } | 601 | } |
601 | EXPORT_SYMBOL_GPL(rt2800_process_rxwi); | 602 | EXPORT_SYMBOL_GPL(rt2800_process_rxwi); |
602 | 603 | ||
603 | static bool rt2800_txdone_entry_check(struct queue_entry *entry, u32 reg) | ||
604 | { | ||
605 | __le32 *txwi; | ||
606 | u32 word; | ||
607 | int wcid, ack, pid; | ||
608 | int tx_wcid, tx_ack, tx_pid; | ||
609 | |||
610 | wcid = rt2x00_get_field32(reg, TX_STA_FIFO_WCID); | ||
611 | ack = rt2x00_get_field32(reg, TX_STA_FIFO_TX_ACK_REQUIRED); | ||
612 | pid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE); | ||
613 | |||
614 | /* | ||
615 | * This frames has returned with an IO error, | ||
616 | * so the status report is not intended for this | ||
617 | * frame. | ||
618 | */ | ||
619 | if (test_bit(ENTRY_DATA_IO_FAILED, &entry->flags)) { | ||
620 | rt2x00lib_txdone_noinfo(entry, TXDONE_FAILURE); | ||
621 | return false; | ||
622 | } | ||
623 | |||
624 | /* | ||
625 | * Validate if this TX status report is intended for | ||
626 | * this entry by comparing the WCID/ACK/PID fields. | ||
627 | */ | ||
628 | txwi = rt2800_drv_get_txwi(entry); | ||
629 | |||
630 | rt2x00_desc_read(txwi, 1, &word); | ||
631 | tx_wcid = rt2x00_get_field32(word, TXWI_W1_WIRELESS_CLI_ID); | ||
632 | tx_ack = rt2x00_get_field32(word, TXWI_W1_ACK); | ||
633 | tx_pid = rt2x00_get_field32(word, TXWI_W1_PACKETID); | ||
634 | |||
635 | if ((wcid != tx_wcid) || (ack != tx_ack) || (pid != tx_pid)) { | ||
636 | WARNING(entry->queue->rt2x00dev, | ||
637 | "TX status report missed for queue %d entry %d\n", | ||
638 | entry->queue->qid, entry->entry_idx); | ||
639 | rt2x00lib_txdone_noinfo(entry, TXDONE_UNKNOWN); | ||
640 | return false; | ||
641 | } | ||
642 | |||
643 | return true; | ||
644 | } | ||
645 | |||
646 | void rt2800_txdone_entry(struct queue_entry *entry, u32 status) | 604 | void rt2800_txdone_entry(struct queue_entry *entry, u32 status) |
647 | { | 605 | { |
648 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | 606 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
@@ -725,45 +683,6 @@ void rt2800_txdone_entry(struct queue_entry *entry, u32 status) | |||
725 | } | 683 | } |
726 | EXPORT_SYMBOL_GPL(rt2800_txdone_entry); | 684 | EXPORT_SYMBOL_GPL(rt2800_txdone_entry); |
727 | 685 | ||
728 | void rt2800_txdone(struct rt2x00_dev *rt2x00dev) | ||
729 | { | ||
730 | struct data_queue *queue; | ||
731 | struct queue_entry *entry; | ||
732 | u32 reg; | ||
733 | u8 qid; | ||
734 | |||
735 | while (kfifo_get(&rt2x00dev->txstatus_fifo, ®)) { | ||
736 | |||
737 | /* TX_STA_FIFO_PID_QUEUE is a 2-bit field, thus | ||
738 | * qid is guaranteed to be one of the TX QIDs | ||
739 | */ | ||
740 | qid = rt2x00_get_field32(reg, TX_STA_FIFO_PID_QUEUE); | ||
741 | queue = rt2x00queue_get_tx_queue(rt2x00dev, qid); | ||
742 | if (unlikely(!queue)) { | ||
743 | WARNING(rt2x00dev, "Got TX status for an unavailable " | ||
744 | "queue %u, dropping\n", qid); | ||
745 | continue; | ||
746 | } | ||
747 | |||
748 | /* | ||
749 | * Inside each queue, we process each entry in a chronological | ||
750 | * order. We first check that the queue is not empty. | ||
751 | */ | ||
752 | entry = NULL; | ||
753 | while (!rt2x00queue_empty(queue)) { | ||
754 | entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE); | ||
755 | if (rt2800_txdone_entry_check(entry, reg)) | ||
756 | break; | ||
757 | } | ||
758 | |||
759 | if (!entry || rt2x00queue_empty(queue)) | ||
760 | break; | ||
761 | |||
762 | rt2800_txdone_entry(entry, reg); | ||
763 | } | ||
764 | } | ||
765 | EXPORT_SYMBOL_GPL(rt2800_txdone); | ||
766 | |||
767 | void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) | 686 | void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc) |
768 | { | 687 | { |
769 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; | 688 | struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; |
@@ -1433,6 +1352,40 @@ void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp, | |||
1433 | } | 1352 | } |
1434 | EXPORT_SYMBOL_GPL(rt2800_config_erp); | 1353 | EXPORT_SYMBOL_GPL(rt2800_config_erp); |
1435 | 1354 | ||
1355 | static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev) | ||
1356 | { | ||
1357 | u32 reg; | ||
1358 | u16 eeprom; | ||
1359 | u8 led_ctrl, led_g_mode, led_r_mode; | ||
1360 | |||
1361 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); | ||
1362 | if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) { | ||
1363 | rt2x00_set_field32(®, GPIO_SWITCH_0, 1); | ||
1364 | rt2x00_set_field32(®, GPIO_SWITCH_1, 1); | ||
1365 | } else { | ||
1366 | rt2x00_set_field32(®, GPIO_SWITCH_0, 0); | ||
1367 | rt2x00_set_field32(®, GPIO_SWITCH_1, 0); | ||
1368 | } | ||
1369 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); | ||
1370 | |||
1371 | rt2800_register_read(rt2x00dev, LED_CFG, ®); | ||
1372 | led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0; | ||
1373 | led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3; | ||
1374 | if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) || | ||
1375 | led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) { | ||
1376 | rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom); | ||
1377 | led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE); | ||
1378 | if (led_ctrl == 0 || led_ctrl > 0x40) { | ||
1379 | rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode); | ||
1380 | rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode); | ||
1381 | rt2800_register_write(rt2x00dev, LED_CFG, reg); | ||
1382 | } else { | ||
1383 | rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff, | ||
1384 | (led_g_mode << 2) | led_r_mode, 1); | ||
1385 | } | ||
1386 | } | ||
1387 | } | ||
1388 | |||
1436 | static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, | 1389 | static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev, |
1437 | enum antenna ant) | 1390 | enum antenna ant) |
1438 | { | 1391 | { |
@@ -1463,6 +1416,10 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) | |||
1463 | rt2800_bbp_read(rt2x00dev, 1, &r1); | 1416 | rt2800_bbp_read(rt2x00dev, 1, &r1); |
1464 | rt2800_bbp_read(rt2x00dev, 3, &r3); | 1417 | rt2800_bbp_read(rt2x00dev, 3, &r3); |
1465 | 1418 | ||
1419 | if (rt2x00_rt(rt2x00dev, RT3572) && | ||
1420 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) | ||
1421 | rt2800_config_3572bt_ant(rt2x00dev); | ||
1422 | |||
1466 | /* | 1423 | /* |
1467 | * Configure the TX antenna. | 1424 | * Configure the TX antenna. |
1468 | */ | 1425 | */ |
@@ -1471,7 +1428,11 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) | |||
1471 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); | 1428 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); |
1472 | break; | 1429 | break; |
1473 | case 2: | 1430 | case 2: |
1474 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); | 1431 | if (rt2x00_rt(rt2x00dev, RT3572) && |
1432 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) | ||
1433 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1); | ||
1434 | else | ||
1435 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2); | ||
1475 | break; | 1436 | break; |
1476 | case 3: | 1437 | case 3: |
1477 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); | 1438 | rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0); |
@@ -1496,7 +1457,15 @@ void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant) | |||
1496 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); | 1457 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0); |
1497 | break; | 1458 | break; |
1498 | case 2: | 1459 | case 2: |
1499 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); | 1460 | if (rt2x00_rt(rt2x00dev, RT3572) && |
1461 | test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { | ||
1462 | rt2x00_set_field8(&r3, BBP3_RX_ADC, 1); | ||
1463 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, | ||
1464 | rt2x00dev->curr_band == IEEE80211_BAND_5GHZ); | ||
1465 | rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B); | ||
1466 | } else { | ||
1467 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1); | ||
1468 | } | ||
1500 | break; | 1469 | break; |
1501 | case 3: | 1470 | case 3: |
1502 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); | 1471 | rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2); |
@@ -1630,6 +1599,161 @@ static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev, | |||
1630 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); | 1599 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); |
1631 | } | 1600 | } |
1632 | 1601 | ||
1602 | static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev, | ||
1603 | struct ieee80211_conf *conf, | ||
1604 | struct rf_channel *rf, | ||
1605 | struct channel_info *info) | ||
1606 | { | ||
1607 | u8 rfcsr; | ||
1608 | u32 reg; | ||
1609 | |||
1610 | if (rf->channel <= 14) { | ||
1611 | rt2800_bbp_write(rt2x00dev, 25, 0x15); | ||
1612 | rt2800_bbp_write(rt2x00dev, 26, 0x85); | ||
1613 | } else { | ||
1614 | rt2800_bbp_write(rt2x00dev, 25, 0x09); | ||
1615 | rt2800_bbp_write(rt2x00dev, 26, 0xff); | ||
1616 | } | ||
1617 | |||
1618 | rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1); | ||
1619 | rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3); | ||
1620 | |||
1621 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | ||
1622 | rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2); | ||
1623 | if (rf->channel <= 14) | ||
1624 | rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2); | ||
1625 | else | ||
1626 | rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1); | ||
1627 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); | ||
1628 | |||
1629 | rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr); | ||
1630 | if (rf->channel <= 14) | ||
1631 | rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1); | ||
1632 | else | ||
1633 | rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2); | ||
1634 | rt2800_rfcsr_write(rt2x00dev, 5, rfcsr); | ||
1635 | |||
1636 | rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr); | ||
1637 | if (rf->channel <= 14) { | ||
1638 | rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3); | ||
1639 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, | ||
1640 | (info->default_power1 & 0x3) | | ||
1641 | ((info->default_power1 & 0xC) << 1)); | ||
1642 | } else { | ||
1643 | rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7); | ||
1644 | rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, | ||
1645 | (info->default_power1 & 0x3) | | ||
1646 | ((info->default_power1 & 0xC) << 1)); | ||
1647 | } | ||
1648 | rt2800_rfcsr_write(rt2x00dev, 12, rfcsr); | ||
1649 | |||
1650 | rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr); | ||
1651 | if (rf->channel <= 14) { | ||
1652 | rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3); | ||
1653 | rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, | ||
1654 | (info->default_power2 & 0x3) | | ||
1655 | ((info->default_power2 & 0xC) << 1)); | ||
1656 | } else { | ||
1657 | rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7); | ||
1658 | rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, | ||
1659 | (info->default_power2 & 0x3) | | ||
1660 | ((info->default_power2 & 0xC) << 1)); | ||
1661 | } | ||
1662 | rt2800_rfcsr_write(rt2x00dev, 13, rfcsr); | ||
1663 | |||
1664 | rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr); | ||
1665 | rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1); | ||
1666 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0); | ||
1667 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0); | ||
1668 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0); | ||
1669 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0); | ||
1670 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) { | ||
1671 | if (rf->channel <= 14) { | ||
1672 | rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1); | ||
1673 | rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1); | ||
1674 | } | ||
1675 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); | ||
1676 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); | ||
1677 | } else { | ||
1678 | switch (rt2x00dev->default_ant.tx_chain_num) { | ||
1679 | case 1: | ||
1680 | rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1); | ||
1681 | case 2: | ||
1682 | rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1); | ||
1683 | break; | ||
1684 | } | ||
1685 | |||
1686 | switch (rt2x00dev->default_ant.rx_chain_num) { | ||
1687 | case 1: | ||
1688 | rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1); | ||
1689 | case 2: | ||
1690 | rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1); | ||
1691 | break; | ||
1692 | } | ||
1693 | } | ||
1694 | rt2800_rfcsr_write(rt2x00dev, 1, rfcsr); | ||
1695 | |||
1696 | rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr); | ||
1697 | rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset); | ||
1698 | rt2800_rfcsr_write(rt2x00dev, 23, rfcsr); | ||
1699 | |||
1700 | rt2800_rfcsr_write(rt2x00dev, 24, | ||
1701 | rt2x00dev->calibration[conf_is_ht40(conf)]); | ||
1702 | rt2800_rfcsr_write(rt2x00dev, 31, | ||
1703 | rt2x00dev->calibration[conf_is_ht40(conf)]); | ||
1704 | |||
1705 | if (rf->channel <= 14) { | ||
1706 | rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); | ||
1707 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); | ||
1708 | rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); | ||
1709 | rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); | ||
1710 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); | ||
1711 | rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); | ||
1712 | rt2800_rfcsr_write(rt2x00dev, 17, 0x23); | ||
1713 | rt2800_rfcsr_write(rt2x00dev, 19, 0x93); | ||
1714 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); | ||
1715 | rt2800_rfcsr_write(rt2x00dev, 25, 0x15); | ||
1716 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | ||
1717 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | ||
1718 | rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); | ||
1719 | } else { | ||
1720 | rt2800_rfcsr_write(rt2x00dev, 7, 0x14); | ||
1721 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc0); | ||
1722 | rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); | ||
1723 | rt2800_rfcsr_write(rt2x00dev, 11, 0x00); | ||
1724 | rt2800_rfcsr_write(rt2x00dev, 15, 0x43); | ||
1725 | rt2800_rfcsr_write(rt2x00dev, 16, 0x7a); | ||
1726 | rt2800_rfcsr_write(rt2x00dev, 17, 0x23); | ||
1727 | if (rf->channel <= 64) { | ||
1728 | rt2800_rfcsr_write(rt2x00dev, 19, 0xb7); | ||
1729 | rt2800_rfcsr_write(rt2x00dev, 20, 0xf6); | ||
1730 | rt2800_rfcsr_write(rt2x00dev, 25, 0x3d); | ||
1731 | } else if (rf->channel <= 128) { | ||
1732 | rt2800_rfcsr_write(rt2x00dev, 19, 0x74); | ||
1733 | rt2800_rfcsr_write(rt2x00dev, 20, 0xf4); | ||
1734 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | ||
1735 | } else { | ||
1736 | rt2800_rfcsr_write(rt2x00dev, 19, 0x72); | ||
1737 | rt2800_rfcsr_write(rt2x00dev, 20, 0xf3); | ||
1738 | rt2800_rfcsr_write(rt2x00dev, 25, 0x01); | ||
1739 | } | ||
1740 | rt2800_rfcsr_write(rt2x00dev, 26, 0x87); | ||
1741 | rt2800_rfcsr_write(rt2x00dev, 27, 0x01); | ||
1742 | rt2800_rfcsr_write(rt2x00dev, 29, 0x9f); | ||
1743 | } | ||
1744 | |||
1745 | rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®); | ||
1746 | rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT7, 0); | ||
1747 | if (rf->channel <= 14) | ||
1748 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT7, 1); | ||
1749 | else | ||
1750 | rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT7, 0); | ||
1751 | rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg); | ||
1752 | |||
1753 | rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr); | ||
1754 | rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1); | ||
1755 | rt2800_rfcsr_write(rt2x00dev, 7, rfcsr); | ||
1756 | } | ||
1633 | 1757 | ||
1634 | #define RT5390_POWER_BOUND 0x27 | 1758 | #define RT5390_POWER_BOUND 0x27 |
1635 | #define RT5390_FREQ_OFFSET_BOUND 0x5f | 1759 | #define RT5390_FREQ_OFFSET_BOUND 0x5f |
@@ -1748,9 +1872,10 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, | |||
1748 | rt2x00_rf(rt2x00dev, RF3020) || | 1872 | rt2x00_rf(rt2x00dev, RF3020) || |
1749 | rt2x00_rf(rt2x00dev, RF3021) || | 1873 | rt2x00_rf(rt2x00dev, RF3021) || |
1750 | rt2x00_rf(rt2x00dev, RF3022) || | 1874 | rt2x00_rf(rt2x00dev, RF3022) || |
1751 | rt2x00_rf(rt2x00dev, RF3052) || | ||
1752 | rt2x00_rf(rt2x00dev, RF3320)) | 1875 | rt2x00_rf(rt2x00dev, RF3320)) |
1753 | rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); | 1876 | rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info); |
1877 | else if (rt2x00_rf(rt2x00dev, RF3052)) | ||
1878 | rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); | ||
1754 | else if (rt2x00_rf(rt2x00dev, RF5370) || | 1879 | else if (rt2x00_rf(rt2x00dev, RF5370) || |
1755 | rt2x00_rf(rt2x00dev, RF5390)) | 1880 | rt2x00_rf(rt2x00dev, RF5390)) |
1756 | rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); | 1881 | rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); |
@@ -1777,7 +1902,10 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, | |||
1777 | } | 1902 | } |
1778 | } | 1903 | } |
1779 | } else { | 1904 | } else { |
1780 | rt2800_bbp_write(rt2x00dev, 82, 0xf2); | 1905 | if (rt2x00_rt(rt2x00dev, RT3572)) |
1906 | rt2800_bbp_write(rt2x00dev, 82, 0x94); | ||
1907 | else | ||
1908 | rt2800_bbp_write(rt2x00dev, 82, 0xf2); | ||
1781 | 1909 | ||
1782 | if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) | 1910 | if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags)) |
1783 | rt2800_bbp_write(rt2x00dev, 75, 0x46); | 1911 | rt2800_bbp_write(rt2x00dev, 75, 0x46); |
@@ -1791,12 +1919,17 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, | |||
1791 | rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); | 1919 | rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14); |
1792 | rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); | 1920 | rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg); |
1793 | 1921 | ||
1922 | if (rt2x00_rt(rt2x00dev, RT3572)) | ||
1923 | rt2800_rfcsr_write(rt2x00dev, 8, 0); | ||
1924 | |||
1794 | tx_pin = 0; | 1925 | tx_pin = 0; |
1795 | 1926 | ||
1796 | /* Turn on unused PA or LNA when not using 1T or 1R */ | 1927 | /* Turn on unused PA or LNA when not using 1T or 1R */ |
1797 | if (rt2x00dev->default_ant.tx_chain_num == 2) { | 1928 | if (rt2x00dev->default_ant.tx_chain_num == 2) { |
1798 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1); | 1929 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, |
1799 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1); | 1930 | rf->channel > 14); |
1931 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, | ||
1932 | rf->channel <= 14); | ||
1800 | } | 1933 | } |
1801 | 1934 | ||
1802 | /* Turn on unused PA or LNA when not using 1T or 1R */ | 1935 | /* Turn on unused PA or LNA when not using 1T or 1R */ |
@@ -1809,11 +1942,18 @@ static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev, | |||
1809 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); | 1942 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1); |
1810 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); | 1943 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1); |
1811 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); | 1944 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1); |
1812 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14); | 1945 | if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) |
1946 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1); | ||
1947 | else | ||
1948 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, | ||
1949 | rf->channel <= 14); | ||
1813 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14); | 1950 | rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14); |
1814 | 1951 | ||
1815 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); | 1952 | rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin); |
1816 | 1953 | ||
1954 | if (rt2x00_rt(rt2x00dev, RT3572)) | ||
1955 | rt2800_rfcsr_write(rt2x00dev, 8, 0x80); | ||
1956 | |||
1817 | rt2800_bbp_read(rt2x00dev, 4, &bbp); | 1957 | rt2800_bbp_read(rt2x00dev, 4, &bbp); |
1818 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); | 1958 | rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf)); |
1819 | rt2800_bbp_write(rt2x00dev, 4, bbp); | 1959 | rt2800_bbp_write(rt2x00dev, 4, bbp); |
@@ -2413,6 +2553,9 @@ static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev) | |||
2413 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); | 2553 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); |
2414 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); | 2554 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000); |
2415 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); | 2555 | rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030); |
2556 | } else if (rt2x00_rt(rt2x00dev, RT3572)) { | ||
2557 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); | ||
2558 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | ||
2416 | } else if (rt2x00_rt(rt2x00dev, RT5390)) { | 2559 | } else if (rt2x00_rt(rt2x00dev, RT5390)) { |
2417 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); | 2560 | rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); |
2418 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); | 2561 | rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); |
@@ -2799,6 +2942,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) | |||
2799 | } | 2942 | } |
2800 | 2943 | ||
2801 | if (rt2800_is_305x_soc(rt2x00dev) || | 2944 | if (rt2800_is_305x_soc(rt2x00dev) || |
2945 | rt2x00_rt(rt2x00dev, RT3572) || | ||
2802 | rt2x00_rt(rt2x00dev, RT5390)) | 2946 | rt2x00_rt(rt2x00dev, RT5390)) |
2803 | rt2800_bbp_write(rt2x00dev, 31, 0x08); | 2947 | rt2800_bbp_write(rt2x00dev, 31, 0x08); |
2804 | 2948 | ||
@@ -2828,6 +2972,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) | |||
2828 | rt2x00_rt(rt2x00dev, RT3071) || | 2972 | rt2x00_rt(rt2x00dev, RT3071) || |
2829 | rt2x00_rt(rt2x00dev, RT3090) || | 2973 | rt2x00_rt(rt2x00dev, RT3090) || |
2830 | rt2x00_rt(rt2x00dev, RT3390) || | 2974 | rt2x00_rt(rt2x00dev, RT3390) || |
2975 | rt2x00_rt(rt2x00dev, RT3572) || | ||
2831 | rt2x00_rt(rt2x00dev, RT5390)) { | 2976 | rt2x00_rt(rt2x00dev, RT5390)) { |
2832 | rt2800_bbp_write(rt2x00dev, 79, 0x13); | 2977 | rt2800_bbp_write(rt2x00dev, 79, 0x13); |
2833 | rt2800_bbp_write(rt2x00dev, 80, 0x05); | 2978 | rt2800_bbp_write(rt2x00dev, 80, 0x05); |
@@ -2868,6 +3013,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) | |||
2868 | rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || | 3013 | rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) || |
2869 | rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || | 3014 | rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) || |
2870 | rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || | 3015 | rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) || |
3016 | rt2x00_rt(rt2x00dev, RT3572) || | ||
2871 | rt2x00_rt(rt2x00dev, RT5390) || | 3017 | rt2x00_rt(rt2x00dev, RT5390) || |
2872 | rt2800_is_305x_soc(rt2x00dev)) | 3018 | rt2800_is_305x_soc(rt2x00dev)) |
2873 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); | 3019 | rt2800_bbp_write(rt2x00dev, 103, 0xc0); |
@@ -2895,6 +3041,7 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) | |||
2895 | if (rt2x00_rt(rt2x00dev, RT3071) || | 3041 | if (rt2x00_rt(rt2x00dev, RT3071) || |
2896 | rt2x00_rt(rt2x00dev, RT3090) || | 3042 | rt2x00_rt(rt2x00dev, RT3090) || |
2897 | rt2x00_rt(rt2x00dev, RT3390) || | 3043 | rt2x00_rt(rt2x00dev, RT3390) || |
3044 | rt2x00_rt(rt2x00dev, RT3572) || | ||
2898 | rt2x00_rt(rt2x00dev, RT5390)) { | 3045 | rt2x00_rt(rt2x00dev, RT5390)) { |
2899 | rt2800_bbp_read(rt2x00dev, 138, &value); | 3046 | rt2800_bbp_read(rt2x00dev, 138, &value); |
2900 | 3047 | ||
@@ -3031,6 +3178,7 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) | |||
3031 | !rt2x00_rt(rt2x00dev, RT3071) && | 3178 | !rt2x00_rt(rt2x00dev, RT3071) && |
3032 | !rt2x00_rt(rt2x00dev, RT3090) && | 3179 | !rt2x00_rt(rt2x00dev, RT3090) && |
3033 | !rt2x00_rt(rt2x00dev, RT3390) && | 3180 | !rt2x00_rt(rt2x00dev, RT3390) && |
3181 | !rt2x00_rt(rt2x00dev, RT3572) && | ||
3034 | !rt2x00_rt(rt2x00dev, RT5390) && | 3182 | !rt2x00_rt(rt2x00dev, RT5390) && |
3035 | !rt2800_is_305x_soc(rt2x00dev)) | 3183 | !rt2800_is_305x_soc(rt2x00dev)) |
3036 | return 0; | 3184 | return 0; |
@@ -3109,6 +3257,38 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) | |||
3109 | rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); | 3257 | rt2800_rfcsr_write(rt2x00dev, 29, 0x8f); |
3110 | rt2800_rfcsr_write(rt2x00dev, 30, 0x20); | 3258 | rt2800_rfcsr_write(rt2x00dev, 30, 0x20); |
3111 | rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); | 3259 | rt2800_rfcsr_write(rt2x00dev, 31, 0x0f); |
3260 | } else if (rt2x00_rt(rt2x00dev, RT3572)) { | ||
3261 | rt2800_rfcsr_write(rt2x00dev, 0, 0x70); | ||
3262 | rt2800_rfcsr_write(rt2x00dev, 1, 0x81); | ||
3263 | rt2800_rfcsr_write(rt2x00dev, 2, 0xf1); | ||
3264 | rt2800_rfcsr_write(rt2x00dev, 3, 0x02); | ||
3265 | rt2800_rfcsr_write(rt2x00dev, 4, 0x4c); | ||
3266 | rt2800_rfcsr_write(rt2x00dev, 5, 0x05); | ||
3267 | rt2800_rfcsr_write(rt2x00dev, 6, 0x4a); | ||
3268 | rt2800_rfcsr_write(rt2x00dev, 7, 0xd8); | ||
3269 | rt2800_rfcsr_write(rt2x00dev, 9, 0xc3); | ||
3270 | rt2800_rfcsr_write(rt2x00dev, 10, 0xf1); | ||
3271 | rt2800_rfcsr_write(rt2x00dev, 11, 0xb9); | ||
3272 | rt2800_rfcsr_write(rt2x00dev, 12, 0x70); | ||
3273 | rt2800_rfcsr_write(rt2x00dev, 13, 0x65); | ||
3274 | rt2800_rfcsr_write(rt2x00dev, 14, 0xa0); | ||
3275 | rt2800_rfcsr_write(rt2x00dev, 15, 0x53); | ||
3276 | rt2800_rfcsr_write(rt2x00dev, 16, 0x4c); | ||
3277 | rt2800_rfcsr_write(rt2x00dev, 17, 0x23); | ||
3278 | rt2800_rfcsr_write(rt2x00dev, 18, 0xac); | ||
3279 | rt2800_rfcsr_write(rt2x00dev, 19, 0x93); | ||
3280 | rt2800_rfcsr_write(rt2x00dev, 20, 0xb3); | ||
3281 | rt2800_rfcsr_write(rt2x00dev, 21, 0xd0); | ||
3282 | rt2800_rfcsr_write(rt2x00dev, 22, 0x00); | ||
3283 | rt2800_rfcsr_write(rt2x00dev, 23, 0x3c); | ||
3284 | rt2800_rfcsr_write(rt2x00dev, 24, 0x16); | ||
3285 | rt2800_rfcsr_write(rt2x00dev, 25, 0x15); | ||
3286 | rt2800_rfcsr_write(rt2x00dev, 26, 0x85); | ||
3287 | rt2800_rfcsr_write(rt2x00dev, 27, 0x00); | ||
3288 | rt2800_rfcsr_write(rt2x00dev, 28, 0x00); | ||
3289 | rt2800_rfcsr_write(rt2x00dev, 29, 0x9b); | ||
3290 | rt2800_rfcsr_write(rt2x00dev, 30, 0x09); | ||
3291 | rt2800_rfcsr_write(rt2x00dev, 31, 0x10); | ||
3112 | } else if (rt2800_is_305x_soc(rt2x00dev)) { | 3292 | } else if (rt2800_is_305x_soc(rt2x00dev)) { |
3113 | rt2800_rfcsr_write(rt2x00dev, 0, 0x50); | 3293 | rt2800_rfcsr_write(rt2x00dev, 0, 0x50); |
3114 | rt2800_rfcsr_write(rt2x00dev, 1, 0x01); | 3294 | rt2800_rfcsr_write(rt2x00dev, 1, 0x01); |
@@ -3258,6 +3438,19 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) | |||
3258 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); | 3438 | rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®); |
3259 | rt2x00_set_field32(®, GPIO_SWITCH_5, 0); | 3439 | rt2x00_set_field32(®, GPIO_SWITCH_5, 0); |
3260 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); | 3440 | rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg); |
3441 | } else if (rt2x00_rt(rt2x00dev, RT3572)) { | ||
3442 | rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr); | ||
3443 | rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1); | ||
3444 | rt2800_rfcsr_write(rt2x00dev, 6, rfcsr); | ||
3445 | |||
3446 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | ||
3447 | rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3); | ||
3448 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | ||
3449 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | ||
3450 | msleep(1); | ||
3451 | rt2800_register_read(rt2x00dev, LDO_CFG0, ®); | ||
3452 | rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1); | ||
3453 | rt2800_register_write(rt2x00dev, LDO_CFG0, reg); | ||
3261 | } | 3454 | } |
3262 | 3455 | ||
3263 | /* | 3456 | /* |
@@ -3270,7 +3463,8 @@ static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev) | |||
3270 | rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); | 3463 | rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19); |
3271 | } else if (rt2x00_rt(rt2x00dev, RT3071) || | 3464 | } else if (rt2x00_rt(rt2x00dev, RT3071) || |
3272 | rt2x00_rt(rt2x00dev, RT3090) || | 3465 | rt2x00_rt(rt2x00dev, RT3090) || |
3273 | rt2x00_rt(rt2x00dev, RT3390)) { | 3466 | rt2x00_rt(rt2x00dev, RT3390) || |
3467 | rt2x00_rt(rt2x00dev, RT3572)) { | ||
3274 | rt2x00dev->calibration[0] = | 3468 | rt2x00dev->calibration[0] = |
3275 | rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13); | 3469 | rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13); |
3276 | rt2x00dev->calibration[1] = | 3470 | rt2x00dev->calibration[1] = |