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authorEmmanuel Grumbach <emmanuel.grumbach@intel.com>2012-05-29 04:29:10 -0400
committerJohannes Berg <johannes.berg@intel.com>2012-06-06 07:21:20 -0400
commit4beaf6c2f8af52902bcd55b51f9ff8c8f547d485 (patch)
treee8fcd906805d19ed08d84d2408a760d876e1a8da /drivers/net/wireless/iwlwifi/pcie/trans.c
parentd0624be65ade709ef1a4220451a474be1ad01af9 (diff)
iwlwifi: s/txq_setup/txq_enable
We need to be able to enable / disable Tx queues in HW dynamically. So this function is no longer related to AGG only. It can do the job for any queue, even AC ones. Change the name to better reflect its role. Also use the new function to configure the AC / CMD queues in tx_start. Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/pcie/trans.c')
-rw-r--r--drivers/net/wireless/iwlwifi/pcie/trans.c29
1 files changed, 4 insertions, 25 deletions
diff --git a/drivers/net/wireless/iwlwifi/pcie/trans.c b/drivers/net/wireless/iwlwifi/pcie/trans.c
index 7c7702a48399..0f59e1f2bcac 100644
--- a/drivers/net/wireless/iwlwifi/pcie/trans.c
+++ b/drivers/net/wireless/iwlwifi/pcie/trans.c
@@ -1054,33 +1054,12 @@ static void iwl_tx_start(struct iwl_trans *trans)
1054 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR, 1054 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
1055 trans_pcie->scd_bc_tbls.dma >> 10); 1055 trans_pcie->scd_bc_tbls.dma >> 10);
1056 1056
1057 iwl_write_prph(trans, SCD_QUEUECHAIN_SEL,
1058 SCD_QUEUECHAIN_SEL_ALL(trans, trans_pcie));
1059 iwl_write_prph(trans, SCD_AGGR_SEL, 0);
1060
1061 /* initiate the queues */
1062 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1063 iwl_trans_set_wr_ptrs(trans, i, 0);
1064 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1065 SCD_CONTEXT_QUEUE_OFFSET(i), 0);
1066 iwl_write_targ_mem(trans, trans_pcie->scd_base_addr +
1067 SCD_CONTEXT_QUEUE_OFFSET(i) +
1068 sizeof(u32),
1069 ((SCD_WIN_SIZE <<
1070 SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1071 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1072 ((SCD_FRAME_LIMIT <<
1073 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1074 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1075 }
1076
1077 for (i = 0; i < trans_pcie->n_q_to_fifo; i++) { 1057 for (i = 0; i < trans_pcie->n_q_to_fifo; i++) {
1078 int fifo = trans_pcie->setup_q_to_fifo[i]; 1058 int fifo = trans_pcie->setup_q_to_fifo[i];
1079 1059
1080 set_bit(i, trans_pcie->queue_used); 1060 __iwl_trans_pcie_txq_enable(trans, i, fifo, IWL_INVALID_STATION,
1081 1061 IWL_TID_NON_QOS,
1082 iwl_trans_tx_queue_set_status(trans, &trans_pcie->txq[i], 1062 SCD_FRAME_LIMIT, 0);
1083 fifo, true);
1084 } 1063 }
1085 1064
1086 /* Activate all Tx DMA/FIFO channels */ 1065 /* Activate all Tx DMA/FIFO channels */
@@ -2040,7 +2019,7 @@ static const struct iwl_trans_ops trans_ops_pcie = {
2040 .reclaim = iwl_trans_pcie_reclaim, 2019 .reclaim = iwl_trans_pcie_reclaim,
2041 2020
2042 .txq_disable = iwl_trans_pcie_txq_disable, 2021 .txq_disable = iwl_trans_pcie_txq_disable,
2043 .tx_agg_setup = iwl_trans_pcie_tx_agg_setup, 2022 .txq_enable = iwl_trans_pcie_txq_enable,
2044 2023
2045 .dbgfs_register = iwl_trans_pcie_dbgfs_register, 2024 .dbgfs_register = iwl_trans_pcie_dbgfs_register,
2046 2025