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authorWey-Yi Guy <wey-yi.w.guy@intel.com>2010-03-17 16:34:34 -0400
committerReinette Chatre <reinette.chatre@intel.com>2010-03-25 14:19:27 -0400
commit74bcdb33e99f49ef5202dd2f8109945b4570edc2 (patch)
tree0c1be859e04b0c460abd9cbf1f40571362c82956 /drivers/net/wireless/iwlwifi/iwl-tx.c
parent348ee7cd57831c47373dd157f138c558daaf129d (diff)
iwlwifi: move agn only tx functions from iwlcore to iwlagn
Identify the tx functions only used by agn driver and move those from iwlcore to iwlagn. Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-tx.c')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-tx.c1029
1 files changed, 0 insertions, 1029 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-tx.c b/drivers/net/wireless/iwlwifi/iwl-tx.c
index 34c983833a8f..91f9c89b1b6d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-tx.c
+++ b/drivers/net/wireless/iwlwifi/iwl-tx.c
@@ -37,84 +37,6 @@
37#include "iwl-io.h" 37#include "iwl-io.h"
38#include "iwl-helpers.h" 38#include "iwl-helpers.h"
39 39
40/*
41 * mac80211 queues, ACs, hardware queues, FIFOs.
42 *
43 * Cf. http://wireless.kernel.org/en/developers/Documentation/mac80211/queues
44 *
45 * Mac80211 uses the following numbers, which we get as from it
46 * by way of skb_get_queue_mapping(skb):
47 *
48 * VO 0
49 * VI 1
50 * BE 2
51 * BK 3
52 *
53 *
54 * Regular (not A-MPDU) frames are put into hardware queues corresponding
55 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their
56 * own queue per aggregation session (RA/TID combination), such queues are
57 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In
58 * order to map frames to the right queue, we also need an AC->hw queue
59 * mapping. This is implemented here.
60 *
61 * Due to the way hw queues are set up (by the hw specific modules like
62 * iwl-4965.c, iwl-5000.c etc.), the AC->hw queue mapping is the identity
63 * mapping.
64 */
65
66static const u8 tid_to_ac[] = {
67 /* this matches the mac80211 numbers */
68 2, 3, 3, 2, 1, 1, 0, 0
69};
70
71static const u8 ac_to_fifo[] = {
72 IWL_TX_FIFO_VO,
73 IWL_TX_FIFO_VI,
74 IWL_TX_FIFO_BE,
75 IWL_TX_FIFO_BK,
76};
77
78static inline int get_fifo_from_ac(u8 ac)
79{
80 return ac_to_fifo[ac];
81}
82
83static inline int get_queue_from_ac(u16 ac)
84{
85 return ac;
86}
87
88static inline int get_fifo_from_tid(u16 tid)
89{
90 if (likely(tid < ARRAY_SIZE(tid_to_ac)))
91 return get_fifo_from_ac(tid_to_ac[tid]);
92
93 /* no support for TIDs 8-15 yet */
94 return -EINVAL;
95}
96
97static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
98 struct iwl_dma_ptr *ptr, size_t size)
99{
100 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
101 GFP_KERNEL);
102 if (!ptr->addr)
103 return -ENOMEM;
104 ptr->size = size;
105 return 0;
106}
107
108static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
109 struct iwl_dma_ptr *ptr)
110{
111 if (unlikely(!ptr->addr))
112 return;
113
114 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
115 memset(ptr, 0, sizeof(*ptr));
116}
117
118/** 40/**
119 * iwl_txq_update_write_ptr - Send new write index to hardware 41 * iwl_txq_update_write_ptr - Send new write index to hardware
120 */ 42 */
@@ -448,579 +370,6 @@ out_free_arrays:
448} 370}
449EXPORT_SYMBOL(iwl_tx_queue_init); 371EXPORT_SYMBOL(iwl_tx_queue_init);
450 372
451/**
452 * iwl_hw_txq_ctx_free - Free TXQ Context
453 *
454 * Destroy all TX DMA queues and structures
455 */
456void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
457{
458 int txq_id;
459
460 /* Tx queues */
461 if (priv->txq) {
462 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
463 txq_id++)
464 if (txq_id == IWL_CMD_QUEUE_NUM)
465 iwl_cmd_queue_free(priv);
466 else
467 iwl_tx_queue_free(priv, txq_id);
468 }
469 iwl_free_dma_ptr(priv, &priv->kw);
470
471 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
472
473 /* free tx queue structure */
474 iwl_free_txq_mem(priv);
475}
476EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
477
478/**
479 * iwl_txq_ctx_reset - Reset TX queue context
480 * Destroys all DMA structures and initialize them again
481 *
482 * @param priv
483 * @return error code
484 */
485int iwl_txq_ctx_reset(struct iwl_priv *priv)
486{
487 int ret = 0;
488 int txq_id, slots_num;
489 unsigned long flags;
490
491 /* Free all tx/cmd queues and keep-warm buffer */
492 iwl_hw_txq_ctx_free(priv);
493
494 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
495 priv->hw_params.scd_bc_tbls_size);
496 if (ret) {
497 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
498 goto error_bc_tbls;
499 }
500 /* Alloc keep-warm buffer */
501 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
502 if (ret) {
503 IWL_ERR(priv, "Keep Warm allocation failed\n");
504 goto error_kw;
505 }
506
507 /* allocate tx queue structure */
508 ret = iwl_alloc_txq_mem(priv);
509 if (ret)
510 goto error;
511
512 spin_lock_irqsave(&priv->lock, flags);
513
514 /* Turn off all Tx DMA fifos */
515 priv->cfg->ops->lib->txq_set_sched(priv, 0);
516
517 /* Tell NIC where to find the "keep warm" buffer */
518 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
519
520 spin_unlock_irqrestore(&priv->lock, flags);
521
522 /* Alloc and init all Tx queues, including the command queue (#4) */
523 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
524 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
525 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
526 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
527 txq_id);
528 if (ret) {
529 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
530 goto error;
531 }
532 }
533
534 return ret;
535
536 error:
537 iwl_hw_txq_ctx_free(priv);
538 iwl_free_dma_ptr(priv, &priv->kw);
539 error_kw:
540 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
541 error_bc_tbls:
542 return ret;
543}
544
545/**
546 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
547 */
548void iwl_txq_ctx_stop(struct iwl_priv *priv)
549{
550 int ch;
551 unsigned long flags;
552
553 /* Turn off all Tx DMA fifos */
554 spin_lock_irqsave(&priv->lock, flags);
555
556 priv->cfg->ops->lib->txq_set_sched(priv, 0);
557
558 /* Stop each Tx DMA channel, and wait for it to be idle */
559 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
560 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
561 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
562 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
563 1000);
564 }
565 spin_unlock_irqrestore(&priv->lock, flags);
566
567 /* Deallocate memory for all Tx queues */
568 iwl_hw_txq_ctx_free(priv);
569}
570EXPORT_SYMBOL(iwl_txq_ctx_stop);
571
572/*
573 * handle build REPLY_TX command notification.
574 */
575static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
576 struct iwl_tx_cmd *tx_cmd,
577 struct ieee80211_tx_info *info,
578 struct ieee80211_hdr *hdr,
579 u8 std_id)
580{
581 __le16 fc = hdr->frame_control;
582 __le32 tx_flags = tx_cmd->tx_flags;
583
584 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
585 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
586 tx_flags |= TX_CMD_FLG_ACK_MSK;
587 if (ieee80211_is_mgmt(fc))
588 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
589 if (ieee80211_is_probe_resp(fc) &&
590 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
591 tx_flags |= TX_CMD_FLG_TSF_MSK;
592 } else {
593 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
594 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
595 }
596
597 if (ieee80211_is_back_req(fc))
598 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
599
600
601 tx_cmd->sta_id = std_id;
602 if (ieee80211_has_morefrags(fc))
603 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
604
605 if (ieee80211_is_data_qos(fc)) {
606 u8 *qc = ieee80211_get_qos_ctl(hdr);
607 tx_cmd->tid_tspec = qc[0] & 0xf;
608 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
609 } else {
610 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
611 }
612
613 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
614
615 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
616 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
617
618 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
619 if (ieee80211_is_mgmt(fc)) {
620 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
621 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
622 else
623 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
624 } else {
625 tx_cmd->timeout.pm_frame_timeout = 0;
626 }
627
628 tx_cmd->driver_txop = 0;
629 tx_cmd->tx_flags = tx_flags;
630 tx_cmd->next_frame_len = 0;
631}
632
633#define RTS_DFAULT_RETRY_LIMIT 60
634
635static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
636 struct iwl_tx_cmd *tx_cmd,
637 struct ieee80211_tx_info *info,
638 __le16 fc)
639{
640 u32 rate_flags;
641 int rate_idx;
642 u8 rts_retry_limit;
643 u8 data_retry_limit;
644 u8 rate_plcp;
645
646 /* Set retry limit on DATA packets and Probe Responses*/
647 if (ieee80211_is_probe_resp(fc))
648 data_retry_limit = 3;
649 else
650 data_retry_limit = IWL_DEFAULT_TX_RETRY;
651 tx_cmd->data_retry_limit = data_retry_limit;
652
653 /* Set retry limit on RTS packets */
654 rts_retry_limit = RTS_DFAULT_RETRY_LIMIT;
655 if (data_retry_limit < rts_retry_limit)
656 rts_retry_limit = data_retry_limit;
657 tx_cmd->rts_retry_limit = rts_retry_limit;
658
659 /* DATA packets will use the uCode station table for rate/antenna
660 * selection */
661 if (ieee80211_is_data(fc)) {
662 tx_cmd->initial_rate_index = 0;
663 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
664 return;
665 }
666
667 /**
668 * If the current TX rate stored in mac80211 has the MCS bit set, it's
669 * not really a TX rate. Thus, we use the lowest supported rate for
670 * this band. Also use the lowest supported rate if the stored rate
671 * index is invalid.
672 */
673 rate_idx = info->control.rates[0].idx;
674 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
675 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
676 rate_idx = rate_lowest_index(&priv->bands[info->band],
677 info->control.sta);
678 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
679 if (info->band == IEEE80211_BAND_5GHZ)
680 rate_idx += IWL_FIRST_OFDM_RATE;
681 /* Get PLCP rate for tx_cmd->rate_n_flags */
682 rate_plcp = iwl_rates[rate_idx].plcp;
683 /* Zero out flags for this packet */
684 rate_flags = 0;
685
686 /* Set CCK flag as needed */
687 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
688 rate_flags |= RATE_MCS_CCK_MSK;
689
690 /* Set up RTS and CTS flags for certain packets */
691 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
692 case cpu_to_le16(IEEE80211_STYPE_AUTH):
693 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
694 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
695 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
696 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
697 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
698 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
699 }
700 break;
701 default:
702 break;
703 }
704
705 /* Set up antennas */
706 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
707 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
708
709 /* Set the rate in the TX cmd */
710 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
711}
712
713static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
714 struct ieee80211_tx_info *info,
715 struct iwl_tx_cmd *tx_cmd,
716 struct sk_buff *skb_frag,
717 int sta_id)
718{
719 struct ieee80211_key_conf *keyconf = info->control.hw_key;
720
721 switch (keyconf->alg) {
722 case ALG_CCMP:
723 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
724 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
725 if (info->flags & IEEE80211_TX_CTL_AMPDU)
726 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
727 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
728 break;
729
730 case ALG_TKIP:
731 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
732 ieee80211_get_tkip_key(keyconf, skb_frag,
733 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
734 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
735 break;
736
737 case ALG_WEP:
738 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
739 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
740
741 if (keyconf->keylen == WEP_KEY_LEN_128)
742 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
743
744 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
745
746 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
747 "with key %d\n", keyconf->keyidx);
748 break;
749
750 default:
751 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
752 break;
753 }
754}
755
756/*
757 * start REPLY_TX command process
758 */
759int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
760{
761 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
762 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
763 struct ieee80211_sta *sta = info->control.sta;
764 struct iwl_station_priv *sta_priv = NULL;
765 struct iwl_tx_queue *txq;
766 struct iwl_queue *q;
767 struct iwl_device_cmd *out_cmd;
768 struct iwl_cmd_meta *out_meta;
769 struct iwl_tx_cmd *tx_cmd;
770 int swq_id, txq_id;
771 dma_addr_t phys_addr;
772 dma_addr_t txcmd_phys;
773 dma_addr_t scratch_phys;
774 u16 len, len_org, firstlen, secondlen;
775 u16 seq_number = 0;
776 __le16 fc;
777 u8 hdr_len;
778 u8 sta_id;
779 u8 wait_write_ptr = 0;
780 u8 tid = 0;
781 u8 *qc = NULL;
782 unsigned long flags;
783
784 spin_lock_irqsave(&priv->lock, flags);
785 if (iwl_is_rfkill(priv)) {
786 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
787 goto drop_unlock;
788 }
789
790 fc = hdr->frame_control;
791
792#ifdef CONFIG_IWLWIFI_DEBUG
793 if (ieee80211_is_auth(fc))
794 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
795 else if (ieee80211_is_assoc_req(fc))
796 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
797 else if (ieee80211_is_reassoc_req(fc))
798 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
799#endif
800
801 hdr_len = ieee80211_hdrlen(fc);
802
803 /* Find (or create) index into station table for destination station */
804 if (info->flags & IEEE80211_TX_CTL_INJECTED)
805 sta_id = priv->hw_params.bcast_sta_id;
806 else
807 sta_id = iwl_get_sta_id(priv, hdr);
808 if (sta_id == IWL_INVALID_STATION) {
809 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
810 hdr->addr1);
811 goto drop_unlock;
812 }
813
814 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
815
816 if (sta)
817 sta_priv = (void *)sta->drv_priv;
818
819 if (sta_priv && sta_id != priv->hw_params.bcast_sta_id &&
820 sta_priv->asleep) {
821 WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE));
822 /*
823 * This sends an asynchronous command to the device,
824 * but we can rely on it being processed before the
825 * next frame is processed -- and the next frame to
826 * this station is the one that will consume this
827 * counter.
828 * For now set the counter to just 1 since we do not
829 * support uAPSD yet.
830 */
831 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
832 }
833
834 txq_id = get_queue_from_ac(skb_get_queue_mapping(skb));
835 if (ieee80211_is_data_qos(fc)) {
836 qc = ieee80211_get_qos_ctl(hdr);
837 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
838 if (unlikely(tid >= MAX_TID_COUNT))
839 goto drop_unlock;
840 seq_number = priv->stations[sta_id].tid[tid].seq_number;
841 seq_number &= IEEE80211_SCTL_SEQ;
842 hdr->seq_ctrl = hdr->seq_ctrl &
843 cpu_to_le16(IEEE80211_SCTL_FRAG);
844 hdr->seq_ctrl |= cpu_to_le16(seq_number);
845 seq_number += 0x10;
846 /* aggregation is on for this <sta,tid> */
847 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
848 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
849 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
850 }
851 }
852
853 txq = &priv->txq[txq_id];
854 swq_id = txq->swq_id;
855 q = &txq->q;
856
857 if (unlikely(iwl_queue_space(q) < q->high_mark))
858 goto drop_unlock;
859
860 if (ieee80211_is_data_qos(fc))
861 priv->stations[sta_id].tid[tid].tfds_in_queue++;
862
863 /* Set up driver data for this TFD */
864 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
865 txq->txb[q->write_ptr].skb[0] = skb;
866
867 /* Set up first empty entry in queue's array of Tx/cmd buffers */
868 out_cmd = txq->cmd[q->write_ptr];
869 out_meta = &txq->meta[q->write_ptr];
870 tx_cmd = &out_cmd->cmd.tx;
871 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
872 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
873
874 /*
875 * Set up the Tx-command (not MAC!) header.
876 * Store the chosen Tx queue and TFD index within the sequence field;
877 * after Tx, uCode's Tx response will return this value so driver can
878 * locate the frame within the tx queue and do post-tx processing.
879 */
880 out_cmd->hdr.cmd = REPLY_TX;
881 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
882 INDEX_TO_SEQ(q->write_ptr)));
883
884 /* Copy MAC header from skb into command buffer */
885 memcpy(tx_cmd->hdr, hdr, hdr_len);
886
887
888 /* Total # bytes to be transmitted */
889 len = (u16)skb->len;
890 tx_cmd->len = cpu_to_le16(len);
891
892 if (info->control.hw_key)
893 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
894
895 /* TODO need this for burst mode later on */
896 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
897 iwl_dbg_log_tx_data_frame(priv, len, hdr);
898
899 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc);
900
901 iwl_update_stats(priv, true, fc, len);
902 /*
903 * Use the first empty entry in this queue's command buffer array
904 * to contain the Tx command and MAC header concatenated together
905 * (payload data will be in another buffer).
906 * Size of this varies, due to varying MAC header length.
907 * If end is not dword aligned, we'll have 2 extra bytes at the end
908 * of the MAC header (device reads on dword boundaries).
909 * We'll tell device about this padding later.
910 */
911 len = sizeof(struct iwl_tx_cmd) +
912 sizeof(struct iwl_cmd_header) + hdr_len;
913
914 len_org = len;
915 firstlen = len = (len + 3) & ~3;
916
917 if (len_org != len)
918 len_org = 1;
919 else
920 len_org = 0;
921
922 /* Tell NIC about any 2-byte padding after MAC header */
923 if (len_org)
924 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
925
926 /* Physical address of this Tx command's header (not MAC header!),
927 * within command buffer array. */
928 txcmd_phys = pci_map_single(priv->pci_dev,
929 &out_cmd->hdr, len,
930 PCI_DMA_BIDIRECTIONAL);
931 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
932 pci_unmap_len_set(out_meta, len, len);
933 /* Add buffer containing Tx command and MAC(!) header to TFD's
934 * first entry */
935 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
936 txcmd_phys, len, 1, 0);
937
938 if (!ieee80211_has_morefrags(hdr->frame_control)) {
939 txq->need_update = 1;
940 if (qc)
941 priv->stations[sta_id].tid[tid].seq_number = seq_number;
942 } else {
943 wait_write_ptr = 1;
944 txq->need_update = 0;
945 }
946
947 /* Set up TFD's 2nd entry to point directly to remainder of skb,
948 * if any (802.11 null frames have no payload). */
949 secondlen = len = skb->len - hdr_len;
950 if (len) {
951 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
952 len, PCI_DMA_TODEVICE);
953 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
954 phys_addr, len,
955 0, 0);
956 }
957
958 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
959 offsetof(struct iwl_tx_cmd, scratch);
960
961 len = sizeof(struct iwl_tx_cmd) +
962 sizeof(struct iwl_cmd_header) + hdr_len;
963 /* take back ownership of DMA buffer to enable update */
964 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
965 len, PCI_DMA_BIDIRECTIONAL);
966 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
967 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
968
969 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
970 le16_to_cpu(out_cmd->hdr.sequence));
971 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
972 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
973 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
974
975 /* Set up entry for this TFD in Tx byte-count array */
976 if (info->flags & IEEE80211_TX_CTL_AMPDU)
977 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
978 le16_to_cpu(tx_cmd->len));
979
980 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
981 len, PCI_DMA_BIDIRECTIONAL);
982
983 trace_iwlwifi_dev_tx(priv,
984 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
985 sizeof(struct iwl_tfd),
986 &out_cmd->hdr, firstlen,
987 skb->data + hdr_len, secondlen);
988
989 /* Tell device the write index *just past* this latest filled TFD */
990 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
991 iwl_txq_update_write_ptr(priv, txq);
992 spin_unlock_irqrestore(&priv->lock, flags);
993
994 /*
995 * At this point the frame is "transmitted" successfully
996 * and we will get a TX status notification eventually,
997 * regardless of the value of ret. "ret" only indicates
998 * whether or not we should update the write pointer.
999 */
1000
1001 /* avoid atomic ops if it isn't an associated client */
1002 if (sta_priv && sta_priv->client)
1003 atomic_inc(&sta_priv->pending_frames);
1004
1005 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
1006 if (wait_write_ptr) {
1007 spin_lock_irqsave(&priv->lock, flags);
1008 txq->need_update = 1;
1009 iwl_txq_update_write_ptr(priv, txq);
1010 spin_unlock_irqrestore(&priv->lock, flags);
1011 } else {
1012 iwl_stop_queue(priv, txq->swq_id);
1013 }
1014 }
1015
1016 return 0;
1017
1018drop_unlock:
1019 spin_unlock_irqrestore(&priv->lock, flags);
1020 return -1;
1021}
1022EXPORT_SYMBOL(iwl_tx_skb);
1023
1024/*************** HOST COMMAND QUEUE FUNCTIONS *****/ 373/*************** HOST COMMAND QUEUE FUNCTIONS *****/
1025 374
1026/** 375/**
@@ -1146,61 +495,6 @@ int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1146 return idx; 495 return idx;
1147} 496}
1148 497
1149static void iwl_tx_status(struct iwl_priv *priv, struct sk_buff *skb)
1150{
1151 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1152 struct ieee80211_sta *sta;
1153 struct iwl_station_priv *sta_priv;
1154
1155 sta = ieee80211_find_sta(priv->vif, hdr->addr1);
1156 if (sta) {
1157 sta_priv = (void *)sta->drv_priv;
1158 /* avoid atomic ops if this isn't a client */
1159 if (sta_priv->client &&
1160 atomic_dec_return(&sta_priv->pending_frames) == 0)
1161 ieee80211_sta_block_awake(priv->hw, sta, false);
1162 }
1163
1164 ieee80211_tx_status_irqsafe(priv->hw, skb);
1165}
1166
1167int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1168{
1169 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1170 struct iwl_queue *q = &txq->q;
1171 struct iwl_tx_info *tx_info;
1172 int nfreed = 0;
1173 struct ieee80211_hdr *hdr;
1174
1175 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1176 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1177 "is out of range [0-%d] %d %d.\n", txq_id,
1178 index, q->n_bd, q->write_ptr, q->read_ptr);
1179 return 0;
1180 }
1181
1182 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1183 q->read_ptr != index;
1184 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1185
1186 tx_info = &txq->txb[txq->q.read_ptr];
1187 iwl_tx_status(priv, tx_info->skb[0]);
1188
1189 hdr = (struct ieee80211_hdr *)tx_info->skb[0]->data;
1190 if (hdr && ieee80211_is_data_qos(hdr->frame_control))
1191 nfreed++;
1192 tx_info->skb[0] = NULL;
1193
1194 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1195 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1196
1197 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1198 }
1199 return nfreed;
1200}
1201EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1202
1203
1204/** 498/**
1205 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd 499 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1206 * 500 *
@@ -1292,329 +586,6 @@ void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1292} 586}
1293EXPORT_SYMBOL(iwl_tx_cmd_complete); 587EXPORT_SYMBOL(iwl_tx_cmd_complete);
1294 588
1295/*
1296 * Find first available (lowest unused) Tx Queue, mark it "active".
1297 * Called only when finding queue for aggregation.
1298 * Should never return anything < 7, because they should already
1299 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6)
1300 */
1301static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1302{
1303 int txq_id;
1304
1305 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1306 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1307 return txq_id;
1308 return -1;
1309}
1310
1311int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1312{
1313 int sta_id;
1314 int tx_fifo;
1315 int txq_id;
1316 int ret;
1317 unsigned long flags;
1318 struct iwl_tid_data *tid_data;
1319
1320 tx_fifo = get_fifo_from_tid(tid);
1321 if (unlikely(tx_fifo < 0))
1322 return tx_fifo;
1323
1324 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1325 __func__, ra, tid);
1326
1327 sta_id = iwl_find_station(priv, ra);
1328 if (sta_id == IWL_INVALID_STATION) {
1329 IWL_ERR(priv, "Start AGG on invalid station\n");
1330 return -ENXIO;
1331 }
1332 if (unlikely(tid >= MAX_TID_COUNT))
1333 return -EINVAL;
1334
1335 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1336 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1337 return -ENXIO;
1338 }
1339
1340 txq_id = iwl_txq_ctx_activate_free(priv);
1341 if (txq_id == -1) {
1342 IWL_ERR(priv, "No free aggregation queue available\n");
1343 return -ENXIO;
1344 }
1345
1346 spin_lock_irqsave(&priv->sta_lock, flags);
1347 tid_data = &priv->stations[sta_id].tid[tid];
1348 *ssn = SEQ_TO_SN(tid_data->seq_number);
1349 tid_data->agg.txq_id = txq_id;
1350 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id);
1351 spin_unlock_irqrestore(&priv->sta_lock, flags);
1352
1353 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1354 sta_id, tid, *ssn);
1355 if (ret)
1356 return ret;
1357
1358 if (tid_data->tfds_in_queue == 0) {
1359 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1360 tid_data->agg.state = IWL_AGG_ON;
1361 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1362 } else {
1363 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1364 tid_data->tfds_in_queue);
1365 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1366 }
1367 return ret;
1368}
1369EXPORT_SYMBOL(iwl_tx_agg_start);
1370
1371int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1372{
1373 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1374 struct iwl_tid_data *tid_data;
1375 int write_ptr, read_ptr;
1376 unsigned long flags;
1377
1378 if (!ra) {
1379 IWL_ERR(priv, "ra = NULL\n");
1380 return -EINVAL;
1381 }
1382
1383 tx_fifo_id = get_fifo_from_tid(tid);
1384 if (unlikely(tx_fifo_id < 0))
1385 return tx_fifo_id;
1386
1387 sta_id = iwl_find_station(priv, ra);
1388
1389 if (sta_id == IWL_INVALID_STATION) {
1390 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1391 return -ENXIO;
1392 }
1393
1394 if (priv->stations[sta_id].tid[tid].agg.state ==
1395 IWL_EMPTYING_HW_QUEUE_ADDBA) {
1396 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1397 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1398 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1399 return 0;
1400 }
1401
1402 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1403 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1404
1405 tid_data = &priv->stations[sta_id].tid[tid];
1406 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1407 txq_id = tid_data->agg.txq_id;
1408 write_ptr = priv->txq[txq_id].q.write_ptr;
1409 read_ptr = priv->txq[txq_id].q.read_ptr;
1410
1411 /* The queue is not empty */
1412 if (write_ptr != read_ptr) {
1413 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1414 priv->stations[sta_id].tid[tid].agg.state =
1415 IWL_EMPTYING_HW_QUEUE_DELBA;
1416 return 0;
1417 }
1418
1419 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1420 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1421
1422 spin_lock_irqsave(&priv->lock, flags);
1423 /*
1424 * the only reason this call can fail is queue number out of range,
1425 * which can happen if uCode is reloaded and all the station
1426 * information are lost. if it is outside the range, there is no need
1427 * to deactivate the uCode queue, just return "success" to allow
1428 * mac80211 to clean up it own data.
1429 */
1430 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1431 tx_fifo_id);
1432 spin_unlock_irqrestore(&priv->lock, flags);
1433
1434 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1435
1436 return 0;
1437}
1438EXPORT_SYMBOL(iwl_tx_agg_stop);
1439
1440int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1441{
1442 struct iwl_queue *q = &priv->txq[txq_id].q;
1443 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1444 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1445
1446 switch (priv->stations[sta_id].tid[tid].agg.state) {
1447 case IWL_EMPTYING_HW_QUEUE_DELBA:
1448 /* We are reclaiming the last packet of the */
1449 /* aggregated HW queue */
1450 if ((txq_id == tid_data->agg.txq_id) &&
1451 (q->read_ptr == q->write_ptr)) {
1452 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1453 int tx_fifo = get_fifo_from_tid(tid);
1454 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1455 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1456 ssn, tx_fifo);
1457 tid_data->agg.state = IWL_AGG_OFF;
1458 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1459 }
1460 break;
1461 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1462 /* We are reclaiming the last packet of the queue */
1463 if (tid_data->tfds_in_queue == 0) {
1464 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1465 tid_data->agg.state = IWL_AGG_ON;
1466 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1467 }
1468 break;
1469 }
1470 return 0;
1471}
1472EXPORT_SYMBOL(iwl_txq_check_empty);
1473
1474/**
1475 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1476 *
1477 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1478 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1479 */
1480static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1481 struct iwl_ht_agg *agg,
1482 struct iwl_compressed_ba_resp *ba_resp)
1483
1484{
1485 int i, sh, ack;
1486 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1487 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1488 u64 bitmap;
1489 int successes = 0;
1490 struct ieee80211_tx_info *info;
1491
1492 if (unlikely(!agg->wait_for_ba)) {
1493 IWL_ERR(priv, "Received BA when not expected\n");
1494 return -EINVAL;
1495 }
1496
1497 /* Mark that the expected block-ack response arrived */
1498 agg->wait_for_ba = 0;
1499 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1500
1501 /* Calculate shift to align block-ack bits with our Tx window bits */
1502 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1503 if (sh < 0) /* tbw something is wrong with indices */
1504 sh += 0x100;
1505
1506 /* don't use 64-bit values for now */
1507 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1508
1509 if (agg->frame_count > (64 - sh)) {
1510 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1511 return -1;
1512 }
1513
1514 /* check for success or failure according to the
1515 * transmitted bitmap and block-ack bitmap */
1516 bitmap &= agg->bitmap;
1517
1518 /* For each frame attempted in aggregation,
1519 * update driver's record of tx frame's status. */
1520 for (i = 0; i < agg->frame_count ; i++) {
1521 ack = bitmap & (1ULL << i);
1522 successes += !!ack;
1523 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1524 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1525 agg->start_idx + i);
1526 }
1527
1528 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1529 memset(&info->status, 0, sizeof(info->status));
1530 info->flags |= IEEE80211_TX_STAT_ACK;
1531 info->flags |= IEEE80211_TX_STAT_AMPDU;
1532 info->status.ampdu_ack_map = successes;
1533 info->status.ampdu_ack_len = agg->frame_count;
1534 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1535
1536 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1537
1538 return 0;
1539}
1540
1541/**
1542 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1543 *
1544 * Handles block-acknowledge notification from device, which reports success
1545 * of frames sent via aggregation.
1546 */
1547void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1548 struct iwl_rx_mem_buffer *rxb)
1549{
1550 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1551 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1552 struct iwl_tx_queue *txq = NULL;
1553 struct iwl_ht_agg *agg;
1554 int index;
1555 int sta_id;
1556 int tid;
1557
1558 /* "flow" corresponds to Tx queue */
1559 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1560
1561 /* "ssn" is start of block-ack Tx window, corresponds to index
1562 * (in Tx queue's circular buffer) of first TFD/frame in window */
1563 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1564
1565 if (scd_flow >= priv->hw_params.max_txq_num) {
1566 IWL_ERR(priv,
1567 "BUG_ON scd_flow is bigger than number of queues\n");
1568 return;
1569 }
1570
1571 txq = &priv->txq[scd_flow];
1572 sta_id = ba_resp->sta_id;
1573 tid = ba_resp->tid;
1574 agg = &priv->stations[sta_id].tid[tid].agg;
1575
1576 /* Find index just before block-ack window */
1577 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1578
1579 /* TODO: Need to get this copy more safely - now good for debug */
1580
1581 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1582 "sta_id = %d\n",
1583 agg->wait_for_ba,
1584 (u8 *) &ba_resp->sta_addr_lo32,
1585 ba_resp->sta_id);
1586 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1587 "%d, scd_ssn = %d\n",
1588 ba_resp->tid,
1589 ba_resp->seq_ctl,
1590 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1591 ba_resp->scd_flow,
1592 ba_resp->scd_ssn);
1593 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1594 agg->start_idx,
1595 (unsigned long long)agg->bitmap);
1596
1597 /* Update driver's record of ACK vs. not for each frame in window */
1598 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1599
1600 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1601 * block-ack window (we assume that they've been successfully
1602 * transmitted ... if not, it's too late anyway). */
1603 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1604 /* calculate mac80211 ampdu sw queue to wake */
1605 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1606 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
1607
1608 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1609 priv->mac80211_registered &&
1610 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1611 iwl_wake_queue(priv, txq->swq_id);
1612
1613 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1614 }
1615}
1616EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1617
1618#ifdef CONFIG_IWLWIFI_DEBUG 589#ifdef CONFIG_IWLWIFI_DEBUG
1619#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x 590#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1620 591
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 06:24:28 -0400