aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/wireless/iwlwifi/iwl-csr.h
diff options
context:
space:
mode:
authorEmmanuel Grumbach <emmanuel.grumbach@intel.com>2013-11-11 08:23:01 -0500
committerEmmanuel Grumbach <emmanuel.grumbach@intel.com>2013-11-25 16:00:19 -0500
commit6960a059b2c618f32fe549f13287b3d2278c09e9 (patch)
tree14f1f27ca98fe7c60072c58df141ed50af028363 /drivers/net/wireless/iwlwifi/iwl-csr.h
parent60765a47a433d54e4744c285ad127f182dcd80aa (diff)
iwlwifi: pcie: fix interrupt coalescing for 7260 / 3160
We changed the timeout for the interrupt coealescing for calibration, but that wasn't effective since we changed that value back before loading the firmware. Since calibrations are notification from firmware and not Rx packets, this doesn't change anyway - the firmware will fire an interrupt straight away regardless of the interrupt coalescing value. Also, a HW issue has been discovered in 7000 devices series. The work around is to disable the new interrupt coalescing timeout feature - do this by setting bit 31 in CSR_INT_COALESCING. This has been fixed in 7265 which means that we can't rely on the device family and must have a hint in the iwl_cfg structure. Cc: stable@vger.kernel.org [3.10+] Fixes: 99cd47142399 ("iwlwifi: add 7000 series device configuration") Reviewed-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-csr.h')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-csr.h5
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-csr.h b/drivers/net/wireless/iwlwifi/iwl-csr.h
index 54a4fdc631b7..da4eca8b3007 100644
--- a/drivers/net/wireless/iwlwifi/iwl-csr.h
+++ b/drivers/net/wireless/iwlwifi/iwl-csr.h
@@ -495,14 +495,11 @@ enum secure_load_status_reg {
495 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit 495 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
496 * 496 *
497 * default interrupt coalescing timer is 64 x 32 = 2048 usecs 497 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
498 * default interrupt coalescing calibration timer is 16 x 32 = 512 usecs
499 */ 498 */
500#define IWL_HOST_INT_TIMEOUT_MAX (0xFF) 499#define IWL_HOST_INT_TIMEOUT_MAX (0xFF)
501#define IWL_HOST_INT_TIMEOUT_DEF (0x40) 500#define IWL_HOST_INT_TIMEOUT_DEF (0x40)
502#define IWL_HOST_INT_TIMEOUT_MIN (0x0) 501#define IWL_HOST_INT_TIMEOUT_MIN (0x0)
503#define IWL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF) 502#define IWL_HOST_INT_OPER_MODE BIT(31)
504#define IWL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
505#define IWL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
506 503
507/***************************************************************************** 504/*****************************************************************************
508 * 7000/3000 series SHR DTS addresses * 505 * 7000/3000 series SHR DTS addresses *