iwlagn: all function iwl-io.c receive iwl_bus

Which means that iwl-io.c doesn't need to include iwl-dev.h any more.

Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 14 insertions, 13 deletions

diff --git a/drivers/net/wireless/iwlwifi/iwl-core.c b/drivers/net/wireless/iwlwifi/iwl-core.c
index 048c8e2578f5..411edc8f3f9d 100644
--- a/drivers/net/wireless/iwlwifi/iwl-core.c
+++ b/drivers/net/wireless/iwlwifi/iwl-core.c
@@ -907,9 +907,10 @@ static int iwl_apm_stop_master(struct iwl_priv *priv)
         int ret = 0;
 
         /* stop device's busmaster DMA activity */
-        iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
+        iwl_set_bit(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 
-        ret = iwl_poll_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_MASTER_DISABLED,
+        ret = iwl_poll_bit(bus(priv), CSR_RESET,
+                        CSR_RESET_REG_FLAG_MASTER_DISABLED,
                         CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
         if (ret)
                 IWL_WARN(priv, "Master Disable Timed Out, 100 usec\n");
@@ -929,7 +930,7 @@ void iwl_apm_stop(struct iwl_priv *priv)
         iwl_apm_stop_master(priv);
 
         /* Reset the entire device */
-        iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
+        iwl_set_bit(bus(priv), CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 
         udelay(10);
 
@@ -937,7 +938,7 @@ void iwl_apm_stop(struct iwl_priv *priv)
          * Clear "initialization complete" bit to move adapter from
          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
          */
-        iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
+        iwl_clear_bit(bus(priv), CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 }
 
 
@@ -957,45 +958,45 @@ int iwl_apm_init(struct iwl_priv *priv)
          */
 
         /* Disable L0S exit timer (platform NMI Work/Around) */
-        iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
+        iwl_set_bit(bus(priv), CSR_GIO_CHICKEN_BITS,
                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 
         /*
          * Disable L0s without affecting L1;
          *  don't wait for ICH L0s (ICH bug W/A)
          */
-        iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
+        iwl_set_bit(bus(priv), CSR_GIO_CHICKEN_BITS,
                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 
         /* Set FH wait threshold to maximum (HW error during stress W/A) */
-        iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
+        iwl_set_bit(bus(priv), CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 
         /*
          * Enable HAP INTA (interrupt from management bus) to
          * wake device's PCI Express link L1a -> L0s
          */
-        iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
+        iwl_set_bit(bus(priv), CSR_HW_IF_CONFIG_REG,
                                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 
         bus_apm_config(priv->bus);
 
         /* Configure analog phase-lock-loop before activating to D0A */
         if (priv->cfg->base_params->pll_cfg_val)
-                iwl_set_bit(priv, CSR_ANA_PLL_CFG,
+                iwl_set_bit(bus(priv), CSR_ANA_PLL_CFG,
                             priv->cfg->base_params->pll_cfg_val);
 
         /*
          * Set "initialization complete" bit to move adapter from
          * D0U* --> D0A* (powered-up active) state.
          */
-        iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
+        iwl_set_bit(bus(priv), CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 
         /*
          * Wait for clock stabilization; once stabilized, access to
          * device-internal resources is supported, e.g. iwl_write_prph()
          * and accesses to uCode SRAM.
          */
-        ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
+        ret = iwl_poll_bit(bus(priv), CSR_GP_CNTRL,
                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
         if (ret < 0) {
@@ -1010,11 +1011,11 @@ int iwl_apm_init(struct iwl_priv *priv)
          * do not disable clocks.  This preserves any hardware bits already
          * set by default in "CLK_CTRL_REG" after reset.
          */
-        iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
+        iwl_write_prph(bus(priv), APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
         udelay(20);
 
         /* Disable L1-Active */
-        iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
+        iwl_set_bits_prph(bus(priv), APMG_PCIDEV_STT_REG,
                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 
         set_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status);