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authorBen Cahill <ben.m.cahill@intel.com>2007-11-28 22:10:07 -0500
committerDavid S. Miller <davem@davemloft.net>2008-01-28 18:05:31 -0500
commite3851447664113bccf9b23af0308e266872a735c (patch)
treee6e5b41c7981c99224f980bf86c04f029bc33032 /drivers/net/wireless/iwlwifi/iwl-4965-hw.h
parent5d5456fe50cb07347dd350fc045dc98677dbc58f (diff)
iwlwifi: document 4965 Tx scheduler
Document 4965 Tx scheduler Signed-off-by: Ben Cahill <ben.m.cahill@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'drivers/net/wireless/iwlwifi/iwl-4965-hw.h')
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965-hw.h268
1 files changed, 260 insertions, 8 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
index b548b7979b42..d5d418e61923 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
+++ b/drivers/net/wireless/iwlwifi/iwl-4965-hw.h
@@ -1554,33 +1554,285 @@ enum {
1554 IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl)) 1554 IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
1555 1555
1556 1556
1557/********************* START TX SCHEDULER *************************************/
1558
1559/**
1560 * 4965 Tx Scheduler
1561 *
1562 * The Tx Scheduler selects the next frame to be transmitted, chosing TFDs
1563 * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in
1564 * host DRAM. It steers each frame's Tx command (which contains the frame
1565 * data) into one of up to 7 prioritized Tx DMA FIFO channels within the
1566 * device. A queue maps to only one (selectable by driver) Tx DMA channel,
1567 * but one DMA channel may take input from several queues.
1568 *
1569 * Tx DMA channels have dedicated purposes. For 4965, they are used as follows:
1570 *
1571 * 0 -- EDCA BK (background) frames, lowest priority
1572 * 1 -- EDCA BE (best effort) frames, normal priority
1573 * 2 -- EDCA VI (video) frames, higher priority
1574 * 3 -- EDCA VO (voice) and management frames, highest priority
1575 * 4 -- Commands (e.g. RXON, etc.)
1576 * 5 -- HCCA short frames
1577 * 6 -- HCCA long frames
1578 * 7 -- not used by driver (device-internal only)
1579 *
1580 * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6.
1581 * In addition, driver can map queues 7-15 to Tx DMA/FIFO channels 0-3 to
1582 * support 11n aggregation via EDCA DMA channels.
1583 *
1584 * The driver sets up each queue to work in one of two modes:
1585 *
1586 * 1) Scheduler-Ack, in which the scheduler automatically supports a
1587 * block-ack (BA) window of up to 64 TFDs. In this mode, each queue
1588 * contains TFDs for a unique combination of Recipient Address (RA)
1589 * and Traffic Identifier (TID), that is, traffic of a given
1590 * Quality-Of-Service (QOS) priority, destined for a single station.
1591 *
1592 * In scheduler-ack mode, the scheduler keeps track of the Tx status of
1593 * each frame within the BA window, including whether it's been transmitted,
1594 * and whether it's been acknowledged by the receiving station. The device
1595 * automatically processes block-acks received from the receiving STA,
1596 * and reschedules un-acked frames to be retransmitted (successful
1597 * Tx completion may end up being out-of-order).
1598 *
1599 * The driver must maintain the queue's Byte Count table in host DRAM
1600 * (struct iwl4965_sched_queue_byte_cnt_tbl) for this mode.
1601 * This mode does not support fragmentation.
1602 *
1603 * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order.
1604 * The device may automatically retry Tx, but will retry only one frame
1605 * at a time, until receiving ACK from receiving station, or reaching
1606 * retry limit and giving up.
1607 *
1608 * The command queue (#4) must use this mode!
1609 * This mode does not require use of the Byte Count table in host DRAM.
1610 *
1611 * Driver controls scheduler operation via 3 means:
1612 * 1) Scheduler registers
1613 * 2) Shared scheduler data base in internal 4956 SRAM
1614 * 3) Shared data in host DRAM
1615 *
1616 * Initialization:
1617 *
1618 * When loading, driver should allocate memory for:
1619 * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs.
1620 * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory
1621 * (1024 bytes for each queue).
1622 *
1623 * After receiving "Alive" response from uCode, driver must initialize
1624 * the scheduler (especially for queue #4, the command queue, otherwise
1625 * the driver can't issue commands!):
1626 */
1627
1628/**
1629 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1630 * can keep track of at one time when creating block-ack chains of frames.
1631 * Note that "64" matches the number of ack bits in a block-ack packet.
1632 * Driver should use SCD_WIN_SIZE and SCD_FRAME_LIMIT values to initialize
1633 * SCD_CONTEXT_QUEUE_OFFSET(x) values.
1634 */
1557#define SCD_WIN_SIZE 64 1635#define SCD_WIN_SIZE 64
1558#define SCD_FRAME_LIMIT 64 1636#define SCD_FRAME_LIMIT 64
1559 1637
1560/* SRAM structures */ 1638/* SCD registers are internal, must be accessed via HBUS_TARG_PRPH regs */
1561#define SCD_CONTEXT_DATA_OFFSET 0x380 1639#define SCD_START_OFFSET 0xa02c00
1562#define SCD_TX_STTS_BITMAP_OFFSET 0x400 1640
1563#define SCD_TRANSLATE_TBL_OFFSET 0x500 1641/*
1564#define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8)) 1642 * 4965 tells driver SRAM address for internal scheduler structs via this reg.
1565#define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \ 1643 * Value is valid only after "Alive" response from uCode.
1566 ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc) 1644 */
1645#define SCD_SRAM_BASE_ADDR (SCD_START_OFFSET + 0x0)
1567 1646
1647/*
1648 * Driver may need to update queue-empty bits after changing queue's
1649 * write and read pointers (indexes) during (re-)initialization (i.e. when
1650 * scheduler is not tracking what's happening).
1651 * Bit fields:
1652 * 31-16: Write mask -- 1: update empty bit, 0: don't change empty bit
1653 * 15-00: Empty state, one for each queue -- 1: empty, 0: non-empty
1654 * NOTE: This register is not used by Linux driver.
1655 */
1656#define SCD_EMPTY_BITS (SCD_START_OFFSET + 0x4)
1657
1658/*
1659 * Physical base address of array of byte count (BC) circular buffers (CBs).
1660 * Each Tx queue has a BC CB in host DRAM to support Scheduler-ACK mode.
1661 * This register points to BC CB for queue 0, must be on 1024-byte boundary.
1662 * Others are spaced by 1024 bytes.
1663 * Each BC CB is 2 bytes * (256 + 64) = 740 bytes, followed by 384 bytes pad.
1664 * (Index into a queue's BC CB) = (index into queue's TFD CB) = (SSN & 0xff).
1665 * Bit fields:
1666 * 25-00: Byte Count CB physical address [35:10], must be 1024-byte aligned.
1667 */
1668#define SCD_DRAM_BASE_ADDR (SCD_START_OFFSET + 0x10)
1669
1670/*
1671 * Enables any/all Tx DMA/FIFO channels.
1672 * Scheduler generates requests for only the active channels.
1673 * Set this to 0xff to enable all 8 channels (normal usage).
1674 * Bit fields:
1675 * 7- 0: Enable (1), disable (0), one bit for each channel 0-7
1676 */
1677#define SCD_TXFACT (SCD_START_OFFSET + 0x1c)
1678
1679/* Mask to enable contiguous Tx DMA/FIFO channels between "lo" and "hi". */
1568#define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \ 1680#define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
1569 ((1<<(hi))|((1<<(hi))-(1<<(lo)))) 1681 ((1<<(hi))|((1<<(hi))-(1<<(lo))))
1570 1682
1683/*
1684 * Queue (x) Write Pointers (indexes, really!), one for each Tx queue.
1685 * Initialized and updated by driver as new TFDs are added to queue.
1686 * NOTE: If using Block Ack, index must correspond to frame's
1687 * Start Sequence Number; index = (SSN & 0xff)
1688 * NOTE: Alternative to HBUS_TARG_WRPTR, which is what Linux driver uses?
1689 */
1690#define SCD_QUEUE_WRPTR(x) (SCD_START_OFFSET + 0x24 + (x) * 4)
1691
1692/*
1693 * Queue (x) Read Pointers (indexes, really!), one for each Tx queue.
1694 * For FIFO mode, index indicates next frame to transmit.
1695 * For Scheduler-ACK mode, index indicates first frame in Tx window.
1696 * Initialized by driver, updated by scheduler.
1697 */
1698#define SCD_QUEUE_RDPTR(x) (SCD_START_OFFSET + 0x64 + (x) * 4)
1699
1700/*
1701 * Select which queues work in chain mode (1) vs. not (0).
1702 * Use chain mode to build chains of aggregated frames.
1703 * Bit fields:
1704 * 31-16: Reserved
1705 * 15-00: Mode, one bit for each queue -- 1: Chain mode, 0: one-at-a-time
1706 * NOTE: If driver sets up queue for chain mode, it should be also set up
1707 * Scheduler-ACK mode as well, via SCD_QUEUE_STATUS_BITS(x).
1708 */
1709#define SCD_QUEUECHAIN_SEL (SCD_START_OFFSET + 0xd0)
1710
1711/*
1712 * Select which queues interrupt driver when scheduler increments
1713 * a queue's read pointer (index).
1714 * Bit fields:
1715 * 31-16: Reserved
1716 * 15-00: Interrupt enable, one bit for each queue -- 1: enabled, 0: disabled
1717 * NOTE: This functionality is apparently a no-op; driver relies on interrupts
1718 * from Rx queue to read Tx command responses and update Tx queues.
1719 */
1720#define SCD_INTERRUPT_MASK (SCD_START_OFFSET + 0xe4)
1721
1722/*
1723 * Queue search status registers. One for each queue.
1724 * Sets up queue mode and assigns queue to Tx DMA channel.
1725 * Bit fields:
1726 * 19-10: Write mask/enable bits for bits 0-9
1727 * 9: Driver should init to "0"
1728 * 8: Scheduler-ACK mode (1), non-Scheduler-ACK (i.e. FIFO) mode (0).
1729 * Driver should init to "1" for aggregation mode, or "0" otherwise.
1730 * 7-6: Driver should init to "0"
1731 * 5: Window Size Left; indicates whether scheduler can request
1732 * another TFD, based on window size, etc. Driver should init
1733 * this bit to "1" for aggregation mode, or "0" for non-agg.
1734 * 4-1: Tx FIFO to use (range 0-7).
1735 * 0: Queue is active (1), not active (0).
1736 * Other bits should be written as "0"
1737 *
1738 * NOTE: If enabling Scheduler-ACK mode, chain mode should also be enabled
1739 * via SCD_QUEUECHAIN_SEL.
1740 */
1741#define SCD_QUEUE_STATUS_BITS(x) (SCD_START_OFFSET + 0x104 + (x) * 4)
1742
1743/* Bit field positions */
1571#define SCD_QUEUE_STTS_REG_POS_ACTIVE (0) 1744#define SCD_QUEUE_STTS_REG_POS_ACTIVE (0)
1572#define SCD_QUEUE_STTS_REG_POS_TXF (1) 1745#define SCD_QUEUE_STTS_REG_POS_TXF (1)
1573#define SCD_QUEUE_STTS_REG_POS_WSL (5) 1746#define SCD_QUEUE_STTS_REG_POS_WSL (5)
1574#define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8) 1747#define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)
1748
1749/* Write masks */
1575#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10) 1750#define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)
1576#define SCD_QUEUE_STTS_REG_MSK (0x0007FC00) 1751#define SCD_QUEUE_STTS_REG_MSK (0x0007FC00)
1577 1752
1753/**
1754 * 4965 internal SRAM structures for scheduler, shared with driver ...
1755 *
1756 * Driver should clear and initialize the following areas after receiving
1757 * "Alive" response from 4965 uCode, i.e. after initial
1758 * uCode load, or after a uCode load done for error recovery:
1759 *
1760 * SCD_CONTEXT_DATA_OFFSET (size 128 bytes)
1761 * SCD_TX_STTS_BITMAP_OFFSET (size 256 bytes)
1762 * SCD_TRANSLATE_TBL_OFFSET (size 32 bytes)
1763 *
1764 * Driver accesses SRAM via HBUS_TARG_MEM_* registers.
1765 * Driver reads base address of this scheduler area from SCD_SRAM_BASE_ADDR.
1766 * All OFFSET values must be added to this base address.
1767 */
1768
1769/*
1770 * Queue context. One 8-byte entry for each of 16 queues.
1771 *
1772 * Driver should clear this entire area (size 0x80) to 0 after receiving
1773 * "Alive" notification from uCode. Additionally, driver should init
1774 * each queue's entry as follows:
1775 *
1776 * LS Dword bit fields:
1777 * 0-06: Max Tx window size for Scheduler-ACK. Driver should init to 64.
1778 *
1779 * MS Dword bit fields:
1780 * 16-22: Frame limit. Driver should init to 10 (0xa).
1781 *
1782 * Driver should init all other bits to 0.
1783 *
1784 * Init must be done after driver receives "Alive" response from 4965 uCode,
1785 * and when setting up queue for aggregation.
1786 */
1787#define SCD_CONTEXT_DATA_OFFSET 0x380
1788#define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
1789
1578#define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0) 1790#define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)
1579#define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F) 1791#define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)
1580
1581#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16) 1792#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1582#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000) 1793#define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1583 1794
1795/*
1796 * Tx Status Bitmap
1797 *
1798 * Driver should clear this entire area (size 0x100) to 0 after receiving
1799 * "Alive" notification from uCode. Area is used only by device itself;
1800 * no other support (besides clearing) is required from driver.
1801 */
1802#define SCD_TX_STTS_BITMAP_OFFSET 0x400
1803
1804/*
1805 * RAxTID to queue translation mapping.
1806 *
1807 * When queue is in Scheduler-ACK mode, frames placed in a that queue must be
1808 * for only one combination of receiver address (RA) and traffic ID (TID), i.e.
1809 * one QOS priority level destined for one station (for this wireless link,
1810 * not final destination). The SCD_TRANSLATE_TABLE area provides 16 16-bit
1811 * mappings, one for each of the 16 queues. If queue is not in Scheduler-ACK
1812 * mode, the device ignores the mapping value.
1813 *
1814 * Bit fields, for each 16-bit map:
1815 * 15-9: Reserved, set to 0
1816 * 8-4: Index into device's station table for recipient station
1817 * 3-0: Traffic ID (tid), range 0-15
1818 *
1819 * Driver should clear this entire area (size 32 bytes) to 0 after receiving
1820 * "Alive" notification from uCode. To update a 16-bit map value, driver
1821 * must read a dword-aligned value from device SRAM, replace the 16-bit map
1822 * value of interest, and write the dword value back into device SRAM.
1823 */
1824#define SCD_TRANSLATE_TBL_OFFSET 0x500
1825
1826/* Find translation table dword to read/write for given queue */
1827#define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
1828 ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
1829
1830#define SCD_TXFIFO_POS_TID (0)
1831#define SCD_TXFIFO_POS_RA (4)
1832#define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1833
1834/*********************** END TX SCHEDULER *************************************/
1835
1584static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags) 1836static inline u8 iwl4965_hw_get_rate(__le32 rate_n_flags)
1585{ 1837{
1586 return le32_to_cpu(rate_n_flags) & 0xFF; 1838 return le32_to_cpu(rate_n_flags) & 0xFF;