iwlwifi: 3945 extract flow handler definitions into iwl-3945-fh.h

This patch moves 3945 definitions into iwl-3945-fh.h
It renames FH_ to FH39 to help inclusion of 3945 into iwlcore
framework

Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>

1 files changed, 42 insertions, 41 deletions

diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index 45cfa1cf194a..f4fee0a91b66 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -39,6 +39,7 @@
 #include <net/mac80211.h>
 
 #include "iwl-3945-core.h"
+#include "iwl-3945-fh.h"
 #include "iwl-3945.h"
 #include "iwl-helpers.h"
 #include "iwl-3945-rs.h"
@@ -984,23 +985,23 @@ static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *r
                 return rc;
         }
 
-        iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
-        iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
+        iwl3945_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
+        iwl3945_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0),
                              priv->hw_setting.shared_phys +
                              offsetof(struct iwl3945_shared, rx_read_ptr[0]));
-        iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
-        iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
-                ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
-                ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
-                ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
-                ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
-                (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
-                ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
-                (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
-                ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
+        iwl3945_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
+        iwl3945_write_direct32(priv, FH39_RCSR_CONFIG(0),
+                FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
+                FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
+                FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
+                FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
+                (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
+                FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
+                (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
+                FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 
         /* fake read to flush all prev I/O */
-        iwl3945_read_direct32(priv, FH_RSSR_CTRL);
+        iwl3945_read_direct32(priv, FH39_RSSR_CTRL);
 
         iwl3945_release_nic_access(priv);
         spin_unlock_irqrestore(&priv->lock, flags);
@@ -1034,17 +1035,17 @@ static int iwl3945_tx_reset(struct iwl3945_priv *priv)
         iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
         iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 
-        iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
+        iwl3945_write_direct32(priv, FH39_TSSR_CBB_BASE,
                              priv->hw_setting.shared_phys);
 
-        iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
-                ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
-                ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
-                ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
-                ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
-                ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
-                ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
-                ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
+        iwl3945_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
+                FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
+                FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
+                FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
+                FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
+                FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
+                FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
+                FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 
         iwl3945_release_nic_access(priv);
         spin_unlock_irqrestore(&priv->lock, flags);
@@ -1210,7 +1211,7 @@ int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
                 spin_unlock_irqrestore(&priv->lock, flags);
                 return rc;
         }
-        iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
+        iwl3945_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
         iwl3945_release_nic_access(priv);
 
         spin_unlock_irqrestore(&priv->lock, flags);
@@ -1240,7 +1241,7 @@ void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
 
 void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
 {
-        int queue;
+        int txq_id;
         unsigned long flags;
 
         spin_lock_irqsave(&priv->lock, flags);
@@ -1254,10 +1255,10 @@ void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
         iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
 
         /* reset TFD queues */
-        for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
-                iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
-                iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
-                                ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
+        for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
+                iwl3945_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
+                iwl3945_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
+                                FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
                                 1000);
         }
 
@@ -2307,9 +2308,9 @@ int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
                 return rc;
         }
 
-        iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
-        rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS,
-                        FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
+        iwl3945_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
+        rc = iwl3945_poll_direct_bit(priv, FH39_RSSR_STATUS,
+                        FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
         if (rc < 0)
                 IWL_ERROR("Can't stop Rx DMA.\n");
 
@@ -2335,19 +2336,19 @@ int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue
                 spin_unlock_irqrestore(&priv->lock, flags);
                 return rc;
         }
-        iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
-        iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
-
-        iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
-                ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
-                ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
-                ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
-                ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
-                ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
+        iwl3945_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
+        iwl3945_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
+
+        iwl3945_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
+                FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
+                FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
+                FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
+                FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
+                FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
         iwl3945_release_nic_access(priv);
 
         /* fake read to flush all prev. writes */
-        iwl3945_read32(priv, FH_TSSR_CBB_BASE);
+        iwl3945_read32(priv, FH39_TSSR_CBB_BASE);
         spin_unlock_irqrestore(&priv->lock, flags);
 
         return 0;